-
Notifications
You must be signed in to change notification settings - Fork 111
/
Copy pathRELEASE_NOTES.TXT
1606 lines (1496 loc) · 99.7 KB
/
RELEASE_NOTES.TXT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
============= RapidWright 2024.2.0-beta released on 2024-12-04 ================
Notes:
- Remove reliance on gap routing test (#1117)
- [ModuleInst] Fix placement behavior when requesting no overlaps (#1108)
- [RWRoute] Clock router for Versal architecture (#1102)
- Various preprocessing fixes for Versal routing (#1115)
- [CUFR] CUFR and PartialCUFR to default to --hus (#1111)
- [TestNet] Improve testSetPinsMultiSrcStatic to track many sources (#1082)
- Changes to support new array-based cell pin mappings (#1101)
- Update tests to reflect bug fixes and minor behavior changes (#1110)
- [RWRoute] Yet more cleanup (#1107)
- [RWRoute] Preserve nodes of Laguna sinks (#1104)
- [GlobalSignalRouting] routeStaticNets() to take a list of static pins (#1105)
- [RWRoute] Fix typo -- not an exclusive sink (#1106)
- [RWRoute] Versal optimizations (#1093)
- [RWRoute] RouteNode.setType() to accept any locals (#1103)
- [RWRoute] Further divide LOCAL nodes into EAST/WEST for UltraScale(+) (#1098)
- [Utils] isClocking() to include TileTypeEnum.CMT_L (#1100)
- TileGroup and DeviceBrowser Improvements (#1094)
- [RWRoute] Divide nodes into LOCAL and NON_LOCAL (#1095)
- Update actions and do not limit to 5G RAM (#1092)
- [HandPlacer] Cleanup snapping code in hand placer (#1091)
- [LUTTools] Add zero padding to LUT INIT strings (#1090)
- [NetTools] Add getNodeTrees() method and NodeTree class (#1089)
- [YosysTools] Add synthXilinx() wrapper for Yosys (#1086)
- [EDIFWriteLegalNameCache] busCollisionRenames to be a ConcurrentHashMap (#1088)
- Add ReportRouteStatus utility (#1087)
- [RWRoute] Signal router for Versal architecture (#1077)
- [FileTools] Add runCommand(String[] ...) & getExecutablePath(String) (#1085)
- [RouterHelper] findPathBetweenNodes() allow clocking if src/sink is so (#1083)
- [RouterHelper] projectOutputPinToINTNode() to breadth-first-search (#1081)
- [RouterHelper] projectInputPinToINTNode() to return solitary node (#1080)
- [RouterHelper] findPathBetweenNodes() to ignore clocking tiles (#1079)
- [RouterHelper] invertPossibleGndPinsToVccPins() to support Versal LUTs (#1078)
- [DesignTools] Fix createCeSrRstPinsToVCC() for US BRAMs (#1075)
- [DesignTools] Add LDCE/LDPE to types that need VCC (#1076)
- [NetTools] Add NetTools.isGlobalClock() (#1057)
- Static router for Versal architecture (#1073)
- [EDIFNetlist] getPhysicalPins() to call getPhysical{Gnd,Vcc}Pins() (#1074)
- Fix Null SLR References in Tiles in xcvp1902
- Add Implements Serializable to All RapidWright Classes
- [SiteInst] Improve memory usage of site routing using array instead of maps
- [Cell] Changes pin mappings from a map to an array to improve memory usage
- [BEL] Deprecate isSRIMR() in favour of more general isIMR()
- [Tile] Add getMaxUniqueAddress()
- [Net] Add support for multiple output sources
API Additions:
- com.xilinx.rapidwright.design.Cell "public Pair<BELPin, String> getFirstPhysicalPinMapping()"
- com.xilinx.rapidwright.design.Cell "public int getUsedPhysicalPinsCount()"
- com.xilinx.rapidwright.design.Cell "public Set<String> getUsedPhysicalPins()"
- com.xilinx.rapidwright.design.Cell "public String[] getPhysicalPinMappings()"
- com.xilinx.rapidwright.design.Cell "public boolean usesPhysicalPin(String physicalPinName)"
- com.xilinx.rapidwright.design.Design "public boolean placeCell(Cell c, Site site, BEL bel, String[] physPinMappings)"
- com.xilinx.rapidwright.design.Net "public List<SitePinInst> getAlternateSources()"
- com.xilinx.rapidwright.device.BEL "public boolean isIMR()"
- com.xilinx.rapidwright.device.Tile "public int getMaxUniqueAddress()"
============= RapidWright 2024.1.3-beta released on 2024-10-02 ================
Notes:
- [RWRoute] Further cleanup (#1070)
- [PhysNetlistReader] Call SiteInst.setDesign() even for STATIC_SOURCEs (#1071)
- [GlobalSignalRouting] Fix VCC routing for UltraScale (#1068)
- [RWRoute] Cleanup static router and RouterHelper (#1059)
- [PartialRouter] Disable ripup in global/static routing (#1067)
- [TestDesign] Add test for net ordering of >= 2022.1 DCPs (#1054)
- [TestBEL] Add testDIFFsAreNotFF() (#1062)
- Test for Design.retargetPart() (#1061)
- [EDIF] Fixes rare bus renaming collision (#1065)
- [RWRoute] Always clear prev pointer of unpreserved RouteNode-s (#1056)
- [LaunchTestsOnLsf] Invoke java with assertions enabled (#1066)
- [LaunchTestsOnLsf] Invoke java with assertions enabled (#1063)
- Fix testRouteStaticNet() to avoid site pins, and fix golden values (#1064)
- [GitHub Actions] Migrate to upload-artifact@v4 (#1058)
- Add recursive partitioning ternary tree (RPTT) (#1055)
- Add support for vu19p tiles in bitstream
- [Design] createModuleInst() to not create duplicate STATIC_SOURCE-s
- Removes all instances of enum.hashCode()
- [Node] equals() to use instanceof for subclass-awareness
- Retarget & relocate an existing design to a new part and location
- Fixes issue related to non-deterministic Net order upon multi-threaded DCP load
- Fix BEL.isFF() based on BELTypes
- Fix missing Design.getSeries()
API Additions:
- com.xilinx.rapidwright.design.Design "public boolean retargetPart(Part targetPart, int tileXOffset, int tileYOffset)"
============= RapidWright 2024.1.2-beta released on 2024-09-04 ================
Notes:
- Creating a standalone entry point to relocate DCPs (#1047)
- [Interchange] Reorders tile types and tiles to follow their Vivado index (#1039)
- [DesignTools] Conform to Vivado *RST* pin inversion site routing configuration (#1053)
- Fix for design merging, including designs with encrypted cells (#1035)
- Filters out comments in XDC while parsing clk constraints (#1037)
- Assign an empty list when path finding for direct connections fails (#1052)
- Make LogicalNetlistToEdif not expand macros by default (#1051)
- [Interchange] Fixes to support Versal designs via Interchange (#1040)
- EDIF cleanup preventing singleton cells/libraries from attaching to user designs (#1050)
- [RWRoute] Refactoring/cleanup/preparation for multi-threading (#1046)
- Add Hybrid Updating Strategy (HUS) (#1043)
- [TestSiteInst] Add test for unrouting through FF routethru cells (#1041)
- [TestPIP] Test PIP constructor for reversed wires (#1045)
- [RWRoute] Preserve primary source nodes on connections (#1038)
- Small Interchange/PhysNetlistReader/VivadoTools improvements (#1042)
- [UnisimManager] Use EDIFLibraryBuiltin for primitive/macro libs
- Avoids NPE when site routing BRAMs
- Fix isCarry() for Versal devices
- Resolves PIP constructor issue for reversed PIPs
- [SiteInst] unrouteIntraSiteNet() to handle FF routethru cells
API Additions:
- com.xilinx.rapidwright.design.Design "public Series getSeries()"
- com.xilinx.rapidwright.design.SiteInst "public SitePIP getUsedSitePIP(BEL bel)"
============= RapidWright 2024.1.1-beta released on 2024-07-17 ================
Notes:
- [VivadoTools] Source *_load.tcl from same dir as DCP (#1032)
- Test that PIP.isReversed() is correct (#1024)
- Add TestSite.testGetIntTile() (#1022)
- [EDIFTools] writeTclLoadScriptForPartialEncryptedDesigns abspath (#1029)
- Adding HDIOB types (#1028)
- Test for site routing from raw placed design (#1000)
- [RWRoute] Do not NPE on encrypted netlists (#1025)
- [RWRoute] Do not assume Y = 0 has Laguna tiles, since it could be HBM device (#1026)
- Adds UNKWN state for LSFJobs (#1027)
- Adding legacy support for u280 (#1021)
- Remove flawed loop intended to for encrypted cell removal (#1023)
- [DesignTools.makeBlackBox()] Fixes an issue of removing CARRY blocks fed by routethrus (#1009)
- Fix null netlist pointer on expanded macro children (#1008)
- [Interchange] Device Resources Verifier Fixes (#1014)
- Fix ConcurrentModificationError (#1015)
- [EDIFTools] Adding method to create a flat netlist from a hierarchical one (#1006)
- Adding HBM ComponentTypes (#1007)
- Test for wire/node mismatch reported in #983 (#1005)
- 3.6% memory reduction usage for large placed designs (de-duplication of cell pin strings)
- Add missing pin entry for BUFG_GT when tracking INT tile connections
- Fixes rare DCP write issue with stubbed bi-directional PIPs (more common on DFX designs)
- Fix for reversed flag on PIPs
- Addresses issue with Net.getBufferDelay() by checking for null wire names
- Fixes two site routing issues
API Additions:
- (None)
API Removals:
- (None)
============= RapidWright 2024.1.0-beta released on 2024-06-11 ================
Notes:
- Support for Vivado 2024.1 DCPs and devices
- Support to write DCPs with physDB components with Params.RW_WRITE_DCP_2024_1
- 2024.1 DCP Write Test (#997)
- Updates to support 2024.1 DCP writing (#995)
- Add FileTools.getAutoBufferedInputStream() with zstd auto-detect (#990)
- BlockPlacer2: Fix off by one error in selecting module instance to move (#987)
- Fix PolynomialGenerator and TestDCPSave tests (#982)
- Use exit code 1 if any LSF job failed (#981)
- Fixes issues around Node->Wire equivalence (#407)
API Additions:
- com.xilinx.rapidwright.device.Device "public boolean hasModularSLRs()"
- com.xilinx.rapidwright.device.Wire "public boolean isConnected()"
- com.xilinx.rapidwright.device.Wire "public boolean isTiedToVCC()"
- com.xilinx.rapidwright.device.Wire "public boolean isTiedToGND()"
- com.xilinx.rapidwright.device.Wire "public boolean isTied()"
API Removals:
- com.xilinx.rapidwright.device.Node "public int getWire()"
- com.xilinx.rapidwright.util.RapidWright "*"
============= RapidWright 2023.2.2-beta released on 2024-04-03 ================
Notes:
- Use new Cell.{LOCKED,PORT_TYPE,isPortCell()} (#977)
- Remove some pre-2023.2.2 workarounds (#978)
- [RWRoute] Fix logical driver flag setting for DCP write (#979)
- Add explicit use case for a Jython script in --help (#980)
- [VivadoTools] Add placeDesign() and getWorstSetupSlack() (#975)
- [RWRoute] Consider all nets in timing-driven routing (#976)
- [DCP] Test Design.writeCheckpoint() when using existing EDIF (#965)
- Work around for multi-inverter BEL in DSP58 (#969)
- [DesignTools.makeBlackBox()] Fix for #967 (#970)
- [RWRoute,PhysNetlistReader] Set logical driver on PIPs (#973)
- [SLRCrosserGenerator] Adds North/South parameterizable bus widths; some error checking (#972)
- [EDIFTokenizer] Account for byte size of UTF-8 characters correctly (#962)
- [VivadoTools] writeBitstream to not delete DCP parent dir (+more) (#955)
- [RWRoute] Preserve [A-H]_O node when [A-H]MUX used as static src (#954)
- [GlobalSignalRouter] No intra site routing for new static source pins (#953)
- [EDIFPropertyValue] Fix getBooleanValue() NPE (#952)
- [PhysNetlistReader] Fix checkConstantRoutingAndNetNaming() (#951)
- [RWRoute] When removing unused source SPI restore intra-site routing (#949)
- [RWRoute] Tidy up createNetWrapperAndConnections() (#950)
- Fix EDIFPropertyValue.getBooleanValue() (#948)
- [RWRoute] Replace main src with altsrc if main is unused (#945)
- [RWRoute] Fix comment Eastern -> Western (#943)
- RouterHelper.invertPossibleGndPinsToVccPins() to invert static LUT inputs (#910)
- [TestRWRoute] Stop skipping some tests when < 8GB (#941)
- Temporary workaround to clear logical net after Net.rename() (#942)
- Known failing test for EDIFHierPortInst.getRoutedSitePinInst() (#577)
- Known failing test for Tile.getSites() result different to Vivado (#745)
- Known failing test for BITSLICE_CONTROL output pin projection (#559)
- Add known failing testcase for #756 (#758)
- Update RWRouteConfig.java (#940)
- [RWRoute] Add --lutRoutethru option (#932)
- [RWRoute] Do not pin swap SRL (shift register) cells (#939)
- [LUTTools] LUT pin swapping fixes (#938)
- Net.rename() to clear logical hier net
- Fix regarding issue around bitstream header
- Fixes issue when site wire lacks GND tag
API Additions:
- com.xilinx.rapidwright.bitstream.Bitstream "public boolean writeBitstream(Path path)"
- com.xilinx.rapidwright.bitstream.Frame "public List<BitLocation> getDiff(Frame otherFrame)"
- com.xilinx.rapidwright.design.Cell "public static final String LOCKED = "<LOCKED>";
- com.xilinx.rapidwright.design.Cell "public static final String PORT_TYPE = "<PORT>";
- com.xilinx.rapidwright.design.Cell "public boolean isPortCell()"
- com.xilinx.rapidwright.design.Cell "public String getPropertyValueString(String key)"
- com.xilinx.rapidwright.design.Design "public void writeCheckpoint(String dcpFileName, String edfFileName, CodePerfTracker t)"
- com.xilinx.rapidwright.design.Design "public void writeCheckpoint(Path dcpFileName, Path edfFileName, CodePerfTracker t)"
- com.xilinx.rapidwright.design.Design "public void detachNetlist(Predicate<Cell> preserveCellProperties)"
- com.xilinx.rapidwright.device.BEL "public static BEL getBEL(Device device, SiteTypeEnum siteTypeEnum, String belName)"
- com.xilinx.rapidwright.device.PIP "public boolean isArcInverted()"
- com.xilinx.rapidwright.device.PIP "public void setIsLogicalDriver(boolean isLogicalDriver)"
- com.xilinx.rapidwright.device.SitePIP "public int getIndex()"
- com.xilinx.rapidwright.device.SitePIP "public static SitePIP getSitePIP(Device device, SiteTypeEnum siteTypeEnum, int sitePIPIndex)"
============= RapidWright 2023.2.1-beta released on 2024-01-10 ================
Notes:
- Add EDIFHierCellInst.isUniquified() (#918)
- [RWRoute] RouteNode to extend Node (#916)
- [DesignComparator] Fix whitespace (#937)
- RouteThruHelper.isRouteThruPIPAvailable(Design, WireInterface, WireIn (#915)
- Create a common interface for Node and Wire Objects (#892)
- DesignComparator - compares place and route data (#931)
- DesignTools.createMissingSitePinInsts() to infer SitePinInsts more smartly (#936)
- LUTTools.swapLutPinsFromPIPs() to warn when site pin not found (#934)
- [PhysNetlistReader] Warn and omit if PIP not found (#933)
- [PhysNetlistWriter] Handle PORT cells in GTY tiles (#930)
- [PhysNetlistWriter] Assume static net output BELPins to be sources too (#929)
- [PhysNetlistWriter] Fix stubs on static nets (#928)
- Get a Boolean from EDIFPropertyValue (#926)
- [PhysNetlistWriter] Infer direction of IOB's PAD.PAD BEL pin (#927)
- [RouteThruHelper] Move assertions, improve tests (#925)
- [RWRoute] Don't swap dist RAMs on 'H' BELs since A and WA are shared (#924)
- [PhysNetlistWriter] Recognize static source BELPins (e.g. LUT outputs) (#923)
- [RWRoute] Analyze a tile below the topmost arbitrary one (#921)
- Adding test for IOB placement (#903)
- [DesignTools.makeBlackBox()] Fixes routing issues in makeBlackBox() (#919)
- [ECOTools] Inline cell insertion (#917)
- RouterHelper.invertPossibleGndPinsToVccPins() to work on all invertible pins (#911)
- [RWRoute] GlobalSignalRouting static net router to use [A-H]MUX outputs (#914)
- [RWRoute] Fix exception for unrouteable connections (#913)
- Declare gradle dependency explicitly (#909)
- Fixes [Versal BELAttr] Parsing issue #912
- Add site pins when site routing through inverter BELs
- Fix UltraScale+ IBUF site routing
- Fix DSP pin mapping removals during site routing
- Adds support for special clock Node flag present in Versal designs
API Additions:
- com.xilinx.rapidwright.device.Node "public Node(Node node)"
- com.xilinx.rapidwright.device.Package "public synchronized PackagePin getPackagePin(Site site)"
- com.xilinx.rapidwright.device.Package "public String getPackagePinName(Site site)"
============= RapidWright 2023.2.0-beta released on 2023-11-20 ================
Notes:
- SLR Corner updates in device models and handling (#886)
- Updates Protobuf to 3.25.0 (#882)
- Updates/adds timestamp APIs (#883)
- Refactor PROHIBIT constraint for faster Tcl interpretation (#881)
- [PerformanceExplorer] Number pblocks by order in file, add first site in dir name (#867)
- DesignTools.createMissingSitePinInsts(Design) to ignore GLOBAL_USEDNET (#880)
- [RWRoute] Check source & sink pin reaches INT tile for dedicated connections (#878)
- ECOTools.createExitSitePinInst() to detect net aliases (#871)
- Rewrite RouterHelper.projectOutputPinToINTNode() with fixes (#877)
- EDIFNetlist.{generateParentNetMap,getNetAliases}() to be inout-aware (#876)
- DesignTools.createMissingSitePinInsts() to cope with net aliases (#875)
- Improve TestECOPlacementHelper (#874)
- Add com.xilinx.rapidwright.eco.ECOPlacementHelper (#870)
- RouteThruHelper to handle SiteInst == null (#866)
- Add RouteThruHelper.isRouteThruPIPAvailable(Design, Node, Node) overload (#865)
- Add DesignTools.getConnectedBELPins() (#864)
- RelocationTools fixes and more robust testing (#863)
- Fix TimingAndWirelengthReport.main() (#860)
- [Tests] Symlinks to absolute paths (#862)
- added check to see if Cell.getLogicalPinMapping() is null (#783)
- [DCP] Update tests to infer SitePinInsts (#857)
- Replace $(shell ...) with $(wildcard) and $(subst) in Makefile (#856)
- Undpreccate Design.createCell()
- Special clock flag fix for Versal DCPs
- More conservative SitePinInst creation upon DCP load
API Additions:
- com.xilinx.rapidwright.design.SitePinInst "public int getConnectedTileWire()"
- com.xilinx.rapidwright.device.Device "public int getSiteIndex(String siteName)"
- com.xilinx.rapidwright.device.Device "public int getSiteIndex(Site site)"
- com.xilinx.rapidwright.device.Device "public Site getSiteByIndex(int siteIndex)"
- com.xilinx.rapidwright.device.Device "public Site[] getAllSites()"
API Removals:
- com.xilinx.rapidwright.bitstream.ConfigRow "public ConfigRow()"
============= RapidWright 2023.1.4-beta released on 2023-10-20 ================
Notes:
- Include RapidWright API Lib Javadoc in Gradle Build (#855)
- Add com.xilinx.rapidwright.eco.ECOTools package (#850)
- More Polynomial Generator improvements (#854)
- ReportRouteStatusResult.isFullyRouted() to check >0 logical net found (#852)
- Fixes for the PolynomialGenerator (tutorial) (#846)
- Test that Design.createModuleInst() copies static sources (#839)
- ModuleInst.place() to check both RAMB36/RAMB18 sites for overlap (#841)
- PartialRouter preprocessing and clock routing improvements (#843)
- Updates to Interchange README.md (#832)
- Simplify and make DesignTools.updatePinsIsRouted() more robust (#844)
- RouterHelper.invertPossibleGndPinsToVccPins() to not invert BRAM CLKs (#840)
- ModuleInst.connect() to leave physical Net alone for pass-thrus (#722)
- Unroute site routing when removing a cell (#729)
- PartialRouter's global router to not unpreserve sink nodes (#736)
- DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
- DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
- Add DcpToInterchange class (#704)
- Add compile step (#733)
- Add EdifToLogicalNetlist to MainEntrypoint (#731)
- [PhysNetlistReader] Set Cell type for routethru cells (#727)
- Fix Javadoc warnings (#723)
- Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
- Multilevel macro expansion (#726)
- TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
- DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
- Add missing Versal DSP SiteTypeEnum (#842)
- [RWRoute] Further fix/cleanup around alternate source pins (#830)
- Adding out-of-context flag to RWRoute (#836)
- fix a bug in PipelineGeneratorWithRouting.createPipeline() (#837)
- Fix verb tense in RWRoute INFO msg (#835)
- Enable RWRoute to load Interchange designs from main() (#834)
- [VivadoTools] Check for Vivado on PATH first (#831)
- [EDIFNetlist] - Ensure Macro Expansion Deep Copies Children (#828)
- Minor RWRoute and UltraScaleClockRouting fixes (#829)
- Properly add/remove dual-output pins (#825)
- [TestRouteNode] Update comment; swap east and west (#827)
- Add VivadoTools.reportRouteStatus() overload for specific net status (#823)
- Update link to Discussions forum (#824)
- [RWRoute] Only add alternative sources to SiteInst if used (#821)
- RouteNode.getPIPsBackToSource() to recognize reversed PIPs (#822)
- [PhysNetlistReader] Create FFRoutethruCell-s correctly (#817)
- Add test for Design.movePinsToNewNetDeleteOldNet() (#796)
- Test Cell.getAllCorrespondingSitePinNames() works for multi-outputs (#792)
- [PhysNetlistWriter] No IO site port output BELPins without SitePinInst (#820)
- [PhysNetlistWriter] Set PhysPip.setForward() even if not bidir (#819)
- [PhysNetlistWriter] Skip output BELPins without cells, and port cells (#818)
- Test that Design.createModuleInst() copies static sources (#839)
- Design.createModuleInst() to copy STATIC_SOURCE_ SiteInsts properly
- Store partname in netlist for new designs
- SiteInst.addPin() to trackChanges() when ?_O or ?MUX pin added
- Method parameter names preserved in API lib jar
- API Additions:
- com.xilinx.rapidwright.design.Module "public Cell getCell(String cellName)"
- com.xilinx.rapidwright.design.Net "public boolean isVCCNet()"
- com.xilinx.rapidwright.design.Net "public boolean isGNDNet()"
- com.xilinx.rapidwright.design.Net "public boolean isUsedNet()"
============= RapidWright 2023.1.3-beta released on 2023-09-13 ================
Notes:
- Fix DesignTools.getConnectionPIPs() (#809)
- [PhysNetlistWriter] RouteBranchNode.getDrivers() to return input BelPin (#800)
- Adds site pins to example code generation for nets. (#807)
- Update to fixed microblazeAndILA_3pblocks.dcp (#808)
- [LogNetlistWriter] Refactor writeStrings method to be public static (#804)
- [VivadoTools] ReportRouteStatusResult to parse more stats (#805)
- EDIF improvements (#806)
- RWRoute improvements (#803)
- Adds a createBitstream() method to VivadoTools (#801)
- Small DesignTools improvements (#797)
- added static function that helps produce test nets (including PIPs) (#784)
- Add reference copy methods (#794)
- [RWRoute] Add alternate source pins and set source routed flags (#787)
- Adds support for RouteThru LUT equations and makes LUTEquationEvaluator public (#795)
- Fix TestDCPLoad to prevent issues with parallel testing (#793)
- [PhysNetlistWriter] Fix route tree construction for bidir PIPs (#791)
- VivadoTools.reportRouteStatus() to handle encrypted cells (#777)
- [PhysNetlistWriter] Insert site port BELPin before site pin (#790)
- fixed null pointer exception in getPhysicalNetFromPin() (#775)
- LUT cell companion helper methods (#764)
- Check for error situation RAPIDWRIGHT_PATH set but not CLASSPATH (#772)
- Set reversed flag on bi-directional PIPs used from end->start (#774)
- Fix RouterHelper.projectOutputPinToINTNode() for depop pins (#779)
- Make PartialRouter.getUnroutedPins() public (#778)
- FileTools.runCommand() - Adds ability to choose run directory (#769)
- [GlobalSignalRouting] Static router to not create site pin if exists (#768)
- RouteThru support for FFs in UltraScale architecture
- Fixes minor SitePinInst creation when reading a DCP
- Improvements to Net.rename() when tracking changes
- Design.detachNetlist() to detach routethru cells
- Adds reference copy APIs and ability to keep copies of modified
SiteInsts and Nets
- Improvements to DCP reading compatibility for different flows
within Vivado
- API Additions:
- com.xilinx.rapidwright.bitstream.BitLocation "public int hashCode()"
- com.xilinx.rapidwright.bitstream.BitLocation "public boolean equals(Object obj)"
- com.xilinx.rapidwright.bitstream.Bitstream "public static Bitstream readBitstream(Path fileName)"
- com.xilinx.rapidwright.bitstream.Block "public int getBit(BitLocation bit, Tile tile)"
- com.xilinx.rapidwright.bitstream.Block "public boolean updateBit(BitLocation bit, Tile tile, int value, Block golden)"
- com.xilinx.rapidwright.bitstream.ConfigRow "public ConfigRow(int configRowIdx)"
- com.xilinx.rapidwright.bitstream.FAR "public Block getConfigBlock(int slrCfgOrder)"
- com.xilinx.rapidwright.bitstream.Packet "public int hashCode()"
- com.xilinx.rapidwright.bitstream.Packet "public boolean equals(Object obj)"
- com.xilinx.rapidwright.design.Cell "public static final String FF_ROUTETHRU_TYPE"
- com.xilinx.rapidwright.design.Cell "public Cell getReferenceCopy()"
- com.xilinx.rapidwright.design.Cell "public boolean isFFRoutethruCell()"
- com.xilinx.rapidwright.design.Design "public boolean isCopyingOriginalNetsRouting()"
- com.xilinx.rapidwright.design.Design "public void setCopyingOriginalNetsRouting(boolean copyOrigNets)"
- com.xilinx.rapidwright.design.Design "public Map<String, List<PIP>> getOriginalNetRouting()"
- com.xilinx.rapidwright.design.Design "public boolean isCopyingOriginalSiteInsts()"
- com.xilinx.rapidwright.design.Design "public void setCopyingOriginalSiteInsts(boolean copyOrigSiteInsts)"
- com.xilinx.rapidwright.design.Design "public Map<String, SiteInst> getOriginalSiteInsts()"
- com.xilinx.rapidwright.design.Net "public List<PIP> getCopyOfPIPs()"
- com.xilinx.rapidwright.design.SiteInst "public void addPin(SitePinInst sitePinInst)"
- com.xilinx.rapidwright.design.SiteInst "public SiteInst getReferenceCopy()"
============= RapidWright 2023.1.2-beta released on 2023-07-24 ================
Notes:
- Shell creation improvements to enable lock_design and timing closure preservation (#760)
- Adds a MakeBlackBox command line tool (#747)
- Removes the VCC A6 pin on 5LUT usages when removing cells (#741)
- Add DesignTools.getAllRoutedSitePinsFromPhysicalPin() (#755)
- Correctly update dual-output route flags when unrouting (#737)
- [PhysNetlistReader] Set cell type of LOCKED cells (#767)
- Updates RAM32X1S property to correct default (#751)
- [Interchange] PhysNetlistReader to create STATIC_SOURCE SiteInsts (#766)
- RWRoute Fixes (#765)
- GlobalSignalRouting.routeStaticNet() to create output SPIs (#761)
- DesignTools.createCeSrRstPinsToVCC() to skip non-SLICE FFs (#744)
- [PartialRouter] Improve incremental global routing (#759)
- GlobalSignalRouting fixes for routing to non clock-pins (#757)
- DesignTools.makePhysNetNamesConsistent() to merge static nets too (#753)
- [UltraScaleClockRouting] Reset RouteNode.parent (#752)
- Created parameterizable counter with an adder as a submodule (#713)
- [RWRoute] Fix PartialRouter for when clk node already unpreserved (#746)
- [Interchange] Fix PhysicalNetlist's MultiCellPinMapping (#743)
- Unroute site routing when removing a cell (#729)
- PartialRouter's global router to not unpreserve sink nodes (#736)
- DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
- DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
- Add DcpToInterchange class (#704)
- Add compile step (#733)
- Add EdifToLogicalNetlist to MainEntrypoint (#731)
- Fix Javadoc warnings (#723)
- Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
- [PhysNetlistReader] Set Cell type for routethru cells (#727)
- Multilevel macro expansion (#726)
- TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
- DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
- Fix to create alternate source pins on dual output nets.
- Fixes incorrect Versal SLR corner tile entries
- Cell.getProperty() returns null if no EDIFCellInst found
- Cell.getAllSitePinsFromLogicalPin() to not return any null pins
- Cell.getAllCorrespondingSitePinNames() to not NPE if no physical pin mapping
- Cell.getCorrespondingSitePinName() to consider F?MUX routethrus
- API Additions:
- com.xilinx.rapidwright.device.PIP "public boolean isLogicalDriver()"
- com.xilinx.rapidwright.design.Cell "public String getCorrespondingSitePinName(String logicalPinName, String physPinName, List<String> siteWires)"
============= RapidWright 2023.1.1-beta released on 2023-06-21 ================
Notes:
- UltraScale Incremental Clock Router Improvements (#540)
- Adds VivadoTools, a Vivado wrapper/helper in RapidWright (#684)
- Fixes published Maven Central jar (#698)
- Enhancements to RWRoute (#691, #696)
- Interchange reader/writer improvements (#677)
- Fix for issue #709
- Improves handling of site routing and site pins when updating
physical netlist
============= RapidWright 2023.1.0-beta released on 2023-05-31 ================
Notes:
- Support for Vivado 2023.1 devices and reading 2023.1 DCPs
- Full adoption of Zstandard compression for all device and data
files - 11% faster device loads and 108% faster device cache loads with file size reductions of 32% and 52% respectively.
- Has a new 'rapidwright' run wrapper that avoids the need to set CLASSPATH, provides convenience to run any class file with a main() method, run the Jython interpreter and enables one-liner Jython commands. Run `rapidwright` at the prompt for more details.
- Fix duplicate net source pins (won't set the alternate source if it is the same as the source)
- Change Net.connect() behavior to connect to existing SitePinInst if net is null
- DesignTools.createCeSrRstPinsToVCC() to detect gnd to invert (#664)
- EDIFNetlist.cellInstIOStandardFallback to collect set of IOSTANDARDs instead of throwing an error if there is a conflict (#671)
- [EDIF] More expanded macros to be deep copied from prim library (#672)
- Ignore TestCheckOpenFilesInstalled.test if outside of gradle (#674)
- [EDIF] EDIFNetlist.collapseMacroUnisims() to not clobber cell (#675)
- [EDIF] Explicit DEFAULT IOStandard on Cell to be overriden by Net (#686)
- API Additions:
- (None)
- API Deprecation Removals (--> Replacements) [Closed Source]:
- com.xilinx.rapidwright.device.Tile "public String getNameRoot() --> "public string getRootName()"
- com.xilinx.rapidwright.device.Device "public Tile[][] getTilesByNameRoot(String nameRoot)" --> "getTilesByRootName(String rootName)"
============= RapidWright 2022.2.3-beta released on 2023-05-03 ================
Notes:
- Adds preliminary support for Zstandard compression. Uses it in device cache file generation. Next release will use it for all data files.
- Fixes an issue with missing Versal Premium families unisim data (#631)
- Adds an option to the Interchange device model writer to exclude routing info. to enable placement of the largest devices (#658)
- Fixes an issue in the PBlockGenerator parser (#633)
- Resolves an issue where collapsed macro ports' parent reference was not set properly (#654)
- EDIFNetlist.getIOStandard() to inherit IOStandard from EDIFNet (#646)
- API Additions:
- com.xilinx.rapidwright.design.Design "public static boolean readEdifAndXdefInParallel()"
- com.xilinx.rapidwright.design.Design "public static void setReadEdifAndXdefInParallel(boolean readEdifAndXdefInParallel)"
============= RapidWright 2022.2.2-beta released on 2023-03-10 ================
Notes:
- Includes new API to ensure all downloaded/generated dependant files are present in RapidWright install (#613)
- Change in Cell.hashCode() and Cell.equals() behavior such that it now distinguishes routethru cells (#624), see Issue #611
- Fixes an issue with isFF() (#622)
- Resolves issue with Cells and Nets that contain backslashes not being properly loaded (#612)
- Fix for parsing gzipped EDIF files in parallel (#619)
- Fix for EDIF export bussed names that collide with bitty names (#616)
- API Additions:
- com.xilinx.rapidwright.device.Device "public void ensureDeviceCacheFileIsGenerated()"
============= RapidWright 2022.2.1-beta released on 2023-01-19 ================
Notes:
- Preserves hwdef information in DCP (#597)
- Adds APIs to access BELAttr information in design (#598)
- Many improvements to RWRoute to cleanup code and improves both quality and runtime performance
- Fixes a bug with 2022.2 DCPs where hierarchical names were getting mangled in RapidWright (#603)
- Adds support for reading gzipped EDIF files
- Fixes an issue with Design.updateDesignWithCheckpointPlaceAndRoute() on more recent version DCPs (#601)
- API Additions:
- com.xilinx.rapidwright.design.Design "public Map<Site, SiteConfig> getBELAttrs()"
- com.xilinx.rapidwright.design.Design "public BELAttr addBELAttr(Net net, Site site, SiteTypeEnum type, BEL bel, String name, String value)"
- com.xilinx.rapidwright.device.Device "public BEL getBEL(SiteTypeEnum type, String belName)"
- com.xilinx.rapidwright.device.Device "public BEL[] getBELs(SiteTypeEnum type)"
============= RapidWright 2022.2.0-beta released on 2022-11-16 ================
Notes:
- Support for Vivado 2022.2 devices and DCPs
- ~5% memory usage improvement over 2022.1.4 when loading (large) DCPs
- Removes several deprecated APIs (See list below)
- Fixes the method "public synchronized boolean isIOStandardSupported(String ioStandard)" on Package.
- Corrects null node scenario as seen in #581
- Moving device root tile name cache into open source (#578)
- API Additions:
- com.xilinx.rapidwright.design.Cell "public Cell copyCell(String name, EDIFHierCellInst inst)"
- com.xilinx.rapidwright.design.Cell "public Cell copyCell(String name, EDIFHierCellInst inst, SiteInst i)"
- com.xilinx.rapidwright.design.Cell "public Map<String, EDIFPropertyValue> getProperties()"
- com.xilinx.rapidwright.device.Device "public Tile[][] getTilesByRootName(String rootName)"
- com.xilinx.rapidwright.device.Tile.java "public String getRootName()"
- API Deprecation Removals (--> Replacements) [Open Source]:
- com.xilinx.rapidwright.design.ModuleInst "public ArrayList<SiteInst> getInsts()"
--> "public List<SiteInst> getSiteInsts()"
- com.xilinx.rapidwright.design.ModuleInst "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile, Device dev)"
--> "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile)"
- com.xilinx.rapidwright.edif.EDIFCellInst "public Map<String, EDIFPortInst> getPortInstMap()"
--> "public Collection<EDIFPortInst> getPortInsts()"
- com.xilinx.rapidwright.edif.EDIFCellInst "public void updateCellType(EDIFCell cellType)"
--> "public void setCellType(EDIFCell cellType)"
- com.xilinx.rapidwright.edif.EDIFNet "public Map<String, EDIFPortInst> getPortInstMap()"
--> "public Collection<EDIFPortInst> getPortInsts()"
- com.xilinx.rapidwright.edif.EDIFNet "public EDIFPortInst getPortInst(String fullName)"
--> "public EDIFPortInst getPortInst(EDIFCellInst inst, String portInstName)"
- com.xilinx.rapidwright.edif.EDIFNet "public EDIFPortInst removePortInst(String portInstName)"
--> "public EDIFPortInst removePortInst(EDIFCellInst inst, String portInstName)"
--> "public EDIFPortInst removePortInst(EDIFPortInst portInst)"
- com.xilinx.rapidwright.edif.EDIFNetlist "public static String getHierParentName(String hierReferenceName)"
--> com.xilinx.rapidwright.edif.EDIFHierCellInst.getParent().toString()
--> com.xilinx.rapidwright.edif.EDIFHierNet.getParent().toString()
--> com.xilinx.rapidwright.edif.EDIFHierPortInst.getParent().toString()
- com.xilinx.rapidwright.edif.EDIFNetlist "public static String getNextHierChildName(String ancestor, String descendent)"
--> com.xilinx.rapidwright.edif.EDIFHierCellInst.getParent().toString()
- com.xilinx.rapidwright.edif.EDIFNetlist "public HashMap<String,EDIFPort> generateEDIFPortMap()"
--> com.xilinx.rapidwright.edif.EDIFCell.getPortMap()
- com.xilinx.rapidwright.edif.EDIFTools "public static EDIFNet connectLogicalNetAcrossHierarchy(String sinkParentInstName, String srcParentInstName, Map<String, EDIFNet> parentInstNameToLogNet, EDIFNetlist netlist)"
--> "public static void connectPortInstsThruHier(EDIFHierPortInst src, EDIFHierPortInst snk, String newName)"
- com.xilinx.rapidwright.edif.EDIFPort "public String getStemName()"
--> "public static String getRootBusName(String name, boolean includeOpenBracket)"
- com.xilinx.rapidwright.edif.EDIFPropertyObject "public EDIFPropertyValue addProperty(EDIFName key, EDIFPropertyValue value)"
--> "public EDIFPropertyValue addProperty(String key, EDIFPropertyValue value)"
- com.xilinx.rapidwright.edif.EDIFPropertyObject "public void addProperties(Map<EDIFName,EDIFPropertyValue> properties)"
--> "public EDIFPropertyValue addProperty(String key, EDIFPropertyValue value)"
- com.xilinx.rapidwright.edif.EDIFPropertyObject "public Map<EDIFName, EDIFPropertyValue> getProperties()"
--> "public Map<String, EDIFPropertyValue> getPropertiesMap()"
- com.xilinx.rapidwright.edif.EDIFPropertyObject "public void setProperties(Map<EDIFName, EDIFPropertyValue> properties)"
--> "public void setPropertiesMap(Map<String, EDIFPropertyValue> properties)"
- com.xilinx.rapidwright.edif.EDIFTools "public static EDIFCellInst getEDIFCellInst(EDIFNetlist netlist, String hierarchicalName)"
--> com.xilinx.rapidwright.edif.EDIFNetlist.getCellInstFromHierName()
- com.xilinx.rapidwright.edif.EDIFTools "public static String getHierarchicalRootFromPinName(String s)"
--> com.xilinx.rapidwright.edif.EDIFHierCellInst.getParent().toString()
- com.xilinx.rapidwright.edif.EDIFTools "public static void flattenNetlist(Design design)"
--> "public static Boolean uniqueifyNetlist(Design design)"
- com.xilinx.rapidwright.util.FileTools "public static boolean checkIfRapidWrightResourceExists(String name)"
--> N/A
- com.xilinx.rapidwright.util.FileTools "public static boolean folderCheck(String name)"
--> java.io.File().exists()
- com.xilinx.rapidwright.util.MessageGenerator "public static void briefErrorAndExit(String msg)"
--> System.err.println(), return or throw new RuntimeException() (avoid System.exit())
- com.xilinx.rapidwright.util.MessageGenerator "public static void briefMessageAndExit(String msg)"
--> System.out.println(), return or throw new RuntimeException() (avoid System.exit())
- API Deprecation Removals (--> Replacements) [Closed Source]:
- com.xilinx.rapidwright.design.Cell "public Map<EDIFName, EDIFPropertyValue> getProperties()"
--> "public Map<String, EDIFPropertyValue> getProperties()"
- com.xilinx.rapidwright.design.Cell "public Cell(String name, EDIFCellInst edifCellInst)"
--> "public Cell(String name)"
- com.xilinx.rapidwright.design.Cell "public Cell(String name, BEL bel, EDIFCellInst edifCellInst)"
--> "public Cell(String name, BEL bel)"
- com.xilinx.rapidwright.design.Cell "public Cell(String name, SiteInst siteInst, BEL bel, EDIFCellInst edifCellInst)"
--> "public Cell(String name, SiteInst siteInst, BEL bel)"
- com.xilinx.rapidwright.design.Cell "public Cell copyCell(String name, EDIFCellInst edifCellInst)"
--> "public Cell(String name)"
- com.xilinx.rapidwright.design.Cell "public Cell copyCell(String name, EDIFCellInst edifCellInst, SiteInst i)"
--> "public Cell(String name)"
- com.xilinx.rapidwright.design.Cell "public void setEDIFCellInst(EDIFCellInst edifCellInst)"
--> "public void setEDIFHierCellInst(EDIFHierCellInst inst)"
- com.xilinx.rapidwright.design.Cell "public void setProperties(Map<EDIFName, EDIFPropertyValue> properties)"
--> "public void setPropertiesMap(Map<String, EDIFPropertyValue> properties)"
- com.xilinx.rapidwright.design.Design "public Net createNet(EDIFNet net)"
--> "public Net createNet(EDIFHierNet net)"
- com.xilinx.rapidwright.design.Design "public Net createNet(String name, EDIFNet net)"
--> "public Net createNet(EDIFHierNet net)"
- com.xilinx.rapidwright.design.Design "public HashMap<String,EDIFCellInst> getNetlistInstMap()"
--> com.xilinx.rapidwright.netlist.EDIFNetlist.generateCellInstMap();
- com.xilinx.rapidwright.design.Design "public HashMap<String, EDIFNet> getNetlistNetMap()"
--> com.xilinx.rapidwright.netlist.EDIFNetlist.generateEDIFNetMap();
- com.xilinx.rapidwright.design.Module "public boolean isValidPlacement(Site proposedAnchorSite, Device dev, Design design)"
--> "public boolean isValidPlacement(Site proposedAnchorSite, Design design)"
- com.xilinx.rapidwright.design.Module "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile, Device dev)"
--> "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile)"
- com.xilinx.rapidwright.design.Net "public Net(String name, EDIFNet logicalNet)"
--> "public Net(String name)"
- com.xilinx.rapidwright.design.Net "public Net(EDIFNet logicalNet)"
--> "public Net(EDIFHierNet net)"
- com.xilinx.rapidwright.design.Net "public SitePinInst createPin(boolean isOutput, String pinName, SiteInst si)"
--> "public SitePinInst createPin(String pinName, SiteInst si)"
- com.xilinx.rapidwright.design.Net "public void setLogicalNet(EDIFNet logicalNet)"
--> "public void setLogicalHierNet(EDIFHierNet logicalHierNet)"
- com.xilinx.rapidwright.design.SiteInst "public Set<Net> getNetList()"
--> "public Set<Net> getConnectedNets()"
- com.xilinx.rapidwright.design.SiteInst "public Map<String,Net> getNetSiteWireMap()"
--> "public Map<String, Net> getSiteWireToNetMap()"
- com.xilinx.rapidwright.device.Device "public String getDeviceName()"
--> "public String getName()"
- com.xilinx.rapidwright.device.Node "public Node(Tile tile, int wire)"
--> "public static Node getNode(Tile tile, int wire)"
- com.xilinx.rapidwright.device.Node "public Node(Wire w)"
--> "public static Node getNode(Wire wire)"
- com.xilinx.rapidwright.device.Node "public Node(Tile tile, String wireName)"
--> "public static Node getNode(Tile tile, int wire)"
- com.xilinx.rapidwright.device.Node "public Node(String nodeName, Device dev)"
--> "public static Node getNode(String nodeName, Device dev)"
- com.xilinx.rapidwright.device.Node "public Node(RouteNode routeNode)"
--> "public static Node getNode(RouteNode routeNode)"
- com.xilinx.rapidwright.device.Package "public String getSiteType(String packagePinName)"
--> "public Site getSiteFromPackagePin(String packagePinName)"
- com.xilinx.rapidwright.device.PackagePin "public String getSiteType()"
--> "public Site getSite()"
============= RapidWright 2022.1.4-beta released on 2022-11-03 ================
Notes:
* Can now load EDIF netlist in parallel with placement and routing when reading a DCP
* Allows the Design object to detach the corresponding EDIFNetlist to save working memory
* Restores the original EDIFPort.getBusName() behavior
* Changes EDIFPortInstList duplicate behavior from prohibit to overwrite
* Net.removePin() to unset alternate source
* Fix Net.removePin() for static nets under preserveOtherRoutes
* Option to track process peak memory usage
* Fix for #548, #572, #564
* Fixes intrasite routing to CARRY pins from LUT outputs on UltraScale/+
- API Additions:
- com.xilinx.rapidwright.design.Cell "public void setEDIFHierCellInst(EDIFHierCellInst inst)"
- com.xilinx.rapidwright.design.Design "public void detachNetlist()"
- com.xilinx.rapidwright.device.Node "public Collection<Node> getAllDownhillNodes(Collection<Node> nodes)"
- com.xilinx.rapidwright.device.Node "public Collection<Node> getAllUphillNodes(Collection<Node> nodes)"
============= RapidWright 2022.1.3-beta released on 2022-09-19 ================
Notes:
* Adds support for partition pins, several new APIs added as seen below
* Fixes site routing for F8MUX inputs and routethrus on CARRY pins
* Fix for DCPs created with -binary_only option
* Fix for DCPs that don't end with '.dcp' extension
* Optimizes EDIF memory usage (see #463)
* Improved handling of dual-output nets
* Fixes BEL.canInvert()
* Preserves BEL attributes DB in Versal DCPs
- API Additions:
- com.xilinx.rapidwright.design.Cell "public void setPropertiesMap(Map<String, EDIFPropertyValue> properties)"
- com.xilinx.rapidwright.design.Cell "public List<String> getAllCorrespondingSitePinNames(String logicalPinName, boolean considerLutRoutethru)"
- com.xilinx.rapidwright.design.Design "public boolean addPartitionPin(PartitionPin pin)"
- com.xilinx.rapidwright.design.Design "public boolean removePartitionPin(PartitionPin pin)"
- com.xilinx.rapidwright.design.Design "public List<PartitionPin> getPartitionPins()"
- com.xilinx.rapidwright.design.Design "public PartitionPin createPartitionPin(EDIFHierPortInst pin, Node node)"
- com.xilinx.rapidwright.design.Design "public PartitionPin createPartitionPin(EDIFPort port, int index, Node node)"
- com.xilinx.rapidwright.design.Design "public PartitionPin createPartitionPin(EDIFPort port, Node node)"
- com.xilinx.rapidwright.design.Design "public void unrouteSites()"
- com.xilinx.rapidwright.design.Net "public static final String Z_NET = "GLOBAL_DUMMY_ROUTE""
- com.xilinx.rapidwright.design.PartitionPin "public Tile getTile()"
- com.xilinx.rapidwright.design.PartitionPin "public String getTileName()"
- com.xilinx.rapidwright.design.PartitionPin "public void setNode(Node node)"
- com.xilinx.rapidwright.design.PartitionPin "public Node getNode()"
- com.xilinx.rapidwright.design.PartitionPin "public int getWireIndex()"
- com.xilinx.rapidwright.design.PartitionPin "public String getWireName()"
- com.xilinx.rapidwright.design.PartitionPin "public void setIsFixed(boolean isFixed)"
- com.xilinx.rapidwright.design.PartitionPin "public void setIsWireFixed(boolean isWireFixed)"
- com.xilinx.rapidwright.design.PartitionPin "public boolean isFixed()"
- com.xilinx.rapidwright.design.PartitionPin "public boolean isWireFixed()"
- com.xilinx.rapidwright.design.PartitionPin "public String getInstanceName()"
- com.xilinx.rapidwright.design.PartitionPin "public boolean isPort()"
- com.xilinx.rapidwright.design.PartitionPin "public String getTerminalName()"
- com.xilinx.rapidwright.design.PartitionPin "public String getLibCellName()"
- com.xilinx.rapidwright.design.PartitionPin "public String toString()"
- com.xilinx.rapidwright.design.SiteInst "public boolean removePin(SitePinInst sitePinInst)"
============= RapidWright 2022.1.2-beta released on 2022-07-27 ================
Notes:
* Includes some memory usage improvements of 8-14% for a parsed EDIF netlist (#428)
* Placement memory reduction by 19% or ~4.7% for a design
* For 2022.1 DCPs, enables placement & routing information to be read in parallel, or load DCPs up
to 44% faster.
* Fix to DeviceBrowser to browse devices prior to downloading their database file (#427)
* Fixes placed (but not routed) design import/export for Interchange-based files (#467)
* Design.createModuleInst() now copies netlist cells rather than migrate them
* Properly unroutes routethru in SiteInst.unrouteIntraSiteNet()
* Net and Cell classes now keep lazy reference to hierarchical netlist object
* Net.unroutePin() now uses code in DesignTools.unroutePins()
* Fix to unique-ify netlist (or previously flatten netlist) (#430)
* Bumps Gradle Wrapper version from 7.1 to 7.4.2 to enable Java 18 support (#453)
* Replacing EDIF in DCP now also removes existing binary netlist equivalent (.xn)
* Includes PRs: #409, #417, #424, #427, #428, #429, #430, #431, #432, #437, #442, #443, #445, #446,
#449, #450, #451, #453, #455, #459, #461, #462, #465, #469, #470, #471, #472, #476,
#477
* Fixes Issues: #136, #419, #441, #444, #454, #464
- API Additions:
- com.xilinx.rapidwright.design.Cell "public EDIFHierCellInst getEDIFHierCellInst()"
- com.xilinx.rapidwright.design.Design "public Net createNet(EDIFHierNet net)"
- com.xilinx.rapidwright.design.Design "public static boolean replaceEDIFinDCP(String inDcpFileName, String edfFileName, String outDcpFileName)"
- com.xilinx.rapidwright.design.Net "public Design getDesign()"
- com.xilinx.rapidwright.design.Net "public EDIFHierNet getLogicalHierNet()"
- com.xilinx.rapidwright.design.Net "public Net(String name, EDIFHierNet logicalHierNet)"
- com.xilinx.rapidwright.design.Net "public void setDesign(Design design)"
- com.xilinx.rapidwright.design.Net "public void setLogicalHierNet(EDIFHierNet logicalHierNet)"
- com.xilinx.rapidwright.design.SiteInst "public BELPin getBELPin(String belName, String pinName)"
- com.xilinx.rapidwright.device.BELPin "public BELPin getConnectedInputPinOnBEL(BEL bel)"
============= RapidWright 2022.1.1-beta released on 2022-05-13 ================
Notes:
* Fixes crash issue while reading DCPs created by Vivado 2022.1
* Adds more granularity to runtime reporting in reading 2022.1 DCPs
============= RapidWright 2022.1.0-beta released on 2022-05-05 ================
Notes:
* Support for Vivado 2022.1 devices and read of DCPs
* Enables parallel EDIF parsing by default (except when EDIF is readable inside DCP). Depending on
file size and number of available threads, speedup can achieve 2.5-10X faster runtimes.
* Adds facilities to track logical netlist and physical netlist changes to keep a record of
incremental changes in a design.
* Preserves AI Engine and NOC data when writing DCPs from RapidWright
* Disallows turning multiple sitePIPs on on the same RBEL at the same time
* Enables LUT routethru routing on intrasite nets
* Net.addPin() to add output pin as an alternate source if a source on the net already exists
* The anchor object on the Module class has been changed from a SiteInst to a Site
* Allows better recovery of augmented tile cache generation failure
* Includes PRs: #378, #379, #380, #381, #382, #383, #385, #387, #396, #395, #397, #400, #401, #402,
#405, #406, #404, #407
* Fixes Issues: #392
- API Additions:
- com.xilinx.rapidwright.design.Design public "void clearTrackedChanges()"
- com.xilinx.rapidwright.design.Design public "void setTrackingChanges(boolean trackChanges)"
- com.xilinx.rapidwright.design.Design public "boolean isTrackingSiteInstChanges()"
- com.xilinx.rapidwright.design.Design public "void setTrackSiteInstChanges(boolean trackSiteInstChanges)"
- com.xilinx.rapidwright.design.Design public "boolean isTrackingNetChanges()"
- com.xilinx.rapidwright.design.Design public "void setTrackNetChanges(boolean trackNetChanges)"
- com.xilinx.rapidwright.design.Design public "Set<SiteInst> getModifiedSiteInsts()"
- com.xilinx.rapidwright.design.Design public "Set<Net> getModifiedNets()"
- com.xilinx.rapidwright.design.Design public "boolean addModifiedNet(Net net)"
- com.xilinx.rapidwright.design.Design public "boolean addModifiedSiteInst(SiteInst siteInst)"
- com.xilinx.rapidwright.device.Device public "Tile getArbitraryTileOfType(TileTypeEnum type)"
============= RapidWright 2021.2.2-beta released on 2022-03-17 ================
Notes:
* Parallelism enabled by default (#365), can be turned off with:
- ParallelismTools.setParallel(false) or
- Set the environment variable to RW_PARALLEL=0.
* Contains bitstream relocation tools for specific UltraScale+ scenarios (#334, #357, #373)
* EDIF netlist memory optimization - netlist uses ~70% less memory when loaded (#339)
* Binary EDIF format - loads ~5x faster (writes ~2x slower) than plain-text EDIF. After EDIF reads
this format can be cached with setting the environment variable RW_ENABLE_EDIF_BINARY_CACHING (#359)
* 'make update_jars' now pulls the jars from Maven Central instead of the rapidwright_jars.zip (#366)
* Caches to a file the uncommon node map generated at runtime for a device (see #362)
* Includes PRs: #321, #343, #339, #352, #353, #348, #346, #362, #359, #361, #344, #357, #334, #365,
#350, #366, #341, #370, #372, #373, #374, #375, #376, #377
* Fixes Issues: #117, #342, #349
- API Additions:
- com.xilinx.rapidwright.bitstream.Bitstream "public static void checkIfDeviceSupported(String partName)"
- com.xilinx.rapidwright.bitstream.BlockType "public static final BlockType[] values"
- com.xilinx.rapidwright.bitstream.ConfigArray "public static final int FRAME_OVERHEAD_COUNT_PER_ROW"
- com.xilinx.rapidwright.bitstream.OpCode "public static final OpCode[] values"
- com.xilinx.rapidwright.bitstream.PacketType "public static final PacketType[] values"
- com.xilinx.rapidwright.bitstream.RegisterType "public static final RegisterType[] values"
- com.xilinx.rapidwright.design.Module "public Module(Design design, String metadataFileName, boolean unrouteStaticNets)"
- com.xilinx.rapidwright.design.Module "public Module(Design design, boolean unrouteStaticNets)"
- com.xilinx.rapidwright.design.Module "public Site getCorrespondingSite(SiteInst inst, Site anchorSite)"
- com.xilinx.rapidwright.design.SiteInst "public Set<Net> getConnectedNets()"
- com.xilinx.rapidwright.device.Device "public static final String DEVICE_CACHE_FILE_VERSION"
============= RapidWright 2021.2.1-beta released on 2022-02-03 ================
Notes:
* 3-4X faster DCP write times using a new parallel, multi-threaded approach (See #337), Enable with:
- ParallelismTools.setParallel(true) or
- Add the environment variable RW_PARALLEL to the environment.
* Multiple DCP read operations can now be initiated in parallel without errors
* Fixes a number of issues related to SitePinInst creation on DCP load (see #317, #318)
* Adds a new MergeDesign capability, allows users to merge two or more existing designs into a
single implementation (See #331)
* All RapidWright dependencies and itself are published on Maven Central. Removes the need to
manually download rapidwright_jars.zip, instead users can simply run './gradlew update_jars'
* Includes PRs: #287, #291, #289, #297, #290 #300, #296, #294, #304, #305, #313, #319, #324, #328,
#320, #332, #330, #336, #331, #333, #322, #318, #317
* Fixes Issues: #326, #298, #299, #312, #315, #326
- API Additions:
- com.xilinx.rapidwright.design.Design "public void setName(String name)"
- com.xilinx.rapidwright.device.Site "public ClockRegion getClockRegion()"
============= RapidWright 2021.2.0-beta released on 2021-11-09 ================
Notes:
* Updates support for latest Vivado devices in 2021.2
* Adds flag information to BEL and BELPin objects (see API additions)
* Moves the RapidWrightDCP submodule to test/RapidWrightDCP
* Several Block Placer runtime and code improvements
* Adds a method to resolve site routing when combining designs built
from in-context builds into another design
* Adds Python support for CI
* Feature to catch System.exit() calls for Python REPL loops, not
turned on by default in Java 17 and later
* Adds DRC framework
* Fixes Issues: #195, #277, #283, #259
- API Additions:
- com.xilinx.rapidwright.device.BEL "public boolean isLUT()"
- com.xilinx.rapidwright.device.BEL "public boolean isFF()"
- com.xilinx.rapidwright.device.BEL "public boolean isCarry()"
- com.xilinx.rapidwright.device.BEL "public boolean isSRIMR()"
- com.xilinx.rapidwright.device.BEL "public boolean isSliceFFClkMod()"
- com.xilinx.rapidwright.device.BELPin "public boolean isPartOfBus()"
- com.xilinx.rapidwright.device.BELPin "public boolean isData()"
- com.xilinx.rapidwright.device.BELPin "public boolean isClock()"
- com.xilinx.rapidwright.device.BELPin "public boolean isEnable()"
- com.xilinx.rapidwright.device.BELPin "public boolean isSet()"
- com.xilinx.rapidwright.device.BELPin "public boolean isReset()"
============= RapidWright 2021.1.2-beta released on 2021-10-23 ================
Notes:
* Includes RWRoute - a full design timing driven router
* Moves online discussions and forum to GitHub Discussions
https://github.com/Xilinx/RapidWright/discussions (retiring Google Groups).
* Turns off Kryo Unsafe usage for Java 15 and above
* Better auto generation handling of readable EDIF files. Creates an
MD5 checksum for DCPs and unique directory for EDIFs to avoid stale EDIFs.
* Includes Python packaging files and adds the option to use local
development RapidWright build when RAPIDWRIGHT_PATH is set (see #267)
* Adds RapidWright relocation tools - the ability to relocate
implementations without using Modules/ModuleInsts.
* Includes a performance evaluation tool to leverage Vivado to
identify true fmax of a design.
* Improves PartNameTools to return integer values of available
resources of a part.
* Fixes Issues #259, #246, #73, #251, #190
- API Additions:
- com.xilinx.rapidwright.design.Design "public static boolean replaceEDIFinDCP(String dcpFileName, String edfFileName)"
============= RapidWright 2021.1.1-beta released on 2021-09-28 ================
Notes:
* Fixes ModuleInst anchor read issue when loading a RapidWright-generated DCP
* Adds correct macro expansion for BUFG and CFGLUT5 primitives
* For executable jars, the RapidWright default directory has been changed to ~/.local/share/RapidWright on Linux and %APPDATA%\RapidWright on Windows.
* Improvements in Utils and TileColumnPattern for URAM
* Adds dotty graph dump facilities for some logical and physical netlist classes
* Fixed an issue in PolynomialGenerator trying to create duplicate pins
* Various fixes around closing files and streams
* Includes fixes for #228, #238, #244
* Changes return type of Module "public RelocatableTileRectangle getBoundingBox()" from TileRectangle
- API Additions:
- com.xilinx.rapidwright.bitstream.Block "public boolean copyFrameData(Block block)"
- com.xilinx.rapidwright.bitstream.Frame "public boolean copyWords(Frame frame)"
- com.xilinx.rapidwright.design.Cell "public Cell createCell(EDIFHierCellInst inst, BEL bel)"
- com.xilinx.rapidwright.design.Net "public void unroutePin(SitePinInst p)"
============= RapidWright 2021.1.0-beta released on 2021-09-14 ================
Notes:
* Updates device models to the public set released in Vivado 2021.1
* Provides a cloud data file download-on-demand model. No longer need to
download large rapidwright_data.zip with each release. Speeds up
install and enables easier packaging/distribution of RapidWright.
* Adds support to automatically invoke Vivado to create a missing
EDIF file when loading a DCP (if a compatible Vivado is on user's PATH).
* Moves timing model files into git repo (out of data directory)
* Includes fixes for #180, #217
- API Additions:
- com.xilinx.rapidwright.design.Design "public static void setAutoGenerateReadableEdif(boolean autoGenerateReadableEdif)"
- com.xilinx.rapidwright.design.Design "public static boolean isAutoGenerateReadableEdif()"
============= RapidWright 2020.2.7-beta released on 2021-07-26 ================
Notes:
* Several fixes for RapidWright API Lib:
- Resolves left over antennas from mishandled bi-directional PIPs
- Resolves issue in module instance creation due to AltPinmapping
cell names not being updated.
- Fixes range issue with BUFCE_ROW instance in Net.setBufferDelay()
- Fixes when anchor is null when writing out metadata for module
instance in DCP.
- Fixes issue when reloading a DCP with encrypted cells back into
RapidWright and EDN file paths not being propagated.
- Patch for dual output net situation where incorrect routing flags
caused Vivado to crash.
* Includes EDIFHier updates to reduce memory and improve runtime.
Avoids use of a String for hierarchical representation and instead
uses an array of EDIFCellInst
* Includes fixes for #193, #194 and partial for #206
* Includes JUnit tests
============= RapidWright 2020.2.6-beta released on 2021-06-23 ================
Notes:
* Updates Cap'n Proto Java Runtime from 0.1.4 to 0.1.7
* Updates Gradle wrapper to point to 7.1 (#189)
* Updates the singleton Device map to have soft references. Allows
unused device objects to be garbage collected without having to call Device.releaseDeviceReferences().
* Includes a fix and some performance enhancements around module relocation.
* Interchange node discovery optimization (#184)
* Fixes tile caching issue in GUI (#185) and other device browser improvements (#187)
* Workaround for Java 16 and Kryo library (#191 - issue #190)
* Includes fixes for #183, #186
- API Additions:
- com.xilinx.rapidwright.device.Device "public Tile getTile(String nameRoot, int xCoordinate, int yCoordinate)"
- com.xilinx.rapidwright.device.Device "public Tile[][] getTilesByNameRoot(String nameRoot)"
- com.xilinx.rapidwright.device.Module "public static Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile, Tile originalAnchor, Tile[][] tiles)"
- com.xilinx.rapidwright.device.Tile "public String getNameRoot()"
- API Deprecations:
- com.xilinx.rapidwright.device.Device "public static void releaseDeviceReferences()"
- com.xilinx.rapidwright.device.Tile "public String getTileNamePrefix()"
============= RapidWright 2020.2.5-beta released on 2021-05-18 ================
Notes:
* License updates:
- Adds a redistribution clause for the RapidWright API library jar
- Adds entries for the Gradle Wrapper, JUnit 5 and JetBrains Java Annotations
* Now includes the Gradle Wrapper
* Includes fixes for #178 (parts), #179, #181, #182
- API Additions:
- com.xilinx.rapidwright.design.Module "public boolean isValidPlacement(Site proposedAnchorSite, Design design)"
- com.xilinx.rapidwright.design.Module "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile)"
- com.xilinx.rapidwright.design.Net "public SitePinInst createPin(String pinName, SiteInst si)"
- com.xilinx.rapidwright.design.SiteInst "public SitePIP[] getSitePIPs()"
- API Deprecations:
- com.xilinx.rapidwright.design.Module "public boolean isValidPlacement(Site proposedAnchorSite, Device dev, Design design)"
- com.xilinx.rapidwright.design.Module "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile, Device dev)"
- com.xilinx.rapidwright.design.Net "public SitePinInst createPin(boolean isOutput, String pinName, SiteInst si)"
============= RapidWright 2020.2.4-beta released on 2021-04-28 ================
Notes:
* Adds IOBank and IOStandard data to Package objects in device model
to match Vivado Tcl capabilities.
* Allows Ports to have multiple pins (see #156 for details)
* Fix for Issues #161, #159, #61
* Minor DCP format changes for improved Versal support
* Gradle improvements (see #165 for details) that adds three tasks:
1) 'run' - a top level application to run a sub application in RapidWright directly
2) 'installDist' - Creates a distribution of all RapidWright dependant code with convenience startup scripts
3) 'distZip'/'distTar' - Creates a zipped/tar'd distribution
* Allow ports to have multiple pins
* A few other minor changes, please see commit log for details
- API Additions:
- com.xilinx.rapidwright.design.Design "public EDIFCellInst createOrFindEDIFCellInst(String name, EDIFCell cell)"
- com.xilinx.rapidwright.device.Package "public Map<String,IOBank> getIOBanksMap()"
- com.xilinx.rapidwright.device.Package "public IOBank getIOBank(String name)"
- com.xilinx.rapidwright.device.Package "public Collection<IOBank> getIOBanks()"
- com.xilinx.rapidwright.device.Package "public Set<IOStandard> getSupportedIOStandards()"
- com.xilinx.rapidwright.device.Package "public boolean isIOStandardSupported(String ioStandard)"
- com.xilinx.rapidwright.device.Package "public PackagePin getPackagePin(String name)"
- com.xilinx.rapidwright.device.PackagePin "public IOBank getIOBank()"
- com.xilinx.rapidwright.device.IOBank "public int getId()"
- com.xilinx.rapidwright.device.IOBank "public String getName()"