How to estimate accurate utilization of LUTL from synthesized netlist in RapidWright?

[wengwz]

Hello RW team,
I'm trying to get the utilization of each kind of resource from a synthesized netlist in RapidWright. To do this, I traverse all leaf EDIFCellInsts and count the number of instances corresponding to each kind of resource? For example, I count the total number of cell instances of LUT2, LUT3, LUT4, LUT5 and LUT6 as the number of used LUTL(LUT as Logic). I found that this method works well for most resource types including DSP, BRAM, FF and CARRY, except for LUTL. The number of LUTL estimated by this method is significantly larger than the number reported by Vivado? I guess that this is because some smaller LUTs, like LUT4, LUT3 or LUT2, may be packed into a single LUT6 by Vivado. I would like to know what are the rules Vivado follows for packing smaller LUTs into LUT6. Additionally, I also want to know if it's possible to estimate more accurate number of used LUTL from the synthesized netlist in RapidWright according to these rules?

[clavin-xlnx]

Yes, you can traverse all of the leaf cells in a netlist and count up the number of instances of each primitive type to get an estimate of the utilization. As for logic LUTs, multiple smaller instances (LUT2, LUT3, LUT4, etc) can be placed into the same LUT6 BEL site if they share enough inputs to fit within the LUT6 (the A6 input is tied to VCC when placing multiple LUTs into the BEL site). For example, a LUT2 and a LUT3 could be placed into the same LUT6, even if their inputs don't overlap, however, two LUT3s that would require the sharing of at least one input to make a valid placement. You can refer to the CLB user Guides for specific rules around placement (Versal: https://docs.amd.com/r/en-US/am005-versal-clb/IMUX-Register, UltraScale+: https://docs.amd.com/v/u/en-US/ug574-ultrascale-clb).

Ultimately, the packing of LUTs into BEL sites occurs during placement, so you would have to devise a search algorithm that could group LUTs based on their packing/placement criteria.

If you would like to get specific, feel free to share a design that we can look at and compare/contrast with what Vivado reports.

[wengwz]

Thank you for your reply. I have uploaded two synthesized checkpoints in which I find that the counted number of LUTL is significantly larger than the value reported by Vivado. You can access these two checkpoints via this link. For example, in the nvdla, the total number of LUT2, LUT3, LUT4, LUT5 and LUT6 in the netlist is 88595 while the number of LUTL reported by Vivado is only 76350. Besides, I have implemented some codes to pack LUTs and calibrate the utilization of LUTL. But there are still some gaps between the calibrated one and the value reported by Vivado.

public static void calibrateLUTUtils(EDIFCell topCell, Map<EDIFCell, Integer> leafCellUtilMap) {
        Set<String> packedLUTCellTypeName = new HashSet<>(Arrays.asList("LUT2", "LUT3", "LUT4", "LUT5"));

        Set<EDIFCellInst> packedLUTCellInsts = new HashSet<>();

        for (EDIFCellInst cellInst : topCell.getCellInsts()) {
            String cellTypeName = cellInst.getCellType().getName();

            if (!packedLUTCellTypeName.contains(cellTypeName)) continue;
            if (packedLUTCellInsts.contains(cellInst)) continue;

            Map<EDIFCellInst, Integer> neighbor2CommonNetNum = new HashMap<>();
            
            List<EDIFPortInst> inputPorts = getInPortInstsOf(cellInst);
            for (EDIFPortInst portInst : inputPorts) {
                EDIFNet net = portInst.getNet();
                
                for (EDIFPortInst sinkPortInst : getSinkPortsOf(net)) {
                    EDIFCellInst sinkCellInst = sinkPortInst.getCellInst();
                    if (sinkCellInst == null || sinkCellInst == cellInst) continue;

                    if (sinkCellInst.getCellName().equals(cellTypeName)) {
                        if (neighbor2CommonNetNum.containsKey(sinkCellInst)) {
                            Integer netNum = neighbor2CommonNetNum.get(sinkCellInst);
                            neighbor2CommonNetNum.replace(sinkCellInst, netNum + 1);
                        } else {
                            neighbor2CommonNetNum.put(sinkCellInst, 1);
                        }
                    }
                }
            }

            List<Map.Entry<EDIFCellInst, Integer>> sortedNeighbors = neighbor2CommonNetNum.entrySet().stream()
            .sorted(Map.Entry.<EDIFCellInst, Integer>comparingByValue().reversed()).collect(Collectors.toList());

            for (Map.Entry<EDIFCellInst, Integer> neighbor : sortedNeighbors) {
                
                EDIFCellInst neighborCellInst = neighbor.getKey();
                Integer commonNetNum = neighbor.getValue();
                
                Integer packThreshold = inputPorts.size();
                if (cellTypeName.equals("LUT3")) {
                    packThreshold = 2;
                } else if (cellTypeName.equals("LUT2")) {
                    packThreshold = 1;
                }
                
                if (commonNetNum >= packThreshold) {
                    packedLUTCellInsts.add(neighborCellInst);
                    Integer amount = leafCellUtilMap.get(neighborCellInst.getCellType());
                    leafCellUtilMap.replace(neighborCellInst.getCellType(), amount - 1);
                    break;
                } 
            }
        }
    }

[clavin-xlnx]

Thank you for the example DCPs. I loaded the nvdla.dcp design and ran report_utilization in Vivado and can confirm your figure of 76350:

1. CLB Logic
------------

+----------------------------+-------+-------+------------+-----------+-------+
|          Site Type         |  Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| CLB LUTs*                  | 78158 |     0 |          0 |    394080 | 19.83 |
|   LUT as Logic             | 76350 |     0 |          0 |    394080 | 19.37 |
|   LUT as Memory            |  1808 |     0 |          0 |    197280 |  0.92 |
|     LUT as Distributed RAM |  1800 |     0 |            |           |       |
|     LUT as Shift Register  |     8 |     0 |            |           |       |
| CLB Registers              | 88395 |     0 |          0 |    788160 | 11.22 |
|   Register as Flip Flop    | 88395 |     0 |          0 |    788160 | 11.22 |
|   Register as Latch        |     0 |     0 |          0 |    788160 |  0.00 |
| CARRY8                     |  1608 |     0 |          0 |     49260 |  3.26 |
| F7 Muxes                   |  4534 |     0 |          0 |    197040 |  2.30 |
| F8 Muxes                   |  1907 |     0 |          0 |     98520 |  1.94 |
| F9 Muxes                   |     0 |     0 |          0 |     49260 |  0.00 |
+----------------------------+-------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
Warning! For any ECO changes, please run place_design if there are unplaced instances

When I load the design into RapidWright and do a raw count of LUTs, I get:

LUT1: 398
LUT2: 6555
LUT3: 13582
LUT4: 22110
LUT5: 12987
LUT6: 33361
------------------
Total: 88993

I believe the 76350 as reported by Vivado is an estimate so it might be difficult to match computationally. I'm sure you can achieve similar approximations though. I wasn't able to run your example code as the body of some of the methods was missing (getInPortInstsOf and getSinkPortsOf). However, it appears that it is not attempting to pack LUT5s, LUT4s, or LUT1s. I did not intend to convey that I could fully enumerate all of the packing rules in my previous post. A few other examples (again, not necessarily an exhaustive list) is that two LUT5s can be placed in the same LUT6 if they share the same 5 inputs. The same for LUT5 and any other LUT. I placed the nvdla design and then re-ran report_utilization and the total number of LUTs also went down to 74729:

1. CLB Logic
------------

+----------------------------+-------+-------+------------+-----------+-------+
|          Site Type         |  Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| CLB LUTs                   | 76537 |     0 |          0 |    394080 | 19.42 |
|   LUT as Logic             | 74729 |     0 |          0 |    394080 | 18.96 |
|   LUT as Memory            |  1808 |     0 |          0 |    197280 |  0.92 |
|     LUT as Distributed RAM |  1800 |     0 |            |           |       |
|     LUT as Shift Register  |     8 |     0 |            |           |       |
| CLB Registers              | 88437 |     0 |          0 |    788160 | 11.22 |
|   Register as Flip Flop    | 88437 |     0 |          0 |    788160 | 11.22 |
|   Register as Latch        |     0 |     0 |          0 |    788160 |  0.00 |
| CARRY8                     |  1608 |     0 |          0 |     49260 |  3.26 |
| F7 Muxes                   |  4534 |     0 |          0 |    197040 |  2.30 |
| F8 Muxes                   |  1907 |     0 |          0 |     98520 |  1.94 |
| F9 Muxes                   |     0 |     0 |          0 |     49260 |  0.00 |
+----------------------------+-------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.

Are you able to share additional information on why accurate LUT counts pre-placement is important?

[wengwz]

I am trying to partition and floorplan the original design into multiple parts, and I need the pre-placement LUT counts to estimate the resource usage of each part to ensure that there is no over-utilization. I don't require the exact numbers reported by Vivado; an approximate count with minimal error is sufficient. But apparently an error of more than 10K LUTs in the nvdla is not acceptable. The codes I shown above can reduce the error to around 1K~2K. And I think it's possible to get more accurate number if I consider more packing rules you mentioned above in my codes. Thank you for your reply!

[clavin-xlnx]

Thanks, let us know how it goes and if you have any more questions!