From 188bf1715eb10e555da62f5d873408e43ea4dac8 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 20 Jun 2024 10:49:44 +0100 Subject: [PATCH 1/2] [Util] Add v80 to versal list --- src/finn/util/basic.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 91c191962f..0cb029a888 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -292,10 +292,10 @@ def memutil(req_mem_spec, primitive_spec): def is_versal(fpgapart): """Returns whether board is part of the Versal family""" - return ( - fpgapart[0:4] in ["xcvc", "xcve", "xcvp", "xcvm", "xqvc", "xqvm"] - or fpgapart[0:5] == "xqrvc" - ) + return fpgapart[0:4] in ["xcvc", "xcve", "xcvp", "xcvm", "xqvc", "xqvm"] or fpgapart[0:5] in [ + "xqrvc", + "xcv80", + ] def get_dsp_block(fpgapart): From 380d2ac00a91600fb39a06dcd27eaf50a9fd4a6f Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 8 Jul 2024 11:26:49 +0100 Subject: [PATCH 2/2] [RTL MVAU] Allow for 4bit compute with dsp48 for versal devices --- .../custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index 3e81aa93e0..d9ab501117 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -208,7 +208,10 @@ def _resolve_impl_style(self, dsp_block): weight_width = self.get_input_datatype(1).bitwidth() if dsp_block == "DSP58": - return "mvu_vvu_8sx9_dsp58" + if act_width <= 4 and weight_width <= 4: + return "mvu_4sx4u_dsp48e2" + else: + return "mvu_vvu_8sx9_dsp58" else: if act_width <= 4 and weight_width <= 4: if dsp_block == "DSP48E1":