vgg10-radioml mapping of IQ to input and classification to output of generated IP

[davidfhorowitz]

Hello,

I generated the IP from this tutorial:

My goal is to test this in hardware on a RFSoC. I have some questions:

1. I ran through generating the IP for the zcu104. I opened the stitched IP project, changed the part to a zcu111, and synthesized and did not get any errors. Is this enough for the IP to work on my part or are there other steps required?

2. What is the expected input and output from the IP? The input axis interface is 16 bits wide, how is the IQ data mapped to these 16 bits? The output from the IP is 8 bits wide, how does the classification map to these bits?

Thanks

[fpjentzsch]

Hi,

1. That should work. Please report back if you encountered any issues here.

2. The input (each I and Q compnent) is quantized to 8 bit integers, so you have a 2x8=16 bit input stream. I don't recall in which order the I/Q are arranged, I would need to double check. The lower 8 bits will be one component and the upper 8 bits the other component.

The output is an 8-bit integer (AXIS requires stream widths of multiples of 8) that gives the index (class) with the highest logit/score. This is because a Top-1 node has been inserted at the end of the model, which is implemented with a "LabelSelect" node in the accelerator.