Compiler strategy for reconfiguring AIE designs with control packets

[erwei-xilinx]

Currently, the protytpe in #1728 demonstrates a control packet-based reconfiguration strategy that roughly follows the following workflow:

1. aie.mlir (with an overlay of ctrl packet flows as part of it) -> (aiecc.py)-> txn_binary.bin ->(txn2mlir.py)-> aie.control_packet ops -> (mlir transformation pass, to be committed)-> aiex.npu.dma_memcpy_nd ops (mlir1)
2. ... aie.control_packet ops -> (aie-translate) -> ctrl_pkts.bin
3. "Base" mlir with control packet flows only + mlir1 -> (xrt loading ctrl_pkts.bin in DDR) -> design reconfigured on AIE

While this prototype shows a functional reconfiguration workflow, the flow contains redundancies. Would love to collect opinions on how we could improve the reconfiguration workflow, to make it work end to end.