From e5c14bbd97e0c05fc7fd11156f37836573b9a283 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sat, 20 Jan 2024 19:31:16 +1000 Subject: [PATCH] Properly handle external 9C clock pins The GW1NR-9C has interesting clock pins on the bottom side - they do not connect directly to the central MUX, but pass through an additional MUX in the corner cell. Let's take this into account. Signed-off-by: YRabbit --- Makefile | 6 +++--- apycula/chipdb.py | 16 ++++++++++++++-- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 0f565318..1f718f2a 100644 --- a/Makefile +++ b/Makefile @@ -18,6 +18,6 @@ apycula/%.pickle: %_stage2.pickle gzip -c $< > $@ clean: - rm *.json - rm *.pickle - rm apycula/*.pickle + rm -f *.json + rm -f *.pickle + rm -f apycula/*.pickle diff --git a/apycula/chipdb.py b/apycula/chipdb.py index 4a657a4e..ccb0b3f8 100644 --- a/apycula/chipdb.py +++ b/apycula/chipdb.py @@ -1293,8 +1293,20 @@ def fse_create_clocks(dev, device, dat: Datfile, fse): # find center muxes for clk_idx, row, col, wire_idx in {(i, dat.cmux_ins[i - 80][0] - 1, dat.cmux_ins[i - 80][1] - 1, dat.cmux_ins[i - 80][2]) for i in range(clknumbers['PCLKT0'], clknumbers['PCLKR1'] + 1)}: if row != -2: - add_node(dev, clknames[clk_idx], "GLOBAL_CLK", row, col, wirenames[wire_idx]) - add_buf_bel(dev, row, col, wirenames[wire_idx]) + # XXX GW1NR-9C has an interesting feature not found in any other + # chip - the external pins for the clock are connected to the + # central clock MUX not directly, but through auxiliary wires that + # lead to the corner cells and only there the connection occurs. + if device == 'GW1N-9C' and row == dev.rows - 1: + add_node(dev, f'{clknames[clk_idx]}-9C', "GLOBAL_CLK", row, col, wirenames[wire_idx]) + if clknames[clk_idx][-1] == '1': + add_node(dev, f'{clknames[clk_idx]}-9C', "GLOBAL_CLK", row, dev.cols - 1, 'LWT6') + else: + add_node(dev, f'{clknames[clk_idx]}-9C', "GLOBAL_CLK", row, 0, 'LWT6') + else: + add_node(dev, clknames[clk_idx], "GLOBAL_CLK", row, col, wirenames[wire_idx]) + add_buf_bel(dev, row, col, wirenames[wire_idx]) + spines = {f'SPINE{i}' for i in range(32)} for row, rd in enumerate(dev.grid):