From af2975e67057763e3e0905e92614c9d13266a252 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Thu, 12 Sep 2024 08:29:32 +1000 Subject: [PATCH] HCLK. Add delays Optimistic delays for now, pending future revision. Signed-off-by: YRabbit --- apycula/chipdb.py | 2 ++ apycula/gowin_pack.py | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/apycula/chipdb.py b/apycula/chipdb.py index 7c7617d..734c035 100644 --- a/apycula/chipdb.py +++ b/apycula/chipdb.py @@ -3576,6 +3576,8 @@ def fse_wire_delays(db): db.wire_delay[clknames[i]] = "CENT_SPINE_PCLK" for i in range(129, 153): # clock inputs (logic->clock) db.wire_delay[clknames[i]] = "CENT_SPINE_PCLK" + for i in range(1000, 1010): # HCLK + db.wire_delay[clknames[i]] = "X0" # XXX # assign pads with plls # for now use static table and store the bel name although it is always PLL without a number diff --git a/apycula/gowin_pack.py b/apycula/gowin_pack.py index 4b2ceea..05fd1b2 100644 --- a/apycula/gowin_pack.py +++ b/apycula/gowin_pack.py @@ -2022,7 +2022,7 @@ def set_fuse(): if side == 'L': col = 0 else: - col = db.col - 1 + col = db.cols - 1 for row in range(db.rows): set_fuse()