From 74d7ebc71f50e1722ade8f2129b5768b01d2fa31 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sat, 28 Oct 2023 17:10:42 +0200 Subject: [PATCH] clangformat Signed-off-by: gatecat --- common/place/placer_static.cc | 33 +++++++++++++++++---------------- machxo2/arch.cc | 28 +++++++++++----------------- machxo2/arch.h | 4 ++-- 3 files changed, 30 insertions(+), 35 deletions(-) diff --git a/common/place/placer_static.cc b/common/place/placer_static.cc index 3e105e4708..729785bb34 100644 --- a/common/place/placer_static.cc +++ b/common/place/placer_static.cc @@ -551,7 +551,7 @@ class StaticPlacer g.overlap /= std::max(1.0f, total_area); if (!overlap_str.empty()) overlap_str += ", "; - overlap_str += stringf("%s=%.1f%%", cfg.cell_groups.at(idx).name.c_str(ctx), g.overlap*100); + overlap_str += stringf("%s=%.1f%%", cfg.cell_groups.at(idx).name.c_str(ctx), g.overlap * 100); g.conc_density.write_csv(stringf("out_conc_density_%d_%d.csv", iter, idx)); } log_info("overlap: %s\n", overlap_str.c_str()); @@ -896,7 +896,7 @@ class StaticPlacer for (int c : macro.conc_cells) { auto &cc = ccells.at(c); auto &mc = mcells.at(c); - mc.pos = mc.pos * (1-alpha) + (pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha; + mc.pos = mc.pos * (1 - alpha) + (pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha; mc.ref_pos = mc.ref_pos * (1 - alpha) + (ref_pos + RealPair(cc.chunk_dx, cc.chunk_dy)) * alpha; } } @@ -927,7 +927,8 @@ class StaticPlacer compute_overlap(); } - void legalise_step(bool dsp_bram) { + void legalise_step(bool dsp_bram) + { // assume DSP and BRAM are all groups 2+ for now for (int i = 0; i < int(ccells.size()); i++) { auto &mc = mcells.at(i); @@ -937,7 +938,7 @@ class StaticPlacer if (!dsp_bram && mc.group >= 2) continue; if (cc.macro_idx != -1 && i != macros.at(cc.macro_idx).root->udata) - continue; // not macro root + continue; // not macro root if (mc.is_fixed) { // already placed NPNR_ASSERT(cc.base_cell->bel != BelId()); continue; @@ -959,7 +960,8 @@ class StaticPlacer log_info("HPWL after legalise: %f (delta: %f)\n", post_hpwl, post_hpwl - pre_hpwl); } - void enqueue_legalise(int cell_idx) { + void enqueue_legalise(int cell_idx) + { NPNR_ASSERT(cell_idx < int(ccells.size())); // we should never be legalising spacers or dark nodes auto &ccell = ccells.at(cell_idx); if (ccell.macro_idx != -1) { @@ -971,7 +973,8 @@ class StaticPlacer } } - void enqueue_legalise(CellInfo *ci) { + void enqueue_legalise(CellInfo *ci) + { if (ci->udata != -1) { // managed by static enqueue_legalise(ci->udata); @@ -1011,7 +1014,7 @@ class StaticPlacer total_iters_noreset++; if (total_iters > int(ccells.size())) { total_iters = 0; - ripup_radius = std::max(std::max(width+1, height+1), ripup_radius * 2); + ripup_radius = std::max(std::max(width + 1, height + 1), ripup_radius * 2); } if (total_iters_noreset > std::max(5000, 8 * int(ctx->cells.size()))) { @@ -1039,23 +1042,21 @@ class StaticPlacer iter_at_radius++; if (iter >= (10 * (radius + 1))) { // No luck yet, increase radius - radius = std::min(std::max(width+1, height+1), radius + 1); - while (radius < std::max(width+1, height+1)) { + radius = std::min(std::max(width + 1, height + 1), radius + 1); + while (radius < std::max(width + 1, height + 1)) { // Keep increasing the radius until it will actually increase the number of cells we are // checking (e.g. BRAM and DSP will not be in all cols/rows), so we don't waste effort - for (int x = std::max(0, cx - radius); - x <= std::min(width+1, cx + radius); x++) { + for (int x = std::max(0, cx - radius); x <= std::min(width + 1, cx + radius); x++) { if (x >= int(fb->size())) break; - for (int y = std::max(0, cy - radius); - y <= std::min(height+1, cy + radius); y++) { + for (int y = std::max(0, cy - radius); y <= std::min(height + 1, cy + radius); y++) { if (y >= int(fb->at(x).size())) break; if (fb->at(x).at(y).size() > 0) goto notempty; } } - radius = std::min(std::max(width+1, height+1), radius + 1); + radius = std::min(std::max(width + 1, height + 1), radius + 1); } notempty: iter_at_radius = 0; @@ -1063,9 +1064,9 @@ class StaticPlacer } // If our randomly chosen cooridnate is out of bounds; or points to a tile with no relevant bels; ignore // it - if (nx < 0 || nx > width+1) + if (nx < 0 || nx > width + 1) continue; - if (ny < 0 || ny > height+1) + if (ny < 0 || ny > height + 1) continue; if (nx >= int(fb->size())) diff --git a/machxo2/arch.cc b/machxo2/arch.cc index 17d56f96f3..f31de2a768 100644 --- a/machxo2/arch.cc +++ b/machxo2/arch.cc @@ -49,8 +49,8 @@ void IdString::initialize_arch(const BaseCtx *ctx) // --------------------------------------------------------------- static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info, - const SpeedGradePOD **speed_grade, - const char **device_name, const char **package_name, int *device_speed) + const SpeedGradePOD **speed_grade, const char **device_name, const char **package_name, + int *device_speed) { std::stringstream ss(available_devices); std::string name; @@ -381,14 +381,11 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const auto phys_wire = getPipSrcWire(*(getPipsUphill(w).begin())); return std::make_pair(int(phys_wire.location.x), int(phys_wire.location.y)); } else if (wire.bel_pins.size() > 0) { - return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, - wire.bel_pins[0].rel_bel_loc.y); + return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, wire.bel_pins[0].rel_bel_loc.y); } else if (wire.pips_downhill.size() > 0) { - return std::make_pair(wire.pips_downhill[0].rel_loc.x, - wire.pips_downhill[0].rel_loc.y); + return std::make_pair(wire.pips_downhill[0].rel_loc.x, wire.pips_downhill[0].rel_loc.y); } else if (wire.pips_uphill.size() > 0) { - return std::make_pair(wire.pips_uphill[0].rel_loc.x, - wire.pips_uphill[0].rel_loc.y); + return std::make_pair(wire.pips_uphill[0].rel_loc.x, wire.pips_uphill[0].rel_loc.y); } else { return std::make_pair(int(w.location.x), int(w.location.y)); } @@ -430,14 +427,11 @@ BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const auto phys_wire = getPipSrcWire(*(getPipsUphill(w).begin())); return std::make_pair(int(phys_wire.location.x), int(phys_wire.location.y)); } else if (wire.bel_pins.size() > 0) { - return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, - wire.bel_pins[0].rel_bel_loc.y); + return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, wire.bel_pins[0].rel_bel_loc.y); } else if (wire.pips_downhill.size() > 0) { - return std::make_pair(wire.pips_downhill[0].rel_loc.x, - wire.pips_downhill[0].rel_loc.y); + return std::make_pair(wire.pips_downhill[0].rel_loc.x, wire.pips_downhill[0].rel_loc.y); } else if (wire.pips_uphill.size() > 0) { - return std::make_pair(wire.pips_uphill[0].rel_loc.x, - wire.pips_uphill[0].rel_loc.y); + return std::make_pair(wire.pips_uphill[0].rel_loc.x, wire.pips_uphill[0].rel_loc.y); } else { return std::make_pair(int(w.location.x), int(w.location.y)); } @@ -781,7 +775,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_IGNORE; } else if (cell->type.in(id_SEDFA, id_GSR, id_JTAGF)) { return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT; - } else if (cell->type.in(id_OSCH,id_OSCJ)) { + } else if (cell->type.in(id_OSCH, id_OSCJ)) { if (port == id_OSC) return TMG_GEN_CLOCK; else @@ -851,8 +845,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port if (cell->ramInfo.is_pdp) { bool is_output = cell->ports.at(port).type == PORT_OUT; // In PDP mode, all read signals are in CLKB domain and write signals in CLKA domain - if (is_output || port.in(id_OCEB, id_CEB, id_ADB5, id_ADB6, id_ADB7, id_ADB8, id_ADB9, id_ADB10, id_ADB11, - id_ADB12)) + if (is_output || + port.in(id_OCEB, id_CEB, id_ADB5, id_ADB6, id_ADB7, id_ADB8, id_ADB9, id_ADB10, id_ADB11, id_ADB12)) info.clock_port = id_CLKB; else info.clock_port = id_CLKA; diff --git a/machxo2/arch.h b/machxo2/arch.h index a8172b8fac..45233586ed 100644 --- a/machxo2/arch.h +++ b/machxo2/arch.h @@ -157,8 +157,8 @@ NPNR_PACKED_STRUCT(struct PackageSupportedPOD { NPNR_PACKED_STRUCT(struct SuffixeSupportedPOD { RelPtr suffix; }); -NPNR_PACKED_STRUCT(struct SpeedSupportedPOD { - int16_t speed; +NPNR_PACKED_STRUCT(struct SpeedSupportedPOD { + int16_t speed; int16_t index; });