Any way/hints to debug ABC pass?

[SergiiDmytruk]

The problem

The issue is that before abc command, there is this assignment:

assign \lpc_periph_inst.interrupt  = _1079_ &(* src = "TwPM_Top.v:143.15-165.4|verilog-tpm-fifo-registers/regs_module.v:484.22-486.46" *)  _1092_;

which is gone after running:

abc -script +read_lut,/opt/f4pga/eos-s3/conda/envs/eos-s3/share/yosys/quicklogic/pp3/lutdefs.txt;strash;ifraig;scorr;dc2;dretime;strash;dch,-f;if;mfs2;sweep;eliminate;if;mfs;lutpack;dress

At the end, .synth_v contains constant assignment:

assign \lpc_periph_inst.interrupt  = 1'h0;

The result is obviously wrong, but how to trace what's going on? There are some warnings during synthesis, but they don't seem too related and the reduced version below has only limited number of them:

Warning: Yosys has only limited support for tri-state logic at the moment. (tmp.v:45)
Warning: Complex async reset for dff `\Q'.
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
Warnings: 2 unique messages, 2 total

Code

The full code is here, I shortened it via delta down to 46 lines (the behaviour seems consistent with the original issue):

reduced.v

module TwPM_Top (LCLK, LRESET, LAD, SERIRQ);
  input         LCLK;
  input         LRESET;
  inout   [3:0] LAD;
  inout         SERIRQ;
  wire    [7:0] data_lpc2dp;
  wire          interrupt;
  lpc_periph lpc_periph_inst (
      .clk_i(LCLK),
      .nrst_i(LRESET),
      .lad_bus(LAD),
      .serirq(SERIRQ),
      .lpc_data_o(data_lpc2dp),
      .interrupt(interrupt)
  );
  assign interrupt = data_lpc2dp[7] & |data_lpc2dp[3:0];
endmodule
module lpc_periph (clk_i, nrst_i, lad_bus, serirq, lpc_data_o, interrupt);
  input  wire        clk_i;        // LPC clock
  input  wire        nrst_i;       // LPC reset (active low)
  inout  wire [ 3:0] lad_bus;      // LPC data bus
  inout  wire        serirq;       // LPC SERIRQ signal
  output reg  [ 7:0] lpc_data_o;   // Data received (I/O Write) from host
  input  wire        interrupt;    // Whether interrupt should be signaled to host, active high
  reg        driving_serirq = 0;   // Enable signal for driving SERIRQ by LPC module
  reg [ 3:0] irq_num_reg = 0;      // IRQ number, latched on SERIRQ start frame
  reg        serirq_reg = 1;       // Value driven on SERIRQ, if enabled
  always @(negedge nrst_i or posedge clk_i) begin : serirq_drive
    integer    serirq_counter;
    if (nrst_i) begin
      if (interrupt) begin
        driving_serirq <= 1;
      end
      if (serirq_counter == irq_num_reg * 3 + 1 && driving_serirq) begin
        driving_serirq <= 0; // Turn-around
      end
      lpc_data_o[3:0]   <= lad_bus;
      lpc_data_o[7:4]   <= lad_bus;
    end else begin
      serirq_counter <= 0;
      serirq_reg     <= 1;
      driving_serirq <= 0;
    end
  end
  assign serirq = driving_serirq ? serirq_reg : 1'bz;
endmodule

Any thoughts?

Is it limited support of tri-state logic in yosys? Is there a way to debug what and why ABC does other than running it under gdb or adding logs myself?

[whitequark]

Generally speaking, tri-states are not synthesizable. If I recall correctly, tribuf -formal can help with your particular use case by converting tri-state nets to normal logic.

[SergiiDmytruk]

I forgot to add a script used for the synthesis, it actually contains the opposite: tribuf -logic. The idea here is to connect FPGA to LPC header on a motherboard and LPC lanes require tri-state, so we can't multiplex those wires implicitly or explicitly.

I've done a bit of reading after seeing your answer. Do I get it right that this can work only if FPGA model has a dedicated block of tri-state I/O ports which will be exposed separately to Verilog (IOBUF)? It looks like EOS S3 doesn't have any, so we'll just need to find something more suitable for our needs in this case.

[whitequark]

You can have tri-states at the boundary of the FPGA, and essentially every FPGA has the ability to do so.

But you cannot have tri-states inside of the FPGA, between two of the modules you synthesize.

[SergiiDmytruk]

Thank you.

[krystian-hebel]

This has nothing to do with tri-states, the signal in question is lost even without it. I simplified that code further:

• no tri-states, only simple inputs and outputs
• data_lpc2dp narrowed to 4 bits (same as LAD) to get rid of some aliases that can be confusing
• no reduction operator - I thought it may be the cause but result is the same
• got rid of integer counter and conditional branch that depended on it - didn't work in the first place as counter was not increased
• changed serirq to reg and set its value directly

reduced_more.v

module TwPM_Top (LCLK, LRESET, LAD, SERIRQ);
  input         LCLK;
  input         LRESET;
  input   [3:0] LAD;
  output        SERIRQ;
  wire    [3:0] data_lpc2dp;
  wire          interrupt;
  lpc_periph lpc_periph_inst (
      .clk_i(LCLK),
      .nrst_i(LRESET),
      .lad_bus(LAD),
      .serirq(SERIRQ),
      .lpc_data_o(data_lpc2dp),
      .interrupt(interrupt)
  );
  assign interrupt = data_lpc2dp[3] & (data_lpc2dp[1] | data_lpc2dp[0]);
endmodule
module lpc_periph (clk_i, nrst_i, lad_bus, serirq, lpc_data_o, interrupt);
  input  wire        clk_i;        // LPC clock
  input  wire        nrst_i;       // LPC reset (active low)
  input  wire [ 3:0] lad_bus;      // LPC data bus
  output reg         serirq;       // LPC SERIRQ signal
  output reg  [ 3:0] lpc_data_o;   // Data received (I/O Write) from host
  input  wire        interrupt;    // Whether interrupt should be signaled to host, active high
  always @(negedge nrst_i or posedge clk_i) begin : serirq_drive
    if (nrst_i) begin
      if (interrupt) begin
        serirq <= 1;
      end
      lpc_data_o[3:0]   <= lad_bus;
    end else begin
      serirq <= 0;
    end
  end
endmodule

This is the script used to produce erroneous results (using qorc-sdk so some paths and file names of libraries and techmaps may be different), it should be the same as synth_quicklogic up to the point of invoking ABC:

abc.ys

read_verilog -lib -specify +/quicklogic/pp3_cells_sim.v +/quicklogic/pp3_cells_map.v
read_verilog reduced_more.v

hierarchy -check -top TwPM_Top
proc
flatten
tribuf -logic
opt_expr
opt_clean
deminout
opt

opt_expr
opt_clean
check
opt
wreduce -keepdc
peepopt
pmuxtree
opt_clean
alumacc
opt
fsm
opt -fast
memory -nomap
opt_clean

memory_bram -rules +/quicklogic/pp3_brams.txt
pp3_braminit
techmap -map +/quicklogic/pp3_brams_map.v

opt -fast -mux_undef -undriven -fine
memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block -attr syn_ramstyle=auto -attr syn_ramstyle=registers -attr syn_romstyle=auto -attr syn_romstyle=logic
opt -undriven -fine

techmap
opt -fast
muxcover -mux8 -mux4

opt_expr -clkinv
dff2dffe
techmap -map +/quicklogic/pp3_ffs_map.v
opt_expr -mux_undef
simplemap

techmap -map +/quicklogic/pp3_latches_map.v

write_verilog before.v

abc -script +read_lut,/home/qorc-sdk/qorc-sdk/fpga_toolchain_install/v1.3.1/conda/share/yosys/quicklogic/pp3_lutdefs.txt;strash;ifraig;scorr;dc2;dretime;strash;dch,-f;if;mfs2;sweep;eliminate;if;mfs;lutpack;dress

write_verilog after.v

This produces two verilog files, immediately before abc is invoked and immediately after. Signals contributing to final \lpc_periph_inst.interrupt look reasonable before abc:

  (* src = "reduced.v:7.17-7.26" *)
  wire interrupt;
  (...)
  (* hdlname = "lpc_periph_inst interrupt" *)
  (* src = "reduced.v:8.14-15.4|reduced.v:24.22-24.31" *)
  wire \lpc_periph_inst.interrupt ;
  (...)
  assign _06_ = \lpc_periph_inst.lpc_data_o [1] |(* src = "reduced.v:16.41-16.73" *)  \lpc_periph_inst.lpc_data_o [0];
  assign \lpc_periph_inst.interrupt  = \lpc_periph_inst.lpc_data_o [3] &(* src = "reduced.v:16.22-16.74" *)  _06_;
  (...)
  assign interrupt = \lpc_periph_inst.interrupt ;

However, after abc \lpc_periph_inst.interrupt is no longer driven, neither by assign nor as an output of FF or any other logic element:

  (* src = "reduced.v:7.17-7.26" *)
  wire interrupt;
  (...)
  (* hdlname = "lpc_periph_inst interrupt" *)
  (* src = "reduced.v:8.14-15.4|reduced.v:24.22-24.31" *)
  wire \lpc_periph_inst.interrupt ;
  (...)
  assign interrupt = \lpc_periph_inst.interrupt ;

As the signal at this point has no driver, it would be simplified to constant 0 by further steps performed by synth_quicklogic.

By changing interrupt assignment in reduced_more.v to something simpler like assign interrupt = data_lpc2dp[3]; I can make it stay properly assigned in after.v: assign \lpc_periph_inst.interrupt = \lpc_periph_inst.lpc_data_o [3];. This obviously changes the logic implemented by the code so it is a no-go. Even in this case I get the network is combinational warning from ABC.