Is there a warning for assigning to narrower bus?

[MrJake222]

So I can avoid this in the future:

wire [7:0] ram_do;
wire [7:0] rom_do;
wire mem_do = ram_do | rom_do;

[KrystalDelusion]

There is a warning if you use the verific parser, however the standard verilog parser is very limited and it is recommended to use something like Icarus Verilog for checking syntax.

[MrJake222]

Thank you for this! I've added Icarus Verilog to my Makefile.

[nakengelhardt]

We don't warn for this because it's incredibly common to do in normal, correct code, and there's no way to differentiate this case from this one:

reg [7:0] counter;
always @(posedge clk) counter <= counter + 1;

With other tools that do produce warnings it just leads to people ignoring all warnings. In fact, I'm currently advocating for turning this message into not a warning by default with the verific frontend too: #4324