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enet.txt
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enet.txt
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################################################################################
##
## Filename: enet.txt
## {{{
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
##
## Purpose:
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
################################################################################
##
## }}}
## Be able to support 2^14, or 16384 byte packets
@$LGPKTBUFSZB=14
##
@PREFIX=netb
@$LGBUFSZ=@$(/LGPKTBUFSZB)
@$MEMORY_ADDRESS_WIDTH=@$(LGBUFSZ)
@$NADDR=(1<<@$MEMORY_ADDRESS_WIDTH)/2
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb
@MAIN.INSERT=
`ifndef ETHERNET_ACCESS
// Ethernet packet memory declaration
//
// The only time this needs to be defined is when the ethernet module
// itself isnt defined. Otherwise, the access is accomplished by the
// ethernet module
memdev #(@$(MEMORY_ADDRESS_WIDTH))
enet_buffers(i_clk,
@$(SLAVE.PORTLIST));
`else
// These don't need to be defined here, and indeed should not be defined here
// lest their definitions override those of the netb interface defined in the
// enetpackets module
//
// assign @$(SLAVE.PREFIX)_ack = 1'b0;
// assign @$(SLAVE.PREFIX)_stall = 1'b0;
// assign @$(SLAVE.PREFIX)_data = @$(netp.SLAVE.PREFIX)_data;
`endif
@REGS.N=2
@REGS.0= 0 R_NET_RXBUF NETRXB
@$TXREG=(1<< @$(MEMORY_ADDRESS_WIDTH))/4
@REGS.1= @$(TXREG) R_NET_TXBUF NETTXB
@BDEF.IONAME=_netb
@BDEF.OSDEF=_BOARD_HAS_ENETB
@BDEF.OSVAL=
static volatile unsigned *const @$(BDEF.IONAME)rx = ((unsigned *)@$[0x%08x](REGBASE));
static volatile unsigned *const @$(BDEF.IONAME)tx = ((unsigned *)(@$[0x%08x](REGBASE) + (@$[0x%04x](NADDR)<<1)));
##
##
##
@PREFIX=netp
@DEVID=ETHERNET
@ACCESS=@$(DEVID)_ACCESS
@$LGBUFSZ=@$(/LGPKTBUFSZB)
@INT.NETRX.WIRE=netrx_int
@INT.NETTX.WIRE=nettx_int
@INT.NETRX.PIC=syspic
@INT.NETTX.PIC=syspic
@NADDR=8
@SLAVE.TYPE=DOUBLE
@SLAVE.BUS=wb
@TOP.PORTLIST=
// Ethernet control (packets) lines
o_net_reset_n,
// eth_int_b // Interrupt, leave floating
// eth_pme_b // Power management event, leave floating
i_net_rx_clk, i_net_rx_ctl, i_net_rxd,
o_net_tx_clk, o_net_tx_ctl, o_net_txd
@TOP.IODECL=
// Ethernet (RGMII) port wires
output wire o_net_reset_n;
input wire i_net_rx_clk, i_net_rx_ctl;
input wire [3:0] i_net_rxd;
output wire o_net_tx_clk, o_net_tx_ctl;
output wire [3:0] o_net_txd;
@TOP.DEFNS=
// Ethernet (RGMII) port wires
wire [7:0] w_net_rxd, w_net_txd;
wire w_net_rxdv, w_net_rxerr,
w_net_txctl;
wire [1:0] w_net_tx_clk;
@TOP.MAIN=
// Ethernet (RGMII) connections
o_net_reset_n,
i_net_rx_clk, w_net_rxdv, w_net_rxdv ^ w_net_rxerr, w_net_rxd,
w_net_tx_clk, w_net_txctl, w_net_txd
@TOP.INSERT=
xiddr rx0(i_net_rx_clk, i_net_rxd[0], { w_net_rxd[4], w_net_rxd[0] });
xiddr rx1(i_net_rx_clk, i_net_rxd[1], { w_net_rxd[5], w_net_rxd[1] });
xiddr rx2(i_net_rx_clk, i_net_rxd[2], { w_net_rxd[6], w_net_rxd[2] });
xiddr rx3(i_net_rx_clk, i_net_rxd[3], { w_net_rxd[7], w_net_rxd[3] });
xiddr rxc(i_net_rx_clk, i_net_rx_ctl, { w_net_rxdv, w_net_rxerr });
xoddr tx0(s_clk_125mhz, { w_net_txd[0], w_net_txd[4] }, o_net_txd[0]);
xoddr tx1(s_clk_125mhz, { w_net_txd[1], w_net_txd[5] }, o_net_txd[1]);
xoddr tx2(s_clk_125mhz, { w_net_txd[2], w_net_txd[6] }, o_net_txd[2]);
xoddr tx3(s_clk_125mhz, { w_net_txd[3], w_net_txd[7] }, o_net_txd[3]);
xoddr txc(s_clk_125mhz, { w_net_txctl, w_net_txctl }, o_net_tx_ctl);
xoddr txck(s_clk_125d,{w_net_tx_clk[1],w_net_tx_clk[0]},o_net_tx_clk);
@MAIN.PORTLIST=
// Ethernet control (packets) lines
o_net_reset_n,
// eth_int_b // Interrupt, leave floating
// eth_pme_b // Power management event, leave floating
i_net_rx_clk, i_net_rx_dv, i_net_rx_err, i_net_rxd,
o_net_tx_clk, o_net_tx_ctl, o_net_txd
@MAIN.IODECL=
// Ethernet (RGMII) control
output wire o_net_reset_n;
input wire i_net_rx_clk, i_net_rx_dv, i_net_rx_err;
input wire [7:0] i_net_rxd;
output wire [1:0] o_net_tx_clk;
output wire o_net_tx_ctl;
output wire [7:0] o_net_txd;
@MAIN.DEFNS=
//
wire netp_debug_clk;
wire [31:0] netp_debug;
@MAWB= @$(netb.MEMORY_ADDRESS_WIDTH)
@MAIN.INSERT=
enetpackets #(.MEMORY_ADDRESS_WIDTH(@$(MAWB)))
netctrl(i_clk, i_reset,
@$(netb.SLAVE.PORTLIST),
@$(SLAVE.PORTLIST),
o_net_reset_n,
i_net_rx_clk, i_net_rx_dv, i_net_rx_err, i_net_rxd,
i_clk_125mhz, o_net_tx_clk, o_net_tx_ctl, o_net_txd,
netrx_int, nettx_int, netp_debug_clk, netp_debug);
@REGS.N=8
@REGS.0= 0 R_NET_RXCMD RXCMD,NETRX
@REGS.1= 1 R_NET_TXCMD TXCMD,NETTX
@REGS.2= 2 R_NET_MACHI MACHI
@REGS.3= 3 R_NET_MACLO MACLO
@REGS.4= 4 R_NET_RXMISS NETMISS
@REGS.5= 5 R_NET_RXERR NETERR
@REGS.6= 6 R_NET_RXCRC NETCRCER
@REGS.7= 7 R_NET_TXCOL NETCOL
@REGDEFS.H.INSERT=
// Network packet interface
#define ENET_TXGO 0x004000
#define ENET_TXBUSY 0x004000
#define ENET_NOHWCRC 0x008000
#define ENET_NOHWMAC 0x010000
#define ENET_RESET 0x020000
#define ENET_NOHWIPCHK 0x040000
#define ENET_TXCMD(LEN) ((LEN)|ENET_TXGO)
#define ENET_TXCLR 0x038000
#define ENET_TXCANCEL 0x000000
#define ENET_RXAVAIL 0x004000
#define ENET_RXBUSY 0x008000
#define ENET_RXMISS 0x010000
#define ENET_RXERR 0x020000
#define ENET_RXCRC 0x040000 // Set on a CRC error
#define ENET_RXLEN rxcmd & 0x0ffff
#define ENET_RXCLR 0x004000
#define ENET_RXBROADCAST 0x080000
#define ENET_RXCLRERR 0x078000
@BDEF.DEFN=
// Network packet interface
#define ENET_TXGO 0x004000
#define ENET_TXBUSY 0x004000
#define ENET_NOHWCRC 0x008000
#define ENET_NOHWMAC 0x010000
#define ENET_RESET 0x020000
#define ENET_NOHWIPCHK 0x040000
#define ENET_TXCMD(LEN) ((LEN)|ENET_TXGO)
#define ENET_TXCLR 0x038000
#define ENET_TXCANCEL 0x000000
#define ENET_RXAVAIL 0x004000
#define ENET_RXBUSY 0x008000
#define ENET_RXMISS 0x010000
#define ENET_RXERR 0x020000
#define ENET_RXCRC 0x040000 // Set on a CRC error
#define ENET_RXLEN rxcmd & 0x0ffff
#define ENET_RXCLR 0x004000
#define ENET_RXBROADCAST 0x080000
#define ENET_RXCLRERR 0x078000
#define ENET_TXBUFLN(NET) (1<<(NET.txcmd>>24))
#define ENET_RXBUFLN(NET) (1<<(NET.rxcmd>>24))
typedef struct ENETPACKET_S {
unsigned n_rxcmd, n_txcmd;
unsigned long n_mac;
unsigned n_rxmiss, n_rxerr, n_rxcrc, n_txcol;
} ENETPACKET;
#define SYSINT_ENETRX SYSINT(@$(INT.NETRX.syspic.ID))
#define SYSINT_ENETTX SYSINT(@$(INT.NETTX.syspic.ID))
@SIM.CLOCK=net_rx_clk
@SIM.TICK=
m_core->i_net_rx_dv = m_core->o_net_tx_ctl;
m_core->i_net_rx_err = 0;
m_core->i_net_rxd = m_core->o_net_txd;
@BDEF.IONAME=io_enet
@BDEF.IOTYPE=ENETPACKET
@BDEF.OSDEF=_BOARD_HAS_ENETP
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const _netp = ((ENETPACKET *)@$[0x%08x](REGBASE));
@RTL.MAKE.GROUP=ENET
@RTL.MAKE.SUBD=ethernet
@RTL.MAKE.FILES= enetpackets.v
addecrc.v addemac.v addepad.v addepreamble.v
rxecrc.v rxehwmac.v rxeipchk.v rxemin.v rxepreambl.v rxewrite.v
xiddr.v xoddr.v txespeed.v txeaddr.v
@CLOCK.NAME=net_rx_clk
@$CLOCK.FREQUENCY=125000000
@XDC.INSERT=
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/tx*}] -to [get_cells -hier -filter {NAME=~*netctrl/n_tx*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/hw_mac*}] -to [get_cells -hier -filter {NAME=~*netctrl/txmaci/r_hw*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/tfrtxspd/r_aval*}] -to [get_cells -hier -filter {NAME=~*netctrl/tfrtxspd/r_val*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/config_hw_mac*}] -to [get_cells -hier -filter {NAME=~*netctrl/n_tx_config_hw_mac*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/config_hw_crc*}] -to [get_cells -hier -filter {NAME=~*netctrl/n_tx_config_hw_crc*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/tfrtxspd/r_*}] -to [get_cells -hier -filter {NAME=~*netctrl/tfrtxspd/q_*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/tx_cmd*}] -to [get_cells -hier -filter {NAME=~*netctrl/r_tx_cmd*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/tx_cancel*}] -to [get_cells -hier -filter {NAME=~*netctrl/r_tx_cancel*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/n_still_busy*}] -to [get_cells -hier -filter {NAME=~*netctrl/r_tx_busy*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *netctrl/txspdi/o_ck*}] -to [get_cells -hier -filter {NAME=~*txck/ODDRi*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *o_sys_reset*}] -to [get_cells -hier -filter {NAME=~*netctrl/q_tx_reset*}] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *o_sys_reset*}] -to [get_cells -hier -filter {NAME=~*netctrl/q_rx_reset*}] 8.0
#