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mdio.txt
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mdio.txt
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################################################################################
##
## Filename: mdio.txt
## {{{
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
##
## Purpose: This file describes how the network MDIO core is to be
## connected to the rest of the design, for use by the autofpga
## program.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
################################################################################
##
## }}}
@PREFIX=mdio
@NADDR=32
@ACCESS=NETCTRL_ACCESS
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb
@TOP.PORTLIST=
// Toplevel ethernet MDIO ports
o_eth_mdclk, io_eth_mdio
@TOP.IODECL=
// Ethernet control (MDIO)
output wire o_eth_mdclk;
inout wire io_eth_mdio;
@TOP.DEFNS=
// Ethernet control (MDIO)
wire w_mdio, w_mdwe;
@TOP.MAIN=
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio
@TOP.INSERT=
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
@MAIN.PORTLIST=
// The ethernet MDIO wires
o_mdclk, o_mdio, o_mdwe, i_mdio
@MAIN.IODECL=
// Ethernet control (MDIO)
output wire o_mdclk, o_mdio, o_mdwe;
input wire i_mdio;
@MAIN.INSERT=
// Verilator lint_off UNUSED
wire[31:0] mdio_debug;
// Verilator lint_on UNUSED
enetctrl #(2)
mdio(i_clk, i_reset, @$(SLAVE.PORTLIST),
o_mdclk, o_mdio, i_mdio, o_mdwe, mdio_debug);
@MAIN.ALT=
assign o_mdclk = 1'b1;
assign o_mdio = 1'b1;
assign o_mdwe = 1'b0;
@REGS.NOTE= // Ethernet configuration (MDIO) port
@REGS.N=30
@REGS.0= 0 R_MDIO_BMCR BMCR
@REGS.1= 1 R_MDIO_BMSR BMSR
@REGS.2= 2 R_MDIO_PHYIDR1 PHYIDR1
@REGS.3= 3 R_MDIO_PHYIDR2 PHYIDR2
@REGS.4= 4 R_MDIO_ANAR ANAR
@REGS.5= 5 R_MDIO_ANLPAR ANLPAR
@REGS.6= 6 R_MDIO_ANER ANER
@REGS.7= 7 R_MDIO_ANNPTR ANNPTR
@REGS.8= 8 R_MDIO_ANNPRR ANNPRR
@REGS.9= 9 R_MDIO_GBCR GBCR
@REGS.10= 10 R_MDIO_GBSR GBSR
@REGS.11= 13 R_MDIO_MACR MACR
@REGS.12= 14 R_MDIO_MAADR MAADR
@REGS.13= 15 R_MDIO_GBESR GBESR
@REGS.14= 16 R_MDIO_PHYCR PHYCR
@REGS.15= 17 R_MDIO_PHYSR PHYSR
@REGS.16= 18 R_MDIO_INER INER
@REGS.17= 19 R_MDIO_INSR INSR
## 20-23 are reserved
@REGS.18=24 R_MDIO_RXERC RXERC
## 25-26 are reserved
@REGS.19=27 R_MDIO_LDPSR LDPSR
@REGS.20=30 R_MDIO_EPAGSR EPAGSR
@REGS.21=31 R_MDIO_PAGSEL PAGSEL
##
@REGS.22=0 R_XMDIO_PC1R XPC1R
@REGS.23=1 R_XMDIO_PS1R XPS1R
@REGS.24=20 R_XMDIO_EEECR XEEECR
@REGS.25=16 R_XMDIO_EEEWER XEEEWER
@REGS.26=60 R_XMDIO_EEEAR XEEEAR
@REGS.27=61 R_XMDIO_EEELPAR XEEELPAR
@REGS.28=26 R_XMDIO_LACR XLACR
@REGS.29=28 R_XMDIO_LCR XLCR
@REGS.30=45 R_XMDIO_ACCR XACCR
@BDEF.DEFN=
//
// The Ethernet MDIO interface
//
#define MDIO_BMCR 0x00
#define MDIO_BMSR 0x01
#define MDIO_PHYIDR1 0x02
#define MDIO_PHYIDR2 0x03
#define MDIO_ANAR 0x04
#define MDIO_ANLPAR 0x05
#define MDIO_ANER 0x06
#define MDIO_ANNPTR 0x07
#define MDIO_ANNPRR 0x08
#define MDIO_GBCR 0x09
#define MDIO_GBSR 0x0a
#define MDIO_MACR 0x0d
#define MDIO_MAADR 0x0e
#define MDIO_GBESR 0x0f
#define MDIO_PHYCR 0x10
#define MDIO_PHYSR 0x11
#define MDIO_INER 0x12
#define MDIO_INSR 0x13
#define MDIO_LDPSR 0x1b
#define MDIO_EPAGSR 0x1e
#define MDIO_PAGSEL 0x1f
#define XMDIO_PC1R 0x00
#define XMDIO_PS1R 0x01
#define XMDIO_EEECR 0x14
#define XMDIO_EEEWER 0x10
// #define XMDIO_EEEAR 0x
// #define XMDIO_EEELPAR 0x18
#define XMDIO_LACR 0x1a
#define XMDIO_LCR 0x1c
// #define XMDIO_ACCR 0x1b
typedef struct ENETMDIO_S {
unsigned e_v[32];
} ENETMDIO;
@BDEF.IOTYPE= ENETMDIO
@BDEF.IONAME= io_netmdio
@BDEF.OSDEF= _BOARD_HAS_NETMDIO
@BDEF.OSVAL= static volatile @$THIS.BDEF.IOTYPE *const _mdio = ((@$THIS.BDEF.IOTYPE *)@$THIS.BASE);
@SIM.CLOCK=clk
@SIM.INCLUDE=
#include "enetctrlsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
ENETCTRLSIM *m_mdio;
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_mdio = new ENETCTRLSIM;
#endif // @$(ACCESS)
@SIM.TICK=
#ifdef @$(ACCESS)
m_core->i_mdio = (*m_mdio)((m_core->o_net_reset_n==0)?1:0,
m_core->o_mdclk,
((m_core->o_mdwe)&&(!m_core->o_mdio))?0:1);
#else
m_core->i_mdio = ((m_core->o_mdwe)&&(!m_core->o_mdio))?0:1;
#endif // @$(ACCESS)
@RTL.MAKE.GROUP=ENETMDIO
@RTL.MAKE.FILES=enetctrl.v