iscachable.v

////////////////////////////////////////////////////////////////////////////////
//
// Filename:	../demo-out/iscachable.v
// {{{
// Project:	AutoFPGA, a utility for composing FPGA designs from peripherals
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine:	./autofpga -d -o ../demo-out -I ../auto-data bkram.txt buserr.txt clkcounter.txt clock.txt enet.txt flash.txt global.txt gpio.txt gps.txt hdmi.txt icape.txt legalgen.txt mdio.txt pic.txt pwrcount.txt rtcdate.txt rtcgps.txt sdram.txt sdspi.txt spio.txt version.txt wbmouse.txt wboledbw.txt wbpmic.txt wbscopc.txt wbscope.txt wbubus.txt xpander.txt zipmaster.txt
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License:	GPL, v3, as defined and found on www.gnu.org,
// {{{
//		http://www.gnu.org/licenses/gpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
`default_nettype none
//
module iscachable(
		// {{{
		input	wire	[30-1:0]	i_addr,
		output	reg			o_cachable
		// }}}
	);

	always @(*)
	begin
		o_cachable = 1'b0;
		// Bus master: wb
		// Bus master: wb_dio
		// Bus master: wb_sio
		// bkram
		if ((i_addr[29:0] & 30'h3e000000) == 30'h1a000000)
			o_cachable = 1'b1;
		// flash
		if ((i_addr[29:0] & 30'h3e000000) == 30'h1c000000)
			o_cachable = 1'b1;
		// Bus master: rambus
		// sdram
		if ((i_addr[29:0] & 30'h20000000) == 30'h20000000)
			o_cachable = 1'b1;
	end

endmodule