binary.md

binary analysis frameworks

• capstone unicorn keystone radare2

  • unicorn + capstone + keystone
  • Unicorn Engine
    • Unicorn Showcase
      • CEmu : The Cheap (Assembly) Emulator
  • Capstone is a lightweight multi-platform, multi-architecture disassembly framework

• angr is an open-source binary analysis platform for Python

  • angr is a platform-agnostic binary analysis framework
  • CLE loads binaries and their associated libraries, resolves imports and provides an abstraction of process memory the same way as if it was loader by the OS's loader
    • Loading a Binary - CLE and angr Projects#symbols-and-relocations
  • Breaking CMU's Bomblab with Angr for Fun and Profit
    • Breaking CMU's Bomblab with Angr for Fun and Profit - Part 1
    • Breaking CMU's Bomblab with Angr for Fun and Profit - Part 2
    • Breaking CMU's Bomblab with Angr for Fun and Profit - Part 3
    • Breaking CMU's Bomblab with Angr for Fun and Profit - Part 4
    • Breaking CMU's Bomblab with Angr for Fun and Profit - Part 5
    • Breaking CMU's Bomblab with Angr for Fun and Profit - Part 6
    • Breaking CMU's Bomblab with Angr for Fun and Profit - Part 7
  • angr's solver engine is called Claripy
  • angr ycombinator
  • Angr - Examples
  • Top Level Interfaces

• Symbolic execution

  • Enhancing symbolic execution with veritesting

• The purpose of LIEF project is to provide a cross platform library which can parse, modify and abstract ELF, PE and MachO formats

  • Profiling C++ code with Frida (2nd part)

• What do the .eh_frame and .eh_frame_hdr sections store, exactly?

  • ref code for eh_frame_header

• What is PLT/GOT?

  • Linkers part 1
  • Linkers part 6 - Relocations

• gem5

  • Creating a very simple SimObject
  • Cycle-accurate Benchmarking of JavaScript Programs
  • gem5 TraceCPU
  • Memory Access Analysis and Endurance Leveling Approaches for Non-volatile Working Memory Systems
  • Minor CPU Model
  • O3CPU - Out-of-Order
  • Memory controller updates for new DRAM technologies, NVM interfaces and flexible memory topologies
  • gem5-gpu Developers List: question about using a different memory controller
  • Using perf_event with the ARM PMU inside gem5
  • Performance Monitoring Unit
  • Investigating Black-Box Function Recognition Using Hardware Performance Counters
  • Examining the use of ARM PMUs for DVFS and scheduling
  • Simulation of RISC-V based Systems in gem5
  • A Tutorial on the Gem5 Minor CPU Model TL;DR

  scons build/ARM/gem5.opt
  ./build/ARM/gem5.opt --debug-flags=Exec configs/example/arm/starter_se.py --cpu=minor some-elf-binary

• ChampSim

  • ChampSim is a trace-based simulator for a microarchitecture study

• Building a RISC-V simulator in Rust - Part 1

• trustedfirmware Performance Monitoring Unit

• Dynarmic - A dynamic recompiler for ARM

• Dust - A Nintendo DS emulator written in Rust

• ARM Guide from Michael Royal

• RISC-V Guide from Michael Royal

• MIPT

  • folder contains sources for the Simulation Book
  • Presentation for "Fundamentals of Full-Platform Simulation" MIPT course
  • Computer Architecture 2021/2022
  • MIPT-V / MIPT-MIPS is a pre-silicon simulator of MIPS and RISC-V CPU
  • Why does a processor have 32 registers?

• RISC V

  • 8 мифов о микропроцессорах RISC-V — ответ критикам
    • Addressing Criticism of RISC-V Microprocessors