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Set QOI_FPGA_ENCODER_POST_CYCLES = 0 so verilator_shim does not compensate for this effect
perhaps comment out all ops in the verilog except QOI_OP_RGB, so it's more visible
Note how everything's shifted over by 1 cycle, so the last pixel is missing. How come the upstream decoder is still ok with this? How does it manage to make up the last 0xffffff on testcard.qoi?
The text was updated successfully, but these errors were encountered:
Heh, my new verilog based decoder produces a different .png hash for the .bad file. An image viewer doesn't really show any difference between the 2. It might be a transparent pixel?
How to reproduce:
Note how everything's shifted over by 1 cycle, so the last pixel is missing. How come the upstream decoder is still ok with this? How does it manage to make up the last 0xffffff on
testcard.qoi
?The text was updated successfully, but these errors were encountered: