From 5126c5ee2fc7651921f869820f73dbdf0c6ac711 Mon Sep 17 00:00:00 2001
From: RRK1000 <38955457+RRK1000@users.noreply.github.com>
Date: Fri, 22 Mar 2019 22:41:12 +0530
Subject: [PATCH] Update README.md

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 README.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/README.md b/README.md
index 0f52ad5..879c1c1 100644
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 # Circular Queue – FIFO implementation in hardware
 
+## Team Members:
+1.  Aniket Kaulavkar 
+2.  Rishi Ravikumar 
+3.  Vishnu S Murali 
+4.  Ziyan Zafar
+
 ## Problem Description
 
 Implement a circular queue (FIFO) buffer in hardware using Icarus Verilog. A FIFO(First in First Out) buffer is an elastic storage usually used between two subsystems. As the name indicates the memory that is first written into the FIFO is the first to be read or processed. A FIFO has two control signals i.e. write and read. When write is enabled data is written into the buffer and when read is enabled data is "removed" from the buffer to make room for more data.