diff --git a/glsl/GLSLLexer.g4 b/glsl/GLSLLexer.g4 index b8a139e7e7..4212b1aa22 100644 --- a/glsl/GLSLLexer.g4 +++ b/glsl/GLSLLexer.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine true, allowShortBlocksOnASingleLine true, minEmptyLines 0, alignSemicolons ownLine @@ -262,7 +259,7 @@ LEFT_PAREN : '('; MOD_ASSIGN : '%='; MUL_ASSIGN : '*='; NE_OP : '!='; -NUMBER_SIGN : '#' -> channel (DIRECTIVES), pushMode (DIRECTIVE_MODE); +NUMBER_SIGN : '#' -> channel(DIRECTIVES), pushMode(DIRECTIVE_MODE); OR_ASSIGN : '|='; OR_OP : '||'; PERCENT : '%'; @@ -293,100 +290,100 @@ FLOATCONSTANT: ; INTCONSTANT : DECIMAL_CONSTANT | HEX_CONSTANT | OCTAL_CONSTANT; UINTCONSTANT : INTCONSTANT INTEGER_SUFFIX; -BLOCK_COMMENT : '/*' .*? '*/' -> channel (COMMENTS); -LINE_COMMENT : '//' (~ [\r\n\\] | '\\' (NEWLINE | .))* -> channel (COMMENTS); -LINE_CONTINUATION : '\\' NEWLINE -> channel (HIDDEN); +BLOCK_COMMENT : '/*' .*? '*/' -> channel(COMMENTS); +LINE_COMMENT : '//' (~ [\r\n\\] | '\\' (NEWLINE | .))* -> channel(COMMENTS); +LINE_CONTINUATION : '\\' NEWLINE -> channel(HIDDEN); IDENTIFIER : [a-zA-Z_] [a-zA-Z0-9_]*; -WHITE_SPACE : [ \t\r\n]+ -> channel (HIDDEN); +WHITE_SPACE : [ \t\r\n]+ -> channel(HIDDEN); mode DIRECTIVE_MODE; -DEFINE_DIRECTIVE : 'define' -> channel (DIRECTIVES), mode (DEFINE_DIRECTIVE_MODE); -ELIF_DIRECTIVE : 'elif' -> channel (DIRECTIVES), popMode, mode (ELIF_DIRECTIVE_MODE); -ELSE_DIRECTIVE : 'else' -> channel (DIRECTIVES), popMode, mode (PROGRAM_TEXT_MODE); -ENDIF_DIRECTIVE : 'endif' -> channel (DIRECTIVES), popMode, popMode, popMode; -ERROR_DIRECTIVE : 'error' -> channel (DIRECTIVES), mode (ERROR_DIRECTIVE_MODE); -EXTENSION_DIRECTIVE : 'extension' -> channel (DIRECTIVES), mode (EXTENSION_DIRECTIVE_MODE); -IF_DIRECTIVE : 'if' -> channel (DIRECTIVES), mode (IF_DIRECTIVE_MODE); -IFDEF_DIRECTIVE : 'ifdef' -> channel (DIRECTIVES), mode (IFDEF_DIRECTIVE_MODE); -IFNDEF_DIRECTIVE : 'ifndef' -> channel (DIRECTIVES), mode (IFDEF_DIRECTIVE_MODE); -LINE_DIRECTIVE : 'line' -> channel (DIRECTIVES), mode (LINE_DIRECTIVE_MODE); -PRAGMA_DIRECTIVE : 'pragma' -> channel (DIRECTIVES), mode (PRAGMA_DIRECTIVE_MODE); -UNDEF_DIRECTIVE : 'undef' -> channel (DIRECTIVES), mode (UNDEF_DIRECTIVE_MODE); -VERSION_DIRECTIVE : 'version' -> channel (DIRECTIVES), mode (VERSION_DIRECTIVE_MODE); -SPACE_TAB_0 : SPACE_TAB -> skip; -NEWLINE_0 : NEWLINE -> skip, popMode; +DEFINE_DIRECTIVE : 'define' -> channel(DIRECTIVES), mode(DEFINE_DIRECTIVE_MODE); +ELIF_DIRECTIVE : 'elif' -> channel(DIRECTIVES), popMode, mode(ELIF_DIRECTIVE_MODE); +ELSE_DIRECTIVE : 'else' -> channel(DIRECTIVES), popMode, mode(PROGRAM_TEXT_MODE); +ENDIF_DIRECTIVE : 'endif' -> channel(DIRECTIVES), popMode, popMode, popMode; +ERROR_DIRECTIVE : 'error' -> channel(DIRECTIVES), mode(ERROR_DIRECTIVE_MODE); +EXTENSION_DIRECTIVE : 'extension' -> channel(DIRECTIVES), mode(EXTENSION_DIRECTIVE_MODE); +IF_DIRECTIVE : 'if' -> channel(DIRECTIVES), mode(IF_DIRECTIVE_MODE); +IFDEF_DIRECTIVE : 'ifdef' -> channel(DIRECTIVES), mode(IFDEF_DIRECTIVE_MODE); +IFNDEF_DIRECTIVE : 'ifndef' -> channel(DIRECTIVES), mode(IFDEF_DIRECTIVE_MODE); +LINE_DIRECTIVE : 'line' -> channel(DIRECTIVES), mode(LINE_DIRECTIVE_MODE); +PRAGMA_DIRECTIVE : 'pragma' -> channel(DIRECTIVES), mode(PRAGMA_DIRECTIVE_MODE); +UNDEF_DIRECTIVE : 'undef' -> channel(DIRECTIVES), mode(UNDEF_DIRECTIVE_MODE); +VERSION_DIRECTIVE : 'version' -> channel(DIRECTIVES), mode(VERSION_DIRECTIVE_MODE); +SPACE_TAB_0 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); +NEWLINE_0 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode; mode DEFINE_DIRECTIVE_MODE; -MACRO_NAME : IDENTIFIER MACRO_ARGS? -> channel (DIRECTIVES), mode (MACRO_TEXT_MODE); -NEWLINE_1 : NEWLINE -> skip, popMode; -SPACE_TAB_1 : SPACE_TAB -> skip; +MACRO_NAME : IDENTIFIER MACRO_ARGS? -> channel(DIRECTIVES), mode(MACRO_TEXT_MODE); +NEWLINE_1 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode; +SPACE_TAB_1 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); mode ELIF_DIRECTIVE_MODE; -CONSTANT_EXPRESSION : ~ [\r\n]+ -> channel (DIRECTIVES); -NEWLINE_2 : NEWLINE -> skip, mode (PROGRAM_TEXT_MODE); +CONSTANT_EXPRESSION : ~ [\r\n]+ -> channel(DIRECTIVES); +NEWLINE_2 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), mode(PROGRAM_TEXT_MODE); mode ERROR_DIRECTIVE_MODE; -ERROR_MESSAGE : ~ [\r\n]+ -> channel (DIRECTIVES); -NEWLINE_3 : NEWLINE -> skip, popMode; +ERROR_MESSAGE : ~ [\r\n]+ -> channel(DIRECTIVES); +NEWLINE_3 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode; mode EXTENSION_DIRECTIVE_MODE; -BEHAVIOR : ('require' | 'enable' | 'warn' | 'disable') -> channel (DIRECTIVES); -COLON_0 : COLON -> channel (DIRECTIVES), type (COLON); -EXTENSION_NAME : IDENTIFIER -> channel (DIRECTIVES); -NEWLINE_4 : NEWLINE -> skip, popMode; -SPACE_TAB_2 : SPACE_TAB -> skip; +BEHAVIOR : ('require' | 'enable' | 'warn' | 'disable') -> channel(DIRECTIVES); +COLON_0 : COLON -> channel(DIRECTIVES), type(COLON); +EXTENSION_NAME : IDENTIFIER -> channel(DIRECTIVES); +NEWLINE_4 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode; +SPACE_TAB_2 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); mode IF_DIRECTIVE_MODE; -CONSTANT_EXPRESSION_0 : CONSTANT_EXPRESSION -> channel (DIRECTIVES), type (CONSTANT_EXPRESSION); -NEWLINE_5 : NEWLINE -> skip, pushMode (PROGRAM_TEXT_MODE); +CONSTANT_EXPRESSION_0 : CONSTANT_EXPRESSION -> channel(DIRECTIVES), type(CONSTANT_EXPRESSION); +NEWLINE_5 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), pushMode(PROGRAM_TEXT_MODE); mode IFDEF_DIRECTIVE_MODE; -MACRO_IDENTIFIER : IDENTIFIER -> channel (DIRECTIVES); -NEWLINE_6 : NEWLINE -> skip, pushMode (PROGRAM_TEXT_MODE); -SPACE_TAB_3 : SPACE_TAB -> skip; +MACRO_IDENTIFIER : IDENTIFIER -> channel(DIRECTIVES); +NEWLINE_6 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), pushMode(PROGRAM_TEXT_MODE); +SPACE_TAB_3 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); mode LINE_DIRECTIVE_MODE; -LINE_EXPRESSION : ~ [\r\n]+ -> channel (DIRECTIVES); -NEWLINE_7 : NEWLINE -> skip, mode (PROGRAM_TEXT_MODE); +LINE_EXPRESSION : ~ [\r\n]+ -> channel(DIRECTIVES); +NEWLINE_7 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), mode(PROGRAM_TEXT_MODE); mode MACRO_TEXT_MODE; -BLOCK_COMMENT_0 : BLOCK_COMMENT -> channel (COMMENTS), type(BLOCK_COMMENT); +BLOCK_COMMENT_0 : BLOCK_COMMENT -> channel(COMMENTS), type(BLOCK_COMMENT); MACRO_ESC_NEWLINE : '\\' NEWLINE -> channel(DIRECTIVES); -MACRO_ESC_SEQUENCE : '\\' . -> channel(DIRECTIVES), type (MACRO_TEXT); -MACRO_TEXT : ~ [/\r\n\\]+ -> channel (DIRECTIVES); -NEWLINE_8 : NEWLINE -> skip, popMode; +MACRO_ESC_SEQUENCE : '\\' . -> channel(DIRECTIVES), type(MACRO_TEXT); +MACRO_TEXT : ~ [/\r\n\\]+ -> channel(DIRECTIVES); +NEWLINE_8 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode; SLASH_0 : SLASH -> more; mode PRAGMA_DIRECTIVE_MODE; -DEBUG : 'debug' -> channel (DIRECTIVES); -LEFT_PAREN_0 : LEFT_PAREN -> channel (DIRECTIVES), type (LEFT_PAREN); -NEWLINE_9 : NEWLINE -> skip, popMode; -OFF : 'off' -> channel (DIRECTIVES); -ON : 'on' -> channel (DIRECTIVES); -OPTIMIZE : 'optimize' -> channel (DIRECTIVES); -RIGHT_PAREN_0 : RIGHT_PAREN -> channel (DIRECTIVES), type (RIGHT_PAREN); -SPACE_TAB_5 : SPACE_TAB -> skip; -STDGL : 'STDGL' -> channel (DIRECTIVES); +DEBUG : 'debug' -> channel(DIRECTIVES); +LEFT_PAREN_0 : LEFT_PAREN -> channel(DIRECTIVES), type(LEFT_PAREN); +NEWLINE_9 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode; +OFF : 'off' -> channel(DIRECTIVES); +ON : 'on' -> channel(DIRECTIVES); +OPTIMIZE : 'optimize' -> channel(DIRECTIVES); +RIGHT_PAREN_0 : RIGHT_PAREN -> channel(DIRECTIVES), type(RIGHT_PAREN); +SPACE_TAB_5 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); +STDGL : 'STDGL' -> channel(DIRECTIVES); mode PROGRAM_TEXT_MODE; -BLOCK_COMMENT_1 : BLOCK_COMMENT -> channel (COMMENTS), type (BLOCK_COMMENT); -LINE_COMMENT_0 : LINE_COMMENT -> channel (COMMENTS), type (LINE_COMMENT); +BLOCK_COMMENT_1 : BLOCK_COMMENT -> channel(COMMENTS), type(BLOCK_COMMENT); +LINE_COMMENT_0 : LINE_COMMENT -> channel(COMMENTS), type(LINE_COMMENT); NUMBER_SIGN_0: - NUMBER_SIGN -> channel (DIRECTIVES), type (NUMBER_SIGN), pushMode (DIRECTIVE_MODE) + NUMBER_SIGN -> channel(DIRECTIVES), type(NUMBER_SIGN), pushMode(DIRECTIVE_MODE) ; -PROGRAM_TEXT : ~ [#/]+ -> channel (DIRECTIVES); +PROGRAM_TEXT : ~ [#/]+ -> channel(DIRECTIVES); SLASH_1 : SLASH -> more; mode UNDEF_DIRECTIVE_MODE; -MACRO_IDENTIFIER_0 : MACRO_IDENTIFIER -> channel (DIRECTIVES), type (MACRO_IDENTIFIER); -NEWLINE_10 : NEWLINE -> skip, popMode; -SPACE_TAB_6 : SPACE_TAB -> skip; +MACRO_IDENTIFIER_0 : MACRO_IDENTIFIER -> channel(DIRECTIVES), type(MACRO_IDENTIFIER); +NEWLINE_10 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode; +SPACE_TAB_6 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); mode VERSION_DIRECTIVE_MODE; -NEWLINE_11 : NEWLINE -> skip, popMode; -NUMBER : [0-9]+ -> channel (DIRECTIVES); -PROFILE : ('core' | 'compatibility' | 'es') -> channel (DIRECTIVES); -SPACE_TAB_7 : SPACE_TAB -> skip; +NEWLINE_11 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode; +NUMBER : [0-9]+ -> channel(DIRECTIVES); +PROFILE : ('core' | 'compatibility' | 'es') -> channel(DIRECTIVES); +SPACE_TAB_7 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); fragment DECIMAL_CONSTANT : [1-9] [0-9]*; fragment DIGIT_SEQUENCE : [0-9]+; diff --git a/glsl/GLSLParser.g4 b/glsl/GLSLParser.g4 index 4630491785..456f71fb07 100644 --- a/glsl/GLSLParser.g4 +++ b/glsl/GLSLParser.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, minEmptyLines 1, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine false, allowShortBlocksOnASingleLine true, alignSemicolons hanging, alignColons hanging diff --git a/glsl/GLSLPreParser.g4 b/glsl/GLSLPreParser.g4 index 952237d1eb..0b74899669 100644 --- a/glsl/GLSLPreParser.g4 +++ b/glsl/GLSLPreParser.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, minEmptyLines 1, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine false, allowShortBlocksOnASingleLine true, alignSemicolons hanging, alignColons hanging diff --git a/glsl/README.md b/glsl/README.md index d617d8ab36..e9c77c9ccd 100644 --- a/glsl/README.md +++ b/glsl/README.md @@ -2,4 +2,4 @@ An ANTLR4 grammar for the OpenGL Shading Language (version 4.60) -Example files have been taken from https://github.com/KhronosGroup/glslang/tree/master/Test +Example files have been taken from [glslang](https://github.com/KhronosGroup/glslang/tree/master/Test). diff --git a/glsl/desc.xml b/glsl/desc.xml index 29c99e5780..cc0d21364d 100644 --- a/glsl/desc.xml +++ b/glsl/desc.xml @@ -1,4 +1,6 @@ CSharp;Dart;Java;JavaScript;Python3;TypeScript;Antlr4ng + GLSL + translation_unit diff --git a/glsl/examples/GL_EXT_shader_integer_mix.vert b/glsl/examples-pre/GL_EXT_shader_integer_mix.vert similarity index 100% rename from glsl/examples/GL_EXT_shader_integer_mix.vert rename to glsl/examples-pre/GL_EXT_shader_integer_mix.vert diff --git a/glsl/examples/preprocessor.edge_cases.vert b/glsl/examples-pre/preprocessor.edge_cases.vert similarity index 100% rename from glsl/examples/preprocessor.edge_cases.vert rename to glsl/examples-pre/preprocessor.edge_cases.vert diff --git a/glsl/examples/preprocessor.extensions.vert b/glsl/examples-pre/preprocessor.extensions.vert similarity index 100% rename from glsl/examples/preprocessor.extensions.vert rename to glsl/examples-pre/preprocessor.extensions.vert diff --git a/glsl/examples/preprocessor.function_macro.vert b/glsl/examples-pre/preprocessor.function_macro.vert similarity index 100% rename from glsl/examples/preprocessor.function_macro.vert rename to glsl/examples-pre/preprocessor.function_macro.vert diff --git a/glsl/examples/preprocessor.line.vert b/glsl/examples-pre/preprocessor.line.vert similarity index 100% rename from glsl/examples/preprocessor.line.vert rename to glsl/examples-pre/preprocessor.line.vert diff --git a/glsl/examples/compoundsuffix.vert.glsl b/glsl/examples/compoundsuffix.vert similarity index 100% rename from glsl/examples/compoundsuffix.vert.glsl rename to glsl/examples/compoundsuffix.vert diff --git a/verilog/systemverilog/SystemVerilogLexer.g4 b/verilog/systemverilog/SystemVerilogLexer.g4 index 3223e5553b..adbc665da2 100755 --- a/verilog/systemverilog/SystemVerilogLexer.g4 +++ b/verilog/systemverilog/SystemVerilogLexer.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine true, allowShortBlocksOnASingleLine true, minEmptyLines 0, alignSemicolons ownLine @@ -465,7 +462,7 @@ ELSE_DIRECTIVE : 'else' -> channel(DIRECTIVES), po ELSIF_DIRECTIVE : 'elsif' -> channel(DIRECTIVES), popMode, mode(ELSIF_DIRECTIVE_MODE); END_KEYWORDS_DIRECTIVE : 'end_keywords' -> channel(DIRECTIVES), popMode; ENDCELLDEFINE_DIRECTIVE : 'endcelldefine' -> channel(DIRECTIVES), popMode; -ENDIF_DIRECTIVE : 'endif' -> channel(DIRECTIVES), popMode, popMode, popMode; +ENDIF_DIRECTIVE : 'endif' -> channel(DIRECTIVES), mode(ENDIF_DIRECTIVE_MODE); FILE_DIRECTIVE : '__FILE__' -> channel(DIRECTIVES), popMode; IFDEF_DIRECTIVE : 'ifdef' -> channel(DIRECTIVES), mode(IFDEF_DIRECTIVE_MODE); IFNDEF_DIRECTIVE : 'ifndef' -> channel(DIRECTIVES), mode(IFDEF_DIRECTIVE_MODE); @@ -535,6 +532,10 @@ IDENTIFIER_0 : IDENTIFIER -> channel(DIRECTIVES), type(MACRO_IDENTIFIER); NEWLINE_9 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), mode(SOURCE_TEXT_MODE); SPACE_TAB_8 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); +mode ENDIF_DIRECTIVE_MODE; +NEWLINE_13 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode, popMode, popMode; +SPACE_TAB_12 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); + mode FILENAME_MODE; DQ_1: DQ -> channel(DIRECTIVES), type(DQ), popMode; FILENAME: diff --git a/verilog/systemverilog/SystemVerilogParser.g4 b/verilog/systemverilog/SystemVerilogParser.g4 index 9e469e4ace..f12bc4243c 100644 --- a/verilog/systemverilog/SystemVerilogParser.g4 +++ b/verilog/systemverilog/SystemVerilogParser.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, minEmptyLines 1, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine false, allowShortBlocksOnASingleLine true, alignSemicolons hanging, alignColons hanging diff --git a/verilog/systemverilog/SystemVerilogPreParser.g4 b/verilog/systemverilog/SystemVerilogPreParser.g4 index a9cf56d5cb..709fd42383 100755 --- a/verilog/systemverilog/SystemVerilogPreParser.g4 +++ b/verilog/systemverilog/SystemVerilogPreParser.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, minEmptyLines 1, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine false, allowShortBlocksOnASingleLine true, alignSemicolons hanging, alignColons hanging diff --git a/verilog/systemverilog/examples-pre/nested_conditional_compile.sv b/verilog/systemverilog/examples-pre/nested_conditional_compile.sv new file mode 100644 index 0000000000..7719390eb3 --- /dev/null +++ b/verilog/systemverilog/examples-pre/nested_conditional_compile.sv @@ -0,0 +1,29 @@ +module test ( + out +); + output out; + `define wow + `define nest_one + `define second_nest + `define nest_two +`ifdef wow + initial $display("wow is defined"); +`ifdef nest_one + initial $display("nest_one is defined"); +`ifdef nest_two + initial $display("nest_two is defined"); +`else + initial $display("nest_two is not defined"); +`endif +`else + initial $display("nest_one is not defined"); +`endif +`else + initial $display("wow is not defined"); +`ifdef second_nest + initial $display("second_nest is defined"); +`else + initial $display("second_nest is not defined"); +`endif +`endif +endmodule diff --git a/verilog/verilog/README.md b/verilog/verilog/README.md index 8c67e68446..9fa7b7951a 100644 --- a/verilog/verilog/README.md +++ b/verilog/verilog/README.md @@ -1,3 +1,5 @@ # Verilog Grammar An ANTLR4 grammar for Verilog (IEEE Std 1364-2005) + +Example files have been taken from [hdlConvertor](https://github.com/Nic30/hdlConvertor/tree/master/tests/verilog). diff --git a/verilog/verilog/VerilogLexer.g4 b/verilog/verilog/VerilogLexer.g4 index 0568be5ccd..ea09592ea9 100644 --- a/verilog/verilog/VerilogLexer.g4 +++ b/verilog/verilog/VerilogLexer.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine true, allowShortBlocksOnASingleLine true, minEmptyLines 0, alignSemicolons ownLine @@ -304,7 +301,7 @@ ELSE_DIRECTIVE : 'else' -> channel(DIRECTIVES), po ELSIF_DIRECTIVE : 'elsif' -> channel(DIRECTIVES), popMode, mode(ELSIF_DIRECTIVE_MODE); END_KEYWORDS_DIRECTIVE : 'end_keywords' -> channel(DIRECTIVES), popMode; ENDCELLDEFINE_DIRECTIVE : 'endcelldefine' -> channel(DIRECTIVES), popMode; -ENDIF_DIRECTIVE : 'endif' -> channel(DIRECTIVES), popMode, popMode, popMode; +ENDIF_DIRECTIVE : 'endif' -> channel(DIRECTIVES), mode(ENDIF_DIRECTIVE_MODE); IFDEF_DIRECTIVE : 'ifdef' -> channel(DIRECTIVES), mode(IFDEF_DIRECTIVE_MODE); IFNDEF_DIRECTIVE : 'ifndef' -> channel(DIRECTIVES), mode(IFDEF_DIRECTIVE_MODE); INCLUDE_DIRECTIVE : 'include' -> channel(DIRECTIVES), mode(INCLUDE_DIRECTIVE_MODE); @@ -362,6 +359,10 @@ IDENTIFIER_0 : IDENTIFIER -> channel(DIRECTIVES), type(MACRO_IDENTIFIER); NEWLINE_9 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), mode(SOURCE_TEXT_MODE); SPACE_TAB_8 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); +mode ENDIF_DIRECTIVE_MODE; +NEWLINE_13 : NEWLINE -> channel(HIDDEN), type(WHITE_SPACE), popMode, popMode, popMode; +SPACE_TAB_12 : SPACE_TAB -> channel(HIDDEN), type(WHITE_SPACE); + mode FILENAME_MODE; DQ_1 : DQ -> channel(DIRECTIVES), type(DQ), popMode; FILENAME : ( ASCII_PRINTABLE_NO_QUOTE_BACKSLASH | ESC_ASCII_PRINTABLE)+ -> channel(DIRECTIVES); diff --git a/verilog/verilog/VerilogParser.g4 b/verilog/verilog/VerilogParser.g4 index d0fa90eb77..add41742e8 100644 --- a/verilog/verilog/VerilogParser.g4 +++ b/verilog/verilog/VerilogParser.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, minEmptyLines 1, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine false, allowShortBlocksOnASingleLine true, alignSemicolons hanging, alignColons hanging diff --git a/verilog/verilog/VerilogPreParser.g4 b/verilog/verilog/VerilogPreParser.g4 index 350b9f8d2b..b6a8cd8207 100644 --- a/verilog/verilog/VerilogPreParser.g4 +++ b/verilog/verilog/VerilogPreParser.g4 @@ -1,26 +1,23 @@ /* -MIT License - -Copyright (c) 2022 Mustafa Said Ağca - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -*/ + MIT License + + Copyright (c) 2022 Mustafa Said Ağca + + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and + associated documentation files (the "Software"), to deal in the Software without restriction, + including without limitation the rights to use, copy, modify, merge, publish, distribute, + sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all copies or + substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT + OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ // $antlr-format alignTrailingComments true, columnLimit 150, minEmptyLines 1, maxEmptyLinesToKeep 1, reflowComments false, useTab false // $antlr-format allowShortRulesOnASingleLine false, allowShortBlocksOnASingleLine true, alignSemicolons hanging, alignColons hanging diff --git a/verilog/verilog/examples-pre/define.v b/verilog/verilog/examples-pre/define.v new file mode 100644 index 0000000000..34849e13fd --- /dev/null +++ b/verilog/verilog/examples-pre/define.v @@ -0,0 +1,23 @@ +// Examples of `define text macros +`define MY_NUMBER 5 +`define MY_STRING "Hello world!" +`define ADD2PLUS2 2 + 2 +`define ADD5(RESULT, SOURCE) \ + RESULT = SOURCE + 5; \ + $display("Inside ADD5 macro. Scope is %m"); +module test; + reg [7:0] a, b; + initial begin + $display(`MY_NUMBER); + $display(`MY_STRING); + $display(2 + 2); + $display(`ADD2PLUS2); + a = 1; +`ifdef MY_FEATURE + `ADD5(b, a) + $display("a:%0d, b:%0d", a, b); +`else + $display("No feature"); +`endif + end +endmodule diff --git a/verilog/verilog/examples-pre/directive_verilogpp.v b/verilog/verilog/examples-pre/directive_verilogpp.v new file mode 100644 index 0000000000..77bbcecf89 --- /dev/null +++ b/verilog/verilog/examples-pre/directive_verilogpp.v @@ -0,0 +1,11 @@ +`celldefine +`endcelldefine +`default_nettype wire +`define MYDEFINE "is the best!" +`undef MYDEFINE +`include "fifo_rx.v" +`resetall +`line 14 "noexistingfile.v" 2 +`timescale 1 ns / 1ps +`unconnected_drive pull1 +`nounconnected_drive diff --git a/verilog/verilog/examples-pre/nested_conditional_compile.v b/verilog/verilog/examples-pre/nested_conditional_compile.v new file mode 100644 index 0000000000..7719390eb3 --- /dev/null +++ b/verilog/verilog/examples-pre/nested_conditional_compile.v @@ -0,0 +1,29 @@ +module test ( + out +); + output out; + `define wow + `define nest_one + `define second_nest + `define nest_two +`ifdef wow + initial $display("wow is defined"); +`ifdef nest_one + initial $display("nest_one is defined"); +`ifdef nest_two + initial $display("nest_two is defined"); +`else + initial $display("nest_two is not defined"); +`endif +`else + initial $display("nest_one is not defined"); +`endif +`else + initial $display("wow is not defined"); +`ifdef second_nest + initial $display("second_nest is defined"); +`else + initial $display("second_nest is not defined"); +`endif +`endif +endmodule diff --git a/verilog/verilog/examples-pre/pragma.v b/verilog/verilog/examples-pre/pragma.v new file mode 100644 index 0000000000..e5774eb45d --- /dev/null +++ b/verilog/verilog/examples-pre/pragma.v @@ -0,0 +1,12 @@ +module Example ( + input clk, + input [3:0] data_in, + output reg [7:0] data_out +); + `pragma synthesis_clock("clk", 10, 5, 0, 0, 0, 0) + always @(posedge clk) begin + `pragma translate_off + data_out <= {4'b0, data_in} + 8'hAA; + `pragma translate_on + end +endmodule diff --git a/verilog/verilog/examples/aFifo.v b/verilog/verilog/examples/aFifo.v new file mode 100644 index 0000000000..0e6842d4a1 --- /dev/null +++ b/verilog/verilog/examples/aFifo.v @@ -0,0 +1,83 @@ +// http://www.asic-world.com/code/hdl_models/aFifo.v +//========================================== +// Function : Asynchronous FIFO (w/ 2 asynchronous clocks). +// Coder : Alex Claros F. +// Date : 15/May/2005. +// Notes : This implementation is based on the article +// 'Asynchronous FIFO in Virtex-II FPGAs' +// writen by Peter Alfke. This TechXclusive +// article can be downloaded from the +// Xilinx website. It has some minor modifications. +//========================================= +module aFifo #( + parameter DATA_WIDTH = 8, + ADDRESS_WIDTH = 4, + FIFO_DEPTH = (1 << ADDRESS_WIDTH) +) +//Reading port +( + output reg [DATA_WIDTH-1:0] Data_out, + output reg Empty_out, + input wire ReadEn_in, + input wire RClk, + //Writing port. + input wire [DATA_WIDTH-1:0] Data_in, + output reg Full_out, + input wire WriteEn_in, + input wire WClk, + input wire Clear_in +); + /////Internal connections & variables////// + reg [DATA_WIDTH-1:0] Mem[FIFO_DEPTH-1:0]; + wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead; + wire EqualAddresses; + wire NextWriteAddressEn, NextReadAddressEn; + wire Set_Status, Rst_Status; + reg Status; + wire PresetFull, PresetEmpty; + //////////////Code/////////////// + //Data ports logic: + //(Uses a dual-port RAM). + //'Data_out' logic: + always @(posedge RClk) if (ReadEn_in & !Empty_out) Data_out <= Mem[pNextWordToRead]; + //'Data_in' logic: + always @(posedge WClk) if (WriteEn_in & !Full_out) Mem[pNextWordToWrite] <= Data_in; + //Fifo addresses support logic: + //'Next Addresses' enable logic: + assign NextWriteAddressEn = WriteEn_in & ~Full_out; + assign NextReadAddressEn = ReadEn_in & ~Empty_out; + //Addreses (Gray counters) logic: + GrayCounter GrayCounter_pWr ( + .GrayCount_out(pNextWordToWrite), + .Enable_in(NextWriteAddressEn), + .Clear_in(Clear_in), + .Clk(WClk) + ); + GrayCounter GrayCounter_pRd ( + .GrayCount_out(pNextWordToRead), + .Enable_in(NextReadAddressEn), + .Clear_in(Clear_in), + .Clk(RClk) + ); + //'EqualAddresses' logic: + assign EqualAddresses = (pNextWordToWrite == pNextWordToRead); + //'Quadrant selectors' logic: + assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) & + (pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]); + assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) & + (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]); + //'Status' latch logic: + always @(Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset. + if (Rst_Status | Clear_in) Status = 0; //Going 'Empty'. + else if (Set_Status) Status = 1; //Going 'Full'. + //'Full_out' logic for the writing port: + assign PresetFull = Status & EqualAddresses; //'Full' Fifo. + always @(posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset. + if (PresetFull) Full_out <= 1; + else Full_out <= 0; + //'Empty_out' logic for the reading port: + assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo. + always @(posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset. + if (PresetEmpty) Empty_out <= 1; + else Empty_out <= 0; +endmodule diff --git a/verilog/verilog/examples/adder_implicit.v b/verilog/verilog/examples/adder_implicit.v new file mode 100644 index 0000000000..78be5ea653 --- /dev/null +++ b/verilog/verilog/examples/adder_implicit.v @@ -0,0 +1,63 @@ +//----------------------------------------------------- +// http://www.asic-world.com/verilog/syntax2.html +// This is simple adder Program +// Design Name : adder_implicit +// File Name : adder_implicit.v +// Function : This program shows how implicit +// port connection are done +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module adder_implicit ( + result, // Output of the adder + carry, // Carry output of adder + r1, // first input + r2, // second input + ci // carry input +); + // Input Port Declarations + input [3:0] r1; + input [3:0] r2; + input ci; + // Output Port Declarations + output [3:0] result; + output carry; + // Port Wires + wire [3:0] r1; + wire [3:0] r2; + wire ci; + wire [3:0] result; + wire carry; + // Internal variables + wire c1; + wire c2; + wire c3; + // Code Starts Here + addbit u0 ( + r1[0], + r2[0], + ci, + result[0], + c1 + ); + addbit u1 ( + r1[1], + r2[1], + c1, + result[1], + c2 + ); + addbit u2 ( + r1[2], + r2[2], + c2, + result[2], + c3 + ); + addbit u3 ( + r1[3], + r2[3], + c3, + result[3], + carry + ); +endmodule // End Of Module adder diff --git a/verilog/verilog/examples/aes.v b/verilog/verilog/examples/aes.v new file mode 100644 index 0000000000..f332e1b627 --- /dev/null +++ b/verilog/verilog/examples/aes.v @@ -0,0 +1,286 @@ +// https://opencores.org/websvn/filedetails?repname=aes_core&path=%2Faes_core%2Ftrunk%2Frtl%2Fverilog%2Faes_cipher_top.v +///////////////////////////////////////////////////////////////////// +//// //// +//// AES Cipher Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/aes_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +// CVS Log +// +// $Id: aes_cipher_top.v,v 1.1.1.1 2002-11-09 11:22:48 rudi Exp $ +// +// $Date: 2002-11-09 11:22:48 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +module aes_cipher_top ( + clk, + rst, + ld, + done, + key, + text_in, + text_out +); + input clk, rst; + input ld; + output done; + input [127:0] key; + input [127:0] text_in; + output [127:0] text_out; + //////////////////////////////////////////////////////////////////// + // + // Local Wires + // + wire [31:0] w0, w1, w2, w3; + reg [127:0] text_in_r; + reg [127:0] text_out; + reg [7:0] sa00, sa01, sa02, sa03; + reg [7:0] sa10, sa11, sa12, sa13; + reg [7:0] sa20, sa21, sa22, sa23; + reg [7:0] sa30, sa31, sa32, sa33; + wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next; + wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next; + wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next; + wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next; + wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub; + wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub; + wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub; + wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub; + wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr; + wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr; + wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr; + wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr; + wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc; + wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc; + wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc; + wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc; + reg done, ld_r; + reg [3:0] dcnt; + //////////////////////////////////////////////////////////////////// + // + // Misc Logic + // + always @(posedge clk) + if (!rst) dcnt <= #1 4'h0; + else if (ld) dcnt <= #1 4'hb; + else if (|dcnt) dcnt <= #1 dcnt - 4'h1; + always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld; + always @(posedge clk) if (ld) text_in_r <= #1 text_in; + always @(posedge clk) ld_r <= #1 ld; + //////////////////////////////////////////////////////////////////// + // + // Initial Permutation (AddRoundKey) + // + always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next; + always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next; + always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next; + always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next; + always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next; + always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next; + always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next; + always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next; + always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next; + always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next; + always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next; + always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next; + always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next; + always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next; + always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next; + always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next; + //////////////////////////////////////////////////////////////////// + // + // Round Permutations + // + assign sa00_sr = sa00_sub; + assign sa01_sr = sa01_sub; + assign sa02_sr = sa02_sub; + assign sa03_sr = sa03_sub; + assign sa10_sr = sa11_sub; + assign sa11_sr = sa12_sub; + assign sa12_sr = sa13_sub; + assign sa13_sr = sa10_sub; + assign sa20_sr = sa22_sub; + assign sa21_sr = sa23_sub; + assign sa22_sr = sa20_sub; + assign sa23_sr = sa21_sub; + assign sa30_sr = sa33_sub; + assign sa31_sr = sa30_sub; + assign sa32_sr = sa31_sub; + assign sa33_sr = sa32_sub; + assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc} = mix_col(sa00_sr, sa10_sr, sa20_sr, sa30_sr); + assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc} = mix_col(sa01_sr, sa11_sr, sa21_sr, sa31_sr); + assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc} = mix_col(sa02_sr, sa12_sr, sa22_sr, sa32_sr); + assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc} = mix_col(sa03_sr, sa13_sr, sa23_sr, sa33_sr); + assign sa00_next = sa00_mc ^ w0[31:24]; + assign sa01_next = sa01_mc ^ w1[31:24]; + assign sa02_next = sa02_mc ^ w2[31:24]; + assign sa03_next = sa03_mc ^ w3[31:24]; + assign sa10_next = sa10_mc ^ w0[23:16]; + assign sa11_next = sa11_mc ^ w1[23:16]; + assign sa12_next = sa12_mc ^ w2[23:16]; + assign sa13_next = sa13_mc ^ w3[23:16]; + assign sa20_next = sa20_mc ^ w0[15:08]; + assign sa21_next = sa21_mc ^ w1[15:08]; + assign sa22_next = sa22_mc ^ w2[15:08]; + assign sa23_next = sa23_mc ^ w3[15:08]; + assign sa30_next = sa30_mc ^ w0[07:00]; + assign sa31_next = sa31_mc ^ w1[07:00]; + assign sa32_next = sa32_mc ^ w2[07:00]; + assign sa33_next = sa33_mc ^ w3[07:00]; + //////////////////////////////////////////////////////////////////// + // + // Final text output + // + always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24]; + always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24]; + always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24]; + always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24]; + always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16]; + always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16]; + always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16]; + always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16]; + always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08]; + always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08]; + always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08]; + always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08]; + always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00]; + always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00]; + always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00]; + always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00]; + //////////////////////////////////////////////////////////////////// + // + // Generic Functions + // + function [31:0] mix_col; + input [7:0] s0, s1, s2, s3; + reg [7:0] s0_o, s1_o, s2_o, s3_o; + begin + mix_col[31:24] = xtime(s0) ^ xtime(s1) ^ s1 ^ s2 ^ s3; + mix_col[23:16] = s0 ^ xtime(s1) ^ xtime(s2) ^ s2 ^ s3; + mix_col[15:08] = s0 ^ s1 ^ xtime(s2) ^ xtime(s3) ^ s3; + mix_col[07:00] = xtime(s0) ^ s0 ^ s1 ^ s2 ^ xtime(s3); + end + endfunction + function [7:0] xtime; + input [7:0] b; + xtime = {b[6:0], 1'b0} ^ (8'h1b & {8{b[7]}}); + endfunction + //////////////////////////////////////////////////////////////////// + // + // Modules + // + aes_key_expand_128 u0 ( + .clk (clk), + .kld (ld), + .key (key), + .wo_0(w0), + .wo_1(w1), + .wo_2(w2), + .wo_3(w3) + ); + aes_sbox us00 ( + .a(sa00), + .d(sa00_sub) + ); + aes_sbox us01 ( + .a(sa01), + .d(sa01_sub) + ); + aes_sbox us02 ( + .a(sa02), + .d(sa02_sub) + ); + aes_sbox us03 ( + .a(sa03), + .d(sa03_sub) + ); + aes_sbox us10 ( + .a(sa10), + .d(sa10_sub) + ); + aes_sbox us11 ( + .a(sa11), + .d(sa11_sub) + ); + aes_sbox us12 ( + .a(sa12), + .d(sa12_sub) + ); + aes_sbox us13 ( + .a(sa13), + .d(sa13_sub) + ); + aes_sbox us20 ( + .a(sa20), + .d(sa20_sub) + ); + aes_sbox us21 ( + .a(sa21), + .d(sa21_sub) + ); + aes_sbox us22 ( + .a(sa22), + .d(sa22_sub) + ); + aes_sbox us23 ( + .a(sa23), + .d(sa23_sub) + ); + aes_sbox us30 ( + .a(sa30), + .d(sa30_sub) + ); + aes_sbox us31 ( + .a(sa31), + .d(sa31_sub) + ); + aes_sbox us32 ( + .a(sa32), + .d(sa32_sub) + ); + aes_sbox us33 ( + .a(sa33), + .d(sa33_sub) + ); +endmodule diff --git a/verilog/verilog/examples/arbiter.v b/verilog/verilog/examples/arbiter.v new file mode 100644 index 0000000000..7ae14f2816 --- /dev/null +++ b/verilog/verilog/examples/arbiter.v @@ -0,0 +1,111 @@ +//http://www.asic-world.com/code/hdl_models/arbiter.v +//---------------------------------------------------- +// A four level, round-robin arbiter. This was +// orginally coded by WD Peterson in VHDL. +//---------------------------------------------------- +module arbiter ( + clk, + rst, + req3, + req2, + req1, + req0, + gnt3, + gnt2, + gnt1, + gnt0 +); + // --------------Port Declaration----------------------- + input clk; + input rst; + input req3; + input req2; + input req1; + input req0; + output gnt3; + output gnt2; + output gnt1; + output gnt0; + //--------------Internal Registers---------------------- + wire [1:0] gnt; + wire comreq; + wire beg; + wire [1:0] lgnt; + wire lcomreq; + reg lgnt0; + reg lgnt1; + reg lgnt2; + reg lgnt3; + reg lasmask; + reg lmask0; + reg lmask1; + reg ledge; + //--------------Code Starts Here----------------------- + always @(posedge clk) + if (rst) begin + lgnt0 <= 0; + lgnt1 <= 0; + lgnt2 <= 0; + lgnt3 <= 0; + end else begin + lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0) + | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0) + | (~lcomreq & lmask1 & lmask0 & req0 ) + | ( lcomreq & lgnt0 ); + lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1) + | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0) + | (~lcomreq & lmask1 & lmask0 & req1 & ~req0) + | ( lcomreq & lgnt1); + lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1) + | (~lcomreq & ~lmask1 & lmask0 & req2) + | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0) + | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0) + | ( lcomreq & lgnt2); + lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1) + | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2) + | (~lcomreq & lmask1 & ~lmask0 & req3) + | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0) + | ( lcomreq & lgnt3); + end + //---------------------------------------------------- + // lasmask state machine. + //---------------------------------------------------- + assign beg = (req3 | req2 | req1 | req0) & ~lcomreq; + always @(posedge clk) begin + lasmask <= (beg & ~ledge & ~lasmask); + ledge <= (beg & ~ledge & lasmask) | (beg & ledge & ~lasmask); + end + //---------------------------------------------------- + // comreq logic. + //---------------------------------------------------- + assign lcomreq = (req3 & lgnt3) | (req2 & lgnt2) | (req1 & lgnt1) | (req0 & lgnt0); + //---------------------------------------------------- + // Encoder logic. + //---------------------------------------------------- + assign lgnt = {(lgnt3 | lgnt2), (lgnt3 | lgnt1)}; + //---------------------------------------------------- + // lmask register. + //---------------------------------------------------- + always @(posedge clk) + if (rst) begin + lmask1 <= 0; + lmask0 <= 0; + end else if (lasmask) begin + lmask1 <= lgnt[1]; + lmask0 <= lgnt[0]; + end else begin + lmask1 <= lmask1; + lmask0 <= lmask0; + end + assign comreq = lcomreq; + assign gnt = lgnt; + //---------------------------------------------------- + // Drive the outputs + //---------------------------------------------------- + assign gnt3 = lgnt3; + assign gnt2 = lgnt2; + assign gnt1 = lgnt1; + assign gnt0 = lgnt0; +endmodule diff --git a/verilog/verilog/examples/arbiter_tb.v b/verilog/verilog/examples/arbiter_tb.v new file mode 100644 index 0000000000..a9f04e05f2 --- /dev/null +++ b/verilog/verilog/examples/arbiter_tb.v @@ -0,0 +1,59 @@ +// http://www.asic-world.com/code/hdl_models/arbiter_tb.v +`include "arbiter.v" +module top (); + reg clk; + reg rst; + reg req3; + reg req2; + reg req1; + reg req0; + wire gnt3; + wire gnt2; + wire gnt1; + wire gnt0; + // Clock generator + always #1 clk = ~clk; + initial begin + $dumpfile("arbiter.vcd"); + $dumpvars(); + clk = 0; + rst = 1; + req0 = 0; + req1 = 0; + req2 = 0; + req3 = 0; + #10 rst = 0; + repeat (1) @(posedge clk); + req0 <= 1; + repeat (1) @(posedge clk); + req0 <= 0; + repeat (1) @(posedge clk); + req0 <= 1; + req1 <= 1; + repeat (1) @(posedge clk); + req2 <= 1; + req1 <= 0; + repeat (1) @(posedge clk); + req3 <= 1; + req2 <= 0; + repeat (1) @(posedge clk); + req3 <= 0; + repeat (1) @(posedge clk); + req0 <= 0; + repeat (1) @(posedge clk); + #10 $finish; + end + // Connect the DUT + arbiter U ( + clk, + rst, + req3, + req2, + req1, + req0, + gnt3, + gnt2, + gnt1, + gnt0 + ); +endmodule diff --git a/verilog/verilog/examples/axiluart.v b/verilog/verilog/examples/axiluart.v deleted file mode 100644 index 62f4e7f865..0000000000 --- a/verilog/verilog/examples/axiluart.v +++ /dev/null @@ -1,482 +0,0 @@ -/* -Copyright (C) 2020-2021, Gisselquist Technology, LLC - -This program is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. (It's in the $(ROOT)/doc directory. Run make with no -target there if the PDF file isn't present.) If not, see - for a copy. - -License: GPL, v3, as defined and found on www.gnu.org, -http://www.gnu.org/licenses/gpl.html -*/ -`default_nettype none -module axiluart #( - parameter [30:0] INITIAL_SETUP = 31'd25, - parameter [3:0] LGFLEN = 4, - parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1, - parameter [3:0] LCLLGFLEN = (LGFLEN > 4'ha) ? 4'ha : ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN), - parameter C_AXI_ADDR_WIDTH = 4, - parameter C_AXI_DATA_WIDTH = 32, - parameter [0:0] OPT_SKIDBUFFER = 1'b0, - parameter [0:0] OPT_LOWPOWER = 0, - parameter ADDRLSB = $clog2(C_AXI_DATA_WIDTH) - 3 -) ( - input wire S_AXI_ACLK, - input wire S_AXI_ARESETN, - input wire S_AXI_AWVALID, - output wire S_AXI_AWREADY, - input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, - input wire [2:0] S_AXI_AWPROT, - input wire S_AXI_WVALID, - output wire S_AXI_WREADY, - input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, - input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, - output wire S_AXI_BVALID, - input wire S_AXI_BREADY, - output wire [1:0] S_AXI_BRESP, - input wire S_AXI_ARVALID, - output wire S_AXI_ARREADY, - input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, - input wire [2:0] S_AXI_ARPROT, - output wire S_AXI_RVALID, - input wire S_AXI_RREADY, - output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, - output wire [1:0] S_AXI_RRESP, - input wire i_uart_rx, - output wire o_uart_tx, - input wire i_cts_n, - output reg o_rts_n, - output wire o_uart_rx_int, - output wire o_uart_tx_int, - output wire o_uart_rxfifo_int, - output wire o_uart_txfifo_int -); - wire i_reset = !S_AXI_ARESETN; - wire axil_write_ready; - wire [C_AXI_ADDR_WIDTH-ADDRLSB-1:0] awskd_addr; - wire [C_AXI_DATA_WIDTH-1:0] wskd_data; - wire [C_AXI_DATA_WIDTH/8-1:0] wskd_strb; - reg axil_bvalid; - wire axil_read_ready; - wire [C_AXI_ADDR_WIDTH-ADDRLSB-1:0] arskd_addr; - reg [C_AXI_DATA_WIDTH-1:0] axil_read_data; - reg axil_read_valid; - wire tx_busy; - reg [30:0] uart_setup; - wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart; - wire [7:0] rx_uart_data; - reg rx_uart_reset; - wire rx_empty_n, rx_fifo_err; - wire [7:0] rxf_axil_data; - wire [15:0] rxf_status; - reg rxf_axil_read; - reg r_rx_perr, r_rx_ferr; - wire [(LCLLGFLEN-1):0] check_cutoff; - wire [31:0] axil_rx_data; - wire tx_empty_n, txf_err, tx_break; - wire [ 7:0] tx_data; - wire [15:0] txf_status; - reg txf_axil_write, tx_uart_reset; - reg [7:0] txf_axil_data; - wire [31:0] axil_tx_data; - wire [31:0] axil_fifo_data; - reg [1:0] r_axil_addr; - reg r_preread; - reg [31:0] new_setup; - generate - if (OPT_SKIDBUFFER) begin : SKIDBUFFER_WRITE - wire awskd_valid, wskd_valid; - skidbuffer #( - .OPT_OUTREG(0), - .OPT_LOWPOWER(OPT_LOWPOWER), - .DW(C_AXI_ADDR_WIDTH - ADDRLSB) - ) axilawskid ( - .i_clk (S_AXI_ACLK), - .i_reset(i_reset), - .i_valid(S_AXI_AWVALID), - .o_ready(S_AXI_AWREADY), - .i_data (S_AXI_AWADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]), - .o_valid(awskd_valid), - .i_ready(axil_write_ready), - .o_data (awskd_addr) - ); - skidbuffer #( - .OPT_OUTREG(0), - .OPT_LOWPOWER(OPT_LOWPOWER), - .DW(C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH / 8) - ) axilwskid ( - .i_clk (S_AXI_ACLK), - .i_reset(i_reset), - .i_valid(S_AXI_WVALID), - .o_ready(S_AXI_WREADY), - .i_data ({S_AXI_WDATA, S_AXI_WSTRB}), - .o_valid(wskd_valid), - .i_ready(axil_write_ready), - .o_data ({wskd_data, wskd_strb}) - ); - assign axil_write_ready = awskd_valid && wskd_valid && (!S_AXI_BVALID || S_AXI_BREADY); - end else begin : SIMPLE_WRITES - reg axil_awready; - initial axil_awready = 1'b0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) axil_awready <= 1'b0; - else - axil_awready <= !axil_awready -&& (S_AXI_AWVALID && S_AXI_WVALID) -&& (!S_AXI_BVALID || S_AXI_BREADY); - assign S_AXI_AWREADY = axil_awready; - assign S_AXI_WREADY = axil_awready; - assign awskd_addr = S_AXI_AWADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]; - assign wskd_data = S_AXI_WDATA; - assign wskd_strb = S_AXI_WSTRB; - assign axil_write_ready = axil_awready; - end - endgenerate - initial axil_bvalid = 0; - always @(posedge S_AXI_ACLK) - if (i_reset) axil_bvalid <= 0; - else if (axil_write_ready) axil_bvalid <= 1; - else if (S_AXI_BREADY) axil_bvalid <= 0; - assign S_AXI_BVALID = axil_bvalid; - assign S_AXI_BRESP = 2'b00; - generate - if (OPT_SKIDBUFFER) begin : SKIDBUFFER_READ - wire arskd_valid; - skidbuffer #( - .OPT_OUTREG(0), - .OPT_LOWPOWER(OPT_LOWPOWER), - .DW(C_AXI_ADDR_WIDTH - ADDRLSB) - ) axilarskid ( - .i_clk (S_AXI_ACLK), - .i_reset(i_reset), - .i_valid(S_AXI_ARVALID), - .o_ready(S_AXI_ARREADY), - .i_data (S_AXI_ARADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]), - .o_valid(arskd_valid), - .i_ready(axil_read_ready), - .o_data (arskd_addr) - ); - assign axil_read_ready = arskd_valid && (!r_preread || !axil_read_valid || S_AXI_RREADY); - end else begin : SIMPLE_READS - reg axil_arready; - initial axil_arready = 1; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) axil_arready <= 1; - else if (S_AXI_ARVALID && S_AXI_ARREADY) axil_arready <= 0; - else if (S_AXI_RVALID && S_AXI_RREADY) axil_arready <= 1; - assign arskd_addr = S_AXI_ARADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]; - assign S_AXI_ARREADY = axil_arready; - assign axil_read_ready = (S_AXI_ARVALID && S_AXI_ARREADY); - end - endgenerate - initial axil_read_valid = 1'b0; - always @(posedge S_AXI_ACLK) - if (i_reset) axil_read_valid <= 1'b0; - else if (r_preread) axil_read_valid <= 1'b1; - else if (S_AXI_RREADY) axil_read_valid <= 1'b0; - assign S_AXI_RVALID = axil_read_valid; - assign S_AXI_RDATA = axil_read_data; - assign S_AXI_RRESP = 2'b00; - localparam [1:0] UART_SETUP = 2'b00, UART_FIFO = 2'b01, UART_RXREG = 2'b10, UART_TXREG = 2'b11; - always @(*) new_setup = apply_wstrb({1'b0, uart_setup}, wskd_data, wskd_strb); - initial uart_setup = INITIAL_SETUP | ((HARDWARE_FLOW_CONTROL_PRESENT == 1'b0) ? 31'h40000000 : 0); - always @(posedge S_AXI_ACLK) - if ((axil_write_ready) && (awskd_addr == UART_SETUP)) begin - uart_setup <= new_setup[30:0]; - if (!HARDWARE_FLOW_CONTROL_PRESENT) uart_setup[30] <= 1'b1; - end -`ifdef FORMAL - (* anyseq *) reg w_rx_break, w_rx_perr, w_rx_ferr, w_ck_uart; - assign rx_break = w_rx_break; - assign w_rx_perr = w_rx_perr; - assign w_rx_ferr = w_rx_ferr; - assign ck_uart = w_ck_uart; -`else -`ifdef USE_LITE_UART - rxuartlite #( - .CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]) - ) rx ( - S_AXI_ACLK, - i_uart_rx, - rx_stb, - rx_uart_data - ); - assign rx_break = 1'b0; - assign rx_perr = 1'b0; - assign rx_ferr = 1'b0; - assign ck_uart = 1'b0; -`else - rxuart #( - .INITIAL_SETUP(INITIAL_SETUP) - ) rx ( - S_AXI_ACLK, - (!S_AXI_ARESETN) || (rx_uart_reset), - uart_setup, - i_uart_rx, - rx_stb, - rx_uart_data, - rx_break, - rx_perr, - rx_ferr, - ck_uart - ); -`endif -`endif - ufifo #( - .LGFLEN(LCLLGFLEN), - .RXFIFO(1) - ) rxfifo ( - S_AXI_ACLK, - (!S_AXI_ARESETN) || (rx_break) || (rx_uart_reset), - rx_stb, - rx_uart_data, - rx_empty_n, - rxf_axil_read, - rxf_axil_data, - rxf_status, - rx_fifo_err - ); - assign o_uart_rxfifo_int = rxf_status[1]; - assign o_uart_rx_int = rxf_status[0]; - assign check_cutoff = -3; - always @(posedge S_AXI_ACLK) - o_rts_n <= ((HARDWARE_FLOW_CONTROL_PRESENT) -&&(!uart_setup[30]) -&&(rxf_status[(LCLLGFLEN+1):2] > check_cutoff)); - initial rxf_axil_read = 1'b0; - always @(posedge S_AXI_ACLK) - rxf_axil_read <= (axil_read_ready) && (arskd_addr[1:0] == UART_RXREG); - initial r_rx_perr = 1'b0; - initial r_rx_ferr = 1'b0; - always @(posedge S_AXI_ACLK) - if ((rx_uart_reset) || (rx_break)) begin - r_rx_perr <= 1'b0; - r_rx_ferr <= 1'b0; - end else if (axil_write_ready && awskd_addr == UART_RXREG && wskd_strb[1]) begin - r_rx_perr <= (r_rx_perr) && (!wskd_data[9]); - r_rx_ferr <= (r_rx_ferr) && (!wskd_data[10]); - end else if (rx_stb) begin - r_rx_perr <= (r_rx_perr) || (rx_perr); - r_rx_ferr <= (r_rx_ferr) || (rx_ferr); - end - initial rx_uart_reset = 1'b1; - always @(posedge S_AXI_ACLK) - if ((!S_AXI_ARESETN) || ((axil_write_ready) && (awskd_addr[1:0] == UART_SETUP) && (&wskd_strb))) - rx_uart_reset <= 1'b1; - else if (axil_write_ready && (awskd_addr[1:0] == UART_RXREG) && wskd_strb[1]) - rx_uart_reset <= wskd_data[12]; - else rx_uart_reset <= 1'b0; - assign axil_rx_data = { - 16'h00, 3'h0, rx_fifo_err, rx_break, rx_ferr, r_rx_perr, !rx_empty_n, rxf_axil_data - }; - initial txf_axil_write = 1'b0; - always @(posedge S_AXI_ACLK) begin - txf_axil_write <= (axil_write_ready) && (awskd_addr == UART_TXREG) && wskd_strb[0]; - txf_axil_data <= wskd_data[7:0]; - end - ufifo #( - .LGFLEN(LGFLEN), - .RXFIFO(0) - ) txfifo ( - S_AXI_ACLK, - (tx_break) || (tx_uart_reset), - txf_axil_write, - txf_axil_data, - tx_empty_n, - (!tx_busy) && (tx_empty_n), - tx_data, - txf_status, - txf_err - ); - assign o_uart_tx_int = txf_status[0]; - assign o_uart_txfifo_int = txf_status[1]; -`ifndef USE_LITE_UART - reg r_tx_break; - initial r_tx_break = 1'b0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) r_tx_break <= 1'b0; - else if (axil_write_ready && (awskd_addr[1:0] == UART_TXREG) && wskd_strb[1]) - r_tx_break <= wskd_data[9]; - assign tx_break = r_tx_break; -`else - assign tx_break = 1'b0; -`endif - initial tx_uart_reset = 1'b1; - always @(posedge S_AXI_ACLK) - if ((!S_AXI_ARESETN) || ((axil_write_ready) && (awskd_addr == UART_SETUP))) - tx_uart_reset <= 1'b1; - else if ((axil_write_ready) && (awskd_addr[1:0] == UART_TXREG) && wskd_strb[1]) - tx_uart_reset <= wskd_data[12]; - else tx_uart_reset <= 1'b0; -`ifdef FORMAL - (* anyseq *) reg w_uart_tx, w_tx_busy; - assign tx_busy = w_uart_tx; - assign o_uart_tx = w_uart_tx; -`else -`ifdef USE_LITE_UART - txuartlite #( - .CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]) - ) tx ( - S_AXI_ACLK, - (tx_empty_n), - tx_data, - o_uart_tx, - tx_busy - ); -`else - wire cts_n; - assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT) && (i_cts_n); - txuart #( - .INITIAL_SETUP(INITIAL_SETUP) - ) tx ( - S_AXI_ACLK, - 1'b0, - uart_setup, - r_tx_break, - (tx_empty_n), - tx_data, - cts_n, - o_uart_tx, - tx_busy - ); -`endif -`endif - assign axil_tx_data = { - 16'h00, - i_cts_n, - txf_status[1:0], - txf_err, - ck_uart, - o_uart_tx, - tx_break, - (tx_busy | txf_status[0]), - (tx_busy | txf_status[0]) ? txf_axil_data : 8'b00 - }; - assign axil_fifo_data = {txf_status, rxf_status}; - initial r_preread = 0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) r_preread <= 0; - else if (axil_read_ready) r_preread <= 1; - else if (!S_AXI_RVALID || S_AXI_RREADY) r_preread <= 0; - always @(posedge S_AXI_ACLK) if (axil_read_ready) r_axil_addr <= arskd_addr; - always @(posedge S_AXI_ACLK) - if (!S_AXI_RVALID || S_AXI_RREADY) begin - casez (r_axil_addr) - UART_SETUP: axil_read_data <= {1'b0, uart_setup}; - UART_FIFO: axil_read_data <= axil_fifo_data; - UART_RXREG: axil_read_data <= axil_rx_data; - UART_TXREG: axil_read_data <= axil_tx_data; - endcase - if (OPT_LOWPOWER && !r_preread) axil_read_data <= 0; - end - function [C_AXI_DATA_WIDTH-1:0] apply_wstrb; - input [C_AXI_DATA_WIDTH-1:0] prior_data; - input [C_AXI_DATA_WIDTH-1:0] new_data; - input [C_AXI_DATA_WIDTH/8-1:0] wstrb; - integer k; - for (k = 0; k < C_AXI_DATA_WIDTH / 8; k = k + 1) begin - apply_wstrb[k*8+:8] = wstrb[k] ? new_data[k*8+:8] : prior_data[k*8+:8]; - end - endfunction - wire unused; - assign unused = &{ 1'b0, S_AXI_AWPROT, S_AXI_ARPROT, -S_AXI_ARADDR[ADDRLSB-1:0], -S_AXI_AWADDR[ADDRLSB-1:0], new_setup[31] }; -`ifdef FORMAL - reg f_past_valid; - initial f_past_valid = 0; - always @(posedge S_AXI_ACLK) f_past_valid <= 1; - localparam F_AXIL_LGDEPTH = 4; - wire [F_AXIL_LGDEPTH-1:0] faxil_rd_outstanding, faxil_wr_outstanding, faxil_awr_outstanding; - faxil_slave #( - .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), - .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), - .F_LGDEPTH(F_AXIL_LGDEPTH), - .F_AXI_MAXWAIT(4), - .F_AXI_MAXDELAY(4), - .F_AXI_MAXRSTALL(3), - .F_OPT_COVER_BURST(4) - ) faxil ( - .i_clk(S_AXI_ACLK), - .i_axi_reset_n(S_AXI_ARESETN), - .i_axi_awvalid(S_AXI_AWVALID), - .i_axi_awready(S_AXI_AWREADY), - .i_axi_awaddr(S_AXI_AWADDR), - .i_axi_awcache(4'h0), - .i_axi_awprot(S_AXI_AWPROT), - .i_axi_wvalid(S_AXI_WVALID), - .i_axi_wready(S_AXI_WREADY), - .i_axi_wdata(S_AXI_WDATA), - .i_axi_wstrb(S_AXI_WSTRB), - .i_axi_bvalid(S_AXI_BVALID), - .i_axi_bready(S_AXI_BREADY), - .i_axi_bresp(S_AXI_BRESP), - .i_axi_arvalid(S_AXI_ARVALID), - .i_axi_arready(S_AXI_ARREADY), - .i_axi_araddr(S_AXI_ARADDR), - .i_axi_arcache(4'h0), - .i_axi_arprot(S_AXI_ARPROT), - .i_axi_rvalid(S_AXI_RVALID), - .i_axi_rready(S_AXI_RREADY), - .i_axi_rdata(S_AXI_RDATA), - .i_axi_rresp(S_AXI_RRESP), - .f_axi_rd_outstanding(faxil_rd_outstanding), - .f_axi_wr_outstanding(faxil_wr_outstanding), - .f_axi_awr_outstanding(faxil_awr_outstanding) - ); - always @(*) - if (OPT_SKIDBUFFER) begin - assert (faxil_awr_outstanding == (S_AXI_BVALID ? 1 : 0) + (S_AXI_AWREADY ? 0 : 1)); - assert (faxil_wr_outstanding == (S_AXI_BVALID ? 1 : 0) + (S_AXI_WREADY ? 0 : 1)); - assert(faxil_rd_outstanding == (S_AXI_RVALID ? 1:0) -+ (r_preread ? 1:0) +(S_AXI_ARREADY ? 0:1)); - end else begin - assert (faxil_wr_outstanding == (S_AXI_BVALID ? 1 : 0)); - assert (faxil_awr_outstanding == faxil_wr_outstanding); - assert (faxil_rd_outstanding == (S_AXI_RVALID ? 1 : 0) + (r_preread ? 1 : 0)); - assert (S_AXI_ARREADY == (!S_AXI_RVALID && !r_preread)); - end -`ifdef VERIFIC - assert property (@(posedge S_AXI_ACLK) -disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY)) -S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_SETUP -|=> r_preread && r_axil_addr == UART_SETUP -##1 S_AXI_RVALID && axil_read_data -== { 1'b0, $past( - uart_setup - )}); - assert property (@(posedge S_AXI_ACLK) -disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY)) -S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2] == UART_FIFO -|=> r_preread && r_axil_addr == UART_FIFO -##1 S_AXI_RVALID && axil_read_data == $past( - axil_fifo_data - )); - assert property (@(posedge S_AXI_ACLK) -disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY)) -S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_RXREG -|=> r_preread && r_axil_addr == UART_RXREG -##1 S_AXI_RVALID && axil_read_data == $past( - axil_rx_data - )); - assert property (@(posedge S_AXI_ACLK) -disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY)) -S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_TXREG -|=> r_preread && r_axil_addr == UART_TXREG -##1 S_AXI_RVALID && axil_read_data == $past( - axil_tx_data - )); -`endif - always @(*) if (OPT_LOWPOWER && !S_AXI_RVALID) assert (S_AXI_RDATA == 0); -`endif -endmodule diff --git a/verilog/verilog/examples/cam.v b/verilog/verilog/examples/cam.v new file mode 100644 index 0000000000..892c6f0df6 --- /dev/null +++ b/verilog/verilog/examples/cam.v @@ -0,0 +1,58 @@ +// http://www.asic-world.com/code/hdl_models/cam.v +//----------------------------------------------------- +// Design Name : cam +// File Name : cam.v +// Function : CAM +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module cam ( + clk, // Cam clock + cam_enable, // Cam enable + cam_data_in, // Cam data to match + cam_hit_out, // Cam match has happened + cam_addr_out // Cam output address +); + parameter ADDR_WIDTH = 8; + parameter DEPTH = 1 << ADDR_WIDTH; + //------------Input Ports-------------- + input clk; + input cam_enable; + input [DEPTH-1:0] cam_data_in; + //----------Output Ports-------------- + output cam_hit_out; + output [ADDR_WIDTH-1:0] cam_addr_out; + //------------Internal Variables-------- + reg [ADDR_WIDTH-1:0] cam_addr_out; + reg cam_hit_out; + reg [ADDR_WIDTH-1:0] cam_addr_combo; + reg cam_hit_combo; + reg found_match; + integer i; + //-------------Code Starts Here------- + always @(cam_data_in) begin + cam_addr_combo = {ADDR_WIDTH{1'b0}}; + found_match = 1'b0; + cam_hit_combo = 1'b0; + for (i = 0; i < DEPTH; i = i + 1) begin + if (cam_data_in[i] && !found_match) begin + found_match = 1'b1; + cam_hit_combo = 1'b1; + cam_addr_combo = i; + end else begin + found_match = found_match; + cam_hit_combo = cam_hit_combo; + cam_addr_combo = cam_addr_combo; + end + end + end + // Register the outputs + always @(posedge clk) begin + if (cam_enable) begin + cam_hit_out <= cam_hit_combo; + cam_addr_out <= cam_addr_combo; + end else begin + cam_hit_out <= 1'b0; + cam_addr_out <= {ADDR_WIDTH{1'b0}}; + end + end +endmodule diff --git a/verilog/verilog/examples/decoder_using_case.v b/verilog/verilog/examples/decoder_using_case.v new file mode 100644 index 0000000000..3872981f1b --- /dev/null +++ b/verilog/verilog/examples/decoder_using_case.v @@ -0,0 +1,40 @@ +// http://www.asic-world.com/code/hdl_models/decoder_using_case.v +//----------------------------------------------------- +// Design Name : decoder_using_case +// File Name : decoder_using_case.v +// Function : decoder using case +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module decoder_using_case ( + binary_in, // 4 bit binary input + decoder_out, // 16-bit out + enable // Enable for the decoder +); + input [3:0] binary_in; + input enable; + output [15:0] decoder_out; + reg [15:0] decoder_out; + always @(enable or binary_in) begin + decoder_out = 0; + if (enable) begin + case (binary_in) + 4'h0: decoder_out = 16'h0001; + 4'h1: decoder_out = 16'h0002; + 4'h2: decoder_out = 16'h0004; + 4'h3: decoder_out = 16'h0008; + 4'h4: decoder_out = 16'h0010; + 4'h5: decoder_out = 16'h0020; + 4'h6: decoder_out = 16'h0040; + 4'h7: decoder_out = 16'h0080; + 4'h8: decoder_out = 16'h0100; + 4'h9: decoder_out = 16'h0200; + 4'hA: decoder_out = 16'h0400; + 4'hB: decoder_out = 16'h0800; + 4'hC: decoder_out = 16'h1000; + 4'hD: decoder_out = 16'h2000; + 4'hE: decoder_out = 16'h4000; + 4'hF: decoder_out = 16'h8000; + endcase + end + end +endmodule diff --git a/verilog/verilog/examples/dff_async_reset.v b/verilog/verilog/examples/dff_async_reset.v new file mode 100644 index 0000000000..1ada572692 --- /dev/null +++ b/verilog/verilog/examples/dff_async_reset.v @@ -0,0 +1,27 @@ +// http://www.asic-world.com/code/hdl_models/dff_async_reset.v +//----------------------------------------------------- +// Design Name : dff_async_reset +// File Name : dff_async_reset.v +// Function : D flip-flop async reset +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module dff_async_reset ( + data, // Data Input + clk, // Clock Input + reset, // Reset input + q // Q output +); + //-----------Input Ports--------------- + input data, clk, reset; + //-----------Output Ports--------------- + output q; + //------------Internal Variables-------- + reg q; + //-------------Code Starts Here--------- + always @(posedge clk or negedge reset) + if (~reset) begin + q <= 1'b0; + end else begin + q <= data; + end +endmodule //End Of Module dff_async_reset diff --git a/verilog/verilog/examples/dlatch_reset.v b/verilog/verilog/examples/dlatch_reset.v new file mode 100644 index 0000000000..68a89591dc --- /dev/null +++ b/verilog/verilog/examples/dlatch_reset.v @@ -0,0 +1,27 @@ +// http://www.asic-world.com/code/hdl_models/dlatch_reset.v +//----------------------------------------------------- +// Design Name : dlatch_reset +// File Name : dlatch_reset.v +// Function : DLATCH async reset +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module dlatch_reset ( + data, // Data Input + en, // LatchInput + reset, // Reset input + q // Q output +); + //-----------Input Ports--------------- + input data, en, reset; + //-----------Output Ports--------------- + output q; + //------------Internal Variables-------- + reg q; + //-------------Code Starts Here--------- + always @(en or reset or data) + if (~reset) begin + q <= 1'b0; + end else if (en) begin + q <= data; + end +endmodule //End Of Module dlatch_reset diff --git a/verilog/verilog/examples/fifo_rx.v b/verilog/verilog/examples/fifo_rx.v new file mode 100644 index 0000000000..c3bdde137b --- /dev/null +++ b/verilog/verilog/examples/fifo_rx.v @@ -0,0 +1,259 @@ +//+FHDR------------------------------------------------------------------------ +//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved +//GLADIC Open Source RTL +//----------------------------------------------------------------------------- +//FILE NAME : +//DEPARTMENT : IC Design / Verification +//AUTHOR : Felipe Fernandes da Costa +//AUTHOR'S EMAIL : +//----------------------------------------------------------------------------- +//RELEASE HISTORY +//VERSION DATE AUTHOR DESCRIPTION +//1.0 YYYY-MM-DD name +//----------------------------------------------------------------------------- +//KEYWORDS : General file searching keywords, leave blank if none. +//----------------------------------------------------------------------------- +//PURPOSE : ECSS_E_ST_50_12C_31_july_2008 +//----------------------------------------------------------------------------- +//PARAMETERS +//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS +//e.g.DATA_WIDTH [32,16] : width of the data : 32: +//----------------------------------------------------------------------------- +//REUSE ISSUES +//Reset Strategy : +//Clock Domains : +//Critical Timing : +//Test Features : +//Asynchronous I/F : +//Scan Methodology : +//Instantiations : +//Synthesizable (y/n) : +//Other : +//-FHDR------------------------------------------------------------------------ +module fifo_rx #( + parameter integer DWIDTH = 9, + parameter integer AWIDTH = 6 +) ( + input clock, + reset, + wr_en, + rd_en, + input [DWIDTH-1:0] data_in, + output reg f_full, + f_empty, + output reg open_slot_fct, + output reg overflow_credit_error, + output [DWIDTH-1:0] data_out, + output reg [AWIDTH-1:0] counter +); + reg [AWIDTH-1:0] wr_ptr; + reg [AWIDTH-1:0] rd_ptr; + reg [AWIDTH-1:0] credit_counter; + reg [1:0] state_data_write; + reg [1:0] next_state_data_write; + reg [1:0] state_data_read; + reg [1:0] next_state_data_read; + reg [1:0] state_open_slot; + reg [1:0] next_state_open_slot; + reg [10:0] counter_wait; + /****************************************/ + always @(*) begin + next_state_open_slot = state_open_slot; + case (state_open_slot) + 2'd0: begin + if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63) + begin + next_state_open_slot = 2'd1; + end else begin + next_state_open_slot = 2'd0; + end + end + 2'd1: begin + if (counter_wait != 11'd300) next_state_open_slot = 2'd1; + else next_state_open_slot = 2'd2; + end + 2'd2: begin + if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63) + begin + next_state_open_slot = 2'd2; + end else begin + next_state_open_slot = 2'd0; + end + end + default: begin + next_state_open_slot = 2'd0; + end + endcase + end + /****************************************/ + always @(*) begin + next_state_data_write = state_data_write; + case (state_data_write) + 2'd0: begin + if (wr_en && !f_full) begin + next_state_data_write = 2'd1; + end else begin + next_state_data_write = 2'd0; + end + end + 2'd1: begin + if (wr_en) begin + next_state_data_write = 2'd1; + end else begin + next_state_data_write = 2'd2; + end + end + 2'd2: begin + next_state_data_write = 2'd0; + end + default: begin + next_state_data_write = 2'd0; + end + endcase + end + /****************************************/ + always @(*) begin + next_state_data_read = state_data_read; + case (state_data_read) + 2'd0: begin + if (rd_en && !f_empty) begin + next_state_data_read = 2'd1; + end else begin + next_state_data_read = 2'd0; + end + end + 2'd1: begin + if (rd_en) begin + next_state_data_read = 2'd1; + end else begin + next_state_data_read = 2'd2; + end + end + 2'd2: begin + next_state_data_read = 2'd0; + end + default: begin + next_state_data_read = 2'd0; + end + endcase + end + always @(posedge clock or negedge reset) begin + if (!reset) begin + state_open_slot <= 2'd0; + open_slot_fct <= 1'b0; + counter_wait <= 11'd0; + end else begin + state_open_slot <= next_state_open_slot; + case (state_open_slot) + 2'd0: begin + if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63) + begin + open_slot_fct <= 1'b1; + counter_wait <= counter_wait + 11'd1; + end else begin + open_slot_fct <= 1'b0; + end + end + 2'd1: begin + if (counter_wait != 11'd300) counter_wait <= counter_wait + 11'd1; + else counter_wait <= counter_wait; + open_slot_fct <= 1'b1; + end + 2'd2: begin + counter_wait <= 11'd0; + open_slot_fct <= 1'b0; + end + default: begin + open_slot_fct <= open_slot_fct; + end + endcase + end + end + //Write pointer + always @(posedge clock or negedge reset) begin + if (!reset) begin + state_data_write <= 2'd0; + wr_ptr <= {(AWIDTH) {1'b0}}; + end else begin + state_data_write <= next_state_data_write; + case (state_data_write) + 2'd0: begin + wr_ptr <= wr_ptr; + end + 2'd1: begin + wr_ptr <= wr_ptr; + end + 2'd2: begin + wr_ptr <= wr_ptr + 6'd1; + end + default: begin + wr_ptr <= wr_ptr; + end + endcase + end + end + //FULL - EMPTY COUNTER + always @(posedge clock or negedge reset) begin + if (!reset) begin + f_full <= 1'b0; + f_empty <= 1'b0; + overflow_credit_error <= 1'b0; + counter <= {(AWIDTH) {1'b0}}; + end else begin + if (state_data_write == 2'd2) begin + counter <= counter + 6'd1; + end else begin + if (counter > 6'd0 && state_data_read == 2'd2) counter <= counter - 6'd1; + else counter <= counter; + end + if (counter > 6'd56) begin + overflow_credit_error <= 1'b1; + end else overflow_credit_error <= 1'b0; + if (counter == 6'd56) begin + f_full <= 1'b1; + end else begin + f_full <= 1'b0; + end + if (counter == 6'd0) begin + f_empty <= 1'b1; + end else begin + f_empty <= 1'b0; + end + end + end + //Read pointer + always @(posedge clock or negedge reset) begin + if (!reset) begin + rd_ptr <= {(AWIDTH) {1'b0}}; + state_data_read <= 2'd0; + end else begin + state_data_read <= next_state_data_read; + case (state_data_read) + 2'd0: begin + if (rd_en) begin + rd_ptr <= rd_ptr + 6'd1; + end else begin + rd_ptr <= rd_ptr; + end + end + 2'd1: begin + rd_ptr <= rd_ptr; + end + 2'd2: begin + rd_ptr <= rd_ptr; + end + default: begin + rd_ptr <= rd_ptr; + end + endcase + end + end + mem_data mem_dta_fifo_rx ( + .clock(clock), + .reset(reset), + .data_in(data_in), + .wr_ptr(wr_ptr), + .rd_ptr(rd_ptr), + .data_out(data_out) + ); +endmodule diff --git a/verilog/verilog/examples/function_non_ansi.v b/verilog/verilog/examples/function_non_ansi.v new file mode 100644 index 0000000000..fe35abe4e3 --- /dev/null +++ b/verilog/verilog/examples/function_non_ansi.v @@ -0,0 +1,15 @@ +module module0 (); + function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + begin + clkout_duty_chk = 1'b1; + end + endfunction +endmodule diff --git a/verilog/verilog/examples/generate_for.v b/verilog/verilog/examples/generate_for.v new file mode 100644 index 0000000000..9d91f58c76 --- /dev/null +++ b/verilog/verilog/examples/generate_for.v @@ -0,0 +1,19 @@ +module top (); + wire [2:0] out; + wire [2:0] out1; + wire [2:0] out2; + genvar i; + generate + for (i = 0; i < 3; i = i + 1) assign out[i] = i; + endgenerate + generate + for (i = 0; i < 3; i = i + 1) begin + assign out1[i] = i; + end + endgenerate + generate + for (i = 0; i < 3; i = i + 1) begin : test1 + assign out2[i] = i; + end + endgenerate +endmodule diff --git a/verilog/verilog/examples/lfsr_updown_tb.v b/verilog/verilog/examples/lfsr_updown_tb.v new file mode 100644 index 0000000000..b603937120 --- /dev/null +++ b/verilog/verilog/examples/lfsr_updown_tb.v @@ -0,0 +1,30 @@ +// http://www.asic-world.com/examples/verilog/lfsr.html#Random_Counter_(LFSR) +`define WIDTH 8 +module tb (); + reg clk; + reg reset; + reg enable; + reg up_down; + wire [`WIDTH-1 : 0] count; + wire overflow; + initial begin + $monitor("rst %b en %b updown %b cnt %b overflow %b", reset, enable, up_down, count, overflow); + clk = 0; + reset = 1; + enable = 0; + up_down = 0; + #10 reset = 0; + #1 enable = 1; + #20 up_down = 1; + #30 $finish; + end + always #1 clk = ~clk; + lfsr_updown U ( + .clk (clk), + .reset (reset), + .enable (enable), + .up_down (up_down), + .count (count), + .overflow(overflow) + ); +endmodule diff --git a/verilog/verilog/examples/parity_using_function2.v b/verilog/verilog/examples/parity_using_function2.v new file mode 100644 index 0000000000..87fabefd8a --- /dev/null +++ b/verilog/verilog/examples/parity_using_function2.v @@ -0,0 +1,28 @@ +// http://www.asic-world.com/code/hdl_models/parity_using_function2.v +//----------------------------------------------------- +// Design Name : parity_using_function2 +// File Name : parity_using_function2.v +// Function : Parity using function +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module parity_using_function2 ( + data_in, // 8 bit data in + parity_out // 1 bit parity out +); + output parity_out; + input [7:0] data_in; + reg parity_out; + function parity; + input [31:0] data; + integer i; + begin + parity = 0; + for (i = 0; i < 32; i = i + 1) begin + parity = parity ^ data[i]; + end + end + endfunction + always @(data_in) begin + parity_out = parity(data_in); + end +endmodule diff --git a/verilog/verilog/examples/pri_encoder_using_assign.v b/verilog/verilog/examples/pri_encoder_using_assign.v new file mode 100644 index 0000000000..da81b40f1b --- /dev/null +++ b/verilog/verilog/examples/pri_encoder_using_assign.v @@ -0,0 +1,33 @@ +//----------------------------------------------------- +// http://www.asic-world.com/code/hdl_models/pri_encoder_using_assign.v +// Design Name : pri_encoder_using_assign +// File Name : pri_encoder_using_assign.v +// Function : Pri Encoder using assign +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module pri_encoder_using_assign ( + binary_out, // 4 bit binary output + encoder_in, // 16-bit input + enable // Enable for the encoder +); + output [3:0] binary_out; + input enable; + input [15:0] encoder_in; + wire [3:0] binary_out; + assign binary_out = (!enable) ? 0 : ( + (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 : + (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 : + (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 : + (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 : + (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 : + (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 : + (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 : + (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 : + (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 : + (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 : + (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 : + (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 : + (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 : + (encoder_in == 16'bxx10_0000_0000_0000) ? 13 : + (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15); +endmodule diff --git a/verilog/verilog/examples/pri_encoder_using_if.v b/verilog/verilog/examples/pri_encoder_using_if.v new file mode 100644 index 0000000000..78bc46b6d9 --- /dev/null +++ b/verilog/verilog/examples/pri_encoder_using_if.v @@ -0,0 +1,53 @@ +//----------------------------------------------------- +// http://www.asic-world.com/code/hdl_models/pri_encoder_using_if.v +// Design Name : pri_encoder_using_if +// File Name : pri_encoder_using_if.v +// Function : Pri Encoder using If +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module pri_encoder_using_if ( + binary_out, // 4 bit binary output + encoder_in, // 16-bit input + enable // Enable for the encoder +); + output [3:0] binary_out; + input enable; + input [15:0] encoder_in; + reg [3:0] binary_out; + always @(enable or encoder_in) begin + binary_out = 0; + if (enable) begin + if (encoder_in == {{14{1'bx}}, 1'b1, {1{1'b0}}}) begin + binary_out = 1; + end else if (encoder_in == {{13{1'bx}}, 1'b1, {2{1'b0}}}) begin + binary_out = 2; + end else if (encoder_in == {{12{1'bx}}, 1'b1, {3{1'b0}}}) begin + binary_out = 3; + end else if (encoder_in == {{11{1'bx}}, 1'b1, {4{1'b0}}}) begin + binary_out = 4; + end else if (encoder_in == {{10{1'bx}}, 1'b1, {5{1'b0}}}) begin + binary_out = 5; + end else if (encoder_in == {{9{1'bx}}, 1'b1, {6{1'b0}}}) begin + binary_out = 6; + end else if (encoder_in == {{8{1'bx}}, 1'b1, {7{1'b0}}}) begin + binary_out = 7; + end else if (encoder_in == {{7{1'bx}}, 1'b1, {8{1'b0}}}) begin + binary_out = 8; + end else if (encoder_in == {{6{1'bx}}, 1'b1, {9{1'b0}}}) begin + binary_out = 9; + end else if (encoder_in == {{5{1'bx}}, 1'b1, {10{1'b0}}}) begin + binary_out = 10; + end else if (encoder_in == {{4{1'bx}}, 1'b1, {11{1'b0}}}) begin + binary_out = 11; + end else if (encoder_in == {{3{1'bx}}, 1'b1, {12{1'b0}}}) begin + binary_out = 12; + end else if (encoder_in == {{2{1'bx}}, 1'b1, {13{1'b0}}}) begin + binary_out = 13; + end else if (encoder_in == {{1{1'bx}}, 1'b1, {14{1'b0}}}) begin + binary_out = 14; + end else if (encoder_in == {1'b1, {15{1'b0}}}) begin + binary_out = 15; + end + end + end +endmodule diff --git a/verilog/verilog/examples/ram_sp_ar_sw.v b/verilog/verilog/examples/ram_sp_ar_sw.v new file mode 100644 index 0000000000..134d77a7b1 --- /dev/null +++ b/verilog/verilog/examples/ram_sp_ar_sw.v @@ -0,0 +1,48 @@ +// http://www.asic-world.com/code/hdl_models/ram_sp_ar_sw.v +//----------------------------------------------------- +// Design Name : ram_sp_ar_sw +// File Name : ram_sp_ar_sw.v +// Function : Asynchronous read write RAM +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module ram_sp_ar_sw ( + clk, // Clock Input + address, // Address Input + data, // Data bi-directional + cs, // Chip Select + we, // Write Enable/Read Enable + oe // Output Enable +); + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 8; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + //--------------Input Ports----------------------- + input clk; + input [ADDR_WIDTH-1:0] address; + input cs; + input we; + input oe; + //--------------Inout Ports----------------------- + inout [DATA_WIDTH-1:0] data; + //--------------Internal variables---------------- + reg [DATA_WIDTH-1:0] data_out; + reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1]; + //--------------Code Starts Here------------------ + // Tri-State Buffer control + // output : When we = 0, oe = 1, cs = 1 + assign data = (cs && oe && !we) ? data_out : 8'bz; + // Memory Write Block + // Write Operation : When we = 1, cs = 1 + always @(posedge clk) begin : MEM_WRITE + if (cs && we) begin + mem[address] = data; + end + end + // Memory Read Block + // Read Operation : When we = 0, oe = 1, cs = 1 + always @(address or cs or we or oe) begin : MEM_READ + if (cs && !we && oe) begin + data_out = mem[address]; + end + end +endmodule // End of Module ram_sp_ar_sw diff --git a/verilog/verilog/examples/ram_sp_sr_sw.v b/verilog/verilog/examples/ram_sp_sr_sw.v new file mode 100644 index 0000000000..3dff63b5e2 --- /dev/null +++ b/verilog/verilog/examples/ram_sp_sr_sw.v @@ -0,0 +1,52 @@ +// http://www.asic-world.com/code/hdl_models/ram_sp_sr_sw.v +//----------------------------------------------------- +// Design Name : ram_sp_sr_sw +// File Name : ram_sp_sr_sw.v +// Function : Synchronous read write RAM +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module ram_sp_sr_sw ( + clk, // Clock Input + address, // Address Input + data, // Data bi-directional + cs, // Chip Select + we, // Write Enable/Read Enable + oe // Output Enable +); + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 8; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + //--------------Input Ports----------------------- + input clk; + input [ADDR_WIDTH-1:0] address; + input cs; + input we; + input oe; + //--------------Inout Ports----------------------- + inout [DATA_WIDTH-1:0] data; + //--------------Internal variables---------------- + reg [DATA_WIDTH-1:0] data_out; + reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + reg oe_r; + //--------------Code Starts Here------------------ + // Tri-State Buffer control + // output : When we = 0, oe = 1, cs = 1 + assign data = (cs && oe && !we) ? data_out : 8'bz; + // Memory Write Block + // Write Operation : When we = 1, cs = 1 + always @(posedge clk) begin : MEM_WRITE + if (cs && we) begin + mem[address] = data; + end + end + // Memory Read Block + // Read Operation : When we = 0, oe = 1, cs = 1 + always @(posedge clk) begin : MEM_READ + if (cs && !we && oe) begin + data_out = mem[address]; + oe_r = 1; + end else begin + oe_r = 0; + end + end +endmodule // End of Module ram_sp_sr_sw diff --git a/verilog/verilog/examples/rom_using_file.v b/verilog/verilog/examples/rom_using_file.v new file mode 100644 index 0000000000..d3b069881d --- /dev/null +++ b/verilog/verilog/examples/rom_using_file.v @@ -0,0 +1,23 @@ +// http://www.asic-world.com/code/hdl_models/rom_using_file.v +//----------------------------------------------------- +// Design Name : rom_using_file +// File Name : rom_using_file.v +// Function : ROM using readmemh +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module rom_using_file ( + address, // Address input + data, // Data output + read_en, // Read Enable + ce // Chip Enable +); + input [7:0] address; + output [7:0] data; + input read_en; + input ce; + reg [7:0] mem[0:255]; + assign data = (ce && read_en) ? mem[address] : 8'b0; + initial begin + $readmemb("memory.list", mem); // memory_list is memory file + end +endmodule diff --git a/verilog/verilog/examples/rxuart.v b/verilog/verilog/examples/rxuart.v deleted file mode 100644 index b7429aca8a..0000000000 --- a/verilog/verilog/examples/rxuart.v +++ /dev/null @@ -1,176 +0,0 @@ -/* -Copyright (C) 2015-2021, Gisselquist Technology, LLC - -This program is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. (It's in the $(ROOT)/doc directory. Run make with no -target there if the PDF file isn't present.) If not, see - for a copy. - -License: GPL, v3, as defined and found on www.gnu.org, -http://www.gnu.org/licenses/gpl.html -*/ -`default_nettype none -module rxuart #( - parameter [30:0] INITIAL_SETUP = 31'd868, - parameter [3:0] RXU_BIT_ZERO = 4'h0, - RXU_BIT_ONE = 4'h1, - RXU_BIT_TWO = 4'h2, - RXU_BIT_THREE = 4'h3, - RXU_BIT_SEVEN = 4'h7, - RXU_PARITY = 4'h8, - RXU_STOP = 4'h9, - RXU_SECOND_STOP = 4'ha, - RXU_BREAK = 4'hd, - RXU_RESET_IDLE = 4'he, - RXU_IDLE = 4'hf -) ( - input wire i_clk, - i_reset, - input wire [30:0] i_setup, - input wire i_uart_rx, - output reg o_wr, - output reg [7:0] o_data, - output reg o_break, - output reg o_parity_err, - o_frame_err, - output wire o_ck_uart -); - wire [27:0] clocks_per_baud, break_condition, half_baud; - wire [1:0] data_bits; - wire use_parity, parity_even, dblstop, fixd_parity; - reg [29:0] r_setup; - reg [3:0] state; - reg [27:0] baud_counter; - reg zero_baud_counter; - reg q_uart, qq_uart, ck_uart; - reg [27:0] chg_counter; - reg line_synch; - reg half_baud_time; - reg [7:0] data_reg; - reg calc_parity; - reg pre_wr; - assign clocks_per_baud = {4'h0, r_setup[23:0]}; - assign data_bits = r_setup[29:28]; - assign dblstop = r_setup[27]; - assign use_parity = r_setup[26]; - assign fixd_parity = r_setup[25]; - assign parity_even = r_setup[24]; - assign break_condition = {r_setup[23:0], 4'h0}; - assign half_baud = {5'h00, r_setup[23:1]} - 28'h1; - initial q_uart = 1'b0; - initial qq_uart = 1'b0; - initial ck_uart = 1'b0; - always @(posedge i_clk) begin - q_uart <= i_uart_rx; - qq_uart <= q_uart; - ck_uart <= qq_uart; - end - assign o_ck_uart = ck_uart; - initial chg_counter = 28'h00; - always @(posedge i_clk) - if (i_reset) chg_counter <= 28'h00; - else if (qq_uart != ck_uart) chg_counter <= 28'h00; - else if (chg_counter < break_condition) chg_counter <= chg_counter + 1; - initial o_break = 1'b0; - always @(posedge i_clk) o_break <= ((chg_counter >= break_condition) && (~ck_uart)) ? 1'b1 : 1'b0; - initial line_synch = 1'b0; - always @(posedge i_clk) line_synch <= ((chg_counter >= break_condition) && (ck_uart)); - initial half_baud_time = 0; - always @(posedge i_clk) half_baud_time <= (~ck_uart) && (chg_counter >= half_baud); - initial r_setup = INITIAL_SETUP[29:0]; - always @(posedge i_clk) if (state >= RXU_RESET_IDLE) r_setup <= i_setup[29:0]; - initial state = RXU_RESET_IDLE; - always @(posedge i_clk) - if (i_reset) state <= RXU_RESET_IDLE; - else if (state == RXU_RESET_IDLE) begin - if (line_synch) state <= RXU_IDLE; - else state <= RXU_RESET_IDLE; - end else if (o_break) begin - state <= RXU_BREAK; - end else if (state == RXU_BREAK) begin - if (ck_uart) state <= RXU_IDLE; - else state <= RXU_BREAK; - end else if (state == RXU_IDLE) begin - if ((~ck_uart) && (half_baud_time)) begin - case (data_bits) - 2'b00: state <= RXU_BIT_ZERO; - 2'b01: state <= RXU_BIT_ONE; - 2'b10: state <= RXU_BIT_TWO; - 2'b11: state <= RXU_BIT_THREE; - endcase - end else state <= RXU_IDLE; - end else if (zero_baud_counter) begin - if (state < RXU_BIT_SEVEN) state <= state + 1; - else if (state == RXU_BIT_SEVEN) state <= (use_parity) ? RXU_PARITY : RXU_STOP; - else if (state == RXU_PARITY) state <= RXU_STOP; - else if (state == RXU_STOP) begin - if (~ck_uart) state <= RXU_RESET_IDLE; - else if (dblstop) state <= RXU_SECOND_STOP; - else state <= RXU_IDLE; - end else begin - if (~ck_uart) state <= RXU_RESET_IDLE; - else state <= RXU_IDLE; - end - end - always @(posedge i_clk) - if ((zero_baud_counter) && (state != RXU_PARITY)) - data_reg <= {ck_uart, data_reg[7:1]}; - always @(posedge i_clk) - if (state == RXU_IDLE) calc_parity <= 0; - else if (zero_baud_counter) calc_parity <= calc_parity ^ ck_uart; - initial o_parity_err = 1'b0; - always @(posedge i_clk) - if ((zero_baud_counter) && (state == RXU_PARITY)) begin - if (fixd_parity) o_parity_err <= (ck_uart ^ parity_even); - else if (parity_even) o_parity_err <= (calc_parity != ck_uart); - else o_parity_err <= (calc_parity == ck_uart); - end else if (state >= RXU_BREAK) o_parity_err <= 1'b0; - initial o_frame_err = 1'b0; - always @(posedge i_clk) - if ((zero_baud_counter) && ((state == RXU_STOP) || (state == RXU_SECOND_STOP))) - o_frame_err <= (o_frame_err) || (~ck_uart); - else if ((zero_baud_counter) || (state >= RXU_BREAK)) o_frame_err <= 1'b0; - initial o_data = 8'h00; - initial pre_wr = 1'b0; - always @(posedge i_clk) - if (i_reset) begin - pre_wr <= 1'b0; - o_data <= 8'h00; - end else if ((zero_baud_counter) && (state == RXU_STOP)) begin - pre_wr <= 1'b1; - case (data_bits) - 2'b00: o_data <= data_reg; - 2'b01: o_data <= {1'b0, data_reg[7:1]}; - 2'b10: o_data <= {2'b0, data_reg[7:2]}; - 2'b11: o_data <= {3'b0, data_reg[7:3]}; - endcase - end else if ((zero_baud_counter) || (state == RXU_IDLE)) pre_wr <= 1'b0; - initial o_wr = 1'b0; - always @(posedge i_clk) - if ((zero_baud_counter) || (state == RXU_IDLE)) o_wr <= (pre_wr) && (!i_reset); - else o_wr <= 1'b0; - always @(posedge i_clk) - if (i_reset) baud_counter <= clocks_per_baud - 28'h01; - else if (zero_baud_counter) baud_counter <= clocks_per_baud - 28'h01; - else - case (state) - RXU_RESET_IDLE: baud_counter <= clocks_per_baud - 28'h01; - RXU_BREAK: baud_counter <= clocks_per_baud - 28'h01; - RXU_IDLE: baud_counter <= clocks_per_baud - 28'h01; - default: baud_counter <= baud_counter - 28'h01; - endcase - initial zero_baud_counter = 1'b0; - always @(posedge i_clk) - if (state == RXU_IDLE) zero_baud_counter <= 1'b0; - else zero_baud_counter <= (baud_counter == 28'h01); -endmodule diff --git a/verilog/verilog/examples/rxuartlite.v b/verilog/verilog/examples/rxuartlite.v deleted file mode 100644 index 43630dee21..0000000000 --- a/verilog/verilog/examples/rxuartlite.v +++ /dev/null @@ -1,346 +0,0 @@ -/* -Copyright (C) 2015-2021, Gisselquist Technology, LLC - -This program is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. (It's in the $(ROOT)/doc directory. Run make with no -target there if the PDF file isn't present.) If not, see - for a copy. - -License: GPL, v3, as defined and found on www.gnu.org, -http://www.gnu.org/licenses/gpl.html -*/ -`default_nettype none -module rxuartlite #( - parameter TIMER_BITS = 10, -`ifdef FORMAL - parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, -`else - parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868, -`endif - parameter TB = TIMER_BITS, - parameter [ 3:0] RXUL_BIT_ZERO = 4'h0, - parameter [ 3:0] RXUL_BIT_ONE = 4'h1, - parameter [ 3:0] RXUL_BIT_TWO = 4'h2, - parameter [ 3:0] RXUL_BIT_THREE = 4'h3, - parameter [ 3:0] RXUL_BIT_FOUR = 4'h4, - parameter [ 3:0] RXUL_BIT_FIVE = 4'h5, - parameter [ 3:0] RXUL_BIT_SIX = 4'h6, - parameter [ 3:0] RXUL_BIT_SEVEN = 4'h7, - parameter [ 3:0] RXUL_STOP = 4'h8, - parameter [ 3:0] RXUL_WAIT = 4'h9, - parameter [ 3:0] RXUL_IDLE = 4'hf -) ( - input wire i_clk, - input wire i_uart_rx, - output reg o_wr, - output reg [7:0] o_data -); - wire [(TB-1):0] half_baud; - reg [3:0] state; - assign half_baud = {1'b0, CLOCKS_PER_BAUD[(TB-1):1]}; - reg [(TB-1):0] baud_counter; - reg zero_baud_counter; - reg q_uart, qq_uart, ck_uart; - reg [(TB-1):0] chg_counter; - reg half_baud_time; - reg [7:0] data_reg; - initial q_uart = 1'b1; - initial qq_uart = 1'b1; - initial ck_uart = 1'b1; - always @(posedge i_clk) {ck_uart, qq_uart, q_uart} <= {qq_uart, q_uart, i_uart_rx}; - initial chg_counter = {(TB) {1'b1}}; - always @(posedge i_clk) - if (qq_uart != ck_uart) chg_counter <= 0; - else if (chg_counter != {(TB) {1'b1}}) chg_counter <= chg_counter + 1; - initial half_baud_time = 0; - always @(posedge i_clk) half_baud_time <= (!ck_uart) && (chg_counter >= half_baud - 1'b1 - 1'b1); - initial state = RXUL_IDLE; - always @(posedge i_clk) - if (state == RXUL_IDLE) begin - state <= RXUL_IDLE; - if ((!ck_uart) && (half_baud_time)) state <= RXUL_BIT_ZERO; - end else if ((state >= RXUL_WAIT) && (ck_uart)) state <= RXUL_IDLE; - else if (zero_baud_counter) begin - if (state <= RXUL_STOP) state <= state + 1; - end - always @(posedge i_clk) - if ((zero_baud_counter) && (state != RXUL_STOP)) - data_reg <= {qq_uart, data_reg[7:1]}; - initial o_wr = 1'b0; - initial o_data = 8'h00; - always @(posedge i_clk) - if ((zero_baud_counter) && (state == RXUL_STOP) && (ck_uart)) begin - o_wr <= 1'b1; - o_data <= data_reg; - end else o_wr <= 1'b0; - initial baud_counter = 0; - always @(posedge i_clk) - if (((state == RXUL_IDLE)) && (!ck_uart) && (half_baud_time)) - baud_counter <= CLOCKS_PER_BAUD - 1'b1; - else if (state == RXUL_WAIT) baud_counter <= 0; - else if ((zero_baud_counter) && (state < RXUL_STOP)) baud_counter <= CLOCKS_PER_BAUD - 1'b1; - else if (!zero_baud_counter) baud_counter <= baud_counter - 1'b1; - initial zero_baud_counter = 1'b1; - always @(posedge i_clk) - if ((state == RXUL_IDLE) && (!ck_uart) && (half_baud_time)) zero_baud_counter <= 1'b0; - else if (state == RXUL_WAIT) zero_baud_counter <= 1'b1; - else if ((zero_baud_counter) && (state < RXUL_STOP)) zero_baud_counter <= 1'b0; - else if (baud_counter == 1) zero_baud_counter <= 1'b1; -`ifdef FORMAL - `define FORMAL_VERILATOR -`else -`ifdef VERILATOR - `define FORMAL_VERILATOR -`endif -`endif -`ifdef FORMAL - `define ASSUME assume - `define ASSERT assert -`ifdef VERIFIC - (* gclk *) wire gbl_clk; - global clocking @(posedge gbl_clk); - endclocking -`endif - localparam F_CKRES = 10; - (* anyseq *) wire f_tx_start; - (* anyconst *) wire [(F_CKRES-1):0] f_tx_step; - reg f_tx_zclk; - reg [(TB-1):0] f_tx_timer; - wire [7:0] f_rx_newdata; - reg [(TB-1):0] f_tx_baud; - wire f_tx_zbaud; - wire [(TB-1):0] f_max_baud_difference; - reg [(TB-1):0] f_baud_difference; - reg [(TB+3):0] f_tx_count, f_rx_count; - (* anyseq *) wire [7:0] f_tx_data; - wire f_txclk; - reg [1:0] f_rx_clock; - reg [(F_CKRES-1):0] f_tx_clock; - reg f_past_valid, f_past_valid_tx; - reg [9:0] f_tx_reg; - reg f_tx_busy; - initial f_past_valid = 1'b0; - always @(posedge i_clk) f_past_valid <= 1'b1; - initial f_rx_clock = 3'h0; - always @($global_clock) f_rx_clock <= f_rx_clock + 1'b1; - always @(*) assume (i_clk == f_rx_clock[1]); - localparam [(F_CKRES-1):0] F_MIDSTEP = {2'b01, {(F_CKRES - 2) {1'b0}}}; - localparam [(F_CKRES-1):0] F_HALFSTEP = F_MIDSTEP / 32; - localparam [(F_CKRES-1):0] F_MINSTEP = F_MIDSTEP - F_HALFSTEP + 1; - localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1; - initial assert (F_MINSTEP <= F_MIDSTEP); - initial assert (F_MIDSTEP <= F_MAXSTEP); - always @(*) - assume ((f_tx_step == F_MINSTEP) || (f_tx_step == F_MIDSTEP) || (f_tx_step == F_MAXSTEP)); - always @($global_clock) f_tx_clock <= f_tx_clock + f_tx_step; - assign f_txclk = f_tx_clock[F_CKRES-1]; - initial f_past_valid_tx = 1'b0; - always @(posedge f_txclk) f_past_valid_tx <= 1'b1; - initial assume (i_uart_rx); - always @(*) if (f_tx_busy) assume (!f_tx_start); - initial f_tx_baud = 0; - always @(posedge f_txclk) - if ((f_tx_zbaud) && ((f_tx_busy) || (f_tx_start))) f_tx_baud <= CLOCKS_PER_BAUD - 1'b1; - else if (!f_tx_zbaud) f_tx_baud <= f_tx_baud - 1'b1; - always @(*) `ASSERT(f_tx_baud < CLOCKS_PER_BAUD); - always @(*) if (!f_tx_busy) `ASSERT(f_tx_baud == 0); - assign f_tx_zbaud = (f_tx_baud == 0); - initial assume (f_tx_data == 0); - always @(posedge f_txclk) - if ((!f_tx_zbaud) || (f_tx_busy) || (!f_tx_start)) - assume (f_tx_data == $past(f_tx_data)); - always @($global_clock) - if ((f_past_valid) && (!$rose(f_txclk))) - assume ($stable(f_tx_data)); - else if (f_tx_busy) assume ($stable(f_tx_data)); - always @($global_clock) - if ((!f_past_valid) || (!$rose(f_txclk))) begin - assume ($stable(f_tx_start)); - assume ($stable(f_tx_data)); - end - initial f_tx_busy = 1'b0; - initial f_tx_reg = 0; - always @(posedge f_txclk) - if (!f_tx_zbaud) begin - `ASSERT(f_tx_busy); - end else begin - f_tx_reg <= {1'b0, f_tx_reg[9:1]}; - if (f_tx_start) f_tx_reg <= {1'b1, f_tx_data, 1'b0}; - end - always @(*) - if (!f_tx_zbaud) f_tx_busy <= 1'b1; - else if (|f_tx_reg) f_tx_busy <= 1'b1; - else f_tx_busy <= 1'b0; - always @(posedge f_txclk) - if (f_tx_reg[9]) `ASSERT(f_tx_reg[8:0] == {f_tx_data, 1'b0}); - else if (f_tx_reg[8]) `ASSERT(f_tx_reg[7:0] == f_tx_data[7:0]); - else if (f_tx_reg[7]) `ASSERT(f_tx_reg[6:0] == f_tx_data[7:1]); - else if (f_tx_reg[6]) `ASSERT(f_tx_reg[5:0] == f_tx_data[7:2]); - else if (f_tx_reg[5]) `ASSERT(f_tx_reg[4:0] == f_tx_data[7:3]); - else if (f_tx_reg[4]) `ASSERT(f_tx_reg[3:0] == f_tx_data[7:4]); - else if (f_tx_reg[3]) `ASSERT(f_tx_reg[2:0] == f_tx_data[7:5]); - else if (f_tx_reg[2]) `ASSERT(f_tx_reg[1:0] == f_tx_data[7:6]); - else if (f_tx_reg[1]) `ASSERT(f_tx_reg[0] == f_tx_data[7]); - initial f_tx_count = 0; - always @(posedge f_txclk) - if (!f_tx_busy) f_tx_count <= 0; - else f_tx_count <= f_tx_count + 1'b1; - always @(*) - if (f_tx_reg == 10'h0) - assume (i_uart_rx); - else assume (i_uart_rx == f_tx_reg[0]); - always @(posedge f_txclk) - if (!f_tx_busy) begin - if ((!f_past_valid_tx) || (!$past(f_tx_busy))) `ASSERT(f_tx_count == 0); - end else if (f_tx_reg[9]) `ASSERT(f_tx_count == CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[8]) `ASSERT(f_tx_count == 2 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[7]) `ASSERT(f_tx_count == 3 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[6]) `ASSERT(f_tx_count == 4 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[5]) `ASSERT(f_tx_count == 5 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[4]) `ASSERT(f_tx_count == 6 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[3]) `ASSERT(f_tx_count == 7 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[2]) `ASSERT(f_tx_count == 8 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[1]) `ASSERT(f_tx_count == 9 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else if (f_tx_reg[0]) `ASSERT(f_tx_count == 10 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - else `ASSERT(f_tx_count == 11 * CLOCKS_PER_BAUD - 1 - f_tx_baud); - initial f_rx_count = 0; - always @(posedge i_clk) - if (state == RXUL_IDLE) f_rx_count = (!ck_uart) ? (chg_counter + 2) : 0; - else f_rx_count <= f_rx_count + 1'b1; - always @(posedge i_clk) - if (state == 0) `ASSERT(f_rx_count == half_baud + (CLOCKS_PER_BAUD - baud_counter)); - else if (state == 1) `ASSERT(f_rx_count == half_baud + 2 * CLOCKS_PER_BAUD - baud_counter); - else if (state == 2) `ASSERT(f_rx_count == half_baud + 3 * CLOCKS_PER_BAUD - baud_counter); - else if (state == 3) `ASSERT(f_rx_count == half_baud + 4 * CLOCKS_PER_BAUD - baud_counter); - else if (state == 4) `ASSERT(f_rx_count == half_baud + 5 * CLOCKS_PER_BAUD - baud_counter); - else if (state == 5) `ASSERT(f_rx_count == half_baud + 6 * CLOCKS_PER_BAUD - baud_counter); - else if (state == 6) `ASSERT(f_rx_count == half_baud + 7 * CLOCKS_PER_BAUD - baud_counter); - else if (state == 7) `ASSERT(f_rx_count == half_baud + 8 * CLOCKS_PER_BAUD - baud_counter); - else if (state == 8) - `ASSERT( - (f_rx_count == half_baud + 9 * CLOCKS_PER_BAUD -- baud_counter) -||(f_rx_count == half_baud + 10 * CLOCKS_PER_BAUD -- baud_counter)); - always @(*) - `ASSERT( - ((!zero_baud_counter) -&&(state == RXUL_IDLE) -&&(baud_counter == 0)) -||((zero_baud_counter)&&(baud_counter == 0)) -||((!zero_baud_counter)&&(baud_counter != 0))); - always @(posedge i_clk) - if (!f_past_valid) - `ASSERT((state == RXUL_IDLE) && (baud_counter == 0) && (zero_baud_counter)); - always @(*) begin - `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h2); - `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h4); - `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h5); - `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h6); - `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h9); - `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'ha); - `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'hb); - `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'hd); - end - always @(posedge i_clk) - if ((f_past_valid) && ($past(state) >= RXUL_WAIT) && ($past(ck_uart))) - `ASSERT(state == RXUL_IDLE); - always @(posedge i_clk) - if ((f_past_valid) && ($past( - state - ) >= RXUL_WAIT) && (($past( - state - ) != RXUL_IDLE) || (state == RXUL_IDLE))) - `ASSERT(zero_baud_counter); - always @(posedge i_clk) - if ((f_past_valid) && ($past(state) == RXUL_IDLE) && (state == RXUL_IDLE)) begin - `ASSERT(($past(ck_uart)) || (chg_counter <= {1'b0, CLOCKS_PER_BAUD[(TB-1):1]})); - end - always @(posedge f_txclk) - if (!f_past_valid_tx) - `ASSERT((state == RXUL_IDLE) && (baud_counter == 0) && (zero_baud_counter) && (!f_tx_busy)); - wire [(TB+3):0] f_tx_count_two_clocks_ago; - assign f_tx_count_two_clocks_ago = f_tx_count - 2; - always @(*) - if (f_tx_count >= f_rx_count + 2) f_baud_difference = f_tx_count_two_clocks_ago - f_rx_count; - else f_baud_difference = f_rx_count - f_tx_count_two_clocks_ago; - localparam F_SYNC_DLY = 8; - reg [(TB+4+F_CKRES-1):0] f_sub_baud_difference; - reg [F_CKRES-1:0] ck_tx_clock; - reg [((F_SYNC_DLY-1)*F_CKRES)-1:0] q_tx_clock; - reg [TB+3:0] ck_tx_count; - reg [(F_SYNC_DLY-1)*(TB+4)-1:0] q_tx_count; - initial q_tx_count = 0; - initial ck_tx_count = 0; - initial q_tx_clock = 0; - initial ck_tx_clock = 0; - always @($global_clock) {ck_tx_clock, q_tx_clock} <= {q_tx_clock, f_tx_clock}; - always @($global_clock) {ck_tx_count, q_tx_count} <= {q_tx_count, f_tx_count}; - reg [TB+4+F_CKRES-1:0] f_ck_tx_time, f_rx_time; - always @(*) f_ck_tx_time = {ck_tx_count, !ck_tx_clock[F_CKRES-1], ck_tx_clock[F_CKRES-2:0]}; - always @(*) f_rx_time = {f_rx_count, !f_rx_clock[1], f_rx_clock[0], {(F_CKRES - 2) {1'b0}}}; - reg [TB+4+F_CKRES-1:0] f_signed_difference; - always @(*) f_signed_difference = f_ck_tx_time - f_rx_time; - always @(*) - if (f_signed_difference[TB+4+F_CKRES-1]) f_sub_baud_difference = -f_signed_difference; - else f_sub_baud_difference = f_signed_difference; - always @($global_clock) if (state == RXUL_WAIT) `ASSERT((!f_tx_busy) || (f_tx_reg[9:1] == 0)); - always @($global_clock) - if (state == RXUL_IDLE) begin - `ASSERT((!f_tx_busy) || (f_tx_reg[9]) || (f_tx_reg[9:1] == 0)); - if (!ck_uart); - else `ASSERT((f_tx_reg[9:1] == 0) || (f_tx_count < (3 + CLOCKS_PER_BAUD / 2))); - end else if (state == 0) - `ASSERT(f_sub_baud_difference <= 2 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - else if (state == 1) `ASSERT(f_sub_baud_difference <= 3 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - else if (state == 2) `ASSERT(f_sub_baud_difference <= 4 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - else if (state == 3) `ASSERT(f_sub_baud_difference <= 5 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - else if (state == 4) `ASSERT(f_sub_baud_difference <= 6 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - else if (state == 5) `ASSERT(f_sub_baud_difference <= 7 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - else if (state == 6) `ASSERT(f_sub_baud_difference <= 8 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - else if (state == 7) `ASSERT(f_sub_baud_difference <= 9 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - else if (state == 8) `ASSERT(f_sub_baud_difference <= 10 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); - always @(posedge i_clk) if (o_wr) `ASSERT(o_data == $past(f_tx_data, 4)); - always @(posedge i_clk) begin - if (state == 4'h0) `ASSERT(!data_reg[7]); - if (state == 4'h1) `ASSERT((data_reg[7] == $past(f_tx_data[0])) && (!data_reg[6])); - if (state == 4'h2) `ASSERT(data_reg[7:6] == $past(f_tx_data[1:0])); - if (state == 4'h3) `ASSERT(data_reg[7:5] == $past(f_tx_data[2:0])); - if (state == 4'h4) `ASSERT(data_reg[7:4] == $past(f_tx_data[3:0])); - if (state == 4'h5) `ASSERT(data_reg[7:3] == $past(f_tx_data[4:0])); - if (state == 4'h6) `ASSERT(data_reg[7:2] == $past(f_tx_data[5:0])); - if (state == 4'h7) `ASSERT(data_reg[7:1] == $past(f_tx_data[6:0])); - if (state == 4'h8) `ASSERT(data_reg[7:0] == $past(f_tx_data[7:0])); - end - always @(posedge i_clk) cover (o_wr); - always @(posedge i_clk) begin - cover (!ck_uart); - cover ((f_past_valid) && ($rose(ck_uart))); - cover ((zero_baud_counter) && (state == RXUL_BIT_ZERO)); - cover ((zero_baud_counter) && (state == RXUL_BIT_ONE)); - cover ((zero_baud_counter) && (state == RXUL_BIT_TWO)); - cover ((zero_baud_counter) && (state == RXUL_BIT_THREE)); - cover ((zero_baud_counter) && (state == RXUL_BIT_FOUR)); - cover ((zero_baud_counter) && (state == RXUL_BIT_FIVE)); - cover ((zero_baud_counter) && (state == RXUL_BIT_SIX)); - cover ((zero_baud_counter) && (state == RXUL_BIT_SEVEN)); - cover ((zero_baud_counter) && (state == RXUL_STOP)); - cover ((zero_baud_counter) && (state == RXUL_WAIT)); - end -`endif -`ifdef FORMAL_VERILATOR - always @(*) assert ((state == 4'hf) || (state <= RXUL_WAIT)); - always @(*) assert (zero_baud_counter == (baud_counter == 0) ? 1'b1 : 1'b0); - always @(*) assert (baud_counter <= CLOCKS_PER_BAUD - 1'b1); -`endif -endmodule diff --git a/verilog/verilog/examples/simple_subunit.v b/verilog/verilog/examples/simple_subunit.v new file mode 100644 index 0000000000..bb456e4188 --- /dev/null +++ b/verilog/verilog/examples/simple_subunit.v @@ -0,0 +1,19 @@ +module subunit0 ( + input a, + output b +); + assign b = a; +endmodule +module SimpleSubunit ( + input a, + output b +); + wire sig_subunit0_a; + wire sig_subunit0_b; + subunit0 subunit0_inst ( + .a(sig_subunit0_a), + .b(sig_subunit0_b) + ); + assign b = sig_subunit0_b; + assign sig_subunit0_a = a; +endmodule diff --git a/verilog/verilog/examples/skidbuffer.v b/verilog/verilog/examples/skidbuffer.v deleted file mode 100644 index ae9b23c8fb..0000000000 --- a/verilog/verilog/examples/skidbuffer.v +++ /dev/null @@ -1,156 +0,0 @@ -/* -Copyright (C) 2019-2021, Gisselquist Technology, LLC - -This program is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. (It's in the $(ROOT)/doc directory. Run make with no -target there if the PDF file isn't present.) If not, see - for a copy. - -License: GPL, v3, as defined and found on www.gnu.org, -http://www.gnu.org/licenses/gpl.html -*/ -`default_nettype none -module skidbuffer #( - parameter [0:0] OPT_LOWPOWER = 0, - parameter [0:0] OPT_OUTREG = 1, - parameter [0:0] OPT_PASSTHROUGH = 0, - parameter DW = 8 -) ( - input wire i_clk, - i_reset, - input wire i_valid, - output reg o_ready, - input wire [DW-1:0] i_data, - output reg o_valid, - input wire i_ready, - output reg [DW-1:0] o_data -); - reg [DW-1:0] r_data; - generate - if (OPT_PASSTHROUGH) begin : PASSTHROUGH - always @(*) o_ready = i_ready; - always @(*) o_valid = i_valid; - always @(*) - if (!i_valid && OPT_LOWPOWER) o_data = 0; - else o_data = i_data; - always @(*) r_data = 0; - end else begin : LOGIC - reg r_valid; - initial r_valid = 0; - always @(posedge i_clk) - if (i_reset) r_valid <= 0; - else if ((i_valid && o_ready) && (o_valid && !i_ready)) r_valid <= 1; - else if (i_ready) r_valid <= 0; - initial r_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && i_reset) r_data <= 0; - else if (OPT_LOWPOWER && (!o_valid || i_ready)) r_data <= 0; - else if ((!OPT_LOWPOWER || !OPT_OUTREG || i_valid) && o_ready) r_data <= i_data; - always @(*) o_ready = !r_valid; - if (!OPT_OUTREG) begin - always @(*) o_valid = !i_reset && (i_valid || r_valid); - always @(*) - if (r_valid) o_data = r_data; - else if (!OPT_LOWPOWER || i_valid) o_data = i_data; - else o_data = 0; - end else begin : REG_OUTPUT - initial o_valid = 0; - always @(posedge i_clk) - if (i_reset) o_valid <= 0; - else if (!o_valid || i_ready) o_valid <= (i_valid || r_valid); - initial o_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && i_reset) o_data <= 0; - else if (!o_valid || i_ready) begin - if (r_valid) o_data <= r_data; - else if (!OPT_LOWPOWER || i_valid) o_data <= i_data; - else o_data <= 0; - end - end - end - endgenerate -`ifdef FORMAL -`ifdef VERIFIC - `define FORMAL_VERIFIC -`endif -`endif -`ifdef FORMAL_VERIFIC - property RESET_CLEARS_IVALID; - @(posedge i_clk) i_reset |=> !i_valid; - endproperty - property IDATA_HELD_WHEN_NOT_READY; - @(posedge i_clk) disable iff (i_reset) i_valid && !o_ready |=> i_valid && $stable( - i_data - ); - endproperty -`ifdef SKIDBUFFER - assume property (IDATA_HELD_WHEN_NOT_READY); -`else - assert property (IDATA_HELD_WHEN_NOT_READY); -`endif - generate - if (!OPT_PASSTHROUGH) begin - assert property (@(posedge i_clk) OPT_OUTREG && i_reset |=> o_ready && !o_valid); - assert property (@(posedge i_clk) !OPT_OUTREG && i_reset |-> !o_valid); - assert property (@(posedge i_clk) -disable iff (i_reset) -o_valid && !i_ready -|=> (o_valid && $stable( - o_data - ))); - assert property (@(posedge i_clk) -disable iff (i_reset) -(i_valid && o_ready -&& (!OPT_OUTREG || o_valid) && !i_ready) -|=> (!o_ready && r_data == $past( - i_data - ))); - if (!OPT_OUTREG) begin - assert property (@(posedge i_clk) disable iff (i_reset) i_ready |=> (o_valid == i_valid)); - end else begin - assert property (@(posedge i_clk) disable iff (i_reset) i_valid && o_ready |=> o_valid); - assert property (@(posedge i_clk) -disable iff (i_reset) -!i_valid && o_ready && i_ready |=> !o_valid); - end - assert property (@(posedge i_clk) !o_ready && i_ready |=> o_ready); - if (OPT_LOWPOWER) begin - assert property (@(posedge i_clk) (OPT_OUTREG || !i_reset) && !o_valid |-> o_data == 0); - assert property (@(posedge i_clk) o_ready |-> r_data == 0); - end -`ifdef SKIDBUFFER - reg f_changed_data; - cover property (@(posedge i_clk) -disable iff (i_reset) -(!o_valid && !i_valid) -##1 i_valid && i_ready [*3] -##1 i_valid && !i_ready -##1 i_valid && i_ready [*2] -##1 i_valid && !i_ready [*2] -##1 i_valid && i_ready [*3] -##1 o_valid && i_ready [*0:5] -##1 (!o_valid && !i_valid && f_changed_data)); - initial f_changed_data = 0; - always @(posedge i_clk) - if (i_reset) f_changed_data <= 1; - else if (i_valid && $past(!i_valid || o_ready)) begin - if (i_data != $past(i_data + 1)) f_changed_data <= 0; - end else if (!i_valid && i_data != 0) f_changed_data <= 0; -`endif - end - endgenerate -`endif -endmodule -`ifndef YOSYS -`default_nettype wire -`endif diff --git a/verilog/verilog/examples/sram.v b/verilog/verilog/examples/sram.v new file mode 100644 index 0000000000..f580a2be37 --- /dev/null +++ b/verilog/verilog/examples/sram.v @@ -0,0 +1,39 @@ +// comment 0 +// comment 1 +// comment with some indinet +/** + * https://timetoexplore.net/blog/block-ram-in-verilog-with-vivado + * simple example of sram + */ +module sram #( + // widht of address + parameter ADDR_WIDTH = 8, + // widht of memory cell in memory + DATA_WIDTH = 8, + // number of cells in memory + DEPTH = 256 +) ( + // main clock signal + input wire i_clk, + input wire [ADDR_WIDTH-1:0] i_addr, + // write enable signal + input wire i_write, + // input data + input wire [DATA_WIDTH-1:0] i_data, + // output data + output reg [DATA_WIDTH-1:0] o_data +); + // main memory + reg [DATA_WIDTH-1:0] memory_array[0:DEPTH-1]; + // the main write/read process + always @(posedge i_clk) begin + // write or read decision + if (i_write) begin + // write data + memory_array[i_addr] <= i_data; + end else begin + // read data + o_data <= memory_array[i_addr]; + end + end +endmodule diff --git a/verilog/verilog/examples/test_verilog_primitives.v b/verilog/verilog/examples/test_verilog_primitives.v new file mode 100644 index 0000000000..3de0898332 --- /dev/null +++ b/verilog/verilog/examples/test_verilog_primitives.v @@ -0,0 +1,37 @@ +// Test Scenario to validate correct translation +// Refer: https://github.com/Nic30/hdlConvertor/issues/173 +module dummy ( + c, + a, + b +); + output c; + input a, b; + and a1 (c, a, b); +endmodule +module d2 ( + y, + a +); + output y; + input a; + not n1 (y, a); +endmodule +module example ( + a, + b, + c, + d +); + input a, b, c; + output d; + wire tmp; + wire tmp2; + and a1 (tmp, a, b); + dummy du ( + tmp2, + b, + c + ); + or o1 (d, tmp, tmp2); +endmodule diff --git a/verilog/verilog/examples/txuart.v b/verilog/verilog/examples/txuart.v deleted file mode 100644 index 3547bc4f8c..0000000000 --- a/verilog/verilog/examples/txuart.v +++ /dev/null @@ -1,705 +0,0 @@ -/* -Copyright (C) 2015-2021, Gisselquist Technology, LLC - -This program is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. (It's in the $(ROOT)/doc directory. Run make with no -target there if the PDF file isn't present.) If not, see - for a copy. - -License: GPL, v3, as defined and found on www.gnu.org, -http://www.gnu.org/licenses/gpl.html -*/ -`default_nettype none -module txuart #( - parameter [30:0] INITIAL_SETUP = 31'd868, - parameter [3:0] TXU_BIT_ZERO = 4'h0, - parameter [3:0] TXU_BIT_ONE = 4'h1, - parameter [3:0] TXU_BIT_TWO = 4'h2, - parameter [3:0] TXU_BIT_THREE = 4'h3, - parameter [3:0] TXU_BIT_SEVEN = 4'h7, - parameter [3:0] TXU_PARITY = 4'h8, - parameter [3:0] TXU_STOP = 4'h9, - parameter [3:0] TXU_SECOND_STOP = 4'ha, - parameter [3:0] TXU_BREAK = 4'he, - parameter [3:0] TXU_IDLE = 4'hf -) ( - input wire i_clk, - i_reset, - input wire [30:0] i_setup, - input wire i_break, - input wire i_wr, - input wire [7:0] i_data, - input wire i_cts_n, - output reg o_uart_tx, - output wire o_busy -); - wire [27:0] clocks_per_baud, break_condition; - wire [1:0] i_data_bits, data_bits; - wire use_parity, parity_odd, dblstop, fixd_parity, fixdp_value, hw_flow_control, i_parity_odd; - reg [30:0] r_setup; - assign clocks_per_baud = {4'h0, r_setup[23:0]}; - assign break_condition = {r_setup[23:0], 4'h0}; - assign hw_flow_control = !r_setup[30]; - assign i_data_bits = i_setup[29:28]; - assign data_bits = r_setup[29:28]; - assign dblstop = r_setup[27]; - assign use_parity = r_setup[26]; - assign fixd_parity = r_setup[25]; - assign i_parity_odd = i_setup[24]; - assign parity_odd = r_setup[24]; - assign fixdp_value = r_setup[24]; - reg [27:0] baud_counter; - reg [ 3:0] state; - reg [ 7:0] lcl_data; - reg calc_parity, r_busy, zero_baud_counter, last_state; - reg q_cts_n, qq_cts_n, ck_cts; - always @(posedge i_clk) {qq_cts_n, q_cts_n} <= {q_cts_n, i_cts_n}; - always @(posedge i_clk) ck_cts <= (!qq_cts_n) || (!hw_flow_control); - initial r_busy = 1'b1; - initial state = TXU_IDLE; - always @(posedge i_clk) - if (i_reset) begin - r_busy <= 1'b1; - state <= TXU_IDLE; - end else if (i_break) begin - state <= TXU_BREAK; - r_busy <= 1'b1; - end else if (!zero_baud_counter) begin - r_busy <= 1'b1; - end else if (state == TXU_BREAK) begin - state <= TXU_IDLE; - r_busy <= !ck_cts; - end else if (state == TXU_IDLE) begin - if ((i_wr) && (!r_busy)) begin - r_busy <= 1'b1; - case (i_data_bits) - 2'b00: state <= TXU_BIT_ZERO; - 2'b01: state <= TXU_BIT_ONE; - 2'b10: state <= TXU_BIT_TWO; - 2'b11: state <= TXU_BIT_THREE; - endcase - end else begin - r_busy <= !ck_cts; - end - end else begin - r_busy <= 1'b1; - if (state[3] == 0) begin - if (state == TXU_BIT_SEVEN) state <= (use_parity) ? TXU_PARITY : TXU_STOP; - else state <= state + 1; - end else if (state == TXU_PARITY) begin - state <= TXU_STOP; - end else if (state == TXU_STOP) begin - if (dblstop) state <= TXU_SECOND_STOP; - else state <= TXU_IDLE; - end else begin - state <= TXU_IDLE; - end - end - assign o_busy = (r_busy); - initial r_setup = INITIAL_SETUP; - always @(posedge i_clk) if (!o_busy) r_setup <= i_setup; - initial lcl_data = 8'hff; - always @(posedge i_clk) - if (!r_busy) lcl_data <= i_data; - else if (zero_baud_counter) lcl_data <= {1'b0, lcl_data[7:1]}; - initial o_uart_tx = 1'b1; - always @(posedge i_clk) - if (i_reset) o_uart_tx <= 1'b1; - else if ((i_break) || ((i_wr) && (!r_busy))) o_uart_tx <= 1'b0; - else if (zero_baud_counter) - casez (state) - 4'b0???: o_uart_tx <= lcl_data[0]; - TXU_PARITY: o_uart_tx <= calc_parity; - default: o_uart_tx <= 1'b1; - endcase - initial calc_parity = 1'b0; - always @(posedge i_clk) - if (!o_busy) calc_parity <= i_setup[24]; - else if (fixd_parity) calc_parity <= fixdp_value; - else if (zero_baud_counter) begin - if (state[3] == 0) calc_parity <= calc_parity ^ lcl_data[0]; - else if (state == TXU_IDLE) calc_parity <= parity_odd; - end else if (!r_busy) calc_parity <= parity_odd; - initial zero_baud_counter = 1'b0; - initial baud_counter = 28'h05; - always @(posedge i_clk) begin - zero_baud_counter <= (baud_counter == 28'h01); - if ((i_reset) || (i_break)) begin - baud_counter <= break_condition; - zero_baud_counter <= 1'b0; - end else if (!zero_baud_counter) baud_counter <= baud_counter - 28'h01; - else if (state == TXU_BREAK) begin - baud_counter <= 0; - zero_baud_counter <= 1'b1; - end else if (state == TXU_IDLE) begin - baud_counter <= 28'h0; - zero_baud_counter <= 1'b1; - if ((i_wr) && (!r_busy)) begin - baud_counter <= {4'h0, i_setup[23:0]} - 28'h01; - zero_baud_counter <= 1'b0; - end - end else if (last_state) baud_counter <= clocks_per_baud - 28'h02; - else baud_counter <= clocks_per_baud - 28'h01; - end - initial last_state = 1'b0; - always @(posedge i_clk) - if (dblstop) last_state <= (state == TXU_SECOND_STOP); - else last_state <= (state == TXU_STOP); - wire unused; - assign unused = &{1'b0, i_parity_odd, data_bits}; -`ifdef FORMAL - reg fsv_parity; - reg [30:0] fsv_setup; - reg [7:0] fsv_data; - reg f_past_valid; - reg [5:0] f_five_seq; - reg [6:0] f_six_seq; - reg [7:0] f_seven_seq; - reg [8:0] f_eight_seq; - reg [2:0] f_stop_seq; - initial f_past_valid = 1'b0; - always @(posedge i_clk) f_past_valid <= 1'b1; - always @(posedge i_clk) if ((i_wr) && (!o_busy)) fsv_data <= i_data; - initial fsv_setup = INITIAL_SETUP; - always @(posedge i_clk) if (!o_busy) fsv_setup <= i_setup; - always @(*) assert (r_setup == fsv_setup); - always @(posedge i_clk) assert (zero_baud_counter == (baud_counter == 0)); - always @(*) if (!o_busy) assert (zero_baud_counter); - /* -* -* Will only pass if !i_break && !i_reset, otherwise the setup can -* change in the middle of this operation -* -always @(posedge i_clk) -if ((f_past_valid)&&(!$past(i_reset))&&(!$past(i_break)) -&&(($past(o_busy))||($past(i_wr)))) -assert(baud_counter <= { fsv_setup[23:0], 4'h0 }); -*/ - always @(posedge i_clk) - if ((f_past_valid) && (!$past( - zero_baud_counter - )) && (!$past( - i_reset - )) && (!$past( - i_break - ))) begin - assert ($stable(o_uart_tx)); - assert ($stable(state)); - assert ($stable(lcl_data)); - if ((state != TXU_IDLE) && (state != TXU_BREAK)) assert ($stable(calc_parity)); - assert (baud_counter == $past(baud_counter) - 1'b1); - end - initial f_five_seq = 0; - always @(posedge i_clk) - if ((i_reset) || (i_break)) f_five_seq = 0; - else if ((state == TXU_IDLE) && (i_wr) && (!o_busy) && (i_data_bits == 2'b11)) f_five_seq <= 1; - else if (zero_baud_counter) f_five_seq <= f_five_seq << 1; - always @(*) - if (|f_five_seq) begin - assert (fsv_setup[29:28] == data_bits); - assert (data_bits == 2'b11); - assert (baud_counter < fsv_setup[23:0]); - assert (1'b0 == |f_six_seq); - assert (1'b0 == |f_seven_seq); - assert (1'b0 == |f_eight_seq); - assert (r_busy); - assert (state > 4'h2); - end - always @(*) - case (f_five_seq) - 6'h00: begin - assert (1); - end - 6'h01: begin - assert (state == 4'h3); - assert (o_uart_tx == 1'b0); - assert (lcl_data[4:0] == fsv_data[4:0]); - if (!fixd_parity) assert (calc_parity == parity_odd); - end - 6'h02: begin - assert (state == 4'h4); - assert (o_uart_tx == fsv_data[0]); - assert (lcl_data[3:0] == fsv_data[4:1]); - if (!fixd_parity) assert (calc_parity == fsv_data[0] ^ parity_odd); - end - 6'h04: begin - assert (state == 4'h5); - assert (o_uart_tx == fsv_data[1]); - assert (lcl_data[2:0] == fsv_data[4:2]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[1:0]) ^ parity_odd); - end - 6'h08: begin - assert (state == 4'h6); - assert (o_uart_tx == fsv_data[2]); - assert (lcl_data[1:0] == fsv_data[4:3]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[2:0]) ^ parity_odd); - end - 6'h10: begin - assert (state == 4'h7); - assert (o_uart_tx == fsv_data[3]); - assert (lcl_data[0] == fsv_data[4]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[3:0]) ^ parity_odd); - end - 6'h20: begin - if (use_parity) - assert (state == 4'h8); - else assert (state == 4'h9); - assert (o_uart_tx == fsv_data[4]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[4:0]) ^ parity_odd); - end - default: begin - assert (0); - end - endcase - initial f_six_seq = 0; - always @(posedge i_clk) - if ((i_reset) || (i_break)) f_six_seq = 0; - else if ((state == TXU_IDLE) && (i_wr) && (!o_busy) && (i_data_bits == 2'b10)) f_six_seq <= 1; - else if (zero_baud_counter) f_six_seq <= f_six_seq << 1; - always @(*) - if (|f_six_seq) begin - assert (fsv_setup[29:28] == 2'b10); - assert (fsv_setup[29:28] == data_bits); - assert (baud_counter < fsv_setup[23:0]); - assert (1'b0 == |f_five_seq); - assert (1'b0 == |f_seven_seq); - assert (1'b0 == |f_eight_seq); - assert (r_busy); - assert (state > 4'h1); - end - always @(*) - case (f_six_seq) - 7'h00: begin - assert (1); - end - 7'h01: begin - assert (state == 4'h2); - assert (o_uart_tx == 1'b0); - assert (lcl_data[5:0] == fsv_data[5:0]); - if (!fixd_parity) assert (calc_parity == parity_odd); - end - 7'h02: begin - assert (state == 4'h3); - assert (o_uart_tx == fsv_data[0]); - assert (lcl_data[4:0] == fsv_data[5:1]); - if (!fixd_parity) assert (calc_parity == fsv_data[0] ^ parity_odd); - end - 7'h04: begin - assert (state == 4'h4); - assert (o_uart_tx == fsv_data[1]); - assert (lcl_data[3:0] == fsv_data[5:2]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[1:0]) ^ parity_odd); - end - 7'h08: begin - assert (state == 4'h5); - assert (o_uart_tx == fsv_data[2]); - assert (lcl_data[2:0] == fsv_data[5:3]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[2:0]) ^ parity_odd); - end - 7'h10: begin - assert (state == 4'h6); - assert (o_uart_tx == fsv_data[3]); - assert (lcl_data[1:0] == fsv_data[5:4]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[3:0]) ^ parity_odd); - end - 7'h20: begin - assert (state == 4'h7); - assert (lcl_data[0] == fsv_data[5]); - assert (o_uart_tx == fsv_data[4]); - if (!fixd_parity) assert (calc_parity == ((^fsv_data[4:0]) ^ parity_odd)); - end - 7'h40: begin - if (use_parity) - assert (state == 4'h8); - else assert (state == 4'h9); - assert (o_uart_tx == fsv_data[5]); - if (!fixd_parity) assert (calc_parity == ((^fsv_data[5:0]) ^ parity_odd)); - end - default: begin - if (f_past_valid) assert (0); - end - endcase - initial f_seven_seq = 0; - always @(posedge i_clk) - if ((i_reset) || (i_break)) f_seven_seq = 0; - else if ((state == TXU_IDLE) && (i_wr) && (!o_busy) && (i_data_bits == 2'b01)) f_seven_seq <= 1; - else if (zero_baud_counter) f_seven_seq <= f_seven_seq << 1; - always @(*) - if (|f_seven_seq) begin - assert (fsv_setup[29:28] == 2'b01); - assert (fsv_setup[29:28] == data_bits); - assert (baud_counter < fsv_setup[23:0]); - assert (1'b0 == |f_five_seq); - assert (1'b0 == |f_six_seq); - assert (1'b0 == |f_eight_seq); - assert (r_busy); - assert (state != 4'h0); - end - always @(*) - case (f_seven_seq) - 8'h00: begin - assert (1); - end - 8'h01: begin - assert (state == 4'h1); - assert (o_uart_tx == 1'b0); - assert (lcl_data[6:0] == fsv_data[6:0]); - if (!fixd_parity) assert (calc_parity == parity_odd); - end - 8'h02: begin - assert (state == 4'h2); - assert (o_uart_tx == fsv_data[0]); - assert (lcl_data[5:0] == fsv_data[6:1]); - if (!fixd_parity) assert (calc_parity == fsv_data[0] ^ parity_odd); - end - 8'h04: begin - assert (state == 4'h3); - assert (o_uart_tx == fsv_data[1]); - assert (lcl_data[4:0] == fsv_data[6:2]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[1:0]) ^ parity_odd); - end - 8'h08: begin - assert (state == 4'h4); - assert (o_uart_tx == fsv_data[2]); - assert (lcl_data[3:0] == fsv_data[6:3]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[2:0]) ^ parity_odd); - end - 8'h10: begin - assert (state == 4'h5); - assert (o_uart_tx == fsv_data[3]); - assert (lcl_data[2:0] == fsv_data[6:4]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[3:0]) ^ parity_odd); - end - 8'h20: begin - assert (state == 4'h6); - assert (o_uart_tx == fsv_data[4]); - assert (lcl_data[1:0] == fsv_data[6:5]); - if (!fixd_parity) assert (calc_parity == ((^fsv_data[4:0]) ^ parity_odd)); - end - 8'h40: begin - assert (state == 4'h7); - assert (lcl_data[0] == fsv_data[6]); - assert (o_uart_tx == fsv_data[5]); - if (!fixd_parity) assert (calc_parity == ((^fsv_data[5:0]) ^ parity_odd)); - end - 8'h80: begin - if (use_parity) - assert (state == 4'h8); - else assert (state == 4'h9); - assert (o_uart_tx == fsv_data[6]); - if (!fixd_parity) assert (calc_parity == ((^fsv_data[6:0]) ^ parity_odd)); - end - default: begin - if (f_past_valid) assert (0); - end - endcase - initial f_eight_seq = 0; - always @(posedge i_clk) - if ((i_reset) || (i_break)) f_eight_seq = 0; - else if ((state == TXU_IDLE) && (i_wr) && (!o_busy) && (i_data_bits == 2'b00)) f_eight_seq <= 1; - else if (zero_baud_counter) f_eight_seq <= f_eight_seq << 1; - always @(*) - if (|f_eight_seq) begin - assert (fsv_setup[29:28] == 2'b00); - assert (fsv_setup[29:28] == data_bits); - assert (baud_counter < {6'h0, fsv_setup[23:0]}); - assert (1'b0 == |f_five_seq); - assert (1'b0 == |f_six_seq); - assert (1'b0 == |f_seven_seq); - assert (r_busy); - end - always @(*) - case (f_eight_seq) - 9'h000: begin - assert (1); - end - 9'h001: begin - assert (state == 4'h0); - assert (o_uart_tx == 1'b0); - assert (lcl_data[7:0] == fsv_data[7:0]); - if (!fixd_parity) assert (calc_parity == parity_odd); - end - 9'h002: begin - assert (state == 4'h1); - assert (o_uart_tx == fsv_data[0]); - assert (lcl_data[6:0] == fsv_data[7:1]); - if (!fixd_parity) assert (calc_parity == fsv_data[0] ^ parity_odd); - end - 9'h004: begin - assert (state == 4'h2); - assert (o_uart_tx == fsv_data[1]); - assert (lcl_data[5:0] == fsv_data[7:2]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[1:0]) ^ parity_odd); - end - 9'h008: begin - assert (state == 4'h3); - assert (o_uart_tx == fsv_data[2]); - assert (lcl_data[4:0] == fsv_data[7:3]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[2:0]) ^ parity_odd); - end - 9'h010: begin - assert (state == 4'h4); - assert (o_uart_tx == fsv_data[3]); - assert (lcl_data[3:0] == fsv_data[7:4]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[3:0]) ^ parity_odd); - end - 9'h020: begin - assert (state == 4'h5); - assert (o_uart_tx == fsv_data[4]); - assert (lcl_data[2:0] == fsv_data[7:5]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[4:0]) ^ parity_odd); - end - 9'h040: begin - assert (state == 4'h6); - assert (o_uart_tx == fsv_data[5]); - assert (lcl_data[1:0] == fsv_data[7:6]); - if (!fixd_parity) assert (calc_parity == (^fsv_data[5:0]) ^ parity_odd); - end - 9'h080: begin - assert (state == 4'h7); - assert (o_uart_tx == fsv_data[6]); - assert (lcl_data[0] == fsv_data[7]); - if (!fixd_parity) assert (calc_parity == ((^fsv_data[6:0]) ^ parity_odd)); - end - 9'h100: begin - if (use_parity) - assert (state == 4'h8); - else assert (state == 4'h9); - assert (o_uart_tx == fsv_data[7]); - if (!fixd_parity) assert (calc_parity == ((^fsv_data[7:0]) ^ parity_odd)); - end - default: begin - if (f_past_valid) assert (0); - end - endcase - always @(posedge i_clk) - if (((|f_five_seq[5:0]) || (|f_six_seq[6:0]) || (|f_seven_seq[7:0]) -|| (|f_eight_seq[8:0])) -&& ($past( - zero_baud_counter - ))) - assert (baud_counter == {4'h0, fsv_setup[23:0]} - 1); - initial f_stop_seq = 1'b0; - always @(posedge i_clk) - if ((i_reset) || (i_break)) f_stop_seq <= 0; - else if (zero_baud_counter) begin - f_stop_seq <= 0; - if (f_stop_seq[0]) begin - if (dblstop) f_stop_seq[1] <= 1'b1; - else f_stop_seq[2] <= 1'b1; - end - if (f_stop_seq[1]) f_stop_seq[2] <= 1'b1; - if (f_eight_seq[8] | f_seven_seq[7] | f_six_seq[6] | f_five_seq[5]) begin - if (use_parity) f_stop_seq[0] <= 1'b1; - else if (dblstop) f_stop_seq[1] <= 1'b1; - else f_stop_seq[2] <= 1'b1; - end - end - always @(*) - if (|f_stop_seq) begin - assert (1'b0 == |f_five_seq[4:0]); - assert (1'b0 == |f_six_seq[5:0]); - assert (1'b0 == |f_seven_seq[6:0]); - assert (1'b0 == |f_eight_seq[7:0]); - assert (r_busy); - end - always @(*) - if (f_stop_seq[0]) begin - if (dblstop) - assert (state == TXU_STOP); - else assert (state == TXU_STOP); - assert (use_parity); - assert (o_uart_tx == fsv_parity); - end - - always @(*) - if (f_stop_seq[1]) begin - assert (state == TXU_SECOND_STOP); - assert (dblstop); - assert (o_uart_tx); - end - always @(*) - if (f_stop_seq[2]) begin - assert (state == 4'hf); - assert (o_uart_tx); - assert (baud_counter < fsv_setup[23:0] - 1'b1); - end - - always @(*) - if (fsv_setup[25]) fsv_parity <= fsv_setup[24]; - else - case (fsv_setup[29:28]) - 2'b00: fsv_parity = (^fsv_data[7:0]) ^ fsv_setup[24]; - 2'b01: fsv_parity = (^fsv_data[6:0]) ^ fsv_setup[24]; - 2'b10: fsv_parity = (^fsv_data[5:0]) ^ fsv_setup[24]; - 2'b11: fsv_parity = (^fsv_data[4:0]) ^ fsv_setup[24]; - endcase - reg [1:0] f_break_seq; - initial f_break_seq = 2'b00; - always @(posedge i_clk) - if (i_reset) f_break_seq <= 2'b00; - else if (i_break) f_break_seq <= 2'b01; - else if (!zero_baud_counter) f_break_seq <= {|f_break_seq, 1'b0}; - else f_break_seq <= 0; - always @(posedge i_clk) - if (f_break_seq[0]) - assert (baud_counter == {$past(fsv_setup[23:0]), 4'h0}); - always @(posedge i_clk) - if ((f_past_valid) && ($past(f_break_seq[1])) && (state != TXU_BREAK)) begin - assert (state == TXU_IDLE); - assert (o_uart_tx == 1'b1); - end - always @(*) - if (|f_break_seq) begin - assert (state == TXU_BREAK); - assert (r_busy); - assert (o_uart_tx == 1'b0); - end -`ifndef TXUART - reg [28:0] f_counter; - initial f_counter = 0; - always @(posedge i_clk) - if (!o_busy) f_counter <= 1'b0; - else f_counter <= f_counter + 1'b1; - always @(*) - if (f_five_seq[0] | f_six_seq[0] | f_seven_seq[0] | f_eight_seq[0]) - assert (f_counter == (fsv_setup[23:0] - baud_counter - 1)); - else if (f_five_seq[1] | f_six_seq[1] | f_seven_seq[1] | f_eight_seq[1]) - assert (f_counter == ({4'h0, fsv_setup[23:0], 1'b0} - baud_counter - 1)); - else if (f_five_seq[2] | f_six_seq[2] | f_seven_seq[2] | f_eight_seq[2]) - assert(f_counter == ({4'h0, fsv_setup[23:0], 1'b0} -+{5'h0, fsv_setup[23:0]} -- baud_counter - 1)); - else if (f_five_seq[3] | f_six_seq[3] | f_seven_seq[3] | f_eight_seq[3]) - assert (f_counter == ({3'h0, fsv_setup[23:0], 2'b0} - baud_counter - 1)); - else if (f_five_seq[4] | f_six_seq[4] | f_seven_seq[4] | f_eight_seq[4]) - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} -+{5'h0, fsv_setup[23:0]} -- baud_counter - 1)); - else if (f_five_seq[5] | f_six_seq[5] | f_seven_seq[5] | f_eight_seq[5]) - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 1)); - else if (f_six_seq[6] | f_seven_seq[6] | f_eight_seq[6]) - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} -+{5'h0, fsv_setup[23:0]} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 1)); - else if (f_seven_seq[7] | f_eight_seq[7]) - assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 1)); - else if (f_eight_seq[8]) - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -- baud_counter - 1)); - else if (f_stop_seq[0] || (!use_parity && f_stop_seq[1])) begin - case (data_bits) - 2'b00: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 1)); - 2'b01: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -- baud_counter - 1)); - 2'b10: - assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 1)); - 2'b11: - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} -+{5'h0, fsv_setup[23:0]} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 1)); - endcase - end else if (!use_parity && !dblstop && f_stop_seq[2]) begin - case (data_bits) - 2'b00: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 2)); - 2'b01: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -- baud_counter - 2)); - 2'b10: - assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 2)); - 2'b11: - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} -+{5'h0, fsv_setup[23:0]} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 2)); - endcase - end else if (f_stop_seq[1]) begin - assert (dblstop && use_parity); - case (data_bits) - 2'b00: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 1)); - 2'b01: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 1)); - 2'b10: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -- baud_counter - 1)); - 2'b11: - assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 1)); - endcase - end else if ((dblstop ^ use_parity) && f_stop_seq[2]) begin - case (data_bits) - 2'b00: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 2)); - 2'b01: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 2)); - 2'b10: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -- baud_counter - 2)); - 2'b11: - assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 2)); - endcase - end else if (f_stop_seq[2]) begin - assert (dblstop); - assert (use_parity); - case (data_bits) - 2'b00: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{3'h0, fsv_setup[23:0], 2'b00} -- baud_counter - 2)); - 2'b01: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 2)); - 2'b10: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{4'h0, fsv_setup[23:0], 1'b0} -- baud_counter - 2)); - 2'b11: - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} -+{5'h0, fsv_setup[23:0]} -- baud_counter - 2)); - endcase - end -`endif - always @(*) assert ((state < 4'hb) || (state >= 4'he)); - always @(*) assume (i_setup[23:0] > 2); - always @(*) assert (fsv_setup[23:0] > 2); -`endif -endmodule diff --git a/verilog/verilog/examples/txuartlite.v b/verilog/verilog/examples/txuartlite.v deleted file mode 100644 index 0ad1d74174..0000000000 --- a/verilog/verilog/examples/txuartlite.v +++ /dev/null @@ -1,184 +0,0 @@ -/* -Copyright (C) 2015-2021, Gisselquist Technology, LLC - -This program is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. (It's in the $(ROOT)/doc directory. Run make with no -target there if the PDF file isn't present.) If not, see - for a copy. - -License: GPL, v3, as defined and found on www.gnu.org, -http://www.gnu.org/licenses/gpl.html -*/ -`default_nettype none -module txuartlite #( - parameter [4:0] TIMING_BITS = 5'd24, - parameter TB = TIMING_BITS, - parameter [(TB-1):0] CLOCKS_PER_BAUD = 8 -) ( - input wire i_clk, - input wire i_wr, - input wire [7:0] i_data, - output reg o_uart_tx, - output wire o_busy -); - localparam [3:0] TXUL_BIT_ZERO = 4'h0, TXUL_STOP = 4'h8, TXUL_IDLE = 4'hf; - reg [(TB-1):0] baud_counter; - reg [3:0] state; - reg [7:0] lcl_data; - reg r_busy, zero_baud_counter; - initial r_busy = 1'b1; - initial state = TXUL_IDLE; - always @(posedge i_clk) begin - if (!zero_baud_counter) r_busy <= 1'b1; - else if (state > TXUL_STOP) begin - state <= TXUL_IDLE; - r_busy <= 1'b0; - if ((i_wr) && (!r_busy)) begin - r_busy <= 1'b1; - state <= TXUL_BIT_ZERO; - end - end else begin - r_busy <= 1'b1; - if (state <= TXUL_STOP) state <= state + 1'b1; - else state <= TXUL_IDLE; - end - end - assign o_busy = (r_busy); - initial lcl_data = 8'hff; - always @(posedge i_clk) - if ((i_wr) && (!r_busy)) lcl_data <= i_data; - else if (zero_baud_counter) lcl_data <= {1'b1, lcl_data[7:1]}; - initial o_uart_tx = 1'b1; - always @(posedge i_clk) - if ((i_wr) && (!r_busy)) o_uart_tx <= 1'b0; - else if (zero_baud_counter) o_uart_tx <= lcl_data[0]; - initial zero_baud_counter = 1'b1; - initial baud_counter = 0; - always @(posedge i_clk) begin - zero_baud_counter <= (baud_counter == 1); - if (state == TXUL_IDLE) begin - baud_counter <= 0; - zero_baud_counter <= 1'b1; - if ((i_wr) && (!r_busy)) begin - baud_counter <= CLOCKS_PER_BAUD - 1'b1; - zero_baud_counter <= 1'b0; - end - end else if (!zero_baud_counter) baud_counter <= baud_counter - 1'b1; - else if (state > TXUL_STOP) begin - baud_counter <= 0; - zero_baud_counter <= 1'b1; - end else if (state == TXUL_STOP) baud_counter <= CLOCKS_PER_BAUD - 2; - else baud_counter <= CLOCKS_PER_BAUD - 1'b1; - end -`ifdef FORMAL -`ifdef TXUARTLITE - `define ASSUME assume -`else - `define ASSUME assert -`endif - reg f_past_valid, f_last_clk; - reg [(TB-1):0] f_baud_count; - reg [9:0] f_txbits; - reg [3:0] f_bitcount; - reg [7:0] f_request_tx_data; - wire [3:0] subcount; - initial f_past_valid = 1'b0; - always @(posedge i_clk) f_past_valid <= 1'b1; - initial `ASSUME(!i_wr); - always @(posedge i_clk) - if ((f_past_valid) && ($past(i_wr)) && ($past(o_busy))) begin - `ASSUME(i_wr == $past(i_wr)); - `ASSUME(i_data == $past(i_data)); - end - always @(posedge i_clk) assert (zero_baud_counter == (baud_counter == 0)); - always @(posedge i_clk) - if ((f_past_valid) && ($past(baud_counter != 0)) && ($past(state != TXUL_IDLE))) - assert (baud_counter == $past(baud_counter - 1'b1)); - always @(posedge i_clk) - if ((f_past_valid) && (!$past(zero_baud_counter)) && ($past(state != TXUL_IDLE))) - assert ($stable(o_uart_tx)); - initial f_baud_count = 1'b0; - always @(posedge i_clk) - if (zero_baud_counter) f_baud_count <= 0; - else f_baud_count <= f_baud_count + 1'b1; - always @(posedge i_clk) assert (f_baud_count < CLOCKS_PER_BAUD); - always @(posedge i_clk) if (baud_counter != 0) assert (o_busy); - initial f_txbits = 0; - always @(posedge i_clk) if (zero_baud_counter) f_txbits <= {o_uart_tx, f_txbits[9:1]}; - always @(posedge i_clk) - if ((f_past_valid) && (!$past(zero_baud_counter)) && (!$past(state == TXUL_IDLE))) - assert (state == $past(state)); - initial f_bitcount = 0; - always @(posedge i_clk) - if ((!f_past_valid) || (!$past(f_past_valid))) f_bitcount <= 0; - else if ((state == TXUL_IDLE) && (zero_baud_counter)) f_bitcount <= 0; - else if (zero_baud_counter) f_bitcount <= f_bitcount + 1'b1; - always @(posedge i_clk) assert (f_bitcount <= 4'ha); - always @(*) if (!o_busy) assert (zero_baud_counter); - always @(posedge i_clk) if ((i_wr) && (!o_busy)) f_request_tx_data <= i_data; - assign subcount = 10 - f_bitcount; - always @(posedge i_clk) if (f_bitcount > 0) assert (!f_txbits[subcount]); - always @(posedge i_clk) - if (f_bitcount == 4'ha) begin - assert (f_txbits[8:1] == f_request_tx_data); - assert (f_txbits[9]); - end - always @(posedge i_clk) assert ((state <= TXUL_STOP + 1'b1) || (state == TXUL_IDLE)); - always @(posedge i_clk) - if ((f_past_valid) && ($past(f_past_valid)) && ($past(o_busy))) - cover (!o_busy); -`endif -`ifdef VERIFIC_SVA - reg [7:0] fsv_data; - always @(posedge i_clk) if ((i_wr) && (!o_busy)) fsv_data <= i_data; - sequence BAUD_INTERVAL(CKS, DAT, SR, ST); - ((o_uart_tx == DAT)&&(state == ST) -&&(lcl_data == SR) -&&(!zero_baud_counter))[*(CKS-1)] -##1 (o_uart_tx == DAT)&&(state == ST) -&&(lcl_data == SR) -&&(zero_baud_counter); - endsequence - sequence SEND(CKS, DATA); - BAUD_INTERVAL( - CKS, 1'b0, DATA, 4'h0 - ) ##1 BAUD_INTERVAL( - CKS, DATA[0], {{(1) {1'b1}}, DATA[7:1]}, 4'h1 - ) ##1 BAUD_INTERVAL( - CKS, DATA[1], {{(2) {1'b1}}, DATA[7:2]}, 4'h2 - ) ##1 BAUD_INTERVAL( - CKS, DATA[2], {{(3) {1'b1}}, DATA[7:3]}, 4'h3 - ) ##1 BAUD_INTERVAL( - CKS, DATA[3], {{(4) {1'b1}}, DATA[7:4]}, 4'h4 - ) ##1 BAUD_INTERVAL( - CKS, DATA[4], {{(5) {1'b1}}, DATA[7:5]}, 4'h5 - ) ##1 BAUD_INTERVAL( - CKS, DATA[5], {{(6) {1'b1}}, DATA[7:6]}, 4'h6 - ) ##1 BAUD_INTERVAL( - CKS, DATA[6], {{(7) {1'b1}}, DATA[7:7]}, 4'h7 - ) ##1 BAUD_INTERVAL( - CKS, DATA[7], 8'hff, 4'h8 - ) ##1 BAUD_INTERVAL( - CKS - 1, 1'b1, 8'hff, 4'h9 - ); - endsequence - assert property (@(posedge i_clk) (i_wr) && (!o_busy) |=> ((o_busy) throughout SEND( - CLOCKS_PER_BAUD, fsv_data - )) ##1 (!o_busy) && (o_uart_tx) && (zero_baud_counter)); - assume property (@(posedge i_clk) (i_wr) && (o_busy) |=> (i_wr) && ($stable(i_data))); - always @(*) assert ((o_busy) || (zero_baud_counter)); - always @(*) assert (zero_baud_counter == (baud_counter == 0)); - always @(*) assert (baud_counter < CLOCKS_PER_BAUD); - always @(*) assert ((state <= TXUL_STOP + 1'b1) || (state == TXUL_IDLE)); -`endif -endmodule diff --git a/verilog/verilog/examples/uart.v b/verilog/verilog/examples/uart.v new file mode 100644 index 0000000000..757b9b3c4a --- /dev/null +++ b/verilog/verilog/examples/uart.v @@ -0,0 +1,151 @@ +//http://www.asic-world.com/examples/verilog/uart.html +//----------------------------------------------------- +// Design Name : uart +// File Name : uart.v +// Function : Simple UART +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module uart ( + reset, + txclk, + ld_tx_data, + tx_data, + tx_enable, + tx_out, + tx_empty, + rxclk, + uld_rx_data, + rx_data, + rx_enable, + rx_in, + rx_empty +); + // Port declarations + input reset; + input txclk; + input ld_tx_data; + input [7:0] tx_data; + input tx_enable; + output tx_out; + output tx_empty; + input rxclk; + input uld_rx_data; + output [7:0] rx_data; + input rx_enable; + input rx_in; + output rx_empty; + // Internal Variables (@note: interference with ports) + reg [7:0] tx_reg; + reg tx_empty; + reg tx_over_run; + reg [3:0] tx_cnt; + reg tx_out; + reg [7:0] rx_reg; + reg [7:0] rx_data; + reg [3:0] rx_sample_cnt; + reg [3:0] rx_cnt; + reg rx_frame_err; + reg rx_over_run; + reg rx_empty; + reg rx_d1; + reg rx_d2; + reg rx_busy; + // UART RX Logic + always @(posedge rxclk or posedge reset) + if (reset) begin + rx_reg <= 0; + rx_data <= 0; + rx_sample_cnt <= 0; + rx_cnt <= 0; + rx_frame_err <= 0; + rx_over_run <= 0; + rx_empty <= 1; + rx_d1 <= 1; + rx_d2 <= 1; + rx_busy <= 0; + end else begin + // Synchronize the asynch signal + rx_d1 <= rx_in; + rx_d2 <= rx_d1; + // Uload the rx data + if (uld_rx_data) begin + rx_data <= rx_reg; + rx_empty <= 1; + end + // Receive data only when rx is enabled + if (rx_enable) begin + // Check if just received start of frame + if (!rx_busy && !rx_d2) begin + rx_busy <= 1; + rx_sample_cnt <= 1; + rx_cnt <= 0; + end + // Start of frame detected, Proceed with rest of data + if (rx_busy) begin + rx_sample_cnt <= rx_sample_cnt + 1; + // Logic to sample at middle of data + if (rx_sample_cnt == 7) begin + if ((rx_d2 == 1) && (rx_cnt == 0)) begin + rx_busy <= 0; + end else begin + rx_cnt <= rx_cnt + 1; + // Start storing the rx data + if (rx_cnt > 0 && rx_cnt < 9) begin + rx_reg[rx_cnt-1] <= rx_d2; + end + if (rx_cnt == 9) begin + rx_busy <= 0; + // Check if End of frame received correctly + if (rx_d2 == 0) begin + rx_frame_err <= 1; + end else begin + rx_empty <= 0; + rx_frame_err <= 0; + // Check if last rx data was not unloaded, + rx_over_run <= (rx_empty) ? 0 : 1; + end + end + end + end + end + end + if (!rx_enable) begin + rx_busy <= 0; + end + end + // UART TX Logic + always @(posedge txclk or posedge reset) + if (reset) begin + tx_reg <= 0; + tx_empty <= 1; + tx_over_run <= 0; + tx_out <= 1; + tx_cnt <= 0; + end else begin + if (ld_tx_data) begin + if (!tx_empty) begin + tx_over_run <= 0; + end else begin + tx_reg <= tx_data; + tx_empty <= 0; + end + end + if (tx_enable && !tx_empty) begin + tx_cnt <= tx_cnt + 1; + if (tx_cnt == 0) begin + tx_out <= 0; + end + if (tx_cnt > 0 && tx_cnt < 9) begin + tx_out <= tx_reg[tx_cnt-1]; + end + if (tx_cnt == 9) begin + tx_out <= 1; + tx_cnt <= 0; + tx_empty <= 1; + end + end + if (!tx_enable) begin + tx_cnt <= 0; + end + end +endmodule diff --git a/verilog/verilog/examples/ufifo.v b/verilog/verilog/examples/ufifo.v deleted file mode 100644 index a8b5c5cf9d..0000000000 --- a/verilog/verilog/examples/ufifo.v +++ /dev/null @@ -1,214 +0,0 @@ -/* -Copyright (C) 2015-2021, Gisselquist Technology, LLC - -This program is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. (It's in the $(ROOT)/doc directory. Run make with no -target there if the PDF file isn't present.) If not, see - for a copy. - -License: GPL, v3, as defined and found on www.gnu.org, -http://www.gnu.org/licenses/gpl.html -*/ -`default_nettype none -module ufifo #( - parameter BW = 8, - parameter [3:0] LGFLEN = 4, - parameter [0:0] RXFIFO = 1'b1, - parameter FLEN = (1 << LGFLEN) -) ( - input wire i_clk, - i_reset, - input wire i_wr, - input wire [(BW-1):0] i_data, - output wire o_empty_n, - input wire i_rd, - output wire [(BW-1):0] o_data, - output wire [15:0] o_status, - output wire o_err -); - reg [(BW-1):0] fifo[0:(FLEN-1)]; - reg [(BW-1):0] r_data, last_write; - reg [(LGFLEN-1):0] wr_addr, rd_addr, r_next; - reg will_overflow, will_underflow; - reg osrc; - wire [(LGFLEN-1):0] w_waddr_plus_one, w_waddr_plus_two; - wire w_write, w_read; - reg [(LGFLEN-1):0] r_fill; - wire [3:0] lglen; - wire w_half_full; - reg [9:0] w_fill; - assign w_write = (i_wr && (!will_overflow || i_rd)); - assign w_read = (i_rd && o_empty_n); - assign w_waddr_plus_two = wr_addr + 2; - assign w_waddr_plus_one = wr_addr + 1; - initial will_overflow = 1'b0; - always @(posedge i_clk) - if (i_reset) will_overflow <= 1'b0; - else if (i_rd) will_overflow <= (will_overflow) && (i_wr); - else if (w_write) will_overflow <= (will_overflow) || (w_waddr_plus_two == rd_addr); - else if (w_waddr_plus_one == rd_addr) will_overflow <= 1'b1; - initial wr_addr = 0; - always @(posedge i_clk) - if (i_reset) wr_addr <= {(LGFLEN) {1'b0}}; - else if (w_write) wr_addr <= w_waddr_plus_one; - always @(posedge i_clk) if (w_write) fifo[wr_addr] <= i_data; - initial will_underflow = 1'b1; - always @(posedge i_clk) - if (i_reset) will_underflow <= 1'b1; - else if (i_wr) will_underflow <= 1'b0; - else if (w_read) will_underflow <= (will_underflow) || (r_next == wr_addr); - initial rd_addr = 0; - initial r_next = 1; - always @(posedge i_clk) - if (i_reset) begin - rd_addr <= 0; - r_next <= 1; - end else if (w_read) begin - rd_addr <= rd_addr + 1; - r_next <= rd_addr + 2; - end - always @(posedge i_clk) if (w_read) r_data <= fifo[r_next[LGFLEN-1:0]]; - always @(posedge i_clk) - if (i_wr && (!o_empty_n || (w_read && r_next == wr_addr))) - last_write <= i_data; - initial osrc = 1'b0; - always @(posedge i_clk) - if (i_reset) osrc <= 1'b0; - else if (i_wr && (!o_empty_n || (w_read && r_next == wr_addr))) osrc <= 1'b1; - else if (i_rd) osrc <= 1'b0; - assign o_data = (osrc) ? last_write : r_data; - generate - if (RXFIFO) begin : RXFIFO_FILL - initial r_fill = 0; - always @(posedge i_clk) - if (i_reset) r_fill <= 0; - else - case ({ - w_write, w_read - }) - 2'b01: r_fill <= r_fill - 1'b1; - 2'b10: r_fill <= r_fill + 1'b1; - default: begin - end - endcase - end else begin : TXFIFO_FILL - initial r_fill = -1; - always @(posedge i_clk) - if (i_reset) r_fill <= -1; - else - case ({ - w_write, w_read - }) - 2'b01: r_fill <= r_fill + 1'b1; - 2'b10: r_fill <= r_fill - 1'b1; - default: begin - end - endcase - end - endgenerate - assign o_err = (i_wr && !w_write); - assign lglen = LGFLEN; - always @(*) begin - w_fill = 0; - w_fill[(LGFLEN-1):0] = r_fill; - end - assign w_half_full = r_fill[(LGFLEN-1)]; - assign o_status = {lglen, w_fill, w_half_full, (RXFIFO != 0) ? !will_underflow : !will_overflow}; - assign o_empty_n = !will_underflow; -`ifdef FORMAL - reg f_past_valid; - initial f_past_valid = 0; - always @(posedge i_clk) f_past_valid <= 1; - reg [LGFLEN-1:0] f_fill; - wire [LGFLEN-1:0] f_raddr_plus_one; - always @(*) f_fill = wr_addr - rd_addr; - always @(*) assert (will_underflow == (f_fill == 0)); - always @(*) assert (will_overflow == (&f_fill)); - assign f_raddr_plus_one = rd_addr + 1; - always @(*) assert (f_raddr_plus_one == r_next); - always @(*) - if (will_underflow) begin - assert (!w_read); - assert (!osrc); - end - always @(posedge i_clk) - if (RXFIFO) - assert (r_fill == f_fill); - else assert (r_fill == (~f_fill)); -`ifdef UFIFO - (* anyconst *) reg [LGFLEN-1:0] f_const_addr; - (* anyconst *) reg [BW-1:0] f_const_data, f_const_second; - reg [LGFLEN-1:0] f_next_addr; - reg [1:0] f_state; - reg f_first_in_fifo, f_second_in_fifo; - reg [LGFLEN-1:0] f_distance_to_first, f_distance_to_second; - always @(*) begin - f_next_addr = f_const_addr + 1; - f_distance_to_first = f_const_addr - rd_addr; - f_distance_to_second = f_next_addr - rd_addr; - f_first_in_fifo = (f_distance_to_first < f_fill) -&& !will_underflow -&& (fifo[f_const_addr] == f_const_data); - f_second_in_fifo = (f_distance_to_second < f_fill) -&& !will_underflow -&& (fifo[f_next_addr] == f_const_second); - end - initial f_state = 2'b00; - always @(posedge i_clk) - if (i_reset) f_state <= 2'b00; - else - case (f_state) - 2'b00: - if (w_write && (wr_addr == f_const_addr) && (i_data == f_const_data)) f_state <= 2'b01; - 2'b01: - if (w_read && (rd_addr == f_const_addr)) f_state <= 2'b00; - else if (w_write && (wr_addr == f_next_addr)) - f_state <= (i_data == f_const_second) ? 2'b10 : 2'b00; - 2'b10: if (w_read && (rd_addr == f_const_addr)) f_state <= 2'b11; - 2'b11: if (w_read) f_state <= 2'b00; - endcase - always @(*) - case (f_state) - 2'b00: begin - end - 2'b01: begin - assert (!will_underflow); - assert (f_first_in_fifo); - assert (!f_second_in_fifo); - assert (wr_addr == f_next_addr); - assert (fifo[f_const_addr] == f_const_data); - if (rd_addr == f_const_addr) assert (o_data == f_const_data); - end - 2'b10: begin - assert (f_first_in_fifo); - assert (f_second_in_fifo); - end - 2'b11: begin - assert (f_second_in_fifo); - assert (rd_addr == f_next_addr); - assert (o_data == f_const_second); - end - endcase -`endif - reg cvr_filled; - always @(*) cover (o_empty_n); -`ifdef UFIFO - always @(*) cover (o_err); - initial cvr_filled = 0; - always @(posedge i_clk) - if (i_reset) cvr_filled <= 0; - else if (&f_fill[LGFLEN-1:0]) cvr_filled <= 1; - always @(*) cover (cvr_filled && !o_empty_n); -`endif -`endif -endmodule diff --git a/verilog/verilog/examples/wbuart.v b/verilog/verilog/examples/wbuart.v deleted file mode 100644 index a505247dd3..0000000000 --- a/verilog/verilog/examples/wbuart.v +++ /dev/null @@ -1,251 +0,0 @@ -/* -Copyright (C) 2015-2021, Gisselquist Technology, LLC - -This program is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. (It's in the $(ROOT)/doc directory. Run make with no -target there if the PDF file isn't present.) If not, see - for a copy. - -License: GPL, v3, as defined and found on www.gnu.org, -http://www.gnu.org/licenses/gpl.html -*/ -`default_nettype none -module wbuart #( - parameter [30:0] INITIAL_SETUP = 31'd25, - parameter [3:0] LGFLEN = 4, - parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1, - parameter [3:0] LCLLGFLEN = (LGFLEN > 4'ha) ? 4'ha : ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN) -) ( - input wire i_clk, - i_reset, - input wire i_wb_cyc, - input wire i_wb_stb, - i_wb_we, - input wire [1:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - input wire i_uart_rx, - output wire o_uart_tx, - input wire i_cts_n, - output reg o_rts_n, - output wire o_uart_rx_int, - o_uart_tx_int, - o_uart_rxfifo_int, - o_uart_txfifo_int -); - localparam [1:0] UART_SETUP = 2'b00, UART_FIFO = 2'b01, UART_RXREG = 2'b10, UART_TXREG = 2'b11; - wire tx_busy; - reg [30:0] uart_setup; - wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart; - wire [7:0] rx_uart_data; - reg rx_uart_reset; - wire rx_empty_n, rx_fifo_err; - wire [7:0] rxf_wb_data; - wire [15:0] rxf_status; - reg rxf_wb_read; - wire [(LCLLGFLEN-1):0] check_cutoff; - reg r_rx_perr, r_rx_ferr; - wire [31:0] wb_rx_data; - wire tx_empty_n, txf_err, tx_break; - wire [ 7:0] tx_data; - wire [15:0] txf_status; - reg txf_wb_write, tx_uart_reset; - reg [7:0] txf_wb_data; - wire [31:0] wb_tx_data; - wire [31:0] wb_fifo_data; - reg [1:0] r_wb_addr; - reg r_wb_ack; - initial uart_setup = INITIAL_SETUP | ((HARDWARE_FLOW_CONTROL_PRESENT == 1'b0) ? 31'h40000000 : 0); - always @(posedge i_clk) - if ((i_wb_stb) && (i_wb_addr == UART_SETUP) && (i_wb_we)) begin - if (i_wb_sel[0]) uart_setup[7:0] <= i_wb_data[7:0]; - if (i_wb_sel[1]) uart_setup[15:8] <= i_wb_data[15:8]; - if (i_wb_sel[2]) uart_setup[23:16] <= i_wb_data[23:16]; - if (i_wb_sel[3]) - uart_setup[30:24] <= { - (i_wb_data[30]) || (!HARDWARE_FLOW_CONTROL_PRESENT), i_wb_data[29:24] - }; - end -`ifdef USE_LITE_UART - rxuartlite #( - .CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]) - ) rx ( - i_clk, - i_uart_rx, - rx_stb, - rx_uart_data - ); - assign rx_break = 1'b0; - assign rx_perr = 1'b0; - assign rx_ferr = 1'b0; - assign ck_uart = 1'b0; -`else - rxuart #( - .INITIAL_SETUP(INITIAL_SETUP) - ) rx ( - i_clk, - (i_reset) || (rx_uart_reset), - uart_setup, - i_uart_rx, - rx_stb, - rx_uart_data, - rx_break, - rx_perr, - rx_ferr, - ck_uart - ); -`endif - ufifo #( - .LGFLEN(LCLLGFLEN), - .RXFIFO(1) - ) rxfifo ( - i_clk, - (i_reset) || (rx_break) || (rx_uart_reset), - rx_stb, - rx_uart_data, - rx_empty_n, - rxf_wb_read, - rxf_wb_data, - rxf_status, - rx_fifo_err - ); - assign o_uart_rxfifo_int = rxf_status[1]; - assign o_uart_rx_int = rxf_status[0]; - assign check_cutoff = -3; - always @(posedge i_clk) - o_rts_n <= ((HARDWARE_FLOW_CONTROL_PRESENT) -&&(!uart_setup[30]) -&&(rxf_status[(LCLLGFLEN+1):2] > check_cutoff)); - initial rxf_wb_read = 1'b0; - always @(posedge i_clk) rxf_wb_read <= (i_wb_stb) && (i_wb_addr[1:0] == UART_RXREG) && (!i_wb_we); - initial r_rx_perr = 1'b0; - initial r_rx_ferr = 1'b0; - always @(posedge i_clk) - if ((rx_uart_reset) || (rx_break)) begin - r_rx_perr <= 1'b0; - r_rx_ferr <= 1'b0; - end else if ((i_wb_stb) && (i_wb_addr[1:0] == UART_RXREG) && (i_wb_we)) begin - if (i_wb_sel[1]) begin - r_rx_perr <= (r_rx_perr) && (~i_wb_data[9]); - r_rx_ferr <= (r_rx_ferr) && (~i_wb_data[10]); - end - end else if (rx_stb) begin - r_rx_perr <= (r_rx_perr) || (rx_perr); - r_rx_ferr <= (r_rx_ferr) || (rx_ferr); - end - initial rx_uart_reset = 1'b1; - always @(posedge i_clk) - if ((i_reset) || ((i_wb_stb) && (i_wb_addr[1:0] == UART_SETUP) && (i_wb_we))) - rx_uart_reset <= 1'b1; - else if ((i_wb_stb) && (i_wb_addr[1:0] == UART_RXREG) && (i_wb_we) && i_wb_sel[1]) - rx_uart_reset <= i_wb_data[12]; - else rx_uart_reset <= 1'b0; - assign wb_rx_data = { - 16'h00, 3'h0, rx_fifo_err, rx_break, rx_ferr, r_rx_perr, !rx_empty_n, rxf_wb_data - }; - initial txf_wb_write = 1'b0; - always @(posedge i_clk) begin - txf_wb_write <= (i_wb_stb) && (i_wb_addr == UART_TXREG) && (i_wb_we) && (i_wb_sel[0]); - txf_wb_data <= i_wb_data[7:0]; - end - ufifo #( - .LGFLEN(LGFLEN), - .RXFIFO(0) - ) txfifo ( - i_clk, - (tx_break) || (tx_uart_reset), - txf_wb_write, - txf_wb_data, - tx_empty_n, - (!tx_busy) && (tx_empty_n), - tx_data, - txf_status, - txf_err - ); - assign o_uart_tx_int = txf_status[0]; - assign o_uart_txfifo_int = txf_status[1]; -`ifndef USE_LITE_UART - reg r_tx_break; - initial r_tx_break = 1'b0; - always @(posedge i_clk) - if (i_reset) r_tx_break <= 1'b0; - else if ((i_wb_stb) && (i_wb_addr[1:0] == UART_TXREG) && (i_wb_we) && (i_wb_sel[1])) - r_tx_break <= i_wb_data[9]; - assign tx_break = r_tx_break; -`else - assign tx_break = 1'b0; -`endif - initial tx_uart_reset = 1'b1; - always @(posedge i_clk) - if ((i_reset) || ((i_wb_stb) && (i_wb_addr == UART_SETUP) && (i_wb_we))) tx_uart_reset <= 1'b1; - else if ((i_wb_stb) && (i_wb_addr[1:0] == UART_TXREG) && (i_wb_we) && i_wb_sel[1]) - tx_uart_reset <= i_wb_data[12]; - else tx_uart_reset <= 1'b0; -`ifdef USE_LITE_UART - txuartlite #( - .CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]) - ) tx ( - i_clk, - (tx_empty_n), - tx_data, - o_uart_tx, - tx_busy - ); -`else - wire cts_n; - assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT) && (i_cts_n); - txuart #( - .INITIAL_SETUP(INITIAL_SETUP) - ) tx ( - i_clk, - 1'b0, - uart_setup, - r_tx_break, - (tx_empty_n), - tx_data, - cts_n, - o_uart_tx, - tx_busy - ); -`endif - assign wb_tx_data = { - 16'h00, - i_cts_n, - txf_status[1:0], - txf_err, - ck_uart, - o_uart_tx, - tx_break, - (tx_busy | txf_status[0]), - (tx_busy | txf_status[0]) ? txf_wb_data : 8'b00 - }; - assign wb_fifo_data = {txf_status, rxf_status}; - always @(posedge i_clk) r_wb_addr <= i_wb_addr; - initial r_wb_ack = 1'b0; - always @(posedge i_clk) r_wb_ack <= i_wb_stb; - initial o_wb_ack = 1'b0; - always @(posedge i_clk) o_wb_ack <= i_wb_cyc && r_wb_ack; - always @(posedge i_clk) - casez (r_wb_addr) - UART_SETUP: o_wb_data <= {1'b0, uart_setup}; - UART_FIFO: o_wb_data <= wb_fifo_data; - UART_RXREG: o_wb_data <= wb_rx_data; - UART_TXREG: o_wb_data <= wb_tx_data; - endcase - assign o_wb_stall = 1'b0; - wire unused; - assign unused = &{1'b0, i_wb_data[31]}; -endmodule