diff --git a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst index 272cd084a7b14..a79de00599473 100644 --- a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst +++ b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst @@ -813,3 +813,57 @@ Configures the board to use the SPI4 and enables RFID driver with MFRC522:: MOSI PE6 CS PE4 ======== ===== + +lvgl +---- + +Configures the board to use display of 7 inch with lvgl example. + +To verify if the display is functioning correctly, use the **fb** command. You should see the display change colors.:: + + nsh> fb + VideoInfo: + fmt: 11 + xres: 1024 + yres: 600 + nplanes: 1 + noverlays: 1 + OverlayInfo (overlay 0): + fbmem: 0xc0000000 + fblen: 1228800 + stride: 2048 + overlay: 0 + bpp: 16 + blank: 0 + chromakey: 0x00000000 + color: 0x00000000 + transp: 0xff + mode: 0 + area: (0,0) => (1024,600) + accl: 1 + PlaneInfo (plane 0): + fbmem: 0xc0000000 + fblen: 1228800 + stride: 2048 + display: 0 + bpp: 16 + Mapped FB: 0xc0000000 + 0: ( 0, 0) (1024,600) + 1: ( 93, 54) (838,492) + 2: (186,108) (652,384) + 3: (279,162) (466,276) + 4: (372,216) (280,168) + 5: (465,270) ( 94, 60) + Test finished + +Once the **fd** command work, run the lvgl exemple. :: + + nsh> lvgldemo + +**WARNING:** This example at the moment is not working correctly yet and have a bug fix to be done. +In the lvgl file **./apps/graphics/lvgl/lvgl/src/drivers/nuttx/lv_nuttx_fbdev.c** +search the function **lv_nuttx_fbdev_set_file** and modify line 156 as follows: + + dsc->mem_off_screen = malloc(data_size); + to + dsc->mem_off_screen = (void*)0xC00000000; diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index 993c609b1ed5c..ed0c7dd2f3a6a 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -2623,7 +2623,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, chromakey=%08x\n", vtable, + lcdinfo("vtable=%p, overlay=%d, chromakey=%08" PRIx32 "\n", vtable, oinfo->overlay, oinfo->chromakey); if (oinfo->overlay < LTDC_NLAYERS) @@ -2689,7 +2689,8 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, const struct fb_overlayinfo_s *oinfo) { DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, color=%08x\n", vtable, oinfo->color); + lcdinfo("vtable=%p, overlay=%d, color=%08" PRIx32 "\n", + vtable, oinfo->overlay, oinfo->color); if (oinfo->overlay < LTDC_NOVERLAYS) { @@ -2737,7 +2738,8 @@ static int stm32_setblank(struct fb_vtable_s *vtable, struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, blank=%02x\n", vtable, oinfo->blank); + lcdinfo("vtable=%p, overlay=%d, blank=%02x\n", + vtable, oinfo->overlay, oinfo->blank); if (oinfo->overlay < LTDC_NLAYERS) { diff --git a/arch/arm/src/stm32h7/stm32_ltdc.c b/arch/arm/src/stm32h7/stm32_ltdc.c index 58b3ebb963b4a..08662e12acc06 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.c +++ b/arch/arm/src/stm32h7/stm32_ltdc.c @@ -2626,7 +2626,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, chromakey=%08x\n", vtable, + lcdinfo("vtable=%p, overlay=%d, chromakey=%08" PRIx32 "\n", vtable, oinfo->overlay, oinfo->chromakey); if (oinfo->overlay < LTDC_NLAYERS) @@ -2692,7 +2692,8 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, const struct fb_overlayinfo_s *oinfo) { DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, color=%08x\n", vtable, oinfo->color); + lcdinfo("vtable=%p, overlay=%d, color=%08" PRIx32 "\n", + vtable, oinfo->overlay, oinfo->color); if (oinfo->overlay < LTDC_NOVERLAYS) { @@ -2739,7 +2740,8 @@ static int stm32_setblank(struct fb_vtable_s *vtable, struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL); - lcdinfo("vtable=%p, overlay=%d, blank=%02x\n", vtable, oinfo->blank); + lcdinfo("vtable=%p, overlay=%d, blank=%02x\n", + vtable, oinfo->overlay, oinfo->blank); if (oinfo->overlay < LTDC_NLAYERS) { diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig new file mode 100644 index 0000000000000..553da01f14bdd --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_FB_CMAP is not set +# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_LVGLDEMO=y +CONFIG_FB_OVERLAY=y +CONFIG_FS_PROCFS=y +CONFIG_GRAPHICS_LVGL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y +CONFIG_LV_USE_DEMO_WIDGETS=y +CONFIG_LV_USE_NUTTX=y +CONFIG_MM_REGIONS=5 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_FMC=y +CONFIG_STM32H7_LTDC=y +CONFIG_STM32H7_LTDC_FB_BASE=0xC0000000 +CONFIG_STM32H7_LTDC_FB_SIZE=1228800 +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_RAMTEST=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index e9f87e1930ec2..3bdf7c3889a7c 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -88,13 +88,13 @@ #define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE -/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR +/* PLL1 - 25 MHz input, enable DIVP, DIVQ, DIVR * * PLL1_VCO = (25 MHz / 5) * 192 = 960 MHz * * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 480 MHz * PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 240 MHz - * PLL1R = PLL1_VCO/8 = 800 MHz / 4 = 240 MHz + * PLL1R = PLL1_VCO/4 = 800 MHz / 4 = 240 MHz */ #define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE| \ @@ -103,24 +103,24 @@ RCC_PLLCFGR_DIVQ1EN| \ RCC_PLLCFGR_DIVR1EN) -#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 5) * 192) -#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) -#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) -#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 4) - #define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(5) #define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(192) #define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) #define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) #define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(4) -/* PLL2, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 5) * 192) +#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) +#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 4) + +/* PLL2 - 25 MHz input, enable DIVP, DIVQ, DIVR * - * PLL1_VCO = (25 MHz / 2) * 48 = 600 MHz + * PLL2_VCO = (25 MHz / 2) * 48 = 600 MHz * - * PLL2P = PLL2_VCO/2 = 600 MHz / 8 = 75 MHz - * PLL2Q = PLL2_VCO/4 = 600 MHz / 40 = 15 MHz - * PLL2R = PLL2_VCO/8 = 600 MHz / 3 = 200 MHz + * PLL2P = PLL2_VCO/8 = 600 MHz / 8 = 75 MHz + * PLL2Q = PLL2_VCO/40 = 600 MHz / 40 = 15 MHz + * PLL2R = PLL2_VCO/3 = 600 MHz / 3 = 200 MHz */ #define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE| \ RCC_PLLCFGR_PLL2RGE_4_8_MHZ| \ @@ -128,30 +128,41 @@ RCC_PLLCFGR_DIVQ2EN| \ RCC_PLLCFGR_DIVR2EN) -#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 48) -#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 8) -#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 40) -#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 3) - #define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) #define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(48) #define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(8) #define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(40) #define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(3) -/* PLL3 */ - -#define STM32_PLLCFG_PLL3CFG 0 -#define STM32_PLLCFG_PLL3M 0 -#define STM32_PLLCFG_PLL3N 0 -#define STM32_PLLCFG_PLL3P 0 -#define STM32_PLLCFG_PLL3Q 0 -#define STM32_PLLCFG_PLL3R 0 +#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 48) +#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 8) +#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 40) +#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 3) -#define STM32_VCO3_FREQUENCY -#define STM32_PLL3P_FREQUENCY -#define STM32_PLL3Q_FREQUENCY -#define STM32_PLL3R_FREQUENCY +/* PLL3 - 25 MHz input, enable DIVP, DIVQ, DIVR + * + * PLL3_VCO = (25 MHz / 1) * 35 = 875 MHz + * + * PLL3P = PLL3_VCO/2 = 875 MHz / 2 = 437.7 MHz + * PLL3Q = PLL3_VCO/1 = 875 MHz / 1 = 875 MHz + * PLL3R = PLL3_VCO/20 = 875 MHz / 20 = 43.75 MHz + */ +#define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE| \ + RCC_PLLCFGR_PLL3RGE_8_16_MHZ| \ + RCC_PLLCFGR_DIVP3EN| \ + RCC_PLLCFGR_DIVQ3EN| \ + RCC_PLLCFGR_DIVR3EN) + +#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(1) +#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(35) +#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2) +#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(1) +#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(20) + +#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 1) * 35) +#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 2) +#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 1) +#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 20) /* SYSCLK = PLL1P = 480 MHz * CPUCLK = SYSCLK / 1 = 480 MHz @@ -163,7 +174,7 @@ /* Configure Clock Assignments */ -/* AHB clock (HCLK) is SYSCLK/2 (480 MHz max) +/* AHB clock (HCLK) is SYSCLK/2 (240 MHz max) * HCLK1 = HCLK2 = HCLK3 = HCLK4 */ @@ -173,22 +184,22 @@ /* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */ -#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* APB2 clock (PCLK2) is HCLK/2 (120 MHz) */ -#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* APB3 clock (PCLK3) is HCLK/2 (120 MHz) */ -#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 = HCLK / 2 */ +#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 = HCLK / 2 */ #define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* APB4 clock (PCLK4) is HCLK/2 (120 MHz) */ -#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 = HCLK / 2 */ +#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 = HCLK / 2 */ #define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* Timer clock frequencies */ @@ -246,6 +257,17 @@ #define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 +/* FDCAN 1 2 clock source, use STM32_HSE_FREQUENCY */ + +#define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE + +/* SDMMC 1 2 clock source, use STM32_PLL1Q_FREQUENCY */ + +#define STM32_RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMC_PLL1 + +/* FMC clock source, use STM32_PLL1Q_FREQUENCY */ +#define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK + /* FLASH wait states * * ------------ ---------- ----------- @@ -268,21 +290,6 @@ #define BOARD_FLASH_WAITSTATES 4 -/* SDMMC definitions ********************************************************/ - -/* Init 400 kHz, PLL1Q/(2*300) = 240 MHz / (2*300) = 400 Khz */ - -#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) - -/* Just set these to 24 MHz for now, - * PLL1Q/(2*5) = 240 MHz / (2*5) = 24 MHz - */ - -#define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) - -#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE - /* LED definitions **********************************************************/ /* The board has 1 user LED RGB that could be used this diagnostic LED too. @@ -386,6 +393,18 @@ /* SDMMC1 - Used SD Card memory */ +/* Init 400 kHz, PLL1Q/(2*300) = 240 MHz / (2*300) = 400 Khz */ + +#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* Just set these to 24 MHz for now, + * PLL1Q/(2*5) = 240 MHz / (2*5) = 24 MHz + */ + +#define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE + #define GPIO_SDMMC1_CK (GPIO_SDMMC1_CK_0|GPIO_SPEED_100MHz) /* PC12 */ #define GPIO_SDMMC1_CMD (GPIO_SDMMC1_CMD_0|GPIO_SPEED_100MHz) /* PD2 */ #define GPIO_SDMMC1_D0 (GPIO_SDMMC1_D0_0|GPIO_SPEED_100MHz) /* PC8 */ @@ -450,15 +469,13 @@ /* SDRAM FMC definitions ****************************************************/ -/* The following settings correspond to W9864G6KH-6 SDRAM - * part-number ("-6" speed grades ) and FMC_SDCLK frequency of 166 MHz - * (period is ~ 6.25 ns). +/* The following settings correspond to IS42S16400J SDRAM + * part-number and FMC_SDCLK frequency of 120 MHz */ -/* Though W9864G6KH-6 SDRAM itself provides 16-bit data bus, +/* Though IS42S16400J SDRAM itself provides 16-bit data bus, * linum board routes only DQ[15:0] bits. */ -#define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK #if CONFIG_STM32H7_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) @@ -559,37 +576,37 @@ /* LTDC */ -#define GPIO_LTDC_R0 (GPIO_LTDC_R0_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R1 (GPIO_LTDC_R1_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R2 (GPIO_LTDC_R2_4|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R3 (GPIO_LTDC_R3_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R4 (GPIO_LTDC_R4_4|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R5 (GPIO_LTDC_R5_4|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R6 (GPIO_LTDC_R6_4|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R7 (GPIO_LTDC_R7_3|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_G0 (GPIO_LTDC_G0_2|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G1 (GPIO_LTDC_G1_2|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G2 (GPIO_LTDC_G2_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G3 (GPIO_LTDC_G3_4|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G4 (GPIO_LTDC_G4_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G5 (GPIO_LTDC_G5_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G6 (GPIO_LTDC_G6_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G7 (GPIO_LTDC_G7_3|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_B0 (GPIO_LTDC_B0_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B1 (GPIO_LTDC_B1_2|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B2 (GPIO_LTDC_B2_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B3 (GPIO_LTDC_B3_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B4 (GPIO_LTDC_B4_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B5 (GPIO_LTDC_B5_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B6 (GPIO_LTDC_B6_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B7 (GPIO_LTDC_B7_3|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_VSYNC (GPIO_LTDC_VSYNC_2|GPIO_SPEED_100MHz) -#define GPIO_LTDC_HSYNC (GPIO_LTDC_HSYNC_2|GPIO_SPEED_100MHz) -#define GPIO_LTDC_DE (GPIO_LTDC_DE_3|GPIO_SPEED_100MHz) -#define GPIO_LTDC_CLK (GPIO_LTDC_CLK_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R0 (GPIO_LTDC_R0_3|GPIO_SPEED_100MHz) /* PI15 */ +#define GPIO_LTDC_R1 (GPIO_LTDC_R1_3|GPIO_SPEED_100MHz) /* PJ0 */ +#define GPIO_LTDC_R2 (GPIO_LTDC_R2_4|GPIO_SPEED_100MHz) /* PJ1 */ +#define GPIO_LTDC_R3 (GPIO_LTDC_R3_2|GPIO_SPEED_100MHz) /* PJ2 */ +#define GPIO_LTDC_R4 (GPIO_LTDC_R4_4|GPIO_SPEED_100MHz) /* PJ3 */ +#define GPIO_LTDC_R5 (GPIO_LTDC_R5_5|GPIO_SPEED_100MHz) /* PJ4 */ +#define GPIO_LTDC_R6 (GPIO_LTDC_R6_3|GPIO_SPEED_100MHz) /* PJ5 */ +#define GPIO_LTDC_R7 (GPIO_LTDC_R7_3|GPIO_SPEED_100MHz) /* PJ6 */ + +#define GPIO_LTDC_G0 (GPIO_LTDC_G0_3|GPIO_SPEED_100MHz) /* PJ7 */ +#define GPIO_LTDC_G1 (GPIO_LTDC_G1_3|GPIO_SPEED_100MHz) /* PJ8 */ +#define GPIO_LTDC_G2 (GPIO_LTDC_G2_3|GPIO_SPEED_100MHz) /* PJ9 */ +#define GPIO_LTDC_G3 (GPIO_LTDC_G3_4|GPIO_SPEED_100MHz) /* PJ10 */ +#define GPIO_LTDC_G4 (GPIO_LTDC_G4_4|GPIO_SPEED_100MHz) /* PJ11 */ +#define GPIO_LTDC_G5 (GPIO_LTDC_G5_3|GPIO_SPEED_100MHz) /* PK0 */ +#define GPIO_LTDC_G6 (GPIO_LTDC_G6_3|GPIO_SPEED_100MHz) /* PK1 */ +#define GPIO_LTDC_G7 (GPIO_LTDC_G7_4|GPIO_SPEED_100MHz) /* PK2 */ + +#define GPIO_LTDC_B0 (GPIO_LTDC_B0_3|GPIO_SPEED_100MHz) /* PJ12 */ +#define GPIO_LTDC_B1 (GPIO_LTDC_B1_3|GPIO_SPEED_100MHz) /* PJ13 */ +#define GPIO_LTDC_B2 (GPIO_LTDC_B2_4|GPIO_SPEED_100MHz) /* PJ14 */ +#define GPIO_LTDC_B3 (GPIO_LTDC_B3_4|GPIO_SPEED_100MHz) /* PJ15 */ +#define GPIO_LTDC_B4 (GPIO_LTDC_B4_4|GPIO_SPEED_100MHz) /* PK3 */ +#define GPIO_LTDC_B5 (GPIO_LTDC_B5_3|GPIO_SPEED_100MHz) /* PK4 */ +#define GPIO_LTDC_B6 (GPIO_LTDC_B6_3|GPIO_SPEED_100MHz) /* PK5 */ +#define GPIO_LTDC_B7 (GPIO_LTDC_B7_3|GPIO_SPEED_100MHz) /* PK6 */ + +#define GPIO_LTDC_DE (GPIO_LTDC_DE_3|GPIO_SPEED_100MHz) /* PK7 */ +#define GPIO_LTDC_CLK (GPIO_LTDC_CLK_3|GPIO_SPEED_100MHz) /* PI14 */ +#define GPIO_LTDC_VSYNC (GPIO_LTDC_VSYNC_3|GPIO_SPEED_100MHz) /* PI9 */ +#define GPIO_LTDC_HSYNC (GPIO_LTDC_HSYNC_2|GPIO_SPEED_100MHz) /* PI10 */ /* LCD definitions **********************************************************/ @@ -598,14 +615,12 @@ #define BOARD_LTDC_OUTPUT_BPP 16 #define BOARD_LTDC_HFP 160 -#define BOARD_LTDC_HBP 160 +#define BOARD_LTDC_HBP 160 /* AccumulatedHBP */ #define BOARD_LTDC_VFP 1 -#define BOARD_LTDC_VBP 23 -#define BOARD_LTDC_HSYNC 0 -#define BOARD_LTDC_VSYNC 0 +#define BOARD_LTDC_VBP 23 /* AccumulatedVBP */ -#define BOARD_LTDC_PLLSAIN 192 -#define BOARD_LTDC_PLLSAIR 5 +#define BOARD_LTDC_HSYNC 1 /* HorizontalSync */ +#define BOARD_LTDC_VSYNC 1 /* VerticalSync */ /* Pixel Clock Polarity */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt index 2e6fdf74f62a3..72d80f069725f 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt @@ -70,6 +70,10 @@ if(CONFIG_CL_MFRC522) list(APPEND SRCS stm32_mfrc522.c) endif() +if(CONFIG_STM32H7_LTDC) + list(APPEND SRCS stm32_lcd.c) +endif() + target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile index b93701f189b46..6ab20189ff0f3 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile @@ -72,4 +72,8 @@ ifeq ($(CONFIG_BOARDCTL),y) CSRCS += stm32_appinitialize.c endif +ifeq ($(CONFIG_STM32H7_LTDC),y) +CSRCS += stm32_lcd.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h index bb1d8b3a091e7..2f959f00c9090 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h @@ -120,11 +120,13 @@ #define LINUMSTM32H753BI_QETIMER 5 -/* LCD */ +/* DISP_RESET */ #define GPIO_LCD_DISP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN7) +/* DISP_PWM */ + #define GPIO_LCD_BL (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ GPIO_OUTPUT_SET|GPIO_PORTH|GPIO_PIN6) diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c index e23c1aa7e027c..036a43b8551ea 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c @@ -75,10 +75,12 @@ static void convert_lcd_rgb565(void) stm32_gpiowrite(GPIO_LTDC_R1, 0); stm32_configgpio(GPIO_LTDC_R2); stm32_gpiowrite(GPIO_LTDC_R2, 0); + stm32_configgpio(GPIO_LTDC_G0); stm32_gpiowrite(GPIO_LTDC_G0, 0); stm32_configgpio(GPIO_LTDC_G1); stm32_gpiowrite(GPIO_LTDC_G1, 0); + stm32_configgpio(GPIO_LTDC_B0); stm32_gpiowrite(GPIO_LTDC_B0, 0); stm32_configgpio(GPIO_LTDC_B1);