From 6a25094fdc22b1c40759074046031ebd5e078316 Mon Sep 17 00:00:00 2001 From: Teddy van Jerry Date: Mon, 25 Mar 2024 20:56:40 +0800 Subject: [PATCH] Recommend PyTV VS Code Extension --- .vscode/extensions.json | 3 ++- README.md | 5 +++-- src/lib.rs | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/.vscode/extensions.json b/.vscode/extensions.json index ff19f8e..59aecce 100644 --- a/.vscode/extensions.json +++ b/.vscode/extensions.json @@ -1,6 +1,7 @@ { "recommendations": [ "rust-lang.rust-analyzer", - "redhat.vscode-yaml" + "redhat.vscode-yaml", + "teddy-van-jerry.pytv" ] } \ No newline at end of file diff --git a/README.md b/README.md index 5d8cad2..acfb6f8 100644 --- a/README.md +++ b/README.md @@ -19,12 +19,13 @@ cargo add pytv This is the basic feature of this package. ```pytv -//! a = 1 + 2; # Python inline +//! a = 1 + 2; # Python inline assign wire_`a` = wire_b; // Verilog with variable/expression substitute /*! -b = a ** 2; # Python block +b = a ** 2; # Python block */ ``` +The magic comment string can be configured (`!` as default). ### Instantiation The crate feature `inst` is enabled by default. diff --git a/src/lib.rs b/src/lib.rs index 75fa530..cc53f8a 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -9,7 +9,7 @@ //! //! # Examples //! ```txt -//! a = 1 + 2; # Python inline +//! //! a = 1 + 2; # Python inline //! assign wire_`a` = wire_b; // Verilog with variable/expression substitute //! /*! //! b = a ** 2; # Python block