diff --git a/README.md b/README.md
index 934213f..5d8cad2 100644
--- a/README.md
+++ b/README.md
@@ -18,6 +18,14 @@ cargo add pytv
 ### Python Template
 This is the basic feature of this package.
 
+```pytv
+//! a = 1 + 2; # Python inline
+assign wire_`a` = wire_b; // Verilog with variable/expression substitute
+/*!
+b = a ** 2; # Python block
+*/
+```
+
 ### Instantiation
 The crate feature `inst` is enabled by default.
 YAML contents between `<INST>` and `</INST>` are used to provide instantiation information.
diff --git a/src/lib.rs b/src/lib.rs
index c62e4ac..75fa530 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -8,7 +8,14 @@
 //! ```
 //! 
 //! # Examples
-//! To be added.
+//! ```txt
+//! a = 1 + 2;                #  Python inline
+//! assign wire_`a` = wire_b; // Verilog with variable/expression substitute
+//! /*!
+//! b = a ** 2;               #  Python block
+//! */
+//! ```
+//! The magic comment string can be configured (`!` as default).
 //! 
 //! # Related Auto Generator Projects
 //! - **FLAMES**: template-based C++ library for Vitis HLS