From 5a673095c4bc2dd6ba06bd148e7cbda0e8201466 Mon Sep 17 00:00:00 2001 From: AfonsoSantos96 Date: Tue, 15 Oct 2024 17:04:34 +0700 Subject: [PATCH 1/6] fix(aarch32/sysregs): fix the assessment of the 64-bit register read Signed-off-by: Afonso Santos --- src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h b/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h index 93cb8988..44c8eeff 100644 --- a/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h +++ b/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h @@ -40,7 +40,7 @@ { \ unsigned long long _temp, _tempH; \ __asm__ volatile("mrrc p15, " #op1 ", %0, %1, " #crm "\n\r" : "=r"(_temp), "=r"(_tempH)); \ - return ((_tempH << 32) | _temp); \ + return ((_tempH << 32) | ((unsigned long)_temp)); \ } \ static inline void sysreg_##reg##_write(unsigned long long val) \ { \ From e09ddf36f1c3f3f7999195095675ab019475c52e Mon Sep 17 00:00:00 2001 From: Jose Martins Date: Thu, 10 Oct 2024 11:56:15 +0100 Subject: [PATCH 2/6] fix(riscv/sbi): return not supported as error (not value) Signed-off-by: Jose Martins --- src/arch/riscv/sbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index a6699a2c..103a07fc 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -436,7 +436,7 @@ size_t sbi_vs_handler() break; default: WARNING("guest issued unsupport sbi extension call (%d)", extid); - ret.value = SBI_ERR_NOT_SUPPORTED; + ret.error = SBI_ERR_NOT_SUPPORTED; } vcpu_writereg(cpu()->vcpu, REG_A0, (unsigned long)ret.error); From 5eed1806c586f5b5bc9e6164eab925b93ee70b4c Mon Sep 17 00:00:00 2001 From: Jose Martins Date: Thu, 10 Oct 2024 11:57:11 +0100 Subject: [PATCH 3/6] fix(riscv/sbi): return hypcall error as sbi value Signed-off-by: Jose Martins --- src/arch/riscv/sbi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 103a07fc..668717c8 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -404,7 +404,10 @@ static struct sbiret sbi_bao_handler(unsigned long fid) { struct sbiret ret; - ret.error = hypercall(fid); + // Any hypercall will always be successful from a purely SBI standpoint. A + // bao-specific hypercall code is returned as the value. + ret.error = SBI_SUCCESS; + ret.value = hypercall(fid); return ret; } From 869b24c75aab2f90f2bf2ce176610396c3e678e9 Mon Sep 17 00:00:00 2001 From: Miguel Silva Date: Mon, 14 Oct 2024 16:24:45 +0100 Subject: [PATCH 4/6] fix(literal-size): Change literal from 1ULL to 1UL When compiling for RV32, the expected size of the argument used is 32-bit. Using 1ULL forces the argument to be 64-bit since shift operations take the size of the largest operand. This results in the error Werror=arith-conversion when compiling for RV32 Signed-off-by: Miguel Silva --- src/arch/riscv/inc/arch/csrs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/inc/arch/csrs.h b/src/arch/riscv/inc/arch/csrs.h index 9539028c..36072bfe 100644 --- a/src/arch/riscv/inc/arch/csrs.h +++ b/src/arch/riscv/inc/arch/csrs.h @@ -104,7 +104,7 @@ #define SSTATUS_XS_DIRTY (3ULL << SSTATUS_XS_OFF) #define SSTATUS_SUM (1ULL << 18) #define SSTATUS_MXR (1ULL << 19) -#define SSTATUS_SD (1ULL << 63) +#define SSTATUS_SD (1ULL << ((REGLEN * 8) - 1)) #define SIE_USIE (1ULL << 0) #define SIE_SSIE (1ULL << 1) From 3c244e5334bc15295b68eb93e64f4f732ed682aa Mon Sep 17 00:00:00 2001 From: Miguel Silva Date: Mon, 14 Oct 2024 16:28:14 +0100 Subject: [PATCH 5/6] fix(reg-size): Change the size of the shift to comply with word size Signed-off-by: Miguel Silva --- src/arch/riscv/irqc/aia/imsic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/irqc/aia/imsic.c b/src/arch/riscv/irqc/aia/imsic.c index bf27845b..06a9fa53 100644 --- a/src/arch/riscv/irqc/aia/imsic.c +++ b/src/arch/riscv/irqc/aia/imsic.c @@ -53,7 +53,7 @@ void imsic_init(void) void imsic_set_enbl(irqid_t intp_id) { csrs_siselect_write(IMSIC_EIE + imsic_eie_index(intp_id)); - csrs_sireg_set(1ULL << imsic_eie_bit(intp_id)); + csrs_sireg_set(1UL << imsic_eie_bit(intp_id)); } bool imsic_get_pend(irqid_t intp_id) @@ -65,7 +65,7 @@ bool imsic_get_pend(irqid_t intp_id) void imsic_clr_pend(irqid_t intp_id) { csrs_siselect_write(IMSIC_EIP + imsic_eie_index(intp_id)); - csrs_sireg_clear(1ULL << imsic_eie_bit(intp_id)); + csrs_sireg_clear(1UL << imsic_eie_bit(intp_id)); } /** @@ -77,7 +77,7 @@ void imsic_inject_pend(size_t guest_file, irqid_t intp_id) UNUSED_ARG(guest_file); csrs_vsiselect_write(IMSIC_EIP + imsic_eie_index(intp_id)); - csrs_vsireg_clear(1ULL << imsic_eie_bit(intp_id)); + csrs_vsireg_clear(1UL << imsic_eie_bit(intp_id)); } void imsic_send_msi(cpuid_t target_cpu, irqid_t ipi_id) From 179337b50b23c06687ee60728ad814f931d5a593 Mon Sep 17 00:00:00 2001 From: David Cerdeira Date: Fri, 18 Oct 2024 10:45:42 +0100 Subject: [PATCH 6/6] update(ci): bump ci version Signed-off-by: David Cerdeira --- ci | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci b/ci index f0fba61d..528dc02b 160000 --- a/ci +++ b/ci @@ -1 +1 @@ -Subproject commit f0fba61d699a73f5f658bde40cbc8b7f6803d2c2 +Subproject commit 528dc02b27b9728a5049248539afeff7ffe0a5e7