From b76daa45ecc46104897f6b4efb38cae757f0d21d Mon Sep 17 00:00:00 2001 From: ElectroQuanta <29806215+ElectroQuanta@users.noreply.github.com> Date: Fri, 18 Oct 2024 17:53:41 +0100 Subject: [PATCH] CI validated --- .../pl011_uart/inc/drivers/pl011_uart.h | 68 +++++++++---------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h b/src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h index a9320f95..28fda249 100644 --- a/src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h +++ b/src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h @@ -15,28 +15,28 @@ /* UART Base Address (PL011) */ -#define UART_BASE_0 0xFDF02000 -#define UART_BASE_1 0xFDF00000 -#define UART_BASE_2 0xFDF03000 -#define UART_BASE_4 0xFDF01000 -#define UART_BASE_5 0xFDF05000 -#define UART_BASE_6 0xFFF32000 +#define UART_BASE_0 0xFDF02000 +#define UART_BASE_1 0xFDF00000 +#define UART_BASE_2 0xFDF03000 +#define UART_BASE_4 0xFDF01000 +#define UART_BASE_5 0xFDF05000 +#define UART_BASE_6 0xFFF32000 /* UART Interrupts */ -#define UART_0_INTERRUPT 106 -#define UART_1_INTERRUPT 107 -#define UART_2_INTERRUPT 108 -#define UART_4_INTERRUPT 109 -#define UART_5_INTERRUPT 110 -#define UART_6_INTERRUPT 111 +#define UART_0_INTERRUPT 106 +#define UART_1_INTERRUPT 107 +#define UART_2_INTERRUPT 108 +#define UART_4_INTERRUPT 109 +#define UART_5_INTERRUPT 110 +#define UART_6_INTERRUPT 111 -#define NUM_UART 6 +#define NUM_UART 6 #ifndef UART_CLK -#define UART_CLK 19200000 +#define UART_CLK 19200000 #endif -#define UART_BAUD_RATE 115200 +#define UART_BAUD_RATE 115200 /* UART Data Register */ @@ -185,25 +185,25 @@ struct Pl011_Uart_hw { const uint8_t offset[PL011_PAGE_OFFSET]; // Offset for page alignment - volatile uint32_t data; // UART Data Register - volatile uint32_t status_error; // UART Receive Status Register/Error Clear - // Register - const uint32_t reserved1[4]; // Reserved: 4(0x4) bytes - volatile uint32_t flag; // UART Flag Register - const uint32_t reserved2[1]; // Reserved: 1(0x1) bytes - volatile uint32_t lp_counter; // UART Low-power Counter Register - volatile uint32_t integer_br; // UART Integer Baud Rate Register - volatile uint32_t fractional_br; // UART Fractional Baud Rate Register - volatile uint32_t line_control; // UART Line Control Register - volatile uint32_t control; // UART Control Register - volatile uint32_t isr_fifo_level_sel; // UART Interrupt FIFO level Select - // Register - volatile uint32_t isr_mask; // UART Interrupt Mask Set/Clear Register - volatile uint32_t raw_isr_status; // UART Raw Interrupt Status Register - volatile uint32_t masked_isr_status; // UART Masked Interrupt Status - // Register - volatile uint32_t isr_clear; // UART Interrupt Clear Register - volatile uint32_t DMA_control; // UART DMA control Register + volatile uint32_t data; // UART Data Register + volatile uint32_t status_error; // UART Receive Status Register/Error Clear + // Register + const uint32_t reserved1[4]; // Reserved: 4(0x4) bytes + volatile uint32_t flag; // UART Flag Register + const uint32_t reserved2[1]; // Reserved: 1(0x1) bytes + volatile uint32_t lp_counter; // UART Low-power Counter Register + volatile uint32_t integer_br; // UART Integer Baud Rate Register + volatile uint32_t fractional_br; // UART Fractional Baud Rate Register + volatile uint32_t line_control; // UART Line Control Register + volatile uint32_t control; // UART Control Register + volatile uint32_t isr_fifo_level_sel; // UART Interrupt FIFO level Select + // Register + volatile uint32_t isr_mask; // UART Interrupt Mask Set/Clear Register + volatile uint32_t raw_isr_status; // UART Raw Interrupt Status Register + volatile uint32_t masked_isr_status; // UART Masked Interrupt Status + // Register + volatile uint32_t isr_clear; // UART Interrupt Clear Register + volatile uint32_t DMA_control; // UART DMA control Register }; typedef struct Pl011_Uart_hw bao_uart_t;