From 40f6242099e70f35fe7401c848c4fc096e779587 Mon Sep 17 00:00:00 2001 From: Jose Martins Date: Wed, 30 Oct 2024 18:48:25 +0000 Subject: [PATCH] fix(riscv): add low order bits to faulting address Signed-off-by: Jose Martins --- src/arch/riscv/sync_exceptions.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/sync_exceptions.c b/src/arch/riscv/sync_exceptions.c index e44c5414..7b7ca3fc 100644 --- a/src/arch/riscv/sync_exceptions.c +++ b/src/arch/riscv/sync_exceptions.c @@ -80,7 +80,7 @@ static inline bool is_pseudo_ins(uint32_t ins) static size_t guest_page_fault_handler(void) { - vaddr_t addr = csrs_htval_read() << 2; + vaddr_t addr = (csrs_htval_read() << 2) | (csrs_stval_read() & 0x3); emul_handler_t handler = vm_emul_get_mem(cpu()->vcpu->vm, addr); if (handler != NULL) {