msx_eng.csv

# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# File: C:\Users\a\msx_eng\msx_eng.csv
# Generated on: Sun May 14 01:48:49 2023

# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.

To,Direction,Location,Fitter Location,Reserved
TCK,Input,,PIN_62,
TDI,Input,,PIN_4,
TDO,Output,,PIN_73,
TMS,Input,,PIN_15,
addr_i[0],Input,PIN_56,PIN_84,As input tri-stated
addr_i[1],Input,PIN_42,PIN_42,As input tri-stated
addr_i[2],Input,PIN_81,PIN_55,As input tri-stated
addr_i[3],Input,PIN_83,PIN_94,As input tri-stated
addr_i[4],Input,PIN_99,PIN_21,As input tri-stated
addr_i[5],Input,PIN_69,PIN_96,As input tri-stated
addr_i[6],Input,PIN_93,PIN_50,As input tri-stated
addr_i[7],Input,PIN_61,PIN_92,As input tri-stated
addr_i[8],Input,PIN_44,PIN_44,As input tri-stated
addr_i[9],Input,PIN_63,PIN_45,As input tri-stated
addr_i[10],Input,PIN_64,PIN_67,As input tri-stated
addr_i[11],Input,PIN_16,PIN_81,As input tri-stated
addr_i[12],Input,PIN_96,PIN_5,As input tri-stated
addr_i[13],Input,PIN_60,PIN_68,As input tri-stated
addr_i[14],Input,PIN_45,PIN_70,As input tri-stated
addr_i[15],Input,PIN_46,PIN_88,As input tri-stated
clk_i,Input,PIN_87,PIN_85,As input tri-stated
data_io[0],Bidir,PIN_68,PIN_37,As bidirectional
data_io[1],Bidir,PIN_85,PIN_9,As bidirectional
data_io[2],Bidir,PIN_94,PIN_36,As bidirectional
data_io[3],Bidir,PIN_80,PIN_29,As bidirectional
data_io[4],Bidir,PIN_98,PIN_28,As bidirectional
data_io[5],Bidir,PIN_79,PIN_13,As bidirectional
data_io[6],Bidir,PIN_21,PIN_12,As bidirectional
data_io[7],Bidir,PIN_57,PIN_10,As bidirectional
en_ascii16_n_i,Input,PIN_92,PIN_72,As input tri-stated
iorq_n_i,Input,PIN_19,PIN_23,As input tri-stated
m1_n_i,Input,PIN_20,PIN_54,As input tri-stated
mreq_n_i,Input,PIN_29,PIN_93,As input tri-stated
ppi_cs_n_o,Input,PIN_35,PIN_30,As input tri-stated
ppi_port_a_i[0],Input,PIN_9,PIN_83,As input tri-stated
ppi_port_a_i[1],Input,PIN_10,PIN_71,As input tri-stated
ppi_port_a_i[2],Input,PIN_84,PIN_56,As input tri-stated
ppi_port_a_i[3],Input,PIN_17,PIN_98,As input tri-stated
ppi_port_a_i[4],Input,PIN_58,PIN_48,As input tri-stated
ppi_port_a_i[5],Input,PIN_97,PIN_78,As input tri-stated
ppi_port_a_i[6],Input,PIN_48,PIN_77,As input tri-stated
ppi_port_a_i[7],Input,PIN_47,PIN_41,As input tri-stated
psg_bc1_o,Output,PIN_32,PIN_31,As output driving an unspecified signal
psg_bdir_o,Output,PIN_31,PIN_35,As output driving an unspecified signal
ram_cs_n_o,Output,PIN_13,PIN_100,As output driving an unspecified signal
rd_n_i,Input,PIN_30,PIN_17,As input tri-stated
reset_n_i,Input,PIN_90,PIN_89,As input tri-stated
rfsh_n_i,Input,PIN_71,PIN_79,As input tri-stated
rom_addr_o[14],Output,PIN_8,PIN_24,As output driving an unspecified signal
rom_addr_o[15],Output,PIN_23,PIN_1,As output driving an unspecified signal
rom_addr_o[16],Output,PIN_6,PIN_25,As output driving an unspecified signal
rom_addr_o[17],Output,PIN_14,PIN_99,As output driving an unspecified signal
rom_cs_n_o,Output,PIN_12,PIN_2,As output driving an unspecified signal
vdp_csrd_n_o,Output,PIN_37,PIN_32,As output driving an unspecified signal
vdp_cswr_n_o,Output,PIN_36,PIN_33,As output driving an unspecified signal
wr_n_i,Input,PIN_27,PIN_27,As input tri-stated