diff --git a/.github/workflows/build-wheels-publish.yml b/.github/workflows/build-wheels-publish.yml new file mode 100644 index 0000000000..ffed6b362d --- /dev/null +++ b/.github/workflows/build-wheels-publish.yml @@ -0,0 +1,279 @@ +# SPDX-FileCopyrightText: 2024 Antelox +# SPDX-License-Identifier: BSD-3 + +name: Build and publish wheels with cibuildwheel + +on: + workflow_dispatch: + inputs: + debugMode: + description: 'Debug Mode' + required: false + default: '' + type: choice + options: + - '0' + - '1' + + push: + paths-ignore: + - ".gitignore" + - "CREDITS.TXT" + - "ChangeLog" + - "README.md" + - "docs/**" + pull_request: + +env: + # Enable DEBUG flag either according to the tag release or manual override + CAPSTONE_DEBUG: ${{ inputs.debugMode != '' && inputs.debugMode || startsWith(github.ref, 'refs/tags') && '0' || '1' }} + +jobs: + # job to be executed for every push - testing purpose + build_wheels_always: + name: Building on ${{ matrix.os }} - ${{ matrix.arch }} - ${{ matrix.cibw_build }} + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + include: + # NOTE: Making this to parallelize and speed up workflow + # i686 - manylinux + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp38-manylinux* cp313-manylinux*', cibw_skip: '' } + # i686 - musllinux + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' } + # x86_64 - manylinux + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp38-manylinux* cp313-manylinux*', cibw_skip: '' } + # x86_64 - musllinux + # - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' } + # aarch64 - manylinux + # - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp38-manylinux* cp313-manylinux*', cibw_skip: '' } + # aarch64 - musllinux + # - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' } + # macos - x86_64 + - { os: macos-13, arch: x86_64, cibw_build: 'cp38* cp313*', cibw_skip: '' } + # macos - arm64 + # - { os: macos-latest, arch: arm64, cibw_build: 'cp38* cp313*', cibw_skip: '' } + # - { os: macos-latest, arch: universal2, cibw_build: 'cp38* cp313*', cibw_skip: '' } + # windows - x86_64 + - { os: windows-latest, arch: AMD64, cibw_build: 'cp38* cp313*', cibw_skip: '' } + # windows - amd64 + # - { os: windows-latest, arch: x86, cibw_build: 'cp38* cp313*', cibw_skip: '' } + # windows - arm64 + # - { os: windows-latest, arch: ARM64, cibw_build: 'cp39* cp313*', cibw_skip: '' } + + steps: + - uses: actions/checkout@v4 + + # https://github.com/actions/upload-artifact/issues/22 + - name: Prepare a unique name for Artifacts + shell: bash + run: | + # replace not-allowed chars with dash + name="cibw-wheels-${{ matrix.os }}-${{ matrix.arch }}-${{ matrix.cibw_build }}" + name=$(echo -n "$name" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g' | sed -e 's/\-$//') + echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV + + # https://cibuildwheel.pypa.io/en/stable/faq/#macos-building-cpython-38-wheels-on-arm64 + - uses: actions/setup-python@v5 + if: runner.os == 'macOS' && runner.arch == 'ARM64' + with: + python-version: 3.8 + + - name: '🛠️ Win MSVC 32 dev cmd setup' + if: runner.os == 'Windows' && matrix.arch == 'x86' + uses: ilammy/msvc-dev-cmd@v1 + with: + arch: x86 + + - name: '🛠️ Win MSVC 64 dev cmd setup' + if: runner.os == 'Windows' && matrix.arch == 'AMD64' + uses: ilammy/msvc-dev-cmd@v1 + with: + arch: x64 + + - name: '🛠️ Win MSVC ARM64 dev cmd setup' + if: runner.os == 'Windows' && matrix.arch == 'ARM64' + uses: ilammy/msvc-dev-cmd@v1 + with: + arch: amd64_arm64 + + - name: '🛠️ Set up QEMU' + if: runner.os == 'Linux' && matrix.arch != 'x86_64' + uses: docker/setup-qemu-action@v3 + + - name: '🚧 cibuildwheel run' + uses: pypa/cibuildwheel@v2.21.3 + env: + CIBW_BUILD_FRONTEND: build + CIBW_BUILD: ${{ matrix.cibw_build }} + CIBW_SKIP: ${{ matrix.cibw_skip }} + CIBW_ARCHS: ${{ matrix.arch }} + CIBW_ENVIRONMENT: DEBUG=${{ env.CAPSTONE_DEBUG }} + CIBW_ENVIRONMENT_PASS_LINUX: DEBUG + # https://cibuildwheel.pypa.io/en/stable/faq/#windows-arm64 + # https://github.com/pypa/cibuildwheel/pull/1169 + CIBW_TEST_SKIP: "*-win_arm64 cp38-macosx_*:arm64" + CIBW_TEST_COMMAND: > + python -m pip install {package}/cstest_py && + python {project}/suite/run_tests.py + with: + package-dir: bindings/python + output-dir: wheelhouse + + - uses: actions/upload-artifact@v4 + with: + name: ${{ env.ARTIFACT_NAME }} + path: ./wheelhouse/*.whl + + # To be executed only in case of a tag release + build_wheels_all: + name: Building on ${{ matrix.os }} - ${{ matrix.arch }} - ${{ matrix.cibw_build }} + runs-on: ${{ matrix.os }} + if: startsWith(github.ref, 'refs/tags') + strategy: + fail-fast: false + matrix: + include: + # NOTE: Making this to parallelize and speed up workflow + # i686 - manylinux + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp39-manylinux*', cibw_skip: '' } + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp310-manylinux*', cibw_skip: '' } + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp311-manylinux*', cibw_skip: '' } + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp312-manylinux*', cibw_skip: '' } + # i686 - musllinux + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp39-musllinux*', cibw_skip: '' } + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp310-musllinux*', cibw_skip: '' } + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp311-musllinux*', cibw_skip: '' } + # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp312-musllinux*', cibw_skip: '' } + # x86_64 - manylinux + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp39-manylinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp310-manylinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp311-manylinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp312-manylinux*', cibw_skip: '' } + # x86_64 - musllinux + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp39-musllinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp310-musllinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp311-musllinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp312-musllinux*', cibw_skip: '' } + # aarch64 - manylinux + - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp39-manylinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp310-manylinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp311-manylinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp312-manylinux*', cibw_skip: '' } + # aarch64 - musllinux + - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp39-musllinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp310-musllinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp311-musllinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp312-musllinux*', cibw_skip: '' } + # macos - x86_64 + - { os: macos-13, arch: x86_64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' } + # macos - arm64 + - { os: macos-latest, arch: arm64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' } + - { os: macos-latest, arch: universal2, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *39* *313*' } + # windows - amd64 + - { os: windows-latest, arch: AMD64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' } + # windows - x86 + # - { os: windows-latest, arch: x86, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' } + # windows - arm64 + - { os: windows-latest, arch: ARM64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *39* *313*' } + + steps: + - uses: actions/checkout@v4 + + # https://github.com/actions/upload-artifact/issues/22 + - name: Prepare a unique name for Artifacts + shell: bash + run: | + # replace not-allowed chars with dash + name="cibw-wheels-${{ matrix.os }}-${{ matrix.arch }}-${{ matrix.cibw_build }}" + name=$(echo -n "$name" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g' | sed -e 's/\-$//') + echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV + + - name: '🛠️ Win MSVC 32 dev cmd setup' + if: runner.os == 'Windows' && matrix.arch == 'x86' + uses: ilammy/msvc-dev-cmd@v1 + with: + arch: x86 + + - name: '🛠️ Win MSVC 64 dev cmd setup' + if: runner.os == 'Windows' && matrix.arch == 'AMD64' + uses: ilammy/msvc-dev-cmd@v1 + with: + arch: x64 + + - name: '🛠️ Win MSVC ARM64 dev cmd setup' + if: runner.os == 'Windows' && matrix.arch == 'ARM64' + uses: ilammy/msvc-dev-cmd@v1 + with: + arch: amd64_arm64 + + - name: '🛠️ Set up QEMU' + if: runner.os == 'Linux' && matrix.arch != 'x86_64' + uses: docker/setup-qemu-action@v3 + + - name: '🚧 cibuildwheel run' + uses: pypa/cibuildwheel@v2.21.3 + env: + CIBW_BUILD_FRONTEND: build + CIBW_BUILD: ${{ matrix.cibw_build }} + CIBW_SKIP: ${{ matrix.cibw_skip }} + CIBW_ARCHS: ${{ matrix.arch }} + CIBW_ENVIRONMENT: DEBUG=${{ env.CAPSTONE_DEBUG }} + CIBW_ENVIRONMENT_PASS_LINUX: DEBUG + # https://cibuildwheel.pypa.io/en/stable/faq/#windows-arm64 + CIBW_TEST_SKIP: "*-win_arm64" + CIBW_TEST_COMMAND: > + python -m pip install {package}/cstest_py && + python {project}/suite/run_tests.py + with: + package-dir: bindings/python + output-dir: wheelhouse + + - uses: actions/upload-artifact@v4 + with: + name: ${{ env.ARTIFACT_NAME }} + path: ./wheelhouse/*.whl + + make_sdist: + name: Make SDist + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 + submodules: true + + - name: Build SDist + run: | + cd bindings/python + python3 -m pip install -U pip build + python3 -m build --sdist + + - uses: actions/upload-artifact@v4 + with: + name: sdist-archive + path: bindings/python/dist/*.tar.gz + + publish: + needs: [ build_wheels_always, build_wheels_all, make_sdist ] + environment: pypi + permissions: + id-token: write + runs-on: ubuntu-latest + if: startsWith(github.ref, 'refs/tags') + steps: + - uses: actions/download-artifact@v4 + with: + merge-multiple: true + path: dist + + - name: Show downloaded artifacts + run: ls -laR dist + + - name: '📦 Publish distribution to PyPI' + uses: pypa/gh-action-pypi-publish@release/v1 + if: ${{ success() }} + with: + user: __token__ + password: ${{ secrets.pypi_pass }} diff --git a/.github/workflows/build_deb.yml b/.github/workflows/build_deb.yml new file mode 100644 index 0000000000..3caf6a0c28 --- /dev/null +++ b/.github/workflows/build_deb.yml @@ -0,0 +1,26 @@ +name: Build Debian Package + +on: workflow_dispatch + +jobs: + build: + name: build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 + submodules: true + + - name: Build Debian Package + working-directory: ./packages/deb + run: ./setup.sh "$(git describe --tags --abbrev=0)" + + - name: Run sanity checks on the Debian package + working-directory: ./packages/deb + run: | + ./check_capstone.sh ./libcapstone-dev.deb "$(git describe --tags --abbrev=0)" + + - uses: actions/upload-artifact@v4 + with: + path: ./packages/deb/libcapstone-dev.deb diff --git a/.github/workflows/build_release.yml b/.github/workflows/build_release.yml index 1e66ef9893..d818270ca8 100644 --- a/.github/workflows/build_release.yml +++ b/.github/workflows/build_release.yml @@ -14,31 +14,8 @@ jobs: - uses: actions/checkout@v4 with: submodules: true - - - name: Make setup.sh and check_capstone.sh are executable - run: | - chmod +x debian/setup.sh - chmod +x debian/check_capstone.sh - - - name: Build Debian Package - working-directory: ./debian - run: ./setup.sh ${{ github.event.release.tag_name }} - - - name: Run sanity checks on the Debian package - working-directory: ./debian - run: | - ./check_capstone.sh ./libcapstone-dev.deb ${{ github.event.release.tag_name }} - - - name: Upload debian package to release - uses: softprops/action-gh-release@v2 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - with: - tag_name: ${{ github.event.release.tag_name }} - files: | - ./debian/*.deb - - name: archive + - name: Create archive id: archive run: | VERSION=${{ github.event.release.tag_name }} diff --git a/.github/workflows/python-publish-release.yml b/.github/workflows/python-publish-release.yml deleted file mode 100644 index d1c15cd5f3..0000000000 --- a/.github/workflows/python-publish-release.yml +++ /dev/null @@ -1,90 +0,0 @@ -name: RELEASE BUILD - PyPI 📦 Distribution - -on: [push, pull_request, release, workflow_dispatch] - -jobs: - build_wheels: - name: Build wheels on ${{ matrix.os }} - runs-on: ${{ matrix.os }} - strategy: - matrix: - os: [ubuntu-latest, windows-latest, macos-latest] - steps: - - uses: actions/checkout@v4 - - - name: Set up MSVC x64 - if: matrix.os == 'windows-latest' - uses: ilammy/msvc-dev-cmd@v1 - - - name: Set up QEMU - if: runner.os == 'Linux' - uses: docker/setup-qemu-action@v3 - with: - platforms: all - - - name: Build wheels - uses: pypa/cibuildwheel@v2.20.0 - env: - CIBW_ARCHS_MACOS: "x86_64 universal2 arm64" - CIBW_ARCHS_LINUX: "x86_64 i686 aarch64" # ppc64le s390x really slow - CIBW_ARCHS_WINDOWS: "AMD64" # ARM64 Seems ARM64 will rebuild amd64 wheel for unknow reason. - CIBW_BUILD: "cp38-* cp39-* cp310-* cp311-* cp312-*" - CIBW_SKIP: "" - with: - package-dir: bindings/python - - - uses: actions/upload-artifact@v4 - with: - path: ./wheelhouse/*.whl - name: artifacts-${{ matrix.os }} - - - name: Check binaries (Windows) - if: matrix.os == 'windows-latest' - run: | - python3.exe suite/check_wheel_bin_arch.py ./wheelhouse/ - - - name: Check binaries (Unix) - if: matrix.os != 'windows-latest' - run: | - ./suite/check_wheel_bin_arch.py ./wheelhouse/ - - make_sdist: - name: Make SDist - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - with: - fetch-depth: 0 # Optional, use if you use setuptools_scm - submodules: true # Optional, use if you have submodules - - - name: Build SDist - run: | - cd bindings/python - pipx run build --sdist - - - uses: actions/upload-artifact@v4 - with: - path: bindings/python/dist/*.tar.gz - - publish: - needs: [build_wheels] - runs-on: ubuntu-latest - if: github.event_name == 'release' && github.event.action == 'released' - permissions: - id-token: write - steps: - - uses: actions/download-artifact@v4 - with: - merge-multiple: true - path: dist - - - name: Show downloaded artifacts - run: ls -laR dist - - - name: Publish distribution 📦 to PyPI - if: ${{ success() }} - uses: pypa/gh-action-pypi-publish@release/v1 - with: - verbose: true - user: __token__ - password: ${{ secrets.pypi_pass }} diff --git a/.github/workflows/python-tests.yml b/.github/workflows/python-tests.yml deleted file mode 100644 index 67dcde37f8..0000000000 --- a/.github/workflows/python-tests.yml +++ /dev/null @@ -1,62 +0,0 @@ -name: Python Package CI - -on: - push: - pull_request: - -# Stop previous runs on the same branch on new push -concurrency: - group: ${{ github.workflow }}-${{ github.ref }} - cancel-in-progress: true - -jobs: - build: - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: [ubuntu-24.04, windows-2022, macOS-14] - python-version: ["3.8", "3.12"] - - steps: - - uses: actions/checkout@v4 - - - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v5 - with: - python-version: ${{ matrix.python-version }} - - - name: Setup MSVC - if: runner.os == 'Windows' - uses: ilammy/msvc-dev-cmd@v1 - - - name: Build and install capstone - run: pip install ./bindings/python - - - name: Install cstest_py - run: pip install ./bindings/python/cstest_py - - - name: Run legacy tests - run: python ./bindings/python/tests/test_all.py - - - name: cstest_py integration tests - run: | - cd suite/cstest/test/ - python3 ./integration_tests.py cstest_py - cd ../../../ - - - name: cstest_py MC - run: | - cstest_py tests/MC/ - - - name: cstest_py details - run: | - cstest_py tests/details/ - - - name: cstest_py issues - run: | - cstest_py tests/issues/ - - - name: cstest_py features - run: | - cstest_py tests/features/ diff --git a/Mapping.h b/Mapping.h index a1f0aff4e4..d191c7a03c 100644 --- a/Mapping.h +++ b/Mapping.h @@ -34,6 +34,7 @@ typedef struct insn_map { aarch64_suppl_info aarch64; systemz_suppl_info systemz; arm_suppl_info arm; + xtensa_suppl_info xtensa; } suppl_info; // Supplementary information for each instruction. #endif } insn_map; diff --git a/arch/LoongArch/LoongArchMapping.c b/arch/LoongArch/LoongArchMapping.c index b32e42c685..e8a3746832 100644 --- a/arch/LoongArch/LoongArchMapping.c +++ b/arch/LoongArch/LoongArchMapping.c @@ -180,6 +180,9 @@ void LoongArch_rewrite_memory_operand(MCInst *MI) const loongarch_suppl_info *suppl_info = map_get_suppl_info(MI, loongarch_insns); + if (!suppl_info) + return; + if (suppl_info->memory_access == CS_AC_INVALID) { // not memory instruction return; diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c index 63a82371b6..0fb216758c 100644 --- a/arch/Xtensa/XtensaDisassembler.c +++ b/arch/Xtensa/XtensaDisassembler.c @@ -37,6 +37,7 @@ #include "../../SStream.h" #include "../../cs_priv.h" #include "../../utils.h" + #include "priv.h" #define GET_INSTRINFO_MC_DESC @@ -53,6 +54,40 @@ static const unsigned ARDecoderTable[] = { Xtensa_A12, Xtensa_A13, Xtensa_A14, Xtensa_A15 }; +static const unsigned AE_DRDecoderTable[] = { + Xtensa_AED0, Xtensa_AED1, Xtensa_AED2, Xtensa_AED3, + Xtensa_AED4, Xtensa_AED5, Xtensa_AED6, Xtensa_AED7, + Xtensa_AED8, Xtensa_AED9, Xtensa_AED10, Xtensa_AED11, + Xtensa_AED12, Xtensa_AED13, Xtensa_AED14, Xtensa_AED15 +}; + +static const unsigned AE_VALIGNDecoderTable[] = { Xtensa_U0, Xtensa_U1, + Xtensa_U2, Xtensa_U3 }; + +static DecodeStatus DecodeAE_DRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo >= ARR_SIZE(AE_DRDecoderTable)) + return MCDisassembler_Fail; + + unsigned Reg = AE_DRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAE_VALIGNRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo >= ARR_SIZE(AE_VALIGNDecoderTable)) + return MCDisassembler_Fail; + + unsigned Reg = AE_VALIGNDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + static DecodeStatus DecodeARRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { @@ -64,17 +99,414 @@ static DecodeStatus DecodeARRegisterClass(MCInst *Inst, uint64_t RegNo, return MCDisassembler_Success; } -static const unsigned SRDecoderTable[] = { Xtensa_SAR, 3 }; +static const unsigned QRDecoderTable[] = { Xtensa_Q0, Xtensa_Q1, Xtensa_Q2, + Xtensa_Q3, Xtensa_Q4, Xtensa_Q5, + Xtensa_Q6, Xtensa_Q7 }; + +static DecodeStatus DecodeQRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo >= ARR_SIZE(QRDecoderTable)) + return MCDisassembler_Fail; + + unsigned Reg = QRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static const unsigned FPRDecoderTable[] = { + Xtensa_F0, Xtensa_F1, Xtensa_F2, Xtensa_F3, Xtensa_F4, Xtensa_F5, + Xtensa_F6, Xtensa_F7, Xtensa_F8, Xtensa_F9, Xtensa_F10, Xtensa_F11, + Xtensa_F12, Xtensa_F13, Xtensa_F14, Xtensa_F15 +}; + +static DecodeStatus DecodeFPRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo >= ARR_SIZE(FPRDecoderTable)) + return MCDisassembler_Fail; + + unsigned Reg = FPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static const unsigned BRDecoderTable[] = { + Xtensa_B0, Xtensa_B1, Xtensa_B2, Xtensa_B3, Xtensa_B4, Xtensa_B5, + Xtensa_B6, Xtensa_B7, Xtensa_B8, Xtensa_B9, Xtensa_B10, Xtensa_B11, + Xtensa_B12, Xtensa_B13, Xtensa_B14, Xtensa_B15 +}; + +static const unsigned BR2DecoderTable[] = { Xtensa_B0_B1, Xtensa_B2_B3, + Xtensa_B4_B5, Xtensa_B6_B7, + Xtensa_B8_B9, Xtensa_B10_B11, + Xtensa_B12_B13, Xtensa_B14_B15 }; + +static const unsigned BR4DecoderTable[] = { Xtensa_B0_B1_B2_B3, + Xtensa_B4_B5_B6_B7, + Xtensa_B8_B9_B10_B11, + Xtensa_B12_B13_B14_B15 }; + +static DecodeStatus DecodeXtensaRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder, + const unsigned *DecoderTable, + size_t DecoderTableLen) +{ + if (RegNo >= DecoderTableLen) + return MCDisassembler_Fail; + + unsigned Reg = DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBR2RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return DecodeXtensaRegisterClass(Inst, RegNo, Address, Decoder, + BR2DecoderTable, + ARR_SIZE(BR2DecoderTable)); +} + +static DecodeStatus DecodeBR4RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return DecodeXtensaRegisterClass(Inst, RegNo, Address, Decoder, + BR4DecoderTable, + ARR_SIZE(BR4DecoderTable)); +} + +static DecodeStatus DecodeBRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo >= ARR_SIZE(BRDecoderTable)) + return MCDisassembler_Fail; + + unsigned Reg = BRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static const unsigned MRDecoderTable[] = { Xtensa_M0, Xtensa_M1, Xtensa_M2, + Xtensa_M3 }; + +static DecodeStatus DecodeMRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo >= ARR_SIZE(MRDecoderTable)) + return MCDisassembler_Fail; + + unsigned Reg = MRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static const unsigned MR01DecoderTable[] = { Xtensa_M0, Xtensa_M1 }; + +static DecodeStatus DecodeMR01RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo >= ARR_SIZE(MR01DecoderTable)) + return MCDisassembler_Fail; + + unsigned Reg = MR01DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static const unsigned MR23DecoderTable[] = { Xtensa_M2, Xtensa_M3 }; + +static DecodeStatus DecodeMR23RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + if ((RegNo < 2) || (RegNo > 3)) + return MCDisassembler_Fail; + + unsigned Reg = MR23DecoderTable[RegNo - 2]; + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +bool Xtensa_getFeatureBits(unsigned int mode, unsigned int feature) +{ + // we support everything + return true; +} + +// Verify SR and UR +bool CheckRegister(MCInst *Inst, unsigned RegNo) +{ + unsigned NumIntLevels = 0; + unsigned NumTimers = 0; + unsigned NumMiscSR = 0; + bool IsESP32 = false; + bool IsESP32S2 = false; + bool Res = true; + + // Assume that CPU is esp32 by default + if ((Inst->csh->mode & CS_MODE_XTENSA_ESP32)) { + NumIntLevels = 6; + NumTimers = 3; + NumMiscSR = 4; + IsESP32 = true; + } else if (Inst->csh->mode & CS_MODE_XTENSA_ESP32S2) { + NumIntLevels = 6; + NumTimers = 3; + NumMiscSR = 4; + IsESP32S2 = true; + } else if (Inst->csh->mode & CS_MODE_XTENSA_ESP8266) { + NumIntLevels = 2; + NumTimers = 1; + } + + switch (RegNo) { + case Xtensa_LBEG: + case Xtensa_LEND: + case Xtensa_LCOUNT: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureLoop); + break; + case Xtensa_BREG: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureBoolean); + break; + case Xtensa_LITBASE: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureExtendedL32R); + break; + case Xtensa_SCOMPARE1: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureS32C1I); + break; + case Xtensa_ACCLO: + case Xtensa_ACCHI: + case Xtensa_M0: + case Xtensa_M1: + case Xtensa_M2: + case Xtensa_M3: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureMAC16); + break; + case Xtensa_WINDOWBASE: + case Xtensa_WINDOWSTART: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureWindowed); + break; + case Xtensa_IBREAKENABLE: + case Xtensa_IBREAKA0: + case Xtensa_IBREAKA1: + case Xtensa_DBREAKA0: + case Xtensa_DBREAKA1: + case Xtensa_DBREAKC0: + case Xtensa_DBREAKC1: + case Xtensa_DEBUGCAUSE: + case Xtensa_ICOUNT: + case Xtensa_ICOUNTLEVEL: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureDebug); + break; + case Xtensa_ATOMCTL: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureATOMCTL); + break; + case Xtensa_MEMCTL: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureMEMCTL); + break; + case Xtensa_EPC1: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureException); + break; + case Xtensa_EPC2: + case Xtensa_EPC3: + case Xtensa_EPC4: + case Xtensa_EPC5: + case Xtensa_EPC6: + case Xtensa_EPC7: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureHighPriInterrupts); + Res = Res & (NumIntLevels >= (RegNo - Xtensa_EPC1)); + break; + case Xtensa_EPS2: + case Xtensa_EPS3: + case Xtensa_EPS4: + case Xtensa_EPS5: + case Xtensa_EPS6: + case Xtensa_EPS7: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureHighPriInterrupts); + Res = Res & (NumIntLevels > (RegNo - Xtensa_EPS2)); + break; + case Xtensa_EXCSAVE1: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureException); + break; + case Xtensa_EXCSAVE2: + case Xtensa_EXCSAVE3: + case Xtensa_EXCSAVE4: + case Xtensa_EXCSAVE5: + case Xtensa_EXCSAVE6: + case Xtensa_EXCSAVE7: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureHighPriInterrupts); + Res = Res & (NumIntLevels >= (RegNo - Xtensa_EXCSAVE1)); + break; + case Xtensa_DEPC: + case Xtensa_EXCCAUSE: + case Xtensa_EXCVADDR: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureException); + break; + case Xtensa_CPENABLE: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureCoprocessor); + break; + case Xtensa_VECBASE: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureRelocatableVector); + break; + case Xtensa_CCOUNT: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureTimerInt); + Res &= (NumTimers > 0); + break; + case Xtensa_CCOMPARE0: + case Xtensa_CCOMPARE1: + case Xtensa_CCOMPARE2: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureTimerInt); + Res &= (NumTimers > (RegNo - Xtensa_CCOMPARE0)); + break; + case Xtensa_PRID: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeaturePRID); + break; + case Xtensa_INTERRUPT: + case Xtensa_INTCLEAR: + case Xtensa_INTENABLE: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureInterrupt); + break; + case Xtensa_MISC0: + case Xtensa_MISC1: + case Xtensa_MISC2: + case Xtensa_MISC3: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureMiscSR); + Res &= (NumMiscSR > (RegNo - Xtensa_MISC0)); + break; + case Xtensa_THREADPTR: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureTHREADPTR); + break; + case Xtensa_GPIO_OUT: + Res = IsESP32S2; + break; + case Xtensa_EXPSTATE: + Res = IsESP32; + break; + case Xtensa_FCR: + case Xtensa_FSR: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureSingleFloat); + break; + case Xtensa_F64R_LO: + case Xtensa_F64R_HI: + case Xtensa_F64S: + Res = Xtensa_getFeatureBits(Inst->csh->mode, + Xtensa_FeatureDFPAccel); + break; + } + + return Res; +} + +static const unsigned SRDecoderTable[] = { + Xtensa_LBEG, 0, Xtensa_LEND, 1, + Xtensa_LCOUNT, 2, Xtensa_SAR, 3, + Xtensa_BREG, 4, Xtensa_LITBASE, 5, + Xtensa_SCOMPARE1, 12, Xtensa_ACCLO, 16, + Xtensa_ACCHI, 17, Xtensa_M0, 32, + Xtensa_M1, 33, Xtensa_M2, 34, + Xtensa_M3, 35, Xtensa_WINDOWBASE, 72, + Xtensa_WINDOWSTART, 73, Xtensa_IBREAKENABLE, 96, + Xtensa_MEMCTL, 97, Xtensa_ATOMCTL, 99, + Xtensa_DDR, 104, Xtensa_IBREAKA0, 128, + Xtensa_IBREAKA1, 129, Xtensa_DBREAKA0, 144, + Xtensa_DBREAKA1, 145, Xtensa_DBREAKC0, 160, + Xtensa_DBREAKC1, 161, Xtensa_CONFIGID0, 176, + Xtensa_EPC1, 177, Xtensa_EPC2, 178, + Xtensa_EPC3, 179, Xtensa_EPC4, 180, + Xtensa_EPC5, 181, Xtensa_EPC6, 182, + Xtensa_EPC7, 183, Xtensa_DEPC, 192, + Xtensa_EPS2, 194, Xtensa_EPS3, 195, + Xtensa_EPS4, 196, Xtensa_EPS5, 197, + Xtensa_EPS6, 198, Xtensa_EPS7, 199, + Xtensa_CONFIGID1, 208, Xtensa_EXCSAVE1, 209, + Xtensa_EXCSAVE2, 210, Xtensa_EXCSAVE3, 211, + Xtensa_EXCSAVE4, 212, Xtensa_EXCSAVE5, 213, + Xtensa_EXCSAVE6, 214, Xtensa_EXCSAVE7, 215, + Xtensa_CPENABLE, 224, Xtensa_INTERRUPT, 226, + Xtensa_INTCLEAR, 227, Xtensa_INTENABLE, 228, + Xtensa_PS, 230, Xtensa_VECBASE, 231, + Xtensa_EXCCAUSE, 232, Xtensa_DEBUGCAUSE, 233, + Xtensa_CCOUNT, 234, Xtensa_PRID, 235, + Xtensa_ICOUNT, 236, Xtensa_ICOUNTLEVEL, 237, + Xtensa_EXCVADDR, 238, Xtensa_CCOMPARE0, 240, + Xtensa_CCOMPARE1, 241, Xtensa_CCOMPARE2, 242, + Xtensa_MISC0, 244, Xtensa_MISC1, 245, + Xtensa_MISC2, 246, Xtensa_MISC3, 247 +}; static DecodeStatus DecodeSRRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + // const llvm_MCSubtargetInfo STI = + // ((const MCDisassembler *)Decoder)->getSubtargetInfo(); + if (RegNo > 255) return MCDisassembler_Fail; - for (unsigned i = 0; i + 1 < ARR_SIZE(SRDecoderTable); i += 2) { + for (unsigned i = 0; i < ARR_SIZE(SRDecoderTable); i += 2) { if (SRDecoderTable[i + 1] == RegNo) { unsigned Reg = SRDecoderTable[i]; + + if (!CheckRegister(Inst, Reg)) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; + } + } + + return MCDisassembler_Fail; +} + +static const unsigned URDecoderTable[] = { + Xtensa_GPIO_OUT, 0, Xtensa_EXPSTATE, 230, Xtensa_THREADPTR, 231, + Xtensa_FCR, 232, Xtensa_FSR, 233, Xtensa_F64R_LO, 234, + Xtensa_F64R_HI, 235, Xtensa_F64S, 236 +}; + +static DecodeStatus DecodeURRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo > 255) + return MCDisassembler_Fail; + + for (unsigned i = 0; i < ARR_SIZE(URDecoderTable); i += 2) { + if (URDecoderTable[i + 1] == RegNo) { + unsigned Reg = URDecoderTable[i]; + + if (!CheckRegister(Inst, Reg)) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -133,13 +565,21 @@ static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm, return MCDisassembler_Success; } +static DecodeStatus decodeLoopOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + if (!tryAddingSymbolicOperand(Imm + 4 + Address, true, Address, 0, 3, + Inst, Decoder)) + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { CS_ASSERT(isUIntN(16, Imm) && "Invalid immediate"); - MCOperand_CreateImm0( - Inst, - (SignExtend64(((Imm << 2) + 0x40000 + (Address & 0x3)), 17))); + MCOperand_CreateImm0(Inst, OneExtend64(Imm << 2, 18)); return MCDisassembler_Success; } @@ -154,7 +594,8 @@ static DecodeStatus decodeImm8Operand(MCInst *Inst, uint64_t Imm, static DecodeStatus decodeImm8_sh8Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { - CS_ASSERT(isUIntN(16, Imm) && "Invalid immediate"); + CS_ASSERT(isUIntN(16, Imm) && ((Imm & 0xff) == 0) && + "Invalid immediate"); MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 16))); return MCDisassembler_Success; } @@ -191,6 +632,67 @@ static DecodeStatus decodeImm1_16Operand(MCInst *Inst, uint64_t Imm, return MCDisassembler_Success; } +static DecodeStatus decodeImm1n_15Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(4, Imm) && "Invalid immediate"); + if (!Imm) + MCOperand_CreateImm0(Inst, (-1)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeImm32n_95Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(7, Imm) && "Invalid immediate"); + if ((Imm & 0x60) == 0x60) + MCOperand_CreateImm0(Inst, ((~0x1f) | Imm)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeImm8n_7Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(4, Imm) && "Invalid immediate"); + if (Imm > 7) + MCOperand_CreateImm0(Inst, (Imm - 16)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeImm64n_4nOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(6, Imm) && ((Imm & 0x3) == 0) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, ((~0x3f) | (Imm))); + return MCDisassembler_Success; +} + +static DecodeStatus decodeOffset8m32Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isUIntN(10, Imm) && ((Imm & 0x3) == 0) && + "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeEntry_Imm12OpValue(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isUIntN(15, Imm) && ((Imm & 0x7) == 0) && + "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + static DecodeStatus decodeShimm1_31Operand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { @@ -199,6 +701,144 @@ static DecodeStatus decodeShimm1_31Operand(MCInst *Inst, uint64_t Imm, return MCDisassembler_Success; } +//static DecodeStatus decodeShimm0_31Operand(MCInst *Inst, uint64_t Imm, +// int64_t Address, const void *Decoder) +//{ +// CS_ASSERT(isUIntN(5, Imm) && "Invalid immediate"); +// MCOperand_CreateImm0(Inst, (32 - Imm)); +// return MCDisassembler_Success; +//} + +static DecodeStatus decodeImm7_22Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(4, Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm + 7)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSelect_2Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSelect_4Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSelect_8Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSelect_16Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSelect_256Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeOffset_16_16Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isIntN(Imm, 8) && "Invalid immediate"); + if ((Imm & 0xf) != 0) + MCOperand_CreateImm0(Inst, (Imm << 4)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeOffset_256_8Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isIntN(16, Imm) && "Invalid immediate"); + if ((Imm & 0x7) != 0) + MCOperand_CreateImm0(Inst, (Imm << 3)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeOffset_256_16Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isIntN(16, Imm) && "Invalid immediate"); + if ((Imm & 0xf) != 0) + MCOperand_CreateImm0(Inst, (Imm << 4)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeOffset_256_4Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isIntN(16, Imm) && "Invalid immediate"); + if ((Imm & 0x2) != 0) + MCOperand_CreateImm0(Inst, (Imm << 2)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeOffset_128_2Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + if ((Imm & 0x1) != 0) + MCOperand_CreateImm0(Inst, (Imm << 1)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeOffset_128_1Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeOffset_64_16Operand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) +{ + CS_ASSERT(isIntN(16, Imm) && "Invalid immediate"); + if ((Imm & 0xf) != 0) + MCOperand_CreateImm0(Inst, (Imm << 4)); + else + MCOperand_CreateImm0(Inst, (Imm)); + return MCDisassembler_Success; +} + static int64_t TableB4const[16] = { -1, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 }; static DecodeStatus decodeB4constOperand(MCInst *Inst, uint64_t Imm, @@ -248,40 +888,202 @@ static DecodeStatus decodeMem32Operand(MCInst *Inst, uint64_t Imm, return MCDisassembler_Success; } +static DecodeStatus decodeMem32nOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate"); + DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder); + MCOperand_CreateImm0(Inst, ((Imm >> 2) & 0x3c)); + return MCDisassembler_Success; +} + +/// Read two bytes from the ArrayRef and return 16 bit data sorted +/// according to the given endianness. +static DecodeStatus readInstruction16(MCInst *MI, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, + uint64_t *Size, uint64_t *Insn, + bool IsLittleEndian) +{ + // We want to read exactly 2 Bytes of data. + if (BytesLen < 2) { + *Size = 0; + return MCDisassembler_Fail; + } + + *Insn = readBytes16(MI, Bytes); + *Size = 2; + + return MCDisassembler_Success; +} + /// Read three bytes from the ArrayRef and return 24 bit data -static DecodeStatus readInstruction24(MCInst *MI, uint64_t *SizeOut, - const uint8_t *Bytes, - const unsigned BytesSize, uint32_t *Insn) +static DecodeStatus readInstruction24(MCInst *MI, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, + uint64_t *Size, uint64_t *Insn, + bool IsLittleEndian, bool CheckTIE) { // We want to read exactly 3 Bytes of data. - if (BytesSize < 3) { - *SizeOut = 0; + if (BytesLen < 3) { + *Size = 0; return MCDisassembler_Fail; } + if (CheckTIE && (Bytes[0] & 0x8) != 0) + return MCDisassembler_Fail; *Insn = readBytes24(MI, Bytes); - *SizeOut = 3; + *Size = 3; + + return MCDisassembler_Success; +} + +/// Read three bytes from the ArrayRef and return 32 bit data +static DecodeStatus readInstruction32(MCInst *MI, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, + uint64_t *Size, uint64_t *Insn, + bool IsLittleEndian) +{ + // We want to read exactly 4 Bytes of data. + if (BytesLen < 4) { + *Size = 0; + return MCDisassembler_Fail; + } + + if ((Bytes[0] & 0x8) == 0) + return MCDisassembler_Fail; + *Insn = readBytes32(MI, Bytes); + *Size = 4; + + return MCDisassembler_Success; +} + +/// Read InstSize bytes from the ArrayRef and return 24 bit data +static DecodeStatus readInstructionN(const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, unsigned InstSize, + uint64_t *Size, uint64_t *Insn, + bool IsLittleEndian) +{ + // We want to read exactly 3 Bytes of data. + if (BytesLen < InstSize) { + *Size = 0; + return MCDisassembler_Fail; + } + + *Insn = 0; + for (unsigned i = 0; i < InstSize; i++) + *Insn |= (uint64_t)(Bytes[i]) << (8 * i); + + *Size = InstSize; return MCDisassembler_Success; } #include "XtensaGenDisassemblerTables.inc" -FieldFromInstruction(field_from_inst, uint32_t); -DecodeToMCInst(decode_to_MCInst, field_from_inst, uint32_t); -DecodeInstruction(decodeInstruction, field_from_inst, decode_to_MCInst, - uint32_t); +FieldFromInstruction(fieldFromInstruction_2, uint64_t); +DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint64_t); +DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, + uint64_t); + +FieldFromInstruction(fieldFromInstruction_4, uint64_t); +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint64_t); +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, + uint64_t); -static DecodeStatus getInstruction(MCInst *MI, uint64_t *SizeOut, - const uint8_t *Bytes, unsigned BytesSize, +FieldFromInstruction(fieldFromInstruction_6, uint64_t); +DecodeToMCInst(decodeToMCInst_6, fieldFromInstruction_6, uint64_t); +DecodeInstruction(decodeInstruction_6, fieldFromInstruction_6, decodeToMCInst_6, + uint64_t); + +static bool hasDensity() +{ + return true; +} +static bool hasESP32S3Ops() +{ + return true; +} +static bool hasHIFI3() +{ + return true; +} + +static DecodeStatus getInstruction(MCInst *MI, uint64_t *Size, + const uint8_t *Bytes, size_t BytesLen, uint64_t Address) { - uint32_t Insn; + uint64_t Insn; DecodeStatus Result; + bool IsLittleEndian = MI->csh->mode & CS_MODE_LITTLE_ENDIAN; + + // Parse 16-bit instructions + if (hasDensity()) { + Result = readInstruction16(MI, Bytes, BytesLen, Address, Size, + &Insn, IsLittleEndian); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + Result = decodeInstruction_2(DecoderTable16, MI, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + } - Result = readInstruction24(MI, SizeOut, Bytes, BytesSize, &Insn); + // Parse Core 24-bit instructions + Result = readInstruction24(MI, Bytes, BytesLen, Address, Size, &Insn, + IsLittleEndian, false); if (Result == MCDisassembler_Fail) return MCDisassembler_Fail; - Result = decodeInstruction(DecoderTable24, MI, Insn, Address, NULL); + + Result = decodeInstruction_3(DecoderTable24, MI, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 3; + return Result; + } + + if (hasESP32S3Ops()) { + // Parse ESP32S3 24-bit instructions + Result = readInstruction24(MI, Bytes, BytesLen, Address, Size, + &Insn, IsLittleEndian, true); + if (Result != MCDisassembler_Fail) { + Result = decodeInstruction_3(DecoderTableESP32S324, MI, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 3; + return Result; + } + } + + // Parse ESP32S3 32-bit instructions + Result = readInstruction32(MI, Bytes, BytesLen, Address, Size, + &Insn, IsLittleEndian); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + Result = decodeInstruction_4(DecoderTableESP32S332, MI, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + if (hasHIFI3()) { + Result = decodeInstruction_3(DecoderTableHIFI324, MI, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + + Result = readInstructionN(Bytes, BytesLen, Address, 48, Size, + &Insn, IsLittleEndian); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + Result = decodeInstruction_6(DecoderTableHIFI348, MI, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } return Result; } diff --git a/arch/Xtensa/XtensaGenAsmWriter.inc b/arch/Xtensa/XtensaGenAsmWriter.inc index 3bf2f06f23..4ac64df812 100644 --- a/arch/Xtensa/XtensaGenAsmWriter.inc +++ b/arch/Xtensa/XtensaGenAsmWriter.inc @@ -12,111 +12,1723 @@ /* https://github.com/capstone-engine/llvm-capstone */ #include -#include +#include "../../cs_priv.h" /// getMnemonic - This method is automatically generated by tablegen /// from the instruction set description. static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ "call0\t\0" - /* 7 */ "callx0\t\0" - /* 15 */ "subx2\t\0" - /* 22 */ "addx2\t\0" - /* 29 */ "subx4\t\0" - /* 36 */ "addx4\t\0" - /* 43 */ "subx8\t\0" - /* 50 */ "addx8\t\0" - /* 57 */ "sra\t\0" - /* 62 */ "sub\t\0" - /* 67 */ "bbc\t\0" - /* 72 */ "src\t\0" - /* 77 */ "add\t\0" - /* 82 */ "and\t\0" - /* 87 */ "bge\t\0" - /* 92 */ "bne\t\0" - /* 97 */ "bnone\t\0" - /* 104 */ "neg\t\0" - /* 109 */ "l32i\t\0" - /* 115 */ "s32i\t\0" - /* 121 */ "s16i\t\0" - /* 127 */ "s8i\t\0" - /* 132 */ "srai\t\0" - /* 138 */ "ssai\t\0" - /* 144 */ "bbci\t\0" - /* 150 */ "addi\t\0" - /* 156 */ "bgei\t\0" - /* 162 */ "bnei\t\0" - /* 168 */ "slli\t\0" - /* 174 */ "srli\t\0" - /* 180 */ "addmi\t\0" - /* 187 */ "beqi\t\0" - /* 193 */ "l16si\t\0" - /* 200 */ "bbsi\t\0" - /* 206 */ "blti\t\0" - /* 212 */ "l16ui\t\0" - /* 219 */ "l8ui\t\0" - /* 225 */ "bgeui\t\0" - /* 232 */ "bltui\t\0" - /* 239 */ "extui\t\0" - /* 246 */ "movi\t\0" - /* 252 */ "j\t\0" - /* 255 */ "ssa8l\t\0" - /* 262 */ "ball\t\0" - /* 268 */ "bnall\t\0" - /* 275 */ "sll\t\0" - /* 280 */ "srl\t\0" - /* 285 */ "ssl\t\0" - /* 290 */ "beq\t\0" - /* 295 */ "l32r\t\0" - /* 301 */ "xor\t\0" - /* 306 */ "rsr\t\0" - /* 311 */ "ssr\t\0" - /* 316 */ "wsr\t\0" - /* 321 */ "xsr\t\0" - /* 326 */ "abs\t\0" - /* 331 */ "bbs\t\0" - /* 336 */ "blt\t\0" - /* 341 */ "bgeu\t\0" - /* 347 */ "bltu\t\0" - /* 353 */ "jx\t\0" - /* 357 */ "bany\t\0" - /* 363 */ "bgez\t\0" - /* 369 */ "movgez\t\0" - /* 377 */ "bnez\t\0" - /* 383 */ "movnez\t\0" - /* 391 */ "beqz\t\0" - /* 397 */ "moveqz\t\0" - /* 405 */ "bltz\t\0" - /* 411 */ "movltz\t\0" - /* 419 */ "# XRay Function Patchable RET.\0" - /* 450 */ "# XRay Typed Event Log.\0" - /* 474 */ "# XRay Custom Event Log.\0" - /* 499 */ "# XRay Function Enter.\0" - /* 522 */ "# XRay Tail Call Exit.\0" - /* 545 */ "# XRay Function Exit.\0" - /* 567 */ "LIFETIME_END\0" - /* 580 */ "PSEUDO_PROBE\0" - /* 593 */ "BUNDLE\0" - /* 600 */ "DBG_VALUE\0" - /* 610 */ "DBG_INSTR_REF\0" - /* 624 */ "DBG_PHI\0" - /* 632 */ "DBG_LABEL\0" - /* 642 */ "LIFETIME_START\0" - /* 657 */ "DBG_VALUE_LIST\0" - /* 672 */ "dsync\0" - /* 678 */ "esync\0" - /* 684 */ "isync\0" - /* 690 */ "rsync\0" - /* 696 */ "# FEntry call\0" - /* 710 */ "nop\0" - /* 714 */ "ret\0" - /* 718 */ "memw\0" - /* 723 */ "extw\0" + /* 0 */ "wur.fcr \t\0" + /* 10 */ "call0\t\0" + /* 17 */ "callx0\t\0" + /* 25 */ "call12\t\0" + /* 33 */ "callx12\t\0" + /* 42 */ "subx2\t\0" + /* 49 */ "addx2\t\0" + /* 56 */ "call4\t\0" + /* 63 */ "subx4\t\0" + /* 70 */ "addx4\t\0" + /* 77 */ "callx4\t\0" + /* 85 */ "any4\t\0" + /* 91 */ "call8\t\0" + /* 98 */ "subx8\t\0" + /* 105 */ "addx8\t\0" + /* 112 */ "callx8\t\0" + /* 120 */ "any8\t\0" + /* 126 */ "sra\t\0" + /* 131 */ "nsa\t\0" + /* 136 */ "andb\t\0" + /* 142 */ "wdtlb\t\0" + /* 149 */ "witlb\t\0" + /* 156 */ "xorb\t\0" + /* 162 */ "sub\t\0" + /* 167 */ "bbc\t\0" + /* 172 */ "andbc\t\0" + /* 179 */ "orbc\t\0" + /* 185 */ "ee.zero.qacc\t\0" + /* 199 */ "src\t\0" + /* 204 */ "add\t\0" + /* 209 */ "and\t\0" + /* 214 */ "l32e\t\0" + /* 220 */ "s32e\t\0" + /* 226 */ "bge\t\0" + /* 231 */ "bne\t\0" + /* 236 */ "bnone\t\0" + /* 243 */ "bf\t\0" + /* 247 */ "movf\t\0" + /* 253 */ "neg\t\0" + /* 258 */ "mula.aa.hh\t\0" + /* 270 */ "umul.aa.hh\t\0" + /* 282 */ "muls.aa.hh\t\0" + /* 294 */ "mula.da.hh\t\0" + /* 306 */ "mul.da.hh\t\0" + /* 317 */ "muls.da.hh\t\0" + /* 329 */ "mula.ad.hh\t\0" + /* 341 */ "mul.ad.hh\t\0" + /* 352 */ "muls.ad.hh\t\0" + /* 364 */ "mula.dd.hh\t\0" + /* 376 */ "mul.dd.hh\t\0" + /* 387 */ "muls.dd.hh\t\0" + /* 399 */ "mula.aa.lh\t\0" + /* 411 */ "umul.aa.lh\t\0" + /* 423 */ "muls.aa.lh\t\0" + /* 435 */ "mula.da.lh\t\0" + /* 447 */ "mul.da.lh\t\0" + /* 458 */ "muls.da.lh\t\0" + /* 470 */ "mula.ad.lh\t\0" + /* 482 */ "mul.ad.lh\t\0" + /* 493 */ "muls.ad.lh\t\0" + /* 505 */ "mula.dd.lh\t\0" + /* 517 */ "mul.dd.lh\t\0" + /* 528 */ "muls.dd.lh\t\0" + /* 540 */ "mulsh\t\0" + /* 547 */ "muluh\t\0" + /* 554 */ "s32c1i\t\0" + /* 562 */ "_l32i\t\0" + /* 569 */ "_s32i\t\0" + /* 576 */ "s16i\t\0" + /* 582 */ "s8i\t\0" + /* 587 */ "srai\t\0" + /* 593 */ "ssai\t\0" + /* 599 */ "bbci\t\0" + /* 605 */ "addi\t\0" + /* 611 */ "bgei\t\0" + /* 617 */ "bnei\t\0" + /* 623 */ "rfi\t\0" + /* 628 */ "_slli\t\0" + /* 635 */ "_srli\t\0" + /* 642 */ "addmi\t\0" + /* 649 */ "beqi\t\0" + /* 655 */ "l16si\t\0" + /* 662 */ "bbsi\t\0" + /* 668 */ "lsi\t\0" + /* 673 */ "ssi\t\0" + /* 678 */ "waiti\t\0" + /* 685 */ "blti\t\0" + /* 691 */ "l16ui\t\0" + /* 698 */ "l8ui\t\0" + /* 704 */ "bgeui\t\0" + /* 711 */ "bltui\t\0" + /* 718 */ "extui\t\0" + /* 725 */ "_movi\t\0" + /* 732 */ "j\t\0" + /* 735 */ "break\t\0" + /* 742 */ "ssa8l\t\0" + /* 749 */ "mula.aa.hl\t\0" + /* 761 */ "umul.aa.hl\t\0" + /* 773 */ "muls.aa.hl\t\0" + /* 785 */ "mula.da.hl\t\0" + /* 797 */ "mul.da.hl\t\0" + /* 808 */ "muls.da.hl\t\0" + /* 820 */ "mula.ad.hl\t\0" + /* 832 */ "mul.ad.hl\t\0" + /* 843 */ "muls.ad.hl\t\0" + /* 855 */ "mula.dd.hl\t\0" + /* 867 */ "mul.dd.hl\t\0" + /* 878 */ "muls.dd.hl\t\0" + /* 890 */ "rsil\t\0" + /* 896 */ "mula.aa.ll\t\0" + /* 908 */ "umul.aa.ll\t\0" + /* 920 */ "muls.aa.ll\t\0" + /* 932 */ "mula.da.ll\t\0" + /* 944 */ "mul.da.ll\t\0" + /* 955 */ "muls.da.ll\t\0" + /* 967 */ "mula.ad.ll\t\0" + /* 979 */ "mul.ad.ll\t\0" + /* 990 */ "muls.ad.ll\t\0" + /* 1002 */ "mula.dd.ll\t\0" + /* 1014 */ "mul.dd.ll\t\0" + /* 1025 */ "muls.dd.ll\t\0" + /* 1037 */ "ball\t\0" + /* 1043 */ "bnall\t\0" + /* 1050 */ "sll\t\0" + /* 1055 */ "mull\t\0" + /* 1061 */ "srl\t\0" + /* 1066 */ "ssl\t\0" + /* 1071 */ "add.n\t\0" + /* 1078 */ "_l32i.n\t\0" + /* 1087 */ "_s32i.n\t\0" + /* 1096 */ "addi.n\t\0" + /* 1104 */ "movi.n\t\0" + /* 1112 */ "break.n\t\0" + /* 1121 */ "mov.n\t\0" + /* 1128 */ "ee.get_gpio_in\t\0" + /* 1144 */ "min\t\0" + /* 1149 */ "lsip\t\0" + /* 1155 */ "ssip\t\0" + /* 1161 */ "loop\t\0" + /* 1167 */ "movsp\t\0" + /* 1174 */ "lsxp\t\0" + /* 1180 */ "ssxp\t\0" + /* 1186 */ "beq\t\0" + /* 1191 */ "l32r\t\0" + /* 1197 */ "rer\t\0" + /* 1202 */ "wer\t\0" + /* 1207 */ "rfr\t\0" + /* 1212 */ "wfr\t\0" + /* 1217 */ "xor\t\0" + /* 1222 */ "rsr\t\0" + /* 1227 */ "ssr\t\0" + /* 1232 */ "wsr\t\0" + /* 1237 */ "xsr\t\0" + /* 1242 */ "rur\t\0" + /* 1247 */ "wur\t\0" + /* 1252 */ "recip0.s\t\0" + /* 1262 */ "rsqrt0.s\t\0" + /* 1272 */ "div0.s\t\0" + /* 1280 */ "nexp01.s\t\0" + /* 1290 */ "msub.s\t\0" + /* 1298 */ "utrunc.s\t\0" + /* 1308 */ "madd.s\t\0" + /* 1316 */ "round.s\t\0" + /* 1325 */ "ole.s\t\0" + /* 1332 */ "ule.s\t\0" + /* 1339 */ "movf.s\t\0" + /* 1347 */ "neg.s\t\0" + /* 1354 */ "mkdadj.s\t\0" + /* 1364 */ "mksadj.s\t\0" + /* 1374 */ "ceil.s\t\0" + /* 1382 */ "mul.s\t\0" + /* 1389 */ "addexpm.s\t\0" + /* 1400 */ "maddn.s\t\0" + /* 1409 */ "un.s\t\0" + /* 1415 */ "divn.s\t\0" + /* 1423 */ "addexp.s\t\0" + /* 1433 */ "oeq.s\t\0" + /* 1440 */ "ueq.s\t\0" + /* 1447 */ "floor.s\t\0" + /* 1456 */ "abs.s\t\0" + /* 1463 */ "ufloat.s\t\0" + /* 1473 */ "olt.s\t\0" + /* 1480 */ "ult.s\t\0" + /* 1487 */ "const.s\t\0" + /* 1496 */ "movt.s\t\0" + /* 1504 */ "mov.s\t\0" + /* 1511 */ "movgez.s\t\0" + /* 1521 */ "movnez.s\t\0" + /* 1531 */ "moveqz.s\t\0" + /* 1541 */ "movltz.s\t\0" + /* 1551 */ "mul16s\t\0" + /* 1559 */ "abs\t\0" + /* 1564 */ "bbs\t\0" + /* 1569 */ "rems\t\0" + /* 1575 */ "quos\t\0" + /* 1581 */ "clamps\t\0" + /* 1589 */ "bt\t\0" + /* 1593 */ "blt\t\0" + /* 1598 */ "ee.wr_mask_gpio_out\t\0" + /* 1619 */ "ee.clr_bit_gpio_out\t\0" + /* 1640 */ "ee.set_bit_gpio_out\t\0" + /* 1661 */ "movt\t\0" + /* 1667 */ "sext\t\0" + /* 1673 */ "mul16u\t\0" + /* 1681 */ "nsau\t\0" + /* 1687 */ "bgeu\t\0" + /* 1693 */ "remu\t\0" + /* 1699 */ "minu\t\0" + /* 1705 */ "quou\t\0" + /* 1711 */ "bltu\t\0" + /* 1717 */ "maxu\t\0" + /* 1723 */ "rotw\t\0" + /* 1729 */ "max\t\0" + /* 1734 */ "ee.zero.accx\t\0" + /* 1748 */ "jx\t\0" + /* 1752 */ "lsx\t\0" + /* 1757 */ "ssx\t\0" + /* 1762 */ "bany\t\0" + /* 1768 */ "entry\t\0" + /* 1775 */ "bgez\t\0" + /* 1781 */ "movgez\t\0" + /* 1789 */ "bnez\t\0" + /* 1795 */ "loopnez\t\0" + /* 1804 */ "movnez\t\0" + /* 1812 */ "beqz\t\0" + /* 1818 */ "moveqz\t\0" + /* 1826 */ "loopgtz\t\0" + /* 1835 */ "bltz\t\0" + /* 1841 */ "movltz\t\0" + /* 1849 */ "rur.ua_state_0\t \0" + /* 1866 */ "wur.ua_state_0\t \0" + /* 1883 */ "rur.qacc_h_0\t \0" + /* 1898 */ "wur.qacc_h_0\t \0" + /* 1913 */ "rur.qacc_l_0\t \0" + /* 1928 */ "wur.qacc_l_0\t \0" + /* 1943 */ "rur.accx_0\t \0" + /* 1956 */ "wur.accx_0\t \0" + /* 1969 */ "rur.ua_state_1\t \0" + /* 1986 */ "wur.ua_state_1\t \0" + /* 2003 */ "rur.qacc_h_1\t \0" + /* 2018 */ "wur.qacc_h_1\t \0" + /* 2033 */ "rur.qacc_l_1\t \0" + /* 2048 */ "wur.qacc_l_1\t \0" + /* 2063 */ "rur.accx_1\t \0" + /* 2076 */ "wur.accx_1\t \0" + /* 2089 */ "ee.vldbc.32\t \0" + /* 2103 */ "ee.vsl.32\t \0" + /* 2115 */ "ee.vunzip.32\t \0" + /* 2130 */ "ee.vzip.32\t \0" + /* 2143 */ "ee.ldxq.32\t \0" + /* 2156 */ "ee.stxq.32\t \0" + /* 2169 */ "ee.vsr.32\t \0" + /* 2181 */ "ee.vmin.s32\t \0" + /* 2195 */ "ee.vcmp.eq.s32\t \0" + /* 2212 */ "ee.vsubs.s32\t \0" + /* 2227 */ "ee.vadds.s32\t \0" + /* 2242 */ "ee.vcmp.gt.s32\t \0" + /* 2259 */ "ee.vcmp.lt.s32\t \0" + /* 2276 */ "ee.vmax.s32\t \0" + /* 2290 */ "rur.ua_state_2\t \0" + /* 2307 */ "wur.ua_state_2\t \0" + /* 2324 */ "rur.qacc_h_2\t \0" + /* 2339 */ "wur.qacc_h_2\t \0" + /* 2354 */ "rur.qacc_l_2\t \0" + /* 2369 */ "wur.qacc_l_2\t \0" + /* 2384 */ "rur.ua_state_3\t \0" + /* 2401 */ "wur.ua_state_3\t \0" + /* 2418 */ "rur.qacc_h_3\t \0" + /* 2433 */ "wur.qacc_h_3\t \0" + /* 2448 */ "rur.qacc_l_3\t \0" + /* 2463 */ "wur.qacc_l_3\t \0" + /* 2478 */ "rur.qacc_h_4\t \0" + /* 2493 */ "wur.qacc_h_4\t \0" + /* 2508 */ "rur.qacc_l_4\t \0" + /* 2523 */ "wur.qacc_l_4\t \0" + /* 2538 */ "ee.vldbc.16\t \0" + /* 2552 */ "ee.vunzip.16\t \0" + /* 2567 */ "ee.vzip.16\t \0" + /* 2580 */ "ee.fft.r2bf.s16\t \0" + /* 2598 */ "ee.cmul.s16\t \0" + /* 2612 */ "ee.vmul.s16\t \0" + /* 2626 */ "ee.vmin.s16\t \0" + /* 2640 */ "ee.vcmp.eq.s16\t \0" + /* 2657 */ "ee.vsubs.s16\t \0" + /* 2672 */ "ee.vadds.s16\t \0" + /* 2687 */ "ee.vcmp.gt.s16\t \0" + /* 2704 */ "ee.vcmp.lt.s16\t \0" + /* 2721 */ "ee.vprelu.s16\t \0" + /* 2737 */ "ee.vrelu.s16\t \0" + /* 2752 */ "ee.vmax.s16\t \0" + /* 2766 */ "ee.vmul.u16\t \0" + /* 2780 */ "ee.vldbc.8\t \0" + /* 2793 */ "ee.vunzip.8\t \0" + /* 2807 */ "ee.vzip.8\t \0" + /* 2819 */ "ee.vmul.s8\t \0" + /* 2832 */ "ee.vmin.s8\t \0" + /* 2845 */ "ee.vcmp.eq.s8\t \0" + /* 2861 */ "ee.vsubs.s8\t \0" + /* 2875 */ "ee.vadds.s8\t \0" + /* 2889 */ "ee.vcmp.gt.s8\t \0" + /* 2905 */ "ee.vcmp.lt.s8\t \0" + /* 2921 */ "ee.vprelu.s8\t \0" + /* 2936 */ "ee.vrelu.s8\t \0" + /* 2950 */ "ee.vmax.s8\t \0" + /* 2963 */ "ee.vmul.u8\t \0" + /* 2976 */ "ee.movi.32.a\t \0" + /* 2991 */ "ee.srcmb.s16.qacc\t \0" + /* 3011 */ "ee.vsmulas.s16.qacc\t \0" + /* 3033 */ "ee.vmulas.s16.qacc\t \0" + /* 3054 */ "ee.mov.s16.qacc\t \0" + /* 3072 */ "ee.vmulas.u16.qacc\t \0" + /* 3093 */ "ee.mov.u16.qacc\t \0" + /* 3111 */ "ee.srcmb.s8.qacc\t \0" + /* 3130 */ "ee.vsmulas.s8.qacc\t \0" + /* 3151 */ "ee.vmulas.s8.qacc\t \0" + /* 3171 */ "ee.mov.s8.qacc\t \0" + /* 3188 */ "ee.vmulas.u8.qacc\t \0" + /* 3208 */ "ee.mov.u8.qacc\t \0" + /* 3225 */ "mula.da.hh.lddec\t \0" + /* 3244 */ "mula.dd.hh.lddec\t \0" + /* 3263 */ "mula.da.lh.lddec\t \0" + /* 3282 */ "mula.dd.lh.lddec\t \0" + /* 3301 */ "mula.da.hl.lddec\t \0" + /* 3320 */ "mula.dd.hl.lddec\t \0" + /* 3339 */ "mula.da.ll.lddec\t \0" + /* 3358 */ "mula.dd.ll.lddec\t \0" + /* 3377 */ "mula.da.hh.ldinc\t \0" + /* 3396 */ "mula.dd.hh.ldinc\t \0" + /* 3415 */ "mula.da.lh.ldinc\t \0" + /* 3434 */ "mula.dd.lh.ldinc\t \0" + /* 3453 */ "mula.da.hl.ldinc\t \0" + /* 3472 */ "mula.dd.hl.ldinc\t \0" + /* 3491 */ "mula.da.ll.ldinc\t \0" + /* 3510 */ "mula.dd.ll.ldinc\t \0" + /* 3529 */ "rur.sar_byte\t \0" + /* 3544 */ "wur.sar_byte\t \0" + /* 3559 */ "rur.fft_bit_width\t \0" + /* 3579 */ "wur.fft_bit_width\t \0" + /* 3599 */ "ee.fft.ams.s16.ld.r32.decp\t \0" + /* 3628 */ "ee.fft.vst.r32.decp\t \0" + /* 3650 */ "ee.vldhbc.16.incp\t \0" + /* 3670 */ "ee.vmulas.s16.qacc.ldbc.incp\t \0" + /* 3701 */ "ee.vmulas.u16.qacc.ldbc.incp\t \0" + /* 3732 */ "ee.vmulas.s8.qacc.ldbc.incp\t \0" + /* 3762 */ "ee.vmulas.u8.qacc.ldbc.incp\t \0" + /* 3792 */ "ee.vmin.s32.ld.incp\t \0" + /* 3814 */ "ee.vsubs.s32.ld.incp\t \0" + /* 3837 */ "ee.vadds.s32.ld.incp\t \0" + /* 3860 */ "ee.vmax.s32.ld.incp\t \0" + /* 3882 */ "ee.cmul.s16.ld.incp\t \0" + /* 3904 */ "ee.vmul.s16.ld.incp\t \0" + /* 3926 */ "ee.vmin.s16.ld.incp\t \0" + /* 3948 */ "ee.vsubs.s16.ld.incp\t \0" + /* 3971 */ "ee.vadds.s16.ld.incp\t \0" + /* 3994 */ "ee.fft.ams.s16.ld.incp\t \0" + /* 4019 */ "ee.vmax.s16.ld.incp\t \0" + /* 4041 */ "ee.vmul.u16.ld.incp\t \0" + /* 4063 */ "ee.vmul.s8.ld.incp\t \0" + /* 4084 */ "ee.vmin.s8.ld.incp\t \0" + /* 4105 */ "ee.vsubs.s8.ld.incp\t \0" + /* 4127 */ "ee.vadds.s8.ld.incp\t \0" + /* 4149 */ "ee.vmax.s8.ld.incp\t \0" + /* 4170 */ "ee.vmul.u8.ld.incp\t \0" + /* 4191 */ "ee.vsmulas.s16.qacc.ld.incp\t \0" + /* 4221 */ "ee.vsmulas.s8.qacc.ld.incp\t \0" + /* 4250 */ "ee.vmin.s32.st.incp\t \0" + /* 4272 */ "ee.vsubs.s32.st.incp\t \0" + /* 4295 */ "ee.vadds.s32.st.incp\t \0" + /* 4318 */ "ee.vmax.s32.st.incp\t \0" + /* 4340 */ "ee.fft.r2bf.s16.st.incp\t \0" + /* 4366 */ "ee.cmul.s16.st.incp\t \0" + /* 4388 */ "ee.vmul.s16.st.incp\t \0" + /* 4410 */ "ee.vmin.s16.st.incp\t \0" + /* 4432 */ "ee.vsubs.s16.st.incp\t \0" + /* 4455 */ "ee.vadds.s16.st.incp\t \0" + /* 4478 */ "ee.fft.ams.s16.st.incp\t \0" + /* 4503 */ "ee.vmax.s16.st.incp\t \0" + /* 4525 */ "ee.vmul.u16.st.incp\t \0" + /* 4547 */ "ee.srcq.128.st.incp\t \0" + /* 4569 */ "ee.vmul.s8.st.incp\t \0" + /* 4590 */ "ee.vmin.s8.st.incp\t \0" + /* 4611 */ "ee.vsubs.s8.st.incp\t \0" + /* 4633 */ "ee.vadds.s8.st.incp\t \0" + /* 4655 */ "ee.vmax.s8.st.incp\t \0" + /* 4676 */ "ee.vmul.u8.st.incp\t \0" + /* 4697 */ "ee.vldbc.32.ip\t \0" + /* 4714 */ "ee.ld.qacc_h.h.32.ip\t \0" + /* 4737 */ "ee.st.qacc_h.h.32.ip\t \0" + /* 4760 */ "ee.ld.qacc_l.h.32.ip\t \0" + /* 4783 */ "ee.st.qacc_l.h.32.ip\t \0" + /* 4806 */ "ee.ldf.64.ip\t \0" + /* 4821 */ "ee.stf.64.ip\t \0" + /* 4836 */ "ee.vld.h.64.ip\t \0" + /* 4853 */ "ee.vst.h.64.ip\t \0" + /* 4870 */ "ee.vld.l.64.ip\t \0" + /* 4887 */ "ee.vst.l.64.ip\t \0" + /* 4904 */ "ee.vldbc.16.ip\t \0" + /* 4921 */ "ee.vldbc.8.ip\t \0" + /* 4937 */ "ee.ldqa.s16.128.ip\t \0" + /* 4958 */ "ee.ldqa.u16.128.ip\t \0" + /* 4979 */ "ee.ldqa.s8.128.ip\t \0" + /* 4999 */ "ee.ldqa.u8.128.ip\t \0" + /* 5019 */ "ee.vld.128.ip\t \0" + /* 5035 */ "ee.ldf.128.ip\t \0" + /* 5051 */ "ee.stf.128.ip\t \0" + /* 5067 */ "ee.ld.qacc_h.l.128.ip\t \0" + /* 5091 */ "ee.st.qacc_h.l.128.ip\t \0" + /* 5115 */ "ee.ld.qacc_l.l.128.ip\t \0" + /* 5139 */ "ee.st.qacc_l.l.128.ip\t \0" + /* 5163 */ "ee.vst.128.ip\t \0" + /* 5179 */ "ee.vmulas.s16.qacc.ld.ip\t \0" + /* 5206 */ "ee.vmulas.u16.qacc.ld.ip\t \0" + /* 5233 */ "ee.vmulas.s8.qacc.ld.ip\t \0" + /* 5259 */ "ee.vmulas.u8.qacc.ld.ip\t \0" + /* 5285 */ "ee.src.q.ld.ip\t \0" + /* 5302 */ "ee.vmulas.s16.accx.ld.ip\t \0" + /* 5329 */ "ee.vmulas.u16.accx.ld.ip\t \0" + /* 5356 */ "ee.vmulas.s8.accx.ld.ip\t \0" + /* 5382 */ "ee.vmulas.u8.accx.ld.ip\t \0" + /* 5408 */ "ee.ld.ua_state.ip\t \0" + /* 5428 */ "ee.st.ua_state.ip\t \0" + /* 5448 */ "ee.ld.128.usar.ip\t \0" + /* 5468 */ "ee.ld.accx.ip\t \0" + /* 5484 */ "ee.st.accx.ip\t \0" + /* 5500 */ "ee.fft.ams.s16.ld.incp.uaup\t \0" + /* 5530 */ "ee.vmulas.s16.qacc.ldbc.incp.qup\t \0" + /* 5565 */ "ee.vmulas.u16.qacc.ldbc.incp.qup\t \0" + /* 5600 */ "ee.vmulas.s8.qacc.ldbc.incp.qup\t \0" + /* 5634 */ "ee.vmulas.u8.qacc.ldbc.incp.qup\t \0" + /* 5668 */ "ee.vmulas.s16.qacc.ld.ip.qup\t \0" + /* 5699 */ "ee.vmulas.u16.qacc.ld.ip.qup\t \0" + /* 5730 */ "ee.vmulas.s8.qacc.ld.ip.qup\t \0" + /* 5760 */ "ee.vmulas.u8.qacc.ld.ip.qup\t \0" + /* 5790 */ "ee.vmulas.s16.accx.ld.ip.qup\t \0" + /* 5821 */ "ee.vmulas.u16.accx.ld.ip.qup\t \0" + /* 5852 */ "ee.vmulas.s8.accx.ld.ip.qup\t \0" + /* 5882 */ "ee.vmulas.u8.accx.ld.ip.qup\t \0" + /* 5912 */ "ee.vmulas.s16.qacc.ld.xp.qup\t \0" + /* 5943 */ "ee.vmulas.u16.qacc.ld.xp.qup\t \0" + /* 5974 */ "ee.vmulas.s8.qacc.ld.xp.qup\t \0" + /* 6004 */ "ee.vmulas.u8.qacc.ld.xp.qup\t \0" + /* 6034 */ "ee.vmulas.s16.accx.ld.xp.qup\t \0" + /* 6065 */ "ee.vmulas.u16.accx.ld.xp.qup\t \0" + /* 6096 */ "ee.vmulas.s8.accx.ld.xp.qup\t \0" + /* 6126 */ "ee.vmulas.u8.accx.ld.xp.qup\t \0" + /* 6156 */ "ee.src.q.qup\t \0" + /* 6171 */ "ee.vldbc.32.xp\t \0" + /* 6188 */ "ee.ldf.64.xp\t \0" + /* 6203 */ "ee.stf.64.xp\t \0" + /* 6218 */ "ee.vld.h.64.xp\t \0" + /* 6235 */ "ee.vst.h.64.xp\t \0" + /* 6252 */ "ee.vld.l.64.xp\t \0" + /* 6269 */ "ee.vst.l.64.xp\t \0" + /* 6286 */ "ee.vldbc.16.xp\t \0" + /* 6303 */ "ee.vldbc.8.xp\t \0" + /* 6319 */ "ee.ldqa.s16.128.xp\t \0" + /* 6340 */ "ee.ldqa.u16.128.xp\t \0" + /* 6361 */ "ee.ldqa.s8.128.xp\t \0" + /* 6381 */ "ee.ldqa.u8.128.xp\t \0" + /* 6401 */ "ee.vld.128.xp\t \0" + /* 6417 */ "ee.ldf.128.xp\t \0" + /* 6433 */ "ee.stf.128.xp\t \0" + /* 6449 */ "ee.vst.128.xp\t \0" + /* 6465 */ "ee.fft.cmul.s16.ld.xp\t \0" + /* 6489 */ "ee.vmulas.s16.qacc.ld.xp\t \0" + /* 6516 */ "ee.vmulas.u16.qacc.ld.xp\t \0" + /* 6543 */ "ee.vmulas.s8.qacc.ld.xp\t \0" + /* 6569 */ "ee.vmulas.u8.qacc.ld.xp\t \0" + /* 6595 */ "ee.src.q.ld.xp\t \0" + /* 6612 */ "ee.vmulas.s16.accx.ld.xp\t \0" + /* 6639 */ "ee.vmulas.u16.accx.ld.xp\t \0" + /* 6666 */ "ee.vmulas.s8.accx.ld.xp\t \0" + /* 6692 */ "ee.vmulas.u8.accx.ld.xp\t \0" + /* 6718 */ "ee.ld.128.usar.xp\t \0" + /* 6738 */ "ee.fft.cmul.s16.st.xp\t \0" + /* 6762 */ "ee.movi.32.q\t \0" + /* 6777 */ "ee.src.q\t \0" + /* 6788 */ "ee.zero.q\t \0" + /* 6800 */ "ee.slci.2q\t \0" + /* 6813 */ "ee.srci.2q\t \0" + /* 6826 */ "ee.slcxxp.2q\t \0" + /* 6841 */ "ee.srcxxp.2q\t \0" + /* 6856 */ "ee.andq\t \0" + /* 6866 */ "ee.orq\t \0" + /* 6875 */ "ee.xorq\t \0" + /* 6885 */ "ee.notq\t \0" + /* 6895 */ "mv.qr\t \0" + /* 6903 */ "wur.fsr\t \0" + /* 6913 */ "rur.gpio_out\t \0" + /* 6928 */ "wur.gpio_out\t \0" + /* 6943 */ "ee.bitrev\t \0" + /* 6955 */ "ee.vmulas.s16.accx\t \0" + /* 6976 */ "ee.vmulas.u16.accx\t \0" + /* 6997 */ "ee.vmulas.s8.accx\t \0" + /* 7017 */ "ee.vmulas.u8.accx\t \0" + /* 7037 */ "ee.srs.accx\t \0" + /* 7051 */ "!xtensa_wsr_m0_p, \0" + /* 7070 */ "!xtensa_xsr_m0_p, \0" + /* 7089 */ "!xtensa_wsr_m1_p, \0" + /* 7108 */ "!xtensa_xsr_m1_p, \0" + /* 7127 */ "!atomic_load_sub_32_p, \0" + /* 7151 */ "!xtensa_ee_vldbc_32_p, \0" + /* 7175 */ "!atomic_load_add_32_p, \0" + /* 7199 */ "!atomic_load_and_32_p, \0" + /* 7223 */ "!atomic_load_nand_32_p, \0" + /* 7248 */ "!xtensa_ee_vsl_32_p, \0" + /* 7270 */ "!atomic_load_min_32_p, \0" + /* 7294 */ "!atomic_load_umin_32_p, \0" + /* 7319 */ "!atomic_swap_32_p, \0" + /* 7339 */ "!atomic_cmp_swap_32_p, \0" + /* 7363 */ "!xtensa_ee_vunzip_32_p, \0" + /* 7388 */ "!xtensa_ee_vzip_32_p, \0" + /* 7411 */ "!xtensa_ee_ldxq_32_p, \0" + /* 7434 */ "!xtensa_ee_stxq_32_p, \0" + /* 7457 */ "!atomic_load_or_32_p, \0" + /* 7480 */ "!atomic_load_xor_32_p, \0" + /* 7504 */ "!xtensa_ee_vsr_32_p, \0" + /* 7526 */ "!atomic_load_max_32_p, \0" + /* 7550 */ "!atomic_load_umax_32_p, \0" + /* 7575 */ "!xtensa_ee_vmin_s32_p, \0" + /* 7599 */ "!xtensa_ee_vcmp_eq_s32_p, \0" + /* 7626 */ "!xtensa_ee_vsubs_s32_p, \0" + /* 7651 */ "!xtensa_ee_vadds_s32_p, \0" + /* 7676 */ "!xtensa_ee_vcmp_gt_s32_p, \0" + /* 7703 */ "!xtensa_ee_vcmp_lt_s32_p, \0" + /* 7730 */ "!xtensa_ee_vmax_s32_p, \0" + /* 7754 */ "!xtensa_wsr_m2_p, \0" + /* 7773 */ "!xtensa_xsr_m2_p, \0" + /* 7792 */ "!xtensa_wsr_m3_p, \0" + /* 7811 */ "!xtensa_xsr_m3_p, \0" + /* 7830 */ "!atomic_load_sub_16_p, \0" + /* 7854 */ "!xtensa_ee_vldbc_16_p, \0" + /* 7878 */ "!atomic_load_add_16_p, \0" + /* 7902 */ "!atomic_load_and_16_p, \0" + /* 7926 */ "!atomic_load_nand_16_p, \0" + /* 7951 */ "!atomic_load_min_16_p, \0" + /* 7975 */ "!atomic_load_umin_16_p, \0" + /* 8000 */ "!atomic_swap_16_p, \0" + /* 8020 */ "!atomic_cmp_swap_16_p, \0" + /* 8044 */ "!xtensa_ee_vunzip_16_p, \0" + /* 8069 */ "!xtensa_ee_vzip_16_p, \0" + /* 8092 */ "!atomic_load_or_16_p, \0" + /* 8115 */ "!atomic_load_xor_16_p, \0" + /* 8139 */ "!atomic_load_max_16_p, \0" + /* 8163 */ "!atomic_load_umax_16_p, \0" + /* 8188 */ "!xtensa_ee_fft_r2bf_s16_p, \0" + /* 8216 */ "!xtensa_ee_cmul_s16_p, \0" + /* 8240 */ "!xtensa_ee_vmul_s16_p, \0" + /* 8264 */ "!xtensa_ee_vmin_s16_p, \0" + /* 8288 */ "!xtensa_ee_vcmp_eq_s16_p, \0" + /* 8315 */ "!xtensa_ee_vsubs_s16_p, \0" + /* 8340 */ "!xtensa_ee_vadds_s16_p, \0" + /* 8365 */ "!xtensa_ee_vcmp_gt_s16_p, \0" + /* 8392 */ "!xtensa_ee_vcmp_lt_s16_p, \0" + /* 8419 */ "!xtensa_ee_vprelu_s16_p, \0" + /* 8445 */ "!xtensa_ee_vrelu_s16_p, \0" + /* 8470 */ "!xtensa_ee_vmax_s16_p, \0" + /* 8494 */ "!xtensa_ee_vmul_u16_p, \0" + /* 8518 */ "!atomic_load_sub_8_p, \0" + /* 8541 */ "!xtensa_ee_vldbc_8_p, \0" + /* 8564 */ "!atomic_load_add_8_p, \0" + /* 8587 */ "!atomic_load_and_8_p, \0" + /* 8610 */ "!atomic_load_nand_8_p, \0" + /* 8634 */ "!atomic_load_min_8_p, \0" + /* 8657 */ "!atomic_load_umin_8_p, \0" + /* 8681 */ "!atomic_swap_8_p, \0" + /* 8700 */ "!atomic_cmp_swap_8_p, \0" + /* 8723 */ "!xtensa_ee_vunzip_8_p, \0" + /* 8747 */ "!xtensa_ee_vzip_8_p, \0" + /* 8769 */ "!atomic_load_or_8_p, \0" + /* 8791 */ "!atomic_load_xor_8_p, \0" + /* 8814 */ "!atomic_load_max_8_p, \0" + /* 8837 */ "!atomic_load_umax_8_p, \0" + /* 8861 */ "!xtensa_ee_vmul_s8_p, \0" + /* 8884 */ "!xtensa_ee_vmin_s8_p, \0" + /* 8907 */ "!xtensa_ee_vcmp_eq_s8_p, \0" + /* 8933 */ "!xtensa_ee_vsubs_s8_p, \0" + /* 8957 */ "!xtensa_ee_vadds_s8_p, \0" + /* 8981 */ "!xtensa_ee_vcmp_gt_s8_p, \0" + /* 9007 */ "!xtensa_ee_vcmp_lt_s8_p, \0" + /* 9033 */ "!xtensa_ee_vprelu_s8_p, \0" + /* 9058 */ "!xtensa_ee_vrelu_s8_p, \0" + /* 9082 */ "!xtensa_ee_vmax_s8_p, \0" + /* 9105 */ "!xtensa_ee_vmul_u8_p, \0" + /* 9128 */ "!xtensa_ee_movi_32_a_p, \0" + /* 9153 */ "!xtensa_ee_srcmb_s16_qacc_p, \0" + /* 9183 */ "!xtensa_ee_vsmulas_s16_qacc_p, \0" + /* 9215 */ "!xtensa_ee_vmulas_s16_qacc_p, \0" + /* 9246 */ "!xtensa_ee_mov_s16_qacc_p, \0" + /* 9274 */ "!xtensa_ee_vmulas_u16_qacc_p, \0" + /* 9305 */ "!xtensa_ee_mov_u16_qacc_p, \0" + /* 9333 */ "!xtensa_ee_srcmb_s8_qacc_p, \0" + /* 9362 */ "!xtensa_ee_vsmulas_s8_qacc_p, \0" + /* 9393 */ "!xtensa_ee_vmulas_s8_qacc_p, \0" + /* 9423 */ "!xtensa_ee_mov_s8_qacc_p, \0" + /* 9450 */ "!xtensa_ee_vmulas_u8_qacc_p, \0" + /* 9480 */ "!xtensa_ee_mov_u8_qacc_p, \0" + /* 9507 */ "!xtensa_lddec_p, \0" + /* 9525 */ "!xtensa_mula_da_hh_lddec_p, \0" + /* 9554 */ "!xtensa_mula_dd_hh_lddec_p, \0" + /* 9583 */ "!xtensa_mula_da_lh_lddec_p, \0" + /* 9612 */ "!xtensa_mula_dd_lh_lddec_p, \0" + /* 9641 */ "!xtensa_mula_da_hl_lddec_p, \0" + /* 9670 */ "!xtensa_mula_dd_hl_lddec_p, \0" + /* 9699 */ "!xtensa_mula_da_ll_lddec_p, \0" + /* 9728 */ "!xtensa_mula_dd_ll_lddec_p, \0" + /* 9757 */ "!xtensa_ldinc_p, \0" + /* 9775 */ "!xtensa_mula_da_hh_ldinc_p, \0" + /* 9804 */ "!xtensa_mula_dd_hh_ldinc_p, \0" + /* 9833 */ "!xtensa_mula_da_lh_ldinc_p, \0" + /* 9862 */ "!xtensa_mula_dd_lh_ldinc_p, \0" + /* 9891 */ "!xtensa_mula_da_hl_ldinc_p, \0" + /* 9920 */ "!xtensa_mula_dd_hl_ldinc_p, \0" + /* 9949 */ "!xtensa_mula_da_ll_ldinc_p, \0" + /* 9978 */ "!xtensa_mula_dd_ll_ldinc_p, \0" + /* 10007 */ "!xtensa_wsr_acchi_p, \0" + /* 10029 */ "!xtensa_xsr_acchi_p, \0" + /* 10051 */ "!xtensa_wsr_acclo_p, \0" + /* 10073 */ "!xtensa_xsr_acclo_p, \0" + /* 10095 */ "!xtensa_ee_fft_ams_s16_ld_r32_decp_p, \0" + /* 10134 */ "!xtensa_ee_fft_vst_r32_decp_p, \0" + /* 10166 */ "!xtensa_ee_vldhbc_16_incp_p, \0" + /* 10196 */ "!xtensa_ee_vmulas_s16_qacc_ldbc_incp_p, \0" + /* 10237 */ "!xtensa_ee_vmulas_u16_qacc_ldbc_incp_p, \0" + /* 10278 */ "!xtensa_ee_vmulas_s8_qacc_ldbc_incp_p, \0" + /* 10318 */ "!xtensa_ee_vmulas_u8_qacc_ldbc_incp_p, \0" + /* 10358 */ "!xtensa_ee_vmin_s32_ld_incp_p, \0" + /* 10390 */ "!xtensa_ee_vsubs_s32_ld_incp_p, \0" + /* 10423 */ "!xtensa_ee_vadds_s32_ld_incp_p, \0" + /* 10456 */ "!xtensa_ee_vmax_s32_ld_incp_p, \0" + /* 10488 */ "!xtensa_ee_cmul_s16_ld_incp_p, \0" + /* 10520 */ "!xtensa_ee_vmul_s16_ld_incp_p, \0" + /* 10552 */ "!xtensa_ee_vmin_s16_ld_incp_p, \0" + /* 10584 */ "!xtensa_ee_vsubs_s16_ld_incp_p, \0" + /* 10617 */ "!xtensa_ee_vadds_s16_ld_incp_p, \0" + /* 10650 */ "!xtensa_ee_fft_ams_s16_ld_incp_p, \0" + /* 10685 */ "!xtensa_ee_vmax_s16_ld_incp_p, \0" + /* 10717 */ "!xtensa_ee_vmul_u16_ld_incp_p, \0" + /* 10749 */ "!xtensa_ee_vmul_s8_ld_incp_p, \0" + /* 10780 */ "!xtensa_ee_vmin_s8_ld_incp_p, \0" + /* 10811 */ "!xtensa_ee_vsubs_s8_ld_incp_p, \0" + /* 10843 */ "!xtensa_ee_vadds_s8_ld_incp_p, \0" + /* 10875 */ "!xtensa_ee_vmax_s8_ld_incp_p, \0" + /* 10906 */ "!xtensa_ee_vmul_u8_ld_incp_p, \0" + /* 10937 */ "!xtensa_ee_vsmulas_s16_qacc_ld_incp_p, \0" + /* 10977 */ "!xtensa_ee_vsmulas_s8_qacc_ld_incp_p, \0" + /* 11016 */ "!xtensa_ee_vmin_s32_st_incp_p, \0" + /* 11048 */ "!xtensa_ee_vsubs_s32_st_incp_p, \0" + /* 11081 */ "!xtensa_ee_vadds_s32_st_incp_p, \0" + /* 11114 */ "!xtensa_ee_vmax_s32_st_incp_p, \0" + /* 11146 */ "!xtensa_ee_fft_r2bf_s16_st_incp_p, \0" + /* 11182 */ "!xtensa_ee_cmul_s16_st_incp_p, \0" + /* 11214 */ "!xtensa_ee_vmul_s16_st_incp_p, \0" + /* 11246 */ "!xtensa_ee_vmin_s16_st_incp_p, \0" + /* 11278 */ "!xtensa_ee_vsubs_s16_st_incp_p, \0" + /* 11311 */ "!xtensa_ee_vadds_s16_st_incp_p, \0" + /* 11344 */ "!xtensa_ee_fft_ams_s16_st_incp_p, \0" + /* 11379 */ "!xtensa_ee_vmax_s16_st_incp_p, \0" + /* 11411 */ "!xtensa_ee_vmul_u16_st_incp_p, \0" + /* 11443 */ "!xtensa_ee_srcq_128_st_incp_p, \0" + /* 11475 */ "!xtensa_ee_vmul_s8_st_incp_p, \0" + /* 11506 */ "!xtensa_ee_vmin_s8_st_incp_p, \0" + /* 11537 */ "!xtensa_ee_vsubs_s8_st_incp_p, \0" + /* 11569 */ "!xtensa_ee_vadds_s8_st_incp_p, \0" + /* 11601 */ "!xtensa_ee_vmax_s8_st_incp_p, \0" + /* 11632 */ "!xtensa_ee_vmul_u8_st_incp_p, \0" + /* 11663 */ "!xtensa_ee_vldbc_32_ip_p, \0" + /* 11690 */ "!xtensa_ee_ld_qacc_h_h_32_ip_p, \0" + /* 11723 */ "!xtensa_ee_st_qacc_h_h_32_ip_p, \0" + /* 11756 */ "!xtensa_ee_ld_qacc_l_h_32_ip_p, \0" + /* 11789 */ "!xtensa_ee_st_qacc_l_h_32_ip_p, \0" + /* 11822 */ "!xtensa_ee_ldf_64_ip_p, \0" + /* 11847 */ "!xtensa_ee_stf_64_ip_p, \0" + /* 11872 */ "!xtensa_ee_vld_h_64_ip_p, \0" + /* 11899 */ "!xtensa_ee_vst_h_64_ip_p, \0" + /* 11926 */ "!xtensa_ee_vld_l_64_ip_p, \0" + /* 11953 */ "!xtensa_ee_vst_l_64_ip_p, \0" + /* 11980 */ "!xtensa_ee_vldbc_16_ip_p, \0" + /* 12007 */ "!xtensa_ee_ldqa_s16_128_ip_p, \0" + /* 12038 */ "!xtensa_ee_ldqa_u16_128_ip_p, \0" + /* 12069 */ "!xtensa_ee_ldqa_s8_128_ip_p, \0" + /* 12099 */ "!xtensa_ee_ldqa_u8_128_ip_p, \0" + /* 12129 */ "!xtensa_ee_vld_128_ip_p, \0" + /* 12155 */ "!xtensa_ee_ldf_128_ip_p, \0" + /* 12181 */ "!xtensa_ee_stf_128_ip_p, \0" + /* 12207 */ "!xtensa_ee_ld_qacc_h_l_128_ip_p, \0" + /* 12241 */ "!xtensa_ee_st_qacc_h_l_128_ip_p, \0" + /* 12275 */ "!xtensa_ee_ld_qacc_l_l_128_ip_p, \0" + /* 12309 */ "!xtensa_ee_st_qacc_l_l_128_ip_p, \0" + /* 12343 */ "!xtensa_ee_vst_128_ip_p, \0" + /* 12369 */ "!xtensa_ee_vldbc_8_ip_p, \0" + /* 12395 */ "!xtensa_ee_vmulas_s16_qacc_ld_ip_p, \0" + /* 12432 */ "!xtensa_ee_vmulas_u16_qacc_ld_ip_p, \0" + /* 12469 */ "!xtensa_ee_vmulas_s8_qacc_ld_ip_p, \0" + /* 12505 */ "!xtensa_ee_vmulas_u8_qacc_ld_ip_p, \0" + /* 12541 */ "!xtensa_ee_src_q_ld_ip_p, \0" + /* 12568 */ "!xtensa_ee_vmulas_s16_accx_ld_ip_p, \0" + /* 12605 */ "!xtensa_ee_vmulas_u16_accx_ld_ip_p, \0" + /* 12642 */ "!xtensa_ee_vmulas_s8_accx_ld_ip_p, \0" + /* 12678 */ "!xtensa_ee_vmulas_u8_accx_ld_ip_p, \0" + /* 12714 */ "!xtensa_ee_ld_ua_state_ip_p, \0" + /* 12744 */ "!xtensa_ee_st_ua_state_ip_p, \0" + /* 12774 */ "!xtensa_ee_ld_128_usar_ip_p, \0" + /* 12804 */ "!xtensa_ee_ld_accx_ip_p, \0" + /* 12830 */ "!xtensa_ee_st_accx_ip_p, \0" + /* 12856 */ "!xtensa_ee_fft_ams_s16_ld_incp_uaup_p, \0" + /* 12896 */ "!xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup_p, \0" + /* 12941 */ "!xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup_p, \0" + /* 12986 */ "!xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup_p, \0" + /* 13030 */ "!xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup_p, \0" + /* 13074 */ "!xtensa_ee_vmulas_s16_qacc_ld_ip_qup_p, \0" + /* 13115 */ "!xtensa_ee_vmulas_u16_qacc_ld_ip_qup_p, \0" + /* 13156 */ "!xtensa_ee_vmulas_s8_qacc_ld_ip_qup_p, \0" + /* 13196 */ "!xtensa_ee_vmulas_u8_qacc_ld_ip_qup_p, \0" + /* 13236 */ "!xtensa_ee_vmulas_s16_accx_ld_ip_qup_p, \0" + /* 13277 */ "!xtensa_ee_vmulas_u16_accx_ld_ip_qup_p, \0" + /* 13318 */ "!xtensa_ee_vmulas_s8_accx_ld_ip_qup_p, \0" + /* 13358 */ "!xtensa_ee_vmulas_u8_accx_ld_ip_qup_p, \0" + /* 13398 */ "!xtensa_ee_vmulas_s16_qacc_ld_xp_qup_p, \0" + /* 13439 */ "!xtensa_ee_vmulas_u16_qacc_ld_xp_qup_p, \0" + /* 13480 */ "!xtensa_ee_vmulas_s8_qacc_ld_xp_qup_p, \0" + /* 13520 */ "!xtensa_ee_vmulas_u8_qacc_ld_xp_qup_p, \0" + /* 13560 */ "!xtensa_ee_vmulas_s16_accx_ld_xp_qup_p, \0" + /* 13601 */ "!xtensa_ee_vmulas_u16_accx_ld_xp_qup_p, \0" + /* 13642 */ "!xtensa_ee_vmulas_s8_accx_ld_xp_qup_p, \0" + /* 13682 */ "!xtensa_ee_vmulas_u8_accx_ld_xp_qup_p, \0" + /* 13722 */ "!xtensa_ee_src_q_qup_p, \0" + /* 13747 */ "!xtensa_ee_vldbc_32_xp_p, \0" + /* 13774 */ "!xtensa_ee_ldf_64_xp_p, \0" + /* 13799 */ "!xtensa_ee_stf_64_xp_p, \0" + /* 13824 */ "!xtensa_ee_vld_h_64_xp_p, \0" + /* 13851 */ "!xtensa_ee_vst_h_64_xp_p, \0" + /* 13878 */ "!xtensa_ee_vld_l_64_xp_p, \0" + /* 13905 */ "!xtensa_ee_vst_l_64_xp_p, \0" + /* 13932 */ "!xtensa_ee_vldbc_16_xp_p, \0" + /* 13959 */ "!xtensa_ee_ldqa_s16_128_xp_p, \0" + /* 13990 */ "!xtensa_ee_ldqa_u16_128_xp_p, \0" + /* 14021 */ "!xtensa_ee_ldqa_s8_128_xp_p, \0" + /* 14051 */ "!xtensa_ee_ldqa_u8_128_xp_p, \0" + /* 14081 */ "!xtensa_ee_vld_128_xp_p, \0" + /* 14107 */ "!xtensa_ee_ldf_128_xp_p, \0" + /* 14133 */ "!xtensa_ee_stf_128_xp_p, \0" + /* 14159 */ "!xtensa_ee_vst_128_xp_p, \0" + /* 14185 */ "!xtensa_ee_vldbc_8_xp_p, \0" + /* 14211 */ "!xtensa_ee_fft_cmul_s16_ld_xp_p, \0" + /* 14245 */ "!xtensa_ee_vmulas_s16_qacc_ld_xp_p, \0" + /* 14282 */ "!xtensa_ee_vmulas_u16_qacc_ld_xp_p, \0" + /* 14319 */ "!xtensa_ee_vmulas_s8_qacc_ld_xp_p, \0" + /* 14355 */ "!xtensa_ee_vmulas_u8_qacc_ld_xp_p, \0" + /* 14391 */ "!xtensa_ee_src_q_ld_xp_p, \0" + /* 14418 */ "!xtensa_ee_vmulas_s16_accx_ld_xp_p, \0" + /* 14455 */ "!xtensa_ee_vmulas_u16_accx_ld_xp_p, \0" + /* 14492 */ "!xtensa_ee_vmulas_s8_accx_ld_xp_p, \0" + /* 14528 */ "!xtensa_ee_vmulas_u8_accx_ld_xp_p, \0" + /* 14564 */ "!xtensa_ee_ld_128_usar_xp_p, \0" + /* 14594 */ "!xtensa_ee_fft_cmul_s16_st_xp_p, \0" + /* 14628 */ "!xtensa_ee_slci_2q_p, \0" + /* 14651 */ "!xtensa_ee_srci_2q_p, \0" + /* 14674 */ "!xtensa_ee_slcxxp_2q_p, \0" + /* 14699 */ "!xtensa_ee_srcxxp_2q_p, \0" + /* 14724 */ "!xtensa_ee_movi_32_q_p, \0" + /* 14749 */ "!xtensa_ee_src_q_p, \0" + /* 14770 */ "!xtensa_ee_zero_q_p, \0" + /* 14792 */ "!xtensa_ee_andq_p, \0" + /* 14812 */ "!xtensa_ee_orq_p, \0" + /* 14831 */ "!xtensa_ee_xorq_p, \0" + /* 14851 */ "!xtensa_ee_notq_p, \0" + /* 14871 */ "!xtensa_mv_qr_p, \0" + /* 14889 */ "!br_jt_p, \0" + /* 14900 */ "!xtensa_ee_bitrev_p, \0" + /* 14922 */ "!xtensa_ee_vmulas_s16_accx_p, \0" + /* 14953 */ "!xtensa_ee_vmulas_u16_accx_p, \0" + /* 14984 */ "!xtensa_ee_vmulas_s8_accx_p, \0" + /* 15014 */ "!xtensa_ee_vmulas_u8_accx_p, \0" + /* 15044 */ "!xtensa_ee_srs_accx_p, \0" + /* 15068 */ "ae_movad16.0 \0" + /* 15082 */ "ae_nsaz16.0 \0" + /* 15095 */ "ae_mulaf16ss.00 \0" + /* 15112 */ "ae_mulf16ss.00 \0" + /* 15128 */ "ae_mulsf16ss.00 \0" + /* 15145 */ "ae_mulaafd16ss.11_00 \0" + /* 15167 */ "ae_mulzaafd16ss.11_00 \0" + /* 15190 */ "ae_mulssfd16ss.11_00 \0" + /* 15212 */ "ae_mulzssfd16ss.11_00 \0" + /* 15235 */ "ae_sext32x2d16.10 \0" + /* 15254 */ "ae_cvt32x2f16.10 \0" + /* 15272 */ "ae_mulaf16ss.10 \0" + /* 15289 */ "ae_mulf16ss.10 \0" + /* 15305 */ "ae_mulsf16ss.10 \0" + /* 15322 */ "ae_mulaf16ss.20 \0" + /* 15339 */ "ae_mulf16ss.20 \0" + /* 15355 */ "ae_mulsf16ss.20 \0" + /* 15372 */ "ae_mulaf16ss.30 \0" + /* 15389 */ "ae_mulf16ss.30 \0" + /* 15405 */ "ae_mulsf16ss.30 \0" + /* 15422 */ "rur.ae_cend0 \0" + /* 15436 */ "wur.ae_cend0 \0" + /* 15450 */ "ae_mula32x16.h0 \0" + /* 15467 */ "ae_mulaf32x16.h0 \0" + /* 15485 */ "ae_mulf32x16.h0 \0" + /* 15502 */ "ae_mulsf32x16.h0 \0" + /* 15520 */ "ae_mul32x16.h0 \0" + /* 15536 */ "ae_muls32x16.h0 \0" + /* 15553 */ "ae_mulaad32x16.h1.l0 \0" + /* 15575 */ "ae_mulzaad32x16.h1.l0 \0" + /* 15598 */ "ae_mulsad32x16.h1.l0 \0" + /* 15620 */ "ae_mulzsad32x16.h1.l0 \0" + /* 15643 */ "ae_mulaafd32x16.h1.l0 \0" + /* 15666 */ "ae_mulzaafd32x16.h1.l0 \0" + /* 15690 */ "ae_mulsafd32x16.h1.l0 \0" + /* 15713 */ "ae_mulzsafd32x16.h1.l0 \0" + /* 15737 */ "ae_mulasfd32x16.h1.l0 \0" + /* 15760 */ "ae_mulzasfd32x16.h1.l0 \0" + /* 15784 */ "ae_mulssfd32x16.h1.l0 \0" + /* 15807 */ "ae_mulzssfd32x16.h1.l0 \0" + /* 15831 */ "ae_mulasd32x16.h1.l0 \0" + /* 15853 */ "ae_mulzasd32x16.h1.l0 \0" + /* 15876 */ "ae_mulssd32x16.h1.l0 \0" + /* 15898 */ "ae_mulzssd32x16.h1.l0 \0" + /* 15921 */ "ae_mula32x16.l0 \0" + /* 15938 */ "ae_mulaf32x16.l0 \0" + /* 15956 */ "ae_mulf32x16.l0 \0" + /* 15973 */ "ae_mulsf32x16.l0 \0" + /* 15991 */ "ae_mul32x16.l0 \0" + /* 16007 */ "ae_muls32x16.l0 \0" + /* 16024 */ "rur.ae_cbegin0 \0" + /* 16040 */ "wur.ae_cbegin0 \0" + /* 16056 */ "ae_movad16.1 \0" + /* 16070 */ "ae_mulaf16ss.11 \0" + /* 16087 */ "ae_mulf16ss.11 \0" + /* 16103 */ "ae_mulsf16ss.11 \0" + /* 16120 */ "ae_mulaf16ss.21 \0" + /* 16137 */ "ae_mulf16ss.21 \0" + /* 16153 */ "ae_mulsf16ss.21 \0" + /* 16170 */ "ae_mulaf16ss.31 \0" + /* 16187 */ "ae_mulf16ss.31 \0" + /* 16203 */ "ae_mulsf16ss.31 \0" + /* 16220 */ "ae_mula32x16.h1 \0" + /* 16237 */ "ae_mulaf32x16.h1 \0" + /* 16255 */ "ae_mulf32x16.h1 \0" + /* 16272 */ "ae_mulsf32x16.h1 \0" + /* 16290 */ "ae_mul32x16.h1 \0" + /* 16306 */ "ae_muls32x16.h1 \0" + /* 16323 */ "ae_mulaad32x16.h0.l1 \0" + /* 16345 */ "ae_mulzaad32x16.h0.l1 \0" + /* 16368 */ "ae_mulaafd32x16.h0.l1 \0" + /* 16391 */ "ae_mulzaafd32x16.h0.l1 \0" + /* 16415 */ "ae_mula32x16.l1 \0" + /* 16432 */ "ae_mulaf32x16.l1 \0" + /* 16450 */ "ae_mulf32x16.l1 \0" + /* 16467 */ "ae_mulsf32x16.l1 \0" + /* 16485 */ "ae_mul32x16.l1 \0" + /* 16501 */ "ae_muls32x16.l1 \0" + /* 16518 */ "ae_movad16.2 \0" + /* 16532 */ "ae_mulaafd16ss.13_02 \0" + /* 16554 */ "ae_mulzaafd16ss.13_02 \0" + /* 16577 */ "ae_mulssfd16ss.13_02 \0" + /* 16599 */ "ae_mulzssfd16ss.13_02 \0" + /* 16622 */ "ae_mulaf16ss.22 \0" + /* 16639 */ "ae_mulf16ss.22 \0" + /* 16655 */ "ae_mulsf16ss.22 \0" + /* 16672 */ "ae_mulaafd16ss.33_22 \0" + /* 16694 */ "ae_mulzaafd16ss.33_22 \0" + /* 16717 */ "ae_mulssfd16ss.33_22 \0" + /* 16739 */ "ae_mulzssfd16ss.33_22 \0" + /* 16762 */ "ae_sext32x2d16.32 \0" + /* 16781 */ "ae_cvt32x2f16.32 \0" + /* 16799 */ "ae_mulaf16ss.32 \0" + /* 16816 */ "ae_mulf16ss.32 \0" + /* 16832 */ "ae_mulsf16ss.32 \0" + /* 16849 */ "ae_sra64_32 \0" + /* 16862 */ "ae_cvt64a32 \0" + /* 16875 */ "ae_cvt48a32 \0" + /* 16888 */ "ae_slaa32 \0" + /* 16899 */ "ae_sraa32 \0" + /* 16910 */ "ae_addbrba32 \0" + /* 16924 */ "ae_movda32 \0" + /* 16936 */ "ae_sha32 \0" + /* 16946 */ "ae_srla32 \0" + /* 16957 */ "ae_sub32 \0" + /* 16967 */ "ae_addsub32 \0" + /* 16980 */ "ae_add32 \0" + /* 16990 */ "ae_subadd32 \0" + /* 17003 */ "ae_le32 \0" + /* 17012 */ "ae_neg32 \0" + /* 17022 */ "ae_slai32 \0" + /* 17033 */ "ae_srai32 \0" + /* 17044 */ "ae_srli32 \0" + /* 17055 */ "ae_min32 \0" + /* 17065 */ "ae_eq32 \0" + /* 17074 */ "ae_pksr32 \0" + /* 17085 */ "ae_slas32 \0" + /* 17096 */ "ae_sras32 \0" + /* 17107 */ "ae_abs32 \0" + /* 17117 */ "ae_srls32 \0" + /* 17128 */ "ae_lt32 \0" + /* 17137 */ "ae_sext32 \0" + /* 17148 */ "ae_max32 \0" + /* 17158 */ "!movba2 \0" + /* 17167 */ "ae_mula32x16.h2 \0" + /* 17184 */ "ae_mulaf32x16.h2 \0" + /* 17202 */ "ae_mulf32x16.h2 \0" + /* 17219 */ "ae_mulsf32x16.h2 \0" + /* 17237 */ "ae_mul32x16.h2 \0" + /* 17253 */ "ae_muls32x16.h2 \0" + /* 17270 */ "ae_mulaad32x16.h3.l2 \0" + /* 17292 */ "ae_mulzaad32x16.h3.l2 \0" + /* 17315 */ "ae_mulsad32x16.h3.l2 \0" + /* 17337 */ "ae_mulzsad32x16.h3.l2 \0" + /* 17360 */ "ae_mulaafd32x16.h3.l2 \0" + /* 17383 */ "ae_mulzaafd32x16.h3.l2 \0" + /* 17407 */ "ae_mulsafd32x16.h3.l2 \0" + /* 17430 */ "ae_mulzsafd32x16.h3.l2 \0" + /* 17454 */ "ae_mulasfd32x16.h3.l2 \0" + /* 17477 */ "ae_mulzasfd32x16.h3.l2 \0" + /* 17501 */ "ae_mulssfd32x16.h3.l2 \0" + /* 17524 */ "ae_mulzssfd32x16.h3.l2 \0" + /* 17548 */ "ae_mulasd32x16.h3.l2 \0" + /* 17570 */ "ae_mulzasd32x16.h3.l2 \0" + /* 17593 */ "ae_mulssd32x16.h3.l2 \0" + /* 17615 */ "ae_mulzssd32x16.h3.l2 \0" + /* 17638 */ "ae_mula32x16.l2 \0" + /* 17655 */ "ae_mulaf32x16.l2 \0" + /* 17673 */ "ae_mulf32x16.l2 \0" + /* 17690 */ "ae_mulsf32x16.l2 \0" + /* 17708 */ "ae_mul32x16.l2 \0" + /* 17724 */ "ae_muls32x16.l2 \0" + /* 17741 */ "!extui_br2 \0" + /* 17753 */ "ae_mulaf16ss.00_s2 \0" + /* 17773 */ "ae_mulf16ss.00_s2 \0" + /* 17792 */ "ae_mulsf16ss.00_s2 \0" + /* 17812 */ "ae_mulaafd16ss.11_00_s2 \0" + /* 17837 */ "ae_mulzaafd16ss.11_00_s2 \0" + /* 17863 */ "ae_mulssfd16ss.11_00_s2 \0" + /* 17888 */ "ae_mulzssfd16ss.11_00_s2 \0" + /* 17914 */ "ae_mula32x16.h0_s2 \0" + /* 17934 */ "ae_mulaf32x16.h0_s2 \0" + /* 17955 */ "ae_mulf32x16.h0_s2 \0" + /* 17975 */ "ae_mulsf32x16.h0_s2 \0" + /* 17996 */ "ae_mul32x16.h0_s2 \0" + /* 18015 */ "ae_muls32x16.h0_s2 \0" + /* 18035 */ "ae_mulaad32x16.h1.l0_s2 \0" + /* 18060 */ "ae_mulzaad32x16.h1.l0_s2 \0" + /* 18086 */ "ae_mulsad32x16.h1.l0_s2 \0" + /* 18111 */ "ae_mulzsad32x16.h1.l0_s2 \0" + /* 18137 */ "ae_mulaafd32x16.h1.l0_s2 \0" + /* 18163 */ "ae_mulzaafd32x16.h1.l0_s2 \0" + /* 18190 */ "ae_mulsafd32x16.h1.l0_s2 \0" + /* 18216 */ "ae_mulzsafd32x16.h1.l0_s2 \0" + /* 18243 */ "ae_mulasfd32x16.h1.l0_s2 \0" + /* 18269 */ "ae_mulzasfd32x16.h1.l0_s2 \0" + /* 18296 */ "ae_mulssfd32x16.h1.l0_s2 \0" + /* 18322 */ "ae_mulzssfd32x16.h1.l0_s2 \0" + /* 18349 */ "ae_mulasd32x16.h1.l0_s2 \0" + /* 18374 */ "ae_mulzasd32x16.h1.l0_s2 \0" + /* 18400 */ "ae_mulssd32x16.h1.l0_s2 \0" + /* 18425 */ "ae_mulzssd32x16.h1.l0_s2 \0" + /* 18451 */ "ae_mula32x16.l0_s2 \0" + /* 18471 */ "ae_mulaf32x16.l0_s2 \0" + /* 18492 */ "ae_mulf32x16.l0_s2 \0" + /* 18512 */ "ae_mulsf32x16.l0_s2 \0" + /* 18533 */ "ae_mul32x16.l0_s2 \0" + /* 18552 */ "ae_muls32x16.l0_s2 \0" + /* 18572 */ "ae_mula32x16.h1_s2 \0" + /* 18592 */ "ae_mulaf32x16.h1_s2 \0" + /* 18613 */ "ae_mulf32x16.h1_s2 \0" + /* 18633 */ "ae_mulsf32x16.h1_s2 \0" + /* 18654 */ "ae_mul32x16.h1_s2 \0" + /* 18673 */ "ae_muls32x16.h1_s2 \0" + /* 18693 */ "ae_mulaad32x16.h0.l1_s2 \0" + /* 18718 */ "ae_mulzaad32x16.h0.l1_s2 \0" + /* 18744 */ "ae_mulaafd32x16.h0.l1_s2 \0" + /* 18770 */ "ae_mulzaafd32x16.h0.l1_s2 \0" + /* 18797 */ "ae_mula32x16.l1_s2 \0" + /* 18817 */ "ae_mulaf32x16.l1_s2 \0" + /* 18838 */ "ae_mulf32x16.l1_s2 \0" + /* 18858 */ "ae_mulsf32x16.l1_s2 \0" + /* 18879 */ "ae_mul32x16.l1_s2 \0" + /* 18898 */ "ae_muls32x16.l1_s2 \0" + /* 18918 */ "ae_mulaafd16ss.13_02_s2 \0" + /* 18943 */ "ae_mulzaafd16ss.13_02_s2 \0" + /* 18969 */ "ae_mulssfd16ss.13_02_s2 \0" + /* 18994 */ "ae_mulzssfd16ss.13_02_s2 \0" + /* 19020 */ "ae_mulaafd16ss.33_22_s2 \0" + /* 19045 */ "ae_mulzaafd16ss.33_22_s2 \0" + /* 19071 */ "ae_mulssfd16ss.33_22_s2 \0" + /* 19096 */ "ae_mulzssfd16ss.33_22_s2 \0" + /* 19122 */ "ae_mula32x16.h2_s2 \0" + /* 19142 */ "ae_mulaf32x16.h2_s2 \0" + /* 19163 */ "ae_mulf32x16.h2_s2 \0" + /* 19183 */ "ae_mulsf32x16.h2_s2 \0" + /* 19204 */ "ae_mul32x16.h2_s2 \0" + /* 19223 */ "ae_muls32x16.h2_s2 \0" + /* 19243 */ "ae_mulaad32x16.h3.l2_s2 \0" + /* 19268 */ "ae_mulzaad32x16.h3.l2_s2 \0" + /* 19294 */ "ae_mulsad32x16.h3.l2_s2 \0" + /* 19319 */ "ae_mulzsad32x16.h3.l2_s2 \0" + /* 19345 */ "ae_mulaafd32x16.h3.l2_s2 \0" + /* 19371 */ "ae_mulzaafd32x16.h3.l2_s2 \0" + /* 19398 */ "ae_mulsafd32x16.h3.l2_s2 \0" + /* 19424 */ "ae_mulzsafd32x16.h3.l2_s2 \0" + /* 19451 */ "ae_mulasfd32x16.h3.l2_s2 \0" + /* 19477 */ "ae_mulzasfd32x16.h3.l2_s2 \0" + /* 19504 */ "ae_mulssfd32x16.h3.l2_s2 \0" + /* 19530 */ "ae_mulzssfd32x16.h3.l2_s2 \0" + /* 19557 */ "ae_mulasd32x16.h3.l2_s2 \0" + /* 19582 */ "ae_mulzasd32x16.h3.l2_s2 \0" + /* 19608 */ "ae_mulssd32x16.h3.l2_s2 \0" + /* 19633 */ "ae_mulzssd32x16.h3.l2_s2 \0" + /* 19659 */ "ae_mula32x16.l2_s2 \0" + /* 19679 */ "ae_mulaf32x16.l2_s2 \0" + /* 19700 */ "ae_mulf32x16.l2_s2 \0" + /* 19720 */ "ae_mulsf32x16.l2_s2 \0" + /* 19741 */ "ae_mul32x16.l2_s2 \0" + /* 19760 */ "ae_muls32x16.l2_s2 \0" + /* 19780 */ "ae_mulap24x2_s2 \0" + /* 19797 */ "ae_mulp24x2_s2 \0" + /* 19813 */ "ae_mulsp24x2_s2 \0" + /* 19830 */ "ae_mula32x16.h3_s2 \0" + /* 19850 */ "ae_mulaf32x16.h3_s2 \0" + /* 19871 */ "ae_mulf32x16.h3_s2 \0" + /* 19891 */ "ae_mulsf32x16.h3_s2 \0" + /* 19912 */ "ae_mul32x16.h3_s2 \0" + /* 19931 */ "ae_muls32x16.h3_s2 \0" + /* 19951 */ "ae_mulaad32x16.h2.l3_s2 \0" + /* 19976 */ "ae_mulzaad32x16.h2.l3_s2 \0" + /* 20002 */ "ae_mulaafd32x16.h2.l3_s2 \0" + /* 20028 */ "ae_mulzaafd32x16.h2.l3_s2 \0" + /* 20055 */ "ae_mula32x16.l3_s2 \0" + /* 20075 */ "ae_mulaf32x16.l3_s2 \0" + /* 20096 */ "ae_mulf32x16.l3_s2 \0" + /* 20116 */ "ae_mulsf32x16.l3_s2 \0" + /* 20137 */ "ae_mul32x16.l3_s2 \0" + /* 20156 */ "ae_muls32x16.l3_s2 \0" + /* 20176 */ "ae_mulafp24x2ra_s2 \0" + /* 20196 */ "ae_mulfp24x2ra_s2 \0" + /* 20215 */ "ae_mulsfp24x2ra_s2 \0" + /* 20235 */ "ae_mulafq32sp24s.h_s2 \0" + /* 20258 */ "ae_mulfq32sp24s.h_s2 \0" + /* 20280 */ "ae_mularfq32sp24s.h_s2 \0" + /* 20304 */ "ae_mulrfq32sp24s.h_s2 \0" + /* 20327 */ "ae_mulsrfq32sp24s.h_s2 \0" + /* 20351 */ "ae_mulsfq32sp24s.h_s2 \0" + /* 20374 */ "ae_mulafp32x16x2ras.h_s2 \0" + /* 20400 */ "ae_mulfp32x16x2ras.h_s2 \0" + /* 20425 */ "ae_mulsfp32x16x2ras.h_s2 \0" + /* 20451 */ "ae_mulafp32x16x2rs.h_s2 \0" + /* 20476 */ "ae_mulfp32x16x2rs.h_s2 \0" + /* 20500 */ "ae_mulsfp32x16x2rs.h_s2 \0" + /* 20525 */ "ae_mulas32f48p16s.hh_s2 \0" + /* 20550 */ "ae_muls32f48p16s.hh_s2 \0" + /* 20574 */ "ae_mulss32f48p16s.hh_s2 \0" + /* 20599 */ "ae_mulaad24.hl.lh_s2 \0" + /* 20621 */ "ae_mulzaad24.hl.lh_s2 \0" + /* 20644 */ "ae_mulaafd24.hl.lh_s2 \0" + /* 20667 */ "ae_mulzaafd24.hl.lh_s2 \0" + /* 20691 */ "ae_mulasfd24.hl.lh_s2 \0" + /* 20714 */ "ae_mulzasfd24.hl.lh_s2 \0" + /* 20738 */ "ae_mulssfd24.hl.lh_s2 \0" + /* 20761 */ "ae_mulzssfd24.hl.lh_s2 \0" + /* 20785 */ "ae_mulasd24.hl.lh_s2 \0" + /* 20807 */ "ae_mulzasd24.hl.lh_s2 \0" + /* 20830 */ "ae_mulssd24.hl.lh_s2 \0" + /* 20852 */ "ae_mulzssd24.hl.lh_s2 \0" + /* 20875 */ "ae_mulas32f48p16s.lh_s2 \0" + /* 20900 */ "ae_muls32f48p16s.lh_s2 \0" + /* 20924 */ "ae_mulss32f48p16s.lh_s2 \0" + /* 20949 */ "ae_mulafq32sp24s.l_s2 \0" + /* 20972 */ "ae_mulfq32sp24s.l_s2 \0" + /* 20994 */ "ae_mularfq32sp24s.l_s2 \0" + /* 21018 */ "ae_mulrfq32sp24s.l_s2 \0" + /* 21041 */ "ae_mulsrfq32sp24s.l_s2 \0" + /* 21065 */ "ae_mulsfq32sp24s.l_s2 \0" + /* 21088 */ "ae_mulaf48q32sp16s.l_s2 \0" + /* 21113 */ "ae_mulf48q32sp16s.l_s2 \0" + /* 21137 */ "ae_mulsf48q32sp16s.l_s2 \0" + /* 21162 */ "ae_mulaq32sp16s.l_s2 \0" + /* 21184 */ "ae_mulq32sp16s.l_s2 \0" + /* 21205 */ "ae_mulsq32sp16s.l_s2 \0" + /* 21227 */ "ae_mulafp32x16x2ras.l_s2 \0" + /* 21253 */ "ae_mulfp32x16x2ras.l_s2 \0" + /* 21278 */ "ae_mulsfp32x16x2ras.l_s2 \0" + /* 21304 */ "ae_mulafp32x16x2rs.l_s2 \0" + /* 21329 */ "ae_mulfp32x16x2rs.l_s2 \0" + /* 21353 */ "ae_mulsfp32x16x2rs.l_s2 \0" + /* 21378 */ "ae_mulaf48q32sp16u.l_s2 \0" + /* 21403 */ "ae_mulf48q32sp16u.l_s2 \0" + /* 21427 */ "ae_mulsf48q32sp16u.l_s2 \0" + /* 21452 */ "ae_mulaq32sp16u.l_s2 \0" + /* 21474 */ "ae_mulq32sp16u.l_s2 \0" + /* 21495 */ "ae_mulsq32sp16u.l_s2 \0" + /* 21517 */ "ae_mula32.ll_s2 \0" + /* 21534 */ "ae_mul32.ll_s2 \0" + /* 21550 */ "ae_mulaad24.hh.ll_s2 \0" + /* 21572 */ "ae_mulzaad24.hh.ll_s2 \0" + /* 21595 */ "ae_mulsad24.hh.ll_s2 \0" + /* 21617 */ "ae_mulzsad24.hh.ll_s2 \0" + /* 21640 */ "ae_mulaafd24.hh.ll_s2 \0" + /* 21663 */ "ae_mulzaafd24.hh.ll_s2 \0" + /* 21687 */ "ae_mulsafd24.hh.ll_s2 \0" + /* 21710 */ "ae_mulzsafd24.hh.ll_s2 \0" + /* 21734 */ "ae_mulasfd24.hh.ll_s2 \0" + /* 21757 */ "ae_mulzasfd24.hh.ll_s2 \0" + /* 21781 */ "ae_mulssfd24.hh.ll_s2 \0" + /* 21804 */ "ae_mulzssfd24.hh.ll_s2 \0" + /* 21828 */ "ae_mulasd24.hh.ll_s2 \0" + /* 21850 */ "ae_mulzasd24.hh.ll_s2 \0" + /* 21873 */ "ae_mulssd24.hh.ll_s2 \0" + /* 21895 */ "ae_mulzssd24.hh.ll_s2 \0" + /* 21918 */ "ae_mulaf32r.ll_s2 \0" + /* 21937 */ "ae_mulf32r.ll_s2 \0" + /* 21955 */ "ae_mulsf32r.ll_s2 \0" + /* 21974 */ "ae_mulaf32s.ll_s2 \0" + /* 21993 */ "ae_mulf32s.ll_s2 \0" + /* 22011 */ "ae_mulas32f48p16s.ll_s2 \0" + /* 22036 */ "ae_muls32f48p16s.ll_s2 \0" + /* 22060 */ "ae_mulss32f48p16s.ll_s2 \0" + /* 22085 */ "ae_mulafp24x2r_s2 \0" + /* 22104 */ "ae_mulfp24x2r_s2 \0" + /* 22122 */ "ae_mulsfp24x2r_s2 \0" + /* 22141 */ "ae_movda32x2 \0" + /* 22155 */ "ae_movf32x2 \0" + /* 22168 */ "ae_mulap32x2 \0" + /* 22182 */ "ae_mulp32x2 \0" + /* 22195 */ "ae_mulsp32x2 \0" + /* 22209 */ "ae_movt32x2 \0" + /* 22222 */ "ae_mulap24x2 \0" + /* 22236 */ "ae_mulp24x2 \0" + /* 22249 */ "ae_mulsp24x2 \0" + /* 22263 */ "ae_movda16x2 \0" + /* 22277 */ "ae_movad16.3 \0" + /* 22291 */ "ae_mulaf16ss.33 \0" + /* 22308 */ "ae_mulf16ss.33 \0" + /* 22324 */ "ae_mulsf16ss.33 \0" + /* 22341 */ "ae_mula32x16.h3 \0" + /* 22358 */ "ae_mulaf32x16.h3 \0" + /* 22376 */ "ae_mulf32x16.h3 \0" + /* 22393 */ "ae_mulsf32x16.h3 \0" + /* 22411 */ "ae_mul32x16.h3 \0" + /* 22427 */ "ae_muls32x16.h3 \0" + /* 22444 */ "ae_mulaad32x16.h2.l3 \0" + /* 22466 */ "ae_mulzaad32x16.h2.l3 \0" + /* 22489 */ "ae_mulaafd32x16.h2.l3 \0" + /* 22512 */ "ae_mulzaafd32x16.h2.l3 \0" + /* 22536 */ "ae_mula32x16.l3 \0" + /* 22553 */ "ae_mulaf32x16.l3 \0" + /* 22571 */ "ae_mulf32x16.l3 \0" + /* 22588 */ "ae_mulsf32x16.l3 \0" + /* 22606 */ "ae_mul32x16.l3 \0" + /* 22622 */ "ae_muls32x16.l3 \0" + /* 22639 */ "ae_mulac24 \0" + /* 22651 */ "ae_mulc24 \0" + /* 22662 */ "ae_slai24 \0" + /* 22673 */ "ae_srai24 \0" + /* 22684 */ "ae_srli24 \0" + /* 22695 */ "ae_pksr24 \0" + /* 22706 */ "ae_slas24 \0" + /* 22717 */ "ae_sras24 \0" + /* 22728 */ "ae_srls24 \0" + /* 22739 */ "ae_slaa64 \0" + /* 22750 */ "ae_sraa64 \0" + /* 22761 */ "ae_srla64 \0" + /* 22772 */ "ae_nsa64 \0" + /* 22782 */ "ae_sub64 \0" + /* 22792 */ "ae_add64 \0" + /* 22802 */ "ae_le64 \0" + /* 22811 */ "ae_movf64 \0" + /* 22822 */ "ae_neg64 \0" + /* 22832 */ "ae_slai64 \0" + /* 22843 */ "ae_srai64 \0" + /* 22854 */ "ae_srli64 \0" + /* 22865 */ "ae_zalign64 \0" + /* 22878 */ "ae_min64 \0" + /* 22888 */ "ae_eq64 \0" + /* 22897 */ "ae_slas64 \0" + /* 22908 */ "ae_sras64 \0" + /* 22919 */ "ae_abs64 \0" + /* 22929 */ "ae_srls64 \0" + /* 22940 */ "ae_lt64 \0" + /* 22949 */ "ae_movt64 \0" + /* 22960 */ "ae_max64 \0" + /* 22970 */ "!movba4 \0" + /* 22979 */ "!extui_br4 \0" + /* 22991 */ "ae_mula16x4 \0" + /* 23004 */ "ae_movf16x4 \0" + /* 23017 */ "ae_mul16x4 \0" + /* 23029 */ "ae_muls16x4 \0" + /* 23042 */ "ae_sat16x4 \0" + /* 23054 */ "ae_movt16x4 \0" + /* 23067 */ "ae_movda16 \0" + /* 23079 */ "ae_sub16 \0" + /* 23089 */ "ae_add16 \0" + /* 23099 */ "ae_le16 \0" + /* 23108 */ "ae_srai16 \0" + /* 23119 */ "ae_eq16 \0" + /* 23128 */ "ae_lt16 \0" + /* 23137 */ "ae_slaaq56 \0" + /* 23149 */ "ae_slasq56 \0" + /* 23161 */ "# SRA_P \0" + /* 23170 */ "!L8I_P \0" + /* 23178 */ "# SLL_P \0" + /* 23187 */ "# SRL_P \0" + /* 23196 */ "!movba \0" + /* 23204 */ "ae_mulafp24x2ra \0" + /* 23221 */ "ae_mulfp24x2ra \0" + /* 23237 */ "ae_mulsfp24x2ra \0" + /* 23254 */ "ae_mulafc24ra \0" + /* 23269 */ "ae_mulfc24ra \0" + /* 23283 */ "ae_db \0" + /* 23290 */ "ae_lb \0" + /* 23297 */ "ae_sb \0" + /* 23304 */ "ae_vldl16c \0" + /* 23316 */ "ae_vles16c \0" + /* 23328 */ "!loopdec \0" + /* 23338 */ "ae_la32x2.ic \0" + /* 23352 */ "ae_sa32x2.ic \0" + /* 23366 */ "ae_la24x2.ic \0" + /* 23380 */ "ae_sa24x2.ic \0" + /* 23394 */ "ae_la24.ic \0" + /* 23406 */ "ae_la32x2f24.ic \0" + /* 23423 */ "ae_sa32x2f24.ic \0" + /* 23440 */ "ae_la16x4.ic \0" + /* 23454 */ "ae_sa16x4.ic \0" + /* 23468 */ "ae_db.ic \0" + /* 23478 */ "ae_sb.ic \0" + /* 23488 */ "ae_vldl16c.ic \0" + /* 23503 */ "ae_vles16c.ic \0" + /* 23518 */ "ae_sbf.ic \0" + /* 23529 */ "ae_dbi.ic \0" + /* 23540 */ "ae_sbi.ic \0" + /* 23551 */ "ae_sa24.l.ic \0" + /* 23565 */ "ae_la32x2.ric \0" + /* 23580 */ "ae_sa32x2.ric \0" + /* 23595 */ "ae_l32x2.ric \0" + /* 23609 */ "ae_s32x2.ric \0" + /* 23623 */ "ae_la24x2.ric \0" + /* 23638 */ "ae_sa24x2.ric \0" + /* 23653 */ "ae_la24.ric \0" + /* 23666 */ "ae_la32x2f24.ric \0" + /* 23684 */ "ae_sa32x2f24.ric \0" + /* 23702 */ "ae_l32x2f24.ric \0" + /* 23719 */ "ae_s32x2f24.ric \0" + /* 23736 */ "ae_la16x4.ric \0" + /* 23751 */ "ae_sa16x4.ric \0" + /* 23766 */ "ae_l16x4.ric \0" + /* 23780 */ "ae_s16x4.ric \0" + /* 23794 */ "ae_sa24.l.ric \0" + /* 23809 */ "ae_la32x2neg.pc \0" + /* 23826 */ "ae_la24x2neg.pc \0" + /* 23843 */ "ae_la24neg.pc \0" + /* 23858 */ "ae_la16x4neg.pc \0" + /* 23875 */ "ae_la32x2pos.pc \0" + /* 23892 */ "ae_la24x2pos.pc \0" + /* 23909 */ "ae_la24pos.pc \0" + /* 23924 */ "ae_la16x4pos.pc \0" + /* 23941 */ "ae_s16.0.xc \0" + /* 23954 */ "ae_l32.xc \0" + /* 23965 */ "ae_l32x2.xc \0" + /* 23978 */ "ae_s32x2.xc \0" + /* 23991 */ "ae_l32f24.xc \0" + /* 24005 */ "ae_l32x2f24.xc \0" + /* 24021 */ "ae_s32x2f24.xc \0" + /* 24037 */ "ae_l64.xc \0" + /* 24048 */ "ae_s64.xc \0" + /* 24059 */ "ae_l16x4.xc \0" + /* 24072 */ "ae_s16x4.xc \0" + /* 24085 */ "ae_l16.xc \0" + /* 24096 */ "ae_s32.l.xc \0" + /* 24109 */ "ae_s32f24.l.xc \0" + /* 24125 */ "ae_s16m.l.xc \0" + /* 24139 */ "ae_l32m.xc \0" + /* 24151 */ "ae_s32m.xc \0" + /* 24163 */ "ae_l16x2m.xc \0" + /* 24177 */ "ae_s16x2m.xc \0" + /* 24191 */ "ae_l16m.xc \0" + /* 24203 */ "ae_s32ra64s.xc \0" + /* 24219 */ "ae_s24ra64s.xc \0" + /* 24235 */ "rur.ae_bithead \0" + /* 24251 */ "wur.ae_bithead \0" + /* 24267 */ "rur.ae_bitsused \0" + /* 24284 */ "wur.ae_bitsused \0" + /* 24301 */ "ae_and \0" + /* 24309 */ "ae_nand \0" + /* 24318 */ "!loopend \0" + /* 24328 */ "rur.ae_searchdone \0" + /* 24347 */ "wur.ae_searchdone \0" + /* 24366 */ "rur.ae_tablesize \0" + /* 24384 */ "wur.ae_tablesize \0" + /* 24402 */ "ae_sbf \0" + /* 24410 */ "ae_div64d32.h \0" + /* 24425 */ "ae_movad32.h \0" + /* 24439 */ "ae_cvt64f32.h \0" + /* 24454 */ "ae_mulap32x16x2.h \0" + /* 24473 */ "ae_mulp32x16x2.h \0" + /* 24491 */ "ae_mulsp32x16x2.h \0" + /* 24510 */ "ae_mulac32x16.h \0" + /* 24527 */ "ae_mulc32x16.h \0" + /* 24543 */ "ae_mulafd24x2.fir.h \0" + /* 24564 */ "ae_mulfd24x2.fir.h \0" + /* 24584 */ "ae_cvtq56p32s.h \0" + /* 24601 */ "ae_cvta32f24s.h \0" + /* 24618 */ "ae_mulafp32x16x2ras.h \0" + /* 24641 */ "ae_mulfp32x16x2ras.h \0" + /* 24663 */ "ae_mulsfp32x16x2ras.h \0" + /* 24686 */ "ae_mulafc32x16ras.h \0" + /* 24707 */ "ae_mulfc32x16ras.h \0" + /* 24727 */ "ae_mulafp32x16x2rs.h \0" + /* 24749 */ "ae_mulfp32x16x2rs.h \0" + /* 24770 */ "ae_mulsfp32x16x2rs.h \0" + /* 24792 */ "ae_mula32.hh \0" + /* 24806 */ "ae_mul32.hh \0" + /* 24819 */ "ae_muls32.hh \0" + /* 24833 */ "ae_mulaf32r.hh \0" + /* 24849 */ "ae_mulf32r.hh \0" + /* 24864 */ "ae_mulsf32r.hh \0" + /* 24880 */ "ae_mulafd32x16x2.fir.hh \0" + /* 24905 */ "ae_mulfd32x16x2.fir.hh \0" + /* 24929 */ "ae_mulaf32s.hh \0" + /* 24945 */ "ae_mulf32s.hh \0" + /* 24960 */ "ae_mulsf32s.hh \0" + /* 24976 */ "ae_mulas32f48p16s.hh \0" + /* 24998 */ "ae_muls32f48p16s.hh \0" + /* 25019 */ "ae_mulss32f48p16s.hh \0" + /* 25041 */ "ae_mula32.lh \0" + /* 25055 */ "ae_mul32.lh \0" + /* 25068 */ "ae_muls32.lh \0" + /* 25082 */ "ae_mulaad24.hl.lh \0" + /* 25101 */ "ae_mulzaad24.hl.lh \0" + /* 25121 */ "ae_mulaafd24.hl.lh \0" + /* 25141 */ "ae_mulzaafd24.hl.lh \0" + /* 25162 */ "ae_mulasfd24.hl.lh \0" + /* 25182 */ "ae_mulzasfd24.hl.lh \0" + /* 25203 */ "ae_mulssfd24.hl.lh \0" + /* 25223 */ "ae_mulzssfd24.hl.lh \0" + /* 25244 */ "ae_mulasd24.hl.lh \0" + /* 25263 */ "ae_mulzasd24.hl.lh \0" + /* 25283 */ "ae_mulssd24.hl.lh \0" + /* 25302 */ "ae_mulzssd24.hl.lh \0" + /* 25322 */ "ae_mulaf32r.lh \0" + /* 25338 */ "ae_mulf32r.lh \0" + /* 25353 */ "ae_mulsf32r.lh \0" + /* 25369 */ "ae_mulafd32x16x2.fir.lh \0" + /* 25394 */ "ae_mulfd32x16x2.fir.lh \0" + /* 25418 */ "ae_mulaf32s.lh \0" + /* 25434 */ "ae_mulf32s.lh \0" + /* 25449 */ "ae_mulsf32s.lh \0" + /* 25465 */ "ae_mulas32f48p16s.lh \0" + /* 25487 */ "ae_muls32f48p16s.lh \0" + /* 25508 */ "ae_mulss32f48p16s.lh \0" + /* 25530 */ "ae_add32_hl_lh \0" + /* 25546 */ "ae_s16.0.i \0" + /* 25558 */ "ae_l32.i \0" + /* 25568 */ "ae_l32x2.i \0" + /* 25580 */ "ae_s32x2.i \0" + /* 25592 */ "ae_l32f24.i \0" + /* 25605 */ "ae_l32x2f24.i \0" + /* 25620 */ "ae_s32x2f24.i \0" + /* 25635 */ "ae_l64.i \0" + /* 25645 */ "ae_lalign64.i \0" + /* 25660 */ "ae_salign64.i \0" + /* 25675 */ "ae_s64.i \0" + /* 25685 */ "ae_l16x4.i \0" + /* 25697 */ "ae_s16x4.i \0" + /* 25709 */ "ae_l16.i \0" + /* 25719 */ "ae_s32.l.i \0" + /* 25731 */ "ae_s32f24.l.i \0" + /* 25746 */ "ae_s16m.l.i \0" + /* 25759 */ "ae_l32m.i \0" + /* 25770 */ "ae_s32m.i \0" + /* 25781 */ "ae_l16x2m.i \0" + /* 25794 */ "ae_s16x2m.i \0" + /* 25807 */ "ae_l16m.i \0" + /* 25818 */ "ae_s32ra64s.i \0" + /* 25833 */ "ae_s24ra64s.i \0" + /* 25848 */ "ae_sel16i \0" + /* 25859 */ "ae_dbi \0" + /* 25867 */ "ae_lbi \0" + /* 25875 */ "ae_sbi \0" + /* 25883 */ "ae_lbki \0" + /* 25892 */ "ae_lbsi \0" + /* 25901 */ "ae_movi \0" + /* 25910 */ "ae_lbk \0" + /* 25918 */ "ae_div64d32.l \0" + /* 25933 */ "ae_movad32.l \0" + /* 25947 */ "ae_nsaz32.l \0" + /* 25960 */ "ae_mulap32x16x2.l \0" + /* 25979 */ "ae_mulp32x16x2.l \0" + /* 25997 */ "ae_mulsp32x16x2.l \0" + /* 26016 */ "ae_mulac32x16.l \0" + /* 26033 */ "ae_mulc32x16.l \0" + /* 26049 */ "ae_mulafd24x2.fir.l \0" + /* 26070 */ "ae_mulfd24x2.fir.l \0" + /* 26090 */ "ae_cvtq56p32s.l \0" + /* 26107 */ "ae_cvta32f24s.l \0" + /* 26124 */ "ae_trunca32f64s.l \0" + /* 26143 */ "ae_trunci32f64s.l \0" + /* 26162 */ "ae_mulaf48q32sp16s.l \0" + /* 26184 */ "ae_mulf48q32sp16s.l \0" + /* 26205 */ "ae_mulsf48q32sp16s.l \0" + /* 26227 */ "ae_mulafp32x16x2ras.l \0" + /* 26250 */ "ae_mulfp32x16x2ras.l \0" + /* 26272 */ "ae_mulsfp32x16x2ras.l \0" + /* 26295 */ "ae_mulafc32x16ras.l \0" + /* 26316 */ "ae_mulfc32x16ras.l \0" + /* 26336 */ "ae_mulafp32x16x2rs.l \0" + /* 26358 */ "ae_mulfp32x16x2rs.l \0" + /* 26379 */ "ae_mulsfp32x16x2rs.l \0" + /* 26401 */ "ae_mulaf48q32sp16u.l \0" + /* 26423 */ "ae_mulf48q32sp16u.l \0" + /* 26444 */ "ae_mulsf48q32sp16u.l \0" + /* 26466 */ "ae_mulafd32x16x2.fir.hl \0" + /* 26491 */ "ae_mulfd32x16x2.fir.hl \0" + /* 26515 */ "ae_mula32.ll \0" + /* 26529 */ "ae_mul32.ll \0" + /* 26542 */ "ae_muls32.ll \0" + /* 26556 */ "ae_mulaad24.hh.ll \0" + /* 26575 */ "ae_mulzaad24.hh.ll \0" + /* 26595 */ "ae_mulsad24.hh.ll \0" + /* 26614 */ "ae_mulzsad24.hh.ll \0" + /* 26634 */ "ae_mulaafd24.hh.ll \0" + /* 26654 */ "ae_mulzaafd24.hh.ll \0" + /* 26675 */ "ae_mulsafd24.hh.ll \0" + /* 26695 */ "ae_mulzsafd24.hh.ll \0" + /* 26716 */ "ae_mulasfd24.hh.ll \0" + /* 26736 */ "ae_mulzasfd24.hh.ll \0" + /* 26757 */ "ae_mulssfd24.hh.ll \0" + /* 26777 */ "ae_mulzssfd24.hh.ll \0" + /* 26798 */ "ae_mulasd24.hh.ll \0" + /* 26817 */ "ae_mulzasd24.hh.ll \0" + /* 26837 */ "ae_mulssd24.hh.ll \0" + /* 26856 */ "ae_mulzssd24.hh.ll \0" + /* 26876 */ "ae_mulaf32r.ll \0" + /* 26892 */ "ae_mulf32r.ll \0" + /* 26907 */ "ae_mulsf32r.ll \0" + /* 26923 */ "ae_mulafd32x16x2.fir.ll \0" + /* 26948 */ "ae_mulfd32x16x2.fir.ll \0" + /* 26972 */ "ae_mulaf32s.ll \0" + /* 26988 */ "ae_mulf32s.ll \0" + /* 27003 */ "ae_mulsf32s.ll \0" + /* 27019 */ "ae_mulas32f48p16s.ll \0" + /* 27041 */ "ae_muls32f48p16s.ll \0" + /* 27062 */ "ae_mulss32f48p16s.ll \0" + /* 27084 */ "ae_mula32u.ll \0" + /* 27099 */ "ae_mul32u.ll \0" + /* 27113 */ "ae_muls32u.ll \0" + /* 27128 */ "!restore_bool \0" + /* 27143 */ "!spill_bool \0" + /* 27156 */ "ae_roundsp16q48x2sym \0" + /* 27178 */ "ae_roundsp16f24sym \0" + /* 27198 */ "ae_roundsq32f48sym \0" + /* 27218 */ "ae_roundsp16q48x2asym \0" + /* 27241 */ "ae_roundsp16f24asym \0" + /* 27262 */ "ae_roundsq32f48asym \0" + /* 27283 */ "ae_round16x4f32sasym \0" + /* 27305 */ "ae_round32x2f64sasym \0" + /* 27327 */ "ae_round32x2f48sasym \0" + /* 27349 */ "ae_round24x2f48sasym \0" + /* 27371 */ "ae_round16x4f32ssym \0" + /* 27392 */ "ae_round32x2f64ssym \0" + /* 27413 */ "ae_round32x2f48ssym \0" + /* 27434 */ "ae_round24x2f48ssym \0" + /* 27455 */ "ae_sel16i.n \0" + /* 27468 */ "ae_movalign \0" + /* 27481 */ "rur.ae_cw_sd_no \0" + /* 27498 */ "wur.ae_cw_sd_no \0" + /* 27515 */ "rur.ae_cwrap \0" + /* 27529 */ "wur.ae_cwrap \0" + /* 27543 */ "ae_shortswap \0" + /* 27557 */ "rur.ae_ts_fts_bu_bp \0" + /* 27578 */ "wur.ae_ts_fts_bu_bp \0" + /* 27599 */ "ae_sa64neg.fp \0" + /* 27614 */ "ae_sa64pos.fp \0" + /* 27629 */ "!brcc_fp \0" + /* 27639 */ "!select_cc_fp_fp \0" + /* 27657 */ "!select_cc_int_fp \0" + /* 27676 */ "ae_s16.0.ip \0" + /* 27689 */ "ae_l32.ip \0" + /* 27700 */ "ae_la32x2.ip \0" + /* 27714 */ "ae_sa32x2.ip \0" + /* 27728 */ "ae_l32x2.ip \0" + /* 27741 */ "ae_s32x2.ip \0" + /* 27754 */ "ae_la24x2.ip \0" + /* 27768 */ "ae_sa24x2.ip \0" + /* 27782 */ "ae_la24.ip \0" + /* 27794 */ "ae_l32f24.ip \0" + /* 27808 */ "ae_la32x2f24.ip \0" + /* 27825 */ "ae_sa32x2f24.ip \0" + /* 27842 */ "ae_l32x2f24.ip \0" + /* 27858 */ "ae_s32x2f24.ip \0" + /* 27874 */ "ae_l64.ip \0" + /* 27885 */ "ae_s64.ip \0" + /* 27896 */ "ae_la16x4.ip \0" + /* 27910 */ "ae_sa16x4.ip \0" + /* 27924 */ "ae_l16x4.ip \0" + /* 27937 */ "ae_s16x4.ip \0" + /* 27950 */ "ae_l16.ip \0" + /* 27961 */ "ae_db.ip \0" + /* 27971 */ "ae_sb.ip \0" + /* 27981 */ "ae_vldl16c.ip \0" + /* 27996 */ "ae_vles16c.ip \0" + /* 28011 */ "ae_sbf.ip \0" + /* 28022 */ "ae_dbi.ip \0" + /* 28033 */ "ae_sbi.ip \0" + /* 28044 */ "ae_s32.l.ip \0" + /* 28057 */ "ae_sa24.l.ip \0" + /* 28071 */ "ae_s32f24.l.ip \0" + /* 28087 */ "ae_s32ra64s.ip \0" + /* 28103 */ "ae_s32x2ra64s.ip \0" + /* 28121 */ "ae_s24x2ra64s.ip \0" + /* 28139 */ "ae_s24ra64s.ip \0" + /* 28155 */ "ae_la32x2.rip \0" + /* 28170 */ "ae_sa32x2.rip \0" + /* 28185 */ "ae_l32x2.rip \0" + /* 28199 */ "ae_s32x2.rip \0" + /* 28213 */ "ae_la24x2.rip \0" + /* 28228 */ "ae_sa24x2.rip \0" + /* 28243 */ "ae_la24.rip \0" + /* 28256 */ "ae_la32x2f24.rip \0" + /* 28274 */ "ae_sa32x2f24.rip \0" + /* 28292 */ "ae_l32x2f24.rip \0" + /* 28309 */ "ae_s32x2f24.rip \0" + /* 28326 */ "ae_la16x4.rip \0" + /* 28341 */ "ae_sa16x4.rip \0" + /* 28356 */ "ae_l16x4.rip \0" + /* 28370 */ "ae_s16x4.rip \0" + /* 28384 */ "ae_sa24.l.rip \0" + /* 28399 */ "ae_la64.pp \0" + /* 28411 */ "ae_s16.0.xp \0" + /* 28424 */ "ae_l32.xp \0" + /* 28435 */ "ae_l32x2.xp \0" + /* 28448 */ "ae_s32x2.xp \0" + /* 28461 */ "ae_l32f24.xp \0" + /* 28475 */ "ae_l32x2f24.xp \0" + /* 28491 */ "ae_s32x2f24.xp \0" + /* 28507 */ "ae_l64.xp \0" + /* 28518 */ "ae_s64.xp \0" + /* 28529 */ "ae_l16x4.xp \0" + /* 28542 */ "ae_s16x4.xp \0" + /* 28555 */ "ae_l16.xp \0" + /* 28566 */ "ae_s32.l.xp \0" + /* 28579 */ "ae_s32f24.l.xp \0" + /* 28595 */ "ae_s32ra64s.xp \0" + /* 28611 */ "ae_s24ra64s.xp \0" + /* 28627 */ "ae_srai32r \0" + /* 28639 */ "ae_mulafp24x2r \0" + /* 28655 */ "ae_mulfp24x2r \0" + /* 28670 */ "ae_mulsfp24x2r \0" + /* 28686 */ "ae_srai16r \0" + /* 28698 */ "rur.ae_sar \0" + /* 28710 */ "wur.ae_sar \0" + /* 28722 */ "rur.ae_ovf_sar \0" + /* 28738 */ "wur.ae_ovf_sar \0" + /* 28754 */ "!slli_br \0" + /* 28764 */ "!extui_br \0" + /* 28775 */ "!loopbr \0" + /* 28784 */ "ae_or \0" + /* 28791 */ "ae_xor \0" + /* 28799 */ "rur.ae_bitptr \0" + /* 28814 */ "wur.ae_bitptr \0" + /* 28829 */ "ae_cvtq56a32s \0" + /* 28844 */ "ae_slaa32s \0" + /* 28856 */ "ae_sraa32s \0" + /* 28868 */ "ae_sub32s \0" + /* 28879 */ "ae_addsub32s \0" + /* 28893 */ "ae_add32s \0" + /* 28904 */ "ae_subadd32s \0" + /* 28918 */ "ae_neg32s \0" + /* 28929 */ "ae_slai32s \0" + /* 28941 */ "ae_slas32s \0" + /* 28953 */ "ae_abs32s \0" + /* 28964 */ "ae_minabs32s \0" + /* 28978 */ "ae_maxabs32s \0" + /* 28992 */ "ae_sub24s \0" + /* 29003 */ "ae_add24s \0" + /* 29014 */ "ae_neg24s \0" + /* 29025 */ "ae_slai24s \0" + /* 29037 */ "ae_slas24s \0" + /* 29049 */ "ae_abs24s \0" + /* 29060 */ "ae_sat24s \0" + /* 29071 */ "ae_slaa64s \0" + /* 29083 */ "ae_sub64s \0" + /* 29094 */ "ae_add64s \0" + /* 29105 */ "ae_trunca32x2f64s \0" + /* 29124 */ "ae_trunci32x2f64s \0" + /* 29143 */ "ae_neg64s \0" + /* 29154 */ "ae_slai64s \0" + /* 29166 */ "ae_slas64s \0" + /* 29178 */ "ae_abs64s \0" + /* 29189 */ "ae_minabs64s \0" + /* 29203 */ "ae_maxabs64s \0" + /* 29217 */ "ae_mulfp16x4s \0" + /* 29232 */ "ae_slaa16s \0" + /* 29244 */ "ae_sraa16s \0" + /* 29256 */ "ae_sub16s \0" + /* 29267 */ "ae_add16s \0" + /* 29278 */ "ae_neg16s \0" + /* 29289 */ "ae_slai16s \0" + /* 29301 */ "ae_abs16s \0" + /* 29312 */ "ae_slaisq56s \0" + /* 29326 */ "ae_slassq56s \0" + /* 29340 */ "ae_satq56s \0" + /* 29352 */ "ae_sat48s \0" + /* 29363 */ "ae_mulafp32x2ras \0" + /* 29381 */ "ae_mulfp32x2ras \0" + /* 29398 */ "ae_mulsfp32x2ras \0" + /* 29416 */ "ae_mulfp16x4ras \0" + /* 29433 */ "ae_lbs \0" + /* 29441 */ "ae_sraa32rs \0" + /* 29454 */ "ae_mulafp32x2rs \0" + /* 29471 */ "ae_mulfp32x2rs \0" + /* 29487 */ "ae_mulsfp32x2rs \0" + /* 29504 */ "ae_sraa16rs \0" + /* 29517 */ "ae_mulaf16x4ss \0" + /* 29533 */ "ae_mulf16x4ss \0" + /* 29548 */ "ae_mulsf16x4ss \0" + /* 29564 */ "rur.ae_first_ts \0" + /* 29581 */ "wur.ae_first_ts \0" + /* 29598 */ "ae_vldl32t \0" + /* 29610 */ "ae_vlel32t \0" + /* 29622 */ "ae_vldl16t \0" + /* 29634 */ "ae_vlel16t \0" + /* 29646 */ "!select \0" + /* 29655 */ "rur.ae_nextoffset \0" + /* 29674 */ "wur.ae_nextoffset \0" + /* 29693 */ "ae_vldsht \0" + /* 29704 */ "!loopinit \0" + /* 29715 */ "!select_cc_fp_int \0" + /* 29734 */ "!loopstart \0" + /* 29746 */ "ae_s16m.l.iu \0" + /* 29760 */ "ae_l32m.iu \0" + /* 29772 */ "ae_s32m.iu \0" + /* 29784 */ "ae_l16x2m.iu \0" + /* 29798 */ "ae_s16x2m.iu \0" + /* 29812 */ "ae_l16m.iu \0" + /* 29824 */ "ae_s16m.l.xu \0" + /* 29838 */ "ae_l32m.xu \0" + /* 29850 */ "ae_s32m.xu \0" + /* 29862 */ "ae_l16x2m.xu \0" + /* 29876 */ "ae_s16x2m.xu \0" + /* 29890 */ "ae_l16m.xu \0" + /* 29902 */ "ae_mov \0" + /* 29910 */ "rur.ae_overflow \0" + /* 29927 */ "wur.ae_overflow \0" + /* 29944 */ "ae_s16.0.x \0" + /* 29956 */ "ae_l32.x \0" + /* 29966 */ "ae_l32x2.x \0" + /* 29978 */ "ae_s32x2.x \0" + /* 29990 */ "ae_l32f24.x \0" + /* 30003 */ "ae_l32x2f24.x \0" + /* 30018 */ "ae_s32x2f24.x \0" + /* 30033 */ "ae_l64.x \0" + /* 30043 */ "ae_s64.x \0" + /* 30053 */ "ae_l16x4.x \0" + /* 30065 */ "ae_s16x4.x \0" + /* 30077 */ "ae_l16.x \0" + /* 30087 */ "ae_s32.l.x \0" + /* 30099 */ "ae_s32f24.l.x \0" + /* 30114 */ "ae_s16m.l.x \0" + /* 30127 */ "ae_l32m.x \0" + /* 30138 */ "ae_s32m.x \0" + /* 30149 */ "ae_l16x2m.x \0" + /* 30162 */ "ae_s16x2m.x \0" + /* 30175 */ "ae_l16m.x \0" + /* 30186 */ "ae_s32ra64s.x \0" + /* 30201 */ "ae_s24ra64s.x \0" + /* 30216 */ "# XRay Function Patchable RET.\0" + /* 30247 */ "# XRay Typed Event Log.\0" + /* 30271 */ "# XRay Custom Event Log.\0" + /* 30296 */ "# XRay Function Enter.\0" + /* 30319 */ "# XRay Tail Call Exit.\0" + /* 30342 */ "# XRay Function Exit.\0" + /* 30364 */ "LIFETIME_END\0" + /* 30377 */ "PSEUDO_PROBE\0" + /* 30390 */ "BUNDLE\0" + /* 30397 */ "DBG_VALUE\0" + /* 30407 */ "DBG_INSTR_REF\0" + /* 30421 */ "DBG_PHI\0" + /* 30429 */ "DBG_LABEL\0" + /* 30439 */ "#ADJCALLSTACKDOWN\0" + /* 30457 */ "#ADJCALLSTACKUP\0" + /* 30473 */ "LIFETIME_START\0" + /* 30488 */ "DBG_VALUE_LIST\0" + /* 30503 */ "dsync\0" + /* 30509 */ "esync\0" + /* 30515 */ "isync\0" + /* 30521 */ "rsync\0" + /* 30527 */ "rfde\0" + /* 30532 */ "rfe\0" + /* 30536 */ "# FEntry call\0" + /* 30550 */ "simcall\0" + /* 30558 */ "syscall\0" + /* 30566 */ "ill\0" + /* 30570 */ "ill.n\0" + /* 30576 */ "ret.n\0" + /* 30582 */ "retw.n\0" + /* 30589 */ "foo\0" + /* 30593 */ "rfwo\0" + /* 30598 */ "!xtensa_ee_zero_qacc_p\0" + /* 30621 */ "!xtensa_ee_zero_accx_p\0" + /* 30644 */ "nop\0" + /* 30648 */ "ret\0" + /* 30652 */ "rfwu\0" + /* 30657 */ "excw\0" + /* 30662 */ "memw\0" + /* 30667 */ "retw\0" + /* 30672 */ "extw\0" }; #endif // CAPSTONE_DIET - static const uint16_t OpInfo0[] = { + static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // INLINEASM_BR @@ -130,20 +1742,20 @@ static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS - 601U, // DBG_VALUE - 658U, // DBG_VALUE_LIST - 611U, // DBG_INSTR_REF - 625U, // DBG_PHI - 633U, // DBG_LABEL + 30398U, // DBG_VALUE + 30489U, // DBG_VALUE_LIST + 30408U, // DBG_INSTR_REF + 30422U, // DBG_PHI + 30430U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY - 594U, // BUNDLE - 643U, // LIFETIME_START - 568U, // LIFETIME_END - 581U, // PSEUDO_PROBE + 30391U, // BUNDLE + 30474U, // LIFETIME_START + 30365U, // LIFETIME_END + 30378U, // PSEUDO_PROBE 0U, // ARITH_FENCE 0U, // STACKMAP - 697U, // FENTRY_CALL + 30537U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // PREALLOCATED_SETUP @@ -152,12 +1764,12 @@ static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP - 500U, // PATCHABLE_FUNCTION_ENTER - 420U, // PATCHABLE_RET - 546U, // PATCHABLE_FUNCTION_EXIT - 523U, // PATCHABLE_TAIL_CALL - 475U, // PATCHABLE_EVENT_CALL - 451U, // PATCHABLE_TYPED_EVENT_CALL + 30297U, // PATCHABLE_FUNCTION_ENTER + 30217U, // PATCHABLE_RET + 30343U, // PATCHABLE_FUNCTION_EXIT + 30320U, // PATCHABLE_TAIL_CALL + 30272U, // PATCHABLE_EVENT_CALL + 30248U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // MEMBARRIER 0U, // JUMP_TABLE_DEBUG_INFO @@ -388,88 +2000,1729 @@ static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 0U, // G_VECREDUCE_UMIN 0U, // G_SBFX 0U, // G_UBFX - 1351U, // ABS - 1102U, // ADD - 1175U, // ADDI - 1205U, // ADDMI - 1047U, // ADDX2 - 1061U, // ADDX4 - 1075U, // ADDX8 - 1107U, // AND - 1287U, // BALL - 1382U, // BANY - 1092U, // BBC - 17553U, // BBCI - 1356U, // BBS - 17609U, // BBSI - 1315U, // BEQ - 33980U, // BEQI - 50568U, // BEQZ - 1112U, // BGE - 33949U, // BGEI - 1366U, // BGEU - 1250U, // BGEUI - 50540U, // BGEZ - 1361U, // BLT - 33999U, // BLTI - 1372U, // BLTU - 1257U, // BLTUI - 50582U, // BLTZ - 1293U, // BNALL - 1117U, // BNE - 33955U, // BNEI - 50554U, // BNEZ - 1122U, // BNONE - 2049U, // CALL0 - 9224U, // CALLX0 - 673U, // DSYNC - 679U, // ESYNC - 1264U, // EXTUI - 724U, // EXTW - 685U, // ISYNC - 3325U, // J - 9570U, // JX - 17602U, // L16SI - 17621U, // L16UI - 17518U, // L32I - 34088U, // L32R - 17628U, // L8UI - 719U, // MEMW - 1422U, // MOVEQZ - 1394U, // MOVGEZ - 50423U, // MOVI - 1436U, // MOVLTZ - 1408U, // MOVNEZ - 1129U, // NEG - 711U, // NOP - 1327U, // OR - 715U, // RET - 1331U, // RSR - 691U, // RSYNC - 17530U, // S16I - 17524U, // S32I - 17536U, // S8I - 1300U, // SLL - 1193U, // SLLI - 1082U, // SRA - 1157U, // SRAI - 1097U, // SRC - 1305U, // SRL - 1199U, // SRLI - 9472U, // SSA8L - 4235U, // SSAI - 9502U, // SSL - 9528U, // SSR - 1087U, // SUB - 1040U, // SUBX2 - 1054U, // SUBX4 - 1068U, // SUBX8 - 5437U, // WSR - 1326U, // XOR - 6466U, // XSR + 30440U, // ADJCALLSTACKDOWN + 30458U, // ADJCALLSTACKUP + 40789U, // ATOMIC_CMP_SWAP_16_P + 40108U, // ATOMIC_CMP_SWAP_32_P + 41469U, // ATOMIC_CMP_SWAP_8_P + 40647U, // ATOMIC_LOAD_ADD_16_P + 39944U, // ATOMIC_LOAD_ADD_32_P + 41333U, // ATOMIC_LOAD_ADD_8_P + 40671U, // ATOMIC_LOAD_AND_16_P + 39968U, // ATOMIC_LOAD_AND_32_P + 41356U, // ATOMIC_LOAD_AND_8_P + 40908U, // ATOMIC_LOAD_MAX_16_P + 40295U, // ATOMIC_LOAD_MAX_32_P + 41583U, // ATOMIC_LOAD_MAX_8_P + 40720U, // ATOMIC_LOAD_MIN_16_P + 40039U, // ATOMIC_LOAD_MIN_32_P + 41403U, // ATOMIC_LOAD_MIN_8_P + 40695U, // ATOMIC_LOAD_NAND_16_P + 39992U, // ATOMIC_LOAD_NAND_32_P + 41379U, // ATOMIC_LOAD_NAND_8_P + 40861U, // ATOMIC_LOAD_OR_16_P + 40226U, // ATOMIC_LOAD_OR_32_P + 41538U, // ATOMIC_LOAD_OR_8_P + 40599U, // ATOMIC_LOAD_SUB_16_P + 39896U, // ATOMIC_LOAD_SUB_32_P + 41287U, // ATOMIC_LOAD_SUB_8_P + 40932U, // ATOMIC_LOAD_UMAX_16_P + 40319U, // ATOMIC_LOAD_UMAX_32_P + 41606U, // ATOMIC_LOAD_UMAX_8_P + 40744U, // ATOMIC_LOAD_UMIN_16_P + 40063U, // ATOMIC_LOAD_UMIN_32_P + 41426U, // ATOMIC_LOAD_UMIN_8_P + 40884U, // ATOMIC_LOAD_XOR_16_P + 40249U, // ATOMIC_LOAD_XOR_32_P + 41560U, // ATOMIC_LOAD_XOR_8_P + 40769U, // ATOMIC_SWAP_16_P + 40088U, // ATOMIC_SWAP_32_P + 41450U, // ATOMIC_SWAP_8_P + 60398U, // BRCC_FP + 67156522U, // BR_JT + 30590U, // CONSTPOOL_ENTRY + 539048393U, // EE_ANDQ_P + 67189301U, // EE_BITREV_P + 536946937U, // EE_CMUL_S16_LD_INCP_P + 539041817U, // EE_CMUL_S16_P + 536947631U, // EE_CMUL_S16_ST_INCP_P + 536947099U, // EE_FFT_AMS_S16_LD_INCP_P + 536949305U, // EE_FFT_AMS_S16_LD_INCP_UAUP_P + 536946544U, // EE_FFT_AMS_S16_LD_R32_DECP_P + 2174033U, // EE_FFT_AMS_S16_ST_INCP_P + 79748U, // EE_FFT_CMUL_S16_LD_XP_P + 539048195U, // EE_FFT_CMUL_S16_ST_XP_P + 539041789U, // EE_FFT_R2BF_S16_P + 539044747U, // EE_FFT_R2BF_S16_ST_INCP_P + 1073817495U, // EE_FFT_VST_R32_DECP_P + 44924U, // EE_LDF_128_IP_P + 46876U, // EE_LDF_128_XP_P + 44591U, // EE_LDF_64_IP_P + 46543U, // EE_LDF_64_XP_P + 4239080U, // EE_LDQA_S16_128_IP_P + 67155592U, // EE_LDQA_S16_128_XP_P + 4239142U, // EE_LDQA_S8_128_IP_P + 67155654U, // EE_LDQA_S8_128_XP_P + 4239111U, // EE_LDQA_U16_128_IP_P + 67155623U, // EE_LDQA_U16_128_XP_P + 4239172U, // EE_LDQA_U8_128_IP_P + 67155684U, // EE_LDQA_U8_128_XP_P + 2170100U, // EE_LDXQ_32_P + 1610691047U, // EE_LD_128_USAR_IP_P + 80101U, // EE_LD_128_USAR_XP_P + 6337029U, // EE_LD_ACCX_IP_P + 8433067U, // EE_LD_QACC_H_H_32_IP_P + 4239280U, // EE_LD_QACC_H_L_128_IP_P + 8433133U, // EE_LD_QACC_L_H_32_IP_P + 4239348U, // EE_LD_QACC_L_L_128_IP_P + 4239787U, // EE_LD_UA_STATE_IP_P + 2147558313U, // EE_MOVI_32_A_P + 2147563909U, // EE_MOVI_32_Q_P + 599071U, // EE_MOV_S16_QACC_P + 599248U, // EE_MOV_S8_QACC_P + 599130U, // EE_MOV_U16_QACC_P + 599305U, // EE_MOV_U8_QACC_P + 69286404U, // EE_NOTQ_P + 539048413U, // EE_ORQ_P + 2686531877U, // EE_SLCI_2Q_P + 2177363U, // EE_SLCXXP_2Q_P + 2686531900U, // EE_SRCI_2Q_P + 1073816514U, // EE_SRCMB_S16_QACC_P + 1073816694U, // EE_SRCMB_S8_QACC_P + 2174132U, // EE_SRCQ_128_ST_INCP_P + 2177388U, // EE_SRCXXP_2Q_P + 1610690814U, // EE_SRC_Q_LD_IP_P + 79928U, // EE_SRC_Q_LD_XP_P + 539048350U, // EE_SRC_Q_P + 539047323U, // EE_SRC_Q_QUP_P + 1073789637U, // EE_SRS_ACCX_P + 44950U, // EE_STF_128_IP_P + 46902U, // EE_STF_128_XP_P + 44616U, // EE_STF_64_IP_P + 46568U, // EE_STF_64_XP_P + 2170123U, // EE_STXQ_32_P + 6337055U, // EE_ST_ACCX_IP_P + 8433100U, // EE_ST_QACC_H_H_32_IP_P + 4239314U, // EE_ST_QACC_H_L_128_IP_P + 8433166U, // EE_ST_QACC_L_H_32_IP_P + 4239382U, // EE_ST_QACC_L_L_128_IP_P + 4239817U, // EE_ST_UA_STATE_IP_P + 536947066U, // EE_VADDS_S16_LD_INCP_P + 539041941U, // EE_VADDS_S16_P + 536947760U, // EE_VADDS_S16_ST_INCP_P + 536946872U, // EE_VADDS_S32_LD_INCP_P + 539041252U, // EE_VADDS_S32_P + 536947530U, // EE_VADDS_S32_ST_INCP_P + 536947292U, // EE_VADDS_S8_LD_INCP_P + 539042558U, // EE_VADDS_S8_P + 536948018U, // EE_VADDS_S8_ST_INCP_P + 539041889U, // EE_VCMP_EQ_S16_P + 539041200U, // EE_VCMP_EQ_S32_P + 539042508U, // EE_VCMP_EQ_S8_P + 539041966U, // EE_VCMP_GT_S16_P + 539041277U, // EE_VCMP_GT_S32_P + 539042582U, // EE_VCMP_GT_S8_P + 539041993U, // EE_VCMP_LT_S16_P + 539041304U, // EE_VCMP_LT_S32_P + 539042608U, // EE_VCMP_LT_S8_P + 3221302989U, // EE_VLDBC_16_IP_P + 67182255U, // EE_VLDBC_16_P + 79469U, // EE_VLDBC_16_XP_P + 3758173584U, // EE_VLDBC_32_IP_P + 67181552U, // EE_VLDBC_32_P + 79284U, // EE_VLDBC_32_XP_P + 77906U, // EE_VLDBC_8_IP_P + 67182942U, // EE_VLDBC_8_P + 79722U, // EE_VLDBC_8_XP_P + 2172855U, // EE_VLDHBC_16_INCP_P + 1610690402U, // EE_VLD_128_IP_P + 79618U, // EE_VLD_128_XP_P + 536948321U, // EE_VLD_H_64_IP_P + 79361U, // EE_VLD_H_64_XP_P + 536948375U, // EE_VLD_L_64_IP_P + 79415U, // EE_VLD_L_64_XP_P + 536947134U, // EE_VMAX_S16_LD_INCP_P + 539042071U, // EE_VMAX_S16_P + 536947828U, // EE_VMAX_S16_ST_INCP_P + 536946905U, // EE_VMAX_S32_LD_INCP_P + 539041331U, // EE_VMAX_S32_P + 536947563U, // EE_VMAX_S32_ST_INCP_P + 536947324U, // EE_VMAX_S8_LD_INCP_P + 539042683U, // EE_VMAX_S8_P + 536948050U, // EE_VMAX_S8_ST_INCP_P + 536947001U, // EE_VMIN_S16_LD_INCP_P + 539041865U, // EE_VMIN_S16_P + 536947695U, // EE_VMIN_S16_ST_INCP_P + 536946807U, // EE_VMIN_S32_LD_INCP_P + 539041176U, // EE_VMIN_S32_P + 536947465U, // EE_VMIN_S32_ST_INCP_P + 536947229U, // EE_VMIN_S8_LD_INCP_P + 539042485U, // EE_VMIN_S8_P + 536947955U, // EE_VMIN_S8_ST_INCP_P + 1073819929U, // EE_VMULAS_S16_ACCX_LD_IP_P + 1073820597U, // EE_VMULAS_S16_ACCX_LD_IP_QUP_P + 79955U, // EE_VMULAS_S16_ACCX_LD_XP_P + 79097U, // EE_VMULAS_S16_ACCX_LD_XP_QUP_P + 69286475U, // EE_VMULAS_S16_ACCX_P + 536946645U, // EE_VMULAS_S16_QACC_LDBC_INCP_P + 536949345U, // EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P + 1073819756U, // EE_VMULAS_S16_QACC_LD_IP_P + 1073820435U, // EE_VMULAS_S16_QACC_LD_IP_QUP_P + 79782U, // EE_VMULAS_S16_QACC_LD_XP_P + 78935U, // EE_VMULAS_S16_QACC_LD_XP_QUP_P + 69280768U, // EE_VMULAS_S16_QACC_P + 1073820003U, // EE_VMULAS_S8_ACCX_LD_IP_P + 1073820679U, // EE_VMULAS_S8_ACCX_LD_IP_QUP_P + 80029U, // EE_VMULAS_S8_ACCX_LD_XP_P + 79179U, // EE_VMULAS_S8_ACCX_LD_XP_QUP_P + 69286537U, // EE_VMULAS_S8_ACCX_P + 536946727U, // EE_VMULAS_S8_QACC_LDBC_INCP_P + 536949435U, // EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P + 1073819830U, // EE_VMULAS_S8_QACC_LD_IP_P + 1073820517U, // EE_VMULAS_S8_QACC_LD_IP_QUP_P + 79856U, // EE_VMULAS_S8_QACC_LD_XP_P + 79017U, // EE_VMULAS_S8_QACC_LD_XP_QUP_P + 69280946U, // EE_VMULAS_S8_QACC_P + 1073819966U, // EE_VMULAS_U16_ACCX_LD_IP_P + 1073820638U, // EE_VMULAS_U16_ACCX_LD_IP_QUP_P + 79992U, // EE_VMULAS_U16_ACCX_LD_XP_P + 79138U, // EE_VMULAS_U16_ACCX_LD_XP_QUP_P + 69286506U, // EE_VMULAS_U16_ACCX_P + 536946686U, // EE_VMULAS_U16_QACC_LDBC_INCP_P + 536949390U, // EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P + 1073819793U, // EE_VMULAS_U16_QACC_LD_IP_P + 1073820476U, // EE_VMULAS_U16_QACC_LD_IP_QUP_P + 79819U, // EE_VMULAS_U16_QACC_LD_XP_P + 78976U, // EE_VMULAS_U16_QACC_LD_XP_QUP_P + 69280827U, // EE_VMULAS_U16_QACC_P + 1073820039U, // EE_VMULAS_U8_ACCX_LD_IP_P + 1073820719U, // EE_VMULAS_U8_ACCX_LD_IP_QUP_P + 80065U, // EE_VMULAS_U8_ACCX_LD_XP_P + 79219U, // EE_VMULAS_U8_ACCX_LD_XP_QUP_P + 69286567U, // EE_VMULAS_U8_ACCX_P + 536946767U, // EE_VMULAS_U8_QACC_LDBC_INCP_P + 536949479U, // EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P + 1073819866U, // EE_VMULAS_U8_QACC_LD_IP_P + 1073820557U, // EE_VMULAS_U8_QACC_LD_IP_QUP_P + 79892U, // EE_VMULAS_U8_QACC_LD_XP_P + 79057U, // EE_VMULAS_U8_QACC_LD_XP_QUP_P + 69281003U, // EE_VMULAS_U8_QACC_P + 536946969U, // EE_VMUL_S16_LD_INCP_P + 539041841U, // EE_VMUL_S16_P + 536947663U, // EE_VMUL_S16_ST_INCP_P + 536947198U, // EE_VMUL_S8_LD_INCP_P + 539042462U, // EE_VMUL_S8_P + 536947924U, // EE_VMUL_S8_ST_INCP_P + 536947166U, // EE_VMUL_U16_LD_INCP_P + 539042095U, // EE_VMUL_U16_P + 536947860U, // EE_VMUL_U16_ST_INCP_P + 536947355U, // EE_VMUL_U8_LD_INCP_P + 539042706U, // EE_VMUL_U8_P + 536948081U, // EE_VMUL_U8_ST_INCP_P + 539042020U, // EE_VPRELU_S16_P + 539042634U, // EE_VPRELU_S8_P + 73982U, // EE_VRELU_S16_P + 74595U, // EE_VRELU_S8_P + 69278801U, // EE_VSL_32_P + 536947386U, // EE_VSMULAS_S16_QACC_LD_INCP_P + 1612784608U, // EE_VSMULAS_S16_QACC_P + 536947426U, // EE_VSMULAS_S8_QACC_LD_INCP_P + 2686526611U, // EE_VSMULAS_S8_QACC_P + 69279057U, // EE_VSR_32_P + 1610690616U, // EE_VST_128_IP_P + 79696U, // EE_VST_128_XP_P + 536948348U, // EE_VST_H_64_IP_P + 79388U, // EE_VST_H_64_XP_P + 536948402U, // EE_VST_L_64_IP_P + 79442U, // EE_VST_L_64_XP_P + 536947033U, // EE_VSUBS_S16_LD_INCP_P + 539041916U, // EE_VSUBS_S16_P + 536947727U, // EE_VSUBS_S16_ST_INCP_P + 536946839U, // EE_VSUBS_S32_LD_INCP_P + 539041227U, // EE_VSUBS_S32_P + 536947497U, // EE_VSUBS_S32_ST_INCP_P + 536947260U, // EE_VSUBS_S8_LD_INCP_P + 539042534U, // EE_VSUBS_S8_P + 536947986U, // EE_VSUBS_S8_ST_INCP_P + 69279597U, // EE_VUNZIP_16_P + 69278916U, // EE_VUNZIP_32_P + 69280276U, // EE_VUNZIP_8_P + 69279622U, // EE_VZIP_16_P + 69278941U, // EE_VZIP_32_P + 69280300U, // EE_VZIP_8_P + 539048432U, // EE_XORQ_P + 30622U, // EE_ZERO_ACCX_P + 30599U, // EE_ZERO_QACC_P + 604595U, // EE_ZERO_Q_P + 50510U, // EXTUI_BR2_P + 55748U, // EXTUI_BR4_P + 61533U, // EXTUI_BR_P + 10541699U, // L8I_P + 67183908U, // LDDEC_P + 67184158U, // LDINC_P + 12644456U, // LOOPBR + 67164961U, // LOOPDEC + 122623U, // LOOPEND + 67171337U, // LOOPINIT + 12645415U, // LOOPSTART + 67158791U, // MOVBA2_P + 55965U, // MOVBA2_P2 + 67164603U, // MOVBA4_P + 55739U, // MOVBA4_P2 + 67164829U, // MOVBA_P + 55965U, // MOVBA_P2 + 536945974U, // MULA_DA_HH_LDDEC_P + 536946224U, // MULA_DA_HH_LDINC_P + 536946090U, // MULA_DA_HL_LDDEC_P + 536946340U, // MULA_DA_HL_LDINC_P + 536946032U, // MULA_DA_LH_LDDEC_P + 536946282U, // MULA_DA_LH_LDINC_P + 536946148U, // MULA_DA_LL_LDDEC_P + 536946398U, // MULA_DA_LL_LDINC_P + 536946003U, // MULA_DD_HH_LDDEC_P + 536946253U, // MULA_DD_HH_LDINC_P + 536946119U, // MULA_DD_HL_LDDEC_P + 536946369U, // MULA_DD_HL_LDINC_P + 536946061U, // MULA_DD_LH_LDDEC_P + 536946311U, // MULA_DD_LH_LDINC_P + 536946177U, // MULA_DD_LL_LDDEC_P + 536946427U, // MULA_DD_LL_LDINC_P + 10545657U, // RESTORE_BOOL + 62415U, // SELECT + 60408U, // SELECT_CC_FP_FP + 62484U, // SELECT_CC_FP_INT + 60426U, // SELECT_CC_INT_FP + 61523U, // SLLI_BR_P + 55947U, // SLL_P + 10545672U, // SPILL_BOOL + 55930U, // SRA_P + 55956U, // SRL_P + 567064U, // WSR_ACCHI_P + 567108U, // WSR_ACCLO_P + 564108U, // WSR_M0_P + 564146U, // WSR_M1_P + 564811U, // WSR_M2_P + 564849U, // WSR_M3_P + 567086U, // XSR_ACCHI_P + 567130U, // XSR_ACCLO_P + 564127U, // XSR_M0_P + 564165U, // XSR_M1_P + 564830U, // XSR_M2_P + 564868U, // XSR_M3_P + 69286424U, // mv_QR_P + 67143192U, // ABS + 67143089U, // ABS_S + 32973U, // ADD + 81921390U, // ADDEXPM_S + 81921424U, // ADDEXP_S + 536904286U, // ADDI + 2147517513U, // ADDI_N + 2684387971U, // ADDMI + 32818U, // ADDX2 + 32839U, // ADDX4 + 32874U, // ADDX8 + 33840U, // ADD_N + 34078U, // ADD_S + 67170934U, // AE_ABS16S + 67170682U, // AE_ABS24S + 67158740U, // AE_ABS32 + 67170586U, // AE_ABS32S + 67164552U, // AE_ABS64 + 67170811U, // AE_ABS64S + 55858U, // AE_ADD16 + 62036U, // AE_ADD16S + 61772U, // AE_ADD24S + 49749U, // AE_ADD32 + 61662U, // AE_ADD32S + 58299U, // AE_ADD32_HL_LH + 55561U, // AE_ADD64 + 61863U, // AE_ADD64S + 49679U, // AE_ADDBRBA32 + 49736U, // AE_ADDSUB32 + 61648U, // AE_ADDSUB32S + 57070U, // AE_AND + 67156887U, // AE_CVT32X2F16_10 + 67158414U, // AE_CVT32X2F16_32 + 67158508U, // AE_CVT48A32 + 67158495U, // AE_CVT64A32 + 67166072U, // AE_CVT64F32_H + 67166234U, // AE_CVTA32F24S_H + 67167740U, // AE_CVTA32F24S_L + 67170462U, // AE_CVTQ56A32S + 67166217U, // AE_CVTQ56P32S_H + 67167723U, // AE_CVTQ56P32S_L + 81943284U, // AE_DB + 16934148U, // AE_DBI + 16931818U, // AE_DBI_IC + 16936311U, // AE_DBI_IP + 81943469U, // AE_DB_IC + 81947962U, // AE_DB_IP + 81944411U, // AE_DIV64D32_H + 81945919U, // AE_DIV64D32_L + 55888U, // AE_EQ16 + 49834U, // AE_EQ32 + 55657U, // AE_EQ64 + 3221284048U, // AE_L16M_I + 3772839029U, // AE_L16M_IU + 62944U, // AE_L16M_X + 14737024U, // AE_L16M_XC + 14742723U, // AE_L16M_XU + 536929462U, // AE_L16X2M_I + 1088484441U, // AE_L16X2M_IU + 62918U, // AE_L16X2M_X + 14736996U, // AE_L16X2M_XC + 14742695U, // AE_L16X2M_XU + 1610671190U, // AE_L16X4_I + 2162224405U, // AE_L16X4_IP + 81845463U, // AE_L16X4_RIC + 81850053U, // AE_L16X4_RIP + 62822U, // AE_L16X4_X + 14736892U, // AE_L16X4_XC + 14741362U, // AE_L16X4_XP + 3221283950U, // AE_L16_I + 3772837167U, // AE_L16_IP + 62846U, // AE_L16_X + 14736918U, // AE_L16_XC + 14741388U, // AE_L16_XP + 536929273U, // AE_L32F24_I + 1088482451U, // AE_L32F24_IP + 62759U, // AE_L32F24_X + 14736824U, // AE_L32F24_XC + 14741294U, // AE_L32F24_XP + 536929440U, // AE_L32M_I + 1088484417U, // AE_L32M_IU + 62896U, // AE_L32M_X + 14736972U, // AE_L32M_XC + 14742671U, // AE_L32M_XU + 1610671110U, // AE_L32X2F24_I + 2162224323U, // AE_L32X2F24_IP + 81845399U, // AE_L32X2F24_RIC + 81849989U, // AE_L32X2F24_RIP + 62772U, // AE_L32X2F24_X + 14736838U, // AE_L32X2F24_XC + 14741308U, // AE_L32X2F24_XP + 1610671073U, // AE_L32X2_I + 2162224209U, // AE_L32X2_IP + 81845292U, // AE_L32X2_RIC + 81849882U, // AE_L32X2_RIP + 62735U, // AE_L32X2_X + 14736798U, // AE_L32X2_XC + 14741268U, // AE_L32X2_XP + 536929239U, // AE_L32_I + 1088482346U, // AE_L32_IP + 62725U, // AE_L32_X + 14736787U, // AE_L32_XC + 14741257U, // AE_L32_XP + 1610671140U, // AE_L64_I + 2699095267U, // AE_L64_IP + 62802U, // AE_L64_X + 14736870U, // AE_L64_XC + 14741340U, // AE_L64_XP + 81845555U, // AE_LA16X4NEG_PC + 81845621U, // AE_LA16X4POS_PC + 3374373777U, // AE_LA16X4_IC + 3374378233U, // AE_LA16X4_IP + 3374374073U, // AE_LA16X4_RIC + 3374378663U, // AE_LA16X4_RIP + 81845540U, // AE_LA24NEG_PC + 81845606U, // AE_LA24POS_PC + 81845523U, // AE_LA24X2NEG_PC + 81845589U, // AE_LA24X2POS_PC + 3374373703U, // AE_LA24X2_IC + 3374378091U, // AE_LA24X2_IP + 3374373960U, // AE_LA24X2_RIC + 3374378550U, // AE_LA24X2_RIP + 3374373731U, // AE_LA24_IC + 3374378119U, // AE_LA24_IP + 3374373990U, // AE_LA24_RIC + 3374378580U, // AE_LA24_RIP + 3374373743U, // AE_LA32X2F24_IC + 3374378145U, // AE_LA32X2F24_IP + 3374374003U, // AE_LA32X2F24_RIC + 3374378593U, // AE_LA32X2F24_RIP + 81845506U, // AE_LA32X2NEG_PC + 81845572U, // AE_LA32X2POS_PC + 3374373675U, // AE_LA32X2_IC + 3374378037U, // AE_LA32X2_IP + 3374373902U, // AE_LA32X2_RIC + 3374378492U, // AE_LA32X2_RIP + 67170032U, // AE_LA64_PP + 1610671150U, // AE_LALIGN64_I + 67164923U, // AE_LB + 21030156U, // AE_LBI + 58679U, // AE_LBK + 3758155036U, // AE_LBKI + 67171066U, // AE_LBS + 21030181U, // AE_LBSI + 55868U, // AE_LE16 + 49772U, // AE_LE32 + 55571U, // AE_LE64 + 55897U, // AE_LT16 + 49897U, // AE_LT32 + 55709U, // AE_LT64 + 49917U, // AE_MAX32 + 55729U, // AE_MAX64 + 61747U, // AE_MAXABS32S + 61972U, // AE_MAXABS64S + 49824U, // AE_MIN32 + 55647U, // AE_MIN64 + 61733U, // AE_MINABS32S + 61958U, // AE_MINABS64S + 67171535U, // AE_MOV + 67156701U, // AE_MOVAD16_0 + 67157689U, // AE_MOVAD16_1 + 67158151U, // AE_MOVAD16_2 + 67163910U, // AE_MOVAD16_3 + 67166058U, // AE_MOVAD32_H + 67167566U, // AE_MOVAD32_L + 67169101U, // AE_MOVALIGN + 67164700U, // AE_MOVDA16 + 55032U, // AE_MOVDA16X2 + 67158557U, // AE_MOVDA32 + 54910U, // AE_MOVDA32X2 + 14834141U, // AE_MOVF16X4 + 14833292U, // AE_MOVF32X2 + 14833948U, // AE_MOVF64 + 23127342U, // AE_MOVI + 14834191U, // AE_MOVT16X4 + 14833346U, // AE_MOVT32X2 + 14834086U, // AE_MOVT64 + 55786U, // AE_MUL16X4 + 59868U, // AE_MUL32U_LL + 48289U, // AE_MUL32X16_H0 + 50765U, // AE_MUL32X16_H0_S2 + 49059U, // AE_MUL32X16_H1 + 51423U, // AE_MUL32X16_H1_S2 + 50006U, // AE_MUL32X16_H2 + 51973U, // AE_MUL32X16_H2_S2 + 55180U, // AE_MUL32X16_H3 + 52681U, // AE_MUL32X16_H3_S2 + 48760U, // AE_MUL32X16_L0 + 51302U, // AE_MUL32X16_L0_S2 + 49254U, // AE_MUL32X16_L1 + 51648U, // AE_MUL32X16_L1_S2 + 50477U, // AE_MUL32X16_L2 + 52510U, // AE_MUL32X16_L2_S2 + 55375U, // AE_MUL32X16_L3 + 52906U, // AE_MUL32X16_L3_S2 + 57575U, // AE_MUL32_HH + 57824U, // AE_MUL32_LH + 59298U, // AE_MUL32_LL + 54303U, // AE_MUL32_LL_S2 + 25352656U, // AE_MULA16X4 + 14838221U, // AE_MULA32U_LL + 14826587U, // AE_MULA32X16_H0 + 14829051U, // AE_MULA32X16_H0_S2 + 14827357U, // AE_MULA32X16_H1 + 14829709U, // AE_MULA32X16_H1_S2 + 14828304U, // AE_MULA32X16_H2 + 14830259U, // AE_MULA32X16_H2_S2 + 14833478U, // AE_MULA32X16_H3 + 14830967U, // AE_MULA32X16_H3_S2 + 14827058U, // AE_MULA32X16_L0 + 14829588U, // AE_MULA32X16_L0_S2 + 14827552U, // AE_MULA32X16_L1 + 14829934U, // AE_MULA32X16_L1_S2 + 14828775U, // AE_MULA32X16_L2 + 14830796U, // AE_MULA32X16_L2_S2 + 14833673U, // AE_MULA32X16_L3 + 14831192U, // AE_MULA32X16_L3_S2 + 14835929U, // AE_MULA32_HH + 14836178U, // AE_MULA32_LH + 14837652U, // AE_MULA32_LL + 14832654U, // AE_MULA32_LL_S2 + 14837693U, // AE_MULAAD24_HH_LL + 14832687U, // AE_MULAAD24_HH_LL_S2 + 14836219U, // AE_MULAAD24_HL_LH + 14831736U, // AE_MULAAD24_HL_LH_S2 + 14827460U, // AE_MULAAD32X16_H0_L1 + 14829830U, // AE_MULAAD32X16_H0_L1_S2 + 14826690U, // AE_MULAAD32X16_H1_L0 + 14829172U, // AE_MULAAD32X16_H1_L0_S2 + 14833581U, // AE_MULAAD32X16_H2_L3 + 14831088U, // AE_MULAAD32X16_H2_L3_S2 + 14828407U, // AE_MULAAD32X16_H3_L2 + 14830380U, // AE_MULAAD32X16_H3_L2_S2 + 14826282U, // AE_MULAAFD16SS_11_00 + 14828949U, // AE_MULAAFD16SS_11_00_S2 + 14827669U, // AE_MULAAFD16SS_13_02 + 14830055U, // AE_MULAAFD16SS_13_02_S2 + 14827809U, // AE_MULAAFD16SS_33_22 + 14830157U, // AE_MULAAFD16SS_33_22_S2 + 14837771U, // AE_MULAAFD24_HH_LL + 14832777U, // AE_MULAAFD24_HH_LL_S2 + 14836258U, // AE_MULAAFD24_HL_LH + 14831781U, // AE_MULAAFD24_HL_LH_S2 + 14827505U, // AE_MULAAFD32X16_H0_L1 + 14829881U, // AE_MULAAFD32X16_H0_L1_S2 + 14826780U, // AE_MULAAFD32X16_H1_L0 + 14829274U, // AE_MULAAFD32X16_H1_L0_S2 + 14833626U, // AE_MULAAFD32X16_H2_L3 + 14831139U, // AE_MULAAFD32X16_H2_L3_S2 + 14828497U, // AE_MULAAFD32X16_H3_L2 + 14830482U, // AE_MULAAFD32X16_H3_L2_S2 + 14833776U, // AE_MULAC24 + 14835647U, // AE_MULAC32X16_H + 14837153U, // AE_MULAC32X16_L + 14826232U, // AE_MULAF16SS_00 + 14828890U, // AE_MULAF16SS_00_S2 + 14826409U, // AE_MULAF16SS_10 + 14827207U, // AE_MULAF16SS_11 + 14826459U, // AE_MULAF16SS_20 + 14827257U, // AE_MULAF16SS_21 + 14827759U, // AE_MULAF16SS_22 + 14826509U, // AE_MULAF16SS_30 + 14827307U, // AE_MULAF16SS_31 + 14827936U, // AE_MULAF16SS_32 + 14833428U, // AE_MULAF16SS_33 + 25359182U, // AE_MULAF16X4SS + 14835970U, // AE_MULAF32R_HH + 14836459U, // AE_MULAF32R_LH + 14838013U, // AE_MULAF32R_LL + 14833055U, // AE_MULAF32R_LL_S2 + 14836066U, // AE_MULAF32S_HH + 14836555U, // AE_MULAF32S_LH + 14838109U, // AE_MULAF32S_LL + 14833111U, // AE_MULAF32S_LL_S2 + 14826604U, // AE_MULAF32X16_H0 + 14829071U, // AE_MULAF32X16_H0_S2 + 14827374U, // AE_MULAF32X16_H1 + 14829729U, // AE_MULAF32X16_H1_S2 + 14828321U, // AE_MULAF32X16_H2 + 14830279U, // AE_MULAF32X16_H2_S2 + 14833495U, // AE_MULAF32X16_H3 + 14830987U, // AE_MULAF32X16_H3_S2 + 14827075U, // AE_MULAF32X16_L0 + 14829608U, // AE_MULAF32X16_L0_S2 + 14827569U, // AE_MULAF32X16_L1 + 14829954U, // AE_MULAF32X16_L1_S2 + 14828792U, // AE_MULAF32X16_L2 + 14830816U, // AE_MULAF32X16_L2_S2 + 14833690U, // AE_MULAF32X16_L3 + 14831212U, // AE_MULAF32X16_L3_S2 + 14837299U, // AE_MULAF48Q32SP16S_L + 14832225U, // AE_MULAF48Q32SP16S_L_S2 + 14837538U, // AE_MULAF48Q32SP16U_L + 14832515U, // AE_MULAF48Q32SP16U_L_S2 + 14834391U, // AE_MULAFC24RA + 14835823U, // AE_MULAFC32X16RAS_H + 14837432U, // AE_MULAFC32X16RAS_L + 25354208U, // AE_MULAFD24X2_FIR_H + 25355714U, // AE_MULAFD24X2_FIR_L + 25354545U, // AE_MULAFD32X16X2_FIR_HH + 25356131U, // AE_MULAFD32X16X2_FIR_HL + 25355034U, // AE_MULAFD32X16X2_FIR_LH + 25356588U, // AE_MULAFD32X16X2_FIR_LL + 14839776U, // AE_MULAFP24X2R + 14834341U, // AE_MULAFP24X2RA + 14831313U, // AE_MULAFP24X2RA_S2 + 14833222U, // AE_MULAFP24X2R_S2 + 14835755U, // AE_MULAFP32X16X2RAS_H + 14831511U, // AE_MULAFP32X16X2RAS_H_S2 + 14837364U, // AE_MULAFP32X16X2RAS_L + 14832364U, // AE_MULAFP32X16X2RAS_L_S2 + 14835864U, // AE_MULAFP32X16X2RS_H + 14831588U, // AE_MULAFP32X16X2RS_H_S2 + 14837473U, // AE_MULAFP32X16X2RS_L + 14832441U, // AE_MULAFP32X16X2RS_L_S2 + 14840500U, // AE_MULAFP32X2RAS + 14840591U, // AE_MULAFP32X2RS + 14831372U, // AE_MULAFQ32SP24S_H_S2 + 14832086U, // AE_MULAFQ32SP24S_L_S2 + 14833359U, // AE_MULAP24X2 + 14830917U, // AE_MULAP24X2_S2 + 14835591U, // AE_MULAP32X16X2_H + 14837097U, // AE_MULAP32X16X2_L + 14833305U, // AE_MULAP32X2 + 14832299U, // AE_MULAQ32SP16S_L_S2 + 14832589U, // AE_MULAQ32SP16U_L_S2 + 14831417U, // AE_MULARFQ32SP24S_H_S2 + 14832131U, // AE_MULARFQ32SP24S_L_S2 + 14836113U, // AE_MULAS32F48P16S_HH + 14831662U, // AE_MULAS32F48P16S_HH_S2 + 14836602U, // AE_MULAS32F48P16S_LH + 14832012U, // AE_MULAS32F48P16S_LH_S2 + 14838156U, // AE_MULAS32F48P16S_LL + 14833148U, // AE_MULAS32F48P16S_LL_S2 + 14837935U, // AE_MULASD24_HH_LL + 14832965U, // AE_MULASD24_HH_LL_S2 + 14836381U, // AE_MULASD24_HL_LH + 14831922U, // AE_MULASD24_HL_LH_S2 + 14826968U, // AE_MULASD32X16_H1_L0 + 14829486U, // AE_MULASD32X16_H1_L0_S2 + 14828685U, // AE_MULASD32X16_H3_L2 + 14830694U, // AE_MULASD32X16_H3_L2_S2 + 14837853U, // AE_MULASFD24_HH_LL + 14832871U, // AE_MULASFD24_HH_LL_S2 + 14836299U, // AE_MULASFD24_HL_LH + 14831828U, // AE_MULASFD24_HL_LH_S2 + 14826874U, // AE_MULASFD32X16_H1_L0 + 14829380U, // AE_MULASFD32X16_H1_L0_S2 + 14828591U, // AE_MULASFD32X16_H3_L2 + 14830588U, // AE_MULASFD32X16_H3_L2_S2 + 55420U, // AE_MULC24 + 57296U, // AE_MULC32X16_H + 58802U, // AE_MULC32X16_L + 47881U, // AE_MULF16SS_00 + 50542U, // AE_MULF16SS_00_S2 + 48058U, // AE_MULF16SS_10 + 48856U, // AE_MULF16SS_11 + 48108U, // AE_MULF16SS_20 + 48906U, // AE_MULF16SS_21 + 49408U, // AE_MULF16SS_22 + 48158U, // AE_MULF16SS_30 + 48956U, // AE_MULF16SS_31 + 49585U, // AE_MULF16SS_32 + 55077U, // AE_MULF16SS_33 + 62302U, // AE_MULF16X4SS + 57618U, // AE_MULF32R_HH + 58107U, // AE_MULF32R_LH + 59661U, // AE_MULF32R_LL + 54706U, // AE_MULF32R_LL_S2 + 57714U, // AE_MULF32S_HH + 58203U, // AE_MULF32S_LH + 59757U, // AE_MULF32S_LL + 54762U, // AE_MULF32S_LL_S2 + 48254U, // AE_MULF32X16_H0 + 50724U, // AE_MULF32X16_H0_S2 + 49024U, // AE_MULF32X16_H1 + 51382U, // AE_MULF32X16_H1_S2 + 49971U, // AE_MULF32X16_H2 + 51932U, // AE_MULF32X16_H2_S2 + 55145U, // AE_MULF32X16_H3 + 52640U, // AE_MULF32X16_H3_S2 + 48725U, // AE_MULF32X16_L0 + 51261U, // AE_MULF32X16_L0_S2 + 49219U, // AE_MULF32X16_L1 + 51607U, // AE_MULF32X16_L1_S2 + 50442U, // AE_MULF32X16_L2 + 52469U, // AE_MULF32X16_L2_S2 + 55340U, // AE_MULF32X16_L3 + 52865U, // AE_MULF32X16_L3_S2 + 58953U, // AE_MULF48Q32SP16S_L + 53882U, // AE_MULF48Q32SP16S_L_S2 + 59192U, // AE_MULF48Q32SP16U_L + 54172U, // AE_MULF48Q32SP16U_L_S2 + 56038U, // AE_MULFC24RA + 57476U, // AE_MULFC32X16RAS_H + 59085U, // AE_MULFC32X16RAS_L + 57333U, // AE_MULFD24X2_FIR_H + 58839U, // AE_MULFD24X2_FIR_L + 57674U, // AE_MULFD32X16X2_FIR_HH + 59260U, // AE_MULFD32X16X2_FIR_HL + 58163U, // AE_MULFD32X16X2_FIR_LH + 59717U, // AE_MULFD32X16X2_FIR_LL + 62185U, // AE_MULFP16X4RAS + 61986U, // AE_MULFP16X4S + 61424U, // AE_MULFP24X2R + 55990U, // AE_MULFP24X2RA + 52965U, // AE_MULFP24X2RA_S2 + 54873U, // AE_MULFP24X2R_S2 + 57410U, // AE_MULFP32X16X2RAS_H + 53169U, // AE_MULFP32X16X2RAS_H_S2 + 59019U, // AE_MULFP32X16X2RAS_L + 54022U, // AE_MULFP32X16X2RAS_L_S2 + 57518U, // AE_MULFP32X16X2RS_H + 53245U, // AE_MULFP32X16X2RS_H_S2 + 59127U, // AE_MULFP32X16X2RS_L + 54098U, // AE_MULFP32X16X2RS_L_S2 + 62150U, // AE_MULFP32X2RAS + 62240U, // AE_MULFP32X2RS + 53027U, // AE_MULFQ32SP24S_H_S2 + 53741U, // AE_MULFQ32SP24S_L_S2 + 55005U, // AE_MULP24X2 + 52566U, // AE_MULP24X2_S2 + 57242U, // AE_MULP32X16X2_H + 58748U, // AE_MULP32X16X2_L + 54951U, // AE_MULP32X2 + 53953U, // AE_MULQ32SP16S_L_S2 + 54243U, // AE_MULQ32SP16U_L_S2 + 53073U, // AE_MULRFQ32SP24S_H_S2 + 53787U, // AE_MULRFQ32SP24S_L_S2 + 25352694U, // AE_MULS16X4 + 57767U, // AE_MULS32F48P16S_HH + 53319U, // AE_MULS32F48P16S_HH_S2 + 58256U, // AE_MULS32F48P16S_LH + 53669U, // AE_MULS32F48P16S_LH_S2 + 59810U, // AE_MULS32F48P16S_LL + 54805U, // AE_MULS32F48P16S_LL_S2 + 14838250U, // AE_MULS32U_LL + 14826673U, // AE_MULS32X16_H0 + 14829152U, // AE_MULS32X16_H0_S2 + 14827443U, // AE_MULS32X16_H1 + 14829810U, // AE_MULS32X16_H1_S2 + 14828390U, // AE_MULS32X16_H2 + 14830360U, // AE_MULS32X16_H2_S2 + 14833564U, // AE_MULS32X16_H3 + 14831068U, // AE_MULS32X16_H3_S2 + 14827144U, // AE_MULS32X16_L0 + 14829689U, // AE_MULS32X16_L0_S2 + 14827638U, // AE_MULS32X16_L1 + 14830035U, // AE_MULS32X16_L1_S2 + 14828861U, // AE_MULS32X16_L2 + 14830897U, // AE_MULS32X16_L2_S2 + 14833759U, // AE_MULS32X16_L3 + 14831293U, // AE_MULS32X16_L3_S2 + 14835956U, // AE_MULS32_HH + 14836205U, // AE_MULS32_LH + 14837679U, // AE_MULS32_LL + 14837732U, // AE_MULSAD24_HH_LL + 14832732U, // AE_MULSAD24_HH_LL_S2 + 14826735U, // AE_MULSAD32X16_H1_L0 + 14829223U, // AE_MULSAD32X16_H1_L0_S2 + 14828452U, // AE_MULSAD32X16_H3_L2 + 14830431U, // AE_MULSAD32X16_H3_L2_S2 + 14837812U, // AE_MULSAFD24_HH_LL + 14832824U, // AE_MULSAFD24_HH_LL_S2 + 14826827U, // AE_MULSAFD32X16_H1_L0 + 14829327U, // AE_MULSAFD32X16_H1_L0_S2 + 14828544U, // AE_MULSAFD32X16_H3_L2 + 14830535U, // AE_MULSAFD32X16_H3_L2_S2 + 14826265U, // AE_MULSF16SS_00 + 14828929U, // AE_MULSF16SS_00_S2 + 14826442U, // AE_MULSF16SS_10 + 14827240U, // AE_MULSF16SS_11 + 14826492U, // AE_MULSF16SS_20 + 14827290U, // AE_MULSF16SS_21 + 14827792U, // AE_MULSF16SS_22 + 14826542U, // AE_MULSF16SS_30 + 14827340U, // AE_MULSF16SS_31 + 14827969U, // AE_MULSF16SS_32 + 14833461U, // AE_MULSF16SS_33 + 25359213U, // AE_MULSF16X4SS + 14836001U, // AE_MULSF32R_HH + 14836490U, // AE_MULSF32R_LH + 14838044U, // AE_MULSF32R_LL + 14833092U, // AE_MULSF32R_LL_S2 + 14836097U, // AE_MULSF32S_HH + 14836586U, // AE_MULSF32S_LH + 14838140U, // AE_MULSF32S_LL + 14826639U, // AE_MULSF32X16_H0 + 14829112U, // AE_MULSF32X16_H0_S2 + 14827409U, // AE_MULSF32X16_H1 + 14829770U, // AE_MULSF32X16_H1_S2 + 14828356U, // AE_MULSF32X16_H2 + 14830320U, // AE_MULSF32X16_H2_S2 + 14833530U, // AE_MULSF32X16_H3 + 14831028U, // AE_MULSF32X16_H3_S2 + 14827110U, // AE_MULSF32X16_L0 + 14829649U, // AE_MULSF32X16_L0_S2 + 14827604U, // AE_MULSF32X16_L1 + 14829995U, // AE_MULSF32X16_L1_S2 + 14828827U, // AE_MULSF32X16_L2 + 14830857U, // AE_MULSF32X16_L2_S2 + 14833725U, // AE_MULSF32X16_L3 + 14831253U, // AE_MULSF32X16_L3_S2 + 14837342U, // AE_MULSF48Q32SP16S_L + 14832274U, // AE_MULSF48Q32SP16S_L_S2 + 14837581U, // AE_MULSF48Q32SP16U_L + 14832564U, // AE_MULSF48Q32SP16U_L_S2 + 14839807U, // AE_MULSFP24X2R + 14834374U, // AE_MULSFP24X2RA + 14831352U, // AE_MULSFP24X2RA_S2 + 14833259U, // AE_MULSFP24X2R_S2 + 14835800U, // AE_MULSFP32X16X2RAS_H + 14831562U, // AE_MULSFP32X16X2RAS_H_S2 + 14837409U, // AE_MULSFP32X16X2RAS_L + 14832415U, // AE_MULSFP32X16X2RAS_L_S2 + 14835907U, // AE_MULSFP32X16X2RS_H + 14831637U, // AE_MULSFP32X16X2RS_H_S2 + 14837516U, // AE_MULSFP32X16X2RS_L + 14832490U, // AE_MULSFP32X16X2RS_L_S2 + 14840535U, // AE_MULSFP32X2RAS + 14840624U, // AE_MULSFP32X2RS + 14831488U, // AE_MULSFQ32SP24S_H_S2 + 14832202U, // AE_MULSFQ32SP24S_L_S2 + 14833386U, // AE_MULSP24X2 + 14830950U, // AE_MULSP24X2_S2 + 14835628U, // AE_MULSP32X16X2_H + 14837134U, // AE_MULSP32X16X2_L + 14833332U, // AE_MULSP32X2 + 14832342U, // AE_MULSQ32SP16S_L_S2 + 14832632U, // AE_MULSQ32SP16U_L_S2 + 14831464U, // AE_MULSRFQ32SP24S_H_S2 + 14832178U, // AE_MULSRFQ32SP24S_L_S2 + 14836156U, // AE_MULSS32F48P16S_HH + 14831711U, // AE_MULSS32F48P16S_HH_S2 + 14836645U, // AE_MULSS32F48P16S_LH + 14832061U, // AE_MULSS32F48P16S_LH_S2 + 14838199U, // AE_MULSS32F48P16S_LL + 14833197U, // AE_MULSS32F48P16S_LL_S2 + 14837974U, // AE_MULSSD24_HH_LL + 14833010U, // AE_MULSSD24_HH_LL_S2 + 14836420U, // AE_MULSSD24_HL_LH + 14831967U, // AE_MULSSD24_HL_LH_S2 + 14827013U, // AE_MULSSD32X16_H1_L0 + 14829537U, // AE_MULSSD32X16_H1_L0_S2 + 14828730U, // AE_MULSSD32X16_H3_L2 + 14830745U, // AE_MULSSD32X16_H3_L2_S2 + 14826327U, // AE_MULSSFD16SS_11_00 + 14829000U, // AE_MULSSFD16SS_11_00_S2 + 14827714U, // AE_MULSSFD16SS_13_02 + 14830106U, // AE_MULSSFD16SS_13_02_S2 + 14827854U, // AE_MULSSFD16SS_33_22 + 14830208U, // AE_MULSSFD16SS_33_22_S2 + 14837894U, // AE_MULSSFD24_HH_LL + 14832918U, // AE_MULSSFD24_HH_LL_S2 + 14836340U, // AE_MULSSFD24_HL_LH + 14831875U, // AE_MULSSFD24_HL_LH_S2 + 14826921U, // AE_MULSSFD32X16_H1_L0 + 14829433U, // AE_MULSSFD32X16_H1_L0_S2 + 14828638U, // AE_MULSSFD32X16_H3_L2 + 14830641U, // AE_MULSSFD32X16_H3_L2_S2 + 59344U, // AE_MULZAAD24_HH_LL + 54341U, // AE_MULZAAD24_HH_LL_S2 + 57870U, // AE_MULZAAD24_HL_LH + 53390U, // AE_MULZAAD24_HL_LH_S2 + 49114U, // AE_MULZAAD32X16_H0_L1 + 51487U, // AE_MULZAAD32X16_H0_L1_S2 + 48344U, // AE_MULZAAD32X16_H1_L0 + 50829U, // AE_MULZAAD32X16_H1_L0_S2 + 55235U, // AE_MULZAAD32X16_H2_L3 + 52745U, // AE_MULZAAD32X16_H2_L3_S2 + 50061U, // AE_MULZAAD32X16_H3_L2 + 52037U, // AE_MULZAAD32X16_H3_L2_S2 + 47936U, // AE_MULZAAFD16SS_11_00 + 50606U, // AE_MULZAAFD16SS_11_00_S2 + 49323U, // AE_MULZAAFD16SS_13_02 + 51712U, // AE_MULZAAFD16SS_13_02_S2 + 49463U, // AE_MULZAAFD16SS_33_22 + 51814U, // AE_MULZAAFD16SS_33_22_S2 + 59423U, // AE_MULZAAFD24_HH_LL + 54432U, // AE_MULZAAFD24_HH_LL_S2 + 57910U, // AE_MULZAAFD24_HL_LH + 53436U, // AE_MULZAAFD24_HL_LH_S2 + 49160U, // AE_MULZAAFD32X16_H0_L1 + 51539U, // AE_MULZAAFD32X16_H0_L1_S2 + 48435U, // AE_MULZAAFD32X16_H1_L0 + 50932U, // AE_MULZAAFD32X16_H1_L0_S2 + 55281U, // AE_MULZAAFD32X16_H2_L3 + 52797U, // AE_MULZAAFD32X16_H2_L3_S2 + 50152U, // AE_MULZAAFD32X16_H3_L2 + 52140U, // AE_MULZAAFD32X16_H3_L2_S2 + 59586U, // AE_MULZASD24_HH_LL + 54619U, // AE_MULZASD24_HH_LL_S2 + 58032U, // AE_MULZASD24_HL_LH + 53576U, // AE_MULZASD24_HL_LH_S2 + 48622U, // AE_MULZASD32X16_H1_L0 + 51143U, // AE_MULZASD32X16_H1_L0_S2 + 50339U, // AE_MULZASD32X16_H3_L2 + 52351U, // AE_MULZASD32X16_H3_L2_S2 + 59505U, // AE_MULZASFD24_HH_LL + 54526U, // AE_MULZASFD24_HH_LL_S2 + 57951U, // AE_MULZASFD24_HL_LH + 53483U, // AE_MULZASFD24_HL_LH_S2 + 48529U, // AE_MULZASFD32X16_H1_L0 + 51038U, // AE_MULZASFD32X16_H1_L0_S2 + 50246U, // AE_MULZASFD32X16_H3_L2 + 52246U, // AE_MULZASFD32X16_H3_L2_S2 + 59383U, // AE_MULZSAD24_HH_LL + 54386U, // AE_MULZSAD24_HH_LL_S2 + 48389U, // AE_MULZSAD32X16_H1_L0 + 50880U, // AE_MULZSAD32X16_H1_L0_S2 + 50106U, // AE_MULZSAD32X16_H3_L2 + 52088U, // AE_MULZSAD32X16_H3_L2_S2 + 59464U, // AE_MULZSAFD24_HH_LL + 54479U, // AE_MULZSAFD24_HH_LL_S2 + 48482U, // AE_MULZSAFD32X16_H1_L0 + 50985U, // AE_MULZSAFD32X16_H1_L0_S2 + 50199U, // AE_MULZSAFD32X16_H3_L2 + 52193U, // AE_MULZSAFD32X16_H3_L2_S2 + 59625U, // AE_MULZSSD24_HH_LL + 54664U, // AE_MULZSSD24_HH_LL_S2 + 58071U, // AE_MULZSSD24_HL_LH + 53621U, // AE_MULZSSD24_HL_LH_S2 + 48667U, // AE_MULZSSD32X16_H1_L0 + 51194U, // AE_MULZSSD32X16_H1_L0_S2 + 50384U, // AE_MULZSSD32X16_H3_L2 + 52402U, // AE_MULZSSD32X16_H3_L2_S2 + 47981U, // AE_MULZSSFD16SS_11_00 + 50657U, // AE_MULZSSFD16SS_11_00_S2 + 49368U, // AE_MULZSSFD16SS_13_02 + 51763U, // AE_MULZSSFD16SS_13_02_S2 + 49508U, // AE_MULZSSFD16SS_33_22 + 51865U, // AE_MULZSSFD16SS_33_22_S2 + 59546U, // AE_MULZSSFD24_HH_LL + 54573U, // AE_MULZSSFD24_HH_LL_S2 + 57992U, // AE_MULZSSFD24_HL_LH + 53530U, // AE_MULZSSFD24_HL_LH_S2 + 48576U, // AE_MULZSSFD32X16_H1_L0 + 51091U, // AE_MULZSSFD32X16_H1_L0_S2 + 50293U, // AE_MULZSSFD32X16_H3_L2 + 52299U, // AE_MULZSSFD32X16_H3_L2_S2 + 57078U, // AE_NAND + 67170911U, // AE_NEG16S + 67170647U, // AE_NEG24S + 67158645U, // AE_NEG32 + 67170551U, // AE_NEG32S + 67164455U, // AE_NEG64 + 67170776U, // AE_NEG64S + 67164405U, // AE_NSA64 + 67156715U, // AE_NSAZ16_0 + 67167580U, // AE_NSAZ32_L + 61553U, // AE_OR + 551704744U, // AE_PKSR24 + 551699123U, // AE_PKSR32 + 60052U, // AE_ROUND16X4F32SASYM + 60140U, // AE_ROUND16X4F32SSYM + 60118U, // AE_ROUND24X2F48SASYM + 60203U, // AE_ROUND24X2F48SSYM + 60096U, // AE_ROUND32X2F48SASYM + 60182U, // AE_ROUND32X2F48SSYM + 60074U, // AE_ROUND32X2F64SASYM + 60161U, // AE_ROUND32X2F64SSYM + 67168874U, // AE_ROUNDSP16F24ASYM + 67168811U, // AE_ROUNDSP16F24SYM + 59987U, // AE_ROUNDSP16Q48X2ASYM + 59925U, // AE_ROUNDSP16Q48X2SYM + 67168895U, // AE_ROUNDSQ32F48ASYM + 67168831U, // AE_ROUNDSQ32F48SYM + 3221283987U, // AE_S16M_L_I + 3772937267U, // AE_S16M_L_IU + 62883U, // AE_S16M_L_X + 14835262U, // AE_S16M_L_XC + 14840961U, // AE_S16M_L_XU + 536929475U, // AE_S16X2M_I + 1088582759U, // AE_S16X2M_IU + 62931U, // AE_S16X2M_X + 14835314U, // AE_S16X2M_XC + 14841013U, // AE_S16X2M_XU + 1610671202U, // AE_S16X4_I + 2162322722U, // AE_S16X4_IP + 81943781U, // AE_S16X4_RIC + 81948371U, // AE_S16X4_RIP + 62834U, // AE_S16X4_X + 14835209U, // AE_S16X4_XC + 14839679U, // AE_S16X4_XP + 3221283787U, // AE_S16_0_I + 3772935197U, // AE_S16_0_IP + 62713U, // AE_S16_0_X + 14835078U, // AE_S16_0_XC + 14839548U, // AE_S16_0_XP + 536929514U, // AE_S24RA64S_I + 1088581100U, // AE_S24RA64S_IP + 62970U, // AE_S24RA64S_X + 14835356U, // AE_S24RA64S_XC + 14839748U, // AE_S24RA64S_XP + 14839258U, // AE_S24X2RA64S_IP + 536929412U, // AE_S32F24_L_I + 1088581032U, // AE_S32F24_L_IP + 62868U, // AE_S32F24_L_X + 14835246U, // AE_S32F24_L_XC + 14839716U, // AE_S32F24_L_XP + 536929451U, // AE_S32M_I + 1088582733U, // AE_S32M_IU + 62907U, // AE_S32M_X + 14835288U, // AE_S32M_XC + 14840987U, // AE_S32M_XU + 536929499U, // AE_S32RA64S_I + 1088581048U, // AE_S32RA64S_IP + 62955U, // AE_S32RA64S_X + 14835340U, // AE_S32RA64S_XC + 14839732U, // AE_S32RA64S_XP + 1610671125U, // AE_S32X2F24_I + 2162322643U, // AE_S32X2F24_IP + 81943720U, // AE_S32X2F24_RIC + 81948310U, // AE_S32X2F24_RIP + 62787U, // AE_S32X2F24_X + 14835158U, // AE_S32X2F24_XC + 14839628U, // AE_S32X2F24_XP + 14839240U, // AE_S32X2RA64S_IP + 1610671085U, // AE_S32X2_I + 2162322526U, // AE_S32X2_IP + 81943610U, // AE_S32X2_RIC + 81948200U, // AE_S32X2_RIP + 62747U, // AE_S32X2_X + 14835115U, // AE_S32X2_XC + 14839585U, // AE_S32X2_XP + 536929400U, // AE_S32_L_I + 1088581005U, // AE_S32_L_IP + 62856U, // AE_S32_L_X + 14835233U, // AE_S32_L_XC + 14839703U, // AE_S32_L_XP + 1610671180U, // AE_S64_I + 2699193582U, // AE_S64_IP + 62812U, // AE_S64_X + 14835185U, // AE_S64_XC + 14839655U, // AE_S64_XP + 92461983U, // AE_SA16X4_IC + 92466439U, // AE_SA16X4_IP + 92462280U, // AE_SA16X4_RIC + 92466870U, // AE_SA16X4_RIP + 92461909U, // AE_SA24X2_IC + 92466297U, // AE_SA24X2_IP + 92462167U, // AE_SA24X2_RIC + 92466757U, // AE_SA24X2_RIP + 92462080U, // AE_SA24_L_IC + 92466586U, // AE_SA24_L_IP + 92462323U, // AE_SA24_L_RIC + 92466913U, // AE_SA24_L_RIP + 92461952U, // AE_SA32X2F24_IC + 92466354U, // AE_SA32X2F24_IP + 92462213U, // AE_SA32X2F24_RIC + 92466803U, // AE_SA32X2F24_RIP + 92461881U, // AE_SA32X2_IC + 92466243U, // AE_SA32X2_IP + 92462109U, // AE_SA32X2_RIC + 92466699U, // AE_SA32X2_RIP + 81947600U, // AE_SA64NEG_FP + 81947615U, // AE_SA64POS_FP + 1610671165U, // AE_SALIGN64_I + 55811U, // AE_SAT16X4 + 67170693U, // AE_SAT24S + 67170985U, // AE_SAT48S + 67170973U, // AE_SATQ56S + 81943298U, // AE_SB + 679763U, // AE_SBF + 678879U, // AE_SBF_IC + 683372U, // AE_SBF_IP + 1088578836U, // AE_SBI + 1088576501U, // AE_SBI_IC + 1088580994U, // AE_SBI_IP + 81943479U, // AE_SB_IC + 81947972U, // AE_SB_IP + 58617U, // AE_SEL16I + 60224U, // AE_SEL16I_N + 1610662642U, // AE_SEXT32 + 67156868U, // AE_SEXT32X2D16_10 + 67158395U, // AE_SEXT32X2D16_32 + 67158569U, // AE_SHA32 + 67169176U, // AE_SHORTSWAP + 62001U, // AE_SLAA16S + 49657U, // AE_SLAA32 + 61613U, // AE_SLAA32S + 55508U, // AE_SLAA64 + 61840U, // AE_SLAA64S + 55906U, // AE_SLAAQ56 + 2147545706U, // AE_SLAI16S + 2684409991U, // AE_SLAI24 + 2684416354U, // AE_SLAI24S + 2684404351U, // AE_SLAI32 + 2684416258U, // AE_SLAI32S + 3221281073U, // AE_SLAI64 + 3221287395U, // AE_SLAI64S + 3221287553U, // AE_SLAISQ56S + 67164339U, // AE_SLAS24 + 67170670U, // AE_SLAS24S + 67158718U, // AE_SLAS32 + 67170574U, // AE_SLAS32S + 67164530U, // AE_SLAS64 + 67170799U, // AE_SLAS64S + 67164782U, // AE_SLASQ56 + 67170959U, // AE_SLASSQ56S + 49618U, // AE_SRA64_32 + 62273U, // AE_SRAA16RS + 62013U, // AE_SRAA16S + 49668U, // AE_SRAA32 + 62210U, // AE_SRAA32RS + 61625U, // AE_SRAA32S + 55519U, // AE_SRAA64 + 2147539525U, // AE_SRAI16 + 2147545103U, // AE_SRAI16R + 2684410002U, // AE_SRAI24 + 2684404362U, // AE_SRAI32 + 2684415956U, // AE_SRAI32R + 3221281084U, // AE_SRAI64 + 67164350U, // AE_SRAS24 + 67158729U, // AE_SRAS32 + 67164541U, // AE_SRAS64 + 49715U, // AE_SRLA32 + 55530U, // AE_SRLA64 + 2684410013U, // AE_SRLI24 + 2684404373U, // AE_SRLI32 + 3221281095U, // AE_SRLI64 + 67164361U, // AE_SRLS24 + 67158750U, // AE_SRLS32 + 67164562U, // AE_SRLS64 + 55848U, // AE_SUB16 + 62025U, // AE_SUB16S + 61761U, // AE_SUB24S + 49726U, // AE_SUB32 + 61637U, // AE_SUB32S + 55551U, // AE_SUB64 + 61852U, // AE_SUB64S + 49759U, // AE_SUBADD32 + 61673U, // AE_SUBADD32S + 58893U, // AE_TRUNCA32F64S_L + 61874U, // AE_TRUNCA32X2F64S + 58912U, // AE_TRUNCI32F64S_L + 61893U, // AE_TRUNCI32X2F64S + 678665U, // AE_VLDL16C + 678849U, // AE_VLDL16C_IC + 683342U, // AE_VLDL16C_IP + 62391U, // AE_VLDL16T + 62367U, // AE_VLDL32T + 586750U, // AE_VLDSHT + 14742467U, // AE_VLEL16T + 14742443U, // AE_VLEL32T + 678677U, // AE_VLES16C + 678864U, // AE_VLES16C_IC + 683357U, // AE_VLES16C_IP + 61560U, // AE_XOR + 579922U, // AE_ZALIGN64 + 67141690U, // ALL4 + 67141725U, // ALL8 + 32978U, // AND + 32905U, // ANDB + 32941U, // ANDBC + 67141718U, // ANY4 + 67141753U, // ANY8 + 3758130190U, // BALL + 3758130915U, // BANY + 3758129320U, // BBC + 27296344U, // BBCI + 3758130717U, // BBS + 27296407U, // BBSI + 3758130339U, // BEQ + 29393546U, // BEQI + 12617493U, // BEQZ + 12615924U, // BF + 3758129379U, // BGE + 29393508U, // BGEI + 3758130840U, // BGEU + 31490753U, // BGEUI + 12617456U, // BGEZ + 3758130746U, // BLT + 29393582U, // BLTI + 3758130864U, // BLTU + 31490760U, // BLTUI + 12617516U, // BLTZ + 3758130196U, // BNALL + 3758129384U, // BNE + 29393514U, // BNEI + 12617470U, // BNEZ + 3758129389U, // BNONE + 33751776U, // BREAK + 722009U, // BREAK_N + 12617270U, // BT + 229387U, // CALL0 + 229402U, // CALL12 + 229433U, // CALL4 + 229468U, // CALL8 + 557074U, // CALLX0 + 557090U, // CALLX12 + 557134U, // CALLX4 + 557169U, // CALLX8 + 2147517791U, // CEIL_S + 1610647086U, // CLAMPS + 263767U, // CLR_BIT_GPIO_OUT + 33588688U, // CONST_S + 67142905U, // DIV0_S + 14812552U, // DIVN_S + 30504U, // DSYNC + 39625U, // EE_ANDQ + 81828640U, // EE_BITREV + 263764U, // EE_CLR_BIT_GPIO_OUT + 35367U, // EE_CMUL_S16 + 220237611U, // EE_CMUL_S16_LD_INCP + 537039119U, // EE_CMUL_S16_ST_INCP + 25202587U, // EE_FFT_AMS_S16_LD_INCP + 25204093U, // EE_FFT_AMS_S16_LD_INCP_UAUP + 25202192U, // EE_FFT_AMS_S16_LD_R32_DECP + 1347967U, // EE_FFT_AMS_S16_ST_INCP + 153131330U, // EE_FFT_CMUL_S16_LD_XP + 14817875U, // EE_FFT_CMUL_S16_ST_XP + 35349U, // EE_FFT_R2BF_S16 + 14717173U, // EE_FFT_R2BF_S16_ST_INCP + 1088556589U, // EE_FFT_VST_R32_DECP + 558185U, // EE_GET_GPIO_IN + 37804U, // EE_LDF_128_IP + 39186U, // EE_LDF_128_XP + 37575U, // EE_LDF_64_IP + 38957U, // EE_LDF_64_XP + 35787594U, // EE_LDQA_S16_128_IP + 81926320U, // EE_LDQA_S16_128_XP + 35787636U, // EE_LDQA_S8_128_IP + 81926362U, // EE_LDQA_S8_128_XP + 35787615U, // EE_LDQA_U16_128_IP + 81926341U, // EE_LDQA_U16_128_XP + 35787656U, // EE_LDQA_U8_128_IP + 81926382U, // EE_LDQA_U8_128_XP + 34912U, // EE_LDXQ_32 + 1625331017U, // EE_LD_128_USAR_IP + 14719551U, // EE_LD_128_USAR_XP + 37885277U, // EE_LD_ACCX_IP + 39981675U, // EE_LD_QACC_H_H_32_IP + 35787724U, // EE_LD_QACC_H_L_128_IP + 39981721U, // EE_LD_QACC_L_H_32_IP + 35787772U, // EE_LD_QACC_L_L_128_IP + 35788065U, // EE_LD_UA_STATE_IP + 2189560737U, // EE_MOVI_32_A + 2147523179U, // EE_MOVI_32_Q + 560111U, // EE_MOV_S16_QACC + 560228U, // EE_MOV_S8_QACC + 560150U, // EE_MOV_U16_QACC + 560265U, // EE_MOV_U8_QACC + 67148518U, // EE_NOTQ + 39635U, // EE_ORQ + 263785U, // EE_SET_BIT_GPIO_OUT + 44210833U, // EE_SLCI_2Q + 1874603U, // EE_SLCXXP_2Q + 44210846U, // EE_SRCI_2Q + 1073777584U, // EE_SRCMB_S16_QACC + 1073777704U, // EE_SRCMB_S8_QACC + 14815684U, // EE_SRCQ_128_ST_INCP + 1874618U, // EE_SRCXXP_2Q + 39546U, // EE_SRC_Q + 287347878U, // EE_SRC_Q_LD_IP + 153131460U, // EE_SRC_Q_LD_XP + 14718989U, // EE_SRC_Q_QUP + 1073781630U, // EE_SRS_ACCX + 14816188U, // EE_STF_128_IP + 14817570U, // EE_STF_128_XP + 14815958U, // EE_STF_64_IP + 14817340U, // EE_STF_64_XP + 34925U, // EE_STXQ_32 + 37885293U, // EE_ST_ACCX_IP + 39981698U, // EE_ST_QACC_H_H_32_IP + 35787748U, // EE_ST_QACC_H_L_128_IP + 39981744U, // EE_ST_QACC_L_H_32_IP + 35787796U, // EE_ST_QACC_L_L_128_IP + 35788085U, // EE_ST_UA_STATE_IP + 35441U, // EE_VADDS_S16 + 3441463172U, // EE_VADDS_S16_LD_INCP + 537039208U, // EE_VADDS_S16_ST_INCP + 34996U, // EE_VADDS_S32 + 3441463038U, // EE_VADDS_S32_LD_INCP + 537039048U, // EE_VADDS_S32_ST_INCP + 35644U, // EE_VADDS_S8 + 3441463328U, // EE_VADDS_S8_LD_INCP + 537039386U, // EE_VADDS_S8_ST_INCP + 35409U, // EE_VCMP_EQ_S16 + 34964U, // EE_VCMP_EQ_S32 + 35614U, // EE_VCMP_EQ_S8 + 35456U, // EE_VCMP_GT_S16 + 35011U, // EE_VCMP_GT_S32 + 35658U, // EE_VCMP_GT_S8 + 35473U, // EE_VCMP_LT_S16 + 35028U, // EE_VCMP_LT_S32 + 35674U, // EE_VCMP_LT_S8 + 67144171U, // EE_VLDBC_16 + 2162201385U, // EE_VLDBC_16_IP + 14719119U, // EE_VLDBC_16_XP + 67143722U, // EE_VLDBC_32 + 2699072090U, // EE_VLDBC_32_IP + 14719004U, // EE_VLDBC_32_XP + 67144413U, // EE_VLDBC_8 + 3235943226U, // EE_VLDBC_8_IP + 14719136U, // EE_VLDBC_8_XP + 36419U, // EE_VLDHBC_16_INCP + 1625330588U, // EE_VLD_128_IP + 14719234U, // EE_VLD_128_XP + 3772814053U, // EE_VLD_H_64_IP + 14719051U, // EE_VLD_H_64_XP + 3772814087U, // EE_VLD_L_64_IP + 14719085U, // EE_VLD_L_64_XP + 35521U, // EE_VMAX_S16 + 3441463220U, // EE_VMAX_S16_LD_INCP + 537039256U, // EE_VMAX_S16_ST_INCP + 35045U, // EE_VMAX_S32 + 3441463061U, // EE_VMAX_S32_LD_INCP + 537039071U, // EE_VMAX_S32_ST_INCP + 35719U, // EE_VMAX_S8 + 3441463350U, // EE_VMAX_S8_LD_INCP + 537039408U, // EE_VMAX_S8_ST_INCP + 35395U, // EE_VMIN_S16 + 3441463127U, // EE_VMIN_S16_LD_INCP + 537039163U, // EE_VMIN_S16_ST_INCP + 34950U, // EE_VMIN_S32 + 3441462993U, // EE_VMIN_S32_LD_INCP + 537039003U, // EE_VMIN_S32_ST_INCP + 35601U, // EE_VMIN_S8 + 3441463285U, // EE_VMIN_S8_LD_INCP + 537039343U, // EE_VMIN_S8_ST_INCP + 67148588U, // EE_VMULAS_S16_ACCX + 14718135U, // EE_VMULAS_S16_ACCX_LD_IP + 354457247U, // EE_VMULAS_S16_ACCX_LD_IP_QUP + 14719445U, // EE_VMULAS_S16_ACCX_LD_XP + 153130899U, // EE_VMULAS_S16_ACCX_LD_XP_QUP + 67144666U, // EE_VMULAS_S16_QACC + 14716503U, // EE_VMULAS_S16_QACC_LDBC_INCP + 153130395U, // EE_VMULAS_S16_QACC_LDBC_INCP_QUP + 14718012U, // EE_VMULAS_S16_QACC_LD_IP + 354457125U, // EE_VMULAS_S16_QACC_LD_IP_QUP + 14719322U, // EE_VMULAS_S16_QACC_LD_XP + 153130777U, // EE_VMULAS_S16_QACC_LD_XP_QUP + 67148630U, // EE_VMULAS_S8_ACCX + 14718189U, // EE_VMULAS_S8_ACCX_LD_IP + 354457309U, // EE_VMULAS_S8_ACCX_LD_IP_QUP + 14719499U, // EE_VMULAS_S8_ACCX_LD_XP + 153130961U, // EE_VMULAS_S8_ACCX_LD_XP_QUP + 67144784U, // EE_VMULAS_S8_QACC + 14716565U, // EE_VMULAS_S8_QACC_LDBC_INCP + 153130465U, // EE_VMULAS_S8_QACC_LDBC_INCP_QUP + 14718066U, // EE_VMULAS_S8_QACC_LD_IP + 354457187U, // EE_VMULAS_S8_QACC_LD_IP_QUP + 14719376U, // EE_VMULAS_S8_QACC_LD_XP + 153130839U, // EE_VMULAS_S8_QACC_LD_XP_QUP + 67148609U, // EE_VMULAS_U16_ACCX + 14718162U, // EE_VMULAS_U16_ACCX_LD_IP + 354457278U, // EE_VMULAS_U16_ACCX_LD_IP_QUP + 14719472U, // EE_VMULAS_U16_ACCX_LD_XP + 153130930U, // EE_VMULAS_U16_ACCX_LD_XP_QUP + 67144705U, // EE_VMULAS_U16_QACC + 14716534U, // EE_VMULAS_U16_QACC_LDBC_INCP + 153130430U, // EE_VMULAS_U16_QACC_LDBC_INCP_QUP + 14718039U, // EE_VMULAS_U16_QACC_LD_IP + 354457156U, // EE_VMULAS_U16_QACC_LD_IP_QUP + 14719349U, // EE_VMULAS_U16_QACC_LD_XP + 153130808U, // EE_VMULAS_U16_QACC_LD_XP_QUP + 67148650U, // EE_VMULAS_U8_ACCX + 14718215U, // EE_VMULAS_U8_ACCX_LD_IP + 354457339U, // EE_VMULAS_U8_ACCX_LD_IP_QUP + 14719525U, // EE_VMULAS_U8_ACCX_LD_XP + 153130991U, // EE_VMULAS_U8_ACCX_LD_XP_QUP + 67144821U, // EE_VMULAS_U8_QACC + 14716595U, // EE_VMULAS_U8_QACC_LDBC_INCP + 153130499U, // EE_VMULAS_U8_QACC_LDBC_INCP_QUP + 14718092U, // EE_VMULAS_U8_QACC_LD_IP + 354457217U, // EE_VMULAS_U8_QACC_LD_IP_QUP + 14719402U, // EE_VMULAS_U8_QACC_LD_XP + 153130869U, // EE_VMULAS_U8_QACC_LD_XP_QUP + 35381U, // EE_VMUL_S16 + 3441463105U, // EE_VMUL_S16_LD_INCP + 537039141U, // EE_VMUL_S16_ST_INCP + 35588U, // EE_VMUL_S8 + 3441463264U, // EE_VMUL_S8_LD_INCP + 537039322U, // EE_VMUL_S8_ST_INCP + 35535U, // EE_VMUL_U16 + 3441463242U, // EE_VMUL_U16_LD_INCP + 537039278U, // EE_VMUL_U16_ST_INCP + 35732U, // EE_VMUL_U8 + 3441463371U, // EE_VMUL_U8_LD_INCP + 537039429U, // EE_VMUL_U8_ST_INCP + 35490U, // EE_VPRELU_S16 + 35690U, // EE_VPRELU_S8 + 14813874U, // EE_VRELU_S16 + 14814073U, // EE_VRELU_S8 + 67143736U, // EE_VSL_32 + 1610648516U, // EE_VSMULAS_S16_QACC + 14717024U, // EE_VSMULAS_S16_QACC_LD_INCP + 2684390459U, // EE_VSMULAS_S8_QACC + 14717054U, // EE_VSMULAS_S8_QACC_LD_INCP + 67143802U, // EE_VSR_32 + 1625429036U, // EE_VST_128_IP + 14817586U, // EE_VST_128_XP + 3772912374U, // EE_VST_H_64_IP + 14817372U, // EE_VST_H_64_XP + 3772912408U, // EE_VST_L_64_IP + 14817406U, // EE_VST_L_64_XP + 35426U, // EE_VSUBS_S16 + 3441463149U, // EE_VSUBS_S16_LD_INCP + 537039185U, // EE_VSUBS_S16_ST_INCP + 34981U, // EE_VSUBS_S32 + 3441463015U, // EE_VSUBS_S32_LD_INCP + 537039025U, // EE_VSUBS_S32_ST_INCP + 35630U, // EE_VSUBS_S8 + 3441463306U, // EE_VSUBS_S8_LD_INCP + 537039364U, // EE_VSUBS_S8_ST_INCP + 690681U, // EE_VUNZIP_16 + 690244U, // EE_VUNZIP_32 + 690922U, // EE_VUNZIP_8 + 690696U, // EE_VZIP_16 + 690259U, // EE_VZIP_32 + 690936U, // EE_VZIP_8 + 67143231U, // EE_WR_MASK_GPIO_OUT + 39644U, // EE_XORQ + 1735U, // EE_ZERO_ACCX + 563845U, // EE_ZERO_Q + 186U, // EE_ZERO_QACC + 46171881U, // ENTRY + 30510U, // ESYNC + 30658U, // EXCW + 2684388047U, // EXTUI + 30673U, // EXTW + 2147517881U, // FLOAT_S + 2147517864U, // FLOOR_S + 558188U, // GET_GPIO_IN + 30567U, // ILL + 30571U, // ILL_N + 30516U, // ISYNC + 328413U, // J + 558805U, // JX + 10519184U, // L16SI + 10519220U, // L16UI + 536903895U, // L32E + 10519092U, // L32I + 10519608U, // L32I_N + 48268456U, // L32R + 10519227U, // L8UI + 81824933U, // LDDEC + 81825085U, // LDINC + 10519134U, // LEA_ADD + 50365578U, // LOOP + 50366243U, // LOOPGTZ + 50366212U, // LOOPNEZ + 10519197U, // LSI + 1088455806U, // LSIP + 34521U, // LSX + 14714007U, // LSXP + 14714233U, // MADDN_S + 14714141U, // MADD_S + 34498U, // MAX + 34486U, // MAXU + 30663U, // MEMW + 33913U, // MIN + 34468U, // MINU + 81921355U, // MKDADJ_S + 67142997U, // MKSADJ_S + 34587U, // MOVEQZ + 14812668U, // MOVEQZ_S + 14811384U, // MOVF + 14812476U, // MOVF_S + 34550U, // MOVGEZ + 14812648U, // MOVGEZ_S + 52462295U, // MOVI + 54559825U, // MOVI_N + 34610U, // MOVLTZ + 14812678U, // MOVLTZ_S + 34573U, // MOVNEZ + 14812658U, // MOVNEZ_S + 67142800U, // MOVSP + 14812798U, // MOVT + 14812633U, // MOVT_S + 67142754U, // MOV_N + 67143137U, // MOV_S + 14714123U, // MSUB_S + 34320U, // MUL16S + 34442U, // MUL16U + 67141891U, // MULA_AA_HH + 67142382U, // MULA_AA_HL + 67142032U, // MULA_AA_LH + 67142529U, // MULA_AA_LL + 67141962U, // MULA_AD_HH + 67142453U, // MULA_AD_HL + 67142103U, // MULA_AD_LH + 67142600U, // MULA_AD_LL + 67141927U, // MULA_DA_HH + 14716058U, // MULA_DA_HH_LDDEC + 14716210U, // MULA_DA_HH_LDINC + 67142418U, // MULA_DA_HL + 14716134U, // MULA_DA_HL_LDDEC + 14716286U, // MULA_DA_HL_LDINC + 67142068U, // MULA_DA_LH + 14716096U, // MULA_DA_LH_LDDEC + 14716248U, // MULA_DA_LH_LDINC + 67142565U, // MULA_DA_LL + 14716172U, // MULA_DA_LL_LDDEC + 14716324U, // MULA_DA_LL_LDINC + 67141997U, // MULA_DD_HH + 14716077U, // MULA_DD_HH_LDDEC + 14716229U, // MULA_DD_HH_LDINC + 67142488U, // MULA_DD_HL + 14716153U, // MULA_DD_HL_LDDEC + 14716305U, // MULA_DD_HL_LDINC + 67142138U, // MULA_DD_LH + 14716115U, // MULA_DD_LH_LDDEC + 14716267U, // MULA_DD_LH_LDINC + 67142635U, // MULA_DD_LL + 14716191U, // MULA_DD_LL_LDDEC + 14716343U, // MULA_DD_LL_LDINC + 33824U, // MULL + 33309U, // MULSH + 67141915U, // MULS_AA_HH + 67142406U, // MULS_AA_HL + 67142056U, // MULS_AA_LH + 67142553U, // MULS_AA_LL + 67141985U, // MULS_AD_HH + 67142476U, // MULS_AD_HL + 67142126U, // MULS_AD_LH + 67142623U, // MULS_AD_LL + 67141950U, // MULS_DA_HH + 67142441U, // MULS_DA_HL + 67142091U, // MULS_DA_LH + 67142588U, // MULS_DA_LL + 67142020U, // MULS_DD_HH + 67142511U, // MULS_DD_HL + 67142161U, // MULS_DD_LH + 67142658U, // MULS_DD_LL + 33316U, // MULUH + 67141904U, // MUL_AA_HH + 67142395U, // MUL_AA_HL + 67142045U, // MUL_AA_LH + 67142542U, // MUL_AA_LL + 67141974U, // MUL_AD_HH + 67142465U, // MUL_AD_HL + 67142115U, // MUL_AD_LH + 67142612U, // MUL_AD_LL + 67141939U, // MUL_DA_HH + 67142430U, // MUL_DA_HL + 67142080U, // MUL_DA_LH + 67142577U, // MUL_DA_LL + 67142009U, // MUL_DD_HH + 67142500U, // MUL_DD_HL + 67142150U, // MUL_DD_LH + 67142647U, // MUL_DD_LL + 34151U, // MUL_S + 67141886U, // NEG + 67142980U, // NEG_S + 67142913U, // NEXP01_S + 30645U, // NOP + 67141764U, // NSA + 67143314U, // NSAU + 34202U, // OEQ_S + 34094U, // OLE_S + 34242U, // OLT_S + 33987U, // OR + 32926U, // ORB + 32948U, // ORBC + 34344U, // QUOS + 34474U, // QUOU + 67142885U, // RECIP0_S + 34338U, // REMS + 34462U, // REMU + 67142830U, // RER + 30649U, // RET + 30668U, // RETW + 30583U, // RETW_N + 30577U, // RET_N + 30528U, // RFDE + 30533U, // RFE + 721520U, // RFI + 67142840U, // RFR + 30594U, // RFWO + 30653U, // RFWU + 362172U, // ROTW + 2147517733U, // ROUND_S + 33588091U, // RSIL + 67142895U, // RSQRT0_S + 67142855U, // RSR + 30522U, // RSYNC + 67142875U, // RUR + 559000U, // RUR_ACCX_0 + 559120U, // RUR_ACCX_1 + 581292U, // RUR_AE_BITHEAD + 585856U, // RUR_AE_BITPTR + 581324U, // RUR_AE_BITSUSED + 573081U, // RUR_AE_CBEGIN0 + 572479U, // RUR_AE_CEND0 + 584572U, // RUR_AE_CWRAP + 584538U, // RUR_AE_CW_SD_NO + 586621U, // RUR_AE_FIRST_TS + 586712U, // RUR_AE_NEXTOFFSET + 586967U, // RUR_AE_OVERFLOW + 585779U, // RUR_AE_OVF_SAR + 585755U, // RUR_AE_SAR + 581385U, // RUR_AE_SEARCHDONE + 581423U, // RUR_AE_TABLESIZE + 584614U, // RUR_AE_TS_FTS_BU_BP + 560616U, // RUR_FFT_BIT_WIDTH + 563970U, // RUR_GPIO_OUT + 558940U, // RUR_QACC_H_0 + 559060U, // RUR_QACC_H_1 + 559381U, // RUR_QACC_H_2 + 559475U, // RUR_QACC_H_3 + 559535U, // RUR_QACC_H_4 + 558970U, // RUR_QACC_L_0 + 559090U, // RUR_QACC_L_1 + 559411U, // RUR_QACC_L_2 + 559505U, // RUR_QACC_L_3 + 559565U, // RUR_QACC_L_4 + 560586U, // RUR_SAR_BYTE + 558906U, // RUR_UA_STATE_0 + 559026U, // RUR_UA_STATE_1 + 559347U, // RUR_UA_STATE_2 + 559441U, // RUR_UA_STATE_3 + 10519105U, // S16I + 56754731U, // S32C1I + 536903901U, // S32E + 10519099U, // S32I + 10519617U, // S32I_N + 10519111U, // S8I + 263788U, // SET_BIT_GPIO_OUT + 1610647172U, // SEXT + 30551U, // SIMCALL + 67142683U, // SLL + 1610646134U, // SLLI + 67142896U, // SQRT0_S + 67141759U, // SRA + 2684387916U, // SRAI + 32968U, // SRC + 67142694U, // SRL + 2684387965U, // SRLI + 557799U, // SSA8L + 393810U, // SSAI + 10519202U, // SSI + 1088554116U, // SSIP + 558123U, // SSL + 558284U, // SSR + 34526U, // SSX + 14812317U, // SSXP + 32931U, // SUB + 32811U, // SUBX2 + 32832U, // SUBX4 + 32867U, // SUBX8 + 34060U, // SUB_S + 30559U, // SYSCALL + 2147517716U, // TRUNC_S + 34209U, // UEQ_S + 2147517880U, // UFLOAT_S + 34101U, // ULE_S + 34249U, // ULT_S + 67141903U, // UMUL_AA_HH + 67142394U, // UMUL_AA_HL + 67142044U, // UMUL_AA_LH + 67142541U, // UMUL_AA_LL + 34178U, // UN_S + 2147517715U, // UTRUNC_S + 721575U, // WAITI + 67141775U, // WDTLB + 67142835U, // WER + 67142845U, // WFR + 67141782U, // WITLB + 67143234U, // WR_MASK_GPIO_OUT + 109184209U, // WSR + 109184224U, // WUR + 559013U, // WUR_ACCX_0 + 559133U, // WUR_ACCX_1 + 581308U, // WUR_AE_BITHEAD + 585871U, // WUR_AE_BITPTR + 581341U, // WUR_AE_BITSUSED + 573097U, // WUR_AE_CBEGIN0 + 572493U, // WUR_AE_CEND0 + 584586U, // WUR_AE_CWRAP + 584555U, // WUR_AE_CW_SD_NO + 586638U, // WUR_AE_FIRST_TS + 586731U, // WUR_AE_NEXTOFFSET + 586984U, // WUR_AE_OVERFLOW + 585795U, // WUR_AE_OVF_SAR + 585767U, // WUR_AE_SAR + 581404U, // WUR_AE_SEARCHDONE + 581441U, // WUR_AE_TABLESIZE + 584635U, // WUR_AE_TS_FTS_BU_BP + 557057U, // WUR_FCR + 560636U, // WUR_FFT_BIT_WIDTH + 563960U, // WUR_FSR + 563985U, // WUR_GPIO_OUT + 558955U, // WUR_QACC_H_0 + 559075U, // WUR_QACC_H_1 + 559396U, // WUR_QACC_H_2 + 559490U, // WUR_QACC_H_3 + 559550U, // WUR_QACC_H_4 + 558985U, // WUR_QACC_L_0 + 559105U, // WUR_QACC_L_1 + 559426U, // WUR_QACC_L_2 + 559520U, // WUR_QACC_L_3 + 559580U, // WUR_QACC_L_4 + 560601U, // WUR_SAR_BYTE + 558923U, // WUR_UA_STATE_0 + 559043U, // WUR_UA_STATE_1 + 559364U, // WUR_UA_STATE_2 + 559458U, // WUR_UA_STATE_3 + 33986U, // XOR + 32925U, // XORB + 689366U, // XSR + 10519091U, // _L32I + 10519607U, // _L32I_N + 58753750U, // _MOVI + 10519098U, // _S32I + 10519616U, // _S32I_N + 2147517045U, // _SLLI + 2147517052U, // _SRLI + 67148528U, // mv_QR }; - static const uint8_t OpInfo1[] = { + static const uint16_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // INLINEASM_BR @@ -741,94 +3994,3730 @@ static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 0U, // G_VECREDUCE_UMIN 0U, // G_SBFX 0U, // G_UBFX + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ATOMIC_CMP_SWAP_16_P + 0U, // ATOMIC_CMP_SWAP_32_P + 0U, // ATOMIC_CMP_SWAP_8_P + 8U, // ATOMIC_LOAD_ADD_16_P + 8U, // ATOMIC_LOAD_ADD_32_P + 8U, // ATOMIC_LOAD_ADD_8_P + 8U, // ATOMIC_LOAD_AND_16_P + 8U, // ATOMIC_LOAD_AND_32_P + 8U, // ATOMIC_LOAD_AND_8_P + 8U, // ATOMIC_LOAD_MAX_16_P + 8U, // ATOMIC_LOAD_MAX_32_P + 8U, // ATOMIC_LOAD_MAX_8_P + 8U, // ATOMIC_LOAD_MIN_16_P + 8U, // ATOMIC_LOAD_MIN_32_P + 8U, // ATOMIC_LOAD_MIN_8_P + 8U, // ATOMIC_LOAD_NAND_16_P + 8U, // ATOMIC_LOAD_NAND_32_P + 8U, // ATOMIC_LOAD_NAND_8_P + 8U, // ATOMIC_LOAD_OR_16_P + 8U, // ATOMIC_LOAD_OR_32_P + 8U, // ATOMIC_LOAD_OR_8_P + 8U, // ATOMIC_LOAD_SUB_16_P + 8U, // ATOMIC_LOAD_SUB_32_P + 8U, // ATOMIC_LOAD_SUB_8_P + 8U, // ATOMIC_LOAD_UMAX_16_P + 8U, // ATOMIC_LOAD_UMAX_32_P + 8U, // ATOMIC_LOAD_UMAX_8_P + 8U, // ATOMIC_LOAD_UMIN_16_P + 8U, // ATOMIC_LOAD_UMIN_32_P + 8U, // ATOMIC_LOAD_UMIN_8_P + 8U, // ATOMIC_LOAD_XOR_16_P + 8U, // ATOMIC_LOAD_XOR_32_P + 8U, // ATOMIC_LOAD_XOR_8_P + 8U, // ATOMIC_SWAP_16_P + 8U, // ATOMIC_SWAP_32_P + 8U, // ATOMIC_SWAP_8_P + 64U, // BRCC_FP + 0U, // BR_JT + 0U, // CONSTPOOL_ENTRY + 8U, // EE_ANDQ_P + 0U, // EE_BITREV_P + 1152U, // EE_CMUL_S16_LD_INCP_P + 192U, // EE_CMUL_S16_P + 1152U, // EE_CMUL_S16_ST_INCP_P + 1152U, // EE_FFT_AMS_S16_LD_INCP_P + 1152U, // EE_FFT_AMS_S16_LD_INCP_UAUP_P + 1152U, // EE_FFT_AMS_S16_LD_R32_DECP_P + 1024U, // EE_FFT_AMS_S16_ST_INCP_P + 1152U, // EE_FFT_CMUL_S16_LD_XP_P + 3072U, // EE_FFT_CMUL_S16_ST_XP_P + 5248U, // EE_FFT_R2BF_S16_P + 7168U, // EE_FFT_R2BF_S16_ST_INCP_P + 0U, // EE_FFT_VST_R32_DECP_P + 3072U, // EE_LDF_128_IP_P + 3072U, // EE_LDF_128_XP_P + 256U, // EE_LDF_64_IP_P + 0U, // EE_LDF_64_XP_P + 0U, // EE_LDQA_S16_128_IP_P + 0U, // EE_LDQA_S16_128_XP_P + 0U, // EE_LDQA_S8_128_IP_P + 0U, // EE_LDQA_S8_128_XP_P + 0U, // EE_LDQA_U16_128_IP_P + 0U, // EE_LDQA_U16_128_XP_P + 0U, // EE_LDQA_U8_128_IP_P + 0U, // EE_LDQA_U8_128_XP_P + 9408U, // EE_LDXQ_32_P + 8U, // EE_LD_128_USAR_IP_P + 8U, // EE_LD_128_USAR_XP_P + 0U, // EE_LD_ACCX_IP_P + 0U, // EE_LD_QACC_H_H_32_IP_P + 0U, // EE_LD_QACC_H_L_128_IP_P + 0U, // EE_LD_QACC_L_H_32_IP_P + 0U, // EE_LD_QACC_L_L_128_IP_P + 0U, // EE_LD_UA_STATE_IP_P + 0U, // EE_MOVI_32_A_P + 0U, // EE_MOVI_32_Q_P + 0U, // EE_MOV_S16_QACC_P + 0U, // EE_MOV_S8_QACC_P + 0U, // EE_MOV_U16_QACC_P + 0U, // EE_MOV_U8_QACC_P + 0U, // EE_NOTQ_P + 8U, // EE_ORQ_P + 0U, // EE_SLCI_2Q_P + 0U, // EE_SLCXXP_2Q_P + 0U, // EE_SRCI_2Q_P + 0U, // EE_SRCMB_S16_QACC_P + 0U, // EE_SRCMB_S8_QACC_P + 8U, // EE_SRCQ_128_ST_INCP_P + 0U, // EE_SRCXXP_2Q_P + 33920U, // EE_SRC_Q_LD_IP_P + 33920U, // EE_SRC_Q_LD_XP_P + 8U, // EE_SRC_Q_P + 8U, // EE_SRC_Q_QUP_P + 0U, // EE_SRS_ACCX_P + 3072U, // EE_STF_128_IP_P + 3072U, // EE_STF_128_XP_P + 256U, // EE_STF_64_IP_P + 0U, // EE_STF_64_XP_P + 9408U, // EE_STXQ_32_P + 0U, // EE_ST_ACCX_IP_P + 0U, // EE_ST_QACC_H_H_32_IP_P + 0U, // EE_ST_QACC_H_L_128_IP_P + 0U, // EE_ST_QACC_L_H_32_IP_P + 0U, // EE_ST_QACC_L_L_128_IP_P + 0U, // EE_ST_UA_STATE_IP_P + 33920U, // EE_VADDS_S16_LD_INCP_P + 8U, // EE_VADDS_S16_P + 33920U, // EE_VADDS_S16_ST_INCP_P + 33920U, // EE_VADDS_S32_LD_INCP_P + 8U, // EE_VADDS_S32_P + 33920U, // EE_VADDS_S32_ST_INCP_P + 33920U, // EE_VADDS_S8_LD_INCP_P + 8U, // EE_VADDS_S8_P + 33920U, // EE_VADDS_S8_ST_INCP_P + 8U, // EE_VCMP_EQ_S16_P + 8U, // EE_VCMP_EQ_S32_P + 8U, // EE_VCMP_EQ_S8_P + 8U, // EE_VCMP_GT_S16_P + 8U, // EE_VCMP_GT_S32_P + 8U, // EE_VCMP_GT_S8_P + 8U, // EE_VCMP_LT_S16_P + 8U, // EE_VCMP_LT_S32_P + 8U, // EE_VCMP_LT_S8_P + 0U, // EE_VLDBC_16_IP_P + 0U, // EE_VLDBC_16_P + 8U, // EE_VLDBC_16_XP_P + 0U, // EE_VLDBC_32_IP_P + 0U, // EE_VLDBC_32_P + 8U, // EE_VLDBC_32_XP_P + 1U, // EE_VLDBC_8_IP_P + 0U, // EE_VLDBC_8_P + 8U, // EE_VLDBC_8_XP_P + 8U, // EE_VLDHBC_16_INCP_P + 8U, // EE_VLD_128_IP_P + 8U, // EE_VLD_128_XP_P + 1U, // EE_VLD_H_64_IP_P + 8U, // EE_VLD_H_64_XP_P + 1U, // EE_VLD_L_64_IP_P + 8U, // EE_VLD_L_64_XP_P + 33920U, // EE_VMAX_S16_LD_INCP_P + 8U, // EE_VMAX_S16_P + 33920U, // EE_VMAX_S16_ST_INCP_P + 33920U, // EE_VMAX_S32_LD_INCP_P + 8U, // EE_VMAX_S32_P + 33920U, // EE_VMAX_S32_ST_INCP_P + 33920U, // EE_VMAX_S8_LD_INCP_P + 8U, // EE_VMAX_S8_P + 33920U, // EE_VMAX_S8_ST_INCP_P + 33920U, // EE_VMIN_S16_LD_INCP_P + 8U, // EE_VMIN_S16_P + 33920U, // EE_VMIN_S16_ST_INCP_P + 33920U, // EE_VMIN_S32_LD_INCP_P + 8U, // EE_VMIN_S32_P + 33920U, // EE_VMIN_S32_ST_INCP_P + 33920U, // EE_VMIN_S8_LD_INCP_P + 8U, // EE_VMIN_S8_P + 33920U, // EE_VMIN_S8_ST_INCP_P + 9U, // EE_VMULAS_S16_ACCX_LD_IP_P + 321U, // EE_VMULAS_S16_ACCX_LD_IP_QUP_P + 33920U, // EE_VMULAS_S16_ACCX_LD_XP_P + 1152U, // EE_VMULAS_S16_ACCX_LD_XP_QUP_P + 0U, // EE_VMULAS_S16_ACCX_P + 128U, // EE_VMULAS_S16_QACC_LDBC_INCP_P + 1152U, // EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P + 9U, // EE_VMULAS_S16_QACC_LD_IP_P + 321U, // EE_VMULAS_S16_QACC_LD_IP_QUP_P + 33920U, // EE_VMULAS_S16_QACC_LD_XP_P + 1152U, // EE_VMULAS_S16_QACC_LD_XP_QUP_P + 0U, // EE_VMULAS_S16_QACC_P + 9U, // EE_VMULAS_S8_ACCX_LD_IP_P + 321U, // EE_VMULAS_S8_ACCX_LD_IP_QUP_P + 33920U, // EE_VMULAS_S8_ACCX_LD_XP_P + 1152U, // EE_VMULAS_S8_ACCX_LD_XP_QUP_P + 0U, // EE_VMULAS_S8_ACCX_P + 128U, // EE_VMULAS_S8_QACC_LDBC_INCP_P + 1152U, // EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P + 9U, // EE_VMULAS_S8_QACC_LD_IP_P + 321U, // EE_VMULAS_S8_QACC_LD_IP_QUP_P + 33920U, // EE_VMULAS_S8_QACC_LD_XP_P + 1152U, // EE_VMULAS_S8_QACC_LD_XP_QUP_P + 0U, // EE_VMULAS_S8_QACC_P + 9U, // EE_VMULAS_U16_ACCX_LD_IP_P + 321U, // EE_VMULAS_U16_ACCX_LD_IP_QUP_P + 33920U, // EE_VMULAS_U16_ACCX_LD_XP_P + 1152U, // EE_VMULAS_U16_ACCX_LD_XP_QUP_P + 0U, // EE_VMULAS_U16_ACCX_P + 128U, // EE_VMULAS_U16_QACC_LDBC_INCP_P + 1152U, // EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P + 9U, // EE_VMULAS_U16_QACC_LD_IP_P + 321U, // EE_VMULAS_U16_QACC_LD_IP_QUP_P + 33920U, // EE_VMULAS_U16_QACC_LD_XP_P + 1152U, // EE_VMULAS_U16_QACC_LD_XP_QUP_P + 0U, // EE_VMULAS_U16_QACC_P + 9U, // EE_VMULAS_U8_ACCX_LD_IP_P + 321U, // EE_VMULAS_U8_ACCX_LD_IP_QUP_P + 33920U, // EE_VMULAS_U8_ACCX_LD_XP_P + 1152U, // EE_VMULAS_U8_ACCX_LD_XP_QUP_P + 0U, // EE_VMULAS_U8_ACCX_P + 128U, // EE_VMULAS_U8_QACC_LDBC_INCP_P + 1152U, // EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P + 9U, // EE_VMULAS_U8_QACC_LD_IP_P + 321U, // EE_VMULAS_U8_QACC_LD_IP_QUP_P + 33920U, // EE_VMULAS_U8_QACC_LD_XP_P + 1152U, // EE_VMULAS_U8_QACC_LD_XP_QUP_P + 0U, // EE_VMULAS_U8_QACC_P + 33920U, // EE_VMUL_S16_LD_INCP_P + 8U, // EE_VMUL_S16_P + 33920U, // EE_VMUL_S16_ST_INCP_P + 33920U, // EE_VMUL_S8_LD_INCP_P + 8U, // EE_VMUL_S8_P + 33920U, // EE_VMUL_S8_ST_INCP_P + 33920U, // EE_VMUL_U16_LD_INCP_P + 8U, // EE_VMUL_U16_P + 33920U, // EE_VMUL_U16_ST_INCP_P + 33920U, // EE_VMUL_U8_LD_INCP_P + 8U, // EE_VMUL_U8_P + 33920U, // EE_VMUL_U8_ST_INCP_P + 0U, // EE_VPRELU_S16_P + 0U, // EE_VPRELU_S8_P + 8U, // EE_VRELU_S16_P + 8U, // EE_VRELU_S8_P + 0U, // EE_VSL_32_P + 9344U, // EE_VSMULAS_S16_QACC_LD_INCP_P + 1U, // EE_VSMULAS_S16_QACC_P + 11392U, // EE_VSMULAS_S8_QACC_LD_INCP_P + 0U, // EE_VSMULAS_S8_QACC_P + 0U, // EE_VSR_32_P + 8U, // EE_VST_128_IP_P + 8U, // EE_VST_128_XP_P + 1U, // EE_VST_H_64_IP_P + 8U, // EE_VST_H_64_XP_P + 1U, // EE_VST_L_64_IP_P + 8U, // EE_VST_L_64_XP_P + 33920U, // EE_VSUBS_S16_LD_INCP_P + 8U, // EE_VSUBS_S16_P + 33920U, // EE_VSUBS_S16_ST_INCP_P + 33920U, // EE_VSUBS_S32_LD_INCP_P + 8U, // EE_VSUBS_S32_P + 33920U, // EE_VSUBS_S32_ST_INCP_P + 33920U, // EE_VSUBS_S8_LD_INCP_P + 8U, // EE_VSUBS_S8_P + 33920U, // EE_VSUBS_S8_ST_INCP_P + 0U, // EE_VUNZIP_16_P + 0U, // EE_VUNZIP_32_P + 0U, // EE_VUNZIP_8_P + 0U, // EE_VZIP_16_P + 0U, // EE_VZIP_32_P + 0U, // EE_VZIP_8_P + 8U, // EE_XORQ_P + 0U, // EE_ZERO_ACCX_P + 0U, // EE_ZERO_QACC_P + 0U, // EE_ZERO_Q_P + 8U, // EXTUI_BR2_P + 8U, // EXTUI_BR4_P + 8U, // EXTUI_BR_P + 0U, // L8I_P + 0U, // LDDEC_P + 0U, // LDINC_P + 0U, // LOOPBR + 0U, // LOOPDEC + 0U, // LOOPEND + 0U, // LOOPINIT + 0U, // LOOPSTART + 0U, // MOVBA2_P + 0U, // MOVBA2_P2 + 0U, // MOVBA4_P + 0U, // MOVBA4_P2 + 0U, // MOVBA_P + 0U, // MOVBA_P2 + 0U, // MULA_DA_HH_LDDEC_P + 0U, // MULA_DA_HH_LDINC_P + 0U, // MULA_DA_HL_LDDEC_P + 0U, // MULA_DA_HL_LDINC_P + 0U, // MULA_DA_LH_LDDEC_P + 0U, // MULA_DA_LH_LDINC_P + 0U, // MULA_DA_LL_LDDEC_P + 0U, // MULA_DA_LL_LDINC_P + 128U, // MULA_DD_HH_LDDEC_P + 128U, // MULA_DD_HH_LDINC_P + 128U, // MULA_DD_HL_LDDEC_P + 128U, // MULA_DD_HL_LDINC_P + 128U, // MULA_DD_LH_LDDEC_P + 128U, // MULA_DD_LH_LDINC_P + 128U, // MULA_DD_LL_LDDEC_P + 128U, // MULA_DD_LL_LDINC_P + 0U, // RESTORE_BOOL + 3072U, // SELECT + 3072U, // SELECT_CC_FP_FP + 3072U, // SELECT_CC_FP_INT + 3072U, // SELECT_CC_INT_FP + 8U, // SLLI_BR_P + 8U, // SLL_P + 0U, // SPILL_BOOL + 8U, // SRA_P + 8U, // SRL_P + 0U, // WSR_ACCHI_P + 0U, // WSR_ACCLO_P + 0U, // WSR_M0_P + 0U, // WSR_M1_P + 0U, // WSR_M2_P + 0U, // WSR_M3_P + 0U, // XSR_ACCHI_P + 0U, // XSR_ACCLO_P + 0U, // XSR_M0_P + 0U, // XSR_M1_P + 0U, // XSR_M2_P + 0U, // XSR_M3_P + 0U, // mv_QR_P 0U, // ABS - 2U, // ADD - 6U, // ADDI - 10U, // ADDMI - 2U, // ADDX2 - 2U, // ADDX4 - 2U, // ADDX8 - 2U, // AND - 14U, // BALL - 14U, // BANY - 14U, // BBC + 0U, // ABS_S + 8U, // ADD + 0U, // ADDEXPM_S + 0U, // ADDEXP_S + 8U, // ADDI + 1U, // ADDI_N + 1U, // ADDMI + 8U, // ADDX2 + 8U, // ADDX4 + 8U, // ADDX8 + 8U, // ADD_N + 8U, // ADD_S + 0U, // AE_ABS16S + 0U, // AE_ABS24S + 0U, // AE_ABS32 + 0U, // AE_ABS32S + 0U, // AE_ABS64 + 0U, // AE_ABS64S + 8U, // AE_ADD16 + 8U, // AE_ADD16S + 8U, // AE_ADD24S + 8U, // AE_ADD32 + 8U, // AE_ADD32S + 8U, // AE_ADD32_HL_LH + 8U, // AE_ADD64 + 8U, // AE_ADD64S + 8U, // AE_ADDBRBA32 + 8U, // AE_ADDSUB32 + 8U, // AE_ADDSUB32S + 8U, // AE_AND + 0U, // AE_CVT32X2F16_10 + 0U, // AE_CVT32X2F16_32 + 0U, // AE_CVT48A32 + 0U, // AE_CVT64A32 + 0U, // AE_CVT64F32_H + 0U, // AE_CVTA32F24S_H + 0U, // AE_CVTA32F24S_L + 0U, // AE_CVTQ56A32S + 0U, // AE_CVTQ56P32S_H + 0U, // AE_CVTQ56P32S_L + 0U, // AE_DB + 0U, // AE_DBI + 0U, // AE_DBI_IC + 0U, // AE_DBI_IP + 0U, // AE_DB_IC + 0U, // AE_DB_IP + 0U, // AE_DIV64D32_H + 0U, // AE_DIV64D32_L + 8U, // AE_EQ16 + 8U, // AE_EQ32 + 8U, // AE_EQ64 + 1U, // AE_L16M_I + 1U, // AE_L16M_IU + 8U, // AE_L16M_X + 10U, // AE_L16M_XC + 10U, // AE_L16M_XU + 2U, // AE_L16X2M_I + 2U, // AE_L16X2M_IU + 8U, // AE_L16X2M_X + 10U, // AE_L16X2M_XC + 10U, // AE_L16X2M_XU + 2U, // AE_L16X4_I + 2U, // AE_L16X4_IP + 0U, // AE_L16X4_RIC + 0U, // AE_L16X4_RIP + 8U, // AE_L16X4_X + 10U, // AE_L16X4_XC + 10U, // AE_L16X4_XP + 1U, // AE_L16_I + 1U, // AE_L16_IP + 8U, // AE_L16_X + 10U, // AE_L16_XC + 10U, // AE_L16_XP + 2U, // AE_L32F24_I + 2U, // AE_L32F24_IP + 8U, // AE_L32F24_X + 10U, // AE_L32F24_XC + 10U, // AE_L32F24_XP + 2U, // AE_L32M_I + 2U, // AE_L32M_IU + 8U, // AE_L32M_X + 10U, // AE_L32M_XC + 10U, // AE_L32M_XU + 2U, // AE_L32X2F24_I + 2U, // AE_L32X2F24_IP + 0U, // AE_L32X2F24_RIC + 0U, // AE_L32X2F24_RIP + 8U, // AE_L32X2F24_X + 10U, // AE_L32X2F24_XC + 10U, // AE_L32X2F24_XP + 2U, // AE_L32X2_I + 2U, // AE_L32X2_IP + 0U, // AE_L32X2_RIC + 0U, // AE_L32X2_RIP + 8U, // AE_L32X2_X + 10U, // AE_L32X2_XC + 10U, // AE_L32X2_XP + 2U, // AE_L32_I + 2U, // AE_L32_IP + 8U, // AE_L32_X + 10U, // AE_L32_XC + 10U, // AE_L32_XP + 2U, // AE_L64_I + 2U, // AE_L64_IP + 8U, // AE_L64_X + 10U, // AE_L64_XC + 10U, // AE_L64_XP + 0U, // AE_LA16X4NEG_PC + 0U, // AE_LA16X4POS_PC + 2U, // AE_LA16X4_IC + 2U, // AE_LA16X4_IP + 2U, // AE_LA16X4_RIC + 2U, // AE_LA16X4_RIP + 0U, // AE_LA24NEG_PC + 0U, // AE_LA24POS_PC + 0U, // AE_LA24X2NEG_PC + 0U, // AE_LA24X2POS_PC + 2U, // AE_LA24X2_IC + 2U, // AE_LA24X2_IP + 2U, // AE_LA24X2_RIC + 2U, // AE_LA24X2_RIP + 2U, // AE_LA24_IC + 2U, // AE_LA24_IP + 2U, // AE_LA24_RIC + 2U, // AE_LA24_RIP + 2U, // AE_LA32X2F24_IC + 2U, // AE_LA32X2F24_IP + 2U, // AE_LA32X2F24_RIC + 2U, // AE_LA32X2F24_RIP + 0U, // AE_LA32X2NEG_PC + 0U, // AE_LA32X2POS_PC + 2U, // AE_LA32X2_IC + 2U, // AE_LA32X2_IP + 2U, // AE_LA32X2_RIC + 2U, // AE_LA32X2_RIP + 0U, // AE_LA64_PP + 2U, // AE_LALIGN64_I + 0U, // AE_LB + 0U, // AE_LBI + 8U, // AE_LBK + 2U, // AE_LBKI + 0U, // AE_LBS + 0U, // AE_LBSI + 8U, // AE_LE16 + 8U, // AE_LE32 + 8U, // AE_LE64 + 8U, // AE_LT16 + 8U, // AE_LT32 + 8U, // AE_LT64 + 8U, // AE_MAX32 + 8U, // AE_MAX64 + 8U, // AE_MAXABS32S + 8U, // AE_MAXABS64S + 8U, // AE_MIN32 + 8U, // AE_MIN64 + 8U, // AE_MINABS32S + 8U, // AE_MINABS64S + 0U, // AE_MOV + 0U, // AE_MOVAD16_0 + 0U, // AE_MOVAD16_1 + 0U, // AE_MOVAD16_2 + 0U, // AE_MOVAD16_3 + 0U, // AE_MOVAD32_H + 0U, // AE_MOVAD32_L + 0U, // AE_MOVALIGN + 0U, // AE_MOVDA16 + 8U, // AE_MOVDA16X2 + 0U, // AE_MOVDA32 + 8U, // AE_MOVDA32X2 + 10U, // AE_MOVF16X4 + 10U, // AE_MOVF32X2 + 10U, // AE_MOVF64 + 0U, // AE_MOVI + 10U, // AE_MOVT16X4 + 10U, // AE_MOVT32X2 + 10U, // AE_MOVT64 + 0U, // AE_MUL16X4 + 8U, // AE_MUL32U_LL + 8U, // AE_MUL32X16_H0 + 8U, // AE_MUL32X16_H0_S2 + 8U, // AE_MUL32X16_H1 + 8U, // AE_MUL32X16_H1_S2 + 8U, // AE_MUL32X16_H2 + 8U, // AE_MUL32X16_H2_S2 + 8U, // AE_MUL32X16_H3 + 8U, // AE_MUL32X16_H3_S2 + 8U, // AE_MUL32X16_L0 + 8U, // AE_MUL32X16_L0_S2 + 8U, // AE_MUL32X16_L1 + 8U, // AE_MUL32X16_L1_S2 + 8U, // AE_MUL32X16_L2 + 8U, // AE_MUL32X16_L2_S2 + 8U, // AE_MUL32X16_L3 + 8U, // AE_MUL32X16_L3_S2 + 8U, // AE_MUL32_HH + 8U, // AE_MUL32_LH + 8U, // AE_MUL32_LL + 8U, // AE_MUL32_LL_S2 + 11U, // AE_MULA16X4 + 10U, // AE_MULA32U_LL + 10U, // AE_MULA32X16_H0 + 10U, // AE_MULA32X16_H0_S2 + 10U, // AE_MULA32X16_H1 + 10U, // AE_MULA32X16_H1_S2 + 10U, // AE_MULA32X16_H2 + 10U, // AE_MULA32X16_H2_S2 + 10U, // AE_MULA32X16_H3 + 10U, // AE_MULA32X16_H3_S2 + 10U, // AE_MULA32X16_L0 + 10U, // AE_MULA32X16_L0_S2 + 10U, // AE_MULA32X16_L1 + 10U, // AE_MULA32X16_L1_S2 + 10U, // AE_MULA32X16_L2 + 10U, // AE_MULA32X16_L2_S2 + 10U, // AE_MULA32X16_L3 + 10U, // AE_MULA32X16_L3_S2 + 10U, // AE_MULA32_HH + 10U, // AE_MULA32_LH + 10U, // AE_MULA32_LL + 10U, // AE_MULA32_LL_S2 + 10U, // AE_MULAAD24_HH_LL + 10U, // AE_MULAAD24_HH_LL_S2 + 10U, // AE_MULAAD24_HL_LH + 10U, // AE_MULAAD24_HL_LH_S2 + 10U, // AE_MULAAD32X16_H0_L1 + 10U, // AE_MULAAD32X16_H0_L1_S2 + 10U, // AE_MULAAD32X16_H1_L0 + 10U, // AE_MULAAD32X16_H1_L0_S2 + 10U, // AE_MULAAD32X16_H2_L3 + 10U, // AE_MULAAD32X16_H2_L3_S2 + 10U, // AE_MULAAD32X16_H3_L2 + 10U, // AE_MULAAD32X16_H3_L2_S2 + 10U, // AE_MULAAFD16SS_11_00 + 10U, // AE_MULAAFD16SS_11_00_S2 + 10U, // AE_MULAAFD16SS_13_02 + 10U, // AE_MULAAFD16SS_13_02_S2 + 10U, // AE_MULAAFD16SS_33_22 + 10U, // AE_MULAAFD16SS_33_22_S2 + 10U, // AE_MULAAFD24_HH_LL + 10U, // AE_MULAAFD24_HH_LL_S2 + 10U, // AE_MULAAFD24_HL_LH + 10U, // AE_MULAAFD24_HL_LH_S2 + 10U, // AE_MULAAFD32X16_H0_L1 + 10U, // AE_MULAAFD32X16_H0_L1_S2 + 10U, // AE_MULAAFD32X16_H1_L0 + 10U, // AE_MULAAFD32X16_H1_L0_S2 + 10U, // AE_MULAAFD32X16_H2_L3 + 10U, // AE_MULAAFD32X16_H2_L3_S2 + 10U, // AE_MULAAFD32X16_H3_L2 + 10U, // AE_MULAAFD32X16_H3_L2_S2 + 10U, // AE_MULAC24 + 10U, // AE_MULAC32X16_H + 10U, // AE_MULAC32X16_L + 10U, // AE_MULAF16SS_00 + 10U, // AE_MULAF16SS_00_S2 + 10U, // AE_MULAF16SS_10 + 10U, // AE_MULAF16SS_11 + 10U, // AE_MULAF16SS_20 + 10U, // AE_MULAF16SS_21 + 10U, // AE_MULAF16SS_22 + 10U, // AE_MULAF16SS_30 + 10U, // AE_MULAF16SS_31 + 10U, // AE_MULAF16SS_32 + 10U, // AE_MULAF16SS_33 + 11U, // AE_MULAF16X4SS + 10U, // AE_MULAF32R_HH + 10U, // AE_MULAF32R_LH + 10U, // AE_MULAF32R_LL + 10U, // AE_MULAF32R_LL_S2 + 10U, // AE_MULAF32S_HH + 10U, // AE_MULAF32S_LH + 10U, // AE_MULAF32S_LL + 10U, // AE_MULAF32S_LL_S2 + 10U, // AE_MULAF32X16_H0 + 10U, // AE_MULAF32X16_H0_S2 + 10U, // AE_MULAF32X16_H1 + 10U, // AE_MULAF32X16_H1_S2 + 10U, // AE_MULAF32X16_H2 + 10U, // AE_MULAF32X16_H2_S2 + 10U, // AE_MULAF32X16_H3 + 10U, // AE_MULAF32X16_H3_S2 + 10U, // AE_MULAF32X16_L0 + 10U, // AE_MULAF32X16_L0_S2 + 10U, // AE_MULAF32X16_L1 + 10U, // AE_MULAF32X16_L1_S2 + 10U, // AE_MULAF32X16_L2 + 10U, // AE_MULAF32X16_L2_S2 + 10U, // AE_MULAF32X16_L3 + 10U, // AE_MULAF32X16_L3_S2 + 10U, // AE_MULAF48Q32SP16S_L + 10U, // AE_MULAF48Q32SP16S_L_S2 + 10U, // AE_MULAF48Q32SP16U_L + 10U, // AE_MULAF48Q32SP16U_L_S2 + 10U, // AE_MULAFC24RA + 10U, // AE_MULAFC32X16RAS_H + 10U, // AE_MULAFC32X16RAS_L + 387U, // AE_MULAFD24X2_FIR_H + 387U, // AE_MULAFD24X2_FIR_L + 387U, // AE_MULAFD32X16X2_FIR_HH + 387U, // AE_MULAFD32X16X2_FIR_HL + 387U, // AE_MULAFD32X16X2_FIR_LH + 387U, // AE_MULAFD32X16X2_FIR_LL + 10U, // AE_MULAFP24X2R + 10U, // AE_MULAFP24X2RA + 10U, // AE_MULAFP24X2RA_S2 + 10U, // AE_MULAFP24X2R_S2 + 10U, // AE_MULAFP32X16X2RAS_H + 10U, // AE_MULAFP32X16X2RAS_H_S2 + 10U, // AE_MULAFP32X16X2RAS_L + 10U, // AE_MULAFP32X16X2RAS_L_S2 + 10U, // AE_MULAFP32X16X2RS_H + 10U, // AE_MULAFP32X16X2RS_H_S2 + 10U, // AE_MULAFP32X16X2RS_L + 10U, // AE_MULAFP32X16X2RS_L_S2 + 10U, // AE_MULAFP32X2RAS + 10U, // AE_MULAFP32X2RS + 10U, // AE_MULAFQ32SP24S_H_S2 + 10U, // AE_MULAFQ32SP24S_L_S2 + 10U, // AE_MULAP24X2 + 10U, // AE_MULAP24X2_S2 + 10U, // AE_MULAP32X16X2_H + 10U, // AE_MULAP32X16X2_L + 10U, // AE_MULAP32X2 + 10U, // AE_MULAQ32SP16S_L_S2 + 10U, // AE_MULAQ32SP16U_L_S2 + 10U, // AE_MULARFQ32SP24S_H_S2 + 10U, // AE_MULARFQ32SP24S_L_S2 + 10U, // AE_MULAS32F48P16S_HH + 10U, // AE_MULAS32F48P16S_HH_S2 + 10U, // AE_MULAS32F48P16S_LH + 10U, // AE_MULAS32F48P16S_LH_S2 + 10U, // AE_MULAS32F48P16S_LL + 10U, // AE_MULAS32F48P16S_LL_S2 + 10U, // AE_MULASD24_HH_LL + 10U, // AE_MULASD24_HH_LL_S2 + 10U, // AE_MULASD24_HL_LH + 10U, // AE_MULASD24_HL_LH_S2 + 10U, // AE_MULASD32X16_H1_L0 + 10U, // AE_MULASD32X16_H1_L0_S2 + 10U, // AE_MULASD32X16_H3_L2 + 10U, // AE_MULASD32X16_H3_L2_S2 + 10U, // AE_MULASFD24_HH_LL + 10U, // AE_MULASFD24_HH_LL_S2 + 10U, // AE_MULASFD24_HL_LH + 10U, // AE_MULASFD24_HL_LH_S2 + 10U, // AE_MULASFD32X16_H1_L0 + 10U, // AE_MULASFD32X16_H1_L0_S2 + 10U, // AE_MULASFD32X16_H3_L2 + 10U, // AE_MULASFD32X16_H3_L2_S2 + 8U, // AE_MULC24 + 8U, // AE_MULC32X16_H + 8U, // AE_MULC32X16_L + 8U, // AE_MULF16SS_00 + 8U, // AE_MULF16SS_00_S2 + 8U, // AE_MULF16SS_10 + 8U, // AE_MULF16SS_11 + 8U, // AE_MULF16SS_20 + 8U, // AE_MULF16SS_21 + 8U, // AE_MULF16SS_22 + 8U, // AE_MULF16SS_30 + 8U, // AE_MULF16SS_31 + 8U, // AE_MULF16SS_32 + 8U, // AE_MULF16SS_33 + 0U, // AE_MULF16X4SS + 8U, // AE_MULF32R_HH + 8U, // AE_MULF32R_LH + 8U, // AE_MULF32R_LL + 8U, // AE_MULF32R_LL_S2 + 8U, // AE_MULF32S_HH + 8U, // AE_MULF32S_LH + 8U, // AE_MULF32S_LL + 8U, // AE_MULF32S_LL_S2 + 8U, // AE_MULF32X16_H0 + 8U, // AE_MULF32X16_H0_S2 + 8U, // AE_MULF32X16_H1 + 8U, // AE_MULF32X16_H1_S2 + 8U, // AE_MULF32X16_H2 + 8U, // AE_MULF32X16_H2_S2 + 8U, // AE_MULF32X16_H3 + 8U, // AE_MULF32X16_H3_S2 + 8U, // AE_MULF32X16_L0 + 8U, // AE_MULF32X16_L0_S2 + 8U, // AE_MULF32X16_L1 + 8U, // AE_MULF32X16_L1_S2 + 8U, // AE_MULF32X16_L2 + 8U, // AE_MULF32X16_L2_S2 + 8U, // AE_MULF32X16_L3 + 8U, // AE_MULF32X16_L3_S2 + 8U, // AE_MULF48Q32SP16S_L + 8U, // AE_MULF48Q32SP16S_L_S2 + 8U, // AE_MULF48Q32SP16U_L + 8U, // AE_MULF48Q32SP16U_L_S2 + 8U, // AE_MULFC24RA + 8U, // AE_MULFC32X16RAS_H + 8U, // AE_MULFC32X16RAS_L + 35840U, // AE_MULFD24X2_FIR_H + 35840U, // AE_MULFD24X2_FIR_L + 35840U, // AE_MULFD32X16X2_FIR_HH + 35840U, // AE_MULFD32X16X2_FIR_HL + 35840U, // AE_MULFD32X16X2_FIR_LH + 35840U, // AE_MULFD32X16X2_FIR_LL + 8U, // AE_MULFP16X4RAS + 8U, // AE_MULFP16X4S + 8U, // AE_MULFP24X2R + 8U, // AE_MULFP24X2RA + 8U, // AE_MULFP24X2RA_S2 + 8U, // AE_MULFP24X2R_S2 + 8U, // AE_MULFP32X16X2RAS_H + 8U, // AE_MULFP32X16X2RAS_H_S2 + 8U, // AE_MULFP32X16X2RAS_L + 8U, // AE_MULFP32X16X2RAS_L_S2 + 8U, // AE_MULFP32X16X2RS_H + 8U, // AE_MULFP32X16X2RS_H_S2 + 8U, // AE_MULFP32X16X2RS_L + 8U, // AE_MULFP32X16X2RS_L_S2 + 8U, // AE_MULFP32X2RAS + 8U, // AE_MULFP32X2RS + 8U, // AE_MULFQ32SP24S_H_S2 + 8U, // AE_MULFQ32SP24S_L_S2 + 8U, // AE_MULP24X2 + 8U, // AE_MULP24X2_S2 + 8U, // AE_MULP32X16X2_H + 8U, // AE_MULP32X16X2_L + 8U, // AE_MULP32X2 + 8U, // AE_MULQ32SP16S_L_S2 + 8U, // AE_MULQ32SP16U_L_S2 + 8U, // AE_MULRFQ32SP24S_H_S2 + 8U, // AE_MULRFQ32SP24S_L_S2 + 11U, // AE_MULS16X4 + 8U, // AE_MULS32F48P16S_HH + 8U, // AE_MULS32F48P16S_HH_S2 + 8U, // AE_MULS32F48P16S_LH + 8U, // AE_MULS32F48P16S_LH_S2 + 8U, // AE_MULS32F48P16S_LL + 8U, // AE_MULS32F48P16S_LL_S2 + 10U, // AE_MULS32U_LL + 10U, // AE_MULS32X16_H0 + 10U, // AE_MULS32X16_H0_S2 + 10U, // AE_MULS32X16_H1 + 10U, // AE_MULS32X16_H1_S2 + 10U, // AE_MULS32X16_H2 + 10U, // AE_MULS32X16_H2_S2 + 10U, // AE_MULS32X16_H3 + 10U, // AE_MULS32X16_H3_S2 + 10U, // AE_MULS32X16_L0 + 10U, // AE_MULS32X16_L0_S2 + 10U, // AE_MULS32X16_L1 + 10U, // AE_MULS32X16_L1_S2 + 10U, // AE_MULS32X16_L2 + 10U, // AE_MULS32X16_L2_S2 + 10U, // AE_MULS32X16_L3 + 10U, // AE_MULS32X16_L3_S2 + 10U, // AE_MULS32_HH + 10U, // AE_MULS32_LH + 10U, // AE_MULS32_LL + 10U, // AE_MULSAD24_HH_LL + 10U, // AE_MULSAD24_HH_LL_S2 + 10U, // AE_MULSAD32X16_H1_L0 + 10U, // AE_MULSAD32X16_H1_L0_S2 + 10U, // AE_MULSAD32X16_H3_L2 + 10U, // AE_MULSAD32X16_H3_L2_S2 + 10U, // AE_MULSAFD24_HH_LL + 10U, // AE_MULSAFD24_HH_LL_S2 + 10U, // AE_MULSAFD32X16_H1_L0 + 10U, // AE_MULSAFD32X16_H1_L0_S2 + 10U, // AE_MULSAFD32X16_H3_L2 + 10U, // AE_MULSAFD32X16_H3_L2_S2 + 10U, // AE_MULSF16SS_00 + 10U, // AE_MULSF16SS_00_S2 + 10U, // AE_MULSF16SS_10 + 10U, // AE_MULSF16SS_11 + 10U, // AE_MULSF16SS_20 + 10U, // AE_MULSF16SS_21 + 10U, // AE_MULSF16SS_22 + 10U, // AE_MULSF16SS_30 + 10U, // AE_MULSF16SS_31 + 10U, // AE_MULSF16SS_32 + 10U, // AE_MULSF16SS_33 + 11U, // AE_MULSF16X4SS + 10U, // AE_MULSF32R_HH + 10U, // AE_MULSF32R_LH + 10U, // AE_MULSF32R_LL + 10U, // AE_MULSF32R_LL_S2 + 10U, // AE_MULSF32S_HH + 10U, // AE_MULSF32S_LH + 10U, // AE_MULSF32S_LL + 10U, // AE_MULSF32X16_H0 + 10U, // AE_MULSF32X16_H0_S2 + 10U, // AE_MULSF32X16_H1 + 10U, // AE_MULSF32X16_H1_S2 + 10U, // AE_MULSF32X16_H2 + 10U, // AE_MULSF32X16_H2_S2 + 10U, // AE_MULSF32X16_H3 + 10U, // AE_MULSF32X16_H3_S2 + 10U, // AE_MULSF32X16_L0 + 10U, // AE_MULSF32X16_L0_S2 + 10U, // AE_MULSF32X16_L1 + 10U, // AE_MULSF32X16_L1_S2 + 10U, // AE_MULSF32X16_L2 + 10U, // AE_MULSF32X16_L2_S2 + 10U, // AE_MULSF32X16_L3 + 10U, // AE_MULSF32X16_L3_S2 + 10U, // AE_MULSF48Q32SP16S_L + 10U, // AE_MULSF48Q32SP16S_L_S2 + 10U, // AE_MULSF48Q32SP16U_L + 10U, // AE_MULSF48Q32SP16U_L_S2 + 10U, // AE_MULSFP24X2R + 10U, // AE_MULSFP24X2RA + 10U, // AE_MULSFP24X2RA_S2 + 10U, // AE_MULSFP24X2R_S2 + 10U, // AE_MULSFP32X16X2RAS_H + 10U, // AE_MULSFP32X16X2RAS_H_S2 + 10U, // AE_MULSFP32X16X2RAS_L + 10U, // AE_MULSFP32X16X2RAS_L_S2 + 10U, // AE_MULSFP32X16X2RS_H + 10U, // AE_MULSFP32X16X2RS_H_S2 + 10U, // AE_MULSFP32X16X2RS_L + 10U, // AE_MULSFP32X16X2RS_L_S2 + 10U, // AE_MULSFP32X2RAS + 10U, // AE_MULSFP32X2RS + 10U, // AE_MULSFQ32SP24S_H_S2 + 10U, // AE_MULSFQ32SP24S_L_S2 + 10U, // AE_MULSP24X2 + 10U, // AE_MULSP24X2_S2 + 10U, // AE_MULSP32X16X2_H + 10U, // AE_MULSP32X16X2_L + 10U, // AE_MULSP32X2 + 10U, // AE_MULSQ32SP16S_L_S2 + 10U, // AE_MULSQ32SP16U_L_S2 + 10U, // AE_MULSRFQ32SP24S_H_S2 + 10U, // AE_MULSRFQ32SP24S_L_S2 + 10U, // AE_MULSS32F48P16S_HH + 10U, // AE_MULSS32F48P16S_HH_S2 + 10U, // AE_MULSS32F48P16S_LH + 10U, // AE_MULSS32F48P16S_LH_S2 + 10U, // AE_MULSS32F48P16S_LL + 10U, // AE_MULSS32F48P16S_LL_S2 + 10U, // AE_MULSSD24_HH_LL + 10U, // AE_MULSSD24_HH_LL_S2 + 10U, // AE_MULSSD24_HL_LH + 10U, // AE_MULSSD24_HL_LH_S2 + 10U, // AE_MULSSD32X16_H1_L0 + 10U, // AE_MULSSD32X16_H1_L0_S2 + 10U, // AE_MULSSD32X16_H3_L2 + 10U, // AE_MULSSD32X16_H3_L2_S2 + 10U, // AE_MULSSFD16SS_11_00 + 10U, // AE_MULSSFD16SS_11_00_S2 + 10U, // AE_MULSSFD16SS_13_02 + 10U, // AE_MULSSFD16SS_13_02_S2 + 10U, // AE_MULSSFD16SS_33_22 + 10U, // AE_MULSSFD16SS_33_22_S2 + 10U, // AE_MULSSFD24_HH_LL + 10U, // AE_MULSSFD24_HH_LL_S2 + 10U, // AE_MULSSFD24_HL_LH + 10U, // AE_MULSSFD24_HL_LH_S2 + 10U, // AE_MULSSFD32X16_H1_L0 + 10U, // AE_MULSSFD32X16_H1_L0_S2 + 10U, // AE_MULSSFD32X16_H3_L2 + 10U, // AE_MULSSFD32X16_H3_L2_S2 + 8U, // AE_MULZAAD24_HH_LL + 8U, // AE_MULZAAD24_HH_LL_S2 + 8U, // AE_MULZAAD24_HL_LH + 8U, // AE_MULZAAD24_HL_LH_S2 + 8U, // AE_MULZAAD32X16_H0_L1 + 8U, // AE_MULZAAD32X16_H0_L1_S2 + 8U, // AE_MULZAAD32X16_H1_L0 + 8U, // AE_MULZAAD32X16_H1_L0_S2 + 8U, // AE_MULZAAD32X16_H2_L3 + 8U, // AE_MULZAAD32X16_H2_L3_S2 + 8U, // AE_MULZAAD32X16_H3_L2 + 8U, // AE_MULZAAD32X16_H3_L2_S2 + 8U, // AE_MULZAAFD16SS_11_00 + 8U, // AE_MULZAAFD16SS_11_00_S2 + 8U, // AE_MULZAAFD16SS_13_02 + 8U, // AE_MULZAAFD16SS_13_02_S2 + 8U, // AE_MULZAAFD16SS_33_22 + 8U, // AE_MULZAAFD16SS_33_22_S2 + 8U, // AE_MULZAAFD24_HH_LL + 8U, // AE_MULZAAFD24_HH_LL_S2 + 8U, // AE_MULZAAFD24_HL_LH + 8U, // AE_MULZAAFD24_HL_LH_S2 + 8U, // AE_MULZAAFD32X16_H0_L1 + 8U, // AE_MULZAAFD32X16_H0_L1_S2 + 8U, // AE_MULZAAFD32X16_H1_L0 + 8U, // AE_MULZAAFD32X16_H1_L0_S2 + 8U, // AE_MULZAAFD32X16_H2_L3 + 8U, // AE_MULZAAFD32X16_H2_L3_S2 + 8U, // AE_MULZAAFD32X16_H3_L2 + 8U, // AE_MULZAAFD32X16_H3_L2_S2 + 8U, // AE_MULZASD24_HH_LL + 8U, // AE_MULZASD24_HH_LL_S2 + 8U, // AE_MULZASD24_HL_LH + 8U, // AE_MULZASD24_HL_LH_S2 + 8U, // AE_MULZASD32X16_H1_L0 + 8U, // AE_MULZASD32X16_H1_L0_S2 + 8U, // AE_MULZASD32X16_H3_L2 + 8U, // AE_MULZASD32X16_H3_L2_S2 + 8U, // AE_MULZASFD24_HH_LL + 8U, // AE_MULZASFD24_HH_LL_S2 + 8U, // AE_MULZASFD24_HL_LH + 8U, // AE_MULZASFD24_HL_LH_S2 + 8U, // AE_MULZASFD32X16_H1_L0 + 8U, // AE_MULZASFD32X16_H1_L0_S2 + 8U, // AE_MULZASFD32X16_H3_L2 + 8U, // AE_MULZASFD32X16_H3_L2_S2 + 8U, // AE_MULZSAD24_HH_LL + 8U, // AE_MULZSAD24_HH_LL_S2 + 8U, // AE_MULZSAD32X16_H1_L0 + 8U, // AE_MULZSAD32X16_H1_L0_S2 + 8U, // AE_MULZSAD32X16_H3_L2 + 8U, // AE_MULZSAD32X16_H3_L2_S2 + 8U, // AE_MULZSAFD24_HH_LL + 8U, // AE_MULZSAFD24_HH_LL_S2 + 8U, // AE_MULZSAFD32X16_H1_L0 + 8U, // AE_MULZSAFD32X16_H1_L0_S2 + 8U, // AE_MULZSAFD32X16_H3_L2 + 8U, // AE_MULZSAFD32X16_H3_L2_S2 + 8U, // AE_MULZSSD24_HH_LL + 8U, // AE_MULZSSD24_HH_LL_S2 + 8U, // AE_MULZSSD24_HL_LH + 8U, // AE_MULZSSD24_HL_LH_S2 + 8U, // AE_MULZSSD32X16_H1_L0 + 8U, // AE_MULZSSD32X16_H1_L0_S2 + 8U, // AE_MULZSSD32X16_H3_L2 + 8U, // AE_MULZSSD32X16_H3_L2_S2 + 8U, // AE_MULZSSFD16SS_11_00 + 8U, // AE_MULZSSFD16SS_11_00_S2 + 8U, // AE_MULZSSFD16SS_13_02 + 8U, // AE_MULZSSFD16SS_13_02_S2 + 8U, // AE_MULZSSFD16SS_33_22 + 8U, // AE_MULZSSFD16SS_33_22_S2 + 8U, // AE_MULZSSFD24_HH_LL + 8U, // AE_MULZSSFD24_HH_LL_S2 + 8U, // AE_MULZSSFD24_HL_LH + 8U, // AE_MULZSSFD24_HL_LH_S2 + 8U, // AE_MULZSSFD32X16_H1_L0 + 8U, // AE_MULZSSFD32X16_H1_L0_S2 + 8U, // AE_MULZSSFD32X16_H3_L2 + 8U, // AE_MULZSSFD32X16_H3_L2_S2 + 8U, // AE_NAND + 0U, // AE_NEG16S + 0U, // AE_NEG24S + 0U, // AE_NEG32 + 0U, // AE_NEG32S + 0U, // AE_NEG64 + 0U, // AE_NEG64S + 0U, // AE_NSA64 + 0U, // AE_NSAZ16_0 + 0U, // AE_NSAZ32_L + 8U, // AE_OR + 3U, // AE_PKSR24 + 3U, // AE_PKSR32 + 8U, // AE_ROUND16X4F32SASYM + 8U, // AE_ROUND16X4F32SSYM + 8U, // AE_ROUND24X2F48SASYM + 8U, // AE_ROUND24X2F48SSYM + 8U, // AE_ROUND32X2F48SASYM + 8U, // AE_ROUND32X2F48SSYM + 8U, // AE_ROUND32X2F64SASYM + 8U, // AE_ROUND32X2F64SSYM + 0U, // AE_ROUNDSP16F24ASYM + 0U, // AE_ROUNDSP16F24SYM + 8U, // AE_ROUNDSP16Q48X2ASYM + 8U, // AE_ROUNDSP16Q48X2SYM + 0U, // AE_ROUNDSQ32F48ASYM + 0U, // AE_ROUNDSQ32F48SYM + 1U, // AE_S16M_L_I + 1U, // AE_S16M_L_IU + 8U, // AE_S16M_L_X + 10U, // AE_S16M_L_XC + 10U, // AE_S16M_L_XU + 2U, // AE_S16X2M_I + 2U, // AE_S16X2M_IU + 8U, // AE_S16X2M_X + 10U, // AE_S16X2M_XC + 10U, // AE_S16X2M_XU + 2U, // AE_S16X4_I + 2U, // AE_S16X4_IP + 0U, // AE_S16X4_RIC + 0U, // AE_S16X4_RIP + 8U, // AE_S16X4_X + 10U, // AE_S16X4_XC + 10U, // AE_S16X4_XP + 1U, // AE_S16_0_I + 1U, // AE_S16_0_IP + 8U, // AE_S16_0_X + 10U, // AE_S16_0_XC + 10U, // AE_S16_0_XP + 2U, // AE_S24RA64S_I + 2U, // AE_S24RA64S_IP + 8U, // AE_S24RA64S_X + 10U, // AE_S24RA64S_XC + 10U, // AE_S24RA64S_XP + 10U, // AE_S24X2RA64S_IP + 2U, // AE_S32F24_L_I + 2U, // AE_S32F24_L_IP + 8U, // AE_S32F24_L_X + 10U, // AE_S32F24_L_XC + 10U, // AE_S32F24_L_XP + 2U, // AE_S32M_I + 2U, // AE_S32M_IU + 8U, // AE_S32M_X + 10U, // AE_S32M_XC + 10U, // AE_S32M_XU + 2U, // AE_S32RA64S_I + 2U, // AE_S32RA64S_IP + 8U, // AE_S32RA64S_X + 10U, // AE_S32RA64S_XC + 10U, // AE_S32RA64S_XP + 2U, // AE_S32X2F24_I + 2U, // AE_S32X2F24_IP + 0U, // AE_S32X2F24_RIC + 0U, // AE_S32X2F24_RIP + 8U, // AE_S32X2F24_X + 10U, // AE_S32X2F24_XC + 10U, // AE_S32X2F24_XP + 10U, // AE_S32X2RA64S_IP + 2U, // AE_S32X2_I + 2U, // AE_S32X2_IP + 0U, // AE_S32X2_RIC + 0U, // AE_S32X2_RIP + 8U, // AE_S32X2_X + 10U, // AE_S32X2_XC + 10U, // AE_S32X2_XP + 2U, // AE_S32_L_I + 2U, // AE_S32_L_IP + 8U, // AE_S32_L_X + 10U, // AE_S32_L_XC + 10U, // AE_S32_L_XP + 2U, // AE_S64_I + 2U, // AE_S64_IP + 8U, // AE_S64_X + 10U, // AE_S64_XC + 10U, // AE_S64_XP + 0U, // AE_SA16X4_IC + 0U, // AE_SA16X4_IP + 0U, // AE_SA16X4_RIC + 0U, // AE_SA16X4_RIP + 0U, // AE_SA24X2_IC + 0U, // AE_SA24X2_IP + 0U, // AE_SA24X2_RIC + 0U, // AE_SA24X2_RIP + 0U, // AE_SA24_L_IC + 0U, // AE_SA24_L_IP + 0U, // AE_SA24_L_RIC + 0U, // AE_SA24_L_RIP + 0U, // AE_SA32X2F24_IC + 0U, // AE_SA32X2F24_IP + 0U, // AE_SA32X2F24_RIC + 0U, // AE_SA32X2F24_RIP + 0U, // AE_SA32X2_IC + 0U, // AE_SA32X2_IP + 0U, // AE_SA32X2_RIC + 0U, // AE_SA32X2_RIP + 0U, // AE_SA64NEG_FP + 0U, // AE_SA64POS_FP + 2U, // AE_SALIGN64_I + 8U, // AE_SAT16X4 + 0U, // AE_SAT24S + 0U, // AE_SAT48S + 0U, // AE_SATQ56S + 0U, // AE_SB + 0U, // AE_SBF + 0U, // AE_SBF_IC + 0U, // AE_SBF_IP + 3U, // AE_SBI + 3U, // AE_SBI_IC + 3U, // AE_SBI_IP + 0U, // AE_SB_IC + 0U, // AE_SB_IP + 448U, // AE_SEL16I + 512U, // AE_SEL16I_N + 3U, // AE_SEXT32 + 0U, // AE_SEXT32X2D16_10 + 0U, // AE_SEXT32X2D16_32 + 0U, // AE_SHA32 + 0U, // AE_SHORTSWAP + 8U, // AE_SLAA16S + 8U, // AE_SLAA32 + 8U, // AE_SLAA32S + 8U, // AE_SLAA64 + 8U, // AE_SLAA64S + 8U, // AE_SLAAQ56 + 3U, // AE_SLAI16S + 11U, // AE_SLAI24 + 11U, // AE_SLAI24S + 11U, // AE_SLAI32 + 11U, // AE_SLAI32S + 3U, // AE_SLAI64 + 3U, // AE_SLAI64S + 3U, // AE_SLAISQ56S + 0U, // AE_SLAS24 + 0U, // AE_SLAS24S + 0U, // AE_SLAS32 + 0U, // AE_SLAS32S + 0U, // AE_SLAS64 + 0U, // AE_SLAS64S + 0U, // AE_SLASQ56 + 0U, // AE_SLASSQ56S + 8U, // AE_SRA64_32 + 8U, // AE_SRAA16RS + 8U, // AE_SRAA16S + 8U, // AE_SRAA32 + 8U, // AE_SRAA32RS + 8U, // AE_SRAA32S + 8U, // AE_SRAA64 + 3U, // AE_SRAI16 + 3U, // AE_SRAI16R + 11U, // AE_SRAI24 + 11U, // AE_SRAI32 + 11U, // AE_SRAI32R + 3U, // AE_SRAI64 + 0U, // AE_SRAS24 + 0U, // AE_SRAS32 + 0U, // AE_SRAS64 + 8U, // AE_SRLA32 + 8U, // AE_SRLA64 + 11U, // AE_SRLI24 + 11U, // AE_SRLI32 + 3U, // AE_SRLI64 + 0U, // AE_SRLS24 + 0U, // AE_SRLS32 + 0U, // AE_SRLS64 + 8U, // AE_SUB16 + 8U, // AE_SUB16S + 8U, // AE_SUB24S + 8U, // AE_SUB32 + 8U, // AE_SUB32S + 8U, // AE_SUB64 + 8U, // AE_SUB64S + 8U, // AE_SUBADD32 + 8U, // AE_SUBADD32S + 0U, // AE_TRUNCA32F64S_L + 0U, // AE_TRUNCA32X2F64S + 448U, // AE_TRUNCI32F64S_L + 448U, // AE_TRUNCI32X2F64S + 0U, // AE_VLDL16C + 0U, // AE_VLDL16C_IC + 0U, // AE_VLDL16C_IP + 8U, // AE_VLDL16T + 8U, // AE_VLDL32T + 0U, // AE_VLDSHT + 10U, // AE_VLEL16T + 10U, // AE_VLEL32T + 0U, // AE_VLES16C + 0U, // AE_VLES16C_IC + 0U, // AE_VLES16C_IP + 8U, // AE_XOR + 0U, // AE_ZALIGN64 + 0U, // ALL4 + 0U, // ALL8 + 8U, // AND + 8U, // ANDB + 8U, // ANDBC + 0U, // ANY4 + 0U, // ANY8 + 3U, // BALL + 3U, // BANY + 3U, // BBC 0U, // BBCI - 14U, // BBS + 3U, // BBS 0U, // BBSI - 14U, // BEQ + 3U, // BEQ 0U, // BEQI 0U, // BEQZ - 14U, // BGE + 0U, // BF + 3U, // BGE 0U, // BGEI - 14U, // BGEU - 1U, // BGEUI + 3U, // BGEU + 0U, // BGEUI 0U, // BGEZ - 14U, // BLT + 3U, // BLT 0U, // BLTI - 14U, // BLTU - 1U, // BLTUI + 3U, // BLTU + 0U, // BLTUI 0U, // BLTZ - 14U, // BNALL - 14U, // BNE + 3U, // BNALL + 3U, // BNE 0U, // BNEI 0U, // BNEZ - 14U, // BNONE + 3U, // BNONE + 0U, // BREAK + 0U, // BREAK_N + 0U, // BT 0U, // CALL0 + 0U, // CALL12 + 0U, // CALL4 + 0U, // CALL8 0U, // CALLX0 + 0U, // CALLX12 + 0U, // CALLX4 + 0U, // CALLX8 + 3U, // CEIL_S + 3U, // CLAMPS + 0U, // CLR_BIT_GPIO_OUT + 0U, // CONST_S + 0U, // DIV0_S + 10U, // DIVN_S 0U, // DSYNC + 8U, // EE_ANDQ + 0U, // EE_BITREV + 0U, // EE_CLR_BIT_GPIO_OUT + 192U, // EE_CMUL_S16 + 20U, // EE_CMUL_S16_LD_INCP + 580U, // EE_CMUL_S16_ST_INCP + 13312U, // EE_FFT_AMS_S16_LD_INCP + 13312U, // EE_FFT_AMS_S16_LD_INCP_UAUP + 13312U, // EE_FFT_AMS_S16_LD_R32_DECP + 0U, // EE_FFT_AMS_S16_ST_INCP + 28U, // EE_FFT_CMUL_S16_LD_XP + 13954U, // EE_FFT_CMUL_S16_ST_XP + 5120U, // EE_FFT_R2BF_S16 + 16002U, // EE_FFT_R2BF_S16_ST_INCP + 4U, // EE_FFT_VST_R32_DECP + 0U, // EE_GET_GPIO_IN + 13312U, // EE_LDF_128_IP + 13312U, // EE_LDF_128_XP + 706U, // EE_LDF_64_IP + 642U, // EE_LDF_64_XP + 0U, // EE_LDQA_S16_128_IP + 0U, // EE_LDQA_S16_128_XP + 0U, // EE_LDQA_S8_128_IP + 0U, // EE_LDQA_S8_128_XP + 0U, // EE_LDQA_U16_128_IP + 0U, // EE_LDQA_U16_128_XP + 0U, // EE_LDQA_U8_128_IP + 0U, // EE_LDQA_U8_128_XP + 9408U, // EE_LDXQ_32 + 4U, // EE_LD_128_USAR_IP + 10U, // EE_LD_128_USAR_XP + 0U, // EE_LD_ACCX_IP + 0U, // EE_LD_QACC_H_H_32_IP + 0U, // EE_LD_QACC_H_L_128_IP + 0U, // EE_LD_QACC_L_H_32_IP + 0U, // EE_LD_QACC_L_L_128_IP + 0U, // EE_LD_UA_STATE_IP + 0U, // EE_MOVI_32_A + 0U, // EE_MOVI_32_Q + 0U, // EE_MOV_S16_QACC + 0U, // EE_MOV_S8_QACC + 0U, // EE_MOV_U16_QACC + 0U, // EE_MOV_U8_QACC + 0U, // EE_NOTQ + 8U, // EE_ORQ + 0U, // EE_SET_BIT_GPIO_OUT + 0U, // EE_SLCI_2Q + 0U, // EE_SLCXXP_2Q + 0U, // EE_SRCI_2Q + 0U, // EE_SRCMB_S16_QACC + 0U, // EE_SRCMB_S8_QACC + 10U, // EE_SRCQ_128_ST_INCP + 0U, // EE_SRCXXP_2Q + 8U, // EE_SRC_Q + 0U, // EE_SRC_Q_LD_IP + 804U, // EE_SRC_Q_LD_XP + 10U, // EE_SRC_Q_QUP + 0U, // EE_SRS_ACCX + 13954U, // EE_STF_128_IP + 13954U, // EE_STF_128_XP + 706U, // EE_STF_64_IP + 642U, // EE_STF_64_XP + 9408U, // EE_STXQ_32 + 0U, // EE_ST_ACCX_IP + 0U, // EE_ST_QACC_H_H_32_IP + 0U, // EE_ST_QACC_H_L_128_IP + 0U, // EE_ST_QACC_L_H_32_IP + 0U, // EE_ST_QACC_L_L_128_IP + 0U, // EE_ST_UA_STATE_IP + 8U, // EE_VADDS_S16 + 2U, // EE_VADDS_S16_LD_INCP + 12U, // EE_VADDS_S16_ST_INCP + 8U, // EE_VADDS_S32 + 2U, // EE_VADDS_S32_LD_INCP + 12U, // EE_VADDS_S32_ST_INCP + 8U, // EE_VADDS_S8 + 2U, // EE_VADDS_S8_LD_INCP + 12U, // EE_VADDS_S8_ST_INCP + 8U, // EE_VCMP_EQ_S16 + 8U, // EE_VCMP_EQ_S32 + 8U, // EE_VCMP_EQ_S8 + 8U, // EE_VCMP_GT_S16 + 8U, // EE_VCMP_GT_S32 + 8U, // EE_VCMP_GT_S8 + 8U, // EE_VCMP_LT_S16 + 8U, // EE_VCMP_LT_S32 + 8U, // EE_VCMP_LT_S8 + 0U, // EE_VLDBC_16 + 4U, // EE_VLDBC_16_IP + 10U, // EE_VLDBC_16_XP + 0U, // EE_VLDBC_32 + 4U, // EE_VLDBC_32_IP + 10U, // EE_VLDBC_32_XP + 0U, // EE_VLDBC_8 + 4U, // EE_VLDBC_8_IP + 10U, // EE_VLDBC_8_XP + 10U, // EE_VLDHBC_16_INCP + 4U, // EE_VLD_128_IP + 10U, // EE_VLD_128_XP + 4U, // EE_VLD_H_64_IP + 10U, // EE_VLD_H_64_XP + 4U, // EE_VLD_L_64_IP + 10U, // EE_VLD_L_64_XP + 8U, // EE_VMAX_S16 + 2U, // EE_VMAX_S16_LD_INCP + 12U, // EE_VMAX_S16_ST_INCP + 8U, // EE_VMAX_S32 + 2U, // EE_VMAX_S32_LD_INCP + 12U, // EE_VMAX_S32_ST_INCP + 8U, // EE_VMAX_S8 + 2U, // EE_VMAX_S8_LD_INCP + 12U, // EE_VMAX_S8_ST_INCP + 8U, // EE_VMIN_S16 + 2U, // EE_VMIN_S16_LD_INCP + 12U, // EE_VMIN_S16_ST_INCP + 8U, // EE_VMIN_S32 + 2U, // EE_VMIN_S32_LD_INCP + 12U, // EE_VMIN_S32_ST_INCP + 8U, // EE_VMIN_S8 + 2U, // EE_VMIN_S8_LD_INCP + 12U, // EE_VMIN_S8_ST_INCP + 0U, // EE_VMULAS_S16_ACCX + 5U, // EE_VMULAS_S16_ACCX_LD_IP + 0U, // EE_VMULAS_S16_ACCX_LD_IP_QUP + 46722U, // EE_VMULAS_S16_ACCX_LD_XP + 18276U, // EE_VMULAS_S16_ACCX_LD_XP_QUP + 0U, // EE_VMULAS_S16_QACC + 642U, // EE_VMULAS_S16_QACC_LDBC_INCP + 868U, // EE_VMULAS_S16_QACC_LDBC_INCP_QUP + 5U, // EE_VMULAS_S16_QACC_LD_IP + 0U, // EE_VMULAS_S16_QACC_LD_IP_QUP + 46722U, // EE_VMULAS_S16_QACC_LD_XP + 18276U, // EE_VMULAS_S16_QACC_LD_XP_QUP + 0U, // EE_VMULAS_S8_ACCX + 5U, // EE_VMULAS_S8_ACCX_LD_IP + 0U, // EE_VMULAS_S8_ACCX_LD_IP_QUP + 46722U, // EE_VMULAS_S8_ACCX_LD_XP + 18276U, // EE_VMULAS_S8_ACCX_LD_XP_QUP + 0U, // EE_VMULAS_S8_QACC + 642U, // EE_VMULAS_S8_QACC_LDBC_INCP + 868U, // EE_VMULAS_S8_QACC_LDBC_INCP_QUP + 5U, // EE_VMULAS_S8_QACC_LD_IP + 0U, // EE_VMULAS_S8_QACC_LD_IP_QUP + 46722U, // EE_VMULAS_S8_QACC_LD_XP + 18276U, // EE_VMULAS_S8_QACC_LD_XP_QUP + 0U, // EE_VMULAS_U16_ACCX + 5U, // EE_VMULAS_U16_ACCX_LD_IP + 0U, // EE_VMULAS_U16_ACCX_LD_IP_QUP + 46722U, // EE_VMULAS_U16_ACCX_LD_XP + 18276U, // EE_VMULAS_U16_ACCX_LD_XP_QUP + 0U, // EE_VMULAS_U16_QACC + 642U, // EE_VMULAS_U16_QACC_LDBC_INCP + 868U, // EE_VMULAS_U16_QACC_LDBC_INCP_QUP + 5U, // EE_VMULAS_U16_QACC_LD_IP + 0U, // EE_VMULAS_U16_QACC_LD_IP_QUP + 46722U, // EE_VMULAS_U16_QACC_LD_XP + 18276U, // EE_VMULAS_U16_QACC_LD_XP_QUP + 0U, // EE_VMULAS_U8_ACCX + 5U, // EE_VMULAS_U8_ACCX_LD_IP + 0U, // EE_VMULAS_U8_ACCX_LD_IP_QUP + 46722U, // EE_VMULAS_U8_ACCX_LD_XP + 18276U, // EE_VMULAS_U8_ACCX_LD_XP_QUP + 0U, // EE_VMULAS_U8_QACC + 642U, // EE_VMULAS_U8_QACC_LDBC_INCP + 868U, // EE_VMULAS_U8_QACC_LDBC_INCP_QUP + 5U, // EE_VMULAS_U8_QACC_LD_IP + 0U, // EE_VMULAS_U8_QACC_LD_IP_QUP + 46722U, // EE_VMULAS_U8_QACC_LD_XP + 18276U, // EE_VMULAS_U8_QACC_LD_XP_QUP + 8U, // EE_VMUL_S16 + 2U, // EE_VMUL_S16_LD_INCP + 12U, // EE_VMUL_S16_ST_INCP + 8U, // EE_VMUL_S8 + 2U, // EE_VMUL_S8_LD_INCP + 12U, // EE_VMUL_S8_ST_INCP + 8U, // EE_VMUL_U16 + 2U, // EE_VMUL_U16_LD_INCP + 12U, // EE_VMUL_U16_ST_INCP + 8U, // EE_VMUL_U8 + 2U, // EE_VMUL_U8_LD_INCP + 12U, // EE_VMUL_U8_ST_INCP + 0U, // EE_VPRELU_S16 + 0U, // EE_VPRELU_S8 + 10U, // EE_VRELU_S16 + 10U, // EE_VRELU_S8 + 0U, // EE_VSL_32 + 1U, // EE_VSMULAS_S16_QACC + 20098U, // EE_VSMULAS_S16_QACC_LD_INCP + 0U, // EE_VSMULAS_S8_QACC + 22146U, // EE_VSMULAS_S8_QACC_LD_INCP + 0U, // EE_VSR_32 + 4U, // EE_VST_128_IP + 10U, // EE_VST_128_XP + 4U, // EE_VST_H_64_IP + 10U, // EE_VST_H_64_XP + 4U, // EE_VST_L_64_IP + 10U, // EE_VST_L_64_XP + 8U, // EE_VSUBS_S16 + 2U, // EE_VSUBS_S16_LD_INCP + 12U, // EE_VSUBS_S16_ST_INCP + 8U, // EE_VSUBS_S32 + 2U, // EE_VSUBS_S32_LD_INCP + 12U, // EE_VSUBS_S32_ST_INCP + 8U, // EE_VSUBS_S8 + 2U, // EE_VSUBS_S8_LD_INCP + 12U, // EE_VSUBS_S8_ST_INCP + 0U, // EE_VUNZIP_16 + 0U, // EE_VUNZIP_32 + 0U, // EE_VUNZIP_8 + 0U, // EE_VZIP_16 + 0U, // EE_VZIP_32 + 0U, // EE_VZIP_8 + 0U, // EE_WR_MASK_GPIO_OUT + 8U, // EE_XORQ + 0U, // EE_ZERO_ACCX + 0U, // EE_ZERO_Q + 0U, // EE_ZERO_QACC + 0U, // ENTRY 0U, // ESYNC - 18U, // EXTUI + 0U, // EXCW + 899U, // EXTUI 0U, // EXTW + 3U, // FLOAT_S + 3U, // FLOOR_S + 0U, // GET_GPIO_IN + 0U, // ILL + 0U, // ILL_N 0U, // ISYNC 0U, // J 0U, // JX - 1U, // L16SI - 1U, // L16UI - 1U, // L32I - 1U, // L32R - 1U, // L8UI + 0U, // L16SI + 0U, // L16UI + 5U, // L32E + 0U, // L32I + 0U, // L32I_N + 0U, // L32R + 0U, // L8UI + 0U, // LDDEC + 0U, // LDINC + 0U, // LEA_ADD + 0U, // LOOP + 0U, // LOOPGTZ + 0U, // LOOPNEZ + 0U, // LSI + 5U, // LSIP + 8U, // LSX + 10U, // LSXP + 10U, // MADDN_S + 10U, // MADD_S + 8U, // MAX + 8U, // MAXU 0U, // MEMW - 2U, // MOVEQZ - 2U, // MOVGEZ - 1U, // MOVI - 2U, // MOVLTZ - 2U, // MOVNEZ + 8U, // MIN + 8U, // MINU + 0U, // MKDADJ_S + 0U, // MKSADJ_S + 8U, // MOVEQZ + 10U, // MOVEQZ_S + 10U, // MOVF + 10U, // MOVF_S + 8U, // MOVGEZ + 10U, // MOVGEZ_S + 0U, // MOVI + 0U, // MOVI_N + 8U, // MOVLTZ + 10U, // MOVLTZ_S + 8U, // MOVNEZ + 10U, // MOVNEZ_S + 0U, // MOVSP + 10U, // MOVT + 10U, // MOVT_S + 0U, // MOV_N + 0U, // MOV_S + 10U, // MSUB_S + 8U, // MUL16S + 8U, // MUL16U + 0U, // MULA_AA_HH + 0U, // MULA_AA_HL + 0U, // MULA_AA_LH + 0U, // MULA_AA_LL + 0U, // MULA_AD_HH + 0U, // MULA_AD_HL + 0U, // MULA_AD_LH + 0U, // MULA_AD_LL + 0U, // MULA_DA_HH + 642U, // MULA_DA_HH_LDDEC + 642U, // MULA_DA_HH_LDINC + 0U, // MULA_DA_HL + 642U, // MULA_DA_HL_LDDEC + 642U, // MULA_DA_HL_LDINC + 0U, // MULA_DA_LH + 642U, // MULA_DA_LH_LDDEC + 642U, // MULA_DA_LH_LDINC + 0U, // MULA_DA_LL + 642U, // MULA_DA_LL_LDDEC + 642U, // MULA_DA_LL_LDINC + 0U, // MULA_DD_HH + 642U, // MULA_DD_HH_LDDEC + 642U, // MULA_DD_HH_LDINC + 0U, // MULA_DD_HL + 642U, // MULA_DD_HL_LDDEC + 642U, // MULA_DD_HL_LDINC + 0U, // MULA_DD_LH + 642U, // MULA_DD_LH_LDDEC + 642U, // MULA_DD_LH_LDINC + 0U, // MULA_DD_LL + 642U, // MULA_DD_LL_LDDEC + 642U, // MULA_DD_LL_LDINC + 8U, // MULL + 8U, // MULSH + 0U, // MULS_AA_HH + 0U, // MULS_AA_HL + 0U, // MULS_AA_LH + 0U, // MULS_AA_LL + 0U, // MULS_AD_HH + 0U, // MULS_AD_HL + 0U, // MULS_AD_LH + 0U, // MULS_AD_LL + 0U, // MULS_DA_HH + 0U, // MULS_DA_HL + 0U, // MULS_DA_LH + 0U, // MULS_DA_LL + 0U, // MULS_DD_HH + 0U, // MULS_DD_HL + 0U, // MULS_DD_LH + 0U, // MULS_DD_LL + 8U, // MULUH + 0U, // MUL_AA_HH + 0U, // MUL_AA_HL + 0U, // MUL_AA_LH + 0U, // MUL_AA_LL + 0U, // MUL_AD_HH + 0U, // MUL_AD_HL + 0U, // MUL_AD_LH + 0U, // MUL_AD_LL + 0U, // MUL_DA_HH + 0U, // MUL_DA_HL + 0U, // MUL_DA_LH + 0U, // MUL_DA_LL + 0U, // MUL_DD_HH + 0U, // MUL_DD_HL + 0U, // MUL_DD_LH + 0U, // MUL_DD_LL + 8U, // MUL_S 0U, // NEG + 0U, // NEG_S + 0U, // NEXP01_S 0U, // NOP - 2U, // OR + 0U, // NSA + 0U, // NSAU + 8U, // OEQ_S + 8U, // OLE_S + 8U, // OLT_S + 8U, // OR + 8U, // ORB + 8U, // ORBC + 8U, // QUOS + 8U, // QUOU + 0U, // RECIP0_S + 8U, // REMS + 8U, // REMU + 0U, // RER 0U, // RET + 0U, // RETW + 0U, // RETW_N + 0U, // RET_N + 0U, // RFDE + 0U, // RFE + 0U, // RFI + 0U, // RFR + 0U, // RFWO + 0U, // RFWU + 0U, // ROTW + 3U, // ROUND_S + 0U, // RSIL + 0U, // RSQRT0_S 0U, // RSR 0U, // RSYNC - 1U, // S16I - 1U, // S32I - 1U, // S8I + 0U, // RUR + 0U, // RUR_ACCX_0 + 0U, // RUR_ACCX_1 + 0U, // RUR_AE_BITHEAD + 0U, // RUR_AE_BITPTR + 0U, // RUR_AE_BITSUSED + 0U, // RUR_AE_CBEGIN0 + 0U, // RUR_AE_CEND0 + 0U, // RUR_AE_CWRAP + 0U, // RUR_AE_CW_SD_NO + 0U, // RUR_AE_FIRST_TS + 0U, // RUR_AE_NEXTOFFSET + 0U, // RUR_AE_OVERFLOW + 0U, // RUR_AE_OVF_SAR + 0U, // RUR_AE_SAR + 0U, // RUR_AE_SEARCHDONE + 0U, // RUR_AE_TABLESIZE + 0U, // RUR_AE_TS_FTS_BU_BP + 0U, // RUR_FFT_BIT_WIDTH + 0U, // RUR_GPIO_OUT + 0U, // RUR_QACC_H_0 + 0U, // RUR_QACC_H_1 + 0U, // RUR_QACC_H_2 + 0U, // RUR_QACC_H_3 + 0U, // RUR_QACC_H_4 + 0U, // RUR_QACC_L_0 + 0U, // RUR_QACC_L_1 + 0U, // RUR_QACC_L_2 + 0U, // RUR_QACC_L_3 + 0U, // RUR_QACC_L_4 + 0U, // RUR_SAR_BYTE + 0U, // RUR_UA_STATE_0 + 0U, // RUR_UA_STATE_1 + 0U, // RUR_UA_STATE_2 + 0U, // RUR_UA_STATE_3 + 0U, // S16I + 0U, // S32C1I + 5U, // S32E + 0U, // S32I + 0U, // S32I_N + 0U, // S8I + 0U, // SET_BIT_GPIO_OUT + 3U, // SEXT + 0U, // SIMCALL 0U, // SLL - 22U, // SLLI + 5U, // SLLI + 0U, // SQRT0_S 0U, // SRA - 50U, // SRAI - 2U, // SRC + 11U, // SRAI + 8U, // SRC 0U, // SRL - 26U, // SRLI + 11U, // SRLI 0U, // SSA8L 0U, // SSAI + 0U, // SSI + 5U, // SSIP 0U, // SSL 0U, // SSR - 2U, // SUB - 2U, // SUBX2 - 2U, // SUBX4 - 2U, // SUBX8 + 8U, // SSX + 10U, // SSXP + 8U, // SUB + 8U, // SUBX2 + 8U, // SUBX4 + 8U, // SUBX8 + 8U, // SUB_S + 0U, // SYSCALL + 3U, // TRUNC_S + 8U, // UEQ_S + 3U, // UFLOAT_S + 8U, // ULE_S + 8U, // ULT_S + 0U, // UMUL_AA_HH + 0U, // UMUL_AA_HL + 0U, // UMUL_AA_LH + 0U, // UMUL_AA_LL + 8U, // UN_S + 3U, // UTRUNC_S + 0U, // WAITI + 0U, // WDTLB + 0U, // WER + 0U, // WFR + 0U, // WITLB + 0U, // WR_MASK_GPIO_OUT 0U, // WSR - 2U, // XOR + 0U, // WUR + 0U, // WUR_ACCX_0 + 0U, // WUR_ACCX_1 + 0U, // WUR_AE_BITHEAD + 0U, // WUR_AE_BITPTR + 0U, // WUR_AE_BITSUSED + 0U, // WUR_AE_CBEGIN0 + 0U, // WUR_AE_CEND0 + 0U, // WUR_AE_CWRAP + 0U, // WUR_AE_CW_SD_NO + 0U, // WUR_AE_FIRST_TS + 0U, // WUR_AE_NEXTOFFSET + 0U, // WUR_AE_OVERFLOW + 0U, // WUR_AE_OVF_SAR + 0U, // WUR_AE_SAR + 0U, // WUR_AE_SEARCHDONE + 0U, // WUR_AE_TABLESIZE + 0U, // WUR_AE_TS_FTS_BU_BP + 0U, // WUR_FCR + 0U, // WUR_FFT_BIT_WIDTH + 0U, // WUR_FSR + 0U, // WUR_GPIO_OUT + 0U, // WUR_QACC_H_0 + 0U, // WUR_QACC_H_1 + 0U, // WUR_QACC_H_2 + 0U, // WUR_QACC_H_3 + 0U, // WUR_QACC_H_4 + 0U, // WUR_QACC_L_0 + 0U, // WUR_QACC_L_1 + 0U, // WUR_QACC_L_2 + 0U, // WUR_QACC_L_3 + 0U, // WUR_QACC_L_4 + 0U, // WUR_SAR_BYTE + 0U, // WUR_UA_STATE_0 + 0U, // WUR_UA_STATE_1 + 0U, // WUR_UA_STATE_2 + 0U, // WUR_UA_STATE_3 + 8U, // XOR + 8U, // XORB 0U, // XSR + 0U, // _L32I + 0U, // _L32I_N + 0U, // _MOVI + 0U, // _S32I + 0U, // _S32I_N + 5U, // _SLLI + 3U, // _SRLI + 0U, // mv_QR + }; + + static const uint8_t OpInfo2[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // JUMP_TABLE_DEBUG_INFO + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_CONSTANT_POOL + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_CONSTANT_FOLD_BARRIER + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_PREFETCH + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_INTRINSIC_CONVERGENT + 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FEXP10 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FLDEXP + 0U, // G_FFREXP + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_GET_FPENV + 0U, // G_SET_FPENV + 0U, // G_RESET_FPENV + 0U, // G_GET_FPMODE + 0U, // G_SET_FPMODE + 0U, // G_RESET_FPMODE + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STACKSAVE + 0U, // G_STACKRESTORE + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_STRICT_FLDEXP + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_FMAXIMUM + 0U, // G_VECREDUCE_FMINIMUM + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ATOMIC_CMP_SWAP_16_P + 0U, // ATOMIC_CMP_SWAP_32_P + 0U, // ATOMIC_CMP_SWAP_8_P + 0U, // ATOMIC_LOAD_ADD_16_P + 0U, // ATOMIC_LOAD_ADD_32_P + 0U, // ATOMIC_LOAD_ADD_8_P + 0U, // ATOMIC_LOAD_AND_16_P + 0U, // ATOMIC_LOAD_AND_32_P + 0U, // ATOMIC_LOAD_AND_8_P + 0U, // ATOMIC_LOAD_MAX_16_P + 0U, // ATOMIC_LOAD_MAX_32_P + 0U, // ATOMIC_LOAD_MAX_8_P + 0U, // ATOMIC_LOAD_MIN_16_P + 0U, // ATOMIC_LOAD_MIN_32_P + 0U, // ATOMIC_LOAD_MIN_8_P + 0U, // ATOMIC_LOAD_NAND_16_P + 0U, // ATOMIC_LOAD_NAND_32_P + 0U, // ATOMIC_LOAD_NAND_8_P + 0U, // ATOMIC_LOAD_OR_16_P + 0U, // ATOMIC_LOAD_OR_32_P + 0U, // ATOMIC_LOAD_OR_8_P + 0U, // ATOMIC_LOAD_SUB_16_P + 0U, // ATOMIC_LOAD_SUB_32_P + 0U, // ATOMIC_LOAD_SUB_8_P + 0U, // ATOMIC_LOAD_UMAX_16_P + 0U, // ATOMIC_LOAD_UMAX_32_P + 0U, // ATOMIC_LOAD_UMAX_8_P + 0U, // ATOMIC_LOAD_UMIN_16_P + 0U, // ATOMIC_LOAD_UMIN_32_P + 0U, // ATOMIC_LOAD_UMIN_8_P + 0U, // ATOMIC_LOAD_XOR_16_P + 0U, // ATOMIC_LOAD_XOR_32_P + 0U, // ATOMIC_LOAD_XOR_8_P + 0U, // ATOMIC_SWAP_16_P + 0U, // ATOMIC_SWAP_32_P + 0U, // ATOMIC_SWAP_8_P + 0U, // BRCC_FP + 0U, // BR_JT + 0U, // CONSTPOOL_ENTRY + 0U, // EE_ANDQ_P + 0U, // EE_BITREV_P + 0U, // EE_CMUL_S16_LD_INCP_P + 0U, // EE_CMUL_S16_P + 0U, // EE_CMUL_S16_ST_INCP_P + 1U, // EE_FFT_AMS_S16_LD_INCP_P + 1U, // EE_FFT_AMS_S16_LD_INCP_UAUP_P + 1U, // EE_FFT_AMS_S16_LD_R32_DECP_P + 1U, // EE_FFT_AMS_S16_ST_INCP_P + 17U, // EE_FFT_CMUL_S16_LD_XP_P + 2U, // EE_FFT_CMUL_S16_ST_XP_P + 0U, // EE_FFT_R2BF_S16_P + 0U, // EE_FFT_R2BF_S16_ST_INCP_P + 0U, // EE_FFT_VST_R32_DECP_P + 3U, // EE_LDF_128_IP_P + 4U, // EE_LDF_128_XP_P + 0U, // EE_LDF_64_IP_P + 0U, // EE_LDF_64_XP_P + 0U, // EE_LDQA_S16_128_IP_P + 0U, // EE_LDQA_S16_128_XP_P + 0U, // EE_LDQA_S8_128_IP_P + 0U, // EE_LDQA_S8_128_XP_P + 0U, // EE_LDQA_U16_128_IP_P + 0U, // EE_LDQA_U16_128_XP_P + 0U, // EE_LDQA_U8_128_IP_P + 0U, // EE_LDQA_U8_128_XP_P + 0U, // EE_LDXQ_32_P + 0U, // EE_LD_128_USAR_IP_P + 0U, // EE_LD_128_USAR_XP_P + 0U, // EE_LD_ACCX_IP_P + 0U, // EE_LD_QACC_H_H_32_IP_P + 0U, // EE_LD_QACC_H_L_128_IP_P + 0U, // EE_LD_QACC_L_H_32_IP_P + 0U, // EE_LD_QACC_L_L_128_IP_P + 0U, // EE_LD_UA_STATE_IP_P + 0U, // EE_MOVI_32_A_P + 0U, // EE_MOVI_32_Q_P + 0U, // EE_MOV_S16_QACC_P + 0U, // EE_MOV_S8_QACC_P + 0U, // EE_MOV_U16_QACC_P + 0U, // EE_MOV_U8_QACC_P + 0U, // EE_NOTQ_P + 0U, // EE_ORQ_P + 0U, // EE_SLCI_2Q_P + 0U, // EE_SLCXXP_2Q_P + 0U, // EE_SRCI_2Q_P + 0U, // EE_SRCMB_S16_QACC_P + 0U, // EE_SRCMB_S8_QACC_P + 0U, // EE_SRCQ_128_ST_INCP_P + 0U, // EE_SRCXXP_2Q_P + 0U, // EE_SRC_Q_LD_IP_P + 0U, // EE_SRC_Q_LD_XP_P + 0U, // EE_SRC_Q_P + 0U, // EE_SRC_Q_QUP_P + 0U, // EE_SRS_ACCX_P + 3U, // EE_STF_128_IP_P + 4U, // EE_STF_128_XP_P + 0U, // EE_STF_64_IP_P + 0U, // EE_STF_64_XP_P + 0U, // EE_STXQ_32_P + 0U, // EE_ST_ACCX_IP_P + 0U, // EE_ST_QACC_H_H_32_IP_P + 0U, // EE_ST_QACC_H_L_128_IP_P + 0U, // EE_ST_QACC_L_H_32_IP_P + 0U, // EE_ST_QACC_L_L_128_IP_P + 0U, // EE_ST_UA_STATE_IP_P + 0U, // EE_VADDS_S16_LD_INCP_P + 0U, // EE_VADDS_S16_P + 0U, // EE_VADDS_S16_ST_INCP_P + 0U, // EE_VADDS_S32_LD_INCP_P + 0U, // EE_VADDS_S32_P + 0U, // EE_VADDS_S32_ST_INCP_P + 0U, // EE_VADDS_S8_LD_INCP_P + 0U, // EE_VADDS_S8_P + 0U, // EE_VADDS_S8_ST_INCP_P + 0U, // EE_VCMP_EQ_S16_P + 0U, // EE_VCMP_EQ_S32_P + 0U, // EE_VCMP_EQ_S8_P + 0U, // EE_VCMP_GT_S16_P + 0U, // EE_VCMP_GT_S32_P + 0U, // EE_VCMP_GT_S8_P + 0U, // EE_VCMP_LT_S16_P + 0U, // EE_VCMP_LT_S32_P + 0U, // EE_VCMP_LT_S8_P + 0U, // EE_VLDBC_16_IP_P + 0U, // EE_VLDBC_16_P + 0U, // EE_VLDBC_16_XP_P + 0U, // EE_VLDBC_32_IP_P + 0U, // EE_VLDBC_32_P + 0U, // EE_VLDBC_32_XP_P + 0U, // EE_VLDBC_8_IP_P + 0U, // EE_VLDBC_8_P + 0U, // EE_VLDBC_8_XP_P + 0U, // EE_VLDHBC_16_INCP_P + 0U, // EE_VLD_128_IP_P + 0U, // EE_VLD_128_XP_P + 0U, // EE_VLD_H_64_IP_P + 0U, // EE_VLD_H_64_XP_P + 0U, // EE_VLD_L_64_IP_P + 0U, // EE_VLD_L_64_XP_P + 0U, // EE_VMAX_S16_LD_INCP_P + 0U, // EE_VMAX_S16_P + 0U, // EE_VMAX_S16_ST_INCP_P + 0U, // EE_VMAX_S32_LD_INCP_P + 0U, // EE_VMAX_S32_P + 0U, // EE_VMAX_S32_ST_INCP_P + 0U, // EE_VMAX_S8_LD_INCP_P + 0U, // EE_VMAX_S8_P + 0U, // EE_VMAX_S8_ST_INCP_P + 0U, // EE_VMIN_S16_LD_INCP_P + 0U, // EE_VMIN_S16_P + 0U, // EE_VMIN_S16_ST_INCP_P + 0U, // EE_VMIN_S32_LD_INCP_P + 0U, // EE_VMIN_S32_P + 0U, // EE_VMIN_S32_ST_INCP_P + 0U, // EE_VMIN_S8_LD_INCP_P + 0U, // EE_VMIN_S8_P + 0U, // EE_VMIN_S8_ST_INCP_P + 0U, // EE_VMULAS_S16_ACCX_LD_IP_P + 0U, // EE_VMULAS_S16_ACCX_LD_IP_QUP_P + 0U, // EE_VMULAS_S16_ACCX_LD_XP_P + 65U, // EE_VMULAS_S16_ACCX_LD_XP_QUP_P + 0U, // EE_VMULAS_S16_ACCX_P + 0U, // EE_VMULAS_S16_QACC_LDBC_INCP_P + 9U, // EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P + 0U, // EE_VMULAS_S16_QACC_LD_IP_P + 0U, // EE_VMULAS_S16_QACC_LD_IP_QUP_P + 0U, // EE_VMULAS_S16_QACC_LD_XP_P + 65U, // EE_VMULAS_S16_QACC_LD_XP_QUP_P + 0U, // EE_VMULAS_S16_QACC_P + 0U, // EE_VMULAS_S8_ACCX_LD_IP_P + 0U, // EE_VMULAS_S8_ACCX_LD_IP_QUP_P + 0U, // EE_VMULAS_S8_ACCX_LD_XP_P + 65U, // EE_VMULAS_S8_ACCX_LD_XP_QUP_P + 0U, // EE_VMULAS_S8_ACCX_P + 0U, // EE_VMULAS_S8_QACC_LDBC_INCP_P + 9U, // EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P + 0U, // EE_VMULAS_S8_QACC_LD_IP_P + 0U, // EE_VMULAS_S8_QACC_LD_IP_QUP_P + 0U, // EE_VMULAS_S8_QACC_LD_XP_P + 65U, // EE_VMULAS_S8_QACC_LD_XP_QUP_P + 0U, // EE_VMULAS_S8_QACC_P + 0U, // EE_VMULAS_U16_ACCX_LD_IP_P + 0U, // EE_VMULAS_U16_ACCX_LD_IP_QUP_P + 0U, // EE_VMULAS_U16_ACCX_LD_XP_P + 65U, // EE_VMULAS_U16_ACCX_LD_XP_QUP_P + 0U, // EE_VMULAS_U16_ACCX_P + 0U, // EE_VMULAS_U16_QACC_LDBC_INCP_P + 9U, // EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P + 0U, // EE_VMULAS_U16_QACC_LD_IP_P + 0U, // EE_VMULAS_U16_QACC_LD_IP_QUP_P + 0U, // EE_VMULAS_U16_QACC_LD_XP_P + 65U, // EE_VMULAS_U16_QACC_LD_XP_QUP_P + 0U, // EE_VMULAS_U16_QACC_P + 0U, // EE_VMULAS_U8_ACCX_LD_IP_P + 0U, // EE_VMULAS_U8_ACCX_LD_IP_QUP_P + 0U, // EE_VMULAS_U8_ACCX_LD_XP_P + 65U, // EE_VMULAS_U8_ACCX_LD_XP_QUP_P + 0U, // EE_VMULAS_U8_ACCX_P + 0U, // EE_VMULAS_U8_QACC_LDBC_INCP_P + 9U, // EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P + 0U, // EE_VMULAS_U8_QACC_LD_IP_P + 0U, // EE_VMULAS_U8_QACC_LD_IP_QUP_P + 0U, // EE_VMULAS_U8_QACC_LD_XP_P + 65U, // EE_VMULAS_U8_QACC_LD_XP_QUP_P + 0U, // EE_VMULAS_U8_QACC_P + 0U, // EE_VMUL_S16_LD_INCP_P + 0U, // EE_VMUL_S16_P + 0U, // EE_VMUL_S16_ST_INCP_P + 0U, // EE_VMUL_S8_LD_INCP_P + 0U, // EE_VMUL_S8_P + 0U, // EE_VMUL_S8_ST_INCP_P + 0U, // EE_VMUL_U16_LD_INCP_P + 0U, // EE_VMUL_U16_P + 0U, // EE_VMUL_U16_ST_INCP_P + 0U, // EE_VMUL_U8_LD_INCP_P + 0U, // EE_VMUL_U8_P + 0U, // EE_VMUL_U8_ST_INCP_P + 0U, // EE_VPRELU_S16_P + 0U, // EE_VPRELU_S8_P + 0U, // EE_VRELU_S16_P + 0U, // EE_VRELU_S8_P + 0U, // EE_VSL_32_P + 0U, // EE_VSMULAS_S16_QACC_LD_INCP_P + 0U, // EE_VSMULAS_S16_QACC_P + 0U, // EE_VSMULAS_S8_QACC_LD_INCP_P + 0U, // EE_VSMULAS_S8_QACC_P + 0U, // EE_VSR_32_P + 0U, // EE_VST_128_IP_P + 0U, // EE_VST_128_XP_P + 0U, // EE_VST_H_64_IP_P + 0U, // EE_VST_H_64_XP_P + 0U, // EE_VST_L_64_IP_P + 0U, // EE_VST_L_64_XP_P + 0U, // EE_VSUBS_S16_LD_INCP_P + 0U, // EE_VSUBS_S16_P + 0U, // EE_VSUBS_S16_ST_INCP_P + 0U, // EE_VSUBS_S32_LD_INCP_P + 0U, // EE_VSUBS_S32_P + 0U, // EE_VSUBS_S32_ST_INCP_P + 0U, // EE_VSUBS_S8_LD_INCP_P + 0U, // EE_VSUBS_S8_P + 0U, // EE_VSUBS_S8_ST_INCP_P + 0U, // EE_VUNZIP_16_P + 0U, // EE_VUNZIP_32_P + 0U, // EE_VUNZIP_8_P + 0U, // EE_VZIP_16_P + 0U, // EE_VZIP_32_P + 0U, // EE_VZIP_8_P + 0U, // EE_XORQ_P + 0U, // EE_ZERO_ACCX_P + 0U, // EE_ZERO_QACC_P + 0U, // EE_ZERO_Q_P + 0U, // EXTUI_BR2_P + 0U, // EXTUI_BR4_P + 0U, // EXTUI_BR_P + 0U, // L8I_P + 0U, // LDDEC_P + 0U, // LDINC_P + 0U, // LOOPBR + 0U, // LOOPDEC + 0U, // LOOPEND + 0U, // LOOPINIT + 0U, // LOOPSTART + 0U, // MOVBA2_P + 0U, // MOVBA2_P2 + 0U, // MOVBA4_P + 0U, // MOVBA4_P2 + 0U, // MOVBA_P + 0U, // MOVBA_P2 + 0U, // MULA_DA_HH_LDDEC_P + 0U, // MULA_DA_HH_LDINC_P + 0U, // MULA_DA_HL_LDDEC_P + 0U, // MULA_DA_HL_LDINC_P + 0U, // MULA_DA_LH_LDDEC_P + 0U, // MULA_DA_LH_LDINC_P + 0U, // MULA_DA_LL_LDDEC_P + 0U, // MULA_DA_LL_LDINC_P + 0U, // MULA_DD_HH_LDDEC_P + 0U, // MULA_DD_HH_LDINC_P + 0U, // MULA_DD_HL_LDDEC_P + 0U, // MULA_DD_HL_LDINC_P + 0U, // MULA_DD_LH_LDDEC_P + 0U, // MULA_DD_LH_LDINC_P + 0U, // MULA_DD_LL_LDDEC_P + 0U, // MULA_DD_LL_LDINC_P + 0U, // RESTORE_BOOL + 4U, // SELECT + 4U, // SELECT_CC_FP_FP + 4U, // SELECT_CC_FP_INT + 4U, // SELECT_CC_INT_FP + 0U, // SLLI_BR_P + 0U, // SLL_P + 0U, // SPILL_BOOL + 0U, // SRA_P + 0U, // SRL_P + 0U, // WSR_ACCHI_P + 0U, // WSR_ACCLO_P + 0U, // WSR_M0_P + 0U, // WSR_M1_P + 0U, // WSR_M2_P + 0U, // WSR_M3_P + 0U, // XSR_ACCHI_P + 0U, // XSR_ACCLO_P + 0U, // XSR_M0_P + 0U, // XSR_M1_P + 0U, // XSR_M2_P + 0U, // XSR_M3_P + 0U, // mv_QR_P + 0U, // ABS + 0U, // ABS_S + 0U, // ADD + 0U, // ADDEXPM_S + 0U, // ADDEXP_S + 0U, // ADDI + 0U, // ADDI_N + 0U, // ADDMI + 0U, // ADDX2 + 0U, // ADDX4 + 0U, // ADDX8 + 0U, // ADD_N + 0U, // ADD_S + 0U, // AE_ABS16S + 0U, // AE_ABS24S + 0U, // AE_ABS32 + 0U, // AE_ABS32S + 0U, // AE_ABS64 + 0U, // AE_ABS64S + 0U, // AE_ADD16 + 0U, // AE_ADD16S + 0U, // AE_ADD24S + 0U, // AE_ADD32 + 0U, // AE_ADD32S + 0U, // AE_ADD32_HL_LH + 0U, // AE_ADD64 + 0U, // AE_ADD64S + 0U, // AE_ADDBRBA32 + 0U, // AE_ADDSUB32 + 0U, // AE_ADDSUB32S + 0U, // AE_AND + 0U, // AE_CVT32X2F16_10 + 0U, // AE_CVT32X2F16_32 + 0U, // AE_CVT48A32 + 0U, // AE_CVT64A32 + 0U, // AE_CVT64F32_H + 0U, // AE_CVTA32F24S_H + 0U, // AE_CVTA32F24S_L + 0U, // AE_CVTQ56A32S + 0U, // AE_CVTQ56P32S_H + 0U, // AE_CVTQ56P32S_L + 0U, // AE_DB + 0U, // AE_DBI + 0U, // AE_DBI_IC + 0U, // AE_DBI_IP + 0U, // AE_DB_IC + 0U, // AE_DB_IP + 0U, // AE_DIV64D32_H + 0U, // AE_DIV64D32_L + 0U, // AE_EQ16 + 0U, // AE_EQ32 + 0U, // AE_EQ64 + 0U, // AE_L16M_I + 0U, // AE_L16M_IU + 0U, // AE_L16M_X + 0U, // AE_L16M_XC + 0U, // AE_L16M_XU + 0U, // AE_L16X2M_I + 0U, // AE_L16X2M_IU + 0U, // AE_L16X2M_X + 0U, // AE_L16X2M_XC + 0U, // AE_L16X2M_XU + 0U, // AE_L16X4_I + 0U, // AE_L16X4_IP + 0U, // AE_L16X4_RIC + 0U, // AE_L16X4_RIP + 0U, // AE_L16X4_X + 0U, // AE_L16X4_XC + 0U, // AE_L16X4_XP + 0U, // AE_L16_I + 0U, // AE_L16_IP + 0U, // AE_L16_X + 0U, // AE_L16_XC + 0U, // AE_L16_XP + 0U, // AE_L32F24_I + 0U, // AE_L32F24_IP + 0U, // AE_L32F24_X + 0U, // AE_L32F24_XC + 0U, // AE_L32F24_XP + 0U, // AE_L32M_I + 0U, // AE_L32M_IU + 0U, // AE_L32M_X + 0U, // AE_L32M_XC + 0U, // AE_L32M_XU + 0U, // AE_L32X2F24_I + 0U, // AE_L32X2F24_IP + 0U, // AE_L32X2F24_RIC + 0U, // AE_L32X2F24_RIP + 0U, // AE_L32X2F24_X + 0U, // AE_L32X2F24_XC + 0U, // AE_L32X2F24_XP + 0U, // AE_L32X2_I + 0U, // AE_L32X2_IP + 0U, // AE_L32X2_RIC + 0U, // AE_L32X2_RIP + 0U, // AE_L32X2_X + 0U, // AE_L32X2_XC + 0U, // AE_L32X2_XP + 0U, // AE_L32_I + 0U, // AE_L32_IP + 0U, // AE_L32_X + 0U, // AE_L32_XC + 0U, // AE_L32_XP + 0U, // AE_L64_I + 0U, // AE_L64_IP + 0U, // AE_L64_X + 0U, // AE_L64_XC + 0U, // AE_L64_XP + 0U, // AE_LA16X4NEG_PC + 0U, // AE_LA16X4POS_PC + 0U, // AE_LA16X4_IC + 0U, // AE_LA16X4_IP + 0U, // AE_LA16X4_RIC + 0U, // AE_LA16X4_RIP + 0U, // AE_LA24NEG_PC + 0U, // AE_LA24POS_PC + 0U, // AE_LA24X2NEG_PC + 0U, // AE_LA24X2POS_PC + 0U, // AE_LA24X2_IC + 0U, // AE_LA24X2_IP + 0U, // AE_LA24X2_RIC + 0U, // AE_LA24X2_RIP + 0U, // AE_LA24_IC + 0U, // AE_LA24_IP + 0U, // AE_LA24_RIC + 0U, // AE_LA24_RIP + 0U, // AE_LA32X2F24_IC + 0U, // AE_LA32X2F24_IP + 0U, // AE_LA32X2F24_RIC + 0U, // AE_LA32X2F24_RIP + 0U, // AE_LA32X2NEG_PC + 0U, // AE_LA32X2POS_PC + 0U, // AE_LA32X2_IC + 0U, // AE_LA32X2_IP + 0U, // AE_LA32X2_RIC + 0U, // AE_LA32X2_RIP + 0U, // AE_LA64_PP + 0U, // AE_LALIGN64_I + 0U, // AE_LB + 0U, // AE_LBI + 0U, // AE_LBK + 0U, // AE_LBKI + 0U, // AE_LBS + 0U, // AE_LBSI + 0U, // AE_LE16 + 0U, // AE_LE32 + 0U, // AE_LE64 + 0U, // AE_LT16 + 0U, // AE_LT32 + 0U, // AE_LT64 + 0U, // AE_MAX32 + 0U, // AE_MAX64 + 0U, // AE_MAXABS32S + 0U, // AE_MAXABS64S + 0U, // AE_MIN32 + 0U, // AE_MIN64 + 0U, // AE_MINABS32S + 0U, // AE_MINABS64S + 0U, // AE_MOV + 0U, // AE_MOVAD16_0 + 0U, // AE_MOVAD16_1 + 0U, // AE_MOVAD16_2 + 0U, // AE_MOVAD16_3 + 0U, // AE_MOVAD32_H + 0U, // AE_MOVAD32_L + 0U, // AE_MOVALIGN + 0U, // AE_MOVDA16 + 0U, // AE_MOVDA16X2 + 0U, // AE_MOVDA32 + 0U, // AE_MOVDA32X2 + 0U, // AE_MOVF16X4 + 0U, // AE_MOVF32X2 + 0U, // AE_MOVF64 + 0U, // AE_MOVI + 0U, // AE_MOVT16X4 + 0U, // AE_MOVT32X2 + 0U, // AE_MOVT64 + 0U, // AE_MUL16X4 + 0U, // AE_MUL32U_LL + 0U, // AE_MUL32X16_H0 + 0U, // AE_MUL32X16_H0_S2 + 0U, // AE_MUL32X16_H1 + 0U, // AE_MUL32X16_H1_S2 + 0U, // AE_MUL32X16_H2 + 0U, // AE_MUL32X16_H2_S2 + 0U, // AE_MUL32X16_H3 + 0U, // AE_MUL32X16_H3_S2 + 0U, // AE_MUL32X16_L0 + 0U, // AE_MUL32X16_L0_S2 + 0U, // AE_MUL32X16_L1 + 0U, // AE_MUL32X16_L1_S2 + 0U, // AE_MUL32X16_L2 + 0U, // AE_MUL32X16_L2_S2 + 0U, // AE_MUL32X16_L3 + 0U, // AE_MUL32X16_L3_S2 + 0U, // AE_MUL32_HH + 0U, // AE_MUL32_LH + 0U, // AE_MUL32_LL + 0U, // AE_MUL32_LL_S2 + 0U, // AE_MULA16X4 + 0U, // AE_MULA32U_LL + 0U, // AE_MULA32X16_H0 + 0U, // AE_MULA32X16_H0_S2 + 0U, // AE_MULA32X16_H1 + 0U, // AE_MULA32X16_H1_S2 + 0U, // AE_MULA32X16_H2 + 0U, // AE_MULA32X16_H2_S2 + 0U, // AE_MULA32X16_H3 + 0U, // AE_MULA32X16_H3_S2 + 0U, // AE_MULA32X16_L0 + 0U, // AE_MULA32X16_L0_S2 + 0U, // AE_MULA32X16_L1 + 0U, // AE_MULA32X16_L1_S2 + 0U, // AE_MULA32X16_L2 + 0U, // AE_MULA32X16_L2_S2 + 0U, // AE_MULA32X16_L3 + 0U, // AE_MULA32X16_L3_S2 + 0U, // AE_MULA32_HH + 0U, // AE_MULA32_LH + 0U, // AE_MULA32_LL + 0U, // AE_MULA32_LL_S2 + 0U, // AE_MULAAD24_HH_LL + 0U, // AE_MULAAD24_HH_LL_S2 + 0U, // AE_MULAAD24_HL_LH + 0U, // AE_MULAAD24_HL_LH_S2 + 0U, // AE_MULAAD32X16_H0_L1 + 0U, // AE_MULAAD32X16_H0_L1_S2 + 0U, // AE_MULAAD32X16_H1_L0 + 0U, // AE_MULAAD32X16_H1_L0_S2 + 0U, // AE_MULAAD32X16_H2_L3 + 0U, // AE_MULAAD32X16_H2_L3_S2 + 0U, // AE_MULAAD32X16_H3_L2 + 0U, // AE_MULAAD32X16_H3_L2_S2 + 0U, // AE_MULAAFD16SS_11_00 + 0U, // AE_MULAAFD16SS_11_00_S2 + 0U, // AE_MULAAFD16SS_13_02 + 0U, // AE_MULAAFD16SS_13_02_S2 + 0U, // AE_MULAAFD16SS_33_22 + 0U, // AE_MULAAFD16SS_33_22_S2 + 0U, // AE_MULAAFD24_HH_LL + 0U, // AE_MULAAFD24_HH_LL_S2 + 0U, // AE_MULAAFD24_HL_LH + 0U, // AE_MULAAFD24_HL_LH_S2 + 0U, // AE_MULAAFD32X16_H0_L1 + 0U, // AE_MULAAFD32X16_H0_L1_S2 + 0U, // AE_MULAAFD32X16_H1_L0 + 0U, // AE_MULAAFD32X16_H1_L0_S2 + 0U, // AE_MULAAFD32X16_H2_L3 + 0U, // AE_MULAAFD32X16_H2_L3_S2 + 0U, // AE_MULAAFD32X16_H3_L2 + 0U, // AE_MULAAFD32X16_H3_L2_S2 + 0U, // AE_MULAC24 + 0U, // AE_MULAC32X16_H + 0U, // AE_MULAC32X16_L + 0U, // AE_MULAF16SS_00 + 0U, // AE_MULAF16SS_00_S2 + 0U, // AE_MULAF16SS_10 + 0U, // AE_MULAF16SS_11 + 0U, // AE_MULAF16SS_20 + 0U, // AE_MULAF16SS_21 + 0U, // AE_MULAF16SS_22 + 0U, // AE_MULAF16SS_30 + 0U, // AE_MULAF16SS_31 + 0U, // AE_MULAF16SS_32 + 0U, // AE_MULAF16SS_33 + 0U, // AE_MULAF16X4SS + 0U, // AE_MULAF32R_HH + 0U, // AE_MULAF32R_LH + 0U, // AE_MULAF32R_LL + 0U, // AE_MULAF32R_LL_S2 + 0U, // AE_MULAF32S_HH + 0U, // AE_MULAF32S_LH + 0U, // AE_MULAF32S_LL + 0U, // AE_MULAF32S_LL_S2 + 0U, // AE_MULAF32X16_H0 + 0U, // AE_MULAF32X16_H0_S2 + 0U, // AE_MULAF32X16_H1 + 0U, // AE_MULAF32X16_H1_S2 + 0U, // AE_MULAF32X16_H2 + 0U, // AE_MULAF32X16_H2_S2 + 0U, // AE_MULAF32X16_H3 + 0U, // AE_MULAF32X16_H3_S2 + 0U, // AE_MULAF32X16_L0 + 0U, // AE_MULAF32X16_L0_S2 + 0U, // AE_MULAF32X16_L1 + 0U, // AE_MULAF32X16_L1_S2 + 0U, // AE_MULAF32X16_L2 + 0U, // AE_MULAF32X16_L2_S2 + 0U, // AE_MULAF32X16_L3 + 0U, // AE_MULAF32X16_L3_S2 + 0U, // AE_MULAF48Q32SP16S_L + 0U, // AE_MULAF48Q32SP16S_L_S2 + 0U, // AE_MULAF48Q32SP16U_L + 0U, // AE_MULAF48Q32SP16U_L_S2 + 0U, // AE_MULAFC24RA + 0U, // AE_MULAFC32X16RAS_H + 0U, // AE_MULAFC32X16RAS_L + 0U, // AE_MULAFD24X2_FIR_H + 0U, // AE_MULAFD24X2_FIR_L + 0U, // AE_MULAFD32X16X2_FIR_HH + 0U, // AE_MULAFD32X16X2_FIR_HL + 0U, // AE_MULAFD32X16X2_FIR_LH + 0U, // AE_MULAFD32X16X2_FIR_LL + 0U, // AE_MULAFP24X2R + 0U, // AE_MULAFP24X2RA + 0U, // AE_MULAFP24X2RA_S2 + 0U, // AE_MULAFP24X2R_S2 + 0U, // AE_MULAFP32X16X2RAS_H + 0U, // AE_MULAFP32X16X2RAS_H_S2 + 0U, // AE_MULAFP32X16X2RAS_L + 0U, // AE_MULAFP32X16X2RAS_L_S2 + 0U, // AE_MULAFP32X16X2RS_H + 0U, // AE_MULAFP32X16X2RS_H_S2 + 0U, // AE_MULAFP32X16X2RS_L + 0U, // AE_MULAFP32X16X2RS_L_S2 + 0U, // AE_MULAFP32X2RAS + 0U, // AE_MULAFP32X2RS + 0U, // AE_MULAFQ32SP24S_H_S2 + 0U, // AE_MULAFQ32SP24S_L_S2 + 0U, // AE_MULAP24X2 + 0U, // AE_MULAP24X2_S2 + 0U, // AE_MULAP32X16X2_H + 0U, // AE_MULAP32X16X2_L + 0U, // AE_MULAP32X2 + 0U, // AE_MULAQ32SP16S_L_S2 + 0U, // AE_MULAQ32SP16U_L_S2 + 0U, // AE_MULARFQ32SP24S_H_S2 + 0U, // AE_MULARFQ32SP24S_L_S2 + 0U, // AE_MULAS32F48P16S_HH + 0U, // AE_MULAS32F48P16S_HH_S2 + 0U, // AE_MULAS32F48P16S_LH + 0U, // AE_MULAS32F48P16S_LH_S2 + 0U, // AE_MULAS32F48P16S_LL + 0U, // AE_MULAS32F48P16S_LL_S2 + 0U, // AE_MULASD24_HH_LL + 0U, // AE_MULASD24_HH_LL_S2 + 0U, // AE_MULASD24_HL_LH + 0U, // AE_MULASD24_HL_LH_S2 + 0U, // AE_MULASD32X16_H1_L0 + 0U, // AE_MULASD32X16_H1_L0_S2 + 0U, // AE_MULASD32X16_H3_L2 + 0U, // AE_MULASD32X16_H3_L2_S2 + 0U, // AE_MULASFD24_HH_LL + 0U, // AE_MULASFD24_HH_LL_S2 + 0U, // AE_MULASFD24_HL_LH + 0U, // AE_MULASFD24_HL_LH_S2 + 0U, // AE_MULASFD32X16_H1_L0 + 0U, // AE_MULASFD32X16_H1_L0_S2 + 0U, // AE_MULASFD32X16_H3_L2 + 0U, // AE_MULASFD32X16_H3_L2_S2 + 0U, // AE_MULC24 + 0U, // AE_MULC32X16_H + 0U, // AE_MULC32X16_L + 0U, // AE_MULF16SS_00 + 0U, // AE_MULF16SS_00_S2 + 0U, // AE_MULF16SS_10 + 0U, // AE_MULF16SS_11 + 0U, // AE_MULF16SS_20 + 0U, // AE_MULF16SS_21 + 0U, // AE_MULF16SS_22 + 0U, // AE_MULF16SS_30 + 0U, // AE_MULF16SS_31 + 0U, // AE_MULF16SS_32 + 0U, // AE_MULF16SS_33 + 0U, // AE_MULF16X4SS + 0U, // AE_MULF32R_HH + 0U, // AE_MULF32R_LH + 0U, // AE_MULF32R_LL + 0U, // AE_MULF32R_LL_S2 + 0U, // AE_MULF32S_HH + 0U, // AE_MULF32S_LH + 0U, // AE_MULF32S_LL + 0U, // AE_MULF32S_LL_S2 + 0U, // AE_MULF32X16_H0 + 0U, // AE_MULF32X16_H0_S2 + 0U, // AE_MULF32X16_H1 + 0U, // AE_MULF32X16_H1_S2 + 0U, // AE_MULF32X16_H2 + 0U, // AE_MULF32X16_H2_S2 + 0U, // AE_MULF32X16_H3 + 0U, // AE_MULF32X16_H3_S2 + 0U, // AE_MULF32X16_L0 + 0U, // AE_MULF32X16_L0_S2 + 0U, // AE_MULF32X16_L1 + 0U, // AE_MULF32X16_L1_S2 + 0U, // AE_MULF32X16_L2 + 0U, // AE_MULF32X16_L2_S2 + 0U, // AE_MULF32X16_L3 + 0U, // AE_MULF32X16_L3_S2 + 0U, // AE_MULF48Q32SP16S_L + 0U, // AE_MULF48Q32SP16S_L_S2 + 0U, // AE_MULF48Q32SP16U_L + 0U, // AE_MULF48Q32SP16U_L_S2 + 0U, // AE_MULFC24RA + 0U, // AE_MULFC32X16RAS_H + 0U, // AE_MULFC32X16RAS_L + 0U, // AE_MULFD24X2_FIR_H + 0U, // AE_MULFD24X2_FIR_L + 0U, // AE_MULFD32X16X2_FIR_HH + 0U, // AE_MULFD32X16X2_FIR_HL + 0U, // AE_MULFD32X16X2_FIR_LH + 0U, // AE_MULFD32X16X2_FIR_LL + 0U, // AE_MULFP16X4RAS + 0U, // AE_MULFP16X4S + 0U, // AE_MULFP24X2R + 0U, // AE_MULFP24X2RA + 0U, // AE_MULFP24X2RA_S2 + 0U, // AE_MULFP24X2R_S2 + 0U, // AE_MULFP32X16X2RAS_H + 0U, // AE_MULFP32X16X2RAS_H_S2 + 0U, // AE_MULFP32X16X2RAS_L + 0U, // AE_MULFP32X16X2RAS_L_S2 + 0U, // AE_MULFP32X16X2RS_H + 0U, // AE_MULFP32X16X2RS_H_S2 + 0U, // AE_MULFP32X16X2RS_L + 0U, // AE_MULFP32X16X2RS_L_S2 + 0U, // AE_MULFP32X2RAS + 0U, // AE_MULFP32X2RS + 0U, // AE_MULFQ32SP24S_H_S2 + 0U, // AE_MULFQ32SP24S_L_S2 + 0U, // AE_MULP24X2 + 0U, // AE_MULP24X2_S2 + 0U, // AE_MULP32X16X2_H + 0U, // AE_MULP32X16X2_L + 0U, // AE_MULP32X2 + 0U, // AE_MULQ32SP16S_L_S2 + 0U, // AE_MULQ32SP16U_L_S2 + 0U, // AE_MULRFQ32SP24S_H_S2 + 0U, // AE_MULRFQ32SP24S_L_S2 + 0U, // AE_MULS16X4 + 0U, // AE_MULS32F48P16S_HH + 0U, // AE_MULS32F48P16S_HH_S2 + 0U, // AE_MULS32F48P16S_LH + 0U, // AE_MULS32F48P16S_LH_S2 + 0U, // AE_MULS32F48P16S_LL + 0U, // AE_MULS32F48P16S_LL_S2 + 0U, // AE_MULS32U_LL + 0U, // AE_MULS32X16_H0 + 0U, // AE_MULS32X16_H0_S2 + 0U, // AE_MULS32X16_H1 + 0U, // AE_MULS32X16_H1_S2 + 0U, // AE_MULS32X16_H2 + 0U, // AE_MULS32X16_H2_S2 + 0U, // AE_MULS32X16_H3 + 0U, // AE_MULS32X16_H3_S2 + 0U, // AE_MULS32X16_L0 + 0U, // AE_MULS32X16_L0_S2 + 0U, // AE_MULS32X16_L1 + 0U, // AE_MULS32X16_L1_S2 + 0U, // AE_MULS32X16_L2 + 0U, // AE_MULS32X16_L2_S2 + 0U, // AE_MULS32X16_L3 + 0U, // AE_MULS32X16_L3_S2 + 0U, // AE_MULS32_HH + 0U, // AE_MULS32_LH + 0U, // AE_MULS32_LL + 0U, // AE_MULSAD24_HH_LL + 0U, // AE_MULSAD24_HH_LL_S2 + 0U, // AE_MULSAD32X16_H1_L0 + 0U, // AE_MULSAD32X16_H1_L0_S2 + 0U, // AE_MULSAD32X16_H3_L2 + 0U, // AE_MULSAD32X16_H3_L2_S2 + 0U, // AE_MULSAFD24_HH_LL + 0U, // AE_MULSAFD24_HH_LL_S2 + 0U, // AE_MULSAFD32X16_H1_L0 + 0U, // AE_MULSAFD32X16_H1_L0_S2 + 0U, // AE_MULSAFD32X16_H3_L2 + 0U, // AE_MULSAFD32X16_H3_L2_S2 + 0U, // AE_MULSF16SS_00 + 0U, // AE_MULSF16SS_00_S2 + 0U, // AE_MULSF16SS_10 + 0U, // AE_MULSF16SS_11 + 0U, // AE_MULSF16SS_20 + 0U, // AE_MULSF16SS_21 + 0U, // AE_MULSF16SS_22 + 0U, // AE_MULSF16SS_30 + 0U, // AE_MULSF16SS_31 + 0U, // AE_MULSF16SS_32 + 0U, // AE_MULSF16SS_33 + 0U, // AE_MULSF16X4SS + 0U, // AE_MULSF32R_HH + 0U, // AE_MULSF32R_LH + 0U, // AE_MULSF32R_LL + 0U, // AE_MULSF32R_LL_S2 + 0U, // AE_MULSF32S_HH + 0U, // AE_MULSF32S_LH + 0U, // AE_MULSF32S_LL + 0U, // AE_MULSF32X16_H0 + 0U, // AE_MULSF32X16_H0_S2 + 0U, // AE_MULSF32X16_H1 + 0U, // AE_MULSF32X16_H1_S2 + 0U, // AE_MULSF32X16_H2 + 0U, // AE_MULSF32X16_H2_S2 + 0U, // AE_MULSF32X16_H3 + 0U, // AE_MULSF32X16_H3_S2 + 0U, // AE_MULSF32X16_L0 + 0U, // AE_MULSF32X16_L0_S2 + 0U, // AE_MULSF32X16_L1 + 0U, // AE_MULSF32X16_L1_S2 + 0U, // AE_MULSF32X16_L2 + 0U, // AE_MULSF32X16_L2_S2 + 0U, // AE_MULSF32X16_L3 + 0U, // AE_MULSF32X16_L3_S2 + 0U, // AE_MULSF48Q32SP16S_L + 0U, // AE_MULSF48Q32SP16S_L_S2 + 0U, // AE_MULSF48Q32SP16U_L + 0U, // AE_MULSF48Q32SP16U_L_S2 + 0U, // AE_MULSFP24X2R + 0U, // AE_MULSFP24X2RA + 0U, // AE_MULSFP24X2RA_S2 + 0U, // AE_MULSFP24X2R_S2 + 0U, // AE_MULSFP32X16X2RAS_H + 0U, // AE_MULSFP32X16X2RAS_H_S2 + 0U, // AE_MULSFP32X16X2RAS_L + 0U, // AE_MULSFP32X16X2RAS_L_S2 + 0U, // AE_MULSFP32X16X2RS_H + 0U, // AE_MULSFP32X16X2RS_H_S2 + 0U, // AE_MULSFP32X16X2RS_L + 0U, // AE_MULSFP32X16X2RS_L_S2 + 0U, // AE_MULSFP32X2RAS + 0U, // AE_MULSFP32X2RS + 0U, // AE_MULSFQ32SP24S_H_S2 + 0U, // AE_MULSFQ32SP24S_L_S2 + 0U, // AE_MULSP24X2 + 0U, // AE_MULSP24X2_S2 + 0U, // AE_MULSP32X16X2_H + 0U, // AE_MULSP32X16X2_L + 0U, // AE_MULSP32X2 + 0U, // AE_MULSQ32SP16S_L_S2 + 0U, // AE_MULSQ32SP16U_L_S2 + 0U, // AE_MULSRFQ32SP24S_H_S2 + 0U, // AE_MULSRFQ32SP24S_L_S2 + 0U, // AE_MULSS32F48P16S_HH + 0U, // AE_MULSS32F48P16S_HH_S2 + 0U, // AE_MULSS32F48P16S_LH + 0U, // AE_MULSS32F48P16S_LH_S2 + 0U, // AE_MULSS32F48P16S_LL + 0U, // AE_MULSS32F48P16S_LL_S2 + 0U, // AE_MULSSD24_HH_LL + 0U, // AE_MULSSD24_HH_LL_S2 + 0U, // AE_MULSSD24_HL_LH + 0U, // AE_MULSSD24_HL_LH_S2 + 0U, // AE_MULSSD32X16_H1_L0 + 0U, // AE_MULSSD32X16_H1_L0_S2 + 0U, // AE_MULSSD32X16_H3_L2 + 0U, // AE_MULSSD32X16_H3_L2_S2 + 0U, // AE_MULSSFD16SS_11_00 + 0U, // AE_MULSSFD16SS_11_00_S2 + 0U, // AE_MULSSFD16SS_13_02 + 0U, // AE_MULSSFD16SS_13_02_S2 + 0U, // AE_MULSSFD16SS_33_22 + 0U, // AE_MULSSFD16SS_33_22_S2 + 0U, // AE_MULSSFD24_HH_LL + 0U, // AE_MULSSFD24_HH_LL_S2 + 0U, // AE_MULSSFD24_HL_LH + 0U, // AE_MULSSFD24_HL_LH_S2 + 0U, // AE_MULSSFD32X16_H1_L0 + 0U, // AE_MULSSFD32X16_H1_L0_S2 + 0U, // AE_MULSSFD32X16_H3_L2 + 0U, // AE_MULSSFD32X16_H3_L2_S2 + 0U, // AE_MULZAAD24_HH_LL + 0U, // AE_MULZAAD24_HH_LL_S2 + 0U, // AE_MULZAAD24_HL_LH + 0U, // AE_MULZAAD24_HL_LH_S2 + 0U, // AE_MULZAAD32X16_H0_L1 + 0U, // AE_MULZAAD32X16_H0_L1_S2 + 0U, // AE_MULZAAD32X16_H1_L0 + 0U, // AE_MULZAAD32X16_H1_L0_S2 + 0U, // AE_MULZAAD32X16_H2_L3 + 0U, // AE_MULZAAD32X16_H2_L3_S2 + 0U, // AE_MULZAAD32X16_H3_L2 + 0U, // AE_MULZAAD32X16_H3_L2_S2 + 0U, // AE_MULZAAFD16SS_11_00 + 0U, // AE_MULZAAFD16SS_11_00_S2 + 0U, // AE_MULZAAFD16SS_13_02 + 0U, // AE_MULZAAFD16SS_13_02_S2 + 0U, // AE_MULZAAFD16SS_33_22 + 0U, // AE_MULZAAFD16SS_33_22_S2 + 0U, // AE_MULZAAFD24_HH_LL + 0U, // AE_MULZAAFD24_HH_LL_S2 + 0U, // AE_MULZAAFD24_HL_LH + 0U, // AE_MULZAAFD24_HL_LH_S2 + 0U, // AE_MULZAAFD32X16_H0_L1 + 0U, // AE_MULZAAFD32X16_H0_L1_S2 + 0U, // AE_MULZAAFD32X16_H1_L0 + 0U, // AE_MULZAAFD32X16_H1_L0_S2 + 0U, // AE_MULZAAFD32X16_H2_L3 + 0U, // AE_MULZAAFD32X16_H2_L3_S2 + 0U, // AE_MULZAAFD32X16_H3_L2 + 0U, // AE_MULZAAFD32X16_H3_L2_S2 + 0U, // AE_MULZASD24_HH_LL + 0U, // AE_MULZASD24_HH_LL_S2 + 0U, // AE_MULZASD24_HL_LH + 0U, // AE_MULZASD24_HL_LH_S2 + 0U, // AE_MULZASD32X16_H1_L0 + 0U, // AE_MULZASD32X16_H1_L0_S2 + 0U, // AE_MULZASD32X16_H3_L2 + 0U, // AE_MULZASD32X16_H3_L2_S2 + 0U, // AE_MULZASFD24_HH_LL + 0U, // AE_MULZASFD24_HH_LL_S2 + 0U, // AE_MULZASFD24_HL_LH + 0U, // AE_MULZASFD24_HL_LH_S2 + 0U, // AE_MULZASFD32X16_H1_L0 + 0U, // AE_MULZASFD32X16_H1_L0_S2 + 0U, // AE_MULZASFD32X16_H3_L2 + 0U, // AE_MULZASFD32X16_H3_L2_S2 + 0U, // AE_MULZSAD24_HH_LL + 0U, // AE_MULZSAD24_HH_LL_S2 + 0U, // AE_MULZSAD32X16_H1_L0 + 0U, // AE_MULZSAD32X16_H1_L0_S2 + 0U, // AE_MULZSAD32X16_H3_L2 + 0U, // AE_MULZSAD32X16_H3_L2_S2 + 0U, // AE_MULZSAFD24_HH_LL + 0U, // AE_MULZSAFD24_HH_LL_S2 + 0U, // AE_MULZSAFD32X16_H1_L0 + 0U, // AE_MULZSAFD32X16_H1_L0_S2 + 0U, // AE_MULZSAFD32X16_H3_L2 + 0U, // AE_MULZSAFD32X16_H3_L2_S2 + 0U, // AE_MULZSSD24_HH_LL + 0U, // AE_MULZSSD24_HH_LL_S2 + 0U, // AE_MULZSSD24_HL_LH + 0U, // AE_MULZSSD24_HL_LH_S2 + 0U, // AE_MULZSSD32X16_H1_L0 + 0U, // AE_MULZSSD32X16_H1_L0_S2 + 0U, // AE_MULZSSD32X16_H3_L2 + 0U, // AE_MULZSSD32X16_H3_L2_S2 + 0U, // AE_MULZSSFD16SS_11_00 + 0U, // AE_MULZSSFD16SS_11_00_S2 + 0U, // AE_MULZSSFD16SS_13_02 + 0U, // AE_MULZSSFD16SS_13_02_S2 + 0U, // AE_MULZSSFD16SS_33_22 + 0U, // AE_MULZSSFD16SS_33_22_S2 + 0U, // AE_MULZSSFD24_HH_LL + 0U, // AE_MULZSSFD24_HH_LL_S2 + 0U, // AE_MULZSSFD24_HL_LH + 0U, // AE_MULZSSFD24_HL_LH_S2 + 0U, // AE_MULZSSFD32X16_H1_L0 + 0U, // AE_MULZSSFD32X16_H1_L0_S2 + 0U, // AE_MULZSSFD32X16_H3_L2 + 0U, // AE_MULZSSFD32X16_H3_L2_S2 + 0U, // AE_NAND + 0U, // AE_NEG16S + 0U, // AE_NEG24S + 0U, // AE_NEG32 + 0U, // AE_NEG32S + 0U, // AE_NEG64 + 0U, // AE_NEG64S + 0U, // AE_NSA64 + 0U, // AE_NSAZ16_0 + 0U, // AE_NSAZ32_L + 0U, // AE_OR + 0U, // AE_PKSR24 + 0U, // AE_PKSR32 + 0U, // AE_ROUND16X4F32SASYM + 0U, // AE_ROUND16X4F32SSYM + 0U, // AE_ROUND24X2F48SASYM + 0U, // AE_ROUND24X2F48SSYM + 0U, // AE_ROUND32X2F48SASYM + 0U, // AE_ROUND32X2F48SSYM + 0U, // AE_ROUND32X2F64SASYM + 0U, // AE_ROUND32X2F64SSYM + 0U, // AE_ROUNDSP16F24ASYM + 0U, // AE_ROUNDSP16F24SYM + 0U, // AE_ROUNDSP16Q48X2ASYM + 0U, // AE_ROUNDSP16Q48X2SYM + 0U, // AE_ROUNDSQ32F48ASYM + 0U, // AE_ROUNDSQ32F48SYM + 0U, // AE_S16M_L_I + 0U, // AE_S16M_L_IU + 0U, // AE_S16M_L_X + 0U, // AE_S16M_L_XC + 0U, // AE_S16M_L_XU + 0U, // AE_S16X2M_I + 0U, // AE_S16X2M_IU + 0U, // AE_S16X2M_X + 0U, // AE_S16X2M_XC + 0U, // AE_S16X2M_XU + 0U, // AE_S16X4_I + 0U, // AE_S16X4_IP + 0U, // AE_S16X4_RIC + 0U, // AE_S16X4_RIP + 0U, // AE_S16X4_X + 0U, // AE_S16X4_XC + 0U, // AE_S16X4_XP + 0U, // AE_S16_0_I + 0U, // AE_S16_0_IP + 0U, // AE_S16_0_X + 0U, // AE_S16_0_XC + 0U, // AE_S16_0_XP + 0U, // AE_S24RA64S_I + 0U, // AE_S24RA64S_IP + 0U, // AE_S24RA64S_X + 0U, // AE_S24RA64S_XC + 0U, // AE_S24RA64S_XP + 0U, // AE_S24X2RA64S_IP + 0U, // AE_S32F24_L_I + 0U, // AE_S32F24_L_IP + 0U, // AE_S32F24_L_X + 0U, // AE_S32F24_L_XC + 0U, // AE_S32F24_L_XP + 0U, // AE_S32M_I + 0U, // AE_S32M_IU + 0U, // AE_S32M_X + 0U, // AE_S32M_XC + 0U, // AE_S32M_XU + 0U, // AE_S32RA64S_I + 0U, // AE_S32RA64S_IP + 0U, // AE_S32RA64S_X + 0U, // AE_S32RA64S_XC + 0U, // AE_S32RA64S_XP + 0U, // AE_S32X2F24_I + 0U, // AE_S32X2F24_IP + 0U, // AE_S32X2F24_RIC + 0U, // AE_S32X2F24_RIP + 0U, // AE_S32X2F24_X + 0U, // AE_S32X2F24_XC + 0U, // AE_S32X2F24_XP + 0U, // AE_S32X2RA64S_IP + 0U, // AE_S32X2_I + 0U, // AE_S32X2_IP + 0U, // AE_S32X2_RIC + 0U, // AE_S32X2_RIP + 0U, // AE_S32X2_X + 0U, // AE_S32X2_XC + 0U, // AE_S32X2_XP + 0U, // AE_S32_L_I + 0U, // AE_S32_L_IP + 0U, // AE_S32_L_X + 0U, // AE_S32_L_XC + 0U, // AE_S32_L_XP + 0U, // AE_S64_I + 0U, // AE_S64_IP + 0U, // AE_S64_X + 0U, // AE_S64_XC + 0U, // AE_S64_XP + 0U, // AE_SA16X4_IC + 0U, // AE_SA16X4_IP + 0U, // AE_SA16X4_RIC + 0U, // AE_SA16X4_RIP + 0U, // AE_SA24X2_IC + 0U, // AE_SA24X2_IP + 0U, // AE_SA24X2_RIC + 0U, // AE_SA24X2_RIP + 0U, // AE_SA24_L_IC + 0U, // AE_SA24_L_IP + 0U, // AE_SA24_L_RIC + 0U, // AE_SA24_L_RIP + 0U, // AE_SA32X2F24_IC + 0U, // AE_SA32X2F24_IP + 0U, // AE_SA32X2F24_RIC + 0U, // AE_SA32X2F24_RIP + 0U, // AE_SA32X2_IC + 0U, // AE_SA32X2_IP + 0U, // AE_SA32X2_RIC + 0U, // AE_SA32X2_RIP + 0U, // AE_SA64NEG_FP + 0U, // AE_SA64POS_FP + 0U, // AE_SALIGN64_I + 0U, // AE_SAT16X4 + 0U, // AE_SAT24S + 0U, // AE_SAT48S + 0U, // AE_SATQ56S + 0U, // AE_SB + 0U, // AE_SBF + 0U, // AE_SBF_IC + 0U, // AE_SBF_IP + 0U, // AE_SBI + 0U, // AE_SBI_IC + 0U, // AE_SBI_IP + 0U, // AE_SB_IC + 0U, // AE_SB_IP + 0U, // AE_SEL16I + 0U, // AE_SEL16I_N + 0U, // AE_SEXT32 + 0U, // AE_SEXT32X2D16_10 + 0U, // AE_SEXT32X2D16_32 + 0U, // AE_SHA32 + 0U, // AE_SHORTSWAP + 0U, // AE_SLAA16S + 0U, // AE_SLAA32 + 0U, // AE_SLAA32S + 0U, // AE_SLAA64 + 0U, // AE_SLAA64S + 0U, // AE_SLAAQ56 + 0U, // AE_SLAI16S + 0U, // AE_SLAI24 + 0U, // AE_SLAI24S + 0U, // AE_SLAI32 + 0U, // AE_SLAI32S + 0U, // AE_SLAI64 + 0U, // AE_SLAI64S + 0U, // AE_SLAISQ56S + 0U, // AE_SLAS24 + 0U, // AE_SLAS24S + 0U, // AE_SLAS32 + 0U, // AE_SLAS32S + 0U, // AE_SLAS64 + 0U, // AE_SLAS64S + 0U, // AE_SLASQ56 + 0U, // AE_SLASSQ56S + 0U, // AE_SRA64_32 + 0U, // AE_SRAA16RS + 0U, // AE_SRAA16S + 0U, // AE_SRAA32 + 0U, // AE_SRAA32RS + 0U, // AE_SRAA32S + 0U, // AE_SRAA64 + 0U, // AE_SRAI16 + 0U, // AE_SRAI16R + 0U, // AE_SRAI24 + 0U, // AE_SRAI32 + 0U, // AE_SRAI32R + 0U, // AE_SRAI64 + 0U, // AE_SRAS24 + 0U, // AE_SRAS32 + 0U, // AE_SRAS64 + 0U, // AE_SRLA32 + 0U, // AE_SRLA64 + 0U, // AE_SRLI24 + 0U, // AE_SRLI32 + 0U, // AE_SRLI64 + 0U, // AE_SRLS24 + 0U, // AE_SRLS32 + 0U, // AE_SRLS64 + 0U, // AE_SUB16 + 0U, // AE_SUB16S + 0U, // AE_SUB24S + 0U, // AE_SUB32 + 0U, // AE_SUB32S + 0U, // AE_SUB64 + 0U, // AE_SUB64S + 0U, // AE_SUBADD32 + 0U, // AE_SUBADD32S + 0U, // AE_TRUNCA32F64S_L + 0U, // AE_TRUNCA32X2F64S + 0U, // AE_TRUNCI32F64S_L + 0U, // AE_TRUNCI32X2F64S + 0U, // AE_VLDL16C + 0U, // AE_VLDL16C_IC + 0U, // AE_VLDL16C_IP + 0U, // AE_VLDL16T + 0U, // AE_VLDL32T + 0U, // AE_VLDSHT + 0U, // AE_VLEL16T + 0U, // AE_VLEL32T + 0U, // AE_VLES16C + 0U, // AE_VLES16C_IC + 0U, // AE_VLES16C_IP + 0U, // AE_XOR + 0U, // AE_ZALIGN64 + 0U, // ALL4 + 0U, // ALL8 + 0U, // AND + 0U, // ANDB + 0U, // ANDBC + 0U, // ANY4 + 0U, // ANY8 + 0U, // BALL + 0U, // BANY + 0U, // BBC + 0U, // BBCI + 0U, // BBS + 0U, // BBSI + 0U, // BEQ + 0U, // BEQI + 0U, // BEQZ + 0U, // BF + 0U, // BGE + 0U, // BGEI + 0U, // BGEU + 0U, // BGEUI + 0U, // BGEZ + 0U, // BLT + 0U, // BLTI + 0U, // BLTU + 0U, // BLTUI + 0U, // BLTZ + 0U, // BNALL + 0U, // BNE + 0U, // BNEI + 0U, // BNEZ + 0U, // BNONE + 0U, // BREAK + 0U, // BREAK_N + 0U, // BT + 0U, // CALL0 + 0U, // CALL12 + 0U, // CALL4 + 0U, // CALL8 + 0U, // CALLX0 + 0U, // CALLX12 + 0U, // CALLX4 + 0U, // CALLX8 + 0U, // CEIL_S + 0U, // CLAMPS + 0U, // CLR_BIT_GPIO_OUT + 0U, // CONST_S + 0U, // DIV0_S + 0U, // DIVN_S + 0U, // DSYNC + 0U, // EE_ANDQ + 0U, // EE_BITREV + 0U, // EE_CLR_BIT_GPIO_OUT + 0U, // EE_CMUL_S16 + 0U, // EE_CMUL_S16_LD_INCP + 0U, // EE_CMUL_S16_ST_INCP + 37U, // EE_FFT_AMS_S16_LD_INCP + 37U, // EE_FFT_AMS_S16_LD_INCP_UAUP + 37U, // EE_FFT_AMS_S16_LD_R32_DECP + 0U, // EE_FFT_AMS_S16_ST_INCP + 0U, // EE_FFT_CMUL_S16_LD_XP + 6U, // EE_FFT_CMUL_S16_ST_XP + 0U, // EE_FFT_R2BF_S16 + 0U, // EE_FFT_R2BF_S16_ST_INCP + 0U, // EE_FFT_VST_R32_DECP + 0U, // EE_GET_GPIO_IN + 7U, // EE_LDF_128_IP + 13U, // EE_LDF_128_XP + 0U, // EE_LDF_64_IP + 0U, // EE_LDF_64_XP + 0U, // EE_LDQA_S16_128_IP + 0U, // EE_LDQA_S16_128_XP + 0U, // EE_LDQA_S8_128_IP + 0U, // EE_LDQA_S8_128_XP + 0U, // EE_LDQA_U16_128_IP + 0U, // EE_LDQA_U16_128_XP + 0U, // EE_LDQA_U8_128_IP + 0U, // EE_LDQA_U8_128_XP + 0U, // EE_LDXQ_32 + 0U, // EE_LD_128_USAR_IP + 0U, // EE_LD_128_USAR_XP + 0U, // EE_LD_ACCX_IP + 0U, // EE_LD_QACC_H_H_32_IP + 0U, // EE_LD_QACC_H_L_128_IP + 0U, // EE_LD_QACC_L_H_32_IP + 0U, // EE_LD_QACC_L_L_128_IP + 0U, // EE_LD_UA_STATE_IP + 0U, // EE_MOVI_32_A + 0U, // EE_MOVI_32_Q + 0U, // EE_MOV_S16_QACC + 0U, // EE_MOV_S8_QACC + 0U, // EE_MOV_U16_QACC + 0U, // EE_MOV_U8_QACC + 0U, // EE_NOTQ + 0U, // EE_ORQ + 0U, // EE_SET_BIT_GPIO_OUT + 0U, // EE_SLCI_2Q + 0U, // EE_SLCXXP_2Q + 0U, // EE_SRCI_2Q + 0U, // EE_SRCMB_S16_QACC + 0U, // EE_SRCMB_S8_QACC + 0U, // EE_SRCQ_128_ST_INCP + 0U, // EE_SRCXXP_2Q + 0U, // EE_SRC_Q + 0U, // EE_SRC_Q_LD_IP + 0U, // EE_SRC_Q_LD_XP + 0U, // EE_SRC_Q_QUP + 0U, // EE_SRS_ACCX + 7U, // EE_STF_128_IP + 13U, // EE_STF_128_XP + 0U, // EE_STF_64_IP + 0U, // EE_STF_64_XP + 0U, // EE_STXQ_32 + 0U, // EE_ST_ACCX_IP + 0U, // EE_ST_QACC_H_H_32_IP + 0U, // EE_ST_QACC_H_L_128_IP + 0U, // EE_ST_QACC_L_H_32_IP + 0U, // EE_ST_QACC_L_L_128_IP + 0U, // EE_ST_UA_STATE_IP + 0U, // EE_VADDS_S16 + 0U, // EE_VADDS_S16_LD_INCP + 0U, // EE_VADDS_S16_ST_INCP + 0U, // EE_VADDS_S32 + 0U, // EE_VADDS_S32_LD_INCP + 0U, // EE_VADDS_S32_ST_INCP + 0U, // EE_VADDS_S8 + 0U, // EE_VADDS_S8_LD_INCP + 0U, // EE_VADDS_S8_ST_INCP + 0U, // EE_VCMP_EQ_S16 + 0U, // EE_VCMP_EQ_S32 + 0U, // EE_VCMP_EQ_S8 + 0U, // EE_VCMP_GT_S16 + 0U, // EE_VCMP_GT_S32 + 0U, // EE_VCMP_GT_S8 + 0U, // EE_VCMP_LT_S16 + 0U, // EE_VCMP_LT_S32 + 0U, // EE_VCMP_LT_S8 + 0U, // EE_VLDBC_16 + 0U, // EE_VLDBC_16_IP + 0U, // EE_VLDBC_16_XP + 0U, // EE_VLDBC_32 + 0U, // EE_VLDBC_32_IP + 0U, // EE_VLDBC_32_XP + 0U, // EE_VLDBC_8 + 0U, // EE_VLDBC_8_IP + 0U, // EE_VLDBC_8_XP + 0U, // EE_VLDHBC_16_INCP + 0U, // EE_VLD_128_IP + 0U, // EE_VLD_128_XP + 0U, // EE_VLD_H_64_IP + 0U, // EE_VLD_H_64_XP + 0U, // EE_VLD_L_64_IP + 0U, // EE_VLD_L_64_XP + 0U, // EE_VMAX_S16 + 0U, // EE_VMAX_S16_LD_INCP + 0U, // EE_VMAX_S16_ST_INCP + 0U, // EE_VMAX_S32 + 0U, // EE_VMAX_S32_LD_INCP + 0U, // EE_VMAX_S32_ST_INCP + 0U, // EE_VMAX_S8 + 0U, // EE_VMAX_S8_LD_INCP + 0U, // EE_VMAX_S8_ST_INCP + 0U, // EE_VMIN_S16 + 0U, // EE_VMIN_S16_LD_INCP + 0U, // EE_VMIN_S16_ST_INCP + 0U, // EE_VMIN_S32 + 0U, // EE_VMIN_S32_LD_INCP + 0U, // EE_VMIN_S32_ST_INCP + 0U, // EE_VMIN_S8 + 0U, // EE_VMIN_S8_LD_INCP + 0U, // EE_VMIN_S8_ST_INCP + 0U, // EE_VMULAS_S16_ACCX + 0U, // EE_VMULAS_S16_ACCX_LD_IP + 0U, // EE_VMULAS_S16_ACCX_LD_IP_QUP + 0U, // EE_VMULAS_S16_ACCX_LD_XP + 0U, // EE_VMULAS_S16_ACCX_LD_XP_QUP + 0U, // EE_VMULAS_S16_QACC + 0U, // EE_VMULAS_S16_QACC_LDBC_INCP + 0U, // EE_VMULAS_S16_QACC_LDBC_INCP_QUP + 0U, // EE_VMULAS_S16_QACC_LD_IP + 0U, // EE_VMULAS_S16_QACC_LD_IP_QUP + 0U, // EE_VMULAS_S16_QACC_LD_XP + 0U, // EE_VMULAS_S16_QACC_LD_XP_QUP + 0U, // EE_VMULAS_S8_ACCX + 0U, // EE_VMULAS_S8_ACCX_LD_IP + 0U, // EE_VMULAS_S8_ACCX_LD_IP_QUP + 0U, // EE_VMULAS_S8_ACCX_LD_XP + 0U, // EE_VMULAS_S8_ACCX_LD_XP_QUP + 0U, // EE_VMULAS_S8_QACC + 0U, // EE_VMULAS_S8_QACC_LDBC_INCP + 0U, // EE_VMULAS_S8_QACC_LDBC_INCP_QUP + 0U, // EE_VMULAS_S8_QACC_LD_IP + 0U, // EE_VMULAS_S8_QACC_LD_IP_QUP + 0U, // EE_VMULAS_S8_QACC_LD_XP + 0U, // EE_VMULAS_S8_QACC_LD_XP_QUP + 0U, // EE_VMULAS_U16_ACCX + 0U, // EE_VMULAS_U16_ACCX_LD_IP + 0U, // EE_VMULAS_U16_ACCX_LD_IP_QUP + 0U, // EE_VMULAS_U16_ACCX_LD_XP + 0U, // EE_VMULAS_U16_ACCX_LD_XP_QUP + 0U, // EE_VMULAS_U16_QACC + 0U, // EE_VMULAS_U16_QACC_LDBC_INCP + 0U, // EE_VMULAS_U16_QACC_LDBC_INCP_QUP + 0U, // EE_VMULAS_U16_QACC_LD_IP + 0U, // EE_VMULAS_U16_QACC_LD_IP_QUP + 0U, // EE_VMULAS_U16_QACC_LD_XP + 0U, // EE_VMULAS_U16_QACC_LD_XP_QUP + 0U, // EE_VMULAS_U8_ACCX + 0U, // EE_VMULAS_U8_ACCX_LD_IP + 0U, // EE_VMULAS_U8_ACCX_LD_IP_QUP + 0U, // EE_VMULAS_U8_ACCX_LD_XP + 0U, // EE_VMULAS_U8_ACCX_LD_XP_QUP + 0U, // EE_VMULAS_U8_QACC + 0U, // EE_VMULAS_U8_QACC_LDBC_INCP + 0U, // EE_VMULAS_U8_QACC_LDBC_INCP_QUP + 0U, // EE_VMULAS_U8_QACC_LD_IP + 0U, // EE_VMULAS_U8_QACC_LD_IP_QUP + 0U, // EE_VMULAS_U8_QACC_LD_XP + 0U, // EE_VMULAS_U8_QACC_LD_XP_QUP + 0U, // EE_VMUL_S16 + 0U, // EE_VMUL_S16_LD_INCP + 0U, // EE_VMUL_S16_ST_INCP + 0U, // EE_VMUL_S8 + 0U, // EE_VMUL_S8_LD_INCP + 0U, // EE_VMUL_S8_ST_INCP + 0U, // EE_VMUL_U16 + 0U, // EE_VMUL_U16_LD_INCP + 0U, // EE_VMUL_U16_ST_INCP + 0U, // EE_VMUL_U8 + 0U, // EE_VMUL_U8_LD_INCP + 0U, // EE_VMUL_U8_ST_INCP + 0U, // EE_VPRELU_S16 + 0U, // EE_VPRELU_S8 + 0U, // EE_VRELU_S16 + 0U, // EE_VRELU_S8 + 0U, // EE_VSL_32 + 0U, // EE_VSMULAS_S16_QACC + 0U, // EE_VSMULAS_S16_QACC_LD_INCP + 0U, // EE_VSMULAS_S8_QACC + 0U, // EE_VSMULAS_S8_QACC_LD_INCP + 0U, // EE_VSR_32 + 0U, // EE_VST_128_IP + 0U, // EE_VST_128_XP + 0U, // EE_VST_H_64_IP + 0U, // EE_VST_H_64_XP + 0U, // EE_VST_L_64_IP + 0U, // EE_VST_L_64_XP + 0U, // EE_VSUBS_S16 + 0U, // EE_VSUBS_S16_LD_INCP + 0U, // EE_VSUBS_S16_ST_INCP + 0U, // EE_VSUBS_S32 + 0U, // EE_VSUBS_S32_LD_INCP + 0U, // EE_VSUBS_S32_ST_INCP + 0U, // EE_VSUBS_S8 + 0U, // EE_VSUBS_S8_LD_INCP + 0U, // EE_VSUBS_S8_ST_INCP + 0U, // EE_VUNZIP_16 + 0U, // EE_VUNZIP_32 + 0U, // EE_VUNZIP_8 + 0U, // EE_VZIP_16 + 0U, // EE_VZIP_32 + 0U, // EE_VZIP_8 + 0U, // EE_WR_MASK_GPIO_OUT + 0U, // EE_XORQ + 0U, // EE_ZERO_ACCX + 0U, // EE_ZERO_Q + 0U, // EE_ZERO_QACC + 0U, // ENTRY + 0U, // ESYNC + 0U, // EXCW + 0U, // EXTUI + 0U, // EXTW + 0U, // FLOAT_S + 0U, // FLOOR_S + 0U, // GET_GPIO_IN + 0U, // ILL + 0U, // ILL_N + 0U, // ISYNC + 0U, // J + 0U, // JX + 0U, // L16SI + 0U, // L16UI + 0U, // L32E + 0U, // L32I + 0U, // L32I_N + 0U, // L32R + 0U, // L8UI + 0U, // LDDEC + 0U, // LDINC + 0U, // LEA_ADD + 0U, // LOOP + 0U, // LOOPGTZ + 0U, // LOOPNEZ + 0U, // LSI + 0U, // LSIP + 0U, // LSX + 0U, // LSXP + 0U, // MADDN_S + 0U, // MADD_S + 0U, // MAX + 0U, // MAXU + 0U, // MEMW + 0U, // MIN + 0U, // MINU + 0U, // MKDADJ_S + 0U, // MKSADJ_S + 0U, // MOVEQZ + 0U, // MOVEQZ_S + 0U, // MOVF + 0U, // MOVF_S + 0U, // MOVGEZ + 0U, // MOVGEZ_S + 0U, // MOVI + 0U, // MOVI_N + 0U, // MOVLTZ + 0U, // MOVLTZ_S + 0U, // MOVNEZ + 0U, // MOVNEZ_S + 0U, // MOVSP + 0U, // MOVT + 0U, // MOVT_S + 0U, // MOV_N + 0U, // MOV_S + 0U, // MSUB_S + 0U, // MUL16S + 0U, // MUL16U + 0U, // MULA_AA_HH + 0U, // MULA_AA_HL + 0U, // MULA_AA_LH + 0U, // MULA_AA_LL + 0U, // MULA_AD_HH + 0U, // MULA_AD_HL + 0U, // MULA_AD_LH + 0U, // MULA_AD_LL + 0U, // MULA_DA_HH + 0U, // MULA_DA_HH_LDDEC + 0U, // MULA_DA_HH_LDINC + 0U, // MULA_DA_HL + 0U, // MULA_DA_HL_LDDEC + 0U, // MULA_DA_HL_LDINC + 0U, // MULA_DA_LH + 0U, // MULA_DA_LH_LDDEC + 0U, // MULA_DA_LH_LDINC + 0U, // MULA_DA_LL + 0U, // MULA_DA_LL_LDDEC + 0U, // MULA_DA_LL_LDINC + 0U, // MULA_DD_HH + 0U, // MULA_DD_HH_LDDEC + 0U, // MULA_DD_HH_LDINC + 0U, // MULA_DD_HL + 0U, // MULA_DD_HL_LDDEC + 0U, // MULA_DD_HL_LDINC + 0U, // MULA_DD_LH + 0U, // MULA_DD_LH_LDDEC + 0U, // MULA_DD_LH_LDINC + 0U, // MULA_DD_LL + 0U, // MULA_DD_LL_LDDEC + 0U, // MULA_DD_LL_LDINC + 0U, // MULL + 0U, // MULSH + 0U, // MULS_AA_HH + 0U, // MULS_AA_HL + 0U, // MULS_AA_LH + 0U, // MULS_AA_LL + 0U, // MULS_AD_HH + 0U, // MULS_AD_HL + 0U, // MULS_AD_LH + 0U, // MULS_AD_LL + 0U, // MULS_DA_HH + 0U, // MULS_DA_HL + 0U, // MULS_DA_LH + 0U, // MULS_DA_LL + 0U, // MULS_DD_HH + 0U, // MULS_DD_HL + 0U, // MULS_DD_LH + 0U, // MULS_DD_LL + 0U, // MULUH + 0U, // MUL_AA_HH + 0U, // MUL_AA_HL + 0U, // MUL_AA_LH + 0U, // MUL_AA_LL + 0U, // MUL_AD_HH + 0U, // MUL_AD_HL + 0U, // MUL_AD_LH + 0U, // MUL_AD_LL + 0U, // MUL_DA_HH + 0U, // MUL_DA_HL + 0U, // MUL_DA_LH + 0U, // MUL_DA_LL + 0U, // MUL_DD_HH + 0U, // MUL_DD_HL + 0U, // MUL_DD_LH + 0U, // MUL_DD_LL + 0U, // MUL_S + 0U, // NEG + 0U, // NEG_S + 0U, // NEXP01_S + 0U, // NOP + 0U, // NSA + 0U, // NSAU + 0U, // OEQ_S + 0U, // OLE_S + 0U, // OLT_S + 0U, // OR + 0U, // ORB + 0U, // ORBC + 0U, // QUOS + 0U, // QUOU + 0U, // RECIP0_S + 0U, // REMS + 0U, // REMU + 0U, // RER + 0U, // RET + 0U, // RETW + 0U, // RETW_N + 0U, // RET_N + 0U, // RFDE + 0U, // RFE + 0U, // RFI + 0U, // RFR + 0U, // RFWO + 0U, // RFWU + 0U, // ROTW + 0U, // ROUND_S + 0U, // RSIL + 0U, // RSQRT0_S + 0U, // RSR + 0U, // RSYNC + 0U, // RUR + 0U, // RUR_ACCX_0 + 0U, // RUR_ACCX_1 + 0U, // RUR_AE_BITHEAD + 0U, // RUR_AE_BITPTR + 0U, // RUR_AE_BITSUSED + 0U, // RUR_AE_CBEGIN0 + 0U, // RUR_AE_CEND0 + 0U, // RUR_AE_CWRAP + 0U, // RUR_AE_CW_SD_NO + 0U, // RUR_AE_FIRST_TS + 0U, // RUR_AE_NEXTOFFSET + 0U, // RUR_AE_OVERFLOW + 0U, // RUR_AE_OVF_SAR + 0U, // RUR_AE_SAR + 0U, // RUR_AE_SEARCHDONE + 0U, // RUR_AE_TABLESIZE + 0U, // RUR_AE_TS_FTS_BU_BP + 0U, // RUR_FFT_BIT_WIDTH + 0U, // RUR_GPIO_OUT + 0U, // RUR_QACC_H_0 + 0U, // RUR_QACC_H_1 + 0U, // RUR_QACC_H_2 + 0U, // RUR_QACC_H_3 + 0U, // RUR_QACC_H_4 + 0U, // RUR_QACC_L_0 + 0U, // RUR_QACC_L_1 + 0U, // RUR_QACC_L_2 + 0U, // RUR_QACC_L_3 + 0U, // RUR_QACC_L_4 + 0U, // RUR_SAR_BYTE + 0U, // RUR_UA_STATE_0 + 0U, // RUR_UA_STATE_1 + 0U, // RUR_UA_STATE_2 + 0U, // RUR_UA_STATE_3 + 0U, // S16I + 0U, // S32C1I + 0U, // S32E + 0U, // S32I + 0U, // S32I_N + 0U, // S8I + 0U, // SET_BIT_GPIO_OUT + 0U, // SEXT + 0U, // SIMCALL + 0U, // SLL + 0U, // SLLI + 0U, // SQRT0_S + 0U, // SRA + 0U, // SRAI + 0U, // SRC + 0U, // SRL + 0U, // SRLI + 0U, // SSA8L + 0U, // SSAI + 0U, // SSI + 0U, // SSIP + 0U, // SSL + 0U, // SSR + 0U, // SSX + 0U, // SSXP + 0U, // SUB + 0U, // SUBX2 + 0U, // SUBX4 + 0U, // SUBX8 + 0U, // SUB_S + 0U, // SYSCALL + 0U, // TRUNC_S + 0U, // UEQ_S + 0U, // UFLOAT_S + 0U, // ULE_S + 0U, // ULT_S + 0U, // UMUL_AA_HH + 0U, // UMUL_AA_HL + 0U, // UMUL_AA_LH + 0U, // UMUL_AA_LL + 0U, // UN_S + 0U, // UTRUNC_S + 0U, // WAITI + 0U, // WDTLB + 0U, // WER + 0U, // WFR + 0U, // WITLB + 0U, // WR_MASK_GPIO_OUT + 0U, // WSR + 0U, // WUR + 0U, // WUR_ACCX_0 + 0U, // WUR_ACCX_1 + 0U, // WUR_AE_BITHEAD + 0U, // WUR_AE_BITPTR + 0U, // WUR_AE_BITSUSED + 0U, // WUR_AE_CBEGIN0 + 0U, // WUR_AE_CEND0 + 0U, // WUR_AE_CWRAP + 0U, // WUR_AE_CW_SD_NO + 0U, // WUR_AE_FIRST_TS + 0U, // WUR_AE_NEXTOFFSET + 0U, // WUR_AE_OVERFLOW + 0U, // WUR_AE_OVF_SAR + 0U, // WUR_AE_SAR + 0U, // WUR_AE_SEARCHDONE + 0U, // WUR_AE_TABLESIZE + 0U, // WUR_AE_TS_FTS_BU_BP + 0U, // WUR_FCR + 0U, // WUR_FFT_BIT_WIDTH + 0U, // WUR_FSR + 0U, // WUR_GPIO_OUT + 0U, // WUR_QACC_H_0 + 0U, // WUR_QACC_H_1 + 0U, // WUR_QACC_H_2 + 0U, // WUR_QACC_H_3 + 0U, // WUR_QACC_H_4 + 0U, // WUR_QACC_L_0 + 0U, // WUR_QACC_L_1 + 0U, // WUR_QACC_L_2 + 0U, // WUR_QACC_L_3 + 0U, // WUR_QACC_L_4 + 0U, // WUR_SAR_BYTE + 0U, // WUR_UA_STATE_0 + 0U, // WUR_UA_STATE_1 + 0U, // WUR_UA_STATE_2 + 0U, // WUR_UA_STATE_3 + 0U, // XOR + 0U, // XORB + 0U, // XSR + 0U, // _L32I + 0U, // _L32I_N + 0U, // _MOVI + 0U, // _S32I + 0U, // _S32I_N + 0U, // _SLLI + 0U, // _SRLI + 0U, // mv_QR }; // Emit the opcode for the instruction. - uint32_t Bits = 0; - Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; - Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + Bits |= (uint64_t)OpInfo2[MCInst_getOpcode(MI)] << 48; MnemonicBitsInfo MBI = { #ifndef CAPSTONE_DIET - AsmStrs+(Bits & 1023)-1, + AsmStrs+(Bits & 32767)-1, #else NULL, #endif // CAPSTONE_DIET @@ -845,171 +7734,831 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { SStream_concat0(O, MnemonicInfo.first); - uint32_t Bits = MnemonicInfo.second; - assert(Bits != 0 && "Cannot print this instruction."); + uint64_t Bits = MnemonicInfo.second; + CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 4 bits for 13 unique commands. + switch ((Bits >> 15) & 15) { + default: CS_ASSERT_RET(0 && "Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // ATOMIC_CMP_SWAP_16_P, ATOMIC_CMP_SWAP_32_P, ATOMIC_CMP_SWAP_8_P, ATOMI... + printOperand(MI, 0, O); + break; + case 2: + // EE_ANDQ_P, EE_BITREV_P, EE_CMUL_S16_LD_INCP_P, EE_CMUL_S16_P, EE_CMUL_... + printImm8_AsmOperand(MI, 0, O); + break; + case 3: + // LOOPEND + printBranchTarget(MI, 0, O); + return; + break; + case 4: + // ADDEXPM_S, ADDEXP_S, AE_DB, AE_DBI, AE_DBI_IC, AE_DBI_IP, AE_DB_IC, AE... + printOperand(MI, 1, O); + break; + case 5: + // AE_MULA16X4, AE_MULAF16X4SS, AE_MULAFD24X2_FIR_H, AE_MULAFD24X2_FIR_L,... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + break; + case 6: + // BREAK, BREAK_N, RFI, WAITI + printUimm4_AsmOperand(MI, 0, O); + break; + case 7: + // CALL0, CALL12, CALL4, CALL8 + printCallOperand(MI, 0, O); + return; + break; + case 8: + // CLR_BIT_GPIO_OUT, EE_CLR_BIT_GPIO_OUT, EE_SET_BIT_GPIO_OUT, SET_BIT_GP... + printSelect_256_AsmOperand(MI, 0, O); + return; + break; + case 9: + // EE_FFT_AMS_S16_ST_INCP, EE_SLCXXP_2Q, EE_SRCXXP_2Q + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 10: + // J + printJumpTarget(MI, 0, O); + return; + break; + case 11: + // ROTW + printImm8n_7_AsmOperand(MI, 0, O); + return; + break; + case 12: + // SSAI + printUimm5_AsmOperand(MI, 0, O); + return; + break; + } + + + // Fragment 1 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 19) & 3) { + default: CS_ASSERT_RET(0 && "Invalid command number."); + case 0: + // ATOMIC_CMP_SWAP_16_P, ATOMIC_CMP_SWAP_32_P, ATOMIC_CMP_SWAP_8_P, ATOMI... + SStream_concat0(O, ", "); + break; + case 1: + // EE_MOV_S16_QACC_P, EE_MOV_S8_QACC_P, EE_MOV_U16_QACC_P, EE_MOV_U8_QACC... + return; + break; + case 2: + // EE_FFT_AMS_S16_ST_INCP + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 6, O); + SStream_concat0(O, ", "); + printOperand(MI, 7, O); + SStream_concat0(O, ", "); + printOperand(MI, 8, O); + SStream_concat0(O, ", "); + printSelect_2_AsmOperand(MI, 9, O); + return; + break; + case 3: + // EE_SLCXXP_2Q, EE_SRCXXP_2Q + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 6, O); + return; + break; + } + + + // Fragment 2 encoded into 5 bits for 29 unique commands. + switch ((Bits >> 21) & 31) { + default: CS_ASSERT_RET(0 && "Invalid command number."); + case 0: + // ATOMIC_CMP_SWAP_16_P, ATOMIC_CMP_SWAP_32_P, ATOMIC_CMP_SWAP_8_P, ATOMI... + printOperand(MI, 1, O); + break; + case 1: + // EE_ANDQ_P, EE_CMUL_S16_P, EE_FFT_AMS_S16_ST_INCP_P, EE_FFT_CMUL_S16_ST... + printImm8_AsmOperand(MI, 1, O); + break; + case 2: + // EE_LDQA_S16_128_IP_P, EE_LDQA_S8_128_IP_P, EE_LDQA_U16_128_IP_P, EE_LD... + printOffset_256_16_AsmOperand(MI, 1, O); + return; + break; + case 3: + // EE_LD_ACCX_IP_P, EE_ST_ACCX_IP_P + printOffset_256_8_AsmOperand(MI, 1, O); + return; + break; + case 4: + // EE_LD_QACC_H_H_32_IP_P, EE_LD_QACC_L_H_32_IP_P, EE_ST_QACC_H_H_32_IP_P... + printOffset_256_4_AsmOperand(MI, 1, O); + return; + break; + case 5: + // L8I_P, RESTORE_BOOL, SPILL_BOOL, L16SI, L16UI, L32I, L32I_N, L8UI, LEA... + printMemOperand(MI, 1, O); + return; + break; + case 6: + // LOOPBR, LOOPSTART, BEQZ, BF, BGEZ, BLTZ, BNEZ, BT + printBranchTarget(MI, 1, O); + return; + break; + case 7: + // ADDEXPM_S, ADDEXP_S, AE_DB, AE_DB_IC, AE_DB_IP, AE_DIV64D32_H, AE_DIV6... + printOperand(MI, 2, O); + break; + case 8: + // AE_DBI, AE_DBI_IC, AE_DBI_IP + printImm1_16_AsmOperand(MI, 2, O); + return; + break; + case 9: + // AE_LA16X4_IC, AE_LA16X4_IP, AE_LA16X4_RIC, AE_LA16X4_RIP, AE_LA24X2_IC... + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + break; + case 10: + // AE_LBI, AE_LBSI + printImm1_16_AsmOperand(MI, 1, O); + return; + break; + case 11: + // AE_MOVI + printImmOperand_minus16_47_1(MI, 1, O); + return; + break; + case 12: + // AE_MULA16X4, AE_MULAF16X4SS, AE_MULAFD24X2_FIR_H, AE_MULAFD24X2_FIR_L,... + printOperand(MI, 4, O); + break; + case 13: + // BBCI, BBSI + printUimm5_AsmOperand(MI, 1, O); + SStream_concat0(O, ", "); + printBranchTarget(MI, 2, O); + return; + break; + case 14: + // BEQI, BGEI, BLTI, BNEI + printB4const_AsmOperand(MI, 1, O); + SStream_concat0(O, ", "); + printBranchTarget(MI, 2, O); + return; + break; + case 15: + // BGEUI, BLTUI + printB4constu_AsmOperand(MI, 1, O); + SStream_concat0(O, ", "); + printBranchTarget(MI, 2, O); + return; + break; + case 16: + // BREAK, CONST_S, RSIL + printUimm4_AsmOperand(MI, 1, O); + return; + break; + case 17: + // EE_LDQA_S16_128_IP, EE_LDQA_S8_128_IP, EE_LDQA_U16_128_IP, EE_LDQA_U8_... + printOffset_256_16_AsmOperand(MI, 2, O); + return; + break; + case 18: + // EE_LD_ACCX_IP, EE_ST_ACCX_IP + printOffset_256_8_AsmOperand(MI, 2, O); + return; + break; + case 19: + // EE_LD_QACC_H_H_32_IP, EE_LD_QACC_L_H_32_IP, EE_ST_QACC_H_H_32_IP, EE_S... + printOffset_256_4_AsmOperand(MI, 2, O); + return; + break; + case 20: + // EE_MOVI_32_A, WSR, WUR + printOperand(MI, 0, O); + break; + case 21: + // EE_SLCI_2Q, EE_SRCI_2Q + printSelect_16_AsmOperand(MI, 4, O); + return; + break; + case 22: + // ENTRY + printEntry_Imm12_AsmOperand(MI, 1, O); + return; + break; + case 23: + // L32R + printL32RTarget(MI, 1, O); + return; + break; + case 24: + // LOOP, LOOPGTZ, LOOPNEZ + printLoopTarget(MI, 1, O); + return; + break; + case 25: + // MOVI + printImm12m_AsmOperand(MI, 1, O); + return; + break; + case 26: + // MOVI_N + printImm32n_95_AsmOperand(MI, 1, O); + return; + break; + case 27: + // S32C1I + printMemOperand(MI, 2, O); + return; + break; + case 28: + // _MOVI + printImm12_AsmOperand(MI, 1, O); + return; + break; + } + + + // Fragment 3 encoded into 3 bits for 6 unique commands. + switch ((Bits >> 26) & 7) { + default: CS_ASSERT_RET(0 && "Invalid command number."); + case 0: + // ATOMIC_CMP_SWAP_16_P, ATOMIC_CMP_SWAP_32_P, ATOMIC_CMP_SWAP_8_P, ATOMI... + SStream_concat0(O, ", "); + break; + case 1: + // BR_JT, EE_BITREV_P, EE_LDQA_S16_128_XP_P, EE_LDQA_S8_128_XP_P, EE_LDQA... + return; + break; + case 2: + // AE_LA16X4_IC, AE_LA16X4_IP, AE_LA16X4_RIC, AE_LA16X4_RIP, AE_LA24X2_IC... + printOperand(MI, 4, O); + break; + case 3: + // EE_CMUL_S16_LD_INCP, EE_VADDS_S16_LD_INCP, EE_VADDS_S32_LD_INCP, EE_VA... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + break; + case 4: + // EE_SRC_Q_LD_IP + printOffset_256_16_AsmOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 6, O); + return; + break; + case 5: + // EE_VMULAS_S16_ACCX_LD_IP_QUP, EE_VMULAS_S16_QACC_LD_IP_QUP, EE_VMULAS_... + printOffset_64_16_AsmOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 6, O); + SStream_concat0(O, ", "); + printOperand(MI, 7, O); + SStream_concat0(O, ", "); + printOperand(MI, 8, O); + return; + break; + } + + + // Fragment 4 encoded into 6 bits for 45 unique commands. + switch ((Bits >> 29) & 63) { + default: CS_ASSERT_RET(0 && "Invalid command number."); + case 0: + // ATOMIC_CMP_SWAP_16_P, ATOMIC_CMP_SWAP_32_P, ATOMIC_CMP_SWAP_8_P, ATOMI... + printOperand(MI, 2, O); + break; + case 1: + // EE_ANDQ_P, EE_CMUL_S16_LD_INCP_P, EE_CMUL_S16_P, EE_CMUL_S16_ST_INCP_P... + printImm8_AsmOperand(MI, 2, O); + break; + case 2: + // EE_FFT_VST_R32_DECP_P, EE_SRCMB_S16_QACC_P, EE_SRCMB_S8_QACC_P, EE_SRS... + printSelect_2_AsmOperand(MI, 2, O); + return; + break; + case 3: + // EE_LD_128_USAR_IP_P, EE_SRC_Q_LD_IP_P, EE_VLD_128_IP_P, EE_VST_128_IP_... + printOffset_256_16_AsmOperand(MI, 2, O); + break; + case 4: + // EE_MOVI_32_A_P, EE_MOVI_32_Q_P, EE_MOVI_32_A, EE_MOVI_32_Q + printSelect_4_AsmOperand(MI, 2, O); + return; + break; + case 5: + // EE_SLCI_2Q_P, EE_SRCI_2Q_P, EE_VSMULAS_S8_QACC_P, EE_VSMULAS_S8_QACC + printSelect_16_AsmOperand(MI, 2, O); + return; + break; + case 6: + // EE_VLDBC_16_IP_P + printOffset_128_2_AsmOperand(MI, 2, O); + return; + break; + case 7: + // EE_VLDBC_32_IP_P + printOffset_256_4_AsmOperand(MI, 2, O); + return; + break; + case 8: + // EE_VLDBC_8_IP_P + printOffset_128_1_AsmOperand(MI, 2, O); + return; + break; + case 9: + // EE_VLD_H_64_IP_P, EE_VLD_L_64_IP_P, EE_VST_H_64_IP_P, EE_VST_L_64_IP_P + printOffset_256_8_AsmOperand(MI, 2, O); + return; + break; + case 10: + // EE_VMULAS_S16_ACCX_LD_IP_P, EE_VMULAS_S16_ACCX_LD_IP_QUP_P, EE_VMULAS_... + printOffset_64_16_AsmOperand(MI, 2, O); + SStream_concat0(O, ", "); + printImm8_AsmOperand(MI, 3, O); + SStream_concat0(O, ", "); + printImm8_AsmOperand(MI, 4, O); + break; + case 11: + // EE_VSMULAS_S16_QACC_P, EE_VSMULAS_S16_QACC + printSelect_8_AsmOperand(MI, 2, O); + return; + break; + case 12: + // ADDI_N + printImm1n_15_AsmOperand(MI, 2, O); + return; + break; + case 13: + // ADDMI + printImm8_sh8_AsmOperand(MI, 2, O); + return; + break; + case 14: + // AE_L16M_I, AE_L16_I, AE_S16M_L_I, AE_S16_0_I + printImmOperand_minus16_14_2(MI, 2, O); + return; + break; + case 15: + // AE_L16M_IU, AE_L16_IP, AE_S16M_L_IU, AE_S16_0_IP + printImmOperand_minus16_14_2(MI, 3, O); + return; + break; + case 16: + // AE_L16M_XC, AE_L16M_XU, AE_L16X2M_XC, AE_L16X2M_XU, AE_L16X4_XC, AE_L1... + printOperand(MI, 3, O); + break; + case 17: + // AE_L16X2M_I, AE_L32F24_I, AE_L32M_I, AE_L32_I, AE_S16X2M_I, AE_S24RA64... + printImmOperand_minus32_28_4(MI, 2, O); + return; + break; + case 18: + // AE_L16X2M_IU, AE_L32F24_IP, AE_L32M_IU, AE_L32_IP, AE_S16X2M_IU, AE_S2... + printImmOperand_minus32_28_4(MI, 3, O); + return; + break; + case 19: + // AE_L16X4_I, AE_L32X2F24_I, AE_L32X2_I, AE_L64_I, AE_LALIGN64_I, AE_S16... + printImmOperand_minus64_56_8(MI, 2, O); + return; + break; + case 20: + // AE_L16X4_IP, AE_L32X2F24_IP, AE_L32X2_IP, AE_S16X4_IP, AE_S32X2F24_IP,... + printImmOperand_0_56_8(MI, 3, O); + return; + break; + case 21: + // AE_L64_IP, AE_S64_IP + printImmOperand_minus64_56_8(MI, 3, O); + return; + break; + case 22: + // AE_LA16X4_IC, AE_LA16X4_IP, AE_LA16X4_RIC, AE_LA16X4_RIP, AE_LA24X2_IC... + return; + break; + case 23: + // AE_LBKI + printImm1_16_AsmOperand(MI, 2, O); + return; + break; + case 24: + // AE_MULA16X4, AE_MULAF16X4SS, AE_MULAFD24X2_FIR_H, AE_MULAFD24X2_FIR_L,... + printOperand(MI, 5, O); + break; + case 25: + // AE_PKSR24, AE_PKSR32 + printImmOperand_0_3_1(MI, 3, O); + return; + break; + case 26: + // AE_SBI, AE_SBI_IC, AE_SBI_IP + printImm1_16_AsmOperand(MI, 3, O); + return; + break; + case 27: + // AE_SEXT32, CLAMPS, SEXT + printImm7_22_AsmOperand(MI, 2, O); + return; + break; + case 28: + // AE_SLAI16S, AE_SRAI16, AE_SRAI16R, CEIL_S, FLOAT_S, FLOOR_S, ROUND_S, ... + printUimm4_AsmOperand(MI, 2, O); + return; + break; + case 29: + // AE_SLAI24, AE_SLAI24S, AE_SLAI32, AE_SLAI32S, AE_SRAI24, AE_SRAI32, AE... + printUimm5_AsmOperand(MI, 2, O); + break; + case 30: + // AE_SLAI64, AE_SLAI64S, AE_SLAISQ56S, AE_SRAI64, AE_SRLI64 + printImmOperand_0_63_1(MI, 2, O); + return; + break; + case 31: + // BALL, BANY, BBC, BBS, BEQ, BGE, BGEU, BLT, BLTU, BNALL, BNE, BNONE + printBranchTarget(MI, 2, O); + return; + break; + case 32: + // EE_CMUL_S16_LD_INCP, EE_FFT_CMUL_S16_LD_XP, EE_SRC_Q_LD_XP, EE_VMULAS_... + SStream_concat0(O, ", "); + break; + case 33: + // EE_CMUL_S16_ST_INCP, EE_VADDS_S16_ST_INCP, EE_VADDS_S32_ST_INCP, EE_VA... + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + break; + case 34: + // EE_FFT_VST_R32_DECP + printSelect_2_AsmOperand(MI, 3, O); + return; + break; + case 35: + // EE_LD_128_USAR_IP, EE_VLD_128_IP, EE_VST_128_IP + printOffset_256_16_AsmOperand(MI, 3, O); + return; + break; + case 36: + // EE_VLDBC_16_IP + printOffset_128_2_AsmOperand(MI, 3, O); + return; + break; + case 37: + // EE_VLDBC_32_IP + printOffset_256_4_AsmOperand(MI, 3, O); + return; + break; + case 38: + // EE_VLDBC_8_IP + printOffset_128_1_AsmOperand(MI, 3, O); + return; + break; + case 39: + // EE_VLD_H_64_IP, EE_VLD_L_64_IP, EE_VST_H_64_IP, EE_VST_L_64_IP + printOffset_256_8_AsmOperand(MI, 3, O); + return; + break; + case 40: + // EE_VMULAS_S16_ACCX_LD_IP, EE_VMULAS_S16_QACC_LD_IP, EE_VMULAS_S8_ACCX_... + printOffset_64_16_AsmOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 41: + // L32E, S32E + printImm64n_4n_AsmOperand(MI, 2, O); + return; + break; + case 42: + // LSIP, SSIP + printOffset8m32_AsmOperand(MI, 3, O); + return; + break; + case 43: + // SLLI + printShimm0_31_AsmOperand(MI, 2, O); + return; + break; + case 44: + // _SLLI + printShimm1_31_AsmOperand(MI, 2, O); + return; + break; + } + - // Fragment 0 encoded into 3 bits for 7 unique commands. - switch ((Bits >> 10) & 7) { - default: assert(0 && "Invalid command number."); + // Fragment 5 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 35) & 7) { + default: CS_ASSERT_RET(0 && "Invalid command number."); case 0: - // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... - return; + // ATOMIC_CMP_SWAP_16_P, ATOMIC_CMP_SWAP_32_P, ATOMIC_CMP_SWAP_8_P, BRCC_... + SStream_concat0(O, ", "); break; case 1: - // ABS, ADD, ADDI, ADDMI, ADDX2, ADDX4, ADDX8, AND, BALL, BANY, BBC, BBCI... - printOperand(MI, 0, O); + // ATOMIC_LOAD_ADD_16_P, ATOMIC_LOAD_ADD_32_P, ATOMIC_LOAD_ADD_8_P, ATOMI... + return; break; case 2: - // CALL0 - printCallOperand(MI, 0, O); + // EE_CMUL_S16_LD_INCP + printSelect_4_AsmOperand(MI, 6, O); return; break; case 3: - // J - printJumpTarget(MI, 0, O); + // EE_FFT_CMUL_S16_LD_XP + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 6, O); + SStream_concat0(O, ", "); + printSelect_8_AsmOperand(MI, 7, O); return; break; case 4: - // SSAI - printUimm5_AsmOperand(MI, 0, O); + // EE_SRC_Q_LD_XP, EE_VMULAS_S16_ACCX_LD_XP_QUP, EE_VMULAS_S16_QACC_LDBC_... + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 6, O); + break; + } + + + // Fragment 6 encoded into 4 bits for 15 unique commands. + switch ((Bits >> 38) & 15) { + default: CS_ASSERT_RET(0 && "Invalid command number."); + case 0: + // ATOMIC_CMP_SWAP_16_P, ATOMIC_CMP_SWAP_32_P, ATOMIC_CMP_SWAP_8_P, EE_FF... + printOperand(MI, 3, O); + break; + case 1: + // BRCC_FP + printBranchTarget(MI, 3, O); + return; + break; + case 2: + // EE_CMUL_S16_LD_INCP_P, EE_CMUL_S16_ST_INCP_P, EE_FFT_AMS_S16_LD_INCP_P... + printImm8_AsmOperand(MI, 3, O); + break; + case 3: + // EE_CMUL_S16_P, EE_LDXQ_32_P, EE_STXQ_32_P, EE_CMUL_S16, EE_LDXQ_32, EE... + printSelect_4_AsmOperand(MI, 3, O); + break; + case 4: + // EE_LDF_64_IP_P, EE_STF_64_IP_P + printOffset_256_8_AsmOperand(MI, 3, O); return; break; case 5: - // WSR - printOperand(MI, 1, O); + // EE_VMULAS_S16_ACCX_LD_IP_QUP_P, EE_VMULAS_S16_QACC_LD_IP_QUP_P, EE_VMU... + printImm8_AsmOperand(MI, 5, O); SStream_concat0(O, ", "); - printOperand(MI, 0, O); + printImm8_AsmOperand(MI, 6, O); return; break; case 6: - // XSR - printOperand(MI, 2, O); + // AE_MULAFD24X2_FIR_H, AE_MULAFD24X2_FIR_L, AE_MULAFD32X16X2_FIR_HH, AE_... + printOperand(MI, 6, O); + return; + break; + case 7: + // AE_SEL16I, AE_TRUNCI32F64S_L, AE_TRUNCI32X2F64S + printUimm4_AsmOperand(MI, 3, O); + return; + break; + case 8: + // AE_SEL16I_N + printImmOperand_0_3_1(MI, 3, O); + return; + break; + case 9: + // EE_CMUL_S16_ST_INCP + printSelect_4_AsmOperand(MI, 6, O); + return; + break; + case 10: + // EE_FFT_CMUL_S16_ST_XP, EE_FFT_R2BF_S16_ST_INCP, EE_LDF_64_XP, EE_STF_1... + printOperand(MI, 4, O); + break; + case 11: + // EE_LDF_64_IP, EE_STF_64_IP + printOffset_256_8_AsmOperand(MI, 4, O); + return; + break; + case 12: + // EE_SRC_Q_LD_XP + return; + break; + case 13: + // EE_VMULAS_S16_ACCX_LD_XP_QUP, EE_VMULAS_S16_QACC_LDBC_INCP_QUP, EE_VMU... SStream_concat0(O, ", "); - printOperand(MI, 3, O); + printOperand(MI, 7, O); + break; + case 14: + // EXTUI + printImm1_16_AsmOperand(MI, 3, O); return; break; } - // Fragment 1 encoded into 1 bits for 2 unique commands. - if ((Bits >> 13) & 1) { - // CALLX0, JX, SSA8L, SSL, SSR - return; - } else { - // ABS, ADD, ADDI, ADDMI, ADDX2, ADDX4, ADDX8, AND, BALL, BANY, BBC, BBCI... + // Fragment 7 encoded into 1 bits for 2 unique commands. + if ((Bits >> 42) & 1) { + // EE_CMUL_S16_LD_INCP_P, EE_CMUL_S16_ST_INCP_P, EE_FFT_AMS_S16_LD_INCP_P... SStream_concat0(O, ", "); + } else { + // ATOMIC_CMP_SWAP_16_P, ATOMIC_CMP_SWAP_32_P, ATOMIC_CMP_SWAP_8_P, EE_CM... + return; } - // Fragment 2 encoded into 3 bits for 8 unique commands. - switch ((Bits >> 14) & 7) { - default: assert(0 && "Invalid command number."); + // Fragment 8 encoded into 4 bits for 11 unique commands. + switch ((Bits >> 43) & 15) { + default: CS_ASSERT_RET(0 && "Invalid command number."); case 0: - // ABS, ADD, ADDI, ADDMI, ADDX2, ADDX4, ADDX8, AND, BALL, BANY, BBC, BBS,... - printOperand(MI, 1, O); + // EE_CMUL_S16_LD_INCP_P, EE_CMUL_S16_ST_INCP_P, EE_FFT_AMS_S16_LD_INCP_P... + printImm8_AsmOperand(MI, 4, O); break; case 1: - // BBCI, BBSI - printUimm5_AsmOperand(MI, 1, O); - SStream_concat0(O, ", "); - printBranchTarget(MI, 2, O); - return; + // EE_FFT_CMUL_S16_ST_XP_P, EE_LDF_128_IP_P, EE_LDF_128_XP_P, EE_STF_128_... + printOperand(MI, 4, O); break; case 2: - // BEQI, BGEI, BLTI, BNEI - printB4const_AsmOperand(MI, 1, O); - SStream_concat0(O, ", "); - printBranchTarget(MI, 2, O); + // EE_FFT_R2BF_S16_P, EE_FFT_R2BF_S16 + printSelect_2_AsmOperand(MI, 4, O); return; break; case 3: - // BEQZ, BGEZ, BLTZ, BNEZ - printBranchTarget(MI, 1, O); + // EE_FFT_R2BF_S16_ST_INCP_P + printSelect_4_AsmOperand(MI, 4, O); return; break; case 4: - // BGEUI, BLTUI - printB4constu_AsmOperand(MI, 1, O); - SStream_concat0(O, ", "); - printBranchTarget(MI, 2, O); + // EE_LDXQ_32_P, EE_STXQ_32_P, EE_VSMULAS_S16_QACC_LD_INCP_P, EE_LDXQ_32,... + printSelect_8_AsmOperand(MI, 4, O); return; break; case 5: - // L16SI, L16UI, L32I, L8UI, S16I, S32I, S8I - printMemOperand(MI, 1, O); + // EE_VSMULAS_S8_QACC_LD_INCP_P + printSelect_16_AsmOperand(MI, 4, O); return; break; case 6: - // L32R - printL32RTarget(MI, 1, O); - return; + // EE_FFT_AMS_S16_LD_INCP, EE_FFT_AMS_S16_LD_INCP_UAUP, EE_FFT_AMS_S16_LD... + printOperand(MI, 5, O); break; case 7: - // MOVI - printImm12m_AsmOperand(MI, 1, O); + // EE_FFT_R2BF_S16_ST_INCP + printSelect_4_AsmOperand(MI, 5, O); + return; + break; + case 8: + // EE_VMULAS_S16_ACCX_LD_XP_QUP, EE_VMULAS_S16_QACC_LD_XP_QUP, EE_VMULAS_... + printOperand(MI, 8, O); + return; + break; + case 9: + // EE_VSMULAS_S16_QACC_LD_INCP + printSelect_8_AsmOperand(MI, 5, O); + return; + break; + case 10: + // EE_VSMULAS_S8_QACC_LD_INCP + printSelect_16_AsmOperand(MI, 5, O); return; break; } - // Fragment 3 encoded into 1 bits for 2 unique commands. - if ((Bits >> 17) & 1) { - // ADD, ADDI, ADDMI, ADDX2, ADDX4, ADDX8, AND, BALL, BANY, BBC, BBS, BEQ,... - SStream_concat0(O, ", "); - } else { - // ABS, NEG, RSR, SLL, SRA, SRL + // Fragment 9 encoded into 1 bits for 2 unique commands. + if ((Bits >> 47) & 1) { + // EE_SRC_Q_LD_IP_P, EE_SRC_Q_LD_XP_P, EE_VADDS_S16_LD_INCP_P, EE_VADDS_S... return; + } else { + // EE_CMUL_S16_LD_INCP_P, EE_CMUL_S16_ST_INCP_P, EE_FFT_AMS_S16_LD_INCP_P... + SStream_concat0(O, ", "); } - // Fragment 4 encoded into 3 bits for 7 unique commands. - switch ((Bits >> 18) & 7) { - default: assert(0 && "Invalid command number."); + // Fragment 10 encoded into 3 bits for 8 unique commands. + switch ((Bits >> 48) & 7) { + default: CS_ASSERT_RET(0 && "Invalid command number."); case 0: - // ADD, ADDX2, ADDX4, ADDX8, AND, MOVEQZ, MOVGEZ, MOVLTZ, MOVNEZ, OR, SRC... - printOperand(MI, 2, O); + // EE_CMUL_S16_LD_INCP_P, EE_CMUL_S16_ST_INCP_P + printSelect_4_AsmOperand(MI, 5, O); return; break; case 1: - // ADDI - printImm8_AsmOperand(MI, 2, O); - return; + // EE_FFT_AMS_S16_LD_INCP_P, EE_FFT_AMS_S16_LD_INCP_UAUP_P, EE_FFT_AMS_S1... + printImm8_AsmOperand(MI, 5, O); break; case 2: - // ADDMI - printImm8_sh8_AsmOperand(MI, 2, O); + // EE_FFT_CMUL_S16_ST_XP_P + printSelect_8_AsmOperand(MI, 5, O); + SStream_concat0(O, ", "); + printSelect_4_AsmOperand(MI, 6, O); + SStream_concat0(O, ", "); + printSelect_4_AsmOperand(MI, 7, O); return; break; case 3: - // BALL, BANY, BBC, BBS, BEQ, BGE, BGEU, BLT, BLTU, BNALL, BNE, BNONE - printBranchTarget(MI, 2, O); + // EE_LDF_128_IP_P, EE_STF_128_IP_P + printOffset_16_16_AsmOperand(MI, 5, O); return; break; case 4: - // EXTUI, SRAI - printUimm5_AsmOperand(MI, 2, O); + // EE_LDF_128_XP_P, EE_STF_128_XP_P, SELECT, SELECT_CC_FP_FP, SELECT_CC_F... + printOperand(MI, 5, O); + return; break; case 5: - // SLLI - printShimm1_31_AsmOperand(MI, 2, O); - return; + // EE_FFT_AMS_S16_LD_INCP, EE_FFT_AMS_S16_LD_INCP_UAUP, EE_FFT_AMS_S16_LD... + printOperand(MI, 6, O); break; case 6: - // SRLI - printUimm4_AsmOperand(MI, 2, O); + // EE_FFT_CMUL_S16_ST_XP + printSelect_8_AsmOperand(MI, 6, O); + SStream_concat0(O, ", "); + printSelect_4_AsmOperand(MI, 7, O); + SStream_concat0(O, ", "); + printSelect_4_AsmOperand(MI, 8, O); + return; + break; + case 7: + // EE_LDF_128_IP, EE_STF_128_IP + printOffset_16_16_AsmOperand(MI, 6, O); return; break; } - // Fragment 5 encoded into 1 bits for 2 unique commands. - if ((Bits >> 21) & 1) { - // SRAI + // Fragment 11 encoded into 1 bits for 2 unique commands. + if ((Bits >> 51) & 1) { + // EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P, EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P,... return; } else { - // EXTUI + // EE_FFT_AMS_S16_LD_INCP_P, EE_FFT_AMS_S16_LD_INCP_UAUP_P, EE_FFT_AMS_S1... SStream_concat0(O, ", "); - printImm1_16_AsmOperand(MI, 3, O); + } + + + // Fragment 12 encoded into 2 bits for 3 unique commands. + switch ((Bits >> 52) & 3) { + default: CS_ASSERT_RET(0 && "Invalid command number."); + case 0: + // EE_FFT_AMS_S16_LD_INCP_P, EE_FFT_AMS_S16_LD_INCP_UAUP_P, EE_FFT_AMS_S1... + printImm8_AsmOperand(MI, 6, O); + break; + case 1: + // EE_FFT_CMUL_S16_LD_XP_P + printSelect_8_AsmOperand(MI, 6, O); + return; + break; + case 2: + // EE_FFT_AMS_S16_LD_INCP, EE_FFT_AMS_S16_LD_INCP_UAUP, EE_FFT_AMS_S16_LD... + printOperand(MI, 7, O); + SStream_concat0(O, ", "); + printSelect_2_AsmOperand(MI, 8, O); + return; + break; + } + + + // Fragment 13 encoded into 1 bits for 2 unique commands. + if ((Bits >> 54) & 1) { + // EE_VMULAS_S16_ACCX_LD_XP_QUP_P, EE_VMULAS_S16_QACC_LD_XP_QUP_P, EE_VMU... + return; + } else { + // EE_FFT_AMS_S16_LD_INCP_P, EE_FFT_AMS_S16_LD_INCP_UAUP_P, EE_FFT_AMS_S1... + SStream_concat0(O, ", "); + printSelect_2_AsmOperand(MI, 7, O); return; } @@ -1021,34 +8570,190 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { /// for the specified register. static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET - assert(RegNo && RegNo < 18 && "Invalid register number!"); + CS_ASSERT_RET_VAL(RegNo && RegNo < 170 && "Invalid register number!", NULL); static const char AsmStrs[] = { /* 0 */ "a10\0" - /* 4 */ "a0\0" - /* 7 */ "a11\0" - /* 11 */ "a1\0" - /* 14 */ "a12\0" - /* 18 */ "a2\0" - /* 21 */ "a13\0" - /* 25 */ "a3\0" - /* 28 */ "a14\0" - /* 32 */ "a4\0" - /* 35 */ "a15\0" - /* 39 */ "a5\0" - /* 42 */ "a6\0" - /* 45 */ "a7\0" - /* 48 */ "a8\0" - /* 51 */ "a9\0" - /* 54 */ "sar\0" + /* 4 */ "b10\0" + /* 8 */ "aed10\0" + /* 14 */ "f10\0" + /* 18 */ "dbreaka0\0" + /* 27 */ "ibreaka0\0" + /* 36 */ "b0\0" + /* 39 */ "dbreakc0\0" + /* 48 */ "misc0\0" + /* 54 */ "aed0\0" + /* 59 */ "configid0\0" + /* 69 */ "ccompare0\0" + /* 79 */ "f0\0" + /* 82 */ "m0\0" + /* 85 */ "q0\0" + /* 88 */ "u0\0" + /* 91 */ "B8_B9_B10_B11\0" + /* 105 */ "a11\0" + /* 109 */ "b11\0" + /* 113 */ "aed11\0" + /* 119 */ "f11\0" + /* 123 */ "B0_B1\0" + /* 129 */ "dbreaka1\0" + /* 138 */ "ibreaka1\0" + /* 147 */ "b1\0" + /* 150 */ "dbreakc1\0" + /* 159 */ "epc1\0" + /* 164 */ "misc1\0" + /* 170 */ "aed1\0" + /* 175 */ "configid1\0" + /* 185 */ "ccompare1\0" + /* 195 */ "scompare1\0" + /* 205 */ "excsave1\0" + /* 214 */ "f1\0" + /* 217 */ "m1\0" + /* 220 */ "q1\0" + /* 223 */ "u1\0" + /* 226 */ "a12\0" + /* 230 */ "b12\0" + /* 234 */ "aed12\0" + /* 240 */ "f12\0" + /* 244 */ "a2\0" + /* 247 */ "b2\0" + /* 250 */ "epc2\0" + /* 255 */ "misc2\0" + /* 261 */ "aed2\0" + /* 266 */ "ccompare2\0" + /* 276 */ "excsave2\0" + /* 285 */ "f2\0" + /* 288 */ "m2\0" + /* 291 */ "q2\0" + /* 294 */ "eps2\0" + /* 299 */ "u2\0" + /* 302 */ "B12_B13\0" + /* 310 */ "a13\0" + /* 314 */ "b13\0" + /* 318 */ "aed13\0" + /* 324 */ "f13\0" + /* 328 */ "B0_B1_B2_B3\0" + /* 340 */ "a3\0" + /* 343 */ "b3\0" + /* 346 */ "epc3\0" + /* 351 */ "misc3\0" + /* 357 */ "aed3\0" + /* 362 */ "excsave3\0" + /* 371 */ "f3\0" + /* 374 */ "m3\0" + /* 377 */ "q3\0" + /* 380 */ "eps3\0" + /* 385 */ "u3\0" + /* 388 */ "a14\0" + /* 392 */ "b14\0" + /* 396 */ "aed14\0" + /* 402 */ "f14\0" + /* 406 */ "a4\0" + /* 409 */ "b4\0" + /* 412 */ "epc4\0" + /* 417 */ "aed4\0" + /* 422 */ "excsave4\0" + /* 431 */ "f4\0" + /* 434 */ "q4\0" + /* 437 */ "eps4\0" + /* 442 */ "B12_B13_B14_B15\0" + /* 458 */ "a15\0" + /* 462 */ "b15\0" + /* 466 */ "aed15\0" + /* 472 */ "f15\0" + /* 476 */ "B4_B5\0" + /* 482 */ "a5\0" + /* 485 */ "b5\0" + /* 488 */ "epc5\0" + /* 493 */ "aed5\0" + /* 498 */ "excsave5\0" + /* 507 */ "f5\0" + /* 510 */ "q5\0" + /* 513 */ "eps5\0" + /* 518 */ "a6\0" + /* 521 */ "b6\0" + /* 524 */ "epc6\0" + /* 529 */ "aed6\0" + /* 534 */ "excsave6\0" + /* 543 */ "f6\0" + /* 546 */ "q6\0" + /* 549 */ "eps6\0" + /* 554 */ "B4_B5_B6_B7\0" + /* 566 */ "a7\0" + /* 569 */ "b7\0" + /* 572 */ "epc7\0" + /* 577 */ "aed7\0" + /* 582 */ "excsave7\0" + /* 591 */ "f7\0" + /* 594 */ "q7\0" + /* 597 */ "eps7\0" + /* 602 */ "a8\0" + /* 605 */ "b8\0" + /* 608 */ "aed8\0" + /* 613 */ "f8\0" + /* 616 */ "B8_B9\0" + /* 622 */ "a9\0" + /* 625 */ "b9\0" + /* 628 */ "aed9\0" + /* 633 */ "f9\0" + /* 636 */ "qacc\0" + /* 641 */ "depc\0" + /* 646 */ "prid\0" + /* 651 */ "lend\0" + /* 656 */ "ibreakenable\0" + /* 669 */ "cpenable\0" + /* 678 */ "intenable\0" + /* 688 */ "vecbase\0" + /* 696 */ "litbase\0" + /* 704 */ "windowbase\0" + /* 715 */ "exccause\0" + /* 724 */ "debugcause\0" + /* 735 */ "ua_state\0" + /* 744 */ "expstate\0" + /* 753 */ "sar_byte\0" + /* 762 */ "lbeg\0" + /* 767 */ "fft_bit_width\0" + /* 781 */ "f64r_hi\0" + /* 789 */ "acchi\0" + /* 795 */ "icountlevel\0" + /* 807 */ "memctl\0" + /* 814 */ "atomctl\0" + /* 822 */ "f64r_lo\0" + /* 830 */ "acclo\0" + /* 836 */ "intclear\0" + /* 845 */ "sar\0" + /* 849 */ "br\0" + /* 852 */ "fcr\0" + /* 856 */ "excvaddr\0" + /* 865 */ "fsr\0" + /* 869 */ "threadptr\0" + /* 879 */ "f64s\0" + /* 884 */ "ps\0" + /* 887 */ "ccount\0" + /* 894 */ "icount\0" + /* 901 */ "lcount\0" + /* 908 */ "interrupt\0" + /* 918 */ "windowstart\0" + /* 930 */ "gpio_out\0" + /* 939 */ "accx\0" }; - static const uint8_t RegAsmOffset[] = { - 54, 11, 4, 18, 25, 32, 39, 42, 45, 48, 51, 0, 7, 14, - 21, 28, 35, + static const uint16_t RegAsmOffset[] = { + 789, 830, 939, 814, 849, 887, 669, 861, 724, 641, 715, 856, 744, 852, + 767, 865, 930, 656, 894, 795, 836, 678, 908, 762, 901, 651, 696, 807, + 646, 884, 636, 845, 753, 135, 869, 735, 688, 704, 918, 24, 244, 340, + 406, 482, 518, 566, 602, 622, 0, 105, 226, 310, 388, 458, 54, 170, + 261, 357, 417, 493, 529, 577, 608, 628, 8, 113, 234, 318, 396, 466, + 36, 147, 247, 343, 409, 485, 521, 569, 605, 625, 4, 109, 230, 314, + 392, 462, 69, 185, 266, 59, 175, 18, 129, 39, 150, 159, 250, 346, + 412, 488, 524, 572, 294, 380, 437, 513, 549, 597, 205, 276, 362, 422, + 498, 534, 582, 79, 214, 285, 371, 431, 507, 543, 591, 613, 633, 14, + 119, 240, 324, 402, 472, 27, 138, 82, 217, 288, 374, 48, 164, 255, + 351, 85, 220, 291, 377, 434, 510, 546, 594, 195, 88, 223, 299, 385, + 781, 822, 879, 123, 334, 476, 560, 616, 97, 302, 450, 328, 554, 91, + 442, }; - assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && - "Invalid alt name index for register!"); + CS_ASSERT_RET_VAL(*(AsmStrs+RegAsmOffset[RegNo-1]) && + "Invalid alt name index for register!", NULL); return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; @@ -1059,8 +8764,370 @@ static const char *getRegisterName(unsigned RegNo) { static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) { #ifndef CAPSTONE_DIET + static const PatternsForOpcode OpToPatterns[] = { + {Xtensa_ADD, 0, 1 }, + {Xtensa_ADDI, 1, 1 }, + {Xtensa_ADDI_N, 2, 1 }, + {Xtensa_ADD_N, 3, 1 }, + {Xtensa_BALL, 4, 1 }, + {Xtensa_BANY, 5, 1 }, + {Xtensa_BBC, 6, 1 }, + {Xtensa_BBS, 7, 1 }, + {Xtensa_BEQ, 8, 1 }, + {Xtensa_BEQI, 9, 1 }, + {Xtensa_BEQZ, 10, 1 }, + {Xtensa_BF, 11, 1 }, + {Xtensa_BGE, 12, 1 }, + {Xtensa_BGEI, 13, 1 }, + {Xtensa_BGEU, 14, 1 }, + {Xtensa_BGEUI, 15, 1 }, + {Xtensa_BGEZ, 16, 1 }, + {Xtensa_BLT, 17, 1 }, + {Xtensa_BLTI, 18, 1 }, + {Xtensa_BLTU, 19, 1 }, + {Xtensa_BLTUI, 20, 1 }, + {Xtensa_BLTZ, 21, 1 }, + {Xtensa_BNALL, 22, 1 }, + {Xtensa_BNE, 23, 1 }, + {Xtensa_BNEI, 24, 1 }, + {Xtensa_BNEZ, 25, 1 }, + {Xtensa_BNONE, 26, 1 }, + {Xtensa_BREAK_N, 27, 1 }, + {Xtensa_BT, 28, 1 }, + {Xtensa_LOOP, 29, 1 }, + {Xtensa_LOOPGTZ, 30, 1 }, + {Xtensa_LOOPNEZ, 31, 1 }, + {Xtensa_MOVI_N, 32, 1 }, + {Xtensa_NOP, 33, 1 }, + {Xtensa_OR, 34, 1 }, + {Xtensa_RET, 35, 1 }, + {Xtensa_RETW, 36, 1 }, + {Xtensa_RETW_N, 37, 1 }, + {Xtensa_RET_N, 38, 1 }, + {0}, }; + + static const AliasPattern Patterns[] = { + // Xtensa_ADD - 0 + {0, 0, 3, 3 }, + // Xtensa_ADDI - 1 + {16, 3, 3, 2 }, + // Xtensa_ADDI_N - 2 + {35, 5, 3, 2 }, + // Xtensa_ADD_N - 3 + {56, 7, 3, 3 }, + // Xtensa_BALL - 4 + {74, 10, 3, 2 }, + // Xtensa_BANY - 5 + {93, 12, 3, 2 }, + // Xtensa_BBC - 6 + {112, 14, 3, 2 }, + // Xtensa_BBS - 7 + {130, 16, 3, 2 }, + // Xtensa_BEQ - 8 + {148, 18, 3, 2 }, + // Xtensa_BEQI - 9 + {166, 20, 3, 2 }, + // Xtensa_BEQZ - 10 + {187, 22, 2, 1 }, + // Xtensa_BF - 11 + {202, 23, 2, 1 }, + // Xtensa_BGE - 12 + {215, 24, 3, 2 }, + // Xtensa_BGEI - 13 + {233, 26, 3, 2 }, + // Xtensa_BGEU - 14 + {254, 28, 3, 2 }, + // Xtensa_BGEUI - 15 + {273, 30, 3, 2 }, + // Xtensa_BGEZ - 16 + {295, 32, 2, 1 }, + // Xtensa_BLT - 17 + {310, 33, 3, 2 }, + // Xtensa_BLTI - 18 + {328, 35, 3, 2 }, + // Xtensa_BLTU - 19 + {349, 37, 3, 2 }, + // Xtensa_BLTUI - 20 + {368, 39, 3, 2 }, + // Xtensa_BLTZ - 21 + {390, 41, 2, 1 }, + // Xtensa_BNALL - 22 + {405, 42, 3, 2 }, + // Xtensa_BNE - 23 + {425, 44, 3, 2 }, + // Xtensa_BNEI - 24 + {443, 46, 3, 2 }, + // Xtensa_BNEZ - 25 + {464, 48, 2, 1 }, + // Xtensa_BNONE - 26 + {479, 49, 3, 2 }, + // Xtensa_BREAK_N - 27 + {499, 51, 1, 0 }, + // Xtensa_BT - 28 + {513, 51, 2, 1 }, + // Xtensa_LOOP - 29 + {526, 52, 2, 1 }, + // Xtensa_LOOPGTZ - 30 + {541, 53, 2, 1 }, + // Xtensa_LOOPNEZ - 31 + {559, 54, 2, 1 }, + // Xtensa_MOVI_N - 32 + {577, 55, 2, 1 }, + // Xtensa_NOP - 33 + {594, 56, 0, 0 }, + // Xtensa_OR - 34 + {599, 56, 3, 3 }, + // Xtensa_RET - 35 + {611, 59, 0, 0 }, + // Xtensa_RETW - 36 + {616, 59, 0, 0 }, + // Xtensa_RETW_N - 37 + {622, 59, 0, 0 }, + // Xtensa_RET_N - 38 + {630, 59, 0, 0 }, + {0}, }; + + static const AliasPatternCond Conds[] = { + // (ADD AR:$r, AR:$s, AR:$t) - 0 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (ADDI AR:$r, AR:$s, imm8:$imm8) - 3 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (ADDI_N AR:$r, AR:$s, imm1n_15:$imm) - 5 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (ADD_N AR:$r, AR:$s, AR:$t) - 7 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BALL AR:$s, AR:$t, brtarget:$target) - 10 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BANY AR:$s, AR:$t, brtarget:$target) - 12 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BBC AR:$s, AR:$t, brtarget:$target) - 14 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BBS AR:$s, AR:$t, brtarget:$target) - 16 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BEQ AR:$s, AR:$t, brtarget:$target) - 18 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BEQI AR:$s, b4const:$imm, brtarget:$target) - 20 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + // (BEQZ AR:$s, brtarget:$target) - 22 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BF BR:$b, brtarget:$target) - 23 + {AliasPatternCond_K_RegClass, Xtensa_BRRegClassID}, + // (BGE AR:$s, AR:$t, brtarget:$target) - 24 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BGEI AR:$s, b4const:$imm, brtarget:$target) - 26 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + // (BGEU AR:$s, AR:$t, brtarget:$target) - 28 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BGEUI AR:$s, b4constu:$imm, brtarget:$target) - 30 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + // (BGEZ AR:$s, brtarget:$target) - 32 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BLT AR:$s, AR:$t, brtarget:$target) - 33 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BLTI AR:$s, b4const:$imm, brtarget:$target) - 35 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + // (BLTU AR:$s, AR:$t, brtarget:$target) - 37 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BLTUI AR:$s, b4constu:$imm, brtarget:$target) - 39 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + // (BLTZ AR:$s, brtarget:$target) - 41 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BNALL AR:$s, AR:$t, brtarget:$target) - 42 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BNE AR:$s, AR:$t, brtarget:$target) - 44 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BNEI AR:$s, b4const:$imm, brtarget:$target) - 46 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + // (BNEZ AR:$s, brtarget:$target) - 48 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BNONE AR:$s, AR:$t, brtarget:$target) - 49 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (BREAK_N uimm4:$imm) - 51 + // (BT BR:$b, brtarget:$target) - 51 + {AliasPatternCond_K_RegClass, Xtensa_BRRegClassID}, + // (LOOP AR:$s, ltarget:$target) - 52 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (LOOPGTZ AR:$s, ltarget:$target) - 53 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (LOOPNEZ AR:$s, ltarget:$target) - 54 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (MOVI_N AR:$s, imm32n_95:$imm7) - 55 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + // (NOP) - 56 + // (OR AR:$t, AR:$s, AR:$s) - 56 + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_RegClass, Xtensa_ARRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (RET) - 59 + // (RETW) - 59 + // (RETW_N) - 59 + // (RET_N) - 59 + {0}, }; + + static const char AsmStrings[] = + /* 0 */ "_add $\x01, $\x02, $\x03\0" + /* 16 */ "_addi $\x01, $\x02, $\xFF\x03\x01\0" + /* 35 */ "_addi.n $\x01, $\x02, $\xFF\x03\x02\0" + /* 56 */ "_add.n $\x01, $\x02, $\x03\0" + /* 74 */ "_ball $\x01, $\x02, $\xFF\x03\x03\0" + /* 93 */ "_bany $\x01, $\x02, $\xFF\x03\x03\0" + /* 112 */ "_bbc $\x01, $\x02, $\xFF\x03\x03\0" + /* 130 */ "_bbs $\x01, $\x02, $\xFF\x03\x03\0" + /* 148 */ "_beq $\x01, $\x02, $\xFF\x03\x03\0" + /* 166 */ "_beqi $\x01, $\xFF\x02\x05, $\xFF\x03\x03\0" + /* 187 */ "_beqz $\x01, $\xFF\x02\x03\0" + /* 202 */ "_BF $\x01, $\xFF\x02\x03\0" + /* 215 */ "_bge $\x01, $\x02, $\xFF\x03\x03\0" + /* 233 */ "_bgei $\x01, $\xFF\x02\x05, $\xFF\x03\x03\0" + /* 254 */ "_bgeu $\x01, $\x02, $\xFF\x03\x03\0" + /* 273 */ "_bgeui $\x01, $\xFF\x02\x06, $\xFF\x03\x03\0" + /* 295 */ "_bgez $\x01, $\xFF\x02\x03\0" + /* 310 */ "_blt $\x01, $\x02, $\xFF\x03\x03\0" + /* 328 */ "_blti $\x01, $\xFF\x02\x05, $\xFF\x03\x03\0" + /* 349 */ "_bltu $\x01, $\x02, $\xFF\x03\x03\0" + /* 368 */ "_bltui $\x01, $\xFF\x02\x06, $\xFF\x03\x03\0" + /* 390 */ "_bltz $\x01, $\xFF\x02\x03\0" + /* 405 */ "_bnall $\x01, $\x02, $\xFF\x03\x03\0" + /* 425 */ "_bne $\x01, $\x02, $\xFF\x03\x03\0" + /* 443 */ "_bnei $\x01, $\xFF\x02\x05, $\xFF\x03\x03\0" + /* 464 */ "_bnez $\x01, $\xFF\x02\x03\0" + /* 479 */ "_bnone $\x01, $\x02, $\xFF\x03\x03\0" + /* 499 */ "_break.n $\xFF\x01\x07\0" + /* 513 */ "_BT $\x01, $\xFF\x02\x03\0" + /* 526 */ "_loop $\x01, $\xFF\x02\x08\0" + /* 541 */ "_loopgtz $\x01, $\xFF\x02\x08\0" + /* 559 */ "_loopnez $\x01, $\xFF\x02\x08\0" + /* 577 */ "_movi.n $\x01, $\xFF\x02\x09\0" + /* 594 */ "_nop\0" + /* 599 */ "mov $\x01, $\x02\0" + /* 611 */ "_ret\0" + /* 616 */ "_retw\0" + /* 622 */ "_retw.n\0" + /* 630 */ "_ret.n\0" + ; + +#ifndef NDEBUG + //static struct SortCheck { + // SortCheck(ArrayRef OpToPatterns) { + // assert(std::is_sorted( + // OpToPatterns.begin(), OpToPatterns.end(), + // [](const PatternsForOpcode &L, const //PatternsForOpcode &R) { + // return L.Opcode < R.Opcode; + // }) && + // "tablegen failed to sort opcode patterns"); + // } + //} sortCheckVar(OpToPatterns); +#endif + + AliasMatchingData M = { + OpToPatterns, + Patterns, + Conds, + AsmStrings, + NULL, + }; + const char *AsmString = matchAliasPatterns(MI, &M); + if (!AsmString) return false; + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + SStream_concat1(OS, '\t'); + char *substr = malloc(I+1); + memcpy(substr, AsmString, I); + substr[I] = '\0'; + SStream_concat0(OS, substr); + free(substr); + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat1(OS, '\t'); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, AsmString[I++]); + } + } while (AsmString[I] != '\0'); + } + + return true; +#else return false; #endif // CAPSTONE_DIET } +static void printCustomAliasOperand( + MCInst *MI, uint64_t Address, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS) { +#ifndef CAPSTONE_DIET + switch (PrintMethodIdx) { + default: + CS_ASSERT_RET(0 && "Unknown PrintMethod kind"); + break; + case 0: + printImm8_AsmOperand(MI, OpIdx, OS); + break; + case 1: + printImm1n_15_AsmOperand(MI, OpIdx, OS); + break; + case 2: + printBranchTarget(MI, OpIdx, OS); + break; + case 3: + printUimm5_AsmOperand(MI, OpIdx, OS); + break; + case 4: + printB4const_AsmOperand(MI, OpIdx, OS); + break; + case 5: + printB4constu_AsmOperand(MI, OpIdx, OS); + break; + case 6: + printUimm4_AsmOperand(MI, OpIdx, OS); + break; + case 7: + printLoopTarget(MI, OpIdx, OS); + break; + case 8: + printImm32n_95_AsmOperand(MI, OpIdx, OS); + break; + } +#endif // CAPSTONE_DIET +} + #endif // PRINT_ALIAS_INSTR diff --git a/arch/Xtensa/XtensaGenCSFeatureName.inc b/arch/Xtensa/XtensaGenCSFeatureName.inc index 6302541aa2..5dbb11bbfd 100644 --- a/arch/Xtensa/XtensaGenCSFeatureName.inc +++ b/arch/Xtensa/XtensaGenCSFeatureName.inc @@ -12,3 +12,36 @@ /* https://github.com/capstone-engine/llvm-capstone */ { XTENSA_FEATURE_HASDENSITY, "HasDensity" }, +{ XTENSA_FEATURE_HASSINGLEFLOAT, "HasSingleFloat" }, +{ XTENSA_FEATURE_HASWINDOWED, "HasWindowed" }, +{ XTENSA_FEATURE_HASBOOLEAN, "HasBoolean" }, +{ XTENSA_FEATURE_HASLOOP, "HasLoop" }, +{ XTENSA_FEATURE_HASSEXT, "HasSEXT" }, +{ XTENSA_FEATURE_HASCLAMPS, "HasCLAMPS" }, +{ XTENSA_FEATURE_HASNSA, "HasNSA" }, +{ XTENSA_FEATURE_HASMINMAX, "HasMINMAX" }, +{ XTENSA_FEATURE_HASMUL16, "HasMul16" }, +{ XTENSA_FEATURE_HASMUL32, "HasMul32" }, +{ XTENSA_FEATURE_HASMUL32HIGH, "HasMul32High" }, +{ XTENSA_FEATURE_HASDIV32, "HasDiv32" }, +{ XTENSA_FEATURE_HASMAC16, "HasMAC16" }, +{ XTENSA_FEATURE_HASDFPACCEL, "HasDFPAccel" }, +{ XTENSA_FEATURE_HASS32C1I, "HasS32C1I" }, +{ XTENSA_FEATURE_HASTHREADPTR, "HasTHREADPTR" }, +{ XTENSA_FEATURE_HASEXTENDEDL32R, "HasExtendedL32R" }, +{ XTENSA_FEATURE_HASATOMCTL, "HasATOMCTL" }, +{ XTENSA_FEATURE_HASMEMCTL, "HasMEMCTL" }, +{ XTENSA_FEATURE_HASDEBUG, "HasDebug" }, +{ XTENSA_FEATURE_HASEXCEPTION, "HasException" }, +{ XTENSA_FEATURE_HASHIGHPRIINTERRUPTS, "HasHighPriInterrupts" }, +{ XTENSA_FEATURE_HASCOPROCESSOR, "HasCoprocessor" }, +{ XTENSA_FEATURE_HASINTERRUPT, "HasInterrupt" }, +{ XTENSA_FEATURE_HASRELOCATABLEVECTOR, "HasRelocatableVector" }, +{ XTENSA_FEATURE_HASTIMERINT, "HasTimerInt" }, +{ XTENSA_FEATURE_HASPRID, "HasPRID" }, +{ XTENSA_FEATURE_HASREGIONPROTECTION, "HasRegionProtection" }, +{ XTENSA_FEATURE_HASMISCSR, "HasMiscSR" }, +{ XTENSA_FEATURE_HASESP32S2OPS, "HasESP32S2Ops" }, +{ XTENSA_FEATURE_HASESP32S3OPS, "HasESP32S3Ops" }, +{ XTENSA_FEATURE_HASHIFI3, "HasHIFI3" }, +{ XTENSA_FEATURE_HASFORCEDATOMICS, "HasForcedAtomics" }, diff --git a/arch/Xtensa/XtensaGenCSMappingInsn.inc b/arch/Xtensa/XtensaGenCSMappingInsn.inc index 58c8d4b8dd..1fc18b4096 100644 --- a/arch/Xtensa/XtensaGenCSMappingInsn.inc +++ b/arch/Xtensa/XtensaGenCSMappingInsn.inc @@ -1908,635 +1908,13452 @@ { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} #endif }, +{ + /* #ADJCALLSTACKDOWN */ + Xtensa_ADJCALLSTACKDOWN /* 271 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* #ADJCALLSTACKUP */ + Xtensa_ADJCALLSTACKUP /* 272 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_cmp_swap_16_p, $dst, $ptr, $cmp, $swap */ + Xtensa_ATOMIC_CMP_SWAP_16_P /* 273 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_cmp_swap_32_p, $dst, $ptr, $cmp, $swap */ + Xtensa_ATOMIC_CMP_SWAP_32_P /* 274 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_cmp_swap_8_p, $dst, $ptr, $cmp, $swap */ + Xtensa_ATOMIC_CMP_SWAP_8_P /* 275 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_add_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_ADD_16_P /* 276 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_add_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_ADD_32_P /* 277 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_add_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_ADD_8_P /* 278 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_and_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_AND_16_P /* 279 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_and_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_AND_32_P /* 280 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_and_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_AND_8_P /* 281 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_max_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_MAX_16_P /* 282 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_max_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_MAX_32_P /* 283 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_max_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_MAX_8_P /* 284 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_min_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_MIN_16_P /* 285 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_min_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_MIN_32_P /* 286 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_min_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_MIN_8_P /* 287 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_nand_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_NAND_16_P /* 288 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_nand_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_NAND_32_P /* 289 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_nand_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_NAND_8_P /* 290 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_or_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_OR_16_P /* 291 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_or_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_OR_32_P /* 292 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_or_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_OR_8_P /* 293 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_sub_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_SUB_16_P /* 294 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_sub_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_SUB_32_P /* 295 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_sub_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_SUB_8_P /* 296 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_umax_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_UMAX_16_P /* 297 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_umax_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_UMAX_32_P /* 298 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_umax_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_UMAX_8_P /* 299 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_umin_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_UMIN_16_P /* 300 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_umin_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_UMIN_32_P /* 301 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_umin_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_UMIN_8_P /* 302 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_xor_16_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_XOR_16_P /* 303 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_xor_32_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_XOR_32_P /* 304 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_load_xor_8_p, $dst, $ptr, $arg */ + Xtensa_ATOMIC_LOAD_XOR_8_P /* 305 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_swap_16_p, $dst, $ptr, $swap */ + Xtensa_ATOMIC_SWAP_16_P /* 306 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_swap_32_p, $dst, $ptr, $swap */ + Xtensa_ATOMIC_SWAP_32_P /* 307 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !atomic_swap_8_p, $dst, $ptr, $swap */ + Xtensa_ATOMIC_SWAP_8_P /* 308 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !brcc_fp $cond, $lhs, $rhs, $target */ + Xtensa_BRCC_FP /* 309 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !br_jt_p, $s, $jt */ + Xtensa_BR_JT /* 310 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* foo */ + Xtensa_CONSTPOOL_ENTRY /* 311 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_andq_p, $qa, $qx, $qy */ + Xtensa_EE_ANDQ_P /* 312 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_bitrev_p, $qa, $ax */ + Xtensa_EE_BITREV_P /* 313 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_cmul_s16_ld_incp_p, $qu, $as, $qz, $qx, $qy, $sel4 */ + Xtensa_EE_CMUL_S16_LD_INCP_P /* 314 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_cmul_s16_p, $qz, $qx, $qy, $sel4 */ + Xtensa_EE_CMUL_S16_P /* 315 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_cmul_s16_st_incp_p, $qv, $as, $qz, $qx, $qy, $sel4 */ + Xtensa_EE_CMUL_S16_ST_INCP_P /* 316 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_ams_s16_ld_incp_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + Xtensa_EE_FFT_AMS_S16_LD_INCP_P /* 317 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_ams_s16_ld_incp_uaup_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + Xtensa_EE_FFT_AMS_S16_LD_INCP_UAUP_P /* 318 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_ams_s16_ld_r32_decp_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + Xtensa_EE_FFT_AMS_S16_LD_R32_DECP_P /* 319 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_ams_s16_st_incp_p, $qv, $qz1, $as0, $as, $qx, $qy, $qm, $sel2 */ + Xtensa_EE_FFT_AMS_S16_ST_INCP_P /* 320 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_cmul_s16_ld_xp_p, $qu, $as, $ad, $qz, $qx, $qy, $sel8 */ + Xtensa_EE_FFT_CMUL_S16_LD_XP_P /* 321 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_cmul_s16_st_xp_p, $qx, $qy, $qv, $as, $ad, $sel8, $upd4, $sar4 */ + Xtensa_EE_FFT_CMUL_S16_ST_XP_P /* 322 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_r2bf_s16_p, $qa0, $qa1, $qx, $qy, $sel2 */ + Xtensa_EE_FFT_R2BF_S16_P /* 323 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_r2bf_s16_st_incp_p, $qa0, $qx, $qy, $as, $sar4 */ + Xtensa_EE_FFT_R2BF_S16_ST_INCP_P /* 324 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_fft_vst_r32_decp_p, $qv, $as, $sar2 */ + Xtensa_EE_FFT_VST_R32_DECP_P /* 325 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldf_128_ip_p, $fu3, $fu2, $fu1, $fu0, $as, $imm16f */ + Xtensa_EE_LDF_128_IP_P /* 326 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldf_128_xp_p, $fu3, $fu2, $fu1, $fu0, $as, $ad */ + Xtensa_EE_LDF_128_XP_P /* 327 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldf_64_ip_p, $fu1, $fu0, $as, $imm8 */ + Xtensa_EE_LDF_64_IP_P /* 328 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldf_64_xp_p, $fu1, $fu0, $as, $ad */ + Xtensa_EE_LDF_64_XP_P /* 329 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldqa_s16_128_ip_p, $as, $imm16 */ + Xtensa_EE_LDQA_S16_128_IP_P /* 330 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldqa_s16_128_xp_p, $as, $ad */ + Xtensa_EE_LDQA_S16_128_XP_P /* 331 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldqa_s8_128_ip_p, $as, $imm16 */ + Xtensa_EE_LDQA_S8_128_IP_P /* 332 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldqa_s8_128_xp_p, $as, $ad */ + Xtensa_EE_LDQA_S8_128_XP_P /* 333 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldqa_u16_128_ip_p, $as, $imm16 */ + Xtensa_EE_LDQA_U16_128_IP_P /* 334 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldqa_u16_128_xp_p, $as, $ad */ + Xtensa_EE_LDQA_U16_128_XP_P /* 335 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldqa_u8_128_ip_p, $as, $imm16 */ + Xtensa_EE_LDQA_U8_128_IP_P /* 336 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldqa_u8_128_xp_p, $as, $ad */ + Xtensa_EE_LDQA_U8_128_XP_P /* 337 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ldxq_32_p, $qu, $qs, $as, $sel4, $sel8 */ + Xtensa_EE_LDXQ_32_P /* 338 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ld_128_usar_ip_p, $qu, $as, $imm16 */ + Xtensa_EE_LD_128_USAR_IP_P /* 339 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ld_128_usar_xp_p, $qu, $as, $ad */ + Xtensa_EE_LD_128_USAR_XP_P /* 340 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ld_accx_ip_p, $as, $imm8 */ + Xtensa_EE_LD_ACCX_IP_P /* 341 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ld_qacc_h_h_32_ip_p, $as, $imm4 */ + Xtensa_EE_LD_QACC_H_H_32_IP_P /* 342 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ld_qacc_h_l_128_ip_p, $as, $imm16 */ + Xtensa_EE_LD_QACC_H_L_128_IP_P /* 343 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ld_qacc_l_h_32_ip_p, $as, $imm4 */ + Xtensa_EE_LD_QACC_L_H_32_IP_P /* 344 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ld_qacc_l_l_128_ip_p, $as, $imm16 */ + Xtensa_EE_LD_QACC_L_L_128_IP_P /* 345 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_ld_ua_state_ip_p, $as, $imm16 */ + Xtensa_EE_LD_UA_STATE_IP_P /* 346 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_movi_32_a_p, $qs, $au, $sel4 */ + Xtensa_EE_MOVI_32_A_P /* 347 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_movi_32_q_p, $qu, $as, $sel4 */ + Xtensa_EE_MOVI_32_Q_P /* 348 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_mov_s16_qacc_p, $qs */ + Xtensa_EE_MOV_S16_QACC_P /* 349 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_mov_s8_qacc_p, $qs */ + Xtensa_EE_MOV_S8_QACC_P /* 350 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_mov_u16_qacc_p, $qs */ + Xtensa_EE_MOV_U16_QACC_P /* 351 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_mov_u8_qacc_p, $qs */ + Xtensa_EE_MOV_U8_QACC_P /* 352 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_notq_p, $qa, $qx */ + Xtensa_EE_NOTQ_P /* 353 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_orq_p, $qa, $qx, $qy */ + Xtensa_EE_ORQ_P /* 354 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_slci_2q_p, $qs1, $qs0, $sar16 */ + Xtensa_EE_SLCI_2Q_P /* 355 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_slcxxp_2q_p, $qs1, $qs0, $as, $ad */ + Xtensa_EE_SLCXXP_2Q_P /* 356 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_srci_2q_p, $qs1, $qs0, $sar16 */ + Xtensa_EE_SRCI_2Q_P /* 357 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_srcmb_s16_qacc_p, $qu, $as, $sel2 */ + Xtensa_EE_SRCMB_S16_QACC_P /* 358 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_srcmb_s8_qacc_p, $qu, $as, $sel2 */ + Xtensa_EE_SRCMB_S8_QACC_P /* 359 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_srcq_128_st_incp_p, $qs0, $qs1, $as */ + Xtensa_EE_SRCQ_128_ST_INCP_P /* 360 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_srcxxp_2q_p, $qs1, $qs0, $as, $ad */ + Xtensa_EE_SRCXXP_2Q_P /* 361 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_src_q_ld_ip_p, $qu, $as, $imm16, $qs0, $qs1 */ + Xtensa_EE_SRC_Q_LD_IP_P /* 362 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_src_q_ld_xp_p, $qu, $as, $ad, $qs0, $qs1 */ + Xtensa_EE_SRC_Q_LD_XP_P /* 363 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_src_q_p, $qa, $qs0, $qs1 */ + Xtensa_EE_SRC_Q_P /* 364 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_src_q_qup_p, $qa, $qs0, $qs1 */ + Xtensa_EE_SRC_Q_QUP_P /* 365 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_srs_accx_p, $au, $as, $sel2 */ + Xtensa_EE_SRS_ACCX_P /* 366 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_stf_128_ip_p, $fv3, $fv2, $fv1, $fv0, $as, $imm16f */ + Xtensa_EE_STF_128_IP_P /* 367 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_stf_128_xp_p, $fv3, $fv2, $fv1, $fv0, $as, $ad */ + Xtensa_EE_STF_128_XP_P /* 368 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_stf_64_ip_p, $fv1, $fv0, $as, $imm8 */ + Xtensa_EE_STF_64_IP_P /* 369 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_stf_64_xp_p, $fv1, $fv0, $as, $ad */ + Xtensa_EE_STF_64_XP_P /* 370 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_stxq_32_p, $qv, $qs, $as, $sel4, $sel8 */ + Xtensa_EE_STXQ_32_P /* 371 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_st_accx_ip_p, $as, $imm8 */ + Xtensa_EE_ST_ACCX_IP_P /* 372 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_st_qacc_h_h_32_ip_p, $as, $imm4 */ + Xtensa_EE_ST_QACC_H_H_32_IP_P /* 373 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_st_qacc_h_l_128_ip_p, $as, $imm16 */ + Xtensa_EE_ST_QACC_H_L_128_IP_P /* 374 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_st_qacc_l_h_32_ip_p, $as, $imm4 */ + Xtensa_EE_ST_QACC_L_H_32_IP_P /* 375 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_st_qacc_l_l_128_ip_p, $as, $imm16 */ + Xtensa_EE_ST_QACC_L_L_128_IP_P /* 376 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_st_ua_state_ip_p, $as, $imm16 */ + Xtensa_EE_ST_UA_STATE_IP_P /* 377 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S16_LD_INCP_P /* 378 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s16_p, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S16_P /* 379 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s16_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S16_ST_INCP_P /* 380 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S32_LD_INCP_P /* 381 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s32_p, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S32_P /* 382 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s32_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S32_ST_INCP_P /* 383 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S8_LD_INCP_P /* 384 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s8_p, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S8_P /* 385 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vadds_s8_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S8_ST_INCP_P /* 386 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_eq_s16_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_EQ_S16_P /* 387 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_eq_s32_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_EQ_S32_P /* 388 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_eq_s8_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_EQ_S8_P /* 389 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_gt_s16_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_GT_S16_P /* 390 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_gt_s32_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_GT_S32_P /* 391 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_gt_s8_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_GT_S8_P /* 392 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_lt_s16_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_LT_S16_P /* 393 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_lt_s32_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_LT_S32_P /* 394 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vcmp_lt_s8_p, $qa, $qx, $qy */ + Xtensa_EE_VCMP_LT_S8_P /* 395 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_16_ip_p, $qu, $as, $imm2 */ + Xtensa_EE_VLDBC_16_IP_P /* 396 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_16_p, $qu, $as */ + Xtensa_EE_VLDBC_16_P /* 397 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_16_xp_p, $qu, $as, $ad */ + Xtensa_EE_VLDBC_16_XP_P /* 398 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_32_ip_p, $qu, $as, $imm4 */ + Xtensa_EE_VLDBC_32_IP_P /* 399 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_32_p, $qu, $as */ + Xtensa_EE_VLDBC_32_P /* 400 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_32_xp_p, $qu, $as, $ad */ + Xtensa_EE_VLDBC_32_XP_P /* 401 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_8_ip_p, $qu, $as, $imm1 */ + Xtensa_EE_VLDBC_8_IP_P /* 402 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_8_p, $qu, $as */ + Xtensa_EE_VLDBC_8_P /* 403 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldbc_8_xp_p, $qu, $as, $ad */ + Xtensa_EE_VLDBC_8_XP_P /* 404 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vldhbc_16_incp_p, $qu, $qu1, $as */ + Xtensa_EE_VLDHBC_16_INCP_P /* 405 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vld_128_ip_p, $qu, $as, $imm16 */ + Xtensa_EE_VLD_128_IP_P /* 406 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vld_128_xp_p, $qu, $as, $ad */ + Xtensa_EE_VLD_128_XP_P /* 407 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vld_h_64_ip_p, $qu, $as, $imm8 */ + Xtensa_EE_VLD_H_64_IP_P /* 408 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vld_h_64_xp_p, $qu, $as, $ad */ + Xtensa_EE_VLD_H_64_XP_P /* 409 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vld_l_64_ip_p, $qu, $as, $imm8 */ + Xtensa_EE_VLD_L_64_IP_P /* 410 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vld_l_64_xp_p, $qu, $as, $ad */ + Xtensa_EE_VLD_L_64_XP_P /* 411 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S16_LD_INCP_P /* 412 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s16_p, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S16_P /* 413 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s16_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S16_ST_INCP_P /* 414 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S32_LD_INCP_P /* 415 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s32_p, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S32_P /* 416 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s32_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S32_ST_INCP_P /* 417 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S8_LD_INCP_P /* 418 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s8_p, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S8_P /* 419 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmax_s8_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S8_ST_INCP_P /* 420 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S16_LD_INCP_P /* 421 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s16_p, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S16_P /* 422 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s16_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S16_ST_INCP_P /* 423 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S32_LD_INCP_P /* 424 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s32_p, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S32_P /* 425 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s32_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S32_ST_INCP_P /* 426 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S8_LD_INCP_P /* 427 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s8_p, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S8_P /* 428 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmin_s8_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S8_ST_INCP_P /* 429 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_S16_ACCX_LD_IP_P /* 430 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_ACCX_LD_IP_QUP_P /* 431 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_S16_ACCX_LD_XP_P /* 432 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_ACCX_LD_XP_QUP_P /* 433 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_accx_p, $qx, $qy */ + Xtensa_EE_VMULAS_S16_ACCX_P /* 434 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_qacc_ldbc_incp_p, $qu, $as, $qx, $qy */ + Xtensa_EE_VMULAS_S16_QACC_LDBC_INCP_P /* 435 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P /* 436 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_S16_QACC_LD_IP_P /* 437 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_QACC_LD_IP_QUP_P /* 438 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_S16_QACC_LD_XP_P /* 439 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_QACC_LD_XP_QUP_P /* 440 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s16_qacc_p, $qx, $qy */ + Xtensa_EE_VMULAS_S16_QACC_P /* 441 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_S8_ACCX_LD_IP_P /* 442 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_ACCX_LD_IP_QUP_P /* 443 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_S8_ACCX_LD_XP_P /* 444 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_ACCX_LD_XP_QUP_P /* 445 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_accx_p, $qx, $qy */ + Xtensa_EE_VMULAS_S8_ACCX_P /* 446 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_qacc_ldbc_incp_p, $qu, $as, $qx, $qy */ + Xtensa_EE_VMULAS_S8_QACC_LDBC_INCP_P /* 447 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P /* 448 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_S8_QACC_LD_IP_P /* 449 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_QACC_LD_IP_QUP_P /* 450 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_S8_QACC_LD_XP_P /* 451 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_QACC_LD_XP_QUP_P /* 452 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_s8_qacc_p, $qx, $qy */ + Xtensa_EE_VMULAS_S8_QACC_P /* 453 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_U16_ACCX_LD_IP_P /* 454 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_ACCX_LD_IP_QUP_P /* 455 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_U16_ACCX_LD_XP_P /* 456 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_ACCX_LD_XP_QUP_P /* 457 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_accx_p, $qx, $qy */ + Xtensa_EE_VMULAS_U16_ACCX_P /* 458 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_qacc_ldbc_incp_p, $qu, $as, $qx, $qy */ + Xtensa_EE_VMULAS_U16_QACC_LDBC_INCP_P /* 459 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P /* 460 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_U16_QACC_LD_IP_P /* 461 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_QACC_LD_IP_QUP_P /* 462 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_U16_QACC_LD_XP_P /* 463 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_QACC_LD_XP_QUP_P /* 464 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u16_qacc_p, $qx, $qy */ + Xtensa_EE_VMULAS_U16_QACC_P /* 465 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_U8_ACCX_LD_IP_P /* 466 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_ACCX_LD_IP_QUP_P /* 467 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_U8_ACCX_LD_XP_P /* 468 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_ACCX_LD_XP_QUP_P /* 469 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_accx_p, $qx, $qy */ + Xtensa_EE_VMULAS_U8_ACCX_P /* 470 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_qacc_ldbc_incp_p, $qu, $as, $qx, $qy */ + Xtensa_EE_VMULAS_U8_QACC_LDBC_INCP_P /* 471 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P /* 472 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_U8_QACC_LD_IP_P /* 473 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_QACC_LD_IP_QUP_P /* 474 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_U8_QACC_LD_XP_P /* 475 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_QACC_LD_XP_QUP_P /* 476 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmulas_u8_qacc_p, $qx, $qy */ + Xtensa_EE_VMULAS_U8_QACC_P /* 477 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_s16_ld_incp_p, $qu, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S16_LD_INCP_P /* 478 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_s16_p, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S16_P /* 479 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_s16_st_incp_p, $qv, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S16_ST_INCP_P /* 480 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_s8_ld_incp_p, $qu, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S8_LD_INCP_P /* 481 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_s8_p, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S8_P /* 482 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_s8_st_incp_p, $qv, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S8_ST_INCP_P /* 483 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_u16_ld_incp_p, $qu, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U16_LD_INCP_P /* 484 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_u16_p, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U16_P /* 485 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_u16_st_incp_p, $qv, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U16_ST_INCP_P /* 486 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_u8_ld_incp_p, $qu, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U8_LD_INCP_P /* 487 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_u8_p, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U8_P /* 488 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vmul_u8_st_incp_p, $qv, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U8_ST_INCP_P /* 489 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vprelu_s16_p, $qz, $qx, $qy, $ay */ + Xtensa_EE_VPRELU_S16_P /* 490 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vprelu_s8_p, $qz, $qx, $qy, $ay */ + Xtensa_EE_VPRELU_S8_P /* 491 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vrelu_s16_p, $qs, $ax, $ay */ + Xtensa_EE_VRELU_S16_P /* 492 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vrelu_s8_p, $qs, $ax, $ay */ + Xtensa_EE_VRELU_S8_P /* 493 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsl_32_p, $qa, $qs */ + Xtensa_EE_VSL_32_P /* 494 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsmulas_s16_qacc_ld_incp_p, $qu, $as, $qx, $qy, $sel8 */ + Xtensa_EE_VSMULAS_S16_QACC_LD_INCP_P /* 495 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsmulas_s16_qacc_p, $qx, $qy, $sel8 */ + Xtensa_EE_VSMULAS_S16_QACC_P /* 496 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsmulas_s8_qacc_ld_incp_p, $qu, $as, $qx, $qy, $sel16 */ + Xtensa_EE_VSMULAS_S8_QACC_LD_INCP_P /* 497 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsmulas_s8_qacc_p, $qx, $qy, $sel16 */ + Xtensa_EE_VSMULAS_S8_QACC_P /* 498 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsr_32_p, $qa, $qs */ + Xtensa_EE_VSR_32_P /* 499 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vst_128_ip_p, $qv, $as, $imm16 */ + Xtensa_EE_VST_128_IP_P /* 500 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vst_128_xp_p, $qv, $as, $ad */ + Xtensa_EE_VST_128_XP_P /* 501 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vst_h_64_ip_p, $qv, $as, $imm8 */ + Xtensa_EE_VST_H_64_IP_P /* 502 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vst_h_64_xp_p, $qv, $as, $ad */ + Xtensa_EE_VST_H_64_XP_P /* 503 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vst_l_64_ip_p, $qv, $as, $imm8 */ + Xtensa_EE_VST_L_64_IP_P /* 504 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vst_l_64_xp_p, $qv, $as, $ad */ + Xtensa_EE_VST_L_64_XP_P /* 505 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S16_LD_INCP_P /* 506 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s16_p, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S16_P /* 507 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s16_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S16_ST_INCP_P /* 508 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S32_LD_INCP_P /* 509 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s32_p, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S32_P /* 510 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s32_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S32_ST_INCP_P /* 511 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S8_LD_INCP_P /* 512 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s8_p, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S8_P /* 513 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vsubs_s8_st_incp_p, $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S8_ST_INCP_P /* 514 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vunzip_16_p, $qs0, $qs1 */ + Xtensa_EE_VUNZIP_16_P /* 515 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vunzip_32_p, $qs0, $qs1 */ + Xtensa_EE_VUNZIP_32_P /* 516 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vunzip_8_p, $qs0, $qs1 */ + Xtensa_EE_VUNZIP_8_P /* 517 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vzip_16_p, $qs0, $qs1 */ + Xtensa_EE_VZIP_16_P /* 518 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vzip_32_p, $qs0, $qs1 */ + Xtensa_EE_VZIP_32_P /* 519 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_vzip_8_p, $qs0, $qs1 */ + Xtensa_EE_VZIP_8_P /* 520 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_xorq_p, $qa, $qx, $qy */ + Xtensa_EE_XORQ_P /* 521 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_zero_accx_p */ + Xtensa_EE_ZERO_ACCX_P /* 522 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_zero_qacc_p */ + Xtensa_EE_ZERO_QACC_P /* 523 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ee_zero_q_p, $qa */ + Xtensa_EE_ZERO_Q_P /* 524 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !extui_br2 $r, $s, $b */ + Xtensa_EXTUI_BR2_P /* 525 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !extui_br4 $r, $s, $b */ + Xtensa_EXTUI_BR4_P /* 526 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !extui_br $r, $s, $b */ + Xtensa_EXTUI_BR_P /* 527 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !L8I_P $t, $addr */ + Xtensa_L8I_P /* 528 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_lddec_p, $mw, $s */ + Xtensa_LDDEC_P /* 529 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_ldinc_p, $mw, $s */ + Xtensa_LDINC_P /* 530 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !loopbr $elts, $target */ + Xtensa_LOOPBR /* 531 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !loopdec $eltsout, $eltsin */ + Xtensa_LOOPDEC /* 532 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !loopend $target */ + Xtensa_LOOPEND /* 533 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !loopinit $elts, $eltsin */ + Xtensa_LOOPINIT /* 534 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !loopstart $s, $target */ + Xtensa_LOOPSTART /* 535 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !movba2 $r, $s */ + Xtensa_MOVBA2_P /* 536 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !movba $r, $x, $y, $s */ + Xtensa_MOVBA2_P2 /* 537 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !movba4 $r, $s */ + Xtensa_MOVBA4_P /* 538 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !movba4 $r, $x, $y, $s */ + Xtensa_MOVBA4_P2 /* 539 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !movba $r, $s */ + Xtensa_MOVBA_P /* 540 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !movba $r, $x, $y, $s */ + Xtensa_MOVBA_P2 /* 541 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_da_hh_lddec_p, $mw, $s, $mx, $t */ + Xtensa_MULA_DA_HH_LDDEC_P /* 542 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_da_hh_ldinc_p, $mw, $s, $mx, $t */ + Xtensa_MULA_DA_HH_LDINC_P /* 543 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_da_hl_lddec_p, $mw, $s, $mx, $t */ + Xtensa_MULA_DA_HL_LDDEC_P /* 544 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_da_hl_ldinc_p, $mw, $s, $mx, $t */ + Xtensa_MULA_DA_HL_LDINC_P /* 545 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_da_lh_lddec_p, $mw, $s, $mx, $t */ + Xtensa_MULA_DA_LH_LDDEC_P /* 546 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_da_lh_ldinc_p, $mw, $s, $mx, $t */ + Xtensa_MULA_DA_LH_LDINC_P /* 547 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_da_ll_lddec_p, $mw, $s, $mx, $t */ + Xtensa_MULA_DA_LL_LDDEC_P /* 548 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_da_ll_ldinc_p, $mw, $s, $mx, $t */ + Xtensa_MULA_DA_LL_LDINC_P /* 549 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_dd_hh_lddec_p, $mw, $s, $mx, $my */ + Xtensa_MULA_DD_HH_LDDEC_P /* 550 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_dd_hh_ldinc_p, $mw, $s, $mx, $my */ + Xtensa_MULA_DD_HH_LDINC_P /* 551 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_dd_hl_lddec_p, $mw, $s, $mx, $my */ + Xtensa_MULA_DD_HL_LDDEC_P /* 552 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_dd_hl_ldinc_p, $mw, $s, $mx, $my */ + Xtensa_MULA_DD_HL_LDINC_P /* 553 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_dd_lh_lddec_p, $mw, $s, $mx, $my */ + Xtensa_MULA_DD_LH_LDDEC_P /* 554 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_dd_lh_ldinc_p, $mw, $s, $mx, $my */ + Xtensa_MULA_DD_LH_LDINC_P /* 555 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_dd_ll_lddec_p, $mw, $s, $mx, $my */ + Xtensa_MULA_DD_LL_LDDEC_P /* 556 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mula_dd_ll_ldinc_p, $mw, $s, $mx, $my */ + Xtensa_MULA_DD_LL_LDINC_P /* 557 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !restore_bool $out, $mem */ + Xtensa_RESTORE_BOOL /* 558 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !select $dst, $lhs, $rhs, $t, $f, $cond */ + Xtensa_SELECT /* 559 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !select_cc_fp_fp $dst, $lhs, $rhs, $t, $f, $cond */ + Xtensa_SELECT_CC_FP_FP /* 560 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !select_cc_fp_int $dst, $lhs, $rhs, $t, $f, $cond */ + Xtensa_SELECT_CC_FP_INT /* 561 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !select_cc_int_fp $dst, $lhs, $rhs, $t, $f, $cond */ + Xtensa_SELECT_CC_INT_FP /* 562 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !slli_br $r, $s, $b */ + Xtensa_SLLI_BR_P /* 563 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # SLL_P $r, $s, $sa */ + Xtensa_SLL_P /* 564 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !spill_bool $b, $mem */ + Xtensa_SPILL_BOOL /* 565 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # SRA_P $r, $t, $sa */ + Xtensa_SRA_P /* 566 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # SRL_P $r, $t, $sa */ + Xtensa_SRL_P /* 567 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_wsr_acchi_p, $s */ + Xtensa_WSR_ACCHI_P /* 568 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_wsr_acclo_p, $s */ + Xtensa_WSR_ACCLO_P /* 569 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_wsr_m0_p, $s */ + Xtensa_WSR_M0_P /* 570 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_wsr_m1_p, $s */ + Xtensa_WSR_M1_P /* 571 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_wsr_m2_p, $s */ + Xtensa_WSR_M2_P /* 572 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_wsr_m3_p, $s */ + Xtensa_WSR_M3_P /* 573 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_xsr_acchi_p, $s */ + Xtensa_XSR_ACCHI_P /* 574 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_xsr_acclo_p, $s */ + Xtensa_XSR_ACCLO_P /* 575 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_xsr_m0_p, $s */ + Xtensa_XSR_M0_P /* 576 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_xsr_m1_p, $s */ + Xtensa_XSR_M1_P /* 577 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_xsr_m2_p, $s */ + Xtensa_XSR_M2_P /* 578 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_xsr_m3_p, $s */ + Xtensa_XSR_M3_P /* 579 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* !xtensa_mv_qr_p, $a, $b */ + Xtensa_mv_QR_P /* 580 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, { /* abs $r, $t */ - Xtensa_ABS /* 271 */, XTENSA_INS_ABS, + Xtensa_ABS /* 581 */, XTENSA_INS_ABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* abs.s $r, $s */ + Xtensa_ABS_S /* 582 */, XTENSA_INS_ABS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* add $r, $s, $t */ + Xtensa_ADD /* 583 */, XTENSA_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* addexpm.s $r, $s */ + Xtensa_ADDEXPM_S /* 584 */, XTENSA_INS_ADDEXPM_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* addexp.s $r, $s */ + Xtensa_ADDEXP_S /* 585 */, XTENSA_INS_ADDEXP_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* addi $t, $s, $imm8 */ + Xtensa_ADDI /* 586 */, XTENSA_INS_ADDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* addi.n $r, $s, $imm */ + Xtensa_ADDI_N /* 587 */, XTENSA_INS_ADDI_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* addmi $t, $s, $imm_sh8 */ + Xtensa_ADDMI /* 588 */, XTENSA_INS_ADDMI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* addx2 $r, $s, $t */ + Xtensa_ADDX2 /* 589 */, XTENSA_INS_ADDX2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* addx4 $r, $s, $t */ + Xtensa_ADDX4 /* 590 */, XTENSA_INS_ADDX4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* addx8 $r, $s, $t */ + Xtensa_ADDX8 /* 591 */, XTENSA_INS_ADDX8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* add.n $r, $s, $t */ + Xtensa_ADD_N /* 592 */, XTENSA_INS_ADD_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* add.s $r, $s, $t */ + Xtensa_ADD_S /* 593 */, XTENSA_INS_ADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ae_abs16s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_ABS16S /* 594 */, XTENSA_INS_AE_ABS16S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_abs24s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_ABS24S /* 595 */, XTENSA_INS_AE_ABS24S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_abs32 $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_ABS32 /* 596 */, XTENSA_INS_AE_ABS32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_abs32s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_ABS32S /* 597 */, XTENSA_INS_AE_ABS32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_abs64 $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_ABS64 /* 598 */, XTENSA_INS_AE_ABS64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_abs64s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_ABS64S /* 599 */, XTENSA_INS_AE_ABS64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_add16 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADD16 /* 600 */, XTENSA_INS_AE_ADD16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_add16s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADD16S /* 601 */, XTENSA_INS_AE_ADD16S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_add24s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADD24S /* 602 */, XTENSA_INS_AE_ADD24S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_add32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADD32 /* 603 */, XTENSA_INS_AE_ADD32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_add32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADD32S /* 604 */, XTENSA_INS_AE_ADD32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_add32_hl_lh $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADD32_HL_LH /* 605 */, XTENSA_INS_AE_ADD32_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_add64 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADD64 /* 606 */, XTENSA_INS_AE_ADD64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_add64s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADD64S /* 607 */, XTENSA_INS_AE_ADD64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_addbrba32 $arr, $art, $ars */ + Xtensa_AE_ADDBRBA32 /* 608 */, XTENSA_INS_AE_ADDBRBA32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_addsub32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADDSUB32 /* 609 */, XTENSA_INS_AE_ADDSUB32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_addsub32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ADDSUB32S /* 610 */, XTENSA_INS_AE_ADDSUB32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_and $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1 */ + Xtensa_AE_AND /* 611 */, XTENSA_INS_AE_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_cvt32x2f16.10 $ae_to_dr_v, $ae_to_dr_v0 */ + Xtensa_AE_CVT32X2F16_10 /* 612 */, XTENSA_INS_AE_CVT32X2F16_10, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_cvt32x2f16.32 $ae_to_dr_v, $ae_to_dr_v0 */ + Xtensa_AE_CVT32X2F16_32 /* 613 */, XTENSA_INS_AE_CVT32X2F16_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_cvt48a32 $ae_ar_to_dr_v, $ars */ + Xtensa_AE_CVT48A32 /* 614 */, XTENSA_INS_AE_CVT48A32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_cvt64a32 $ae_ar_to_dr_v, $ars */ + Xtensa_AE_CVT64A32 /* 615 */, XTENSA_INS_AE_CVT64A32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_cvt64f32.h $ae_dr_to_dr_v, $ae_dr_to_dr_v0 */ + Xtensa_AE_CVT64F32_H /* 616 */, XTENSA_INS_AE_CVT64F32_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_cvta32f24s.h $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_CVTA32F24S_H /* 617 */, XTENSA_INS_AE_CVTA32F24S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_cvta32f24s.l $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_CVTA32F24S_L /* 618 */, XTENSA_INS_AE_CVTA32F24S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_cvtq56a32s $ae_ar_to_dr_v, $ars */ + Xtensa_AE_CVTQ56A32S /* 619 */, XTENSA_INS_AE_CVTQ56A32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_cvtq56p32s.h $ae_dr_to_dr_v, $ae_dr_to_dr_v0 */ + Xtensa_AE_CVTQ56P32S_H /* 620 */, XTENSA_INS_AE_CVTQ56P32S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_cvtq56p32s.l $ae_dr_to_dr_v, $ae_dr_to_dr_v0 */ + Xtensa_AE_CVTQ56P32S_L /* 621 */, XTENSA_INS_AE_CVTQ56P32S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_db $ars, $art */ + Xtensa_AE_DB /* 622 */, XTENSA_INS_AE_DB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_dbi $ars, $ae_ohba */ + Xtensa_AE_DBI /* 623 */, XTENSA_INS_AE_DBI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_dbi.ic $ars, $ae_ohba */ + Xtensa_AE_DBI_IC /* 624 */, XTENSA_INS_AE_DBI_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_dbi.ip $ars, $ae_ohba */ + Xtensa_AE_DBI_IP /* 625 */, XTENSA_INS_AE_DBI_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_db.ic $ars, $art */ + Xtensa_AE_DB_IC /* 626 */, XTENSA_INS_AE_DB_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_db.ip $ars, $art */ + Xtensa_AE_DB_IP /* 627 */, XTENSA_INS_AE_DB_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_div64d32.h $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_DIV64D32_H /* 628 */, XTENSA_INS_AE_DIV64D32_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_div64d32.l $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_DIV64D32_L /* 629 */, XTENSA_INS_AE_DIV64D32_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_eq16 $br4, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_EQ16 /* 630 */, XTENSA_INS_AE_EQ16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_eq32 $br2, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_EQ32 /* 631 */, XTENSA_INS_AE_EQ32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_eq64 $br, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_EQ64 /* 632 */, XTENSA_INS_AE_EQ64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16m.i $ae_ls_v, $ars, $ae_immls16 */ + Xtensa_AE_L16M_I /* 633 */, XTENSA_INS_AE_L16M_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16m.iu $ae_ls_v, $ars, $ae_immls16 */ + Xtensa_AE_L16M_IU /* 634 */, XTENSA_INS_AE_L16M_IU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16m.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L16M_X /* 635 */, XTENSA_INS_AE_L16M_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16m.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L16M_XC /* 636 */, XTENSA_INS_AE_L16M_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16m.xu $ae_ls_v, $ars, $art */ + Xtensa_AE_L16M_XU /* 637 */, XTENSA_INS_AE_L16M_XU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16x2m.i $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_L16X2M_I /* 638 */, XTENSA_INS_AE_L16X2M_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16x2m.iu $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_L16X2M_IU /* 639 */, XTENSA_INS_AE_L16X2M_IU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16x2m.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L16X2M_X /* 640 */, XTENSA_INS_AE_L16X2M_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16x2m.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L16X2M_XC /* 641 */, XTENSA_INS_AE_L16X2M_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16x2m.xu $ae_ls_v, $ars, $art */ + Xtensa_AE_L16X2M_XU /* 642 */, XTENSA_INS_AE_L16X2M_XU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16x4.i $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_L16X4_I /* 643 */, XTENSA_INS_AE_L16X4_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16x4.ip $ae_ls_v, $ars, $ae_immls64pos */ + Xtensa_AE_L16X4_IP /* 644 */, XTENSA_INS_AE_L16X4_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16x4.ric $ae_ls_v, $ars */ + Xtensa_AE_L16X4_RIC /* 645 */, XTENSA_INS_AE_L16X4_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16x4.rip $ae_ls_v, $ars */ + Xtensa_AE_L16X4_RIP /* 646 */, XTENSA_INS_AE_L16X4_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16x4.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L16X4_X /* 647 */, XTENSA_INS_AE_L16X4_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16x4.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L16X4_XC /* 648 */, XTENSA_INS_AE_L16X4_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16x4.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_L16X4_XP /* 649 */, XTENSA_INS_AE_L16X4_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16.i $ae_ls_v, $ars, $ae_immls16 */ + Xtensa_AE_L16_I /* 650 */, XTENSA_INS_AE_L16_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16.ip $ae_ls_v, $ars, $ae_immls16 */ + Xtensa_AE_L16_IP /* 651 */, XTENSA_INS_AE_L16_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l16.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L16_X /* 652 */, XTENSA_INS_AE_L16_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L16_XC /* 653 */, XTENSA_INS_AE_L16_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l16.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_L16_XP /* 654 */, XTENSA_INS_AE_L16_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l32f24.i $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_L32F24_I /* 655 */, XTENSA_INS_AE_L32F24_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32f24.ip $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_L32F24_IP /* 656 */, XTENSA_INS_AE_L32F24_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32f24.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L32F24_X /* 657 */, XTENSA_INS_AE_L32F24_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l32f24.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L32F24_XC /* 658 */, XTENSA_INS_AE_L32F24_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32f24.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_L32F24_XP /* 659 */, XTENSA_INS_AE_L32F24_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l32m.i $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_L32M_I /* 660 */, XTENSA_INS_AE_L32M_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32m.iu $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_L32M_IU /* 661 */, XTENSA_INS_AE_L32M_IU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32m.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L32M_X /* 662 */, XTENSA_INS_AE_L32M_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32m.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L32M_XC /* 663 */, XTENSA_INS_AE_L32M_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l32m.xu $ae_ls_v, $ars, $art */ + Xtensa_AE_L32M_XU /* 664 */, XTENSA_INS_AE_L32M_XU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2f24.i $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_L32X2F24_I /* 665 */, XTENSA_INS_AE_L32X2F24_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2f24.ip $ae_ls_v, $ars, $ae_immls64pos */ + Xtensa_AE_L32X2F24_IP /* 666 */, XTENSA_INS_AE_L32X2F24_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2f24.ric $ae_ls_v, $ars */ + Xtensa_AE_L32X2F24_RIC /* 667 */, XTENSA_INS_AE_L32X2F24_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l32x2f24.rip $ae_ls_v, $ars */ + Xtensa_AE_L32X2F24_RIP /* 668 */, XTENSA_INS_AE_L32X2F24_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2f24.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L32X2F24_X /* 669 */, XTENSA_INS_AE_L32X2F24_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2f24.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L32X2F24_XC /* 670 */, XTENSA_INS_AE_L32X2F24_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2f24.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_L32X2F24_XP /* 671 */, XTENSA_INS_AE_L32X2F24_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2.i $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_L32X2_I /* 672 */, XTENSA_INS_AE_L32X2_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2.ip $ae_ls_v, $ars, $ae_immls64pos */ + Xtensa_AE_L32X2_IP /* 673 */, XTENSA_INS_AE_L32X2_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2.ric $ae_ls_v, $ars */ + Xtensa_AE_L32X2_RIC /* 674 */, XTENSA_INS_AE_L32X2_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l32x2.rip $ae_ls_v, $ars */ + Xtensa_AE_L32X2_RIP /* 675 */, XTENSA_INS_AE_L32X2_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L32X2_X /* 676 */, XTENSA_INS_AE_L32X2_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L32X2_XC /* 677 */, XTENSA_INS_AE_L32X2_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32x2.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_L32X2_XP /* 678 */, XTENSA_INS_AE_L32X2_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32.i $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_L32_I /* 679 */, XTENSA_INS_AE_L32_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32.ip $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_L32_IP /* 680 */, XTENSA_INS_AE_L32_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L32_X /* 681 */, XTENSA_INS_AE_L32_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L32_XC /* 682 */, XTENSA_INS_AE_L32_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l32.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_L32_XP /* 683 */, XTENSA_INS_AE_L32_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l64.i $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_L64_I /* 684 */, XTENSA_INS_AE_L64_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l64.ip $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_L64_IP /* 685 */, XTENSA_INS_AE_L64_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_l64.x $ae_ls_v, $ars, $art */ + Xtensa_AE_L64_X /* 686 */, XTENSA_INS_AE_L64_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l64.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_L64_XC /* 687 */, XTENSA_INS_AE_L64_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_l64.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_L64_XP /* 688 */, XTENSA_INS_AE_L64_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la16x4neg.pc $ae_ls_uu, $ars */ + Xtensa_AE_LA16X4NEG_PC /* 689 */, XTENSA_INS_AE_LA16X4NEG_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la16x4pos.pc $ae_ls_uu, $ars */ + Xtensa_AE_LA16X4POS_PC /* 690 */, XTENSA_INS_AE_LA16X4POS_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la16x4.ic $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA16X4_IC /* 691 */, XTENSA_INS_AE_LA16X4_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la16x4.ip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA16X4_IP /* 692 */, XTENSA_INS_AE_LA16X4_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la16x4.ric $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA16X4_RIC /* 693 */, XTENSA_INS_AE_LA16X4_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la16x4.rip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA16X4_RIP /* 694 */, XTENSA_INS_AE_LA16X4_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la24neg.pc $ae_ls_uu, $ars */ + Xtensa_AE_LA24NEG_PC /* 695 */, XTENSA_INS_AE_LA24NEG_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24pos.pc $ae_ls_uu, $ars */ + Xtensa_AE_LA24POS_PC /* 696 */, XTENSA_INS_AE_LA24POS_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24x2neg.pc $ae_ls_uu, $ars */ + Xtensa_AE_LA24X2NEG_PC /* 697 */, XTENSA_INS_AE_LA24X2NEG_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24x2pos.pc $ae_ls_uu, $ars */ + Xtensa_AE_LA24X2POS_PC /* 698 */, XTENSA_INS_AE_LA24X2POS_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24x2.ic $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA24X2_IC /* 699 */, XTENSA_INS_AE_LA24X2_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la24x2.ip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA24X2_IP /* 700 */, XTENSA_INS_AE_LA24X2_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la24x2.ric $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA24X2_RIC /* 701 */, XTENSA_INS_AE_LA24X2_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24x2.rip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA24X2_RIP /* 702 */, XTENSA_INS_AE_LA24X2_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24.ic $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA24_IC /* 703 */, XTENSA_INS_AE_LA24_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24.ip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA24_IP /* 704 */, XTENSA_INS_AE_LA24_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24.ric $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA24_RIC /* 705 */, XTENSA_INS_AE_LA24_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la24.rip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA24_RIP /* 706 */, XTENSA_INS_AE_LA24_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la32x2f24.ic $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2F24_IC /* 707 */, XTENSA_INS_AE_LA32X2F24_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la32x2f24.ip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2F24_IP /* 708 */, XTENSA_INS_AE_LA32X2F24_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la32x2f24.ric $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2F24_RIC /* 709 */, XTENSA_INS_AE_LA32X2F24_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la32x2f24.rip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2F24_RIP /* 710 */, XTENSA_INS_AE_LA32X2F24_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la32x2neg.pc $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2NEG_PC /* 711 */, XTENSA_INS_AE_LA32X2NEG_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la32x2pos.pc $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2POS_PC /* 712 */, XTENSA_INS_AE_LA32X2POS_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la32x2.ic $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2_IC /* 713 */, XTENSA_INS_AE_LA32X2_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la32x2.ip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2_IP /* 714 */, XTENSA_INS_AE_LA32X2_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_la32x2.ric $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2_RIC /* 715 */, XTENSA_INS_AE_LA32X2_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la32x2.rip $ae_ls_av, $ae_ls_uu, $ars */ + Xtensa_AE_LA32X2_RIP /* 716 */, XTENSA_INS_AE_LA32X2_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_la64.pp $ae_ls_uu, $ars */ + Xtensa_AE_LA64_PP /* 717 */, XTENSA_INS_AE_LA64_PP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_lalign64.i $ae_ls_uu, $ars, $ae_immls64 */ + Xtensa_AE_LALIGN64_I /* 718 */, XTENSA_INS_AE_LALIGN64_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_lb $arr, $art */ + Xtensa_AE_LB /* 719 */, XTENSA_INS_AE_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_lbi $arr, $ae_ohba */ + Xtensa_AE_LBI /* 720 */, XTENSA_INS_AE_LBI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_lbk $arr, $ars, $art */ + Xtensa_AE_LBK /* 721 */, XTENSA_INS_AE_LBK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_lbki $arr, $ars, $ae_ohba */ + Xtensa_AE_LBKI /* 722 */, XTENSA_INS_AE_LBKI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_lbs $arr, $art */ + Xtensa_AE_LBS /* 723 */, XTENSA_INS_AE_LBS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_lbsi $arr, $ae_ohba */ + Xtensa_AE_LBSI /* 724 */, XTENSA_INS_AE_LBSI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_le16 $br4, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_LE16 /* 725 */, XTENSA_INS_AE_LE16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_le32 $br2, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_LE32 /* 726 */, XTENSA_INS_AE_LE32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_le64 $br, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_LE64 /* 727 */, XTENSA_INS_AE_LE64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_lt16 $br4, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_LT16 /* 728 */, XTENSA_INS_AE_LT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_lt32 $br2, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_LT32 /* 729 */, XTENSA_INS_AE_LT32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_lt64 $br, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_LT64 /* 730 */, XTENSA_INS_AE_LT64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_max32 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_MAX32 /* 731 */, XTENSA_INS_AE_MAX32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_max64 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_MAX64 /* 732 */, XTENSA_INS_AE_MAX64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_maxabs32s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_MAXABS32S /* 733 */, XTENSA_INS_AE_MAXABS32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_maxabs64s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_MAXABS64S /* 734 */, XTENSA_INS_AE_MAXABS64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_min32 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_MIN32 /* 735 */, XTENSA_INS_AE_MIN32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_min64 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_MIN64 /* 736 */, XTENSA_INS_AE_MIN64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_minabs32s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_MINABS32S /* 737 */, XTENSA_INS_AE_MINABS32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_minabs64s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ + Xtensa_AE_MINABS64S /* 738 */, XTENSA_INS_AE_MINABS64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mov $ae_to_dr_v, $ae_to_dr_v0 */ + Xtensa_AE_MOV /* 739 */, XTENSA_INS_AE_MOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movad16.0 $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_MOVAD16_0 /* 740 */, XTENSA_INS_AE_MOVAD16_0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movad16.1 $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_MOVAD16_1 /* 741 */, XTENSA_INS_AE_MOVAD16_1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_movad16.2 $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_MOVAD16_2 /* 742 */, XTENSA_INS_AE_MOVAD16_2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movad16.3 $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_MOVAD16_3 /* 743 */, XTENSA_INS_AE_MOVAD16_3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movad32.h $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_MOVAD32_H /* 744 */, XTENSA_INS_AE_MOVAD32_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movad32.l $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_MOVAD32_L /* 745 */, XTENSA_INS_AE_MOVAD32_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movalign $ae_uu_uu, $ae_uu_v */ + Xtensa_AE_MOVALIGN /* 746 */, XTENSA_INS_AE_MOVALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movda16 $ae_ar_to_dr_v, $ars */ + Xtensa_AE_MOVDA16 /* 747 */, XTENSA_INS_AE_MOVDA16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movda16x2 $ae_ar_to_dr_v, $ars, $art */ + Xtensa_AE_MOVDA16X2 /* 748 */, XTENSA_INS_AE_MOVDA16X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movda32 $ae_ar_to_dr_v, $ars */ + Xtensa_AE_MOVDA32 /* 749 */, XTENSA_INS_AE_MOVDA32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movda32x2 $ae_ar_to_dr_v, $ars, $art */ + Xtensa_AE_MOVDA32X2 /* 750 */, XTENSA_INS_AE_MOVDA32X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movf16x4 $ae_cmov_v, $ae_cmov_v0, $bt4 */ + Xtensa_AE_MOVF16X4 /* 751 */, XTENSA_INS_AE_MOVF16X4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_movf32x2 $ae_cmov_v, $ae_cmov_v0, $bt2 */ + Xtensa_AE_MOVF32X2 /* 752 */, XTENSA_INS_AE_MOVF32X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movf64 $ae_cmov_v, $ae_cmov_v0, $bt */ + Xtensa_AE_MOVF64 /* 753 */, XTENSA_INS_AE_MOVF64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_movi $ae_ar_to_dr_v, $movi_imm */ + Xtensa_AE_MOVI /* 754 */, XTENSA_INS_AE_MOVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movt16x4 $ae_cmov_v, $ae_cmov_v0, $bt4 */ + Xtensa_AE_MOVT16X4 /* 755 */, XTENSA_INS_AE_MOVT16X4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_movt32x2 $ae_cmov_v, $ae_cmov_v0, $bt2 */ + Xtensa_AE_MOVT32X2 /* 756 */, XTENSA_INS_AE_MOVT32X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_movt64 $ae_cmov_v, $ae_cmov_v0, $bt */ + Xtensa_AE_MOVT64 /* 757 */, XTENSA_INS_AE_MOVT64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_mul16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ + Xtensa_AE_MUL16X4 /* 758 */, XTENSA_INS_AE_MUL16X4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32U_LL /* 759 */, XTENSA_INS_AE_MUL32U_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32X16_H0 /* 760 */, XTENSA_INS_AE_MUL32X16_H0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32X16_H0_S2 /* 761 */, XTENSA_INS_AE_MUL32X16_H0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32X16_H1 /* 762 */, XTENSA_INS_AE_MUL32X16_H1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32X16_H1_S2 /* 763 */, XTENSA_INS_AE_MUL32X16_H1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32X16_H2 /* 764 */, XTENSA_INS_AE_MUL32X16_H2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32X16_H2_S2 /* 765 */, XTENSA_INS_AE_MUL32X16_H2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32X16_H3 /* 766 */, XTENSA_INS_AE_MUL32X16_H3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32X16_H3_S2 /* 767 */, XTENSA_INS_AE_MUL32X16_H3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32X16_L0 /* 768 */, XTENSA_INS_AE_MUL32X16_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32X16_L0_S2 /* 769 */, XTENSA_INS_AE_MUL32X16_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32X16_L1 /* 770 */, XTENSA_INS_AE_MUL32X16_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32X16_L1_S2 /* 771 */, XTENSA_INS_AE_MUL32X16_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32X16_L2 /* 772 */, XTENSA_INS_AE_MUL32X16_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32X16_L2_S2 /* 773 */, XTENSA_INS_AE_MUL32X16_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32X16_L3 /* 774 */, XTENSA_INS_AE_MUL32X16_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32X16_L3_S2 /* 775 */, XTENSA_INS_AE_MUL32X16_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32_HH /* 776 */, XTENSA_INS_AE_MUL32_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32_LH /* 777 */, XTENSA_INS_AE_MUL32_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MUL32_LL /* 778 */, XTENSA_INS_AE_MUL32_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mul32.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MUL32_LL_S2 /* 779 */, XTENSA_INS_AE_MUL32_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ + Xtensa_AE_MULA16X4 /* 780 */, XTENSA_INS_AE_MULA16X4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32U_LL /* 781 */, XTENSA_INS_AE_MULA32U_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32X16_H0 /* 782 */, XTENSA_INS_AE_MULA32X16_H0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32X16_H0_S2 /* 783 */, XTENSA_INS_AE_MULA32X16_H0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32X16_H1 /* 784 */, XTENSA_INS_AE_MULA32X16_H1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32X16_H1_S2 /* 785 */, XTENSA_INS_AE_MULA32X16_H1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32X16_H2 /* 786 */, XTENSA_INS_AE_MULA32X16_H2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32X16_H2_S2 /* 787 */, XTENSA_INS_AE_MULA32X16_H2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32X16_H3 /* 788 */, XTENSA_INS_AE_MULA32X16_H3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32X16_H3_S2 /* 789 */, XTENSA_INS_AE_MULA32X16_H3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32X16_L0 /* 790 */, XTENSA_INS_AE_MULA32X16_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32X16_L0_S2 /* 791 */, XTENSA_INS_AE_MULA32X16_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32X16_L1 /* 792 */, XTENSA_INS_AE_MULA32X16_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32X16_L1_S2 /* 793 */, XTENSA_INS_AE_MULA32X16_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32X16_L2 /* 794 */, XTENSA_INS_AE_MULA32X16_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32X16_L2_S2 /* 795 */, XTENSA_INS_AE_MULA32X16_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32X16_L3 /* 796 */, XTENSA_INS_AE_MULA32X16_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32X16_L3_S2 /* 797 */, XTENSA_INS_AE_MULA32X16_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32_HH /* 798 */, XTENSA_INS_AE_MULA32_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32_LH /* 799 */, XTENSA_INS_AE_MULA32_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULA32_LL /* 800 */, XTENSA_INS_AE_MULA32_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mula32.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULA32_LL_S2 /* 801 */, XTENSA_INS_AE_MULA32_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAAD24_HH_LL /* 802 */, XTENSA_INS_AE_MULAAD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAD24_HH_LL_S2 /* 803 */, XTENSA_INS_AE_MULAAD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAAD24_HL_LH /* 804 */, XTENSA_INS_AE_MULAAD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAD24_HL_LH_S2 /* 805 */, XTENSA_INS_AE_MULAAD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAD32X16_H0_L1 /* 806 */, XTENSA_INS_AE_MULAAD32X16_H0_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAD32X16_H0_L1_S2 /* 807 */, XTENSA_INS_AE_MULAAD32X16_H0_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAD32X16_H1_L0 /* 808 */, XTENSA_INS_AE_MULAAD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAD32X16_H1_L0_S2 /* 809 */, XTENSA_INS_AE_MULAAD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAD32X16_H2_L3 /* 810 */, XTENSA_INS_AE_MULAAD32X16_H2_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAD32X16_H2_L3_S2 /* 811 */, XTENSA_INS_AE_MULAAD32X16_H2_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAD32X16_H3_L2 /* 812 */, XTENSA_INS_AE_MULAAD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAD32X16_H3_L2_S2 /* 813 */, XTENSA_INS_AE_MULAAD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAFD16SS_11_00 /* 814 */, XTENSA_INS_AE_MULAAFD16SS_11_00, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD16SS_11_00_S2 /* 815 */, XTENSA_INS_AE_MULAAFD16SS_11_00_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAFD16SS_13_02 /* 816 */, XTENSA_INS_AE_MULAAFD16SS_13_02, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD16SS_13_02_S2 /* 817 */, XTENSA_INS_AE_MULAAFD16SS_13_02_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAFD16SS_33_22 /* 818 */, XTENSA_INS_AE_MULAAFD16SS_33_22, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD16SS_33_22_S2 /* 819 */, XTENSA_INS_AE_MULAAFD16SS_33_22_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAAFD24_HH_LL /* 820 */, XTENSA_INS_AE_MULAAFD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD24_HH_LL_S2 /* 821 */, XTENSA_INS_AE_MULAAFD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAAFD24_HL_LH /* 822 */, XTENSA_INS_AE_MULAAFD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD24_HL_LH_S2 /* 823 */, XTENSA_INS_AE_MULAAFD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAFD32X16_H0_L1 /* 824 */, XTENSA_INS_AE_MULAAFD32X16_H0_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD32X16_H0_L1_S2 /* 825 */, XTENSA_INS_AE_MULAAFD32X16_H0_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAFD32X16_H1_L0 /* 826 */, XTENSA_INS_AE_MULAAFD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD32X16_H1_L0_S2 /* 827 */, XTENSA_INS_AE_MULAAFD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAFD32X16_H2_L3 /* 828 */, XTENSA_INS_AE_MULAAFD32X16_H2_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD32X16_H2_L3_S2 /* 829 */, XTENSA_INS_AE_MULAAFD32X16_H2_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAAFD32X16_H3_L2 /* 830 */, XTENSA_INS_AE_MULAAFD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAAFD32X16_H3_L2_S2 /* 831 */, XTENSA_INS_AE_MULAAFD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulac24 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAC24 /* 832 */, XTENSA_INS_AE_MULAC24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulac32x16.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULAC32X16_H /* 833 */, XTENSA_INS_AE_MULAC32X16_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulac32x16.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULAC32X16_L /* 834 */, XTENSA_INS_AE_MULAC32X16_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF16SS_00 /* 835 */, XTENSA_INS_AE_MULAF16SS_00, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF16SS_00_S2 /* 836 */, XTENSA_INS_AE_MULAF16SS_00_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_10 /* 837 */, XTENSA_INS_AE_MULAF16SS_10, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_11 /* 838 */, XTENSA_INS_AE_MULAF16SS_11, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_20 /* 839 */, XTENSA_INS_AE_MULAF16SS_20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_21 /* 840 */, XTENSA_INS_AE_MULAF16SS_21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_22 /* 841 */, XTENSA_INS_AE_MULAF16SS_22, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_30 /* 842 */, XTENSA_INS_AE_MULAF16SS_30, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_31 /* 843 */, XTENSA_INS_AE_MULAF16SS_31, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_32 /* 844 */, XTENSA_INS_AE_MULAF16SS_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAF16SS_33 /* 845 */, XTENSA_INS_AE_MULAF16SS_33, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ + Xtensa_AE_MULAF16X4SS /* 846 */, XTENSA_INS_AE_MULAF16X4SS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32R_HH /* 847 */, XTENSA_INS_AE_MULAF32R_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32R_LH /* 848 */, XTENSA_INS_AE_MULAF32R_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32R_LL /* 849 */, XTENSA_INS_AE_MULAF32R_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32R_LL_S2 /* 850 */, XTENSA_INS_AE_MULAF32R_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32S_HH /* 851 */, XTENSA_INS_AE_MULAF32S_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32S_LH /* 852 */, XTENSA_INS_AE_MULAF32S_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32S_LL /* 853 */, XTENSA_INS_AE_MULAF32S_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32S_LL_S2 /* 854 */, XTENSA_INS_AE_MULAF32S_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32X16_H0 /* 855 */, XTENSA_INS_AE_MULAF32X16_H0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32X16_H0_S2 /* 856 */, XTENSA_INS_AE_MULAF32X16_H0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32X16_H1 /* 857 */, XTENSA_INS_AE_MULAF32X16_H1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32X16_H1_S2 /* 858 */, XTENSA_INS_AE_MULAF32X16_H1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32X16_H2 /* 859 */, XTENSA_INS_AE_MULAF32X16_H2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32X16_H2_S2 /* 860 */, XTENSA_INS_AE_MULAF32X16_H2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32X16_H3 /* 861 */, XTENSA_INS_AE_MULAF32X16_H3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32X16_H3_S2 /* 862 */, XTENSA_INS_AE_MULAF32X16_H3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32X16_L0 /* 863 */, XTENSA_INS_AE_MULAF32X16_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32X16_L0_S2 /* 864 */, XTENSA_INS_AE_MULAF32X16_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32X16_L1 /* 865 */, XTENSA_INS_AE_MULAF32X16_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32X16_L1_S2 /* 866 */, XTENSA_INS_AE_MULAF32X16_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32X16_L2 /* 867 */, XTENSA_INS_AE_MULAF32X16_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32X16_L2_S2 /* 868 */, XTENSA_INS_AE_MULAF32X16_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF32X16_L3 /* 869 */, XTENSA_INS_AE_MULAF32X16_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF32X16_L3_S2 /* 870 */, XTENSA_INS_AE_MULAF32X16_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF48Q32SP16S_L /* 871 */, XTENSA_INS_AE_MULAF48Q32SP16S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF48Q32SP16S_L_S2 /* 872 */, XTENSA_INS_AE_MULAF48Q32SP16S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAF48Q32SP16U_L /* 873 */, XTENSA_INS_AE_MULAF48Q32SP16U_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAF48Q32SP16U_L_S2 /* 874 */, XTENSA_INS_AE_MULAF48Q32SP16U_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafc24ra $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULAFC24RA /* 875 */, XTENSA_INS_AE_MULAFC24RA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafc32x16ras.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULAFC32X16RAS_H /* 876 */, XTENSA_INS_AE_MULAFC32X16RAS_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafc32x16ras.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULAFC32X16RAS_L /* 877 */, XTENSA_INS_AE_MULAFC32X16RAS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafd24x2.fir.h $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULAFD24X2_FIR_H /* 878 */, XTENSA_INS_AE_MULAFD24X2_FIR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafd24x2.fir.l $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULAFD24X2_FIR_L /* 879 */, XTENSA_INS_AE_MULAFD24X2_FIR_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafd32x16x2.fir.hh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULAFD32X16X2_FIR_HH /* 880 */, XTENSA_INS_AE_MULAFD32X16X2_FIR_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafd32x16x2.fir.hl $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULAFD32X16X2_FIR_HL /* 881 */, XTENSA_INS_AE_MULAFD32X16X2_FIR_HL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafd32x16x2.fir.lh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULAFD32X16X2_FIR_LH /* 882 */, XTENSA_INS_AE_MULAFD32X16X2_FIR_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafd32x16x2.fir.ll $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULAFD32X16X2_FIR_LL /* 883 */, XTENSA_INS_AE_MULAFD32X16X2_FIR_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAFP24X2R /* 884 */, XTENSA_INS_AE_MULAFP24X2R, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAFP24X2RA /* 885 */, XTENSA_INS_AE_MULAFP24X2RA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAFP24X2RA_S2 /* 886 */, XTENSA_INS_AE_MULAFP24X2RA_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAFP24X2R_S2 /* 887 */, XTENSA_INS_AE_MULAFP24X2R_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAFP32X16X2RAS_H /* 888 */, XTENSA_INS_AE_MULAFP32X16X2RAS_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAFP32X16X2RAS_H_S2 /* 889 */, XTENSA_INS_AE_MULAFP32X16X2RAS_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAFP32X16X2RAS_L /* 890 */, XTENSA_INS_AE_MULAFP32X16X2RAS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAFP32X16X2RAS_L_S2 /* 891 */, XTENSA_INS_AE_MULAFP32X16X2RAS_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAFP32X16X2RS_H /* 892 */, XTENSA_INS_AE_MULAFP32X16X2RS_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAFP32X16X2RS_H_S2 /* 893 */, XTENSA_INS_AE_MULAFP32X16X2RS_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAFP32X16X2RS_L /* 894 */, XTENSA_INS_AE_MULAFP32X16X2RS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAFP32X16X2RS_L_S2 /* 895 */, XTENSA_INS_AE_MULAFP32X16X2RS_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAFP32X2RAS /* 896 */, XTENSA_INS_AE_MULAFP32X2RAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAFP32X2RS /* 897 */, XTENSA_INS_AE_MULAFP32X2RS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAFQ32SP24S_H_S2 /* 898 */, XTENSA_INS_AE_MULAFQ32SP24S_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulafq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAFQ32SP24S_L_S2 /* 899 */, XTENSA_INS_AE_MULAFQ32SP24S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulap24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULAP24X2 /* 900 */, XTENSA_INS_AE_MULAP24X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulap24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAP24X2_S2 /* 901 */, XTENSA_INS_AE_MULAP24X2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulap32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAP32X16X2_H /* 902 */, XTENSA_INS_AE_MULAP32X16X2_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulap32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAP32X16X2_L /* 903 */, XTENSA_INS_AE_MULAP32X16X2_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulap32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAP32X2 /* 904 */, XTENSA_INS_AE_MULAP32X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAQ32SP16S_L_S2 /* 905 */, XTENSA_INS_AE_MULAQ32SP16S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulaq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAQ32SP16U_L_S2 /* 906 */, XTENSA_INS_AE_MULAQ32SP16U_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mularfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULARFQ32SP24S_H_S2 /* 907 */, XTENSA_INS_AE_MULARFQ32SP24S_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mularfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULARFQ32SP24S_L_S2 /* 908 */, XTENSA_INS_AE_MULARFQ32SP24S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulas32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAS32F48P16S_HH /* 909 */, XTENSA_INS_AE_MULAS32F48P16S_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulas32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAS32F48P16S_HH_S2 /* 910 */, XTENSA_INS_AE_MULAS32F48P16S_HH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulas32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAS32F48P16S_LH /* 911 */, XTENSA_INS_AE_MULAS32F48P16S_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulas32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAS32F48P16S_LH_S2 /* 912 */, XTENSA_INS_AE_MULAS32F48P16S_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulas32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULAS32F48P16S_LL /* 913 */, XTENSA_INS_AE_MULAS32F48P16S_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulas32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULAS32F48P16S_LL_S2 /* 914 */, XTENSA_INS_AE_MULAS32F48P16S_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULASD24_HH_LL /* 915 */, XTENSA_INS_AE_MULASD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULASD24_HH_LL_S2 /* 916 */, XTENSA_INS_AE_MULASD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULASD24_HL_LH /* 917 */, XTENSA_INS_AE_MULASD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULASD24_HL_LH_S2 /* 918 */, XTENSA_INS_AE_MULASD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULASD32X16_H1_L0 /* 919 */, XTENSA_INS_AE_MULASD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULASD32X16_H1_L0_S2 /* 920 */, XTENSA_INS_AE_MULASD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULASD32X16_H3_L2 /* 921 */, XTENSA_INS_AE_MULASD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULASD32X16_H3_L2_S2 /* 922 */, XTENSA_INS_AE_MULASD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULASFD24_HH_LL /* 923 */, XTENSA_INS_AE_MULASFD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULASFD24_HH_LL_S2 /* 924 */, XTENSA_INS_AE_MULASFD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULASFD24_HL_LH /* 925 */, XTENSA_INS_AE_MULASFD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULASFD24_HL_LH_S2 /* 926 */, XTENSA_INS_AE_MULASFD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULASFD32X16_H1_L0 /* 927 */, XTENSA_INS_AE_MULASFD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULASFD32X16_H1_L0_S2 /* 928 */, XTENSA_INS_AE_MULASFD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULASFD32X16_H3_L2 /* 929 */, XTENSA_INS_AE_MULASFD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulasfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULASFD32X16_H3_L2_S2 /* 930 */, XTENSA_INS_AE_MULASFD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulc24 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULC24 /* 931 */, XTENSA_INS_AE_MULC24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulc32x16.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULC32X16_H /* 932 */, XTENSA_INS_AE_MULC32X16_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulc32x16.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULC32X16_L /* 933 */, XTENSA_INS_AE_MULC32X16_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF16SS_00 /* 934 */, XTENSA_INS_AE_MULF16SS_00, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF16SS_00_S2 /* 935 */, XTENSA_INS_AE_MULF16SS_00_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_10 /* 936 */, XTENSA_INS_AE_MULF16SS_10, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_11 /* 937 */, XTENSA_INS_AE_MULF16SS_11, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_20 /* 938 */, XTENSA_INS_AE_MULF16SS_20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_21 /* 939 */, XTENSA_INS_AE_MULF16SS_21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_22 /* 940 */, XTENSA_INS_AE_MULF16SS_22, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_30 /* 941 */, XTENSA_INS_AE_MULF16SS_30, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_31 /* 942 */, XTENSA_INS_AE_MULF16SS_31, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_32 /* 943 */, XTENSA_INS_AE_MULF16SS_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULF16SS_33 /* 944 */, XTENSA_INS_AE_MULF16SS_33, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ + Xtensa_AE_MULF16X4SS /* 945 */, XTENSA_INS_AE_MULF16X4SS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32R_HH /* 946 */, XTENSA_INS_AE_MULF32R_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32R_LH /* 947 */, XTENSA_INS_AE_MULF32R_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32R_LL /* 948 */, XTENSA_INS_AE_MULF32R_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32R_LL_S2 /* 949 */, XTENSA_INS_AE_MULF32R_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32S_HH /* 950 */, XTENSA_INS_AE_MULF32S_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32S_LH /* 951 */, XTENSA_INS_AE_MULF32S_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32S_LL /* 952 */, XTENSA_INS_AE_MULF32S_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32S_LL_S2 /* 953 */, XTENSA_INS_AE_MULF32S_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32X16_H0 /* 954 */, XTENSA_INS_AE_MULF32X16_H0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32X16_H0_S2 /* 955 */, XTENSA_INS_AE_MULF32X16_H0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32X16_H1 /* 956 */, XTENSA_INS_AE_MULF32X16_H1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32X16_H1_S2 /* 957 */, XTENSA_INS_AE_MULF32X16_H1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32X16_H2 /* 958 */, XTENSA_INS_AE_MULF32X16_H2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32X16_H2_S2 /* 959 */, XTENSA_INS_AE_MULF32X16_H2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32X16_H3 /* 960 */, XTENSA_INS_AE_MULF32X16_H3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32X16_H3_S2 /* 961 */, XTENSA_INS_AE_MULF32X16_H3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32X16_L0 /* 962 */, XTENSA_INS_AE_MULF32X16_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32X16_L0_S2 /* 963 */, XTENSA_INS_AE_MULF32X16_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32X16_L1 /* 964 */, XTENSA_INS_AE_MULF32X16_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32X16_L1_S2 /* 965 */, XTENSA_INS_AE_MULF32X16_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32X16_L2 /* 966 */, XTENSA_INS_AE_MULF32X16_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32X16_L2_S2 /* 967 */, XTENSA_INS_AE_MULF32X16_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF32X16_L3 /* 968 */, XTENSA_INS_AE_MULF32X16_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF32X16_L3_S2 /* 969 */, XTENSA_INS_AE_MULF32X16_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF48Q32SP16S_L /* 970 */, XTENSA_INS_AE_MULF48Q32SP16S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF48Q32SP16S_L_S2 /* 971 */, XTENSA_INS_AE_MULF48Q32SP16S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULF48Q32SP16U_L /* 972 */, XTENSA_INS_AE_MULF48Q32SP16U_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULF48Q32SP16U_L_S2 /* 973 */, XTENSA_INS_AE_MULF48Q32SP16U_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfc24ra $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULFC24RA /* 974 */, XTENSA_INS_AE_MULFC24RA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfc32x16ras.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULFC32X16RAS_H /* 975 */, XTENSA_INS_AE_MULFC32X16RAS_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfc32x16ras.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ + Xtensa_AE_MULFC32X16RAS_L /* 976 */, XTENSA_INS_AE_MULFC32X16RAS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfd24x2.fir.h $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULFD24X2_FIR_H /* 977 */, XTENSA_INS_AE_MULFD24X2_FIR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfd24x2.fir.l $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULFD24X2_FIR_L /* 978 */, XTENSA_INS_AE_MULFD24X2_FIR_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfd32x16x2.fir.hh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULFD32X16X2_FIR_HH /* 979 */, XTENSA_INS_AE_MULFD32X16X2_FIR_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfd32x16x2.fir.hl $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULFD32X16X2_FIR_HL /* 980 */, XTENSA_INS_AE_MULFD32X16X2_FIR_HL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfd32x16x2.fir.lh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULFD32X16X2_FIR_LH /* 981 */, XTENSA_INS_AE_MULFD32X16X2_FIR_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfd32x16x2.fir.ll $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ + Xtensa_AE_MULFD32X16X2_FIR_LL /* 982 */, XTENSA_INS_AE_MULFD32X16X2_FIR_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp16x4ras $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULFP16X4RAS /* 983 */, XTENSA_INS_AE_MULFP16X4RAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp16x4s $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULFP16X4S /* 984 */, XTENSA_INS_AE_MULFP16X4S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULFP24X2R /* 985 */, XTENSA_INS_AE_MULFP24X2R, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULFP24X2RA /* 986 */, XTENSA_INS_AE_MULFP24X2RA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULFP24X2RA_S2 /* 987 */, XTENSA_INS_AE_MULFP24X2RA_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULFP24X2R_S2 /* 988 */, XTENSA_INS_AE_MULFP24X2R_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULFP32X16X2RAS_H /* 989 */, XTENSA_INS_AE_MULFP32X16X2RAS_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULFP32X16X2RAS_H_S2 /* 990 */, XTENSA_INS_AE_MULFP32X16X2RAS_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULFP32X16X2RAS_L /* 991 */, XTENSA_INS_AE_MULFP32X16X2RAS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULFP32X16X2RAS_L_S2 /* 992 */, XTENSA_INS_AE_MULFP32X16X2RAS_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULFP32X16X2RS_H /* 993 */, XTENSA_INS_AE_MULFP32X16X2RS_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULFP32X16X2RS_H_S2 /* 994 */, XTENSA_INS_AE_MULFP32X16X2RS_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULFP32X16X2RS_L /* 995 */, XTENSA_INS_AE_MULFP32X16X2RS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULFP32X16X2RS_L_S2 /* 996 */, XTENSA_INS_AE_MULFP32X16X2RS_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULFP32X2RAS /* 997 */, XTENSA_INS_AE_MULFP32X2RAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULFP32X2RS /* 998 */, XTENSA_INS_AE_MULFP32X2RS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULFQ32SP24S_H_S2 /* 999 */, XTENSA_INS_AE_MULFQ32SP24S_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULFQ32SP24S_L_S2 /* 1000 */, XTENSA_INS_AE_MULFQ32SP24S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulp24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULP24X2 /* 1001 */, XTENSA_INS_AE_MULP24X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulp24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULP24X2_S2 /* 1002 */, XTENSA_INS_AE_MULP24X2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulp32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULP32X16X2_H /* 1003 */, XTENSA_INS_AE_MULP32X16X2_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulp32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULP32X16X2_L /* 1004 */, XTENSA_INS_AE_MULP32X16X2_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulp32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULP32X2 /* 1005 */, XTENSA_INS_AE_MULP32X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULQ32SP16S_L_S2 /* 1006 */, XTENSA_INS_AE_MULQ32SP16S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULQ32SP16U_L_S2 /* 1007 */, XTENSA_INS_AE_MULQ32SP16U_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulrfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULRFQ32SP24S_H_S2 /* 1008 */, XTENSA_INS_AE_MULRFQ32SP24S_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulrfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULRFQ32SP24S_L_S2 /* 1009 */, XTENSA_INS_AE_MULRFQ32SP24S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ + Xtensa_AE_MULS16X4 /* 1010 */, XTENSA_INS_AE_MULS16X4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32F48P16S_HH /* 1011 */, XTENSA_INS_AE_MULS32F48P16S_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32F48P16S_HH_S2 /* 1012 */, XTENSA_INS_AE_MULS32F48P16S_HH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32F48P16S_LH /* 1013 */, XTENSA_INS_AE_MULS32F48P16S_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32F48P16S_LH_S2 /* 1014 */, XTENSA_INS_AE_MULS32F48P16S_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32F48P16S_LL /* 1015 */, XTENSA_INS_AE_MULS32F48P16S_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32F48P16S_LL_S2 /* 1016 */, XTENSA_INS_AE_MULS32F48P16S_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32U_LL /* 1017 */, XTENSA_INS_AE_MULS32U_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32X16_H0 /* 1018 */, XTENSA_INS_AE_MULS32X16_H0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32X16_H0_S2 /* 1019 */, XTENSA_INS_AE_MULS32X16_H0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32X16_H1 /* 1020 */, XTENSA_INS_AE_MULS32X16_H1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32X16_H1_S2 /* 1021 */, XTENSA_INS_AE_MULS32X16_H1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32X16_H2 /* 1022 */, XTENSA_INS_AE_MULS32X16_H2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32X16_H2_S2 /* 1023 */, XTENSA_INS_AE_MULS32X16_H2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32X16_H3 /* 1024 */, XTENSA_INS_AE_MULS32X16_H3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32X16_H3_S2 /* 1025 */, XTENSA_INS_AE_MULS32X16_H3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32X16_L0 /* 1026 */, XTENSA_INS_AE_MULS32X16_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32X16_L0_S2 /* 1027 */, XTENSA_INS_AE_MULS32X16_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32X16_L1 /* 1028 */, XTENSA_INS_AE_MULS32X16_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32X16_L1_S2 /* 1029 */, XTENSA_INS_AE_MULS32X16_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32X16_L2 /* 1030 */, XTENSA_INS_AE_MULS32X16_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32X16_L2_S2 /* 1031 */, XTENSA_INS_AE_MULS32X16_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32X16_L3 /* 1032 */, XTENSA_INS_AE_MULS32X16_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULS32X16_L3_S2 /* 1033 */, XTENSA_INS_AE_MULS32X16_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32_HH /* 1034 */, XTENSA_INS_AE_MULS32_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32_LH /* 1035 */, XTENSA_INS_AE_MULS32_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_muls32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULS32_LL /* 1036 */, XTENSA_INS_AE_MULS32_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSAD24_HH_LL /* 1037 */, XTENSA_INS_AE_MULSAD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSAD24_HH_LL_S2 /* 1038 */, XTENSA_INS_AE_MULSAD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsad32x16.h1.l0 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSAD32X16_H1_L0 /* 1039 */, XTENSA_INS_AE_MULSAD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSAD32X16_H1_L0_S2 /* 1040 */, XTENSA_INS_AE_MULSAD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsad32x16.h3.l2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSAD32X16_H3_L2 /* 1041 */, XTENSA_INS_AE_MULSAD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSAD32X16_H3_L2_S2 /* 1042 */, XTENSA_INS_AE_MULSAD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSAFD24_HH_LL /* 1043 */, XTENSA_INS_AE_MULSAFD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSAFD24_HH_LL_S2 /* 1044 */, XTENSA_INS_AE_MULSAFD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSAFD32X16_H1_L0 /* 1045 */, XTENSA_INS_AE_MULSAFD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSAFD32X16_H1_L0_S2 /* 1046 */, XTENSA_INS_AE_MULSAFD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSAFD32X16_H3_L2 /* 1047 */, XTENSA_INS_AE_MULSAFD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSAFD32X16_H3_L2_S2 /* 1048 */, XTENSA_INS_AE_MULSAFD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF16SS_00 /* 1049 */, XTENSA_INS_AE_MULSF16SS_00, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF16SS_00_S2 /* 1050 */, XTENSA_INS_AE_MULSF16SS_00_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_10 /* 1051 */, XTENSA_INS_AE_MULSF16SS_10, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_11 /* 1052 */, XTENSA_INS_AE_MULSF16SS_11, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_20 /* 1053 */, XTENSA_INS_AE_MULSF16SS_20, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_21 /* 1054 */, XTENSA_INS_AE_MULSF16SS_21, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_22 /* 1055 */, XTENSA_INS_AE_MULSF16SS_22, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_30 /* 1056 */, XTENSA_INS_AE_MULSF16SS_30, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_31 /* 1057 */, XTENSA_INS_AE_MULSF16SS_31, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_32 /* 1058 */, XTENSA_INS_AE_MULSF16SS_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSF16SS_33 /* 1059 */, XTENSA_INS_AE_MULSF16SS_33, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ + Xtensa_AE_MULSF16X4SS /* 1060 */, XTENSA_INS_AE_MULSF16X4SS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32R_HH /* 1061 */, XTENSA_INS_AE_MULSF32R_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32R_LH /* 1062 */, XTENSA_INS_AE_MULSF32R_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32R_LL /* 1063 */, XTENSA_INS_AE_MULSF32R_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32R_LL_S2 /* 1064 */, XTENSA_INS_AE_MULSF32R_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32S_HH /* 1065 */, XTENSA_INS_AE_MULSF32S_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32S_LH /* 1066 */, XTENSA_INS_AE_MULSF32S_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32S_LL /* 1067 */, XTENSA_INS_AE_MULSF32S_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32X16_H0 /* 1068 */, XTENSA_INS_AE_MULSF32X16_H0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32X16_H0_S2 /* 1069 */, XTENSA_INS_AE_MULSF32X16_H0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32X16_H1 /* 1070 */, XTENSA_INS_AE_MULSF32X16_H1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32X16_H1_S2 /* 1071 */, XTENSA_INS_AE_MULSF32X16_H1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32X16_H2 /* 1072 */, XTENSA_INS_AE_MULSF32X16_H2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32X16_H2_S2 /* 1073 */, XTENSA_INS_AE_MULSF32X16_H2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32X16_H3 /* 1074 */, XTENSA_INS_AE_MULSF32X16_H3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32X16_H3_S2 /* 1075 */, XTENSA_INS_AE_MULSF32X16_H3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32X16_L0 /* 1076 */, XTENSA_INS_AE_MULSF32X16_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32X16_L0_S2 /* 1077 */, XTENSA_INS_AE_MULSF32X16_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32X16_L1 /* 1078 */, XTENSA_INS_AE_MULSF32X16_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32X16_L1_S2 /* 1079 */, XTENSA_INS_AE_MULSF32X16_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32X16_L2 /* 1080 */, XTENSA_INS_AE_MULSF32X16_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32X16_L2_S2 /* 1081 */, XTENSA_INS_AE_MULSF32X16_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF32X16_L3 /* 1082 */, XTENSA_INS_AE_MULSF32X16_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF32X16_L3_S2 /* 1083 */, XTENSA_INS_AE_MULSF32X16_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF48Q32SP16S_L /* 1084 */, XTENSA_INS_AE_MULSF48Q32SP16S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF48Q32SP16S_L_S2 /* 1085 */, XTENSA_INS_AE_MULSF48Q32SP16S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSF48Q32SP16U_L /* 1086 */, XTENSA_INS_AE_MULSF48Q32SP16U_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSF48Q32SP16U_L_S2 /* 1087 */, XTENSA_INS_AE_MULSF48Q32SP16U_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSFP24X2R /* 1088 */, XTENSA_INS_AE_MULSFP24X2R, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSFP24X2RA /* 1089 */, XTENSA_INS_AE_MULSFP24X2RA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSFP24X2RA_S2 /* 1090 */, XTENSA_INS_AE_MULSFP24X2RA_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSFP24X2R_S2 /* 1091 */, XTENSA_INS_AE_MULSFP24X2R_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSFP32X16X2RAS_H /* 1092 */, XTENSA_INS_AE_MULSFP32X16X2RAS_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSFP32X16X2RAS_H_S2 /* 1093 */, XTENSA_INS_AE_MULSFP32X16X2RAS_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSFP32X16X2RAS_L /* 1094 */, XTENSA_INS_AE_MULSFP32X16X2RAS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSFP32X16X2RAS_L_S2 /* 1095 */, XTENSA_INS_AE_MULSFP32X16X2RAS_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSFP32X16X2RS_H /* 1096 */, XTENSA_INS_AE_MULSFP32X16X2RS_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSFP32X16X2RS_H_S2 /* 1097 */, XTENSA_INS_AE_MULSFP32X16X2RS_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSFP32X16X2RS_L /* 1098 */, XTENSA_INS_AE_MULSFP32X16X2RS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSFP32X16X2RS_L_S2 /* 1099 */, XTENSA_INS_AE_MULSFP32X16X2RS_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSFP32X2RAS /* 1100 */, XTENSA_INS_AE_MULSFP32X2RAS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSFP32X2RS /* 1101 */, XTENSA_INS_AE_MULSFP32X2RS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSFQ32SP24S_H_S2 /* 1102 */, XTENSA_INS_AE_MULSFQ32SP24S_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSFQ32SP24S_L_S2 /* 1103 */, XTENSA_INS_AE_MULSFQ32SP24S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsp24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSP24X2 /* 1104 */, XTENSA_INS_AE_MULSP24X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsp24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSP24X2_S2 /* 1105 */, XTENSA_INS_AE_MULSP24X2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsp32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSP32X16X2_H /* 1106 */, XTENSA_INS_AE_MULSP32X16X2_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsp32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSP32X16X2_L /* 1107 */, XTENSA_INS_AE_MULSP32X16X2_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsp32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSP32X2 /* 1108 */, XTENSA_INS_AE_MULSP32X2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSQ32SP16S_L_S2 /* 1109 */, XTENSA_INS_AE_MULSQ32SP16S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSQ32SP16U_L_S2 /* 1110 */, XTENSA_INS_AE_MULSQ32SP16U_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsrfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSRFQ32SP24S_H_S2 /* 1111 */, XTENSA_INS_AE_MULSRFQ32SP24S_H_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulsrfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSRFQ32SP24S_L_S2 /* 1112 */, XTENSA_INS_AE_MULSRFQ32SP24S_L_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulss32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSS32F48P16S_HH /* 1113 */, XTENSA_INS_AE_MULSS32F48P16S_HH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulss32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSS32F48P16S_HH_S2 /* 1114 */, XTENSA_INS_AE_MULSS32F48P16S_HH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulss32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSS32F48P16S_LH /* 1115 */, XTENSA_INS_AE_MULSS32F48P16S_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulss32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSS32F48P16S_LH_S2 /* 1116 */, XTENSA_INS_AE_MULSS32F48P16S_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulss32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSS32F48P16S_LL /* 1117 */, XTENSA_INS_AE_MULSS32F48P16S_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulss32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSS32F48P16S_LL_S2 /* 1118 */, XTENSA_INS_AE_MULSS32F48P16S_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSSD24_HH_LL /* 1119 */, XTENSA_INS_AE_MULSSD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSD24_HH_LL_S2 /* 1120 */, XTENSA_INS_AE_MULSSD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSSD24_HL_LH /* 1121 */, XTENSA_INS_AE_MULSSD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSD24_HL_LH_S2 /* 1122 */, XTENSA_INS_AE_MULSSD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSSD32X16_H1_L0 /* 1123 */, XTENSA_INS_AE_MULSSD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSD32X16_H1_L0_S2 /* 1124 */, XTENSA_INS_AE_MULSSD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSSD32X16_H3_L2 /* 1125 */, XTENSA_INS_AE_MULSSD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSD32X16_H3_L2_S2 /* 1126 */, XTENSA_INS_AE_MULSSD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSSFD16SS_11_00 /* 1127 */, XTENSA_INS_AE_MULSSFD16SS_11_00, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSFD16SS_11_00_S2 /* 1128 */, XTENSA_INS_AE_MULSSFD16SS_11_00_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSSFD16SS_13_02 /* 1129 */, XTENSA_INS_AE_MULSSFD16SS_13_02, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSFD16SS_13_02_S2 /* 1130 */, XTENSA_INS_AE_MULSSFD16SS_13_02_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSSFD16SS_33_22 /* 1131 */, XTENSA_INS_AE_MULSSFD16SS_33_22, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSFD16SS_33_22_S2 /* 1132 */, XTENSA_INS_AE_MULSSFD16SS_33_22_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSSFD24_HH_LL /* 1133 */, XTENSA_INS_AE_MULSSFD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSFD24_HH_LL_S2 /* 1134 */, XTENSA_INS_AE_MULSSFD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULSSFD24_HL_LH /* 1135 */, XTENSA_INS_AE_MULSSFD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSFD24_HL_LH_S2 /* 1136 */, XTENSA_INS_AE_MULSSFD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSSFD32X16_H1_L0 /* 1137 */, XTENSA_INS_AE_MULSSFD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSFD32X16_H1_L0_S2 /* 1138 */, XTENSA_INS_AE_MULSSFD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULSSFD32X16_H3_L2 /* 1139 */, XTENSA_INS_AE_MULSSFD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulssfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULSSFD32X16_H3_L2_S2 /* 1140 */, XTENSA_INS_AE_MULSSFD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZAAD24_HH_LL /* 1141 */, XTENSA_INS_AE_MULZAAD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAD24_HH_LL_S2 /* 1142 */, XTENSA_INS_AE_MULZAAD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZAAD24_HL_LH /* 1143 */, XTENSA_INS_AE_MULZAAD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAD24_HL_LH_S2 /* 1144 */, XTENSA_INS_AE_MULZAAD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAD32X16_H0_L1 /* 1145 */, XTENSA_INS_AE_MULZAAD32X16_H0_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAD32X16_H0_L1_S2 /* 1146 */, XTENSA_INS_AE_MULZAAD32X16_H0_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAD32X16_H1_L0 /* 1147 */, XTENSA_INS_AE_MULZAAD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAD32X16_H1_L0_S2 /* 1148 */, XTENSA_INS_AE_MULZAAD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAD32X16_H2_L3 /* 1149 */, XTENSA_INS_AE_MULZAAD32X16_H2_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAD32X16_H2_L3_S2 /* 1150 */, XTENSA_INS_AE_MULZAAD32X16_H2_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAD32X16_H3_L2 /* 1151 */, XTENSA_INS_AE_MULZAAD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAD32X16_H3_L2_S2 /* 1152 */, XTENSA_INS_AE_MULZAAD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAFD16SS_11_00 /* 1153 */, XTENSA_INS_AE_MULZAAFD16SS_11_00, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD16SS_11_00_S2 /* 1154 */, XTENSA_INS_AE_MULZAAFD16SS_11_00_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAFD16SS_13_02 /* 1155 */, XTENSA_INS_AE_MULZAAFD16SS_13_02, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD16SS_13_02_S2 /* 1156 */, XTENSA_INS_AE_MULZAAFD16SS_13_02_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAFD16SS_33_22 /* 1157 */, XTENSA_INS_AE_MULZAAFD16SS_33_22, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD16SS_33_22_S2 /* 1158 */, XTENSA_INS_AE_MULZAAFD16SS_33_22_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZAAFD24_HH_LL /* 1159 */, XTENSA_INS_AE_MULZAAFD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD24_HH_LL_S2 /* 1160 */, XTENSA_INS_AE_MULZAAFD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZAAFD24_HL_LH /* 1161 */, XTENSA_INS_AE_MULZAAFD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD24_HL_LH_S2 /* 1162 */, XTENSA_INS_AE_MULZAAFD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAFD32X16_H0_L1 /* 1163 */, XTENSA_INS_AE_MULZAAFD32X16_H0_L1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD32X16_H0_L1_S2 /* 1164 */, XTENSA_INS_AE_MULZAAFD32X16_H0_L1_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAFD32X16_H1_L0 /* 1165 */, XTENSA_INS_AE_MULZAAFD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD32X16_H1_L0_S2 /* 1166 */, XTENSA_INS_AE_MULZAAFD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAFD32X16_H2_L3 /* 1167 */, XTENSA_INS_AE_MULZAAFD32X16_H2_L3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD32X16_H2_L3_S2 /* 1168 */, XTENSA_INS_AE_MULZAAFD32X16_H2_L3_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZAAFD32X16_H3_L2 /* 1169 */, XTENSA_INS_AE_MULZAAFD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzaafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZAAFD32X16_H3_L2_S2 /* 1170 */, XTENSA_INS_AE_MULZAAFD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZASD24_HH_LL /* 1171 */, XTENSA_INS_AE_MULZASD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZASD24_HH_LL_S2 /* 1172 */, XTENSA_INS_AE_MULZASD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZASD24_HL_LH /* 1173 */, XTENSA_INS_AE_MULZASD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZASD24_HL_LH_S2 /* 1174 */, XTENSA_INS_AE_MULZASD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZASD32X16_H1_L0 /* 1175 */, XTENSA_INS_AE_MULZASD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZASD32X16_H1_L0_S2 /* 1176 */, XTENSA_INS_AE_MULZASD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZASD32X16_H3_L2 /* 1177 */, XTENSA_INS_AE_MULZASD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZASD32X16_H3_L2_S2 /* 1178 */, XTENSA_INS_AE_MULZASD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZASFD24_HH_LL /* 1179 */, XTENSA_INS_AE_MULZASFD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZASFD24_HH_LL_S2 /* 1180 */, XTENSA_INS_AE_MULZASFD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZASFD24_HL_LH /* 1181 */, XTENSA_INS_AE_MULZASFD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZASFD24_HL_LH_S2 /* 1182 */, XTENSA_INS_AE_MULZASFD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZASFD32X16_H1_L0 /* 1183 */, XTENSA_INS_AE_MULZASFD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZASFD32X16_H1_L0_S2 /* 1184 */, XTENSA_INS_AE_MULZASFD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZASFD32X16_H3_L2 /* 1185 */, XTENSA_INS_AE_MULZASFD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzasfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZASFD32X16_H3_L2_S2 /* 1186 */, XTENSA_INS_AE_MULZASFD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZSAD24_HH_LL /* 1187 */, XTENSA_INS_AE_MULZSAD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSAD24_HH_LL_S2 /* 1188 */, XTENSA_INS_AE_MULZSAD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsad32x16.h1.l0 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZSAD32X16_H1_L0 /* 1189 */, XTENSA_INS_AE_MULZSAD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSAD32X16_H1_L0_S2 /* 1190 */, XTENSA_INS_AE_MULZSAD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsad32x16.h3.l2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZSAD32X16_H3_L2 /* 1191 */, XTENSA_INS_AE_MULZSAD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSAD32X16_H3_L2_S2 /* 1192 */, XTENSA_INS_AE_MULZSAD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZSAFD24_HH_LL /* 1193 */, XTENSA_INS_AE_MULZSAFD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSAFD24_HH_LL_S2 /* 1194 */, XTENSA_INS_AE_MULZSAFD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSAFD32X16_H1_L0 /* 1195 */, XTENSA_INS_AE_MULZSAFD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSAFD32X16_H1_L0_S2 /* 1196 */, XTENSA_INS_AE_MULZSAFD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSAFD32X16_H3_L2 /* 1197 */, XTENSA_INS_AE_MULZSAFD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzsafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSAFD32X16_H3_L2_S2 /* 1198 */, XTENSA_INS_AE_MULZSAFD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZSSD24_HH_LL /* 1199 */, XTENSA_INS_AE_MULZSSD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSD24_HH_LL_S2 /* 1200 */, XTENSA_INS_AE_MULZSSD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZSSD24_HL_LH /* 1201 */, XTENSA_INS_AE_MULZSSD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSD24_HL_LH_S2 /* 1202 */, XTENSA_INS_AE_MULZSSD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSSD32X16_H1_L0 /* 1203 */, XTENSA_INS_AE_MULZSSD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSD32X16_H1_L0_S2 /* 1204 */, XTENSA_INS_AE_MULZSSD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSSD32X16_H3_L2 /* 1205 */, XTENSA_INS_AE_MULZSSD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSD32X16_H3_L2_S2 /* 1206 */, XTENSA_INS_AE_MULZSSD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSSFD16SS_11_00 /* 1207 */, XTENSA_INS_AE_MULZSSFD16SS_11_00, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSFD16SS_11_00_S2 /* 1208 */, XTENSA_INS_AE_MULZSSFD16SS_11_00_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSSFD16SS_13_02 /* 1209 */, XTENSA_INS_AE_MULZSSFD16SS_13_02, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSFD16SS_13_02_S2 /* 1210 */, XTENSA_INS_AE_MULZSSFD16SS_13_02_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSSFD16SS_33_22 /* 1211 */, XTENSA_INS_AE_MULZSSFD16SS_33_22, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSFD16SS_33_22_S2 /* 1212 */, XTENSA_INS_AE_MULZSSFD16SS_33_22_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZSSFD24_HH_LL /* 1213 */, XTENSA_INS_AE_MULZSSFD24_HH_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSFD24_HH_LL_S2 /* 1214 */, XTENSA_INS_AE_MULZSSFD24_HH_LL_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ + Xtensa_AE_MULZSSFD24_HL_LH /* 1215 */, XTENSA_INS_AE_MULZSSFD24_HL_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSFD24_HL_LH_S2 /* 1216 */, XTENSA_INS_AE_MULZSSFD24_HL_LH_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSSFD32X16_H1_L0 /* 1217 */, XTENSA_INS_AE_MULZSSFD32X16_H1_L0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSFD32X16_H1_L0_S2 /* 1218 */, XTENSA_INS_AE_MULZSSFD32X16_H1_L0_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ + Xtensa_AE_MULZSSFD32X16_H3_L2 /* 1219 */, XTENSA_INS_AE_MULZSSFD32X16_H3_L2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_mulzssfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ + Xtensa_AE_MULZSSFD32X16_H3_L2_S2 /* 1220 */, XTENSA_INS_AE_MULZSSFD32X16_H3_L2_S2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_nand $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1 */ + Xtensa_AE_NAND /* 1221 */, XTENSA_INS_AE_NAND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_neg16s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_NEG16S /* 1222 */, XTENSA_INS_AE_NEG16S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_neg24s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_NEG24S /* 1223 */, XTENSA_INS_AE_NEG24S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_neg32 $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_NEG32 /* 1224 */, XTENSA_INS_AE_NEG32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_neg32s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_NEG32S /* 1225 */, XTENSA_INS_AE_NEG32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_neg64 $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_NEG64 /* 1226 */, XTENSA_INS_AE_NEG64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_neg64s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_NEG64S /* 1227 */, XTENSA_INS_AE_NEG64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_nsa64 $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_NSA64 /* 1228 */, XTENSA_INS_AE_NSA64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_nsaz16.0 $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_NSAZ16_0 /* 1229 */, XTENSA_INS_AE_NSAZ16_0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_nsaz32.l $arr, $ae_dr_to_ar_v0 */ + Xtensa_AE_NSAZ32_L /* 1230 */, XTENSA_INS_AE_NSAZ32_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_or $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1 */ + Xtensa_AE_OR /* 1231 */, XTENSA_INS_AE_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_pksr24 $ae_pks_d, $ae_pks_s, $ae_imm2 */ + Xtensa_AE_PKSR24 /* 1232 */, XTENSA_INS_AE_PKSR24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_pksr32 $ae_pks_d, $ae_pks_s, $ae_imm2 */ + Xtensa_AE_PKSR32 /* 1233 */, XTENSA_INS_AE_PKSR32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_round16x4f32sasym $ae_arth_v, $ae_arth_v1, $ae_arth_v0 */ + Xtensa_AE_ROUND16X4F32SASYM /* 1234 */, XTENSA_INS_AE_ROUND16X4F32SASYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_round16x4f32ssym $ae_arth_v, $ae_arth_v1, $ae_arth_v0 */ + Xtensa_AE_ROUND16X4F32SSYM /* 1235 */, XTENSA_INS_AE_ROUND16X4F32SSYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_round24x2f48sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ROUND24X2F48SASYM /* 1236 */, XTENSA_INS_AE_ROUND24X2F48SASYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_round24x2f48ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ROUND24X2F48SSYM /* 1237 */, XTENSA_INS_AE_ROUND24X2F48SSYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_round32x2f48sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ROUND32X2F48SASYM /* 1238 */, XTENSA_INS_AE_ROUND32X2F48SASYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_round32x2f48ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ROUND32X2F48SSYM /* 1239 */, XTENSA_INS_AE_ROUND32X2F48SSYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_round32x2f64sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ROUND32X2F64SASYM /* 1240 */, XTENSA_INS_AE_ROUND32X2F64SASYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_round32x2f64ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ROUND32X2F64SSYM /* 1241 */, XTENSA_INS_AE_ROUND32X2F64SSYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_roundsp16f24asym $ae_arth_v, $ae_arth_v0 */ + Xtensa_AE_ROUNDSP16F24ASYM /* 1242 */, XTENSA_INS_AE_ROUNDSP16F24ASYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_roundsp16f24sym $ae_arth_v, $ae_arth_v0 */ + Xtensa_AE_ROUNDSP16F24SYM /* 1243 */, XTENSA_INS_AE_ROUNDSP16F24SYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_roundsp16q48x2asym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ROUNDSP16Q48X2ASYM /* 1244 */, XTENSA_INS_AE_ROUNDSP16Q48X2ASYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_roundsp16q48x2sym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_ROUNDSP16Q48X2SYM /* 1245 */, XTENSA_INS_AE_ROUNDSP16Q48X2SYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_roundsq32f48asym $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_ROUNDSQ32F48ASYM /* 1246 */, XTENSA_INS_AE_ROUNDSQ32F48ASYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_roundsq32f48sym $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_ROUNDSQ32F48SYM /* 1247 */, XTENSA_INS_AE_ROUNDSQ32F48SYM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16m.l.i $ae_ls_v, $ars, $ae_immls16 */ + Xtensa_AE_S16M_L_I /* 1248 */, XTENSA_INS_AE_S16M_L_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16m.l.iu $ae_ls_v, $ars, $ae_immls16 */ + Xtensa_AE_S16M_L_IU /* 1249 */, XTENSA_INS_AE_S16M_L_IU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16m.l.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S16M_L_X /* 1250 */, XTENSA_INS_AE_S16M_L_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16m.l.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S16M_L_XC /* 1251 */, XTENSA_INS_AE_S16M_L_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16m.l.xu $ae_ls_v, $ars, $art */ + Xtensa_AE_S16M_L_XU /* 1252 */, XTENSA_INS_AE_S16M_L_XU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16x2m.i $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_S16X2M_I /* 1253 */, XTENSA_INS_AE_S16X2M_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16x2m.iu $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_S16X2M_IU /* 1254 */, XTENSA_INS_AE_S16X2M_IU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16x2m.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S16X2M_X /* 1255 */, XTENSA_INS_AE_S16X2M_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16x2m.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S16X2M_XC /* 1256 */, XTENSA_INS_AE_S16X2M_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16x2m.xu $ae_ls_v, $ars, $art */ + Xtensa_AE_S16X2M_XU /* 1257 */, XTENSA_INS_AE_S16X2M_XU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16x4.i $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_S16X4_I /* 1258 */, XTENSA_INS_AE_S16X4_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16x4.ip $ae_ls_v, $ars, $ae_immls64pos */ + Xtensa_AE_S16X4_IP /* 1259 */, XTENSA_INS_AE_S16X4_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16x4.ric $ae_ls_v, $ars */ + Xtensa_AE_S16X4_RIC /* 1260 */, XTENSA_INS_AE_S16X4_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16x4.rip $ae_ls_v, $ars */ + Xtensa_AE_S16X4_RIP /* 1261 */, XTENSA_INS_AE_S16X4_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16x4.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S16X4_X /* 1262 */, XTENSA_INS_AE_S16X4_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16x4.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S16X4_XC /* 1263 */, XTENSA_INS_AE_S16X4_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16x4.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_S16X4_XP /* 1264 */, XTENSA_INS_AE_S16X4_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16.0.i $ae_ls_v, $ars, $ae_immls16 */ + Xtensa_AE_S16_0_I /* 1265 */, XTENSA_INS_AE_S16_0_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16.0.ip $ae_ls_v, $ars, $ae_immls16 */ + Xtensa_AE_S16_0_IP /* 1266 */, XTENSA_INS_AE_S16_0_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s16.0.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S16_0_X /* 1267 */, XTENSA_INS_AE_S16_0_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16.0.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S16_0_XC /* 1268 */, XTENSA_INS_AE_S16_0_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s16.0.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_S16_0_XP /* 1269 */, XTENSA_INS_AE_S16_0_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s24ra64s.i $ae_ls_v1, $ars, $ae_immls32 */ + Xtensa_AE_S24RA64S_I /* 1270 */, XTENSA_INS_AE_S24RA64S_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s24ra64s.ip $ae_ls_v1, $ars, $ae_immls32 */ + Xtensa_AE_S24RA64S_IP /* 1271 */, XTENSA_INS_AE_S24RA64S_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s24ra64s.x $ae_ls_v1, $ars, $art */ + Xtensa_AE_S24RA64S_X /* 1272 */, XTENSA_INS_AE_S24RA64S_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s24ra64s.xc $ae_ls_v1, $ars, $art */ + Xtensa_AE_S24RA64S_XC /* 1273 */, XTENSA_INS_AE_S24RA64S_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s24ra64s.xp $ae_ls_v1, $ars, $art */ + Xtensa_AE_S24RA64S_XP /* 1274 */, XTENSA_INS_AE_S24RA64S_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s24x2ra64s.ip $ae_ls_v2, $ae_ls_v1, $ars */ + Xtensa_AE_S24X2RA64S_IP /* 1275 */, XTENSA_INS_AE_S24X2RA64S_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32f24.l.i $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_S32F24_L_I /* 1276 */, XTENSA_INS_AE_S32F24_L_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32f24.l.ip $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_S32F24_L_IP /* 1277 */, XTENSA_INS_AE_S32F24_L_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32f24.l.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S32F24_L_X /* 1278 */, XTENSA_INS_AE_S32F24_L_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32f24.l.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S32F24_L_XC /* 1279 */, XTENSA_INS_AE_S32F24_L_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32f24.l.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_S32F24_L_XP /* 1280 */, XTENSA_INS_AE_S32F24_L_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32m.i $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_S32M_I /* 1281 */, XTENSA_INS_AE_S32M_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32m.iu $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_S32M_IU /* 1282 */, XTENSA_INS_AE_S32M_IU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32m.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S32M_X /* 1283 */, XTENSA_INS_AE_S32M_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32m.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S32M_XC /* 1284 */, XTENSA_INS_AE_S32M_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32m.xu $ae_ls_v, $ars, $art */ + Xtensa_AE_S32M_XU /* 1285 */, XTENSA_INS_AE_S32M_XU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32ra64s.i $ae_ls_v1, $ars, $ae_immls32 */ + Xtensa_AE_S32RA64S_I /* 1286 */, XTENSA_INS_AE_S32RA64S_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32ra64s.ip $ae_ls_v1, $ars, $ae_immls32 */ + Xtensa_AE_S32RA64S_IP /* 1287 */, XTENSA_INS_AE_S32RA64S_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32ra64s.x $ae_ls_v1, $ars, $art */ + Xtensa_AE_S32RA64S_X /* 1288 */, XTENSA_INS_AE_S32RA64S_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32ra64s.xc $ae_ls_v1, $ars, $art */ + Xtensa_AE_S32RA64S_XC /* 1289 */, XTENSA_INS_AE_S32RA64S_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32ra64s.xp $ae_ls_v1, $ars, $art */ + Xtensa_AE_S32RA64S_XP /* 1290 */, XTENSA_INS_AE_S32RA64S_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2f24.i $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_S32X2F24_I /* 1291 */, XTENSA_INS_AE_S32X2F24_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2f24.ip $ae_ls_v, $ars, $ae_immls64pos */ + Xtensa_AE_S32X2F24_IP /* 1292 */, XTENSA_INS_AE_S32X2F24_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2f24.ric $ae_ls_v, $ars */ + Xtensa_AE_S32X2F24_RIC /* 1293 */, XTENSA_INS_AE_S32X2F24_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32x2f24.rip $ae_ls_v, $ars */ + Xtensa_AE_S32X2F24_RIP /* 1294 */, XTENSA_INS_AE_S32X2F24_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32x2f24.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S32X2F24_X /* 1295 */, XTENSA_INS_AE_S32X2F24_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2f24.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S32X2F24_XC /* 1296 */, XTENSA_INS_AE_S32X2F24_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2f24.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_S32X2F24_XP /* 1297 */, XTENSA_INS_AE_S32X2F24_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2ra64s.ip $ae_ls_v2, $ae_ls_v1, $ars */ + Xtensa_AE_S32X2RA64S_IP /* 1298 */, XTENSA_INS_AE_S32X2RA64S_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2.i $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_S32X2_I /* 1299 */, XTENSA_INS_AE_S32X2_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2.ip $ae_ls_v, $ars, $ae_immls64pos */ + Xtensa_AE_S32X2_IP /* 1300 */, XTENSA_INS_AE_S32X2_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2.ric $ae_ls_v, $ars */ + Xtensa_AE_S32X2_RIC /* 1301 */, XTENSA_INS_AE_S32X2_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32x2.rip $ae_ls_v, $ars */ + Xtensa_AE_S32X2_RIP /* 1302 */, XTENSA_INS_AE_S32X2_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32x2.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S32X2_X /* 1303 */, XTENSA_INS_AE_S32X2_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S32X2_XC /* 1304 */, XTENSA_INS_AE_S32X2_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32x2.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_S32X2_XP /* 1305 */, XTENSA_INS_AE_S32X2_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32.l.i $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_S32_L_I /* 1306 */, XTENSA_INS_AE_S32_L_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32.l.ip $ae_ls_v, $ars, $ae_immls32 */ + Xtensa_AE_S32_L_IP /* 1307 */, XTENSA_INS_AE_S32_L_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32.l.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S32_L_X /* 1308 */, XTENSA_INS_AE_S32_L_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s32.l.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S32_L_XC /* 1309 */, XTENSA_INS_AE_S32_L_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s32.l.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_S32_L_XP /* 1310 */, XTENSA_INS_AE_S32_L_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s64.i $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_S64_I /* 1311 */, XTENSA_INS_AE_S64_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s64.ip $ae_ls_v, $ars, $ae_immls64 */ + Xtensa_AE_S64_IP /* 1312 */, XTENSA_INS_AE_S64_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_s64.x $ae_ls_v, $ars, $art */ + Xtensa_AE_S64_X /* 1313 */, XTENSA_INS_AE_S64_X, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s64.xc $ae_ls_v, $ars, $art */ + Xtensa_AE_S64_XC /* 1314 */, XTENSA_INS_AE_S64_XC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_s64.xp $ae_ls_v, $ars, $art */ + Xtensa_AE_S64_XP /* 1315 */, XTENSA_INS_AE_S64_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa16x4.ic $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA16X4_IC /* 1316 */, XTENSA_INS_AE_SA16X4_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa16x4.ip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA16X4_IP /* 1317 */, XTENSA_INS_AE_SA16X4_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sa16x4.ric $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA16X4_RIC /* 1318 */, XTENSA_INS_AE_SA16X4_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa16x4.rip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA16X4_RIP /* 1319 */, XTENSA_INS_AE_SA16X4_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa24x2.ic $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA24X2_IC /* 1320 */, XTENSA_INS_AE_SA24X2_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa24x2.ip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA24X2_IP /* 1321 */, XTENSA_INS_AE_SA24X2_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa24x2.ric $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA24X2_RIC /* 1322 */, XTENSA_INS_AE_SA24X2_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa24x2.rip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA24X2_RIP /* 1323 */, XTENSA_INS_AE_SA24X2_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa24.l.ic $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA24_L_IC /* 1324 */, XTENSA_INS_AE_SA24_L_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa24.l.ip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA24_L_IP /* 1325 */, XTENSA_INS_AE_SA24_L_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa24.l.ric $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA24_L_RIC /* 1326 */, XTENSA_INS_AE_SA24_L_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa24.l.rip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA24_L_RIP /* 1327 */, XTENSA_INS_AE_SA24_L_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa32x2f24.ic $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA32X2F24_IC /* 1328 */, XTENSA_INS_AE_SA32X2F24_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa32x2f24.ip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA32X2F24_IP /* 1329 */, XTENSA_INS_AE_SA32X2F24_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sa32x2f24.ric $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA32X2F24_RIC /* 1330 */, XTENSA_INS_AE_SA32X2F24_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa32x2f24.rip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA32X2F24_RIP /* 1331 */, XTENSA_INS_AE_SA32X2F24_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa32x2.ic $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA32X2_IC /* 1332 */, XTENSA_INS_AE_SA32X2_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa32x2.ip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA32X2_IP /* 1333 */, XTENSA_INS_AE_SA32X2_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sa32x2.ric $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA32X2_RIC /* 1334 */, XTENSA_INS_AE_SA32X2_RIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa32x2.rip $ae_ls_v, $ae_ls_su, $ars */ + Xtensa_AE_SA32X2_RIP /* 1335 */, XTENSA_INS_AE_SA32X2_RIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa64neg.fp $ae_ls_su, $ars */ + Xtensa_AE_SA64NEG_FP /* 1336 */, XTENSA_INS_AE_SA64NEG_FP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sa64pos.fp $ae_ls_su, $ars */ + Xtensa_AE_SA64POS_FP /* 1337 */, XTENSA_INS_AE_SA64POS_FP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_salign64.i $ae_ls_su, $ars, $ae_immls64 */ + Xtensa_AE_SALIGN64_I /* 1338 */, XTENSA_INS_AE_SALIGN64_I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sat16x4 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SAT16X4 /* 1339 */, XTENSA_INS_AE_SAT16X4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sat24s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_SAT24S /* 1340 */, XTENSA_INS_AE_SAT24S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sat48s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_SAT48S /* 1341 */, XTENSA_INS_AE_SAT48S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_satq56s $ae_arth_v, $ae_arth_v1 */ + Xtensa_AE_SATQ56S /* 1342 */, XTENSA_INS_AE_SATQ56S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sb $ars, $art */ + Xtensa_AE_SB /* 1343 */, XTENSA_INS_AE_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sbf $ars */ + Xtensa_AE_SBF /* 1344 */, XTENSA_INS_AE_SBF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sbf.ic $ars */ + Xtensa_AE_SBF_IC /* 1345 */, XTENSA_INS_AE_SBF_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sbf.ip $ars */ + Xtensa_AE_SBF_IP /* 1346 */, XTENSA_INS_AE_SBF_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sbi $ars, $art, $ae_ohba2 */ + Xtensa_AE_SBI /* 1347 */, XTENSA_INS_AE_SBI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sbi.ic $ars, $art, $ae_ohba2 */ + Xtensa_AE_SBI_IC /* 1348 */, XTENSA_INS_AE_SBI_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sbi.ip $ars, $art, $ae_ohba2 */ + Xtensa_AE_SBI_IP /* 1349 */, XTENSA_INS_AE_SBI_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sb.ic $ars, $art */ + Xtensa_AE_SB_IC /* 1350 */, XTENSA_INS_AE_SB_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sb.ip $ars, $art */ + Xtensa_AE_SB_IP /* 1351 */, XTENSA_INS_AE_SB_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sel16i $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1, $ae_selimm */ + Xtensa_AE_SEL16I /* 1352 */, XTENSA_INS_AE_SEL16I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sel16i.n $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1, $ae_selimm_N */ + Xtensa_AE_SEL16I_N /* 1353 */, XTENSA_INS_AE_SEL16I_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sext32 $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_opnd_tp7 */ + Xtensa_AE_SEXT32 /* 1354 */, XTENSA_INS_AE_SEXT32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sext32x2d16.10 $ae_to_dr_v, $ae_to_dr_v0 */ + Xtensa_AE_SEXT32X2D16_10 /* 1355 */, XTENSA_INS_AE_SEXT32X2D16_10, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sext32x2d16.32 $ae_to_dr_v, $ae_to_dr_v0 */ + Xtensa_AE_SEXT32X2D16_32 /* 1356 */, XTENSA_INS_AE_SEXT32X2D16_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sha32 $arr, $ars */ + Xtensa_AE_SHA32 /* 1357 */, XTENSA_INS_AE_SHA32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_shortswap $ae_to_dr_v, $ae_to_dr_v0 */ + Xtensa_AE_SHORTSWAP /* 1358 */, XTENSA_INS_AE_SHORTSWAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_slaa16s $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SLAA16S /* 1359 */, XTENSA_INS_AE_SLAA16S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slaa32 $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SLAA32 /* 1360 */, XTENSA_INS_AE_SLAA32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slaa32s $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SLAA32S /* 1361 */, XTENSA_INS_AE_SLAA32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slaa64 $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SLAA64 /* 1362 */, XTENSA_INS_AE_SLAA64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slaa64s $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SLAA64S /* 1363 */, XTENSA_INS_AE_SLAA64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_slaaq56 $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SLAAQ56 /* 1364 */, XTENSA_INS_AE_SLAAQ56, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slai16s $ae_shift_d, $ae_shift_d0, $ae_osa16 */ + Xtensa_AE_SLAI16S /* 1365 */, XTENSA_INS_AE_SLAI16S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_slai24 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SLAI24 /* 1366 */, XTENSA_INS_AE_SLAI24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slai24s $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SLAI24S /* 1367 */, XTENSA_INS_AE_SLAI24S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slai32 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SLAI32 /* 1368 */, XTENSA_INS_AE_SLAI32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slai32s $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SLAI32S /* 1369 */, XTENSA_INS_AE_SLAI32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slai64 $ae_shift_d, $ae_shift_d0, $ae_osa64 */ + Xtensa_AE_SLAI64 /* 1370 */, XTENSA_INS_AE_SLAI64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slai64s $ae_shift_d, $ae_shift_d0, $ae_osa64 */ + Xtensa_AE_SLAI64S /* 1371 */, XTENSA_INS_AE_SLAI64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_slaisq56s $ae_shift_d, $ae_shift_d0, $ae_osa64 */ + Xtensa_AE_SLAISQ56S /* 1372 */, XTENSA_INS_AE_SLAISQ56S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slas24 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SLAS24 /* 1373 */, XTENSA_INS_AE_SLAS24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slas24s $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SLAS24S /* 1374 */, XTENSA_INS_AE_SLAS24S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_slas32 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SLAS32 /* 1375 */, XTENSA_INS_AE_SLAS32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_slas32s $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SLAS32S /* 1376 */, XTENSA_INS_AE_SLAS32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_slas64 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SLAS64 /* 1377 */, XTENSA_INS_AE_SLAS64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_slas64s $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SLAS64S /* 1378 */, XTENSA_INS_AE_SLAS64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slasq56 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SLASQ56 /* 1379 */, XTENSA_INS_AE_SLASQ56, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_slassq56s $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SLASSQ56S /* 1380 */, XTENSA_INS_AE_SLASSQ56S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sra64_32 $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRA64_32 /* 1381 */, XTENSA_INS_AE_SRA64_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sraa16rs $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRAA16RS /* 1382 */, XTENSA_INS_AE_SRAA16RS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sraa16s $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRAA16S /* 1383 */, XTENSA_INS_AE_SRAA16S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sraa32 $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRAA32 /* 1384 */, XTENSA_INS_AE_SRAA32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sraa32rs $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRAA32RS /* 1385 */, XTENSA_INS_AE_SRAA32RS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sraa32s $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRAA32S /* 1386 */, XTENSA_INS_AE_SRAA32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sraa64 $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRAA64 /* 1387 */, XTENSA_INS_AE_SRAA64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_srai16 $ae_shift_d, $ae_shift_d0, $ae_osa16 */ + Xtensa_AE_SRAI16 /* 1388 */, XTENSA_INS_AE_SRAI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srai16r $ae_shift_d, $ae_shift_d0, $ae_osa16 */ + Xtensa_AE_SRAI16R /* 1389 */, XTENSA_INS_AE_SRAI16R, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srai24 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SRAI24 /* 1390 */, XTENSA_INS_AE_SRAI24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_srai32 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SRAI32 /* 1391 */, XTENSA_INS_AE_SRAI32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_srai32r $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SRAI32R /* 1392 */, XTENSA_INS_AE_SRAI32R, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srai64 $ae_shift_d, $ae_shift_d0, $ae_osa64 */ + Xtensa_AE_SRAI64 /* 1393 */, XTENSA_INS_AE_SRAI64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sras24 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SRAS24 /* 1394 */, XTENSA_INS_AE_SRAS24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sras32 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SRAS32 /* 1395 */, XTENSA_INS_AE_SRAS32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sras64 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SRAS64 /* 1396 */, XTENSA_INS_AE_SRAS64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srla32 $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRLA32 /* 1397 */, XTENSA_INS_AE_SRLA32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srla64 $ae_shift_d, $ae_shift_d0, $ars */ + Xtensa_AE_SRLA64 /* 1398 */, XTENSA_INS_AE_SRLA64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srli24 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SRLI24 /* 1399 */, XTENSA_INS_AE_SRLI24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srli32 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ + Xtensa_AE_SRLI32 /* 1400 */, XTENSA_INS_AE_SRLI32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_srli64 $ae_shift_d, $ae_shift_d0, $ae_osa64 */ + Xtensa_AE_SRLI64 /* 1401 */, XTENSA_INS_AE_SRLI64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srls24 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SRLS24 /* 1402 */, XTENSA_INS_AE_SRLS24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srls32 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SRLS32 /* 1403 */, XTENSA_INS_AE_SRLS32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_srls64 $ae_shift_d, $ae_shift_d0 */ + Xtensa_AE_SRLS64 /* 1404 */, XTENSA_INS_AE_SRLS64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sub16 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUB16 /* 1405 */, XTENSA_INS_AE_SUB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sub16s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUB16S /* 1406 */, XTENSA_INS_AE_SUB16S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sub24s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUB24S /* 1407 */, XTENSA_INS_AE_SUB24S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_sub32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUB32 /* 1408 */, XTENSA_INS_AE_SUB32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sub32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUB32S /* 1409 */, XTENSA_INS_AE_SUB32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sub64 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUB64 /* 1410 */, XTENSA_INS_AE_SUB64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_sub64s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUB64S /* 1411 */, XTENSA_INS_AE_SUB64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_subadd32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUBADD32 /* 1412 */, XTENSA_INS_AE_SUBADD32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_subadd32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ + Xtensa_AE_SUBADD32S /* 1413 */, XTENSA_INS_AE_SUBADD32S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_trunca32f64s.l $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ars */ + Xtensa_AE_TRUNCA32F64S_L /* 1414 */, XTENSA_INS_AE_TRUNCA32F64S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_trunca32x2f64s $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ars */ + Xtensa_AE_TRUNCA32X2F64S /* 1415 */, XTENSA_INS_AE_TRUNCA32X2F64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_trunci32f64s.l $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ae_osa16 */ + Xtensa_AE_TRUNCI32F64S_L /* 1416 */, XTENSA_INS_AE_TRUNCI32F64S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_trunci32x2f64s $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ae_osa16 */ + Xtensa_AE_TRUNCI32X2F64S /* 1417 */, XTENSA_INS_AE_TRUNCI32X2F64S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ae_vldl16c $ars */ + Xtensa_AE_VLDL16C /* 1418 */, XTENSA_INS_AE_VLDL16C, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vldl16c.ic $ars */ + Xtensa_AE_VLDL16C_IC /* 1419 */, XTENSA_INS_AE_VLDL16C_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vldl16c.ip $ars */ + Xtensa_AE_VLDL16C_IP /* 1420 */, XTENSA_INS_AE_VLDL16C_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vldl16t $br, $art, $ars */ + Xtensa_AE_VLDL16T /* 1421 */, XTENSA_INS_AE_VLDL16T, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vldl32t $br, $art, $ars */ + Xtensa_AE_VLDL32T /* 1422 */, XTENSA_INS_AE_VLDL32T, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vldsht $art */ + Xtensa_AE_VLDSHT /* 1423 */, XTENSA_INS_AE_VLDSHT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vlel16t $br, $art, $ars */ + Xtensa_AE_VLEL16T /* 1424 */, XTENSA_INS_AE_VLEL16T, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vlel32t $br, $art, $ars */ + Xtensa_AE_VLEL32T /* 1425 */, XTENSA_INS_AE_VLEL32T, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vles16c $ars */ + Xtensa_AE_VLES16C /* 1426 */, XTENSA_INS_AE_VLES16C, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vles16c.ic $ars */ + Xtensa_AE_VLES16C_IC /* 1427 */, XTENSA_INS_AE_VLES16C_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_vles16c.ip $ars */ + Xtensa_AE_VLES16C_IP /* 1428 */, XTENSA_INS_AE_VLES16C_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_xor $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1 */ + Xtensa_AE_XOR /* 1429 */, XTENSA_INS_AE_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* ae_zalign64 $ae_uu_uu */ + Xtensa_AE_ZALIGN64 /* 1430 */, XTENSA_INS_AE_ZALIGN64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* all4 $t, $s */ + Xtensa_ALL4 /* 1431 */, XTENSA_INS_ALL4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* all8 $t, $s */ + Xtensa_ALL8 /* 1432 */, XTENSA_INS_ALL8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* and $r, $s, $t */ + Xtensa_AND /* 1433 */, XTENSA_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* andb $r, $s, $t */ + Xtensa_ANDB /* 1434 */, XTENSA_INS_ANDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* andbc $r, $s, $t */ + Xtensa_ANDBC /* 1435 */, XTENSA_INS_ANDBC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* any4 $t, $s */ + Xtensa_ANY4 /* 1436 */, XTENSA_INS_ANY4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* any8 $t, $s */ + Xtensa_ANY8 /* 1437 */, XTENSA_INS_ANY8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ball $s, $t, $target */ + Xtensa_BALL /* 1438 */, XTENSA_INS_BALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bany $s, $t, $target */ + Xtensa_BANY /* 1439 */, XTENSA_INS_BANY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bbc $s, $t, $target */ + Xtensa_BBC /* 1440 */, XTENSA_INS_BBC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bbci $s, $imm, $target */ + Xtensa_BBCI /* 1441 */, XTENSA_INS_BBCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bbs $s, $t, $target */ + Xtensa_BBS /* 1442 */, XTENSA_INS_BBS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bbsi $s, $imm, $target */ + Xtensa_BBSI /* 1443 */, XTENSA_INS_BBSI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* beq $s, $t, $target */ + Xtensa_BEQ /* 1444 */, XTENSA_INS_BEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* beqi $s, $imm, $target */ + Xtensa_BEQI /* 1445 */, XTENSA_INS_BEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* beqz $s, $target */ + Xtensa_BEQZ /* 1446 */, XTENSA_INS_BEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_BRI12 }} + + #endif +}, +{ + /* bf $b, $target */ + Xtensa_BF /* 1447 */, XTENSA_INS_BF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, XTENSA_FEATURE_HASBOOLEAN, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bge $s, $t, $target */ + Xtensa_BGE /* 1448 */, XTENSA_INS_BGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bgei $s, $imm, $target */ + Xtensa_BGEI /* 1449 */, XTENSA_INS_BGEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bgeu $s, $t, $target */ + Xtensa_BGEU /* 1450 */, XTENSA_INS_BGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bgeui $s, $imm, $target */ + Xtensa_BGEUI /* 1451 */, XTENSA_INS_BGEUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bgez $s, $target */ + Xtensa_BGEZ /* 1452 */, XTENSA_INS_BGEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_BRI12 }} + + #endif +}, +{ + /* blt $s, $t, $target */ + Xtensa_BLT /* 1453 */, XTENSA_INS_BLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* blti $s, $imm, $target */ + Xtensa_BLTI /* 1454 */, XTENSA_INS_BLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bltu $s, $t, $target */ + Xtensa_BLTU /* 1455 */, XTENSA_INS_BLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bltui $s, $imm, $target */ + Xtensa_BLTUI /* 1456 */, XTENSA_INS_BLTUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bltz $s, $target */ + Xtensa_BLTZ /* 1457 */, XTENSA_INS_BLTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_BRI12 }} + + #endif +}, +{ + /* bnall $s, $t, $target */ + Xtensa_BNALL /* 1458 */, XTENSA_INS_BNALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bne $s, $t, $target */ + Xtensa_BNE /* 1459 */, XTENSA_INS_BNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bnei $s, $imm, $target */ + Xtensa_BNEI /* 1460 */, XTENSA_INS_BNEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* bnez $s, $target */ + Xtensa_BNEZ /* 1461 */, XTENSA_INS_BNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_BRI12 }} + + #endif +}, +{ + /* bnone $s, $t, $target */ + Xtensa_BNONE /* 1462 */, XTENSA_INS_BNONE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* break $s, $t */ + Xtensa_BREAK /* 1463 */, XTENSA_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDEBUG, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* break.n $imm */ + Xtensa_BREAK_N /* 1464 */, XTENSA_INS_BREAK_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, XTENSA_FEATURE_HASDEBUG, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* bt $b, $target */ + Xtensa_BT /* 1465 */, XTENSA_INS_BT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, XTENSA_FEATURE_HASBOOLEAN, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* call0 $offset */ + Xtensa_CALL0 /* 1466 */, XTENSA_INS_CALL0, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALL }} + + #endif +}, +{ + /* call12 $offset */ + Xtensa_CALL12 /* 1467 */, XTENSA_INS_CALL12, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALL }} + + #endif +}, +{ + /* call4 $offset */ + Xtensa_CALL4 /* 1468 */, XTENSA_INS_CALL4, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALL }} + + #endif +}, +{ + /* call8 $offset */ + Xtensa_CALL8 /* 1469 */, XTENSA_INS_CALL8, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALL }} + + #endif +}, +{ + /* callx0 $s */ + Xtensa_CALLX0 /* 1470 */, XTENSA_INS_CALLX0, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALLX }} + + #endif +}, +{ + /* callx12 $s */ + Xtensa_CALLX12 /* 1471 */, XTENSA_INS_CALLX12, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALLX }} + + #endif +}, +{ + /* callx4 $s */ + Xtensa_CALLX4 /* 1472 */, XTENSA_INS_CALLX4, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALLX }} + + #endif +}, +{ + /* callx8 $s */ + Xtensa_CALLX8 /* 1473 */, XTENSA_INS_CALLX8, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALLX }} + + #endif +}, +{ + /* ceil.s $r, $s, $imm */ + Xtensa_CEIL_S /* 1474 */, XTENSA_INS_CEIL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* clamps $r, $s, $imm */ + Xtensa_CLAMPS /* 1475 */, XTENSA_INS_CLAMPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASCLAMPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* clr_bit_gpio_out $imm */ + Xtensa_CLR_BIT_GPIO_OUT /* 1476 */, XTENSA_INS_CLR_BIT_GPIO_OUT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S2OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* const.s $r, $imm */ + Xtensa_CONST_S /* 1477 */, XTENSA_INS_CONST_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* div0.s $r, $s */ + Xtensa_DIV0_S /* 1478 */, XTENSA_INS_DIV0_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* divn.s $r, $s, $t */ + Xtensa_DIVN_S /* 1479 */, XTENSA_INS_DIVN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* dsync */ + Xtensa_DSYNC /* 1480 */, XTENSA_INS_DSYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ee.andq $qa, $qx, $qy */ + Xtensa_EE_ANDQ /* 1481 */, XTENSA_INS_EE_ANDQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.bitrev $qa, $ax */ + Xtensa_EE_BITREV /* 1482 */, XTENSA_INS_EE_BITREV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.clr_bit_gpio_out $imm */ + Xtensa_EE_CLR_BIT_GPIO_OUT /* 1483 */, XTENSA_INS_EE_CLR_BIT_GPIO_OUT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ee.cmul.s16 $qz, $qx, $qy, $sel4 */ + Xtensa_EE_CMUL_S16 /* 1484 */, XTENSA_INS_EE_CMUL_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.cmul.s16.ld.incp $qu, $as, $qz, $qx, $qy, $sel4 */ + Xtensa_EE_CMUL_S16_LD_INCP /* 1485 */, XTENSA_INS_EE_CMUL_S16_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.cmul.s16.st.incp $qv, $as, $qz, $qx, $qy, $sel4 */ + Xtensa_EE_CMUL_S16_ST_INCP /* 1486 */, XTENSA_INS_EE_CMUL_S16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.fft.ams.s16.ld.incp $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + Xtensa_EE_FFT_AMS_S16_LD_INCP /* 1487 */, XTENSA_INS_EE_FFT_AMS_S16_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.fft.ams.s16.ld.incp.uaup $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + Xtensa_EE_FFT_AMS_S16_LD_INCP_UAUP /* 1488 */, XTENSA_INS_EE_FFT_AMS_S16_LD_INCP_UAUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.fft.ams.s16.ld.r32.decp $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + Xtensa_EE_FFT_AMS_S16_LD_R32_DECP /* 1489 */, XTENSA_INS_EE_FFT_AMS_S16_LD_R32_DECP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.fft.ams.s16.st.incp $qv, $qz1, $as0, $as, $qx, $qy, $qm, $sel2 */ + Xtensa_EE_FFT_AMS_S16_ST_INCP /* 1490 */, XTENSA_INS_EE_FFT_AMS_S16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.fft.cmul.s16.ld.xp $qu, $as, $ad, $qz, $qx, $qy, $sel8 */ + Xtensa_EE_FFT_CMUL_S16_LD_XP /* 1491 */, XTENSA_INS_EE_FFT_CMUL_S16_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.fft.cmul.s16.st.xp $qx, $qy, $qv, $as, $ad, $sel8, $upd4, $sar4 */ + Xtensa_EE_FFT_CMUL_S16_ST_XP /* 1492 */, XTENSA_INS_EE_FFT_CMUL_S16_ST_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.fft.r2bf.s16 $qa0, $qa1, $qx, $qy, $sel2 */ + Xtensa_EE_FFT_R2BF_S16 /* 1493 */, XTENSA_INS_EE_FFT_R2BF_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.fft.r2bf.s16.st.incp $qa0, $qx, $qy, $as, $sar4 */ + Xtensa_EE_FFT_R2BF_S16_ST_INCP /* 1494 */, XTENSA_INS_EE_FFT_R2BF_S16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.fft.vst.r32.decp $qv, $as, $sar2 */ + Xtensa_EE_FFT_VST_R32_DECP /* 1495 */, XTENSA_INS_EE_FFT_VST_R32_DECP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.get_gpio_in $t */ + Xtensa_EE_GET_GPIO_IN /* 1496 */, XTENSA_INS_EE_GET_GPIO_IN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ee.ldf.128.ip $fu3, $fu2, $fu1, $fu0, $as, $imm16f */ + Xtensa_EE_LDF_128_IP /* 1497 */, XTENSA_INS_EE_LDF_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.ldf.128.xp $fu3, $fu2, $fu1, $fu0, $as, $ad */ + Xtensa_EE_LDF_128_XP /* 1498 */, XTENSA_INS_EE_LDF_128_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.ldf.64.ip $fu1, $fu0, $as, $imm8 */ + Xtensa_EE_LDF_64_IP /* 1499 */, XTENSA_INS_EE_LDF_64_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.ldf.64.xp $fu1, $fu0, $as, $ad */ + Xtensa_EE_LDF_64_XP /* 1500 */, XTENSA_INS_EE_LDF_64_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldqa.s16.128.ip $as, $imm16 */ + Xtensa_EE_LDQA_S16_128_IP /* 1501 */, XTENSA_INS_EE_LDQA_S16_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldqa.s16.128.xp $as, $ad */ + Xtensa_EE_LDQA_S16_128_XP /* 1502 */, XTENSA_INS_EE_LDQA_S16_128_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldqa.s8.128.ip $as, $imm16 */ + Xtensa_EE_LDQA_S8_128_IP /* 1503 */, XTENSA_INS_EE_LDQA_S8_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldqa.s8.128.xp $as, $ad */ + Xtensa_EE_LDQA_S8_128_XP /* 1504 */, XTENSA_INS_EE_LDQA_S8_128_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldqa.u16.128.ip $as, $imm16 */ + Xtensa_EE_LDQA_U16_128_IP /* 1505 */, XTENSA_INS_EE_LDQA_U16_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldqa.u16.128.xp $as, $ad */ + Xtensa_EE_LDQA_U16_128_XP /* 1506 */, XTENSA_INS_EE_LDQA_U16_128_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldqa.u8.128.ip $as, $imm16 */ + Xtensa_EE_LDQA_U8_128_IP /* 1507 */, XTENSA_INS_EE_LDQA_U8_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldqa.u8.128.xp $as, $ad */ + Xtensa_EE_LDQA_U8_128_XP /* 1508 */, XTENSA_INS_EE_LDQA_U8_128_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ldxq.32 $qu, $qs, $as, $sel4, $sel8 */ + Xtensa_EE_LDXQ_32 /* 1509 */, XTENSA_INS_EE_LDXQ_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.ld.128.usar.ip $qu, $as, $imm16 */ + Xtensa_EE_LD_128_USAR_IP /* 1510 */, XTENSA_INS_EE_LD_128_USAR_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ld.128.usar.xp $qu, $as, $ad */ + Xtensa_EE_LD_128_USAR_XP /* 1511 */, XTENSA_INS_EE_LD_128_USAR_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ld.accx.ip $as, $imm8 */ + Xtensa_EE_LD_ACCX_IP /* 1512 */, XTENSA_INS_EE_LD_ACCX_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ld.qacc_h.h.32.ip $as, $imm4 */ + Xtensa_EE_LD_QACC_H_H_32_IP /* 1513 */, XTENSA_INS_EE_LD_QACC_H_H_32_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ld.qacc_h.l.128.ip $as, $imm16 */ + Xtensa_EE_LD_QACC_H_L_128_IP /* 1514 */, XTENSA_INS_EE_LD_QACC_H_L_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ld.qacc_l.h.32.ip $as, $imm4 */ + Xtensa_EE_LD_QACC_L_H_32_IP /* 1515 */, XTENSA_INS_EE_LD_QACC_L_H_32_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ld.qacc_l.l.128.ip $as, $imm16 */ + Xtensa_EE_LD_QACC_L_L_128_IP /* 1516 */, XTENSA_INS_EE_LD_QACC_L_L_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.ld.ua_state.ip $as, $imm16 */ + Xtensa_EE_LD_UA_STATE_IP /* 1517 */, XTENSA_INS_EE_LD_UA_STATE_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.movi.32.a $qs, $au, $sel4 */ + Xtensa_EE_MOVI_32_A /* 1518 */, XTENSA_INS_EE_MOVI_32_A, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.movi.32.q $qu, $as, $sel4 */ + Xtensa_EE_MOVI_32_Q /* 1519 */, XTENSA_INS_EE_MOVI_32_Q, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.mov.s16.qacc $qs */ + Xtensa_EE_MOV_S16_QACC /* 1520 */, XTENSA_INS_EE_MOV_S16_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.mov.s8.qacc $qs */ + Xtensa_EE_MOV_S8_QACC /* 1521 */, XTENSA_INS_EE_MOV_S8_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.mov.u16.qacc $qs */ + Xtensa_EE_MOV_U16_QACC /* 1522 */, XTENSA_INS_EE_MOV_U16_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.mov.u8.qacc $qs */ + Xtensa_EE_MOV_U8_QACC /* 1523 */, XTENSA_INS_EE_MOV_U8_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.notq $qa, $qx */ + Xtensa_EE_NOTQ /* 1524 */, XTENSA_INS_EE_NOTQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.orq $qa, $qx, $qy */ + Xtensa_EE_ORQ /* 1525 */, XTENSA_INS_EE_ORQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.set_bit_gpio_out $imm */ + Xtensa_EE_SET_BIT_GPIO_OUT /* 1526 */, XTENSA_INS_EE_SET_BIT_GPIO_OUT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ee.slci.2q $qs1, $qs0, $sar16 */ + Xtensa_EE_SLCI_2Q /* 1527 */, XTENSA_INS_EE_SLCI_2Q, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.slcxxp.2q $qs1, $qs0, $as, $ad */ + Xtensa_EE_SLCXXP_2Q /* 1528 */, XTENSA_INS_EE_SLCXXP_2Q, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.srci.2q $qs1, $qs0, $sar16 */ + Xtensa_EE_SRCI_2Q /* 1529 */, XTENSA_INS_EE_SRCI_2Q, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.srcmb.s16.qacc $qu, $as, $sel2 */ + Xtensa_EE_SRCMB_S16_QACC /* 1530 */, XTENSA_INS_EE_SRCMB_S16_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.srcmb.s8.qacc $qu, $as, $sel2 */ + Xtensa_EE_SRCMB_S8_QACC /* 1531 */, XTENSA_INS_EE_SRCMB_S8_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.srcq.128.st.incp $qs0, $qs1, $as */ + Xtensa_EE_SRCQ_128_ST_INCP /* 1532 */, XTENSA_INS_EE_SRCQ_128_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.srcxxp.2q $qs1, $qs0, $as, $ad */ + Xtensa_EE_SRCXXP_2Q /* 1533 */, XTENSA_INS_EE_SRCXXP_2Q, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.src.q $qa, $qs0, $qs1 */ + Xtensa_EE_SRC_Q /* 1534 */, XTENSA_INS_EE_SRC_Q, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.src.q.ld.ip $qu, $as, $imm16, $qs0, $qs1 */ + Xtensa_EE_SRC_Q_LD_IP /* 1535 */, XTENSA_INS_EE_SRC_Q_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.src.q.ld.xp $qu, $as, $ad, $qs0, $qs1 */ + Xtensa_EE_SRC_Q_LD_XP /* 1536 */, XTENSA_INS_EE_SRC_Q_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.src.q.qup $qa, $qs0, $qs1 */ + Xtensa_EE_SRC_Q_QUP /* 1537 */, XTENSA_INS_EE_SRC_Q_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.srs.accx $au, $as, $sel2 */ + Xtensa_EE_SRS_ACCX /* 1538 */, XTENSA_INS_EE_SRS_ACCX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.stf.128.ip $fv3, $fv2, $fv1, $fv0, $as, $imm16f */ + Xtensa_EE_STF_128_IP /* 1539 */, XTENSA_INS_EE_STF_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.stf.128.xp $fv3, $fv2, $fv1, $fv0, $as, $ad */ + Xtensa_EE_STF_128_XP /* 1540 */, XTENSA_INS_EE_STF_128_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.stf.64.ip $fv1, $fv0, $as, $imm8 */ + Xtensa_EE_STF_64_IP /* 1541 */, XTENSA_INS_EE_STF_64_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.stf.64.xp $fv1, $fv0, $as, $ad */ + Xtensa_EE_STF_64_XP /* 1542 */, XTENSA_INS_EE_STF_64_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.stxq.32 $qv, $qs, $as, $sel4, $sel8 */ + Xtensa_EE_STXQ_32 /* 1543 */, XTENSA_INS_EE_STXQ_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.st.accx.ip $as, $imm8 */ + Xtensa_EE_ST_ACCX_IP /* 1544 */, XTENSA_INS_EE_ST_ACCX_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.st.qacc_h.h.32.ip $as, $imm4 */ + Xtensa_EE_ST_QACC_H_H_32_IP /* 1545 */, XTENSA_INS_EE_ST_QACC_H_H_32_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.st.qacc_h.l.128.ip $as, $imm16 */ + Xtensa_EE_ST_QACC_H_L_128_IP /* 1546 */, XTENSA_INS_EE_ST_QACC_H_L_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.st.qacc_l.h.32.ip $as, $imm4 */ + Xtensa_EE_ST_QACC_L_H_32_IP /* 1547 */, XTENSA_INS_EE_ST_QACC_L_H_32_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.st.qacc_l.l.128.ip $as, $imm16 */ + Xtensa_EE_ST_QACC_L_L_128_IP /* 1548 */, XTENSA_INS_EE_ST_QACC_L_L_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.st.ua_state.ip $as, $imm16 */ + Xtensa_EE_ST_UA_STATE_IP /* 1549 */, XTENSA_INS_EE_ST_UA_STATE_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vadds.s16 $qa, $qx, $qy */ + Xtensa_EE_VADDS_S16 /* 1550 */, XTENSA_INS_EE_VADDS_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vadds.s16.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S16_LD_INCP /* 1551 */, XTENSA_INS_EE_VADDS_S16_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vadds.s16.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S16_ST_INCP /* 1552 */, XTENSA_INS_EE_VADDS_S16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vadds.s32 $qa, $qx, $qy */ + Xtensa_EE_VADDS_S32 /* 1553 */, XTENSA_INS_EE_VADDS_S32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vadds.s32.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S32_LD_INCP /* 1554 */, XTENSA_INS_EE_VADDS_S32_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vadds.s32.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S32_ST_INCP /* 1555 */, XTENSA_INS_EE_VADDS_S32_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vadds.s8 $qa, $qx, $qy */ + Xtensa_EE_VADDS_S8 /* 1556 */, XTENSA_INS_EE_VADDS_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vadds.s8.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S8_LD_INCP /* 1557 */, XTENSA_INS_EE_VADDS_S8_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vadds.s8.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VADDS_S8_ST_INCP /* 1558 */, XTENSA_INS_EE_VADDS_S8_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vcmp.eq.s16 $qa, $qx, $qy */ + Xtensa_EE_VCMP_EQ_S16 /* 1559 */, XTENSA_INS_EE_VCMP_EQ_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vcmp.eq.s32 $qa, $qx, $qy */ + Xtensa_EE_VCMP_EQ_S32 /* 1560 */, XTENSA_INS_EE_VCMP_EQ_S32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vcmp.eq.s8 $qa, $qx, $qy */ + Xtensa_EE_VCMP_EQ_S8 /* 1561 */, XTENSA_INS_EE_VCMP_EQ_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vcmp.gt.s16 $qa, $qx, $qy */ + Xtensa_EE_VCMP_GT_S16 /* 1562 */, XTENSA_INS_EE_VCMP_GT_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vcmp.gt.s32 $qa, $qx, $qy */ + Xtensa_EE_VCMP_GT_S32 /* 1563 */, XTENSA_INS_EE_VCMP_GT_S32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vcmp.gt.s8 $qa, $qx, $qy */ + Xtensa_EE_VCMP_GT_S8 /* 1564 */, XTENSA_INS_EE_VCMP_GT_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vcmp.lt.s16 $qa, $qx, $qy */ + Xtensa_EE_VCMP_LT_S16 /* 1565 */, XTENSA_INS_EE_VCMP_LT_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vcmp.lt.s32 $qa, $qx, $qy */ + Xtensa_EE_VCMP_LT_S32 /* 1566 */, XTENSA_INS_EE_VCMP_LT_S32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vcmp.lt.s8 $qa, $qx, $qy */ + Xtensa_EE_VCMP_LT_S8 /* 1567 */, XTENSA_INS_EE_VCMP_LT_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.16 $qu, $as */ + Xtensa_EE_VLDBC_16 /* 1568 */, XTENSA_INS_EE_VLDBC_16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.16.ip $qu, $as, $imm2 */ + Xtensa_EE_VLDBC_16_IP /* 1569 */, XTENSA_INS_EE_VLDBC_16_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.16.xp $qu, $as, $ad */ + Xtensa_EE_VLDBC_16_XP /* 1570 */, XTENSA_INS_EE_VLDBC_16_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.32 $qu, $as */ + Xtensa_EE_VLDBC_32 /* 1571 */, XTENSA_INS_EE_VLDBC_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.32.ip $qu, $as, $imm4 */ + Xtensa_EE_VLDBC_32_IP /* 1572 */, XTENSA_INS_EE_VLDBC_32_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.32.xp $qu, $as, $ad */ + Xtensa_EE_VLDBC_32_XP /* 1573 */, XTENSA_INS_EE_VLDBC_32_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.8 $qu, $as */ + Xtensa_EE_VLDBC_8 /* 1574 */, XTENSA_INS_EE_VLDBC_8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.8.ip $qu, $as, $imm1 */ + Xtensa_EE_VLDBC_8_IP /* 1575 */, XTENSA_INS_EE_VLDBC_8_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldbc.8.xp $qu, $as, $ad */ + Xtensa_EE_VLDBC_8_XP /* 1576 */, XTENSA_INS_EE_VLDBC_8_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vldhbc.16.incp $qu, $qu1, $as */ + Xtensa_EE_VLDHBC_16_INCP /* 1577 */, XTENSA_INS_EE_VLDHBC_16_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vld.128.ip $qu, $as, $imm16 */ + Xtensa_EE_VLD_128_IP /* 1578 */, XTENSA_INS_EE_VLD_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vld.128.xp $qu, $as, $ad */ + Xtensa_EE_VLD_128_XP /* 1579 */, XTENSA_INS_EE_VLD_128_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vld.h.64.ip $qu, $as, $imm8 */ + Xtensa_EE_VLD_H_64_IP /* 1580 */, XTENSA_INS_EE_VLD_H_64_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vld.h.64.xp $qu, $as, $ad */ + Xtensa_EE_VLD_H_64_XP /* 1581 */, XTENSA_INS_EE_VLD_H_64_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vld.l.64.ip $qu, $as, $imm8 */ + Xtensa_EE_VLD_L_64_IP /* 1582 */, XTENSA_INS_EE_VLD_L_64_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vld.l.64.xp $qu, $as, $ad */ + Xtensa_EE_VLD_L_64_XP /* 1583 */, XTENSA_INS_EE_VLD_L_64_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmax.s16 $qa, $qx, $qy */ + Xtensa_EE_VMAX_S16 /* 1584 */, XTENSA_INS_EE_VMAX_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmax.s16.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S16_LD_INCP /* 1585 */, XTENSA_INS_EE_VMAX_S16_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmax.s16.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S16_ST_INCP /* 1586 */, XTENSA_INS_EE_VMAX_S16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmax.s32 $qa, $qx, $qy */ + Xtensa_EE_VMAX_S32 /* 1587 */, XTENSA_INS_EE_VMAX_S32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmax.s32.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S32_LD_INCP /* 1588 */, XTENSA_INS_EE_VMAX_S32_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmax.s32.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S32_ST_INCP /* 1589 */, XTENSA_INS_EE_VMAX_S32_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmax.s8 $qa, $qx, $qy */ + Xtensa_EE_VMAX_S8 /* 1590 */, XTENSA_INS_EE_VMAX_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmax.s8.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S8_LD_INCP /* 1591 */, XTENSA_INS_EE_VMAX_S8_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmax.s8.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMAX_S8_ST_INCP /* 1592 */, XTENSA_INS_EE_VMAX_S8_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmin.s16 $qa, $qx, $qy */ + Xtensa_EE_VMIN_S16 /* 1593 */, XTENSA_INS_EE_VMIN_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmin.s16.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S16_LD_INCP /* 1594 */, XTENSA_INS_EE_VMIN_S16_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmin.s16.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S16_ST_INCP /* 1595 */, XTENSA_INS_EE_VMIN_S16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmin.s32 $qa, $qx, $qy */ + Xtensa_EE_VMIN_S32 /* 1596 */, XTENSA_INS_EE_VMIN_S32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmin.s32.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S32_LD_INCP /* 1597 */, XTENSA_INS_EE_VMIN_S32_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmin.s32.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S32_ST_INCP /* 1598 */, XTENSA_INS_EE_VMIN_S32_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmin.s8 $qa, $qx, $qy */ + Xtensa_EE_VMIN_S8 /* 1599 */, XTENSA_INS_EE_VMIN_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmin.s8.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S8_LD_INCP /* 1600 */, XTENSA_INS_EE_VMIN_S8_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmin.s8.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VMIN_S8_ST_INCP /* 1601 */, XTENSA_INS_EE_VMIN_S8_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.accx $qx, $qy */ + Xtensa_EE_VMULAS_S16_ACCX /* 1602 */, XTENSA_INS_EE_VMULAS_S16_ACCX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.s16.accx.ld.ip $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_S16_ACCX_LD_IP /* 1603 */, XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.accx.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_ACCX_LD_IP_QUP /* 1604 */, XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.accx.ld.xp $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_S16_ACCX_LD_XP /* 1605 */, XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.accx.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_ACCX_LD_XP_QUP /* 1606 */, XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.qacc $qx, $qy */ + Xtensa_EE_VMULAS_S16_QACC /* 1607 */, XTENSA_INS_EE_VMULAS_S16_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.s16.qacc.ldbc.incp $qu, $as, $qx, $qy */ + Xtensa_EE_VMULAS_S16_QACC_LDBC_INCP /* 1608 */, XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.s16.qacc.ldbc.incp.qup $qu, $as, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_QACC_LDBC_INCP_QUP /* 1609 */, XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.qacc.ld.ip $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_S16_QACC_LD_IP /* 1610 */, XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.qacc.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_QACC_LD_IP_QUP /* 1611 */, XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.qacc.ld.xp $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_S16_QACC_LD_XP /* 1612 */, XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s16.qacc.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S16_QACC_LD_XP_QUP /* 1613 */, XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.accx $qx, $qy */ + Xtensa_EE_VMULAS_S8_ACCX /* 1614 */, XTENSA_INS_EE_VMULAS_S8_ACCX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.s8.accx.ld.ip $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_S8_ACCX_LD_IP /* 1615 */, XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.accx.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_ACCX_LD_IP_QUP /* 1616 */, XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.accx.ld.xp $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_S8_ACCX_LD_XP /* 1617 */, XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.accx.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_ACCX_LD_XP_QUP /* 1618 */, XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.qacc $qx, $qy */ + Xtensa_EE_VMULAS_S8_QACC /* 1619 */, XTENSA_INS_EE_VMULAS_S8_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.s8.qacc.ldbc.incp $qu, $as, $qx, $qy */ + Xtensa_EE_VMULAS_S8_QACC_LDBC_INCP /* 1620 */, XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.s8.qacc.ldbc.incp.qup $qu, $as, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_QACC_LDBC_INCP_QUP /* 1621 */, XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.qacc.ld.ip $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_S8_QACC_LD_IP /* 1622 */, XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.qacc.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_QACC_LD_IP_QUP /* 1623 */, XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.qacc.ld.xp $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_S8_QACC_LD_XP /* 1624 */, XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.s8.qacc.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_S8_QACC_LD_XP_QUP /* 1625 */, XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.accx $qx, $qy */ + Xtensa_EE_VMULAS_U16_ACCX /* 1626 */, XTENSA_INS_EE_VMULAS_U16_ACCX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.u16.accx.ld.ip $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_U16_ACCX_LD_IP /* 1627 */, XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.accx.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_ACCX_LD_IP_QUP /* 1628 */, XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.accx.ld.xp $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_U16_ACCX_LD_XP /* 1629 */, XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.accx.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_ACCX_LD_XP_QUP /* 1630 */, XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.qacc $qx, $qy */ + Xtensa_EE_VMULAS_U16_QACC /* 1631 */, XTENSA_INS_EE_VMULAS_U16_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.u16.qacc.ldbc.incp $qu, $as, $qx, $qy */ + Xtensa_EE_VMULAS_U16_QACC_LDBC_INCP /* 1632 */, XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.u16.qacc.ldbc.incp.qup $qu, $as, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_QACC_LDBC_INCP_QUP /* 1633 */, XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.qacc.ld.ip $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_U16_QACC_LD_IP /* 1634 */, XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.qacc.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_QACC_LD_IP_QUP /* 1635 */, XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.qacc.ld.xp $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_U16_QACC_LD_XP /* 1636 */, XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u16.qacc.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U16_QACC_LD_XP_QUP /* 1637 */, XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.accx $qx, $qy */ + Xtensa_EE_VMULAS_U8_ACCX /* 1638 */, XTENSA_INS_EE_VMULAS_U8_ACCX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.u8.accx.ld.ip $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_U8_ACCX_LD_IP /* 1639 */, XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.accx.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_ACCX_LD_IP_QUP /* 1640 */, XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.accx.ld.xp $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_U8_ACCX_LD_XP /* 1641 */, XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.accx.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_ACCX_LD_XP_QUP /* 1642 */, XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.qacc $qx, $qy */ + Xtensa_EE_VMULAS_U8_QACC /* 1643 */, XTENSA_INS_EE_VMULAS_U8_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.u8.qacc.ldbc.incp $qu, $as, $qx, $qy */ + Xtensa_EE_VMULAS_U8_QACC_LDBC_INCP /* 1644 */, XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmulas.u8.qacc.ldbc.incp.qup $qu, $as, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_QACC_LDBC_INCP_QUP /* 1645 */, XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.qacc.ld.ip $qu, $as, $imm16, $qx, $qy */ + Xtensa_EE_VMULAS_U8_QACC_LD_IP /* 1646 */, XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.qacc.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_QACC_LD_IP_QUP /* 1647 */, XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.qacc.ld.xp $qu, $as, $ad, $qx, $qy */ + Xtensa_EE_VMULAS_U8_QACC_LD_XP /* 1648 */, XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmulas.u8.qacc.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + Xtensa_EE_VMULAS_U8_QACC_LD_XP_QUP /* 1649 */, XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP_QUP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmul.s16 $qz, $qx, $qy */ + Xtensa_EE_VMUL_S16 /* 1650 */, XTENSA_INS_EE_VMUL_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmul.s16.ld.incp $qu, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S16_LD_INCP /* 1651 */, XTENSA_INS_EE_VMUL_S16_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmul.s16.st.incp $qv, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S16_ST_INCP /* 1652 */, XTENSA_INS_EE_VMUL_S16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmul.s8 $qz, $qx, $qy */ + Xtensa_EE_VMUL_S8 /* 1653 */, XTENSA_INS_EE_VMUL_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmul.s8.ld.incp $qu, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S8_LD_INCP /* 1654 */, XTENSA_INS_EE_VMUL_S8_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmul.s8.st.incp $qv, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_S8_ST_INCP /* 1655 */, XTENSA_INS_EE_VMUL_S8_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmul.u16 $qz, $qx, $qy */ + Xtensa_EE_VMUL_U16 /* 1656 */, XTENSA_INS_EE_VMUL_U16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmul.u16.ld.incp $qu, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U16_LD_INCP /* 1657 */, XTENSA_INS_EE_VMUL_U16_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmul.u16.st.incp $qv, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U16_ST_INCP /* 1658 */, XTENSA_INS_EE_VMUL_U16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmul.u8 $qz, $qx, $qy */ + Xtensa_EE_VMUL_U8 /* 1659 */, XTENSA_INS_EE_VMUL_U8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vmul.u8.ld.incp $qu, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U8_LD_INCP /* 1660 */, XTENSA_INS_EE_VMUL_U8_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vmul.u8.st.incp $qv, $as, $qz, $qx, $qy */ + Xtensa_EE_VMUL_U8_ST_INCP /* 1661 */, XTENSA_INS_EE_VMUL_U8_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vprelu.s16 $qz, $qx, $qy, $ay */ + Xtensa_EE_VPRELU_S16 /* 1662 */, XTENSA_INS_EE_VPRELU_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vprelu.s8 $qz, $qx, $qy, $ay */ + Xtensa_EE_VPRELU_S8 /* 1663 */, XTENSA_INS_EE_VPRELU_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vrelu.s16 $qs, $ax, $ay */ + Xtensa_EE_VRELU_S16 /* 1664 */, XTENSA_INS_EE_VRELU_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vrelu.s8 $qs, $ax, $ay */ + Xtensa_EE_VRELU_S8 /* 1665 */, XTENSA_INS_EE_VRELU_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vsl.32 $qa, $qs */ + Xtensa_EE_VSL_32 /* 1666 */, XTENSA_INS_EE_VSL_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vsmulas.s16.qacc $qx, $qy, $sel8 */ + Xtensa_EE_VSMULAS_S16_QACC /* 1667 */, XTENSA_INS_EE_VSMULAS_S16_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vsmulas.s16.qacc.ld.incp $qu, $as, $qx, $qy, $sel8 */ + Xtensa_EE_VSMULAS_S16_QACC_LD_INCP /* 1668 */, XTENSA_INS_EE_VSMULAS_S16_QACC_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vsmulas.s8.qacc $qx, $qy, $sel16 */ + Xtensa_EE_VSMULAS_S8_QACC /* 1669 */, XTENSA_INS_EE_VSMULAS_S8_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vsmulas.s8.qacc.ld.incp $qu, $as, $qx, $qy, $sel16 */ + Xtensa_EE_VSMULAS_S8_QACC_LD_INCP /* 1670 */, XTENSA_INS_EE_VSMULAS_S8_QACC_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vsr.32 $qa, $qs */ + Xtensa_EE_VSR_32 /* 1671 */, XTENSA_INS_EE_VSR_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vst.128.ip $qv, $as, $imm16 */ + Xtensa_EE_VST_128_IP /* 1672 */, XTENSA_INS_EE_VST_128_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vst.128.xp $qv, $as, $ad */ + Xtensa_EE_VST_128_XP /* 1673 */, XTENSA_INS_EE_VST_128_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vst.h.64.ip $qv, $as, $imm8 */ + Xtensa_EE_VST_H_64_IP /* 1674 */, XTENSA_INS_EE_VST_H_64_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vst.h.64.xp $qv, $as, $ad */ + Xtensa_EE_VST_H_64_XP /* 1675 */, XTENSA_INS_EE_VST_H_64_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vst.l.64.ip $qv, $as, $imm8 */ + Xtensa_EE_VST_L_64_IP /* 1676 */, XTENSA_INS_EE_VST_L_64_IP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vst.l.64.xp $qv, $as, $ad */ + Xtensa_EE_VST_L_64_XP /* 1677 */, XTENSA_INS_EE_VST_L_64_XP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vsubs.s16 $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S16 /* 1678 */, XTENSA_INS_EE_VSUBS_S16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vsubs.s16.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S16_LD_INCP /* 1679 */, XTENSA_INS_EE_VSUBS_S16_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vsubs.s16.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S16_ST_INCP /* 1680 */, XTENSA_INS_EE_VSUBS_S16_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vsubs.s32 $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S32 /* 1681 */, XTENSA_INS_EE_VSUBS_S32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vsubs.s32.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S32_LD_INCP /* 1682 */, XTENSA_INS_EE_VSUBS_S32_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vsubs.s32.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S32_ST_INCP /* 1683 */, XTENSA_INS_EE_VSUBS_S32_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vsubs.s8 $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S8 /* 1684 */, XTENSA_INS_EE_VSUBS_S8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vsubs.s8.ld.incp $qu, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S8_LD_INCP /* 1685 */, XTENSA_INS_EE_VSUBS_S8_LD_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vsubs.s8.st.incp $qv, $as, $qa, $qx, $qy */ + Xtensa_EE_VSUBS_S8_ST_INCP /* 1686 */, XTENSA_INS_EE_VSUBS_S8_ST_INCP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ee.vunzip.16 $qs0, $qs1 */ + Xtensa_EE_VUNZIP_16 /* 1687 */, XTENSA_INS_EE_VUNZIP_16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vunzip.32 $qs0, $qs1 */ + Xtensa_EE_VUNZIP_32 /* 1688 */, XTENSA_INS_EE_VUNZIP_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vunzip.8 $qs0, $qs1 */ + Xtensa_EE_VUNZIP_8 /* 1689 */, XTENSA_INS_EE_VUNZIP_8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vzip.16 $qs0, $qs1 */ + Xtensa_EE_VZIP_16 /* 1690 */, XTENSA_INS_EE_VZIP_16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vzip.32 $qs0, $qs1 */ + Xtensa_EE_VZIP_32 /* 1691 */, XTENSA_INS_EE_VZIP_32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.vzip.8 $qs0, $qs1 */ + Xtensa_EE_VZIP_8 /* 1692 */, XTENSA_INS_EE_VZIP_8, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.wr_mask_gpio_out $t, $s */ + Xtensa_EE_WR_MASK_GPIO_OUT /* 1693 */, XTENSA_INS_EE_WR_MASK_GPIO_OUT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ee.xorq $qa, $qx, $qy */ + Xtensa_EE_XORQ /* 1694 */, XTENSA_INS_EE_XORQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.zero.accx */ + Xtensa_EE_ZERO_ACCX /* 1695 */, XTENSA_INS_EE_ZERO_ACCX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.zero.q $qa */ + Xtensa_EE_ZERO_Q /* 1696 */, XTENSA_INS_EE_ZERO_Q, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* ee.zero.qacc */ + Xtensa_EE_ZERO_QACC /* 1697 */, XTENSA_INS_EE_ZERO_QACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* entry $s, $imm */ + Xtensa_ENTRY /* 1698 */, XTENSA_INS_ENTRY, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_SP, 0 }, { XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_BRI12 }} + + #endif +}, +{ + /* esync */ + Xtensa_ESYNC /* 1699 */, XTENSA_INS_ESYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* excw */ + Xtensa_EXCW /* 1700 */, XTENSA_INS_EXCW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASEXCEPTION, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* extui $r, $t, $imm1, $imm2 */ + Xtensa_EXTUI /* 1701 */, XTENSA_INS_EXTUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* extw */ + Xtensa_EXTW /* 1702 */, XTENSA_INS_EXTW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* float.s $r, $s, $imm */ + Xtensa_FLOAT_S /* 1703 */, XTENSA_INS_FLOAT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* floor.s $r, $s, $imm */ + Xtensa_FLOOR_S /* 1704 */, XTENSA_INS_FLOOR_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* get_gpio_in $t */ + Xtensa_GET_GPIO_IN /* 1705 */, XTENSA_INS_GET_GPIO_IN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S2OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ill */ + Xtensa_ILL /* 1706 */, XTENSA_INS_ILL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_CALLX }} + + #endif +}, +{ + /* ill.n */ + Xtensa_ILL_N /* 1707 */, XTENSA_INS_ILL_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* isync */ + Xtensa_ISYNC /* 1708 */, XTENSA_INS_ISYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* j $offset */ + Xtensa_J /* 1709 */, XTENSA_INS_J, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_CALL }} + + #endif +}, +{ + /* jx $s */ + Xtensa_JX /* 1710 */, XTENSA_INS_JX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 1, { .xtensa = { XTENSA_INSN_FORM_CALLX }} + + #endif +}, +{ + /* l16si $t, $addr */ + Xtensa_L16SI /* 1711 */, XTENSA_INS_L16SI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* l16ui $t, $addr */ + Xtensa_L16UI /* 1712 */, XTENSA_INS_L16UI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* l32e $t, $s, $imm */ + Xtensa_L32E /* 1713 */, XTENSA_INS_L32E, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI4 }} + + #endif +}, +{ + /* l32i $t, $addr */ + Xtensa_L32I /* 1714 */, XTENSA_INS_L32I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* l32i.n $t, $addr */ + Xtensa_L32I_N /* 1715 */, XTENSA_INS_L32I_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* l32r $t, $label */ + Xtensa_L32R /* 1716 */, XTENSA_INS_L32R, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RI16 }} + + #endif +}, +{ + /* l8ui $t, $addr */ + Xtensa_L8UI /* 1717 */, XTENSA_INS_L8UI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* lddec $w, $s */ + Xtensa_LDDEC /* 1718 */, XTENSA_INS_LDDEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ldinc $w, $s */ + Xtensa_LDINC /* 1719 */, XTENSA_INS_LDINC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* addi $t, $addr */ + Xtensa_LEA_ADD /* 1720 */, XTENSA_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* loop $s, $target */ + Xtensa_LOOP /* 1721 */, XTENSA_INS_LOOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASLOOP, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* loopgtz $s, $target */ + Xtensa_LOOPGTZ /* 1722 */, XTENSA_INS_LOOPGTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASLOOP, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* loopnez $s, $target */ + Xtensa_LOOPNEZ /* 1723 */, XTENSA_INS_LOOPNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASLOOP, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* lsi $t, $addr */ + Xtensa_LSI /* 1724 */, XTENSA_INS_LSI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* lsip $t, $s, $off */ + Xtensa_LSIP /* 1725 */, XTENSA_INS_LSIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* lsx $r, $s, $t */ + Xtensa_LSX /* 1726 */, XTENSA_INS_LSX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* lsxp $r, $s, $t */ + Xtensa_LSXP /* 1727 */, XTENSA_INS_LSXP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* maddn.s $r, $s, $t */ + Xtensa_MADDN_S /* 1728 */, XTENSA_INS_MADDN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* madd.s $r, $s, $t */ + Xtensa_MADD_S /* 1729 */, XTENSA_INS_MADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* max $r, $s, $t */ + Xtensa_MAX /* 1730 */, XTENSA_INS_MAX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMINMAX, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* maxu $r, $s, $t */ + Xtensa_MAXU /* 1731 */, XTENSA_INS_MAXU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMINMAX, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* memw */ + Xtensa_MEMW /* 1732 */, XTENSA_INS_MEMW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* min $r, $s, $t */ + Xtensa_MIN /* 1733 */, XTENSA_INS_MIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMINMAX, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* minu $r, $s, $t */ + Xtensa_MINU /* 1734 */, XTENSA_INS_MINU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMINMAX, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mkdadj.s $r, $s */ + Xtensa_MKDADJ_S /* 1735 */, XTENSA_INS_MKDADJ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mksadj.s $r, $s */ + Xtensa_MKSADJ_S /* 1736 */, XTENSA_INS_MKSADJ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* moveqz $r, $s, $t */ + Xtensa_MOVEQZ /* 1737 */, XTENSA_INS_MOVEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* moveqz.s $r, $s, $t */ + Xtensa_MOVEQZ_S /* 1738 */, XTENSA_INS_MOVEQZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movf $r, $s, $t */ + Xtensa_MOVF /* 1739 */, XTENSA_INS_MOVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movf.s $r, $s, $t */ + Xtensa_MOVF_S /* 1740 */, XTENSA_INS_MOVF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movgez $r, $s, $t */ + Xtensa_MOVGEZ /* 1741 */, XTENSA_INS_MOVGEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movgez.s $r, $s, $t */ + Xtensa_MOVGEZ_S /* 1742 */, XTENSA_INS_MOVGEZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movi $t, $imm */ + Xtensa_MOVI /* 1743 */, XTENSA_INS_MOVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* movi.n $s, $imm7 */ + Xtensa_MOVI_N /* 1744 */, XTENSA_INS_MOVI_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RI7 }} + + #endif +}, +{ + /* movltz $r, $s, $t */ + Xtensa_MOVLTZ /* 1745 */, XTENSA_INS_MOVLTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movltz.s $r, $s, $t */ + Xtensa_MOVLTZ_S /* 1746 */, XTENSA_INS_MOVLTZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movnez $r, $s, $t */ + Xtensa_MOVNEZ /* 1747 */, XTENSA_INS_MOVNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movnez.s $r, $s, $t */ + Xtensa_MOVNEZ_S /* 1748 */, XTENSA_INS_MOVNEZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movsp $t, $s */ + Xtensa_MOVSP /* 1749 */, XTENSA_INS_MOVSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movt $r, $s, $t */ + Xtensa_MOVT /* 1750 */, XTENSA_INS_MOVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* movt.s $r, $s, $t */ + Xtensa_MOVT_S /* 1751 */, XTENSA_INS_MOVT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mov.n $t, $s */ + Xtensa_MOV_N /* 1752 */, XTENSA_INS_MOV_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* mov.s $r, $s */ + Xtensa_MOV_S /* 1753 */, XTENSA_INS_MOV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* msub.s $r, $s, $t */ + Xtensa_MSUB_S /* 1754 */, XTENSA_INS_MSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul16s $r, $s, $t */ + Xtensa_MUL16S /* 1755 */, XTENSA_INS_MUL16S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMUL16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul16u $r, $s, $t */ + Xtensa_MUL16U /* 1756 */, XTENSA_INS_MUL16U, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMUL16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.aa.hh $s, $t */ + Xtensa_MULA_AA_HH /* 1757 */, XTENSA_INS_MULA_AA_HH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.aa.hl $s, $t */ + Xtensa_MULA_AA_HL /* 1758 */, XTENSA_INS_MULA_AA_HL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.aa.lh $s, $t */ + Xtensa_MULA_AA_LH /* 1759 */, XTENSA_INS_MULA_AA_LH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.aa.ll $s, $t */ + Xtensa_MULA_AA_LL /* 1760 */, XTENSA_INS_MULA_AA_LL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.ad.hh $s, $y */ + Xtensa_MULA_AD_HH /* 1761 */, XTENSA_INS_MULA_AD_HH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.ad.hl $s, $y */ + Xtensa_MULA_AD_HL /* 1762 */, XTENSA_INS_MULA_AD_HL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.ad.lh $s, $y */ + Xtensa_MULA_AD_LH /* 1763 */, XTENSA_INS_MULA_AD_LH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.ad.ll $s, $y */ + Xtensa_MULA_AD_LL /* 1764 */, XTENSA_INS_MULA_AD_LL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.hh $x, $t */ + Xtensa_MULA_DA_HH /* 1765 */, XTENSA_INS_MULA_DA_HH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.hh.lddec $w, $s, $x, $t */ + Xtensa_MULA_DA_HH_LDDEC /* 1766 */, XTENSA_INS_MULA_DA_HH_LDDEC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.hh.ldinc $w, $s, $x, $t */ + Xtensa_MULA_DA_HH_LDINC /* 1767 */, XTENSA_INS_MULA_DA_HH_LDINC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.hl $x, $t */ + Xtensa_MULA_DA_HL /* 1768 */, XTENSA_INS_MULA_DA_HL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.hl.lddec $w, $s, $x, $t */ + Xtensa_MULA_DA_HL_LDDEC /* 1769 */, XTENSA_INS_MULA_DA_HL_LDDEC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.hl.ldinc $w, $s, $x, $t */ + Xtensa_MULA_DA_HL_LDINC /* 1770 */, XTENSA_INS_MULA_DA_HL_LDINC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.lh $x, $t */ + Xtensa_MULA_DA_LH /* 1771 */, XTENSA_INS_MULA_DA_LH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.lh.lddec $w, $s, $x, $t */ + Xtensa_MULA_DA_LH_LDDEC /* 1772 */, XTENSA_INS_MULA_DA_LH_LDDEC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.lh.ldinc $w, $s, $x, $t */ + Xtensa_MULA_DA_LH_LDINC /* 1773 */, XTENSA_INS_MULA_DA_LH_LDINC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.ll $x, $t */ + Xtensa_MULA_DA_LL /* 1774 */, XTENSA_INS_MULA_DA_LL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.ll.lddec $w, $s, $x, $t */ + Xtensa_MULA_DA_LL_LDDEC /* 1775 */, XTENSA_INS_MULA_DA_LL_LDDEC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.da.ll.ldinc $w, $s, $x, $t */ + Xtensa_MULA_DA_LL_LDINC /* 1776 */, XTENSA_INS_MULA_DA_LL_LDINC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.hh $x, $y */ + Xtensa_MULA_DD_HH /* 1777 */, XTENSA_INS_MULA_DD_HH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.hh.lddec $w, $s, $x, $y */ + Xtensa_MULA_DD_HH_LDDEC /* 1778 */, XTENSA_INS_MULA_DD_HH_LDDEC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.hh.ldinc $w, $s, $x, $y */ + Xtensa_MULA_DD_HH_LDINC /* 1779 */, XTENSA_INS_MULA_DD_HH_LDINC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.hl $x, $y */ + Xtensa_MULA_DD_HL /* 1780 */, XTENSA_INS_MULA_DD_HL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.hl.lddec $w, $s, $x, $y */ + Xtensa_MULA_DD_HL_LDDEC /* 1781 */, XTENSA_INS_MULA_DD_HL_LDDEC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.hl.ldinc $w, $s, $x, $y */ + Xtensa_MULA_DD_HL_LDINC /* 1782 */, XTENSA_INS_MULA_DD_HL_LDINC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.lh $x, $y */ + Xtensa_MULA_DD_LH /* 1783 */, XTENSA_INS_MULA_DD_LH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.lh.lddec $w, $s, $x, $y */ + Xtensa_MULA_DD_LH_LDDEC /* 1784 */, XTENSA_INS_MULA_DD_LH_LDDEC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.lh.ldinc $w, $s, $x, $y */ + Xtensa_MULA_DD_LH_LDINC /* 1785 */, XTENSA_INS_MULA_DD_LH_LDINC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.ll $x, $y */ + Xtensa_MULA_DD_LL /* 1786 */, XTENSA_INS_MULA_DD_LL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.ll.lddec $w, $s, $x, $y */ + Xtensa_MULA_DD_LL_LDDEC /* 1787 */, XTENSA_INS_MULA_DD_LL_LDDEC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mula.dd.ll.ldinc $w, $s, $x, $y */ + Xtensa_MULA_DD_LL_LDINC /* 1788 */, XTENSA_INS_MULA_DD_LL_LDINC, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mull $r, $s, $t */ + Xtensa_MULL /* 1789 */, XTENSA_INS_MULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMUL32, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mulsh $r, $s, $t */ + Xtensa_MULSH /* 1790 */, XTENSA_INS_MULSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMUL32HIGH, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.aa.hh $s, $t */ + Xtensa_MULS_AA_HH /* 1791 */, XTENSA_INS_MULS_AA_HH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.aa.hl $s, $t */ + Xtensa_MULS_AA_HL /* 1792 */, XTENSA_INS_MULS_AA_HL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.aa.lh $s, $t */ + Xtensa_MULS_AA_LH /* 1793 */, XTENSA_INS_MULS_AA_LH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.aa.ll $s, $t */ + Xtensa_MULS_AA_LL /* 1794 */, XTENSA_INS_MULS_AA_LL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.ad.hh $s, $y */ + Xtensa_MULS_AD_HH /* 1795 */, XTENSA_INS_MULS_AD_HH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.ad.hl $s, $y */ + Xtensa_MULS_AD_HL /* 1796 */, XTENSA_INS_MULS_AD_HL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.ad.lh $s, $y */ + Xtensa_MULS_AD_LH /* 1797 */, XTENSA_INS_MULS_AD_LH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.ad.ll $s, $y */ + Xtensa_MULS_AD_LL /* 1798 */, XTENSA_INS_MULS_AD_LL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.da.hh $x, $t */ + Xtensa_MULS_DA_HH /* 1799 */, XTENSA_INS_MULS_DA_HH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.da.hl $x, $t */ + Xtensa_MULS_DA_HL /* 1800 */, XTENSA_INS_MULS_DA_HL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.da.lh $x, $t */ + Xtensa_MULS_DA_LH /* 1801 */, XTENSA_INS_MULS_DA_LH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.da.ll $x, $t */ + Xtensa_MULS_DA_LL /* 1802 */, XTENSA_INS_MULS_DA_LL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.dd.hh $x, $y */ + Xtensa_MULS_DD_HH /* 1803 */, XTENSA_INS_MULS_DD_HH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.dd.hl $x, $y */ + Xtensa_MULS_DD_HL /* 1804 */, XTENSA_INS_MULS_DD_HL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.dd.lh $x, $y */ + Xtensa_MULS_DD_LH /* 1805 */, XTENSA_INS_MULS_DD_LH, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muls.dd.ll $x, $y */ + Xtensa_MULS_DD_LL /* 1806 */, XTENSA_INS_MULS_DD_LL, + #ifndef CAPSTONE_DIET + { XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* muluh $r, $s, $t */ + Xtensa_MULUH /* 1807 */, XTENSA_INS_MULUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASMUL32HIGH, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.aa.hh $s, $t */ + Xtensa_MUL_AA_HH /* 1808 */, XTENSA_INS_MUL_AA_HH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.aa.hl $s, $t */ + Xtensa_MUL_AA_HL /* 1809 */, XTENSA_INS_MUL_AA_HL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.aa.lh $s, $t */ + Xtensa_MUL_AA_LH /* 1810 */, XTENSA_INS_MUL_AA_LH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.aa.ll $s, $t */ + Xtensa_MUL_AA_LL /* 1811 */, XTENSA_INS_MUL_AA_LL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.ad.hh $s, $y */ + Xtensa_MUL_AD_HH /* 1812 */, XTENSA_INS_MUL_AD_HH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.ad.hl $s, $y */ + Xtensa_MUL_AD_HL /* 1813 */, XTENSA_INS_MUL_AD_HL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.ad.lh $s, $y */ + Xtensa_MUL_AD_LH /* 1814 */, XTENSA_INS_MUL_AD_LH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.ad.ll $s, $y */ + Xtensa_MUL_AD_LL /* 1815 */, XTENSA_INS_MUL_AD_LL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.da.hh $x, $t */ + Xtensa_MUL_DA_HH /* 1816 */, XTENSA_INS_MUL_DA_HH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.da.hl $x, $t */ + Xtensa_MUL_DA_HL /* 1817 */, XTENSA_INS_MUL_DA_HL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.da.lh $x, $t */ + Xtensa_MUL_DA_LH /* 1818 */, XTENSA_INS_MUL_DA_LH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.da.ll $x, $t */ + Xtensa_MUL_DA_LL /* 1819 */, XTENSA_INS_MUL_DA_LL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.dd.hh $x, $y */ + Xtensa_MUL_DD_HH /* 1820 */, XTENSA_INS_MUL_DD_HH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.dd.hl $x, $y */ + Xtensa_MUL_DD_HL /* 1821 */, XTENSA_INS_MUL_DD_HL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.dd.lh $x, $y */ + Xtensa_MUL_DD_LH /* 1822 */, XTENSA_INS_MUL_DD_LH, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.dd.ll $x, $y */ + Xtensa_MUL_DD_LL /* 1823 */, XTENSA_INS_MUL_DD_LL, + #ifndef CAPSTONE_DIET + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mul.s $r, $s, $t */ + Xtensa_MUL_S /* 1824 */, XTENSA_INS_MUL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* neg $r, $t */ + Xtensa_NEG /* 1825 */, XTENSA_INS_NEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* neg.s $r, $s */ + Xtensa_NEG_S /* 1826 */, XTENSA_INS_NEG_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* nexp01.s $r, $s */ + Xtensa_NEXP01_S /* 1827 */, XTENSA_INS_NEXP01_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* nop */ + Xtensa_NOP /* 1828 */, XTENSA_INS_NOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* nsa $t, $s */ + Xtensa_NSA /* 1829 */, XTENSA_INS_NSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASNSA, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* nsau $t, $s */ + Xtensa_NSAU /* 1830 */, XTENSA_INS_NSAU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASNSA, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* oeq.s $r, $s, $t */ + Xtensa_OEQ_S /* 1831 */, XTENSA_INS_OEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ole.s $r, $s, $t */ + Xtensa_OLE_S /* 1832 */, XTENSA_INS_OLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* olt.s $r, $s, $t */ + Xtensa_OLT_S /* 1833 */, XTENSA_INS_OLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* or $r, $s, $t */ + Xtensa_OR /* 1834 */, XTENSA_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* orb $r, $s, $t */ + Xtensa_ORB /* 1835 */, XTENSA_INS_ORB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* orbc $r, $s, $t */ + Xtensa_ORBC /* 1836 */, XTENSA_INS_ORBC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* quos $r, $s, $t */ + Xtensa_QUOS /* 1837 */, XTENSA_INS_QUOS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDIV32, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* quou $r, $s, $t */ + Xtensa_QUOU /* 1838 */, XTENSA_INS_QUOU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDIV32, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* recip0.s $r, $s */ + Xtensa_RECIP0_S /* 1839 */, XTENSA_INS_RECIP0_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rems $r, $s, $t */ + Xtensa_REMS /* 1840 */, XTENSA_INS_REMS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDIV32, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* remu $r, $s, $t */ + Xtensa_REMU /* 1841 */, XTENSA_INS_REMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDIV32, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rer $t, $s */ + Xtensa_RER /* 1842 */, XTENSA_INS_RER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* ret */ + Xtensa_RET /* 1843 */, XTENSA_INS_RET, + #ifndef CAPSTONE_DIET + { XTENSA_REG_A0, 0 }, { 0 }, { XTENSA_GRP_JUMP, XTENSA_GRP_RET, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_CALLX }} + + #endif +}, +{ + /* retw */ + Xtensa_RETW /* 1844 */, XTENSA_INS_RETW, + #ifndef CAPSTONE_DIET + { XTENSA_REG_A0, 0 }, { 0 }, { XTENSA_GRP_JUMP, XTENSA_GRP_RET, XTENSA_FEATURE_HASWINDOWED, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_CALLX }} + + #endif +}, +{ + /* retw.n */ + Xtensa_RETW_N /* 1845 */, XTENSA_INS_RETW_N, + #ifndef CAPSTONE_DIET + { XTENSA_REG_A0, 0 }, { 0 }, { XTENSA_GRP_JUMP, XTENSA_GRP_RET, XTENSA_FEATURE_HASWINDOWED, XTENSA_FEATURE_HASDENSITY, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* ret.n */ + Xtensa_RET_N /* 1846 */, XTENSA_INS_RET_N, + #ifndef CAPSTONE_DIET + { XTENSA_REG_A0, 0 }, { 0 }, { XTENSA_GRP_JUMP, XTENSA_GRP_RET, XTENSA_FEATURE_HASDENSITY, 0 }, 1, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* rfde */ + Xtensa_RFDE /* 1847 */, XTENSA_INS_RFDE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASEXCEPTION, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rfe */ + Xtensa_RFE /* 1848 */, XTENSA_INS_RFE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASEXCEPTION, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rfi $imm */ + Xtensa_RFI /* 1849 */, XTENSA_INS_RFI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASINTERRUPT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rfr $r, $s */ + Xtensa_RFR /* 1850 */, XTENSA_INS_RFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rfwo */ + Xtensa_RFWO /* 1851 */, XTENSA_INS_RFWO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rfwu */ + Xtensa_RFWU /* 1852 */, XTENSA_INS_RFWU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rotw $imm */ + Xtensa_ROTW /* 1853 */, XTENSA_INS_ROTW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* round.s $r, $s, $imm */ + Xtensa_ROUND_S /* 1854 */, XTENSA_INS_ROUND_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rsil $t, $imm */ + Xtensa_RSIL /* 1855 */, XTENSA_INS_RSIL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASINTERRUPT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rsqrt0.s $r, $s */ + Xtensa_RSQRT0_S /* 1856 */, XTENSA_INS_RSQRT0_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rsr $t, $sr */ + Xtensa_RSR /* 1857 */, XTENSA_INS_RSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RSR }} + + #endif +}, +{ + /* rsync */ + Xtensa_RSYNC /* 1858 */, XTENSA_INS_RSYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rur $r, $ur */ + Xtensa_RUR /* 1859 */, XTENSA_INS_RUR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* rur.accx_0 $arr */ + Xtensa_RUR_ACCX_0 /* 1860 */, XTENSA_INS_RUR_ACCX_0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.accx_1 $arr */ + Xtensa_RUR_ACCX_1 /* 1861 */, XTENSA_INS_RUR_ACCX_1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.ae_bithead $arr */ + Xtensa_RUR_AE_BITHEAD /* 1862 */, XTENSA_INS_RUR_AE_BITHEAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_bitptr $art */ + Xtensa_RUR_AE_BITPTR /* 1863 */, XTENSA_INS_RUR_AE_BITPTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_bitsused $art */ + Xtensa_RUR_AE_BITSUSED /* 1864 */, XTENSA_INS_RUR_AE_BITSUSED, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_cbegin0 $arr */ + Xtensa_RUR_AE_CBEGIN0 /* 1865 */, XTENSA_INS_RUR_AE_CBEGIN0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_cend0 $arr */ + Xtensa_RUR_AE_CEND0 /* 1866 */, XTENSA_INS_RUR_AE_CEND0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_cwrap $art */ + Xtensa_RUR_AE_CWRAP /* 1867 */, XTENSA_INS_RUR_AE_CWRAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_cw_sd_no $arr */ + Xtensa_RUR_AE_CW_SD_NO /* 1868 */, XTENSA_INS_RUR_AE_CW_SD_NO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_first_ts $art */ + Xtensa_RUR_AE_FIRST_TS /* 1869 */, XTENSA_INS_RUR_AE_FIRST_TS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_nextoffset $art */ + Xtensa_RUR_AE_NEXTOFFSET /* 1870 */, XTENSA_INS_RUR_AE_NEXTOFFSET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_overflow $art */ + Xtensa_RUR_AE_OVERFLOW /* 1871 */, XTENSA_INS_RUR_AE_OVERFLOW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_ovf_sar $arr */ + Xtensa_RUR_AE_OVF_SAR /* 1872 */, XTENSA_INS_RUR_AE_OVF_SAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_sar $art */ + Xtensa_RUR_AE_SAR /* 1873 */, XTENSA_INS_RUR_AE_SAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_searchdone $art */ + Xtensa_RUR_AE_SEARCHDONE /* 1874 */, XTENSA_INS_RUR_AE_SEARCHDONE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_tablesize $art */ + Xtensa_RUR_AE_TABLESIZE /* 1875 */, XTENSA_INS_RUR_AE_TABLESIZE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.ae_ts_fts_bu_bp $arr */ + Xtensa_RUR_AE_TS_FTS_BU_BP /* 1876 */, XTENSA_INS_RUR_AE_TS_FTS_BU_BP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} + + #endif +}, +{ + /* rur.fft_bit_width $arr */ + Xtensa_RUR_FFT_BIT_WIDTH /* 1877 */, XTENSA_INS_RUR_FFT_BIT_WIDTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.gpio_out $arr */ + Xtensa_RUR_GPIO_OUT /* 1878 */, XTENSA_INS_RUR_GPIO_OUT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_h_0 $arr */ + Xtensa_RUR_QACC_H_0 /* 1879 */, XTENSA_INS_RUR_QACC_H_0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_h_1 $arr */ + Xtensa_RUR_QACC_H_1 /* 1880 */, XTENSA_INS_RUR_QACC_H_1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_h_2 $arr */ + Xtensa_RUR_QACC_H_2 /* 1881 */, XTENSA_INS_RUR_QACC_H_2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_h_3 $arr */ + Xtensa_RUR_QACC_H_3 /* 1882 */, XTENSA_INS_RUR_QACC_H_3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_h_4 $arr */ + Xtensa_RUR_QACC_H_4 /* 1883 */, XTENSA_INS_RUR_QACC_H_4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_l_0 $arr */ + Xtensa_RUR_QACC_L_0 /* 1884 */, XTENSA_INS_RUR_QACC_L_0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_l_1 $arr */ + Xtensa_RUR_QACC_L_1 /* 1885 */, XTENSA_INS_RUR_QACC_L_1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_l_2 $arr */ + Xtensa_RUR_QACC_L_2 /* 1886 */, XTENSA_INS_RUR_QACC_L_2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_l_3 $arr */ + Xtensa_RUR_QACC_L_3 /* 1887 */, XTENSA_INS_RUR_QACC_L_3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.qacc_l_4 $arr */ + Xtensa_RUR_QACC_L_4 /* 1888 */, XTENSA_INS_RUR_QACC_L_4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.sar_byte $arr */ + Xtensa_RUR_SAR_BYTE /* 1889 */, XTENSA_INS_RUR_SAR_BYTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.ua_state_0 $arr */ + Xtensa_RUR_UA_STATE_0 /* 1890 */, XTENSA_INS_RUR_UA_STATE_0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* rur.ua_state_1 $arr */ + Xtensa_RUR_UA_STATE_1 /* 1891 */, XTENSA_INS_RUR_UA_STATE_1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* add $r, $s, $t */ - Xtensa_ADD /* 272 */, XTENSA_INS_ADD, + /* rur.ua_state_2 $arr */ + Xtensa_RUR_UA_STATE_2 /* 1892 */, XTENSA_INS_RUR_UA_STATE_2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* addi $t, $s, $imm8 */ - Xtensa_ADDI /* 273 */, XTENSA_INS_ADDI, + /* rur.ua_state_3 $arr */ + Xtensa_RUR_UA_STATE_3 /* 1893 */, XTENSA_INS_RUR_UA_STATE_3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* addmi $t, $s, $imm_sh8 */ - Xtensa_ADDMI /* 274 */, XTENSA_INS_ADDMI, + /* s16i $t, $addr */ + Xtensa_S16I /* 1894 */, XTENSA_INS_S16I, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} #endif }, { - /* addx2 $r, $s, $t */ - Xtensa_ADDX2 /* 275 */, XTENSA_INS_ADDX2, + /* s32c1i $t, $addr */ + Xtensa_S32C1I /* 1895 */, XTENSA_INS_S32C1I, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { XTENSA_REG_SCOMPARE1, 0 }, { 0 }, { XTENSA_FEATURE_HASS32C1I, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} #endif }, { - /* addx4 $r, $s, $t */ - Xtensa_ADDX4 /* 276 */, XTENSA_INS_ADDX4, + /* s32e $t, $s, $imm */ + Xtensa_S32E /* 1896 */, XTENSA_INS_S32E, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASWINDOWED, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI4 }} #endif }, { - /* addx8 $r, $s, $t */ - Xtensa_ADDX8 /* 277 */, XTENSA_INS_ADDX8, + /* s32i $t, $addr */ + Xtensa_S32I /* 1897 */, XTENSA_INS_S32I, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} #endif }, { - /* and $r, $s, $t */ - Xtensa_AND /* 278 */, XTENSA_INS_AND, + /* s32i.n $t, $addr */ + Xtensa_S32I_N /* 1898 */, XTENSA_INS_S32I_N, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} #endif }, { - /* ball $s, $t, $target */ - Xtensa_BALL /* 279 */, XTENSA_INS_BALL, + /* s8i $t, $addr */ + Xtensa_S8I /* 1899 */, XTENSA_INS_S8I, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} #endif }, { - /* bany $s, $t, $target */ - Xtensa_BANY /* 280 */, XTENSA_INS_BANY, + /* set_bit_gpio_out $imm */ + Xtensa_SET_BIT_GPIO_OUT /* 1900 */, XTENSA_INS_SET_BIT_GPIO_OUT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S2OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bbc $s, $t, $target */ - Xtensa_BBC /* 281 */, XTENSA_INS_BBC, + /* sext $r, $s, $imm */ + Xtensa_SEXT /* 1901 */, XTENSA_INS_SEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSEXT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bbci $s, $imm, $target */ - Xtensa_BBCI /* 282 */, XTENSA_INS_BBCI, + /* simcall */ + Xtensa_SIMCALL /* 1902 */, XTENSA_INS_SIMCALL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bbs $s, $t, $target */ - Xtensa_BBS /* 283 */, XTENSA_INS_BBS, + /* sll $r, $s */ + Xtensa_SLL /* 1903 */, XTENSA_INS_SLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { XTENSA_REG_SAR, 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bbsi $s, $imm, $target */ - Xtensa_BBSI /* 284 */, XTENSA_INS_BBSI, + /* slli $r, $s, $sa */ + Xtensa_SLLI /* 1904 */, XTENSA_INS_SLLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* beq $s, $t, $target */ - Xtensa_BEQ /* 285 */, XTENSA_INS_BEQ, + /* sqrt0.s $r, $s */ + Xtensa_SQRT0_S /* 1905 */, XTENSA_INS_SQRT0_S, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* beqi $s, $imm, $target */ - Xtensa_BEQI /* 286 */, XTENSA_INS_BEQI, + /* sra $r, $t */ + Xtensa_SRA /* 1906 */, XTENSA_INS_SRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { XTENSA_REG_SAR, 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* beqz $s, $target */ - Xtensa_BEQZ /* 287 */, XTENSA_INS_BEQZ, + /* srai $r, $t, $sa */ + Xtensa_SRAI /* 1907 */, XTENSA_INS_SRAI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bge $s, $t, $target */ - Xtensa_BGE /* 288 */, XTENSA_INS_BGE, + /* src $r, $s, $t */ + Xtensa_SRC /* 1908 */, XTENSA_INS_SRC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { XTENSA_REG_SAR, 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bgei $s, $imm, $target */ - Xtensa_BGEI /* 289 */, XTENSA_INS_BGEI, + /* srl $r, $t */ + Xtensa_SRL /* 1909 */, XTENSA_INS_SRL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { XTENSA_REG_SAR, 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bgeu $s, $t, $target */ - Xtensa_BGEU /* 290 */, XTENSA_INS_BGEU, + /* srli $r, $t, $sa */ + Xtensa_SRLI /* 1910 */, XTENSA_INS_SRLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bgeui $s, $imm, $target */ - Xtensa_BGEUI /* 291 */, XTENSA_INS_BGEUI, + /* ssa8l $s */ + Xtensa_SSA8L /* 1911 */, XTENSA_INS_SSA8L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bgez $s, $target */ - Xtensa_BGEZ /* 292 */, XTENSA_INS_BGEZ, + /* ssai $imm */ + Xtensa_SSAI /* 1912 */, XTENSA_INS_SSAI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* blt $s, $t, $target */ - Xtensa_BLT /* 293 */, XTENSA_INS_BLT, + /* ssi $t, $addr */ + Xtensa_SSI /* 1913 */, XTENSA_INS_SSI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} #endif }, { - /* blti $s, $imm, $target */ - Xtensa_BLTI /* 294 */, XTENSA_INS_BLTI, + /* ssip $t, $s, $off */ + Xtensa_SSIP /* 1914 */, XTENSA_INS_SSIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} #endif }, { - /* bltu $s, $t, $target */ - Xtensa_BLTU /* 295 */, XTENSA_INS_BLTU, + /* ssl $s */ + Xtensa_SSL /* 1915 */, XTENSA_INS_SSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { XTENSA_REG_SAR, 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bltui $s, $imm, $target */ - Xtensa_BLTUI /* 296 */, XTENSA_INS_BLTUI, + /* ssr $s */ + Xtensa_SSR /* 1916 */, XTENSA_INS_SSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { XTENSA_REG_SAR, 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bltz $s, $target */ - Xtensa_BLTZ /* 297 */, XTENSA_INS_BLTZ, + /* ssx $r, $s, $t */ + Xtensa_SSX /* 1917 */, XTENSA_INS_SSX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bnall $s, $t, $target */ - Xtensa_BNALL /* 298 */, XTENSA_INS_BNALL, + /* ssxp $r, $s, $t */ + Xtensa_SSXP /* 1918 */, XTENSA_INS_SSXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bne $s, $t, $target */ - Xtensa_BNE /* 299 */, XTENSA_INS_BNE, + /* sub $r, $s, $t */ + Xtensa_SUB /* 1919 */, XTENSA_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bnei $s, $imm, $target */ - Xtensa_BNEI /* 300 */, XTENSA_INS_BNEI, + /* subx2 $r, $s, $t */ + Xtensa_SUBX2 /* 1920 */, XTENSA_INS_SUBX2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bnez $s, $target */ - Xtensa_BNEZ /* 301 */, XTENSA_INS_BNEZ, + /* subx4 $r, $s, $t */ + Xtensa_SUBX4 /* 1921 */, XTENSA_INS_SUBX4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* bnone $s, $t, $target */ - Xtensa_BNONE /* 302 */, XTENSA_INS_BNONE, + /* subx8 $r, $s, $t */ + Xtensa_SUBX8 /* 1922 */, XTENSA_INS_SUBX8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* call0 $offset */ - Xtensa_CALL0 /* 303 */, XTENSA_INS_CALL0, + /* sub.s $r, $s, $t */ + Xtensa_SUB_S /* 1923 */, XTENSA_INS_SUB_S, #ifndef CAPSTONE_DIET - { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* callx0 $s */ - Xtensa_CALLX0 /* 304 */, XTENSA_INS_CALLX0, + /* syscall */ + Xtensa_SYSCALL /* 1924 */, XTENSA_INS_SYSCALL, #ifndef CAPSTONE_DIET - { 0 }, { XTENSA_REG_A0, 0 }, { XTENSA_GRP_CALL, 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASEXCEPTION, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* dsync */ - Xtensa_DSYNC /* 305 */, XTENSA_INS_DSYNC, + /* trunc.s $r, $s, $imm */ + Xtensa_TRUNC_S /* 1925 */, XTENSA_INS_TRUNC_S, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* esync */ - Xtensa_ESYNC /* 306 */, XTENSA_INS_ESYNC, + /* ueq.s $r, $s, $t */ + Xtensa_UEQ_S /* 1926 */, XTENSA_INS_UEQ_S, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* extui $r, $t, $imm1, $imm2 */ - Xtensa_EXTUI /* 307 */, XTENSA_INS_EXTUI, + /* ufloat.s $r, $s, $imm */ + Xtensa_UFLOAT_S /* 1927 */, XTENSA_INS_UFLOAT_S, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* extw */ - Xtensa_EXTW /* 308 */, XTENSA_INS_EXTW, + /* ule.s $r, $s, $t */ + Xtensa_ULE_S /* 1928 */, XTENSA_INS_ULE_S, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* isync */ - Xtensa_ISYNC /* 309 */, XTENSA_INS_ISYNC, + /* ult.s $r, $s, $t */ + Xtensa_ULT_S /* 1929 */, XTENSA_INS_ULT_S, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* j $offset */ - Xtensa_J /* 310 */, XTENSA_INS_J, + /* umul.aa.hh $s, $t */ + Xtensa_UMUL_AA_HH /* 1930 */, XTENSA_INS_UMUL_AA_HH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 0, {{ 0 }} + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* jx $s */ - Xtensa_JX /* 311 */, XTENSA_INS_JX, + /* umul.aa.hl $s, $t */ + Xtensa_UMUL_AA_HL /* 1931 */, XTENSA_INS_UMUL_AA_HL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { XTENSA_GRP_JUMP, 0 }, 1, 1, {{ 0 }} + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* l16si $t, $addr */ - Xtensa_L16SI /* 312 */, XTENSA_INS_L16SI, + /* umul.aa.lh $s, $t */ + Xtensa_UMUL_AA_LH /* 1932 */, XTENSA_INS_UMUL_AA_LH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* l16ui $t, $addr */ - Xtensa_L16UI /* 313 */, XTENSA_INS_L16UI, + /* umul.aa.ll $s, $t */ + Xtensa_UMUL_AA_LL /* 1933 */, XTENSA_INS_UMUL_AA_LL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { XTENSA_REG_M1, XTENSA_REG_M2, XTENSA_REG_ACCLO, XTENSA_REG_ACCHI, 0 }, { XTENSA_FEATURE_HASMAC16, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* l32i $t, $addr */ - Xtensa_L32I /* 314 */, XTENSA_INS_L32I, + /* un.s $r, $s, $t */ + Xtensa_UN_S /* 1934 */, XTENSA_INS_UN_S, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* l32r $t, $label */ - Xtensa_L32R /* 315 */, XTENSA_INS_L32R, + /* utrunc.s $r, $s, $imm */ + Xtensa_UTRUNC_S /* 1935 */, XTENSA_INS_UTRUNC_S, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* l8ui $t, $addr */ - Xtensa_L8UI /* 316 */, XTENSA_INS_L8UI, + /* waiti $imm */ + Xtensa_WAITI /* 1936 */, XTENSA_INS_WAITI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASINTERRUPT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* memw */ - Xtensa_MEMW /* 317 */, XTENSA_INS_MEMW, + /* wdtlb $t, $s */ + Xtensa_WDTLB /* 1937 */, XTENSA_INS_WDTLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASREGIONPROTECTION, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* moveqz $r, $s, $t */ - Xtensa_MOVEQZ /* 318 */, XTENSA_INS_MOVEQZ, + /* wer $t, $s */ + Xtensa_WER /* 1938 */, XTENSA_INS_WER, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* movgez $r, $s, $t */ - Xtensa_MOVGEZ /* 319 */, XTENSA_INS_MOVGEZ, + /* wfr $r, $s */ + Xtensa_WFR /* 1939 */, XTENSA_INS_WFR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASSINGLEFLOAT, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* movi $t, $imm */ - Xtensa_MOVI /* 320 */, XTENSA_INS_MOVI, + /* witlb $t, $s */ + Xtensa_WITLB /* 1940 */, XTENSA_INS_WITLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASREGIONPROTECTION, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* movltz $r, $s, $t */ - Xtensa_MOVLTZ /* 321 */, XTENSA_INS_MOVLTZ, + /* wr_mask_gpio_out $s, $t */ + Xtensa_WR_MASK_GPIO_OUT /* 1941 */, XTENSA_INS_WR_MASK_GPIO_OUT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S2OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* movnez $r, $s, $t */ - Xtensa_MOVNEZ /* 322 */, XTENSA_INS_MOVNEZ, + /* wsr $t, $sr */ + Xtensa_WSR /* 1942 */, XTENSA_INS_WSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RSR }} #endif }, { - /* neg $r, $t */ - Xtensa_NEG /* 323 */, XTENSA_INS_NEG, + /* wur $t, $ur */ + Xtensa_WUR /* 1943 */, XTENSA_INS_WUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* nop */ - Xtensa_NOP /* 324 */, XTENSA_INS_NOP, + /* wur.accx_0 $art */ + Xtensa_WUR_ACCX_0 /* 1944 */, XTENSA_INS_WUR_ACCX_0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* or $r, $s, $t */ - Xtensa_OR /* 325 */, XTENSA_INS_OR, + /* wur.accx_1 $art */ + Xtensa_WUR_ACCX_1 /* 1945 */, XTENSA_INS_WUR_ACCX_1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* ret */ - Xtensa_RET /* 326 */, XTENSA_INS_RET, + /* wur.ae_bithead $art */ + Xtensa_WUR_AE_BITHEAD /* 1946 */, XTENSA_INS_WUR_AE_BITHEAD, #ifndef CAPSTONE_DIET - { XTENSA_REG_A0, 0 }, { 0 }, { XTENSA_GRP_JUMP, XTENSA_GRP_RET, 0 }, 1, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* rsr $t, $sr */ - Xtensa_RSR /* 327 */, XTENSA_INS_RSR, + /* wur.ae_bitptr $art */ + Xtensa_WUR_AE_BITPTR /* 1947 */, XTENSA_INS_WUR_AE_BITPTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* rsync */ - Xtensa_RSYNC /* 328 */, XTENSA_INS_RSYNC, + /* wur.ae_bitsused $art */ + Xtensa_WUR_AE_BITSUSED /* 1948 */, XTENSA_INS_WUR_AE_BITSUSED, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* s16i $t, $addr */ - Xtensa_S16I /* 329 */, XTENSA_INS_S16I, + /* wur.ae_cbegin0 $art */ + Xtensa_WUR_AE_CBEGIN0 /* 1949 */, XTENSA_INS_WUR_AE_CBEGIN0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* s32i $t, $addr */ - Xtensa_S32I /* 330 */, XTENSA_INS_S32I, + /* wur.ae_cend0 $art */ + Xtensa_WUR_AE_CEND0 /* 1950 */, XTENSA_INS_WUR_AE_CEND0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* s8i $t, $addr */ - Xtensa_S8I /* 331 */, XTENSA_INS_S8I, + /* wur.ae_cwrap $art */ + Xtensa_WUR_AE_CWRAP /* 1951 */, XTENSA_INS_WUR_AE_CWRAP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* sll $r, $s */ - Xtensa_SLL /* 332 */, XTENSA_INS_SLL, + /* wur.ae_cw_sd_no $art */ + Xtensa_WUR_AE_CW_SD_NO /* 1952 */, XTENSA_INS_WUR_AE_CW_SD_NO, #ifndef CAPSTONE_DIET - { XTENSA_REG_SAR, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* slli $r, $s, $sa */ - Xtensa_SLLI /* 333 */, XTENSA_INS_SLLI, + /* wur.ae_first_ts $art */ + Xtensa_WUR_AE_FIRST_TS /* 1953 */, XTENSA_INS_WUR_AE_FIRST_TS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* sra $r, $t */ - Xtensa_SRA /* 334 */, XTENSA_INS_SRA, + /* wur.ae_nextoffset $art */ + Xtensa_WUR_AE_NEXTOFFSET /* 1954 */, XTENSA_INS_WUR_AE_NEXTOFFSET, #ifndef CAPSTONE_DIET - { XTENSA_REG_SAR, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* srai $r, $t, $sa */ - Xtensa_SRAI /* 335 */, XTENSA_INS_SRAI, + /* wur.ae_overflow $art */ + Xtensa_WUR_AE_OVERFLOW /* 1955 */, XTENSA_INS_WUR_AE_OVERFLOW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* src $r, $s, $t */ - Xtensa_SRC /* 336 */, XTENSA_INS_SRC, + /* wur.ae_ovf_sar $art */ + Xtensa_WUR_AE_OVF_SAR /* 1956 */, XTENSA_INS_WUR_AE_OVF_SAR, #ifndef CAPSTONE_DIET - { XTENSA_REG_SAR, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* srl $r, $t */ - Xtensa_SRL /* 337 */, XTENSA_INS_SRL, + /* wur.ae_sar $art */ + Xtensa_WUR_AE_SAR /* 1957 */, XTENSA_INS_WUR_AE_SAR, #ifndef CAPSTONE_DIET - { XTENSA_REG_SAR, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* srli $r, $t, $sa */ - Xtensa_SRLI /* 338 */, XTENSA_INS_SRLI, + /* wur.ae_searchdone $art */ + Xtensa_WUR_AE_SEARCHDONE /* 1958 */, XTENSA_INS_WUR_AE_SEARCHDONE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* ssa8l $s */ - Xtensa_SSA8L /* 339 */, XTENSA_INS_SSA8L, + /* wur.ae_tablesize $art */ + Xtensa_WUR_AE_TABLESIZE /* 1959 */, XTENSA_INS_WUR_AE_TABLESIZE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* ssai $imm */ - Xtensa_SSAI /* 340 */, XTENSA_INS_SSAI, + /* wur.ae_ts_fts_bu_bp $art */ + Xtensa_WUR_AE_TS_FTS_BU_BP /* 1960 */, XTENSA_INS_WUR_AE_TS_FTS_BU_BP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASHIFI3, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_AEINST24 }} #endif }, { - /* ssl $s */ - Xtensa_SSL /* 341 */, XTENSA_INS_SSL, + /* wur.fcr $t */ + Xtensa_WUR_FCR /* 1961 */, XTENSA_INS_WUR_FCR, #ifndef CAPSTONE_DIET - { 0 }, { XTENSA_REG_SAR, 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { XTENSA_REG_FCR, 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* ssr $s */ - Xtensa_SSR /* 342 */, XTENSA_INS_SSR, + /* wur.fft_bit_width $art */ + Xtensa_WUR_FFT_BIT_WIDTH /* 1962 */, XTENSA_INS_WUR_FFT_BIT_WIDTH, #ifndef CAPSTONE_DIET - { 0 }, { XTENSA_REG_SAR, 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* sub $r, $s, $t */ - Xtensa_SUB /* 343 */, XTENSA_INS_SUB, + /* wur.fsr $t */ + Xtensa_WUR_FSR /* 1963 */, XTENSA_INS_WUR_FSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { XTENSA_REG_FSR, 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { - /* subx2 $r, $s, $t */ - Xtensa_SUBX2 /* 344 */, XTENSA_INS_SUBX2, + /* wur.gpio_out $art */ + Xtensa_WUR_GPIO_OUT /* 1964 */, XTENSA_INS_WUR_GPIO_OUT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* subx4 $r, $s, $t */ - Xtensa_SUBX4 /* 345 */, XTENSA_INS_SUBX4, + /* wur.qacc_h_0 $art */ + Xtensa_WUR_QACC_H_0 /* 1965 */, XTENSA_INS_WUR_QACC_H_0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* subx8 $r, $s, $t */ - Xtensa_SUBX8 /* 346 */, XTENSA_INS_SUBX8, + /* wur.qacc_h_1 $art */ + Xtensa_WUR_QACC_H_1 /* 1966 */, XTENSA_INS_WUR_QACC_H_1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { - /* wsr $t, $sr */ - Xtensa_WSR /* 347 */, XTENSA_INS_WSR, + /* wur.qacc_h_2 $art */ + Xtensa_WUR_QACC_H_2 /* 1967 */, XTENSA_INS_WUR_QACC_H_2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.qacc_h_3 $art */ + Xtensa_WUR_QACC_H_3 /* 1968 */, XTENSA_INS_WUR_QACC_H_3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.qacc_h_4 $art */ + Xtensa_WUR_QACC_H_4 /* 1969 */, XTENSA_INS_WUR_QACC_H_4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.qacc_l_0 $art */ + Xtensa_WUR_QACC_L_0 /* 1970 */, XTENSA_INS_WUR_QACC_L_0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.qacc_l_1 $art */ + Xtensa_WUR_QACC_L_1 /* 1971 */, XTENSA_INS_WUR_QACC_L_1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.qacc_l_2 $art */ + Xtensa_WUR_QACC_L_2 /* 1972 */, XTENSA_INS_WUR_QACC_L_2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.qacc_l_3 $art */ + Xtensa_WUR_QACC_L_3 /* 1973 */, XTENSA_INS_WUR_QACC_L_3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.qacc_l_4 $art */ + Xtensa_WUR_QACC_L_4 /* 1974 */, XTENSA_INS_WUR_QACC_L_4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.sar_byte $art */ + Xtensa_WUR_SAR_BYTE /* 1975 */, XTENSA_INS_WUR_SAR_BYTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.ua_state_0 $art */ + Xtensa_WUR_UA_STATE_0 /* 1976 */, XTENSA_INS_WUR_UA_STATE_0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.ua_state_1 $art */ + Xtensa_WUR_UA_STATE_1 /* 1977 */, XTENSA_INS_WUR_UA_STATE_1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.ua_state_2 $art */ + Xtensa_WUR_UA_STATE_2 /* 1978 */, XTENSA_INS_WUR_UA_STATE_2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} + + #endif +}, +{ + /* wur.ua_state_3 $art */ + Xtensa_WUR_UA_STATE_3 /* 1979 */, XTENSA_INS_WUR_UA_STATE_3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, { /* xor $r, $s, $t */ - Xtensa_XOR /* 348 */, XTENSA_INS_XOR, + Xtensa_XOR /* 1980 */, XTENSA_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* xorb $r, $s, $t */ + Xtensa_XORB /* 1981 */, XTENSA_INS_XORB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASBOOLEAN, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} #endif }, { /* xsr $t, $sr */ - Xtensa_XSR /* 349 */, XTENSA_INS_XSR, + Xtensa_XSR /* 1982 */, XTENSA_INS_XSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RSR }} + + #endif +}, +{ + /* _l32i $t, $addr */ + Xtensa__L32I /* 1983 */, XTENSA_INS__L32I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* _l32i.n $t, $addr */ + Xtensa__L32I_N /* 1984 */, XTENSA_INS__L32I_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* _movi $t, $imm */ + Xtensa__MOVI /* 1985 */, XTENSA_INS__MOVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* _s32i $t, $addr */ + Xtensa__S32I /* 1986 */, XTENSA_INS__S32I, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRI8 }} + + #endif +}, +{ + /* _s32i.n $t, $addr */ + Xtensa__S32I_N /* 1987 */, XTENSA_INS__S32I_N, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASDENSITY, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRRN }} + + #endif +}, +{ + /* _slli $r, $s, $sa */ + Xtensa__SLLI /* 1988 */, XTENSA_INS__SLLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* _srli $r, $t, $sa */ + Xtensa__SRLI /* 1989 */, XTENSA_INS__SRLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_RRR }} + + #endif +}, +{ + /* mv.qr $a, $b */ + Xtensa_mv_QR /* 1990 */, XTENSA_INS_MV_QR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { XTENSA_FEATURE_HASESP32S3OPS, 0 }, 0, 0, { .xtensa = { XTENSA_INSN_FORM_EE_INST24 }} #endif }, diff --git a/arch/Xtensa/XtensaGenCSMappingInsnName.inc b/arch/Xtensa/XtensaGenCSMappingInsnName.inc index 8621505e8f..51a3c84261 100644 --- a/arch/Xtensa/XtensaGenCSMappingInsnName.inc +++ b/arch/Xtensa/XtensaGenCSMappingInsnName.inc @@ -13,13 +13,862 @@ "invalid", // XTENSA_INS_INVALID "abs", // XTENSA_INS_ABS + "abs_s", // XTENSA_INS_ABS_S "add", // XTENSA_INS_ADD + "addexpm_s", // XTENSA_INS_ADDEXPM_S + "addexp_s", // XTENSA_INS_ADDEXP_S "addi", // XTENSA_INS_ADDI + "addi_n", // XTENSA_INS_ADDI_N "addmi", // XTENSA_INS_ADDMI "addx2", // XTENSA_INS_ADDX2 "addx4", // XTENSA_INS_ADDX4 "addx8", // XTENSA_INS_ADDX8 + "add_n", // XTENSA_INS_ADD_N + "add_s", // XTENSA_INS_ADD_S + "ae_abs16s", // XTENSA_INS_AE_ABS16S + "ae_abs24s", // XTENSA_INS_AE_ABS24S + "ae_abs32", // XTENSA_INS_AE_ABS32 + "ae_abs32s", // XTENSA_INS_AE_ABS32S + "ae_abs64", // XTENSA_INS_AE_ABS64 + "ae_abs64s", // XTENSA_INS_AE_ABS64S + "ae_add16", // XTENSA_INS_AE_ADD16 + "ae_add16s", // XTENSA_INS_AE_ADD16S + "ae_add24s", // XTENSA_INS_AE_ADD24S + "ae_add32", // XTENSA_INS_AE_ADD32 + "ae_add32s", // XTENSA_INS_AE_ADD32S + "ae_add32_hl_lh", // XTENSA_INS_AE_ADD32_HL_LH + "ae_add64", // XTENSA_INS_AE_ADD64 + "ae_add64s", // XTENSA_INS_AE_ADD64S + "ae_addbrba32", // XTENSA_INS_AE_ADDBRBA32 + "ae_addsub32", // XTENSA_INS_AE_ADDSUB32 + "ae_addsub32s", // XTENSA_INS_AE_ADDSUB32S + "ae_and", // XTENSA_INS_AE_AND + "ae_cvt32x2f16_10", // XTENSA_INS_AE_CVT32X2F16_10 + "ae_cvt32x2f16_32", // XTENSA_INS_AE_CVT32X2F16_32 + "ae_cvt48a32", // XTENSA_INS_AE_CVT48A32 + "ae_cvt64a32", // XTENSA_INS_AE_CVT64A32 + "ae_cvt64f32_h", // XTENSA_INS_AE_CVT64F32_H + "ae_cvta32f24s_h", // XTENSA_INS_AE_CVTA32F24S_H + "ae_cvta32f24s_l", // XTENSA_INS_AE_CVTA32F24S_L + "ae_cvtq56a32s", // XTENSA_INS_AE_CVTQ56A32S + "ae_cvtq56p32s_h", // XTENSA_INS_AE_CVTQ56P32S_H + "ae_cvtq56p32s_l", // XTENSA_INS_AE_CVTQ56P32S_L + "ae_db", // XTENSA_INS_AE_DB + "ae_dbi", // XTENSA_INS_AE_DBI + "ae_dbi_ic", // XTENSA_INS_AE_DBI_IC + "ae_dbi_ip", // XTENSA_INS_AE_DBI_IP + "ae_db_ic", // XTENSA_INS_AE_DB_IC + "ae_db_ip", // XTENSA_INS_AE_DB_IP + "ae_div64d32_h", // XTENSA_INS_AE_DIV64D32_H + "ae_div64d32_l", // XTENSA_INS_AE_DIV64D32_L + "ae_eq16", // XTENSA_INS_AE_EQ16 + "ae_eq32", // XTENSA_INS_AE_EQ32 + "ae_eq64", // XTENSA_INS_AE_EQ64 + "ae_l16m_i", // XTENSA_INS_AE_L16M_I + "ae_l16m_iu", // XTENSA_INS_AE_L16M_IU + "ae_l16m_x", // XTENSA_INS_AE_L16M_X + "ae_l16m_xc", // XTENSA_INS_AE_L16M_XC + "ae_l16m_xu", // XTENSA_INS_AE_L16M_XU + "ae_l16x2m_i", // XTENSA_INS_AE_L16X2M_I + "ae_l16x2m_iu", // XTENSA_INS_AE_L16X2M_IU + "ae_l16x2m_x", // XTENSA_INS_AE_L16X2M_X + "ae_l16x2m_xc", // XTENSA_INS_AE_L16X2M_XC + "ae_l16x2m_xu", // XTENSA_INS_AE_L16X2M_XU + "ae_l16x4_i", // XTENSA_INS_AE_L16X4_I + "ae_l16x4_ip", // XTENSA_INS_AE_L16X4_IP + "ae_l16x4_ric", // XTENSA_INS_AE_L16X4_RIC + "ae_l16x4_rip", // XTENSA_INS_AE_L16X4_RIP + "ae_l16x4_x", // XTENSA_INS_AE_L16X4_X + "ae_l16x4_xc", // XTENSA_INS_AE_L16X4_XC + "ae_l16x4_xp", // XTENSA_INS_AE_L16X4_XP + "ae_l16_i", // XTENSA_INS_AE_L16_I + "ae_l16_ip", // XTENSA_INS_AE_L16_IP + "ae_l16_x", // XTENSA_INS_AE_L16_X + "ae_l16_xc", // XTENSA_INS_AE_L16_XC + "ae_l16_xp", // XTENSA_INS_AE_L16_XP + "ae_l32f24_i", // XTENSA_INS_AE_L32F24_I + "ae_l32f24_ip", // XTENSA_INS_AE_L32F24_IP + "ae_l32f24_x", // XTENSA_INS_AE_L32F24_X + "ae_l32f24_xc", // XTENSA_INS_AE_L32F24_XC + "ae_l32f24_xp", // XTENSA_INS_AE_L32F24_XP + "ae_l32m_i", // XTENSA_INS_AE_L32M_I + "ae_l32m_iu", // XTENSA_INS_AE_L32M_IU + "ae_l32m_x", // XTENSA_INS_AE_L32M_X + "ae_l32m_xc", // XTENSA_INS_AE_L32M_XC + "ae_l32m_xu", // XTENSA_INS_AE_L32M_XU + "ae_l32x2f24_i", // XTENSA_INS_AE_L32X2F24_I + "ae_l32x2f24_ip", // XTENSA_INS_AE_L32X2F24_IP + "ae_l32x2f24_ric", // XTENSA_INS_AE_L32X2F24_RIC + "ae_l32x2f24_rip", // XTENSA_INS_AE_L32X2F24_RIP + "ae_l32x2f24_x", // XTENSA_INS_AE_L32X2F24_X + "ae_l32x2f24_xc", // XTENSA_INS_AE_L32X2F24_XC + "ae_l32x2f24_xp", // XTENSA_INS_AE_L32X2F24_XP + "ae_l32x2_i", // XTENSA_INS_AE_L32X2_I + "ae_l32x2_ip", // XTENSA_INS_AE_L32X2_IP + "ae_l32x2_ric", // XTENSA_INS_AE_L32X2_RIC + "ae_l32x2_rip", // XTENSA_INS_AE_L32X2_RIP + "ae_l32x2_x", // XTENSA_INS_AE_L32X2_X + "ae_l32x2_xc", // XTENSA_INS_AE_L32X2_XC + "ae_l32x2_xp", // XTENSA_INS_AE_L32X2_XP + "ae_l32_i", // XTENSA_INS_AE_L32_I + "ae_l32_ip", // XTENSA_INS_AE_L32_IP + "ae_l32_x", // XTENSA_INS_AE_L32_X + "ae_l32_xc", // XTENSA_INS_AE_L32_XC + "ae_l32_xp", // XTENSA_INS_AE_L32_XP + "ae_l64_i", // XTENSA_INS_AE_L64_I + "ae_l64_ip", // XTENSA_INS_AE_L64_IP + "ae_l64_x", // XTENSA_INS_AE_L64_X + "ae_l64_xc", // XTENSA_INS_AE_L64_XC + "ae_l64_xp", // XTENSA_INS_AE_L64_XP + "ae_la16x4neg_pc", // XTENSA_INS_AE_LA16X4NEG_PC + "ae_la16x4pos_pc", // XTENSA_INS_AE_LA16X4POS_PC + "ae_la16x4_ic", // XTENSA_INS_AE_LA16X4_IC + "ae_la16x4_ip", // XTENSA_INS_AE_LA16X4_IP + "ae_la16x4_ric", // XTENSA_INS_AE_LA16X4_RIC + "ae_la16x4_rip", // XTENSA_INS_AE_LA16X4_RIP + "ae_la24neg_pc", // XTENSA_INS_AE_LA24NEG_PC + "ae_la24pos_pc", // XTENSA_INS_AE_LA24POS_PC + "ae_la24x2neg_pc", // XTENSA_INS_AE_LA24X2NEG_PC + "ae_la24x2pos_pc", // XTENSA_INS_AE_LA24X2POS_PC + "ae_la24x2_ic", // XTENSA_INS_AE_LA24X2_IC + "ae_la24x2_ip", // XTENSA_INS_AE_LA24X2_IP + "ae_la24x2_ric", // XTENSA_INS_AE_LA24X2_RIC + "ae_la24x2_rip", // XTENSA_INS_AE_LA24X2_RIP + "ae_la24_ic", // XTENSA_INS_AE_LA24_IC + "ae_la24_ip", // XTENSA_INS_AE_LA24_IP + "ae_la24_ric", // XTENSA_INS_AE_LA24_RIC + "ae_la24_rip", // XTENSA_INS_AE_LA24_RIP + "ae_la32x2f24_ic", // XTENSA_INS_AE_LA32X2F24_IC + "ae_la32x2f24_ip", // XTENSA_INS_AE_LA32X2F24_IP + "ae_la32x2f24_ric", // XTENSA_INS_AE_LA32X2F24_RIC + "ae_la32x2f24_rip", // XTENSA_INS_AE_LA32X2F24_RIP + "ae_la32x2neg_pc", // XTENSA_INS_AE_LA32X2NEG_PC + "ae_la32x2pos_pc", // XTENSA_INS_AE_LA32X2POS_PC + "ae_la32x2_ic", // XTENSA_INS_AE_LA32X2_IC + "ae_la32x2_ip", // XTENSA_INS_AE_LA32X2_IP + "ae_la32x2_ric", // XTENSA_INS_AE_LA32X2_RIC + "ae_la32x2_rip", // XTENSA_INS_AE_LA32X2_RIP + "ae_la64_pp", // XTENSA_INS_AE_LA64_PP + "ae_lalign64_i", // XTENSA_INS_AE_LALIGN64_I + "ae_lb", // XTENSA_INS_AE_LB + "ae_lbi", // XTENSA_INS_AE_LBI + "ae_lbk", // XTENSA_INS_AE_LBK + "ae_lbki", // XTENSA_INS_AE_LBKI + "ae_lbs", // XTENSA_INS_AE_LBS + "ae_lbsi", // XTENSA_INS_AE_LBSI + "ae_le16", // XTENSA_INS_AE_LE16 + "ae_le32", // XTENSA_INS_AE_LE32 + "ae_le64", // XTENSA_INS_AE_LE64 + "ae_lt16", // XTENSA_INS_AE_LT16 + "ae_lt32", // XTENSA_INS_AE_LT32 + "ae_lt64", // XTENSA_INS_AE_LT64 + "ae_max32", // XTENSA_INS_AE_MAX32 + "ae_max64", // XTENSA_INS_AE_MAX64 + "ae_maxabs32s", // XTENSA_INS_AE_MAXABS32S + "ae_maxabs64s", // XTENSA_INS_AE_MAXABS64S + "ae_min32", // XTENSA_INS_AE_MIN32 + "ae_min64", // XTENSA_INS_AE_MIN64 + "ae_minabs32s", // XTENSA_INS_AE_MINABS32S + "ae_minabs64s", // XTENSA_INS_AE_MINABS64S + "ae_mov", // XTENSA_INS_AE_MOV + "ae_movad16_0", // XTENSA_INS_AE_MOVAD16_0 + "ae_movad16_1", // XTENSA_INS_AE_MOVAD16_1 + "ae_movad16_2", // XTENSA_INS_AE_MOVAD16_2 + "ae_movad16_3", // XTENSA_INS_AE_MOVAD16_3 + "ae_movad32_h", // XTENSA_INS_AE_MOVAD32_H + "ae_movad32_l", // XTENSA_INS_AE_MOVAD32_L + "ae_movalign", // XTENSA_INS_AE_MOVALIGN + "ae_movda16", // XTENSA_INS_AE_MOVDA16 + "ae_movda16x2", // XTENSA_INS_AE_MOVDA16X2 + "ae_movda32", // XTENSA_INS_AE_MOVDA32 + "ae_movda32x2", // XTENSA_INS_AE_MOVDA32X2 + "ae_movf16x4", // XTENSA_INS_AE_MOVF16X4 + "ae_movf32x2", // XTENSA_INS_AE_MOVF32X2 + "ae_movf64", // XTENSA_INS_AE_MOVF64 + "ae_movi", // XTENSA_INS_AE_MOVI + "ae_movt16x4", // XTENSA_INS_AE_MOVT16X4 + "ae_movt32x2", // XTENSA_INS_AE_MOVT32X2 + "ae_movt64", // XTENSA_INS_AE_MOVT64 + "ae_mul16x4", // XTENSA_INS_AE_MUL16X4 + "ae_mul32u_ll", // XTENSA_INS_AE_MUL32U_LL + "ae_mul32x16_h0", // XTENSA_INS_AE_MUL32X16_H0 + "ae_mul32x16_h0_s2", // XTENSA_INS_AE_MUL32X16_H0_S2 + "ae_mul32x16_h1", // XTENSA_INS_AE_MUL32X16_H1 + "ae_mul32x16_h1_s2", // XTENSA_INS_AE_MUL32X16_H1_S2 + "ae_mul32x16_h2", // XTENSA_INS_AE_MUL32X16_H2 + "ae_mul32x16_h2_s2", // XTENSA_INS_AE_MUL32X16_H2_S2 + "ae_mul32x16_h3", // XTENSA_INS_AE_MUL32X16_H3 + "ae_mul32x16_h3_s2", // XTENSA_INS_AE_MUL32X16_H3_S2 + "ae_mul32x16_l0", // XTENSA_INS_AE_MUL32X16_L0 + "ae_mul32x16_l0_s2", // XTENSA_INS_AE_MUL32X16_L0_S2 + "ae_mul32x16_l1", // XTENSA_INS_AE_MUL32X16_L1 + "ae_mul32x16_l1_s2", // XTENSA_INS_AE_MUL32X16_L1_S2 + "ae_mul32x16_l2", // XTENSA_INS_AE_MUL32X16_L2 + "ae_mul32x16_l2_s2", // XTENSA_INS_AE_MUL32X16_L2_S2 + "ae_mul32x16_l3", // XTENSA_INS_AE_MUL32X16_L3 + "ae_mul32x16_l3_s2", // XTENSA_INS_AE_MUL32X16_L3_S2 + "ae_mul32_hh", // XTENSA_INS_AE_MUL32_HH + "ae_mul32_lh", // XTENSA_INS_AE_MUL32_LH + "ae_mul32_ll", // XTENSA_INS_AE_MUL32_LL + "ae_mul32_ll_s2", // XTENSA_INS_AE_MUL32_LL_S2 + "ae_mula16x4", // XTENSA_INS_AE_MULA16X4 + "ae_mula32u_ll", // XTENSA_INS_AE_MULA32U_LL + "ae_mula32x16_h0", // XTENSA_INS_AE_MULA32X16_H0 + "ae_mula32x16_h0_s2", // XTENSA_INS_AE_MULA32X16_H0_S2 + "ae_mula32x16_h1", // XTENSA_INS_AE_MULA32X16_H1 + "ae_mula32x16_h1_s2", // XTENSA_INS_AE_MULA32X16_H1_S2 + "ae_mula32x16_h2", // XTENSA_INS_AE_MULA32X16_H2 + "ae_mula32x16_h2_s2", // XTENSA_INS_AE_MULA32X16_H2_S2 + "ae_mula32x16_h3", // XTENSA_INS_AE_MULA32X16_H3 + "ae_mula32x16_h3_s2", // XTENSA_INS_AE_MULA32X16_H3_S2 + "ae_mula32x16_l0", // XTENSA_INS_AE_MULA32X16_L0 + "ae_mula32x16_l0_s2", // XTENSA_INS_AE_MULA32X16_L0_S2 + "ae_mula32x16_l1", // XTENSA_INS_AE_MULA32X16_L1 + "ae_mula32x16_l1_s2", // XTENSA_INS_AE_MULA32X16_L1_S2 + "ae_mula32x16_l2", // XTENSA_INS_AE_MULA32X16_L2 + "ae_mula32x16_l2_s2", // XTENSA_INS_AE_MULA32X16_L2_S2 + "ae_mula32x16_l3", // XTENSA_INS_AE_MULA32X16_L3 + "ae_mula32x16_l3_s2", // XTENSA_INS_AE_MULA32X16_L3_S2 + "ae_mula32_hh", // XTENSA_INS_AE_MULA32_HH + "ae_mula32_lh", // XTENSA_INS_AE_MULA32_LH + "ae_mula32_ll", // XTENSA_INS_AE_MULA32_LL + "ae_mula32_ll_s2", // XTENSA_INS_AE_MULA32_LL_S2 + "ae_mulaad24_hh_ll", // XTENSA_INS_AE_MULAAD24_HH_LL + "ae_mulaad24_hh_ll_s2", // XTENSA_INS_AE_MULAAD24_HH_LL_S2 + "ae_mulaad24_hl_lh", // XTENSA_INS_AE_MULAAD24_HL_LH + "ae_mulaad24_hl_lh_s2", // XTENSA_INS_AE_MULAAD24_HL_LH_S2 + "ae_mulaad32x16_h0_l1", // XTENSA_INS_AE_MULAAD32X16_H0_L1 + "ae_mulaad32x16_h0_l1_s2", // XTENSA_INS_AE_MULAAD32X16_H0_L1_S2 + "ae_mulaad32x16_h1_l0", // XTENSA_INS_AE_MULAAD32X16_H1_L0 + "ae_mulaad32x16_h1_l0_s2", // XTENSA_INS_AE_MULAAD32X16_H1_L0_S2 + "ae_mulaad32x16_h2_l3", // XTENSA_INS_AE_MULAAD32X16_H2_L3 + "ae_mulaad32x16_h2_l3_s2", // XTENSA_INS_AE_MULAAD32X16_H2_L3_S2 + "ae_mulaad32x16_h3_l2", // XTENSA_INS_AE_MULAAD32X16_H3_L2 + "ae_mulaad32x16_h3_l2_s2", // XTENSA_INS_AE_MULAAD32X16_H3_L2_S2 + "ae_mulaafd16ss_11_00", // XTENSA_INS_AE_MULAAFD16SS_11_00 + "ae_mulaafd16ss_11_00_s2", // XTENSA_INS_AE_MULAAFD16SS_11_00_S2 + "ae_mulaafd16ss_13_02", // XTENSA_INS_AE_MULAAFD16SS_13_02 + "ae_mulaafd16ss_13_02_s2", // XTENSA_INS_AE_MULAAFD16SS_13_02_S2 + "ae_mulaafd16ss_33_22", // XTENSA_INS_AE_MULAAFD16SS_33_22 + "ae_mulaafd16ss_33_22_s2", // XTENSA_INS_AE_MULAAFD16SS_33_22_S2 + "ae_mulaafd24_hh_ll", // XTENSA_INS_AE_MULAAFD24_HH_LL + "ae_mulaafd24_hh_ll_s2", // XTENSA_INS_AE_MULAAFD24_HH_LL_S2 + "ae_mulaafd24_hl_lh", // XTENSA_INS_AE_MULAAFD24_HL_LH + "ae_mulaafd24_hl_lh_s2", // XTENSA_INS_AE_MULAAFD24_HL_LH_S2 + "ae_mulaafd32x16_h0_l1", // XTENSA_INS_AE_MULAAFD32X16_H0_L1 + "ae_mulaafd32x16_h0_l1_s2", // XTENSA_INS_AE_MULAAFD32X16_H0_L1_S2 + "ae_mulaafd32x16_h1_l0", // XTENSA_INS_AE_MULAAFD32X16_H1_L0 + "ae_mulaafd32x16_h1_l0_s2", // XTENSA_INS_AE_MULAAFD32X16_H1_L0_S2 + "ae_mulaafd32x16_h2_l3", // XTENSA_INS_AE_MULAAFD32X16_H2_L3 + "ae_mulaafd32x16_h2_l3_s2", // XTENSA_INS_AE_MULAAFD32X16_H2_L3_S2 + "ae_mulaafd32x16_h3_l2", // XTENSA_INS_AE_MULAAFD32X16_H3_L2 + "ae_mulaafd32x16_h3_l2_s2", // XTENSA_INS_AE_MULAAFD32X16_H3_L2_S2 + "ae_mulac24", // XTENSA_INS_AE_MULAC24 + "ae_mulac32x16_h", // XTENSA_INS_AE_MULAC32X16_H + "ae_mulac32x16_l", // XTENSA_INS_AE_MULAC32X16_L + "ae_mulaf16ss_00", // XTENSA_INS_AE_MULAF16SS_00 + "ae_mulaf16ss_00_s2", // XTENSA_INS_AE_MULAF16SS_00_S2 + "ae_mulaf16ss_10", // XTENSA_INS_AE_MULAF16SS_10 + "ae_mulaf16ss_11", // XTENSA_INS_AE_MULAF16SS_11 + "ae_mulaf16ss_20", // XTENSA_INS_AE_MULAF16SS_20 + "ae_mulaf16ss_21", // XTENSA_INS_AE_MULAF16SS_21 + "ae_mulaf16ss_22", // XTENSA_INS_AE_MULAF16SS_22 + "ae_mulaf16ss_30", // XTENSA_INS_AE_MULAF16SS_30 + "ae_mulaf16ss_31", // XTENSA_INS_AE_MULAF16SS_31 + "ae_mulaf16ss_32", // XTENSA_INS_AE_MULAF16SS_32 + "ae_mulaf16ss_33", // XTENSA_INS_AE_MULAF16SS_33 + "ae_mulaf16x4ss", // XTENSA_INS_AE_MULAF16X4SS + "ae_mulaf32r_hh", // XTENSA_INS_AE_MULAF32R_HH + "ae_mulaf32r_lh", // XTENSA_INS_AE_MULAF32R_LH + "ae_mulaf32r_ll", // XTENSA_INS_AE_MULAF32R_LL + "ae_mulaf32r_ll_s2", // XTENSA_INS_AE_MULAF32R_LL_S2 + "ae_mulaf32s_hh", // XTENSA_INS_AE_MULAF32S_HH + "ae_mulaf32s_lh", // XTENSA_INS_AE_MULAF32S_LH + "ae_mulaf32s_ll", // XTENSA_INS_AE_MULAF32S_LL + "ae_mulaf32s_ll_s2", // XTENSA_INS_AE_MULAF32S_LL_S2 + "ae_mulaf32x16_h0", // XTENSA_INS_AE_MULAF32X16_H0 + "ae_mulaf32x16_h0_s2", // XTENSA_INS_AE_MULAF32X16_H0_S2 + "ae_mulaf32x16_h1", // XTENSA_INS_AE_MULAF32X16_H1 + "ae_mulaf32x16_h1_s2", // XTENSA_INS_AE_MULAF32X16_H1_S2 + "ae_mulaf32x16_h2", // XTENSA_INS_AE_MULAF32X16_H2 + "ae_mulaf32x16_h2_s2", // XTENSA_INS_AE_MULAF32X16_H2_S2 + "ae_mulaf32x16_h3", // XTENSA_INS_AE_MULAF32X16_H3 + "ae_mulaf32x16_h3_s2", // XTENSA_INS_AE_MULAF32X16_H3_S2 + "ae_mulaf32x16_l0", // XTENSA_INS_AE_MULAF32X16_L0 + "ae_mulaf32x16_l0_s2", // XTENSA_INS_AE_MULAF32X16_L0_S2 + "ae_mulaf32x16_l1", // XTENSA_INS_AE_MULAF32X16_L1 + "ae_mulaf32x16_l1_s2", // XTENSA_INS_AE_MULAF32X16_L1_S2 + "ae_mulaf32x16_l2", // XTENSA_INS_AE_MULAF32X16_L2 + "ae_mulaf32x16_l2_s2", // XTENSA_INS_AE_MULAF32X16_L2_S2 + "ae_mulaf32x16_l3", // XTENSA_INS_AE_MULAF32X16_L3 + "ae_mulaf32x16_l3_s2", // XTENSA_INS_AE_MULAF32X16_L3_S2 + "ae_mulaf48q32sp16s_l", // XTENSA_INS_AE_MULAF48Q32SP16S_L + "ae_mulaf48q32sp16s_l_s2", // XTENSA_INS_AE_MULAF48Q32SP16S_L_S2 + "ae_mulaf48q32sp16u_l", // XTENSA_INS_AE_MULAF48Q32SP16U_L + "ae_mulaf48q32sp16u_l_s2", // XTENSA_INS_AE_MULAF48Q32SP16U_L_S2 + "ae_mulafc24ra", // XTENSA_INS_AE_MULAFC24RA + "ae_mulafc32x16ras_h", // XTENSA_INS_AE_MULAFC32X16RAS_H + "ae_mulafc32x16ras_l", // XTENSA_INS_AE_MULAFC32X16RAS_L + "ae_mulafd24x2_fir_h", // XTENSA_INS_AE_MULAFD24X2_FIR_H + "ae_mulafd24x2_fir_l", // XTENSA_INS_AE_MULAFD24X2_FIR_L + "ae_mulafd32x16x2_fir_hh", // XTENSA_INS_AE_MULAFD32X16X2_FIR_HH + "ae_mulafd32x16x2_fir_hl", // XTENSA_INS_AE_MULAFD32X16X2_FIR_HL + "ae_mulafd32x16x2_fir_lh", // XTENSA_INS_AE_MULAFD32X16X2_FIR_LH + "ae_mulafd32x16x2_fir_ll", // XTENSA_INS_AE_MULAFD32X16X2_FIR_LL + "ae_mulafp24x2r", // XTENSA_INS_AE_MULAFP24X2R + "ae_mulafp24x2ra", // XTENSA_INS_AE_MULAFP24X2RA + "ae_mulafp24x2ra_s2", // XTENSA_INS_AE_MULAFP24X2RA_S2 + "ae_mulafp24x2r_s2", // XTENSA_INS_AE_MULAFP24X2R_S2 + "ae_mulafp32x16x2ras_h", // XTENSA_INS_AE_MULAFP32X16X2RAS_H + "ae_mulafp32x16x2ras_h_s2", // XTENSA_INS_AE_MULAFP32X16X2RAS_H_S2 + "ae_mulafp32x16x2ras_l", // XTENSA_INS_AE_MULAFP32X16X2RAS_L + "ae_mulafp32x16x2ras_l_s2", // XTENSA_INS_AE_MULAFP32X16X2RAS_L_S2 + "ae_mulafp32x16x2rs_h", // XTENSA_INS_AE_MULAFP32X16X2RS_H + "ae_mulafp32x16x2rs_h_s2", // XTENSA_INS_AE_MULAFP32X16X2RS_H_S2 + "ae_mulafp32x16x2rs_l", // XTENSA_INS_AE_MULAFP32X16X2RS_L + "ae_mulafp32x16x2rs_l_s2", // XTENSA_INS_AE_MULAFP32X16X2RS_L_S2 + "ae_mulafp32x2ras", // XTENSA_INS_AE_MULAFP32X2RAS + "ae_mulafp32x2rs", // XTENSA_INS_AE_MULAFP32X2RS + "ae_mulafq32sp24s_h_s2", // XTENSA_INS_AE_MULAFQ32SP24S_H_S2 + "ae_mulafq32sp24s_l_s2", // XTENSA_INS_AE_MULAFQ32SP24S_L_S2 + "ae_mulap24x2", // XTENSA_INS_AE_MULAP24X2 + "ae_mulap24x2_s2", // XTENSA_INS_AE_MULAP24X2_S2 + "ae_mulap32x16x2_h", // XTENSA_INS_AE_MULAP32X16X2_H + "ae_mulap32x16x2_l", // XTENSA_INS_AE_MULAP32X16X2_L + "ae_mulap32x2", // XTENSA_INS_AE_MULAP32X2 + "ae_mulaq32sp16s_l_s2", // XTENSA_INS_AE_MULAQ32SP16S_L_S2 + "ae_mulaq32sp16u_l_s2", // XTENSA_INS_AE_MULAQ32SP16U_L_S2 + "ae_mularfq32sp24s_h_s2", // XTENSA_INS_AE_MULARFQ32SP24S_H_S2 + "ae_mularfq32sp24s_l_s2", // XTENSA_INS_AE_MULARFQ32SP24S_L_S2 + "ae_mulas32f48p16s_hh", // XTENSA_INS_AE_MULAS32F48P16S_HH + "ae_mulas32f48p16s_hh_s2", // XTENSA_INS_AE_MULAS32F48P16S_HH_S2 + "ae_mulas32f48p16s_lh", // XTENSA_INS_AE_MULAS32F48P16S_LH + "ae_mulas32f48p16s_lh_s2", // XTENSA_INS_AE_MULAS32F48P16S_LH_S2 + "ae_mulas32f48p16s_ll", // XTENSA_INS_AE_MULAS32F48P16S_LL + "ae_mulas32f48p16s_ll_s2", // XTENSA_INS_AE_MULAS32F48P16S_LL_S2 + "ae_mulasd24_hh_ll", // XTENSA_INS_AE_MULASD24_HH_LL + "ae_mulasd24_hh_ll_s2", // XTENSA_INS_AE_MULASD24_HH_LL_S2 + "ae_mulasd24_hl_lh", // XTENSA_INS_AE_MULASD24_HL_LH + "ae_mulasd24_hl_lh_s2", // XTENSA_INS_AE_MULASD24_HL_LH_S2 + "ae_mulasd32x16_h1_l0", // XTENSA_INS_AE_MULASD32X16_H1_L0 + "ae_mulasd32x16_h1_l0_s2", // XTENSA_INS_AE_MULASD32X16_H1_L0_S2 + "ae_mulasd32x16_h3_l2", // XTENSA_INS_AE_MULASD32X16_H3_L2 + "ae_mulasd32x16_h3_l2_s2", // XTENSA_INS_AE_MULASD32X16_H3_L2_S2 + "ae_mulasfd24_hh_ll", // XTENSA_INS_AE_MULASFD24_HH_LL + "ae_mulasfd24_hh_ll_s2", // XTENSA_INS_AE_MULASFD24_HH_LL_S2 + "ae_mulasfd24_hl_lh", // XTENSA_INS_AE_MULASFD24_HL_LH + "ae_mulasfd24_hl_lh_s2", // XTENSA_INS_AE_MULASFD24_HL_LH_S2 + "ae_mulasfd32x16_h1_l0", // XTENSA_INS_AE_MULASFD32X16_H1_L0 + "ae_mulasfd32x16_h1_l0_s2", // XTENSA_INS_AE_MULASFD32X16_H1_L0_S2 + "ae_mulasfd32x16_h3_l2", // XTENSA_INS_AE_MULASFD32X16_H3_L2 + "ae_mulasfd32x16_h3_l2_s2", // XTENSA_INS_AE_MULASFD32X16_H3_L2_S2 + "ae_mulc24", // XTENSA_INS_AE_MULC24 + "ae_mulc32x16_h", // XTENSA_INS_AE_MULC32X16_H + "ae_mulc32x16_l", // XTENSA_INS_AE_MULC32X16_L + "ae_mulf16ss_00", // XTENSA_INS_AE_MULF16SS_00 + "ae_mulf16ss_00_s2", // XTENSA_INS_AE_MULF16SS_00_S2 + "ae_mulf16ss_10", // XTENSA_INS_AE_MULF16SS_10 + "ae_mulf16ss_11", // XTENSA_INS_AE_MULF16SS_11 + "ae_mulf16ss_20", // XTENSA_INS_AE_MULF16SS_20 + "ae_mulf16ss_21", // XTENSA_INS_AE_MULF16SS_21 + "ae_mulf16ss_22", // XTENSA_INS_AE_MULF16SS_22 + "ae_mulf16ss_30", // XTENSA_INS_AE_MULF16SS_30 + "ae_mulf16ss_31", // XTENSA_INS_AE_MULF16SS_31 + "ae_mulf16ss_32", // XTENSA_INS_AE_MULF16SS_32 + "ae_mulf16ss_33", // XTENSA_INS_AE_MULF16SS_33 + "ae_mulf16x4ss", // XTENSA_INS_AE_MULF16X4SS + "ae_mulf32r_hh", // XTENSA_INS_AE_MULF32R_HH + "ae_mulf32r_lh", // XTENSA_INS_AE_MULF32R_LH + "ae_mulf32r_ll", // XTENSA_INS_AE_MULF32R_LL + "ae_mulf32r_ll_s2", // XTENSA_INS_AE_MULF32R_LL_S2 + "ae_mulf32s_hh", // XTENSA_INS_AE_MULF32S_HH + "ae_mulf32s_lh", // XTENSA_INS_AE_MULF32S_LH + "ae_mulf32s_ll", // XTENSA_INS_AE_MULF32S_LL + "ae_mulf32s_ll_s2", // XTENSA_INS_AE_MULF32S_LL_S2 + "ae_mulf32x16_h0", // XTENSA_INS_AE_MULF32X16_H0 + "ae_mulf32x16_h0_s2", // XTENSA_INS_AE_MULF32X16_H0_S2 + "ae_mulf32x16_h1", // XTENSA_INS_AE_MULF32X16_H1 + "ae_mulf32x16_h1_s2", // XTENSA_INS_AE_MULF32X16_H1_S2 + "ae_mulf32x16_h2", // XTENSA_INS_AE_MULF32X16_H2 + "ae_mulf32x16_h2_s2", // XTENSA_INS_AE_MULF32X16_H2_S2 + "ae_mulf32x16_h3", // XTENSA_INS_AE_MULF32X16_H3 + "ae_mulf32x16_h3_s2", // XTENSA_INS_AE_MULF32X16_H3_S2 + "ae_mulf32x16_l0", // XTENSA_INS_AE_MULF32X16_L0 + "ae_mulf32x16_l0_s2", // XTENSA_INS_AE_MULF32X16_L0_S2 + "ae_mulf32x16_l1", // XTENSA_INS_AE_MULF32X16_L1 + "ae_mulf32x16_l1_s2", // XTENSA_INS_AE_MULF32X16_L1_S2 + "ae_mulf32x16_l2", // XTENSA_INS_AE_MULF32X16_L2 + "ae_mulf32x16_l2_s2", // XTENSA_INS_AE_MULF32X16_L2_S2 + "ae_mulf32x16_l3", // XTENSA_INS_AE_MULF32X16_L3 + "ae_mulf32x16_l3_s2", // XTENSA_INS_AE_MULF32X16_L3_S2 + "ae_mulf48q32sp16s_l", // XTENSA_INS_AE_MULF48Q32SP16S_L + "ae_mulf48q32sp16s_l_s2", // XTENSA_INS_AE_MULF48Q32SP16S_L_S2 + "ae_mulf48q32sp16u_l", // XTENSA_INS_AE_MULF48Q32SP16U_L + "ae_mulf48q32sp16u_l_s2", // XTENSA_INS_AE_MULF48Q32SP16U_L_S2 + "ae_mulfc24ra", // XTENSA_INS_AE_MULFC24RA + "ae_mulfc32x16ras_h", // XTENSA_INS_AE_MULFC32X16RAS_H + "ae_mulfc32x16ras_l", // XTENSA_INS_AE_MULFC32X16RAS_L + "ae_mulfd24x2_fir_h", // XTENSA_INS_AE_MULFD24X2_FIR_H + "ae_mulfd24x2_fir_l", // XTENSA_INS_AE_MULFD24X2_FIR_L + "ae_mulfd32x16x2_fir_hh", // XTENSA_INS_AE_MULFD32X16X2_FIR_HH + "ae_mulfd32x16x2_fir_hl", // XTENSA_INS_AE_MULFD32X16X2_FIR_HL + "ae_mulfd32x16x2_fir_lh", // XTENSA_INS_AE_MULFD32X16X2_FIR_LH + "ae_mulfd32x16x2_fir_ll", // XTENSA_INS_AE_MULFD32X16X2_FIR_LL + "ae_mulfp16x4ras", // XTENSA_INS_AE_MULFP16X4RAS + "ae_mulfp16x4s", // XTENSA_INS_AE_MULFP16X4S + "ae_mulfp24x2r", // XTENSA_INS_AE_MULFP24X2R + "ae_mulfp24x2ra", // XTENSA_INS_AE_MULFP24X2RA + "ae_mulfp24x2ra_s2", // XTENSA_INS_AE_MULFP24X2RA_S2 + "ae_mulfp24x2r_s2", // XTENSA_INS_AE_MULFP24X2R_S2 + "ae_mulfp32x16x2ras_h", // XTENSA_INS_AE_MULFP32X16X2RAS_H + "ae_mulfp32x16x2ras_h_s2", // XTENSA_INS_AE_MULFP32X16X2RAS_H_S2 + "ae_mulfp32x16x2ras_l", // XTENSA_INS_AE_MULFP32X16X2RAS_L + "ae_mulfp32x16x2ras_l_s2", // XTENSA_INS_AE_MULFP32X16X2RAS_L_S2 + "ae_mulfp32x16x2rs_h", // XTENSA_INS_AE_MULFP32X16X2RS_H + "ae_mulfp32x16x2rs_h_s2", // XTENSA_INS_AE_MULFP32X16X2RS_H_S2 + "ae_mulfp32x16x2rs_l", // XTENSA_INS_AE_MULFP32X16X2RS_L + "ae_mulfp32x16x2rs_l_s2", // XTENSA_INS_AE_MULFP32X16X2RS_L_S2 + "ae_mulfp32x2ras", // XTENSA_INS_AE_MULFP32X2RAS + "ae_mulfp32x2rs", // XTENSA_INS_AE_MULFP32X2RS + "ae_mulfq32sp24s_h_s2", // XTENSA_INS_AE_MULFQ32SP24S_H_S2 + "ae_mulfq32sp24s_l_s2", // XTENSA_INS_AE_MULFQ32SP24S_L_S2 + "ae_mulp24x2", // XTENSA_INS_AE_MULP24X2 + "ae_mulp24x2_s2", // XTENSA_INS_AE_MULP24X2_S2 + "ae_mulp32x16x2_h", // XTENSA_INS_AE_MULP32X16X2_H + "ae_mulp32x16x2_l", // XTENSA_INS_AE_MULP32X16X2_L + "ae_mulp32x2", // XTENSA_INS_AE_MULP32X2 + "ae_mulq32sp16s_l_s2", // XTENSA_INS_AE_MULQ32SP16S_L_S2 + "ae_mulq32sp16u_l_s2", // XTENSA_INS_AE_MULQ32SP16U_L_S2 + "ae_mulrfq32sp24s_h_s2", // XTENSA_INS_AE_MULRFQ32SP24S_H_S2 + "ae_mulrfq32sp24s_l_s2", // XTENSA_INS_AE_MULRFQ32SP24S_L_S2 + "ae_muls16x4", // XTENSA_INS_AE_MULS16X4 + "ae_muls32f48p16s_hh", // XTENSA_INS_AE_MULS32F48P16S_HH + "ae_muls32f48p16s_hh_s2", // XTENSA_INS_AE_MULS32F48P16S_HH_S2 + "ae_muls32f48p16s_lh", // XTENSA_INS_AE_MULS32F48P16S_LH + "ae_muls32f48p16s_lh_s2", // XTENSA_INS_AE_MULS32F48P16S_LH_S2 + "ae_muls32f48p16s_ll", // XTENSA_INS_AE_MULS32F48P16S_LL + "ae_muls32f48p16s_ll_s2", // XTENSA_INS_AE_MULS32F48P16S_LL_S2 + "ae_muls32u_ll", // XTENSA_INS_AE_MULS32U_LL + "ae_muls32x16_h0", // XTENSA_INS_AE_MULS32X16_H0 + "ae_muls32x16_h0_s2", // XTENSA_INS_AE_MULS32X16_H0_S2 + "ae_muls32x16_h1", // XTENSA_INS_AE_MULS32X16_H1 + "ae_muls32x16_h1_s2", // XTENSA_INS_AE_MULS32X16_H1_S2 + "ae_muls32x16_h2", // XTENSA_INS_AE_MULS32X16_H2 + "ae_muls32x16_h2_s2", // XTENSA_INS_AE_MULS32X16_H2_S2 + "ae_muls32x16_h3", // XTENSA_INS_AE_MULS32X16_H3 + "ae_muls32x16_h3_s2", // XTENSA_INS_AE_MULS32X16_H3_S2 + "ae_muls32x16_l0", // XTENSA_INS_AE_MULS32X16_L0 + "ae_muls32x16_l0_s2", // XTENSA_INS_AE_MULS32X16_L0_S2 + "ae_muls32x16_l1", // XTENSA_INS_AE_MULS32X16_L1 + "ae_muls32x16_l1_s2", // XTENSA_INS_AE_MULS32X16_L1_S2 + "ae_muls32x16_l2", // XTENSA_INS_AE_MULS32X16_L2 + "ae_muls32x16_l2_s2", // XTENSA_INS_AE_MULS32X16_L2_S2 + "ae_muls32x16_l3", // XTENSA_INS_AE_MULS32X16_L3 + "ae_muls32x16_l3_s2", // XTENSA_INS_AE_MULS32X16_L3_S2 + "ae_muls32_hh", // XTENSA_INS_AE_MULS32_HH + "ae_muls32_lh", // XTENSA_INS_AE_MULS32_LH + "ae_muls32_ll", // XTENSA_INS_AE_MULS32_LL + "ae_mulsad24_hh_ll", // XTENSA_INS_AE_MULSAD24_HH_LL + "ae_mulsad24_hh_ll_s2", // XTENSA_INS_AE_MULSAD24_HH_LL_S2 + "ae_mulsad32x16_h1_l0", // XTENSA_INS_AE_MULSAD32X16_H1_L0 + "ae_mulsad32x16_h1_l0_s2", // XTENSA_INS_AE_MULSAD32X16_H1_L0_S2 + "ae_mulsad32x16_h3_l2", // XTENSA_INS_AE_MULSAD32X16_H3_L2 + "ae_mulsad32x16_h3_l2_s2", // XTENSA_INS_AE_MULSAD32X16_H3_L2_S2 + "ae_mulsafd24_hh_ll", // XTENSA_INS_AE_MULSAFD24_HH_LL + "ae_mulsafd24_hh_ll_s2", // XTENSA_INS_AE_MULSAFD24_HH_LL_S2 + "ae_mulsafd32x16_h1_l0", // XTENSA_INS_AE_MULSAFD32X16_H1_L0 + "ae_mulsafd32x16_h1_l0_s2", // XTENSA_INS_AE_MULSAFD32X16_H1_L0_S2 + "ae_mulsafd32x16_h3_l2", // XTENSA_INS_AE_MULSAFD32X16_H3_L2 + "ae_mulsafd32x16_h3_l2_s2", // XTENSA_INS_AE_MULSAFD32X16_H3_L2_S2 + "ae_mulsf16ss_00", // XTENSA_INS_AE_MULSF16SS_00 + "ae_mulsf16ss_00_s2", // XTENSA_INS_AE_MULSF16SS_00_S2 + "ae_mulsf16ss_10", // XTENSA_INS_AE_MULSF16SS_10 + "ae_mulsf16ss_11", // XTENSA_INS_AE_MULSF16SS_11 + "ae_mulsf16ss_20", // XTENSA_INS_AE_MULSF16SS_20 + "ae_mulsf16ss_21", // XTENSA_INS_AE_MULSF16SS_21 + "ae_mulsf16ss_22", // XTENSA_INS_AE_MULSF16SS_22 + "ae_mulsf16ss_30", // XTENSA_INS_AE_MULSF16SS_30 + "ae_mulsf16ss_31", // XTENSA_INS_AE_MULSF16SS_31 + "ae_mulsf16ss_32", // XTENSA_INS_AE_MULSF16SS_32 + "ae_mulsf16ss_33", // XTENSA_INS_AE_MULSF16SS_33 + "ae_mulsf16x4ss", // XTENSA_INS_AE_MULSF16X4SS + "ae_mulsf32r_hh", // XTENSA_INS_AE_MULSF32R_HH + "ae_mulsf32r_lh", // XTENSA_INS_AE_MULSF32R_LH + "ae_mulsf32r_ll", // XTENSA_INS_AE_MULSF32R_LL + "ae_mulsf32r_ll_s2", // XTENSA_INS_AE_MULSF32R_LL_S2 + "ae_mulsf32s_hh", // XTENSA_INS_AE_MULSF32S_HH + "ae_mulsf32s_lh", // XTENSA_INS_AE_MULSF32S_LH + "ae_mulsf32s_ll", // XTENSA_INS_AE_MULSF32S_LL + "ae_mulsf32x16_h0", // XTENSA_INS_AE_MULSF32X16_H0 + "ae_mulsf32x16_h0_s2", // XTENSA_INS_AE_MULSF32X16_H0_S2 + "ae_mulsf32x16_h1", // XTENSA_INS_AE_MULSF32X16_H1 + "ae_mulsf32x16_h1_s2", // XTENSA_INS_AE_MULSF32X16_H1_S2 + "ae_mulsf32x16_h2", // XTENSA_INS_AE_MULSF32X16_H2 + "ae_mulsf32x16_h2_s2", // XTENSA_INS_AE_MULSF32X16_H2_S2 + "ae_mulsf32x16_h3", // XTENSA_INS_AE_MULSF32X16_H3 + "ae_mulsf32x16_h3_s2", // XTENSA_INS_AE_MULSF32X16_H3_S2 + "ae_mulsf32x16_l0", // XTENSA_INS_AE_MULSF32X16_L0 + "ae_mulsf32x16_l0_s2", // XTENSA_INS_AE_MULSF32X16_L0_S2 + "ae_mulsf32x16_l1", // XTENSA_INS_AE_MULSF32X16_L1 + "ae_mulsf32x16_l1_s2", // XTENSA_INS_AE_MULSF32X16_L1_S2 + "ae_mulsf32x16_l2", // XTENSA_INS_AE_MULSF32X16_L2 + "ae_mulsf32x16_l2_s2", // XTENSA_INS_AE_MULSF32X16_L2_S2 + "ae_mulsf32x16_l3", // XTENSA_INS_AE_MULSF32X16_L3 + "ae_mulsf32x16_l3_s2", // XTENSA_INS_AE_MULSF32X16_L3_S2 + "ae_mulsf48q32sp16s_l", // XTENSA_INS_AE_MULSF48Q32SP16S_L + "ae_mulsf48q32sp16s_l_s2", // XTENSA_INS_AE_MULSF48Q32SP16S_L_S2 + "ae_mulsf48q32sp16u_l", // XTENSA_INS_AE_MULSF48Q32SP16U_L + "ae_mulsf48q32sp16u_l_s2", // XTENSA_INS_AE_MULSF48Q32SP16U_L_S2 + "ae_mulsfp24x2r", // XTENSA_INS_AE_MULSFP24X2R + "ae_mulsfp24x2ra", // XTENSA_INS_AE_MULSFP24X2RA + "ae_mulsfp24x2ra_s2", // XTENSA_INS_AE_MULSFP24X2RA_S2 + "ae_mulsfp24x2r_s2", // XTENSA_INS_AE_MULSFP24X2R_S2 + "ae_mulsfp32x16x2ras_h", // XTENSA_INS_AE_MULSFP32X16X2RAS_H + "ae_mulsfp32x16x2ras_h_s2", // XTENSA_INS_AE_MULSFP32X16X2RAS_H_S2 + "ae_mulsfp32x16x2ras_l", // XTENSA_INS_AE_MULSFP32X16X2RAS_L + "ae_mulsfp32x16x2ras_l_s2", // XTENSA_INS_AE_MULSFP32X16X2RAS_L_S2 + "ae_mulsfp32x16x2rs_h", // XTENSA_INS_AE_MULSFP32X16X2RS_H + "ae_mulsfp32x16x2rs_h_s2", // XTENSA_INS_AE_MULSFP32X16X2RS_H_S2 + "ae_mulsfp32x16x2rs_l", // XTENSA_INS_AE_MULSFP32X16X2RS_L + "ae_mulsfp32x16x2rs_l_s2", // XTENSA_INS_AE_MULSFP32X16X2RS_L_S2 + "ae_mulsfp32x2ras", // XTENSA_INS_AE_MULSFP32X2RAS + "ae_mulsfp32x2rs", // XTENSA_INS_AE_MULSFP32X2RS + "ae_mulsfq32sp24s_h_s2", // XTENSA_INS_AE_MULSFQ32SP24S_H_S2 + "ae_mulsfq32sp24s_l_s2", // XTENSA_INS_AE_MULSFQ32SP24S_L_S2 + "ae_mulsp24x2", // XTENSA_INS_AE_MULSP24X2 + "ae_mulsp24x2_s2", // XTENSA_INS_AE_MULSP24X2_S2 + "ae_mulsp32x16x2_h", // XTENSA_INS_AE_MULSP32X16X2_H + "ae_mulsp32x16x2_l", // XTENSA_INS_AE_MULSP32X16X2_L + "ae_mulsp32x2", // XTENSA_INS_AE_MULSP32X2 + "ae_mulsq32sp16s_l_s2", // XTENSA_INS_AE_MULSQ32SP16S_L_S2 + "ae_mulsq32sp16u_l_s2", // XTENSA_INS_AE_MULSQ32SP16U_L_S2 + "ae_mulsrfq32sp24s_h_s2", // XTENSA_INS_AE_MULSRFQ32SP24S_H_S2 + "ae_mulsrfq32sp24s_l_s2", // XTENSA_INS_AE_MULSRFQ32SP24S_L_S2 + "ae_mulss32f48p16s_hh", // XTENSA_INS_AE_MULSS32F48P16S_HH + "ae_mulss32f48p16s_hh_s2", // XTENSA_INS_AE_MULSS32F48P16S_HH_S2 + "ae_mulss32f48p16s_lh", // XTENSA_INS_AE_MULSS32F48P16S_LH + "ae_mulss32f48p16s_lh_s2", // XTENSA_INS_AE_MULSS32F48P16S_LH_S2 + "ae_mulss32f48p16s_ll", // XTENSA_INS_AE_MULSS32F48P16S_LL + "ae_mulss32f48p16s_ll_s2", // XTENSA_INS_AE_MULSS32F48P16S_LL_S2 + "ae_mulssd24_hh_ll", // XTENSA_INS_AE_MULSSD24_HH_LL + "ae_mulssd24_hh_ll_s2", // XTENSA_INS_AE_MULSSD24_HH_LL_S2 + "ae_mulssd24_hl_lh", // XTENSA_INS_AE_MULSSD24_HL_LH + "ae_mulssd24_hl_lh_s2", // XTENSA_INS_AE_MULSSD24_HL_LH_S2 + "ae_mulssd32x16_h1_l0", // XTENSA_INS_AE_MULSSD32X16_H1_L0 + "ae_mulssd32x16_h1_l0_s2", // XTENSA_INS_AE_MULSSD32X16_H1_L0_S2 + "ae_mulssd32x16_h3_l2", // XTENSA_INS_AE_MULSSD32X16_H3_L2 + "ae_mulssd32x16_h3_l2_s2", // XTENSA_INS_AE_MULSSD32X16_H3_L2_S2 + "ae_mulssfd16ss_11_00", // XTENSA_INS_AE_MULSSFD16SS_11_00 + "ae_mulssfd16ss_11_00_s2", // XTENSA_INS_AE_MULSSFD16SS_11_00_S2 + "ae_mulssfd16ss_13_02", // XTENSA_INS_AE_MULSSFD16SS_13_02 + "ae_mulssfd16ss_13_02_s2", // XTENSA_INS_AE_MULSSFD16SS_13_02_S2 + "ae_mulssfd16ss_33_22", // XTENSA_INS_AE_MULSSFD16SS_33_22 + "ae_mulssfd16ss_33_22_s2", // XTENSA_INS_AE_MULSSFD16SS_33_22_S2 + "ae_mulssfd24_hh_ll", // XTENSA_INS_AE_MULSSFD24_HH_LL + "ae_mulssfd24_hh_ll_s2", // XTENSA_INS_AE_MULSSFD24_HH_LL_S2 + "ae_mulssfd24_hl_lh", // XTENSA_INS_AE_MULSSFD24_HL_LH + "ae_mulssfd24_hl_lh_s2", // XTENSA_INS_AE_MULSSFD24_HL_LH_S2 + "ae_mulssfd32x16_h1_l0", // XTENSA_INS_AE_MULSSFD32X16_H1_L0 + "ae_mulssfd32x16_h1_l0_s2", // XTENSA_INS_AE_MULSSFD32X16_H1_L0_S2 + "ae_mulssfd32x16_h3_l2", // XTENSA_INS_AE_MULSSFD32X16_H3_L2 + "ae_mulssfd32x16_h3_l2_s2", // XTENSA_INS_AE_MULSSFD32X16_H3_L2_S2 + "ae_mulzaad24_hh_ll", // XTENSA_INS_AE_MULZAAD24_HH_LL + "ae_mulzaad24_hh_ll_s2", // XTENSA_INS_AE_MULZAAD24_HH_LL_S2 + "ae_mulzaad24_hl_lh", // XTENSA_INS_AE_MULZAAD24_HL_LH + "ae_mulzaad24_hl_lh_s2", // XTENSA_INS_AE_MULZAAD24_HL_LH_S2 + "ae_mulzaad32x16_h0_l1", // XTENSA_INS_AE_MULZAAD32X16_H0_L1 + "ae_mulzaad32x16_h0_l1_s2", // XTENSA_INS_AE_MULZAAD32X16_H0_L1_S2 + "ae_mulzaad32x16_h1_l0", // XTENSA_INS_AE_MULZAAD32X16_H1_L0 + "ae_mulzaad32x16_h1_l0_s2", // XTENSA_INS_AE_MULZAAD32X16_H1_L0_S2 + "ae_mulzaad32x16_h2_l3", // XTENSA_INS_AE_MULZAAD32X16_H2_L3 + "ae_mulzaad32x16_h2_l3_s2", // XTENSA_INS_AE_MULZAAD32X16_H2_L3_S2 + "ae_mulzaad32x16_h3_l2", // XTENSA_INS_AE_MULZAAD32X16_H3_L2 + "ae_mulzaad32x16_h3_l2_s2", // XTENSA_INS_AE_MULZAAD32X16_H3_L2_S2 + "ae_mulzaafd16ss_11_00", // XTENSA_INS_AE_MULZAAFD16SS_11_00 + "ae_mulzaafd16ss_11_00_s2", // XTENSA_INS_AE_MULZAAFD16SS_11_00_S2 + "ae_mulzaafd16ss_13_02", // XTENSA_INS_AE_MULZAAFD16SS_13_02 + "ae_mulzaafd16ss_13_02_s2", // XTENSA_INS_AE_MULZAAFD16SS_13_02_S2 + "ae_mulzaafd16ss_33_22", // XTENSA_INS_AE_MULZAAFD16SS_33_22 + "ae_mulzaafd16ss_33_22_s2", // XTENSA_INS_AE_MULZAAFD16SS_33_22_S2 + "ae_mulzaafd24_hh_ll", // XTENSA_INS_AE_MULZAAFD24_HH_LL + "ae_mulzaafd24_hh_ll_s2", // XTENSA_INS_AE_MULZAAFD24_HH_LL_S2 + "ae_mulzaafd24_hl_lh", // XTENSA_INS_AE_MULZAAFD24_HL_LH + "ae_mulzaafd24_hl_lh_s2", // XTENSA_INS_AE_MULZAAFD24_HL_LH_S2 + "ae_mulzaafd32x16_h0_l1", // XTENSA_INS_AE_MULZAAFD32X16_H0_L1 + "ae_mulzaafd32x16_h0_l1_s2", // XTENSA_INS_AE_MULZAAFD32X16_H0_L1_S2 + "ae_mulzaafd32x16_h1_l0", // XTENSA_INS_AE_MULZAAFD32X16_H1_L0 + "ae_mulzaafd32x16_h1_l0_s2", // XTENSA_INS_AE_MULZAAFD32X16_H1_L0_S2 + "ae_mulzaafd32x16_h2_l3", // XTENSA_INS_AE_MULZAAFD32X16_H2_L3 + "ae_mulzaafd32x16_h2_l3_s2", // XTENSA_INS_AE_MULZAAFD32X16_H2_L3_S2 + "ae_mulzaafd32x16_h3_l2", // XTENSA_INS_AE_MULZAAFD32X16_H3_L2 + "ae_mulzaafd32x16_h3_l2_s2", // XTENSA_INS_AE_MULZAAFD32X16_H3_L2_S2 + "ae_mulzasd24_hh_ll", // XTENSA_INS_AE_MULZASD24_HH_LL + "ae_mulzasd24_hh_ll_s2", // XTENSA_INS_AE_MULZASD24_HH_LL_S2 + "ae_mulzasd24_hl_lh", // XTENSA_INS_AE_MULZASD24_HL_LH + "ae_mulzasd24_hl_lh_s2", // XTENSA_INS_AE_MULZASD24_HL_LH_S2 + "ae_mulzasd32x16_h1_l0", // XTENSA_INS_AE_MULZASD32X16_H1_L0 + "ae_mulzasd32x16_h1_l0_s2", // XTENSA_INS_AE_MULZASD32X16_H1_L0_S2 + "ae_mulzasd32x16_h3_l2", // XTENSA_INS_AE_MULZASD32X16_H3_L2 + "ae_mulzasd32x16_h3_l2_s2", // XTENSA_INS_AE_MULZASD32X16_H3_L2_S2 + "ae_mulzasfd24_hh_ll", // XTENSA_INS_AE_MULZASFD24_HH_LL + "ae_mulzasfd24_hh_ll_s2", // XTENSA_INS_AE_MULZASFD24_HH_LL_S2 + "ae_mulzasfd24_hl_lh", // XTENSA_INS_AE_MULZASFD24_HL_LH + "ae_mulzasfd24_hl_lh_s2", // XTENSA_INS_AE_MULZASFD24_HL_LH_S2 + "ae_mulzasfd32x16_h1_l0", // XTENSA_INS_AE_MULZASFD32X16_H1_L0 + "ae_mulzasfd32x16_h1_l0_s2", // XTENSA_INS_AE_MULZASFD32X16_H1_L0_S2 + "ae_mulzasfd32x16_h3_l2", // XTENSA_INS_AE_MULZASFD32X16_H3_L2 + "ae_mulzasfd32x16_h3_l2_s2", // XTENSA_INS_AE_MULZASFD32X16_H3_L2_S2 + "ae_mulzsad24_hh_ll", // XTENSA_INS_AE_MULZSAD24_HH_LL + "ae_mulzsad24_hh_ll_s2", // XTENSA_INS_AE_MULZSAD24_HH_LL_S2 + "ae_mulzsad32x16_h1_l0", // XTENSA_INS_AE_MULZSAD32X16_H1_L0 + "ae_mulzsad32x16_h1_l0_s2", // XTENSA_INS_AE_MULZSAD32X16_H1_L0_S2 + "ae_mulzsad32x16_h3_l2", // XTENSA_INS_AE_MULZSAD32X16_H3_L2 + "ae_mulzsad32x16_h3_l2_s2", // XTENSA_INS_AE_MULZSAD32X16_H3_L2_S2 + "ae_mulzsafd24_hh_ll", // XTENSA_INS_AE_MULZSAFD24_HH_LL + "ae_mulzsafd24_hh_ll_s2", // XTENSA_INS_AE_MULZSAFD24_HH_LL_S2 + "ae_mulzsafd32x16_h1_l0", // XTENSA_INS_AE_MULZSAFD32X16_H1_L0 + "ae_mulzsafd32x16_h1_l0_s2", // XTENSA_INS_AE_MULZSAFD32X16_H1_L0_S2 + "ae_mulzsafd32x16_h3_l2", // XTENSA_INS_AE_MULZSAFD32X16_H3_L2 + "ae_mulzsafd32x16_h3_l2_s2", // XTENSA_INS_AE_MULZSAFD32X16_H3_L2_S2 + "ae_mulzssd24_hh_ll", // XTENSA_INS_AE_MULZSSD24_HH_LL + "ae_mulzssd24_hh_ll_s2", // XTENSA_INS_AE_MULZSSD24_HH_LL_S2 + "ae_mulzssd24_hl_lh", // XTENSA_INS_AE_MULZSSD24_HL_LH + "ae_mulzssd24_hl_lh_s2", // XTENSA_INS_AE_MULZSSD24_HL_LH_S2 + "ae_mulzssd32x16_h1_l0", // XTENSA_INS_AE_MULZSSD32X16_H1_L0 + "ae_mulzssd32x16_h1_l0_s2", // XTENSA_INS_AE_MULZSSD32X16_H1_L0_S2 + "ae_mulzssd32x16_h3_l2", // XTENSA_INS_AE_MULZSSD32X16_H3_L2 + "ae_mulzssd32x16_h3_l2_s2", // XTENSA_INS_AE_MULZSSD32X16_H3_L2_S2 + "ae_mulzssfd16ss_11_00", // XTENSA_INS_AE_MULZSSFD16SS_11_00 + "ae_mulzssfd16ss_11_00_s2", // XTENSA_INS_AE_MULZSSFD16SS_11_00_S2 + "ae_mulzssfd16ss_13_02", // XTENSA_INS_AE_MULZSSFD16SS_13_02 + "ae_mulzssfd16ss_13_02_s2", // XTENSA_INS_AE_MULZSSFD16SS_13_02_S2 + "ae_mulzssfd16ss_33_22", // XTENSA_INS_AE_MULZSSFD16SS_33_22 + "ae_mulzssfd16ss_33_22_s2", // XTENSA_INS_AE_MULZSSFD16SS_33_22_S2 + "ae_mulzssfd24_hh_ll", // XTENSA_INS_AE_MULZSSFD24_HH_LL + "ae_mulzssfd24_hh_ll_s2", // XTENSA_INS_AE_MULZSSFD24_HH_LL_S2 + "ae_mulzssfd24_hl_lh", // XTENSA_INS_AE_MULZSSFD24_HL_LH + "ae_mulzssfd24_hl_lh_s2", // XTENSA_INS_AE_MULZSSFD24_HL_LH_S2 + "ae_mulzssfd32x16_h1_l0", // XTENSA_INS_AE_MULZSSFD32X16_H1_L0 + "ae_mulzssfd32x16_h1_l0_s2", // XTENSA_INS_AE_MULZSSFD32X16_H1_L0_S2 + "ae_mulzssfd32x16_h3_l2", // XTENSA_INS_AE_MULZSSFD32X16_H3_L2 + "ae_mulzssfd32x16_h3_l2_s2", // XTENSA_INS_AE_MULZSSFD32X16_H3_L2_S2 + "ae_nand", // XTENSA_INS_AE_NAND + "ae_neg16s", // XTENSA_INS_AE_NEG16S + "ae_neg24s", // XTENSA_INS_AE_NEG24S + "ae_neg32", // XTENSA_INS_AE_NEG32 + "ae_neg32s", // XTENSA_INS_AE_NEG32S + "ae_neg64", // XTENSA_INS_AE_NEG64 + "ae_neg64s", // XTENSA_INS_AE_NEG64S + "ae_nsa64", // XTENSA_INS_AE_NSA64 + "ae_nsaz16_0", // XTENSA_INS_AE_NSAZ16_0 + "ae_nsaz32_l", // XTENSA_INS_AE_NSAZ32_L + "ae_or", // XTENSA_INS_AE_OR + "ae_pksr24", // XTENSA_INS_AE_PKSR24 + "ae_pksr32", // XTENSA_INS_AE_PKSR32 + "ae_round16x4f32sasym", // XTENSA_INS_AE_ROUND16X4F32SASYM + "ae_round16x4f32ssym", // XTENSA_INS_AE_ROUND16X4F32SSYM + "ae_round24x2f48sasym", // XTENSA_INS_AE_ROUND24X2F48SASYM + "ae_round24x2f48ssym", // XTENSA_INS_AE_ROUND24X2F48SSYM + "ae_round32x2f48sasym", // XTENSA_INS_AE_ROUND32X2F48SASYM + "ae_round32x2f48ssym", // XTENSA_INS_AE_ROUND32X2F48SSYM + "ae_round32x2f64sasym", // XTENSA_INS_AE_ROUND32X2F64SASYM + "ae_round32x2f64ssym", // XTENSA_INS_AE_ROUND32X2F64SSYM + "ae_roundsp16f24asym", // XTENSA_INS_AE_ROUNDSP16F24ASYM + "ae_roundsp16f24sym", // XTENSA_INS_AE_ROUNDSP16F24SYM + "ae_roundsp16q48x2asym", // XTENSA_INS_AE_ROUNDSP16Q48X2ASYM + "ae_roundsp16q48x2sym", // XTENSA_INS_AE_ROUNDSP16Q48X2SYM + "ae_roundsq32f48asym", // XTENSA_INS_AE_ROUNDSQ32F48ASYM + "ae_roundsq32f48sym", // XTENSA_INS_AE_ROUNDSQ32F48SYM + "ae_s16m_l_i", // XTENSA_INS_AE_S16M_L_I + "ae_s16m_l_iu", // XTENSA_INS_AE_S16M_L_IU + "ae_s16m_l_x", // XTENSA_INS_AE_S16M_L_X + "ae_s16m_l_xc", // XTENSA_INS_AE_S16M_L_XC + "ae_s16m_l_xu", // XTENSA_INS_AE_S16M_L_XU + "ae_s16x2m_i", // XTENSA_INS_AE_S16X2M_I + "ae_s16x2m_iu", // XTENSA_INS_AE_S16X2M_IU + "ae_s16x2m_x", // XTENSA_INS_AE_S16X2M_X + "ae_s16x2m_xc", // XTENSA_INS_AE_S16X2M_XC + "ae_s16x2m_xu", // XTENSA_INS_AE_S16X2M_XU + "ae_s16x4_i", // XTENSA_INS_AE_S16X4_I + "ae_s16x4_ip", // XTENSA_INS_AE_S16X4_IP + "ae_s16x4_ric", // XTENSA_INS_AE_S16X4_RIC + "ae_s16x4_rip", // XTENSA_INS_AE_S16X4_RIP + "ae_s16x4_x", // XTENSA_INS_AE_S16X4_X + "ae_s16x4_xc", // XTENSA_INS_AE_S16X4_XC + "ae_s16x4_xp", // XTENSA_INS_AE_S16X4_XP + "ae_s16_0_i", // XTENSA_INS_AE_S16_0_I + "ae_s16_0_ip", // XTENSA_INS_AE_S16_0_IP + "ae_s16_0_x", // XTENSA_INS_AE_S16_0_X + "ae_s16_0_xc", // XTENSA_INS_AE_S16_0_XC + "ae_s16_0_xp", // XTENSA_INS_AE_S16_0_XP + "ae_s24ra64s_i", // XTENSA_INS_AE_S24RA64S_I + "ae_s24ra64s_ip", // XTENSA_INS_AE_S24RA64S_IP + "ae_s24ra64s_x", // XTENSA_INS_AE_S24RA64S_X + "ae_s24ra64s_xc", // XTENSA_INS_AE_S24RA64S_XC + "ae_s24ra64s_xp", // XTENSA_INS_AE_S24RA64S_XP + "ae_s24x2ra64s_ip", // XTENSA_INS_AE_S24X2RA64S_IP + "ae_s32f24_l_i", // XTENSA_INS_AE_S32F24_L_I + "ae_s32f24_l_ip", // XTENSA_INS_AE_S32F24_L_IP + "ae_s32f24_l_x", // XTENSA_INS_AE_S32F24_L_X + "ae_s32f24_l_xc", // XTENSA_INS_AE_S32F24_L_XC + "ae_s32f24_l_xp", // XTENSA_INS_AE_S32F24_L_XP + "ae_s32m_i", // XTENSA_INS_AE_S32M_I + "ae_s32m_iu", // XTENSA_INS_AE_S32M_IU + "ae_s32m_x", // XTENSA_INS_AE_S32M_X + "ae_s32m_xc", // XTENSA_INS_AE_S32M_XC + "ae_s32m_xu", // XTENSA_INS_AE_S32M_XU + "ae_s32ra64s_i", // XTENSA_INS_AE_S32RA64S_I + "ae_s32ra64s_ip", // XTENSA_INS_AE_S32RA64S_IP + "ae_s32ra64s_x", // XTENSA_INS_AE_S32RA64S_X + "ae_s32ra64s_xc", // XTENSA_INS_AE_S32RA64S_XC + "ae_s32ra64s_xp", // XTENSA_INS_AE_S32RA64S_XP + "ae_s32x2f24_i", // XTENSA_INS_AE_S32X2F24_I + "ae_s32x2f24_ip", // XTENSA_INS_AE_S32X2F24_IP + "ae_s32x2f24_ric", // XTENSA_INS_AE_S32X2F24_RIC + "ae_s32x2f24_rip", // XTENSA_INS_AE_S32X2F24_RIP + "ae_s32x2f24_x", // XTENSA_INS_AE_S32X2F24_X + "ae_s32x2f24_xc", // XTENSA_INS_AE_S32X2F24_XC + "ae_s32x2f24_xp", // XTENSA_INS_AE_S32X2F24_XP + "ae_s32x2ra64s_ip", // XTENSA_INS_AE_S32X2RA64S_IP + "ae_s32x2_i", // XTENSA_INS_AE_S32X2_I + "ae_s32x2_ip", // XTENSA_INS_AE_S32X2_IP + "ae_s32x2_ric", // XTENSA_INS_AE_S32X2_RIC + "ae_s32x2_rip", // XTENSA_INS_AE_S32X2_RIP + "ae_s32x2_x", // XTENSA_INS_AE_S32X2_X + "ae_s32x2_xc", // XTENSA_INS_AE_S32X2_XC + "ae_s32x2_xp", // XTENSA_INS_AE_S32X2_XP + "ae_s32_l_i", // XTENSA_INS_AE_S32_L_I + "ae_s32_l_ip", // XTENSA_INS_AE_S32_L_IP + "ae_s32_l_x", // XTENSA_INS_AE_S32_L_X + "ae_s32_l_xc", // XTENSA_INS_AE_S32_L_XC + "ae_s32_l_xp", // XTENSA_INS_AE_S32_L_XP + "ae_s64_i", // XTENSA_INS_AE_S64_I + "ae_s64_ip", // XTENSA_INS_AE_S64_IP + "ae_s64_x", // XTENSA_INS_AE_S64_X + "ae_s64_xc", // XTENSA_INS_AE_S64_XC + "ae_s64_xp", // XTENSA_INS_AE_S64_XP + "ae_sa16x4_ic", // XTENSA_INS_AE_SA16X4_IC + "ae_sa16x4_ip", // XTENSA_INS_AE_SA16X4_IP + "ae_sa16x4_ric", // XTENSA_INS_AE_SA16X4_RIC + "ae_sa16x4_rip", // XTENSA_INS_AE_SA16X4_RIP + "ae_sa24x2_ic", // XTENSA_INS_AE_SA24X2_IC + "ae_sa24x2_ip", // XTENSA_INS_AE_SA24X2_IP + "ae_sa24x2_ric", // XTENSA_INS_AE_SA24X2_RIC + "ae_sa24x2_rip", // XTENSA_INS_AE_SA24X2_RIP + "ae_sa24_l_ic", // XTENSA_INS_AE_SA24_L_IC + "ae_sa24_l_ip", // XTENSA_INS_AE_SA24_L_IP + "ae_sa24_l_ric", // XTENSA_INS_AE_SA24_L_RIC + "ae_sa24_l_rip", // XTENSA_INS_AE_SA24_L_RIP + "ae_sa32x2f24_ic", // XTENSA_INS_AE_SA32X2F24_IC + "ae_sa32x2f24_ip", // XTENSA_INS_AE_SA32X2F24_IP + "ae_sa32x2f24_ric", // XTENSA_INS_AE_SA32X2F24_RIC + "ae_sa32x2f24_rip", // XTENSA_INS_AE_SA32X2F24_RIP + "ae_sa32x2_ic", // XTENSA_INS_AE_SA32X2_IC + "ae_sa32x2_ip", // XTENSA_INS_AE_SA32X2_IP + "ae_sa32x2_ric", // XTENSA_INS_AE_SA32X2_RIC + "ae_sa32x2_rip", // XTENSA_INS_AE_SA32X2_RIP + "ae_sa64neg_fp", // XTENSA_INS_AE_SA64NEG_FP + "ae_sa64pos_fp", // XTENSA_INS_AE_SA64POS_FP + "ae_salign64_i", // XTENSA_INS_AE_SALIGN64_I + "ae_sat16x4", // XTENSA_INS_AE_SAT16X4 + "ae_sat24s", // XTENSA_INS_AE_SAT24S + "ae_sat48s", // XTENSA_INS_AE_SAT48S + "ae_satq56s", // XTENSA_INS_AE_SATQ56S + "ae_sb", // XTENSA_INS_AE_SB + "ae_sbf", // XTENSA_INS_AE_SBF + "ae_sbf_ic", // XTENSA_INS_AE_SBF_IC + "ae_sbf_ip", // XTENSA_INS_AE_SBF_IP + "ae_sbi", // XTENSA_INS_AE_SBI + "ae_sbi_ic", // XTENSA_INS_AE_SBI_IC + "ae_sbi_ip", // XTENSA_INS_AE_SBI_IP + "ae_sb_ic", // XTENSA_INS_AE_SB_IC + "ae_sb_ip", // XTENSA_INS_AE_SB_IP + "ae_sel16i", // XTENSA_INS_AE_SEL16I + "ae_sel16i_n", // XTENSA_INS_AE_SEL16I_N + "ae_sext32", // XTENSA_INS_AE_SEXT32 + "ae_sext32x2d16_10", // XTENSA_INS_AE_SEXT32X2D16_10 + "ae_sext32x2d16_32", // XTENSA_INS_AE_SEXT32X2D16_32 + "ae_sha32", // XTENSA_INS_AE_SHA32 + "ae_shortswap", // XTENSA_INS_AE_SHORTSWAP + "ae_slaa16s", // XTENSA_INS_AE_SLAA16S + "ae_slaa32", // XTENSA_INS_AE_SLAA32 + "ae_slaa32s", // XTENSA_INS_AE_SLAA32S + "ae_slaa64", // XTENSA_INS_AE_SLAA64 + "ae_slaa64s", // XTENSA_INS_AE_SLAA64S + "ae_slaaq56", // XTENSA_INS_AE_SLAAQ56 + "ae_slai16s", // XTENSA_INS_AE_SLAI16S + "ae_slai24", // XTENSA_INS_AE_SLAI24 + "ae_slai24s", // XTENSA_INS_AE_SLAI24S + "ae_slai32", // XTENSA_INS_AE_SLAI32 + "ae_slai32s", // XTENSA_INS_AE_SLAI32S + "ae_slai64", // XTENSA_INS_AE_SLAI64 + "ae_slai64s", // XTENSA_INS_AE_SLAI64S + "ae_slaisq56s", // XTENSA_INS_AE_SLAISQ56S + "ae_slas24", // XTENSA_INS_AE_SLAS24 + "ae_slas24s", // XTENSA_INS_AE_SLAS24S + "ae_slas32", // XTENSA_INS_AE_SLAS32 + "ae_slas32s", // XTENSA_INS_AE_SLAS32S + "ae_slas64", // XTENSA_INS_AE_SLAS64 + "ae_slas64s", // XTENSA_INS_AE_SLAS64S + "ae_slasq56", // XTENSA_INS_AE_SLASQ56 + "ae_slassq56s", // XTENSA_INS_AE_SLASSQ56S + "ae_sra64_32", // XTENSA_INS_AE_SRA64_32 + "ae_sraa16rs", // XTENSA_INS_AE_SRAA16RS + "ae_sraa16s", // XTENSA_INS_AE_SRAA16S + "ae_sraa32", // XTENSA_INS_AE_SRAA32 + "ae_sraa32rs", // XTENSA_INS_AE_SRAA32RS + "ae_sraa32s", // XTENSA_INS_AE_SRAA32S + "ae_sraa64", // XTENSA_INS_AE_SRAA64 + "ae_srai16", // XTENSA_INS_AE_SRAI16 + "ae_srai16r", // XTENSA_INS_AE_SRAI16R + "ae_srai24", // XTENSA_INS_AE_SRAI24 + "ae_srai32", // XTENSA_INS_AE_SRAI32 + "ae_srai32r", // XTENSA_INS_AE_SRAI32R + "ae_srai64", // XTENSA_INS_AE_SRAI64 + "ae_sras24", // XTENSA_INS_AE_SRAS24 + "ae_sras32", // XTENSA_INS_AE_SRAS32 + "ae_sras64", // XTENSA_INS_AE_SRAS64 + "ae_srla32", // XTENSA_INS_AE_SRLA32 + "ae_srla64", // XTENSA_INS_AE_SRLA64 + "ae_srli24", // XTENSA_INS_AE_SRLI24 + "ae_srli32", // XTENSA_INS_AE_SRLI32 + "ae_srli64", // XTENSA_INS_AE_SRLI64 + "ae_srls24", // XTENSA_INS_AE_SRLS24 + "ae_srls32", // XTENSA_INS_AE_SRLS32 + "ae_srls64", // XTENSA_INS_AE_SRLS64 + "ae_sub16", // XTENSA_INS_AE_SUB16 + "ae_sub16s", // XTENSA_INS_AE_SUB16S + "ae_sub24s", // XTENSA_INS_AE_SUB24S + "ae_sub32", // XTENSA_INS_AE_SUB32 + "ae_sub32s", // XTENSA_INS_AE_SUB32S + "ae_sub64", // XTENSA_INS_AE_SUB64 + "ae_sub64s", // XTENSA_INS_AE_SUB64S + "ae_subadd32", // XTENSA_INS_AE_SUBADD32 + "ae_subadd32s", // XTENSA_INS_AE_SUBADD32S + "ae_trunca32f64s_l", // XTENSA_INS_AE_TRUNCA32F64S_L + "ae_trunca32x2f64s", // XTENSA_INS_AE_TRUNCA32X2F64S + "ae_trunci32f64s_l", // XTENSA_INS_AE_TRUNCI32F64S_L + "ae_trunci32x2f64s", // XTENSA_INS_AE_TRUNCI32X2F64S + "ae_vldl16c", // XTENSA_INS_AE_VLDL16C + "ae_vldl16c_ic", // XTENSA_INS_AE_VLDL16C_IC + "ae_vldl16c_ip", // XTENSA_INS_AE_VLDL16C_IP + "ae_vldl16t", // XTENSA_INS_AE_VLDL16T + "ae_vldl32t", // XTENSA_INS_AE_VLDL32T + "ae_vldsht", // XTENSA_INS_AE_VLDSHT + "ae_vlel16t", // XTENSA_INS_AE_VLEL16T + "ae_vlel32t", // XTENSA_INS_AE_VLEL32T + "ae_vles16c", // XTENSA_INS_AE_VLES16C + "ae_vles16c_ic", // XTENSA_INS_AE_VLES16C_IC + "ae_vles16c_ip", // XTENSA_INS_AE_VLES16C_IP + "ae_xor", // XTENSA_INS_AE_XOR + "ae_zalign64", // XTENSA_INS_AE_ZALIGN64 + "all4", // XTENSA_INS_ALL4 + "all8", // XTENSA_INS_ALL8 "and", // XTENSA_INS_AND + "andb", // XTENSA_INS_ANDB + "andbc", // XTENSA_INS_ANDBC + "any4", // XTENSA_INS_ANY4 + "any8", // XTENSA_INS_ANY8 "ball", // XTENSA_INS_BALL "bany", // XTENSA_INS_BANY "bbc", // XTENSA_INS_BBC @@ -29,6 +878,7 @@ "beq", // XTENSA_INS_BEQ "beqi", // XTENSA_INS_BEQI "beqz", // XTENSA_INS_BEQZ + "bf", // XTENSA_INS_BF "bge", // XTENSA_INS_BGE "bgei", // XTENSA_INS_BGEI "bgeu", // XTENSA_INS_BGEU @@ -44,37 +894,448 @@ "bnei", // XTENSA_INS_BNEI "bnez", // XTENSA_INS_BNEZ "bnone", // XTENSA_INS_BNONE + "break", // XTENSA_INS_BREAK + "break_n", // XTENSA_INS_BREAK_N + "bt", // XTENSA_INS_BT "call0", // XTENSA_INS_CALL0 + "call12", // XTENSA_INS_CALL12 + "call4", // XTENSA_INS_CALL4 + "call8", // XTENSA_INS_CALL8 "callx0", // XTENSA_INS_CALLX0 + "callx12", // XTENSA_INS_CALLX12 + "callx4", // XTENSA_INS_CALLX4 + "callx8", // XTENSA_INS_CALLX8 + "ceil_s", // XTENSA_INS_CEIL_S + "clamps", // XTENSA_INS_CLAMPS + "clr_bit_gpio_out", // XTENSA_INS_CLR_BIT_GPIO_OUT + "const_s", // XTENSA_INS_CONST_S + "div0_s", // XTENSA_INS_DIV0_S + "divn_s", // XTENSA_INS_DIVN_S "dsync", // XTENSA_INS_DSYNC + "ee_andq", // XTENSA_INS_EE_ANDQ + "ee_bitrev", // XTENSA_INS_EE_BITREV + "ee_clr_bit_gpio_out", // XTENSA_INS_EE_CLR_BIT_GPIO_OUT + "ee_cmul_s16", // XTENSA_INS_EE_CMUL_S16 + "ee_cmul_s16_ld_incp", // XTENSA_INS_EE_CMUL_S16_LD_INCP + "ee_cmul_s16_st_incp", // XTENSA_INS_EE_CMUL_S16_ST_INCP + "ee_fft_ams_s16_ld_incp", // XTENSA_INS_EE_FFT_AMS_S16_LD_INCP + "ee_fft_ams_s16_ld_incp_uaup", // XTENSA_INS_EE_FFT_AMS_S16_LD_INCP_UAUP + "ee_fft_ams_s16_ld_r32_decp", // XTENSA_INS_EE_FFT_AMS_S16_LD_R32_DECP + "ee_fft_ams_s16_st_incp", // XTENSA_INS_EE_FFT_AMS_S16_ST_INCP + "ee_fft_cmul_s16_ld_xp", // XTENSA_INS_EE_FFT_CMUL_S16_LD_XP + "ee_fft_cmul_s16_st_xp", // XTENSA_INS_EE_FFT_CMUL_S16_ST_XP + "ee_fft_r2bf_s16", // XTENSA_INS_EE_FFT_R2BF_S16 + "ee_fft_r2bf_s16_st_incp", // XTENSA_INS_EE_FFT_R2BF_S16_ST_INCP + "ee_fft_vst_r32_decp", // XTENSA_INS_EE_FFT_VST_R32_DECP + "ee_get_gpio_in", // XTENSA_INS_EE_GET_GPIO_IN + "ee_ldf_128_ip", // XTENSA_INS_EE_LDF_128_IP + "ee_ldf_128_xp", // XTENSA_INS_EE_LDF_128_XP + "ee_ldf_64_ip", // XTENSA_INS_EE_LDF_64_IP + "ee_ldf_64_xp", // XTENSA_INS_EE_LDF_64_XP + "ee_ldqa_s16_128_ip", // XTENSA_INS_EE_LDQA_S16_128_IP + "ee_ldqa_s16_128_xp", // XTENSA_INS_EE_LDQA_S16_128_XP + "ee_ldqa_s8_128_ip", // XTENSA_INS_EE_LDQA_S8_128_IP + "ee_ldqa_s8_128_xp", // XTENSA_INS_EE_LDQA_S8_128_XP + "ee_ldqa_u16_128_ip", // XTENSA_INS_EE_LDQA_U16_128_IP + "ee_ldqa_u16_128_xp", // XTENSA_INS_EE_LDQA_U16_128_XP + "ee_ldqa_u8_128_ip", // XTENSA_INS_EE_LDQA_U8_128_IP + "ee_ldqa_u8_128_xp", // XTENSA_INS_EE_LDQA_U8_128_XP + "ee_ldxq_32", // XTENSA_INS_EE_LDXQ_32 + "ee_ld_128_usar_ip", // XTENSA_INS_EE_LD_128_USAR_IP + "ee_ld_128_usar_xp", // XTENSA_INS_EE_LD_128_USAR_XP + "ee_ld_accx_ip", // XTENSA_INS_EE_LD_ACCX_IP + "ee_ld_qacc_h_h_32_ip", // XTENSA_INS_EE_LD_QACC_H_H_32_IP + "ee_ld_qacc_h_l_128_ip", // XTENSA_INS_EE_LD_QACC_H_L_128_IP + "ee_ld_qacc_l_h_32_ip", // XTENSA_INS_EE_LD_QACC_L_H_32_IP + "ee_ld_qacc_l_l_128_ip", // XTENSA_INS_EE_LD_QACC_L_L_128_IP + "ee_ld_ua_state_ip", // XTENSA_INS_EE_LD_UA_STATE_IP + "ee_movi_32_a", // XTENSA_INS_EE_MOVI_32_A + "ee_movi_32_q", // XTENSA_INS_EE_MOVI_32_Q + "ee_mov_s16_qacc", // XTENSA_INS_EE_MOV_S16_QACC + "ee_mov_s8_qacc", // XTENSA_INS_EE_MOV_S8_QACC + "ee_mov_u16_qacc", // XTENSA_INS_EE_MOV_U16_QACC + "ee_mov_u8_qacc", // XTENSA_INS_EE_MOV_U8_QACC + "ee_notq", // XTENSA_INS_EE_NOTQ + "ee_orq", // XTENSA_INS_EE_ORQ + "ee_set_bit_gpio_out", // XTENSA_INS_EE_SET_BIT_GPIO_OUT + "ee_slci_2q", // XTENSA_INS_EE_SLCI_2Q + "ee_slcxxp_2q", // XTENSA_INS_EE_SLCXXP_2Q + "ee_srci_2q", // XTENSA_INS_EE_SRCI_2Q + "ee_srcmb_s16_qacc", // XTENSA_INS_EE_SRCMB_S16_QACC + "ee_srcmb_s8_qacc", // XTENSA_INS_EE_SRCMB_S8_QACC + "ee_srcq_128_st_incp", // XTENSA_INS_EE_SRCQ_128_ST_INCP + "ee_srcxxp_2q", // XTENSA_INS_EE_SRCXXP_2Q + "ee_src_q", // XTENSA_INS_EE_SRC_Q + "ee_src_q_ld_ip", // XTENSA_INS_EE_SRC_Q_LD_IP + "ee_src_q_ld_xp", // XTENSA_INS_EE_SRC_Q_LD_XP + "ee_src_q_qup", // XTENSA_INS_EE_SRC_Q_QUP + "ee_srs_accx", // XTENSA_INS_EE_SRS_ACCX + "ee_stf_128_ip", // XTENSA_INS_EE_STF_128_IP + "ee_stf_128_xp", // XTENSA_INS_EE_STF_128_XP + "ee_stf_64_ip", // XTENSA_INS_EE_STF_64_IP + "ee_stf_64_xp", // XTENSA_INS_EE_STF_64_XP + "ee_stxq_32", // XTENSA_INS_EE_STXQ_32 + "ee_st_accx_ip", // XTENSA_INS_EE_ST_ACCX_IP + "ee_st_qacc_h_h_32_ip", // XTENSA_INS_EE_ST_QACC_H_H_32_IP + "ee_st_qacc_h_l_128_ip", // XTENSA_INS_EE_ST_QACC_H_L_128_IP + "ee_st_qacc_l_h_32_ip", // XTENSA_INS_EE_ST_QACC_L_H_32_IP + "ee_st_qacc_l_l_128_ip", // XTENSA_INS_EE_ST_QACC_L_L_128_IP + "ee_st_ua_state_ip", // XTENSA_INS_EE_ST_UA_STATE_IP + "ee_vadds_s16", // XTENSA_INS_EE_VADDS_S16 + "ee_vadds_s16_ld_incp", // XTENSA_INS_EE_VADDS_S16_LD_INCP + "ee_vadds_s16_st_incp", // XTENSA_INS_EE_VADDS_S16_ST_INCP + "ee_vadds_s32", // XTENSA_INS_EE_VADDS_S32 + "ee_vadds_s32_ld_incp", // XTENSA_INS_EE_VADDS_S32_LD_INCP + "ee_vadds_s32_st_incp", // XTENSA_INS_EE_VADDS_S32_ST_INCP + "ee_vadds_s8", // XTENSA_INS_EE_VADDS_S8 + "ee_vadds_s8_ld_incp", // XTENSA_INS_EE_VADDS_S8_LD_INCP + "ee_vadds_s8_st_incp", // XTENSA_INS_EE_VADDS_S8_ST_INCP + "ee_vcmp_eq_s16", // XTENSA_INS_EE_VCMP_EQ_S16 + "ee_vcmp_eq_s32", // XTENSA_INS_EE_VCMP_EQ_S32 + "ee_vcmp_eq_s8", // XTENSA_INS_EE_VCMP_EQ_S8 + "ee_vcmp_gt_s16", // XTENSA_INS_EE_VCMP_GT_S16 + "ee_vcmp_gt_s32", // XTENSA_INS_EE_VCMP_GT_S32 + "ee_vcmp_gt_s8", // XTENSA_INS_EE_VCMP_GT_S8 + "ee_vcmp_lt_s16", // XTENSA_INS_EE_VCMP_LT_S16 + "ee_vcmp_lt_s32", // XTENSA_INS_EE_VCMP_LT_S32 + "ee_vcmp_lt_s8", // XTENSA_INS_EE_VCMP_LT_S8 + "ee_vldbc_16", // XTENSA_INS_EE_VLDBC_16 + "ee_vldbc_16_ip", // XTENSA_INS_EE_VLDBC_16_IP + "ee_vldbc_16_xp", // XTENSA_INS_EE_VLDBC_16_XP + "ee_vldbc_32", // XTENSA_INS_EE_VLDBC_32 + "ee_vldbc_32_ip", // XTENSA_INS_EE_VLDBC_32_IP + "ee_vldbc_32_xp", // XTENSA_INS_EE_VLDBC_32_XP + "ee_vldbc_8", // XTENSA_INS_EE_VLDBC_8 + "ee_vldbc_8_ip", // XTENSA_INS_EE_VLDBC_8_IP + "ee_vldbc_8_xp", // XTENSA_INS_EE_VLDBC_8_XP + "ee_vldhbc_16_incp", // XTENSA_INS_EE_VLDHBC_16_INCP + "ee_vld_128_ip", // XTENSA_INS_EE_VLD_128_IP + "ee_vld_128_xp", // XTENSA_INS_EE_VLD_128_XP + "ee_vld_h_64_ip", // XTENSA_INS_EE_VLD_H_64_IP + "ee_vld_h_64_xp", // XTENSA_INS_EE_VLD_H_64_XP + "ee_vld_l_64_ip", // XTENSA_INS_EE_VLD_L_64_IP + "ee_vld_l_64_xp", // XTENSA_INS_EE_VLD_L_64_XP + "ee_vmax_s16", // XTENSA_INS_EE_VMAX_S16 + "ee_vmax_s16_ld_incp", // XTENSA_INS_EE_VMAX_S16_LD_INCP + "ee_vmax_s16_st_incp", // XTENSA_INS_EE_VMAX_S16_ST_INCP + "ee_vmax_s32", // XTENSA_INS_EE_VMAX_S32 + "ee_vmax_s32_ld_incp", // XTENSA_INS_EE_VMAX_S32_LD_INCP + "ee_vmax_s32_st_incp", // XTENSA_INS_EE_VMAX_S32_ST_INCP + "ee_vmax_s8", // XTENSA_INS_EE_VMAX_S8 + "ee_vmax_s8_ld_incp", // XTENSA_INS_EE_VMAX_S8_LD_INCP + "ee_vmax_s8_st_incp", // XTENSA_INS_EE_VMAX_S8_ST_INCP + "ee_vmin_s16", // XTENSA_INS_EE_VMIN_S16 + "ee_vmin_s16_ld_incp", // XTENSA_INS_EE_VMIN_S16_LD_INCP + "ee_vmin_s16_st_incp", // XTENSA_INS_EE_VMIN_S16_ST_INCP + "ee_vmin_s32", // XTENSA_INS_EE_VMIN_S32 + "ee_vmin_s32_ld_incp", // XTENSA_INS_EE_VMIN_S32_LD_INCP + "ee_vmin_s32_st_incp", // XTENSA_INS_EE_VMIN_S32_ST_INCP + "ee_vmin_s8", // XTENSA_INS_EE_VMIN_S8 + "ee_vmin_s8_ld_incp", // XTENSA_INS_EE_VMIN_S8_LD_INCP + "ee_vmin_s8_st_incp", // XTENSA_INS_EE_VMIN_S8_ST_INCP + "ee_vmulas_s16_accx", // XTENSA_INS_EE_VMULAS_S16_ACCX + "ee_vmulas_s16_accx_ld_ip", // XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP + "ee_vmulas_s16_accx_ld_ip_qup", // XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP_QUP + "ee_vmulas_s16_accx_ld_xp", // XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP + "ee_vmulas_s16_accx_ld_xp_qup", // XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP_QUP + "ee_vmulas_s16_qacc", // XTENSA_INS_EE_VMULAS_S16_QACC + "ee_vmulas_s16_qacc_ldbc_incp", // XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP + "ee_vmulas_s16_qacc_ldbc_incp_qup", // XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP_QUP + "ee_vmulas_s16_qacc_ld_ip", // XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP + "ee_vmulas_s16_qacc_ld_ip_qup", // XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP_QUP + "ee_vmulas_s16_qacc_ld_xp", // XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP + "ee_vmulas_s16_qacc_ld_xp_qup", // XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP_QUP + "ee_vmulas_s8_accx", // XTENSA_INS_EE_VMULAS_S8_ACCX + "ee_vmulas_s8_accx_ld_ip", // XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP + "ee_vmulas_s8_accx_ld_ip_qup", // XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP_QUP + "ee_vmulas_s8_accx_ld_xp", // XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP + "ee_vmulas_s8_accx_ld_xp_qup", // XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP_QUP + "ee_vmulas_s8_qacc", // XTENSA_INS_EE_VMULAS_S8_QACC + "ee_vmulas_s8_qacc_ldbc_incp", // XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP + "ee_vmulas_s8_qacc_ldbc_incp_qup", // XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP_QUP + "ee_vmulas_s8_qacc_ld_ip", // XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP + "ee_vmulas_s8_qacc_ld_ip_qup", // XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP_QUP + "ee_vmulas_s8_qacc_ld_xp", // XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP + "ee_vmulas_s8_qacc_ld_xp_qup", // XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP_QUP + "ee_vmulas_u16_accx", // XTENSA_INS_EE_VMULAS_U16_ACCX + "ee_vmulas_u16_accx_ld_ip", // XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP + "ee_vmulas_u16_accx_ld_ip_qup", // XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP_QUP + "ee_vmulas_u16_accx_ld_xp", // XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP + "ee_vmulas_u16_accx_ld_xp_qup", // XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP_QUP + "ee_vmulas_u16_qacc", // XTENSA_INS_EE_VMULAS_U16_QACC + "ee_vmulas_u16_qacc_ldbc_incp", // XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP + "ee_vmulas_u16_qacc_ldbc_incp_qup", // XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP_QUP + "ee_vmulas_u16_qacc_ld_ip", // XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP + "ee_vmulas_u16_qacc_ld_ip_qup", // XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP_QUP + "ee_vmulas_u16_qacc_ld_xp", // XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP + "ee_vmulas_u16_qacc_ld_xp_qup", // XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP_QUP + "ee_vmulas_u8_accx", // XTENSA_INS_EE_VMULAS_U8_ACCX + "ee_vmulas_u8_accx_ld_ip", // XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP + "ee_vmulas_u8_accx_ld_ip_qup", // XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP_QUP + "ee_vmulas_u8_accx_ld_xp", // XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP + "ee_vmulas_u8_accx_ld_xp_qup", // XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP_QUP + "ee_vmulas_u8_qacc", // XTENSA_INS_EE_VMULAS_U8_QACC + "ee_vmulas_u8_qacc_ldbc_incp", // XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP + "ee_vmulas_u8_qacc_ldbc_incp_qup", // XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP_QUP + "ee_vmulas_u8_qacc_ld_ip", // XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP + "ee_vmulas_u8_qacc_ld_ip_qup", // XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP_QUP + "ee_vmulas_u8_qacc_ld_xp", // XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP + "ee_vmulas_u8_qacc_ld_xp_qup", // XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP_QUP + "ee_vmul_s16", // XTENSA_INS_EE_VMUL_S16 + "ee_vmul_s16_ld_incp", // XTENSA_INS_EE_VMUL_S16_LD_INCP + "ee_vmul_s16_st_incp", // XTENSA_INS_EE_VMUL_S16_ST_INCP + "ee_vmul_s8", // XTENSA_INS_EE_VMUL_S8 + "ee_vmul_s8_ld_incp", // XTENSA_INS_EE_VMUL_S8_LD_INCP + "ee_vmul_s8_st_incp", // XTENSA_INS_EE_VMUL_S8_ST_INCP + "ee_vmul_u16", // XTENSA_INS_EE_VMUL_U16 + "ee_vmul_u16_ld_incp", // XTENSA_INS_EE_VMUL_U16_LD_INCP + "ee_vmul_u16_st_incp", // XTENSA_INS_EE_VMUL_U16_ST_INCP + "ee_vmul_u8", // XTENSA_INS_EE_VMUL_U8 + "ee_vmul_u8_ld_incp", // XTENSA_INS_EE_VMUL_U8_LD_INCP + "ee_vmul_u8_st_incp", // XTENSA_INS_EE_VMUL_U8_ST_INCP + "ee_vprelu_s16", // XTENSA_INS_EE_VPRELU_S16 + "ee_vprelu_s8", // XTENSA_INS_EE_VPRELU_S8 + "ee_vrelu_s16", // XTENSA_INS_EE_VRELU_S16 + "ee_vrelu_s8", // XTENSA_INS_EE_VRELU_S8 + "ee_vsl_32", // XTENSA_INS_EE_VSL_32 + "ee_vsmulas_s16_qacc", // XTENSA_INS_EE_VSMULAS_S16_QACC + "ee_vsmulas_s16_qacc_ld_incp", // XTENSA_INS_EE_VSMULAS_S16_QACC_LD_INCP + "ee_vsmulas_s8_qacc", // XTENSA_INS_EE_VSMULAS_S8_QACC + "ee_vsmulas_s8_qacc_ld_incp", // XTENSA_INS_EE_VSMULAS_S8_QACC_LD_INCP + "ee_vsr_32", // XTENSA_INS_EE_VSR_32 + "ee_vst_128_ip", // XTENSA_INS_EE_VST_128_IP + "ee_vst_128_xp", // XTENSA_INS_EE_VST_128_XP + "ee_vst_h_64_ip", // XTENSA_INS_EE_VST_H_64_IP + "ee_vst_h_64_xp", // XTENSA_INS_EE_VST_H_64_XP + "ee_vst_l_64_ip", // XTENSA_INS_EE_VST_L_64_IP + "ee_vst_l_64_xp", // XTENSA_INS_EE_VST_L_64_XP + "ee_vsubs_s16", // XTENSA_INS_EE_VSUBS_S16 + "ee_vsubs_s16_ld_incp", // XTENSA_INS_EE_VSUBS_S16_LD_INCP + "ee_vsubs_s16_st_incp", // XTENSA_INS_EE_VSUBS_S16_ST_INCP + "ee_vsubs_s32", // XTENSA_INS_EE_VSUBS_S32 + "ee_vsubs_s32_ld_incp", // XTENSA_INS_EE_VSUBS_S32_LD_INCP + "ee_vsubs_s32_st_incp", // XTENSA_INS_EE_VSUBS_S32_ST_INCP + "ee_vsubs_s8", // XTENSA_INS_EE_VSUBS_S8 + "ee_vsubs_s8_ld_incp", // XTENSA_INS_EE_VSUBS_S8_LD_INCP + "ee_vsubs_s8_st_incp", // XTENSA_INS_EE_VSUBS_S8_ST_INCP + "ee_vunzip_16", // XTENSA_INS_EE_VUNZIP_16 + "ee_vunzip_32", // XTENSA_INS_EE_VUNZIP_32 + "ee_vunzip_8", // XTENSA_INS_EE_VUNZIP_8 + "ee_vzip_16", // XTENSA_INS_EE_VZIP_16 + "ee_vzip_32", // XTENSA_INS_EE_VZIP_32 + "ee_vzip_8", // XTENSA_INS_EE_VZIP_8 + "ee_wr_mask_gpio_out", // XTENSA_INS_EE_WR_MASK_GPIO_OUT + "ee_xorq", // XTENSA_INS_EE_XORQ + "ee_zero_accx", // XTENSA_INS_EE_ZERO_ACCX + "ee_zero_q", // XTENSA_INS_EE_ZERO_Q + "ee_zero_qacc", // XTENSA_INS_EE_ZERO_QACC + "entry", // XTENSA_INS_ENTRY "esync", // XTENSA_INS_ESYNC + "excw", // XTENSA_INS_EXCW "extui", // XTENSA_INS_EXTUI "extw", // XTENSA_INS_EXTW + "float_s", // XTENSA_INS_FLOAT_S + "floor_s", // XTENSA_INS_FLOOR_S + "get_gpio_in", // XTENSA_INS_GET_GPIO_IN + "ill", // XTENSA_INS_ILL + "ill_n", // XTENSA_INS_ILL_N "isync", // XTENSA_INS_ISYNC "j", // XTENSA_INS_J "jx", // XTENSA_INS_JX "l16si", // XTENSA_INS_L16SI "l16ui", // XTENSA_INS_L16UI + "l32e", // XTENSA_INS_L32E "l32i", // XTENSA_INS_L32I + "l32i_n", // XTENSA_INS_L32I_N "l32r", // XTENSA_INS_L32R "l8ui", // XTENSA_INS_L8UI + "lddec", // XTENSA_INS_LDDEC + "ldinc", // XTENSA_INS_LDINC + "loop", // XTENSA_INS_LOOP + "loopgtz", // XTENSA_INS_LOOPGTZ + "loopnez", // XTENSA_INS_LOOPNEZ + "lsi", // XTENSA_INS_LSI + "lsip", // XTENSA_INS_LSIP + "lsx", // XTENSA_INS_LSX + "lsxp", // XTENSA_INS_LSXP + "maddn_s", // XTENSA_INS_MADDN_S + "madd_s", // XTENSA_INS_MADD_S + "max", // XTENSA_INS_MAX + "maxu", // XTENSA_INS_MAXU "memw", // XTENSA_INS_MEMW + "min", // XTENSA_INS_MIN + "minu", // XTENSA_INS_MINU + "mkdadj_s", // XTENSA_INS_MKDADJ_S + "mksadj_s", // XTENSA_INS_MKSADJ_S "moveqz", // XTENSA_INS_MOVEQZ + "moveqz_s", // XTENSA_INS_MOVEQZ_S + "movf", // XTENSA_INS_MOVF + "movf_s", // XTENSA_INS_MOVF_S "movgez", // XTENSA_INS_MOVGEZ + "movgez_s", // XTENSA_INS_MOVGEZ_S "movi", // XTENSA_INS_MOVI + "movi_n", // XTENSA_INS_MOVI_N "movltz", // XTENSA_INS_MOVLTZ + "movltz_s", // XTENSA_INS_MOVLTZ_S "movnez", // XTENSA_INS_MOVNEZ + "movnez_s", // XTENSA_INS_MOVNEZ_S + "movsp", // XTENSA_INS_MOVSP + "movt", // XTENSA_INS_MOVT + "movt_s", // XTENSA_INS_MOVT_S + "mov_n", // XTENSA_INS_MOV_N + "mov_s", // XTENSA_INS_MOV_S + "msub_s", // XTENSA_INS_MSUB_S + "mul16s", // XTENSA_INS_MUL16S + "mul16u", // XTENSA_INS_MUL16U + "mula_aa_hh", // XTENSA_INS_MULA_AA_HH + "mula_aa_hl", // XTENSA_INS_MULA_AA_HL + "mula_aa_lh", // XTENSA_INS_MULA_AA_LH + "mula_aa_ll", // XTENSA_INS_MULA_AA_LL + "mula_ad_hh", // XTENSA_INS_MULA_AD_HH + "mula_ad_hl", // XTENSA_INS_MULA_AD_HL + "mula_ad_lh", // XTENSA_INS_MULA_AD_LH + "mula_ad_ll", // XTENSA_INS_MULA_AD_LL + "mula_da_hh", // XTENSA_INS_MULA_DA_HH + "mula_da_hh_lddec", // XTENSA_INS_MULA_DA_HH_LDDEC + "mula_da_hh_ldinc", // XTENSA_INS_MULA_DA_HH_LDINC + "mula_da_hl", // XTENSA_INS_MULA_DA_HL + "mula_da_hl_lddec", // XTENSA_INS_MULA_DA_HL_LDDEC + "mula_da_hl_ldinc", // XTENSA_INS_MULA_DA_HL_LDINC + "mula_da_lh", // XTENSA_INS_MULA_DA_LH + "mula_da_lh_lddec", // XTENSA_INS_MULA_DA_LH_LDDEC + "mula_da_lh_ldinc", // XTENSA_INS_MULA_DA_LH_LDINC + "mula_da_ll", // XTENSA_INS_MULA_DA_LL + "mula_da_ll_lddec", // XTENSA_INS_MULA_DA_LL_LDDEC + "mula_da_ll_ldinc", // XTENSA_INS_MULA_DA_LL_LDINC + "mula_dd_hh", // XTENSA_INS_MULA_DD_HH + "mula_dd_hh_lddec", // XTENSA_INS_MULA_DD_HH_LDDEC + "mula_dd_hh_ldinc", // XTENSA_INS_MULA_DD_HH_LDINC + "mula_dd_hl", // XTENSA_INS_MULA_DD_HL + "mula_dd_hl_lddec", // XTENSA_INS_MULA_DD_HL_LDDEC + "mula_dd_hl_ldinc", // XTENSA_INS_MULA_DD_HL_LDINC + "mula_dd_lh", // XTENSA_INS_MULA_DD_LH + "mula_dd_lh_lddec", // XTENSA_INS_MULA_DD_LH_LDDEC + "mula_dd_lh_ldinc", // XTENSA_INS_MULA_DD_LH_LDINC + "mula_dd_ll", // XTENSA_INS_MULA_DD_LL + "mula_dd_ll_lddec", // XTENSA_INS_MULA_DD_LL_LDDEC + "mula_dd_ll_ldinc", // XTENSA_INS_MULA_DD_LL_LDINC + "mull", // XTENSA_INS_MULL + "mulsh", // XTENSA_INS_MULSH + "muls_aa_hh", // XTENSA_INS_MULS_AA_HH + "muls_aa_hl", // XTENSA_INS_MULS_AA_HL + "muls_aa_lh", // XTENSA_INS_MULS_AA_LH + "muls_aa_ll", // XTENSA_INS_MULS_AA_LL + "muls_ad_hh", // XTENSA_INS_MULS_AD_HH + "muls_ad_hl", // XTENSA_INS_MULS_AD_HL + "muls_ad_lh", // XTENSA_INS_MULS_AD_LH + "muls_ad_ll", // XTENSA_INS_MULS_AD_LL + "muls_da_hh", // XTENSA_INS_MULS_DA_HH + "muls_da_hl", // XTENSA_INS_MULS_DA_HL + "muls_da_lh", // XTENSA_INS_MULS_DA_LH + "muls_da_ll", // XTENSA_INS_MULS_DA_LL + "muls_dd_hh", // XTENSA_INS_MULS_DD_HH + "muls_dd_hl", // XTENSA_INS_MULS_DD_HL + "muls_dd_lh", // XTENSA_INS_MULS_DD_LH + "muls_dd_ll", // XTENSA_INS_MULS_DD_LL + "muluh", // XTENSA_INS_MULUH + "mul_aa_hh", // XTENSA_INS_MUL_AA_HH + "mul_aa_hl", // XTENSA_INS_MUL_AA_HL + "mul_aa_lh", // XTENSA_INS_MUL_AA_LH + "mul_aa_ll", // XTENSA_INS_MUL_AA_LL + "mul_ad_hh", // XTENSA_INS_MUL_AD_HH + "mul_ad_hl", // XTENSA_INS_MUL_AD_HL + "mul_ad_lh", // XTENSA_INS_MUL_AD_LH + "mul_ad_ll", // XTENSA_INS_MUL_AD_LL + "mul_da_hh", // XTENSA_INS_MUL_DA_HH + "mul_da_hl", // XTENSA_INS_MUL_DA_HL + "mul_da_lh", // XTENSA_INS_MUL_DA_LH + "mul_da_ll", // XTENSA_INS_MUL_DA_LL + "mul_dd_hh", // XTENSA_INS_MUL_DD_HH + "mul_dd_hl", // XTENSA_INS_MUL_DD_HL + "mul_dd_lh", // XTENSA_INS_MUL_DD_LH + "mul_dd_ll", // XTENSA_INS_MUL_DD_LL + "mul_s", // XTENSA_INS_MUL_S "neg", // XTENSA_INS_NEG + "neg_s", // XTENSA_INS_NEG_S + "nexp01_s", // XTENSA_INS_NEXP01_S "nop", // XTENSA_INS_NOP + "nsa", // XTENSA_INS_NSA + "nsau", // XTENSA_INS_NSAU + "oeq_s", // XTENSA_INS_OEQ_S + "ole_s", // XTENSA_INS_OLE_S + "olt_s", // XTENSA_INS_OLT_S "or", // XTENSA_INS_OR + "orb", // XTENSA_INS_ORB + "orbc", // XTENSA_INS_ORBC + "quos", // XTENSA_INS_QUOS + "quou", // XTENSA_INS_QUOU + "recip0_s", // XTENSA_INS_RECIP0_S + "rems", // XTENSA_INS_REMS + "remu", // XTENSA_INS_REMU + "rer", // XTENSA_INS_RER "ret", // XTENSA_INS_RET + "retw", // XTENSA_INS_RETW + "retw_n", // XTENSA_INS_RETW_N + "ret_n", // XTENSA_INS_RET_N + "rfde", // XTENSA_INS_RFDE + "rfe", // XTENSA_INS_RFE + "rfi", // XTENSA_INS_RFI + "rfr", // XTENSA_INS_RFR + "rfwo", // XTENSA_INS_RFWO + "rfwu", // XTENSA_INS_RFWU + "rotw", // XTENSA_INS_ROTW + "round_s", // XTENSA_INS_ROUND_S + "rsil", // XTENSA_INS_RSIL + "rsqrt0_s", // XTENSA_INS_RSQRT0_S "rsr", // XTENSA_INS_RSR "rsync", // XTENSA_INS_RSYNC + "rur", // XTENSA_INS_RUR + "rur_accx_0", // XTENSA_INS_RUR_ACCX_0 + "rur_accx_1", // XTENSA_INS_RUR_ACCX_1 + "rur_ae_bithead", // XTENSA_INS_RUR_AE_BITHEAD + "rur_ae_bitptr", // XTENSA_INS_RUR_AE_BITPTR + "rur_ae_bitsused", // XTENSA_INS_RUR_AE_BITSUSED + "rur_ae_cbegin0", // XTENSA_INS_RUR_AE_CBEGIN0 + "rur_ae_cend0", // XTENSA_INS_RUR_AE_CEND0 + "rur_ae_cwrap", // XTENSA_INS_RUR_AE_CWRAP + "rur_ae_cw_sd_no", // XTENSA_INS_RUR_AE_CW_SD_NO + "rur_ae_first_ts", // XTENSA_INS_RUR_AE_FIRST_TS + "rur_ae_nextoffset", // XTENSA_INS_RUR_AE_NEXTOFFSET + "rur_ae_overflow", // XTENSA_INS_RUR_AE_OVERFLOW + "rur_ae_ovf_sar", // XTENSA_INS_RUR_AE_OVF_SAR + "rur_ae_sar", // XTENSA_INS_RUR_AE_SAR + "rur_ae_searchdone", // XTENSA_INS_RUR_AE_SEARCHDONE + "rur_ae_tablesize", // XTENSA_INS_RUR_AE_TABLESIZE + "rur_ae_ts_fts_bu_bp", // XTENSA_INS_RUR_AE_TS_FTS_BU_BP + "rur_fft_bit_width", // XTENSA_INS_RUR_FFT_BIT_WIDTH + "rur_gpio_out", // XTENSA_INS_RUR_GPIO_OUT + "rur_qacc_h_0", // XTENSA_INS_RUR_QACC_H_0 + "rur_qacc_h_1", // XTENSA_INS_RUR_QACC_H_1 + "rur_qacc_h_2", // XTENSA_INS_RUR_QACC_H_2 + "rur_qacc_h_3", // XTENSA_INS_RUR_QACC_H_3 + "rur_qacc_h_4", // XTENSA_INS_RUR_QACC_H_4 + "rur_qacc_l_0", // XTENSA_INS_RUR_QACC_L_0 + "rur_qacc_l_1", // XTENSA_INS_RUR_QACC_L_1 + "rur_qacc_l_2", // XTENSA_INS_RUR_QACC_L_2 + "rur_qacc_l_3", // XTENSA_INS_RUR_QACC_L_3 + "rur_qacc_l_4", // XTENSA_INS_RUR_QACC_L_4 + "rur_sar_byte", // XTENSA_INS_RUR_SAR_BYTE + "rur_ua_state_0", // XTENSA_INS_RUR_UA_STATE_0 + "rur_ua_state_1", // XTENSA_INS_RUR_UA_STATE_1 + "rur_ua_state_2", // XTENSA_INS_RUR_UA_STATE_2 + "rur_ua_state_3", // XTENSA_INS_RUR_UA_STATE_3 "s16i", // XTENSA_INS_S16I + "s32c1i", // XTENSA_INS_S32C1I + "s32e", // XTENSA_INS_S32E "s32i", // XTENSA_INS_S32I + "s32i_n", // XTENSA_INS_S32I_N "s8i", // XTENSA_INS_S8I + "set_bit_gpio_out", // XTENSA_INS_SET_BIT_GPIO_OUT + "sext", // XTENSA_INS_SEXT + "simcall", // XTENSA_INS_SIMCALL "sll", // XTENSA_INS_SLL "slli", // XTENSA_INS_SLLI + "sqrt0_s", // XTENSA_INS_SQRT0_S "sra", // XTENSA_INS_SRA "srai", // XTENSA_INS_SRAI "src", // XTENSA_INS_SRC @@ -82,12 +1343,81 @@ "srli", // XTENSA_INS_SRLI "ssa8l", // XTENSA_INS_SSA8L "ssai", // XTENSA_INS_SSAI + "ssi", // XTENSA_INS_SSI + "ssip", // XTENSA_INS_SSIP "ssl", // XTENSA_INS_SSL "ssr", // XTENSA_INS_SSR + "ssx", // XTENSA_INS_SSX + "ssxp", // XTENSA_INS_SSXP "sub", // XTENSA_INS_SUB "subx2", // XTENSA_INS_SUBX2 "subx4", // XTENSA_INS_SUBX4 "subx8", // XTENSA_INS_SUBX8 + "sub_s", // XTENSA_INS_SUB_S + "syscall", // XTENSA_INS_SYSCALL + "trunc_s", // XTENSA_INS_TRUNC_S + "ueq_s", // XTENSA_INS_UEQ_S + "ufloat_s", // XTENSA_INS_UFLOAT_S + "ule_s", // XTENSA_INS_ULE_S + "ult_s", // XTENSA_INS_ULT_S + "umul_aa_hh", // XTENSA_INS_UMUL_AA_HH + "umul_aa_hl", // XTENSA_INS_UMUL_AA_HL + "umul_aa_lh", // XTENSA_INS_UMUL_AA_LH + "umul_aa_ll", // XTENSA_INS_UMUL_AA_LL + "un_s", // XTENSA_INS_UN_S + "utrunc_s", // XTENSA_INS_UTRUNC_S + "waiti", // XTENSA_INS_WAITI + "wdtlb", // XTENSA_INS_WDTLB + "wer", // XTENSA_INS_WER + "wfr", // XTENSA_INS_WFR + "witlb", // XTENSA_INS_WITLB + "wr_mask_gpio_out", // XTENSA_INS_WR_MASK_GPIO_OUT "wsr", // XTENSA_INS_WSR + "wur", // XTENSA_INS_WUR + "wur_accx_0", // XTENSA_INS_WUR_ACCX_0 + "wur_accx_1", // XTENSA_INS_WUR_ACCX_1 + "wur_ae_bithead", // XTENSA_INS_WUR_AE_BITHEAD + "wur_ae_bitptr", // XTENSA_INS_WUR_AE_BITPTR + "wur_ae_bitsused", // XTENSA_INS_WUR_AE_BITSUSED + "wur_ae_cbegin0", // XTENSA_INS_WUR_AE_CBEGIN0 + "wur_ae_cend0", // XTENSA_INS_WUR_AE_CEND0 + "wur_ae_cwrap", // XTENSA_INS_WUR_AE_CWRAP + "wur_ae_cw_sd_no", // XTENSA_INS_WUR_AE_CW_SD_NO + "wur_ae_first_ts", // XTENSA_INS_WUR_AE_FIRST_TS + "wur_ae_nextoffset", // XTENSA_INS_WUR_AE_NEXTOFFSET + "wur_ae_overflow", // XTENSA_INS_WUR_AE_OVERFLOW + "wur_ae_ovf_sar", // XTENSA_INS_WUR_AE_OVF_SAR + "wur_ae_sar", // XTENSA_INS_WUR_AE_SAR + "wur_ae_searchdone", // XTENSA_INS_WUR_AE_SEARCHDONE + "wur_ae_tablesize", // XTENSA_INS_WUR_AE_TABLESIZE + "wur_ae_ts_fts_bu_bp", // XTENSA_INS_WUR_AE_TS_FTS_BU_BP + "wur_fcr", // XTENSA_INS_WUR_FCR + "wur_fft_bit_width", // XTENSA_INS_WUR_FFT_BIT_WIDTH + "wur_fsr", // XTENSA_INS_WUR_FSR + "wur_gpio_out", // XTENSA_INS_WUR_GPIO_OUT + "wur_qacc_h_0", // XTENSA_INS_WUR_QACC_H_0 + "wur_qacc_h_1", // XTENSA_INS_WUR_QACC_H_1 + "wur_qacc_h_2", // XTENSA_INS_WUR_QACC_H_2 + "wur_qacc_h_3", // XTENSA_INS_WUR_QACC_H_3 + "wur_qacc_h_4", // XTENSA_INS_WUR_QACC_H_4 + "wur_qacc_l_0", // XTENSA_INS_WUR_QACC_L_0 + "wur_qacc_l_1", // XTENSA_INS_WUR_QACC_L_1 + "wur_qacc_l_2", // XTENSA_INS_WUR_QACC_L_2 + "wur_qacc_l_3", // XTENSA_INS_WUR_QACC_L_3 + "wur_qacc_l_4", // XTENSA_INS_WUR_QACC_L_4 + "wur_sar_byte", // XTENSA_INS_WUR_SAR_BYTE + "wur_ua_state_0", // XTENSA_INS_WUR_UA_STATE_0 + "wur_ua_state_1", // XTENSA_INS_WUR_UA_STATE_1 + "wur_ua_state_2", // XTENSA_INS_WUR_UA_STATE_2 + "wur_ua_state_3", // XTENSA_INS_WUR_UA_STATE_3 "xor", // XTENSA_INS_XOR + "xorb", // XTENSA_INS_XORB "xsr", // XTENSA_INS_XSR + "_l32i", // XTENSA_INS__L32I + "_l32i_n", // XTENSA_INS__L32I_N + "_movi", // XTENSA_INS__MOVI + "_s32i", // XTENSA_INS__S32I + "_s32i_n", // XTENSA_INS__S32I_N + "_slli", // XTENSA_INS__SLLI + "_srli", // XTENSA_INS__SRLI + "mv_qr", // XTENSA_INS_MV_QR diff --git a/arch/Xtensa/XtensaGenCSMappingInsnOp.inc b/arch/Xtensa/XtensaGenCSMappingInsnOp.inc index c1cb57d494..76e6ae510c 100644 --- a/arch/Xtensa/XtensaGenCSMappingInsnOp.inc +++ b/arch/Xtensa/XtensaGenCSMappingInsnOp.inc @@ -824,505 +824,11278 @@ {{{ /* XTENSA_G_UBFX (270) - XTENSA_INS_INVALID - */ 0 }}}, -{ /* XTENSA_ABS (271) - XTENSA_INS_ABS - abs $r, $t */ +{{{ /* XTENSA_ADJCALLSTACKDOWN (271) - XTENSA_INS_INVALID - #ADJCALLSTACKDOWN */ + 0 +}}}, +{{{ /* XTENSA_ADJCALLSTACKUP (272) - XTENSA_INS_INVALID - #ADJCALLSTACKUP */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_CMP_SWAP_16_P (273) - XTENSA_INS_INVALID - !atomic_cmp_swap_16_p, $dst, $ptr, $cmp, $swap */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_CMP_SWAP_32_P (274) - XTENSA_INS_INVALID - !atomic_cmp_swap_32_p, $dst, $ptr, $cmp, $swap */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_CMP_SWAP_8_P (275) - XTENSA_INS_INVALID - !atomic_cmp_swap_8_p, $dst, $ptr, $cmp, $swap */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_ADD_16_P (276) - XTENSA_INS_INVALID - !atomic_load_add_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_ADD_32_P (277) - XTENSA_INS_INVALID - !atomic_load_add_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_ADD_8_P (278) - XTENSA_INS_INVALID - !atomic_load_add_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_AND_16_P (279) - XTENSA_INS_INVALID - !atomic_load_and_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_AND_32_P (280) - XTENSA_INS_INVALID - !atomic_load_and_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_AND_8_P (281) - XTENSA_INS_INVALID - !atomic_load_and_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_MAX_16_P (282) - XTENSA_INS_INVALID - !atomic_load_max_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_MAX_32_P (283) - XTENSA_INS_INVALID - !atomic_load_max_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_MAX_8_P (284) - XTENSA_INS_INVALID - !atomic_load_max_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_MIN_16_P (285) - XTENSA_INS_INVALID - !atomic_load_min_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_MIN_32_P (286) - XTENSA_INS_INVALID - !atomic_load_min_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_MIN_8_P (287) - XTENSA_INS_INVALID - !atomic_load_min_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_NAND_16_P (288) - XTENSA_INS_INVALID - !atomic_load_nand_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_NAND_32_P (289) - XTENSA_INS_INVALID - !atomic_load_nand_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_NAND_8_P (290) - XTENSA_INS_INVALID - !atomic_load_nand_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_OR_16_P (291) - XTENSA_INS_INVALID - !atomic_load_or_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_OR_32_P (292) - XTENSA_INS_INVALID - !atomic_load_or_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_OR_8_P (293) - XTENSA_INS_INVALID - !atomic_load_or_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_SUB_16_P (294) - XTENSA_INS_INVALID - !atomic_load_sub_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_SUB_32_P (295) - XTENSA_INS_INVALID - !atomic_load_sub_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_SUB_8_P (296) - XTENSA_INS_INVALID - !atomic_load_sub_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_UMAX_16_P (297) - XTENSA_INS_INVALID - !atomic_load_umax_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_UMAX_32_P (298) - XTENSA_INS_INVALID - !atomic_load_umax_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_UMAX_8_P (299) - XTENSA_INS_INVALID - !atomic_load_umax_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_UMIN_16_P (300) - XTENSA_INS_INVALID - !atomic_load_umin_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_UMIN_32_P (301) - XTENSA_INS_INVALID - !atomic_load_umin_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_UMIN_8_P (302) - XTENSA_INS_INVALID - !atomic_load_umin_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_XOR_16_P (303) - XTENSA_INS_INVALID - !atomic_load_xor_16_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_XOR_32_P (304) - XTENSA_INS_INVALID - !atomic_load_xor_32_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_LOAD_XOR_8_P (305) - XTENSA_INS_INVALID - !atomic_load_xor_8_p, $dst, $ptr, $arg */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_SWAP_16_P (306) - XTENSA_INS_INVALID - !atomic_swap_16_p, $dst, $ptr, $swap */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_SWAP_32_P (307) - XTENSA_INS_INVALID - !atomic_swap_32_p, $dst, $ptr, $swap */ + 0 +}}}, +{{{ /* XTENSA_ATOMIC_SWAP_8_P (308) - XTENSA_INS_INVALID - !atomic_swap_8_p, $dst, $ptr, $swap */ + 0 +}}}, +{{{ /* XTENSA_BRCC_FP (309) - XTENSA_INS_INVALID - !brcc_fp $cond, $lhs, $rhs, $target */ + 0 +}}}, +{{{ /* XTENSA_BR_JT (310) - XTENSA_INS_INVALID - !br_jt_p, $s, $jt */ + 0 +}}}, +{{{ /* XTENSA_CONSTPOOL_ENTRY (311) - XTENSA_INS_INVALID - foo */ + 0 +}}}, +{{{ /* XTENSA_EE_ANDQ_P (312) - XTENSA_INS_INVALID - !xtensa_ee_andq_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_BITREV_P (313) - XTENSA_INS_INVALID - !xtensa_ee_bitrev_p, $qa, $ax */ + 0 +}}}, +{{{ /* XTENSA_EE_CMUL_S16_LD_INCP_P (314) - XTENSA_INS_INVALID - !xtensa_ee_cmul_s16_ld_incp_p, $qu, $as, $qz, $qx, $qy, $sel4 */ + 0 +}}}, +{{{ /* XTENSA_EE_CMUL_S16_P (315) - XTENSA_INS_INVALID - !xtensa_ee_cmul_s16_p, $qz, $qx, $qy, $sel4 */ + 0 +}}}, +{{{ /* XTENSA_EE_CMUL_S16_ST_INCP_P (316) - XTENSA_INS_INVALID - !xtensa_ee_cmul_s16_st_incp_p, $qv, $as, $qz, $qx, $qy, $sel4 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_AMS_S16_LD_INCP_P (317) - XTENSA_INS_INVALID - !xtensa_ee_fft_ams_s16_ld_incp_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_AMS_S16_LD_INCP_UAUP_P (318) - XTENSA_INS_INVALID - !xtensa_ee_fft_ams_s16_ld_incp_uaup_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_AMS_S16_LD_R32_DECP_P (319) - XTENSA_INS_INVALID - !xtensa_ee_fft_ams_s16_ld_r32_decp_p, $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_AMS_S16_ST_INCP_P (320) - XTENSA_INS_INVALID - !xtensa_ee_fft_ams_s16_st_incp_p, $qv, $qz1, $as0, $as, $qx, $qy, $qm, $sel2 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_CMUL_S16_LD_XP_P (321) - XTENSA_INS_INVALID - !xtensa_ee_fft_cmul_s16_ld_xp_p, $qu, $as, $ad, $qz, $qx, $qy, $sel8 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_CMUL_S16_ST_XP_P (322) - XTENSA_INS_INVALID - !xtensa_ee_fft_cmul_s16_st_xp_p, $qx, $qy, $qv, $as, $ad, $sel8, $upd4, $sar4 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_R2BF_S16_P (323) - XTENSA_INS_INVALID - !xtensa_ee_fft_r2bf_s16_p, $qa0, $qa1, $qx, $qy, $sel2 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_R2BF_S16_ST_INCP_P (324) - XTENSA_INS_INVALID - !xtensa_ee_fft_r2bf_s16_st_incp_p, $qa0, $qx, $qy, $as, $sar4 */ + 0 +}}}, +{{{ /* XTENSA_EE_FFT_VST_R32_DECP_P (325) - XTENSA_INS_INVALID - !xtensa_ee_fft_vst_r32_decp_p, $qv, $as, $sar2 */ + 0 +}}}, +{{{ /* XTENSA_EE_LDF_128_IP_P (326) - XTENSA_INS_INVALID - !xtensa_ee_ldf_128_ip_p, $fu3, $fu2, $fu1, $fu0, $as, $imm16f */ + 0 +}}}, +{{{ /* XTENSA_EE_LDF_128_XP_P (327) - XTENSA_INS_INVALID - !xtensa_ee_ldf_128_xp_p, $fu3, $fu2, $fu1, $fu0, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_LDF_64_IP_P (328) - XTENSA_INS_INVALID - !xtensa_ee_ldf_64_ip_p, $fu1, $fu0, $as, $imm8 */ + 0 +}}}, +{{{ /* XTENSA_EE_LDF_64_XP_P (329) - XTENSA_INS_INVALID - !xtensa_ee_ldf_64_xp_p, $fu1, $fu0, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_LDQA_S16_128_IP_P (330) - XTENSA_INS_INVALID - !xtensa_ee_ldqa_s16_128_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_LDQA_S16_128_XP_P (331) - XTENSA_INS_INVALID - !xtensa_ee_ldqa_s16_128_xp_p, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_LDQA_S8_128_IP_P (332) - XTENSA_INS_INVALID - !xtensa_ee_ldqa_s8_128_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_LDQA_S8_128_XP_P (333) - XTENSA_INS_INVALID - !xtensa_ee_ldqa_s8_128_xp_p, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_LDQA_U16_128_IP_P (334) - XTENSA_INS_INVALID - !xtensa_ee_ldqa_u16_128_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_LDQA_U16_128_XP_P (335) - XTENSA_INS_INVALID - !xtensa_ee_ldqa_u16_128_xp_p, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_LDQA_U8_128_IP_P (336) - XTENSA_INS_INVALID - !xtensa_ee_ldqa_u8_128_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_LDQA_U8_128_XP_P (337) - XTENSA_INS_INVALID - !xtensa_ee_ldqa_u8_128_xp_p, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_LDXQ_32_P (338) - XTENSA_INS_INVALID - !xtensa_ee_ldxq_32_p, $qu, $qs, $as, $sel4, $sel8 */ + 0 +}}}, +{{{ /* XTENSA_EE_LD_128_USAR_IP_P (339) - XTENSA_INS_INVALID - !xtensa_ee_ld_128_usar_ip_p, $qu, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_LD_128_USAR_XP_P (340) - XTENSA_INS_INVALID - !xtensa_ee_ld_128_usar_xp_p, $qu, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_LD_ACCX_IP_P (341) - XTENSA_INS_INVALID - !xtensa_ee_ld_accx_ip_p, $as, $imm8 */ + 0 +}}}, +{{{ /* XTENSA_EE_LD_QACC_H_H_32_IP_P (342) - XTENSA_INS_INVALID - !xtensa_ee_ld_qacc_h_h_32_ip_p, $as, $imm4 */ + 0 +}}}, +{{{ /* XTENSA_EE_LD_QACC_H_L_128_IP_P (343) - XTENSA_INS_INVALID - !xtensa_ee_ld_qacc_h_l_128_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_LD_QACC_L_H_32_IP_P (344) - XTENSA_INS_INVALID - !xtensa_ee_ld_qacc_l_h_32_ip_p, $as, $imm4 */ + 0 +}}}, +{{{ /* XTENSA_EE_LD_QACC_L_L_128_IP_P (345) - XTENSA_INS_INVALID - !xtensa_ee_ld_qacc_l_l_128_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_LD_UA_STATE_IP_P (346) - XTENSA_INS_INVALID - !xtensa_ee_ld_ua_state_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_MOVI_32_A_P (347) - XTENSA_INS_INVALID - !xtensa_ee_movi_32_a_p, $qs, $au, $sel4 */ + 0 +}}}, +{{{ /* XTENSA_EE_MOVI_32_Q_P (348) - XTENSA_INS_INVALID - !xtensa_ee_movi_32_q_p, $qu, $as, $sel4 */ + 0 +}}}, +{{{ /* XTENSA_EE_MOV_S16_QACC_P (349) - XTENSA_INS_INVALID - !xtensa_ee_mov_s16_qacc_p, $qs */ + 0 +}}}, +{{{ /* XTENSA_EE_MOV_S8_QACC_P (350) - XTENSA_INS_INVALID - !xtensa_ee_mov_s8_qacc_p, $qs */ + 0 +}}}, +{{{ /* XTENSA_EE_MOV_U16_QACC_P (351) - XTENSA_INS_INVALID - !xtensa_ee_mov_u16_qacc_p, $qs */ + 0 +}}}, +{{{ /* XTENSA_EE_MOV_U8_QACC_P (352) - XTENSA_INS_INVALID - !xtensa_ee_mov_u8_qacc_p, $qs */ + 0 +}}}, +{{{ /* XTENSA_EE_NOTQ_P (353) - XTENSA_INS_INVALID - !xtensa_ee_notq_p, $qa, $qx */ + 0 +}}}, +{{{ /* XTENSA_EE_ORQ_P (354) - XTENSA_INS_INVALID - !xtensa_ee_orq_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_SLCI_2Q_P (355) - XTENSA_INS_INVALID - !xtensa_ee_slci_2q_p, $qs1, $qs0, $sar16 */ + 0 +}}}, +{{{ /* XTENSA_EE_SLCXXP_2Q_P (356) - XTENSA_INS_INVALID - !xtensa_ee_slcxxp_2q_p, $qs1, $qs0, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_SRCI_2Q_P (357) - XTENSA_INS_INVALID - !xtensa_ee_srci_2q_p, $qs1, $qs0, $sar16 */ + 0 +}}}, +{{{ /* XTENSA_EE_SRCMB_S16_QACC_P (358) - XTENSA_INS_INVALID - !xtensa_ee_srcmb_s16_qacc_p, $qu, $as, $sel2 */ + 0 +}}}, +{{{ /* XTENSA_EE_SRCMB_S8_QACC_P (359) - XTENSA_INS_INVALID - !xtensa_ee_srcmb_s8_qacc_p, $qu, $as, $sel2 */ + 0 +}}}, +{{{ /* XTENSA_EE_SRCQ_128_ST_INCP_P (360) - XTENSA_INS_INVALID - !xtensa_ee_srcq_128_st_incp_p, $qs0, $qs1, $as */ + 0 +}}}, +{{{ /* XTENSA_EE_SRCXXP_2Q_P (361) - XTENSA_INS_INVALID - !xtensa_ee_srcxxp_2q_p, $qs1, $qs0, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_SRC_Q_LD_IP_P (362) - XTENSA_INS_INVALID - !xtensa_ee_src_q_ld_ip_p, $qu, $as, $imm16, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_SRC_Q_LD_XP_P (363) - XTENSA_INS_INVALID - !xtensa_ee_src_q_ld_xp_p, $qu, $as, $ad, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_SRC_Q_P (364) - XTENSA_INS_INVALID - !xtensa_ee_src_q_p, $qa, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_SRC_Q_QUP_P (365) - XTENSA_INS_INVALID - !xtensa_ee_src_q_qup_p, $qa, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_SRS_ACCX_P (366) - XTENSA_INS_INVALID - !xtensa_ee_srs_accx_p, $au, $as, $sel2 */ + 0 +}}}, +{{{ /* XTENSA_EE_STF_128_IP_P (367) - XTENSA_INS_INVALID - !xtensa_ee_stf_128_ip_p, $fv3, $fv2, $fv1, $fv0, $as, $imm16f */ + 0 +}}}, +{{{ /* XTENSA_EE_STF_128_XP_P (368) - XTENSA_INS_INVALID - !xtensa_ee_stf_128_xp_p, $fv3, $fv2, $fv1, $fv0, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_STF_64_IP_P (369) - XTENSA_INS_INVALID - !xtensa_ee_stf_64_ip_p, $fv1, $fv0, $as, $imm8 */ + 0 +}}}, +{{{ /* XTENSA_EE_STF_64_XP_P (370) - XTENSA_INS_INVALID - !xtensa_ee_stf_64_xp_p, $fv1, $fv0, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_STXQ_32_P (371) - XTENSA_INS_INVALID - !xtensa_ee_stxq_32_p, $qv, $qs, $as, $sel4, $sel8 */ + 0 +}}}, +{{{ /* XTENSA_EE_ST_ACCX_IP_P (372) - XTENSA_INS_INVALID - !xtensa_ee_st_accx_ip_p, $as, $imm8 */ + 0 +}}}, +{{{ /* XTENSA_EE_ST_QACC_H_H_32_IP_P (373) - XTENSA_INS_INVALID - !xtensa_ee_st_qacc_h_h_32_ip_p, $as, $imm4 */ + 0 +}}}, +{{{ /* XTENSA_EE_ST_QACC_H_L_128_IP_P (374) - XTENSA_INS_INVALID - !xtensa_ee_st_qacc_h_l_128_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_ST_QACC_L_H_32_IP_P (375) - XTENSA_INS_INVALID - !xtensa_ee_st_qacc_l_h_32_ip_p, $as, $imm4 */ + 0 +}}}, +{{{ /* XTENSA_EE_ST_QACC_L_L_128_IP_P (376) - XTENSA_INS_INVALID - !xtensa_ee_st_qacc_l_l_128_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_ST_UA_STATE_IP_P (377) - XTENSA_INS_INVALID - !xtensa_ee_st_ua_state_ip_p, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S16_LD_INCP_P (378) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S16_P (379) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s16_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S16_ST_INCP_P (380) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s16_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S32_LD_INCP_P (381) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S32_P (382) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s32_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S32_ST_INCP_P (383) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s32_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S8_LD_INCP_P (384) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S8_P (385) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s8_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VADDS_S8_ST_INCP_P (386) - XTENSA_INS_INVALID - !xtensa_ee_vadds_s8_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_EQ_S16_P (387) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_eq_s16_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_EQ_S32_P (388) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_eq_s32_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_EQ_S8_P (389) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_eq_s8_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_GT_S16_P (390) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_gt_s16_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_GT_S32_P (391) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_gt_s32_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_GT_S8_P (392) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_gt_s8_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_LT_S16_P (393) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_lt_s16_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_LT_S32_P (394) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_lt_s32_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VCMP_LT_S8_P (395) - XTENSA_INS_INVALID - !xtensa_ee_vcmp_lt_s8_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_16_IP_P (396) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_16_ip_p, $qu, $as, $imm2 */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_16_P (397) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_16_p, $qu, $as */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_16_XP_P (398) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_16_xp_p, $qu, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_32_IP_P (399) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_32_ip_p, $qu, $as, $imm4 */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_32_P (400) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_32_p, $qu, $as */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_32_XP_P (401) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_32_xp_p, $qu, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_8_IP_P (402) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_8_ip_p, $qu, $as, $imm1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_8_P (403) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_8_p, $qu, $as */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDBC_8_XP_P (404) - XTENSA_INS_INVALID - !xtensa_ee_vldbc_8_xp_p, $qu, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VLDHBC_16_INCP_P (405) - XTENSA_INS_INVALID - !xtensa_ee_vldhbc_16_incp_p, $qu, $qu1, $as */ + 0 +}}}, +{{{ /* XTENSA_EE_VLD_128_IP_P (406) - XTENSA_INS_INVALID - !xtensa_ee_vld_128_ip_p, $qu, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_VLD_128_XP_P (407) - XTENSA_INS_INVALID - !xtensa_ee_vld_128_xp_p, $qu, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VLD_H_64_IP_P (408) - XTENSA_INS_INVALID - !xtensa_ee_vld_h_64_ip_p, $qu, $as, $imm8 */ + 0 +}}}, +{{{ /* XTENSA_EE_VLD_H_64_XP_P (409) - XTENSA_INS_INVALID - !xtensa_ee_vld_h_64_xp_p, $qu, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VLD_L_64_IP_P (410) - XTENSA_INS_INVALID - !xtensa_ee_vld_l_64_ip_p, $qu, $as, $imm8 */ + 0 +}}}, +{{{ /* XTENSA_EE_VLD_L_64_XP_P (411) - XTENSA_INS_INVALID - !xtensa_ee_vld_l_64_xp_p, $qu, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S16_LD_INCP_P (412) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S16_P (413) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s16_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S16_ST_INCP_P (414) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s16_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S32_LD_INCP_P (415) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S32_P (416) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s32_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S32_ST_INCP_P (417) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s32_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S8_LD_INCP_P (418) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S8_P (419) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s8_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMAX_S8_ST_INCP_P (420) - XTENSA_INS_INVALID - !xtensa_ee_vmax_s8_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S16_LD_INCP_P (421) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S16_P (422) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s16_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S16_ST_INCP_P (423) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s16_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S32_LD_INCP_P (424) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S32_P (425) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s32_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S32_ST_INCP_P (426) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s32_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S8_LD_INCP_P (427) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S8_P (428) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s8_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMIN_S8_ST_INCP_P (429) - XTENSA_INS_INVALID - !xtensa_ee_vmin_s8_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_ACCX_LD_IP_P (430) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_ACCX_LD_IP_QUP_P (431) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_ACCX_LD_XP_P (432) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_ACCX_LD_XP_QUP_P (433) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_ACCX_P (434) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_accx_p, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_QACC_LDBC_INCP_P (435) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_qacc_ldbc_incp_p, $qu, $as, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P (436) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_QACC_LD_IP_P (437) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_QACC_LD_IP_QUP_P (438) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_QACC_LD_XP_P (439) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_QACC_LD_XP_QUP_P (440) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S16_QACC_P (441) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s16_qacc_p, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_ACCX_LD_IP_P (442) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_ACCX_LD_IP_QUP_P (443) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_ACCX_LD_XP_P (444) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_ACCX_LD_XP_QUP_P (445) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_ACCX_P (446) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_accx_p, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_QACC_LDBC_INCP_P (447) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_qacc_ldbc_incp_p, $qu, $as, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P (448) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_QACC_LD_IP_P (449) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_QACC_LD_IP_QUP_P (450) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_QACC_LD_XP_P (451) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_QACC_LD_XP_QUP_P (452) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_S8_QACC_P (453) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_s8_qacc_p, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_ACCX_LD_IP_P (454) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_ACCX_LD_IP_QUP_P (455) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_ACCX_LD_XP_P (456) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_ACCX_LD_XP_QUP_P (457) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_ACCX_P (458) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_accx_p, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_QACC_LDBC_INCP_P (459) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_qacc_ldbc_incp_p, $qu, $as, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P (460) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_QACC_LD_IP_P (461) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_QACC_LD_IP_QUP_P (462) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_QACC_LD_XP_P (463) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_QACC_LD_XP_QUP_P (464) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U16_QACC_P (465) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u16_qacc_p, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_ACCX_LD_IP_P (466) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_accx_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_ACCX_LD_IP_QUP_P (467) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_accx_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_ACCX_LD_XP_P (468) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_accx_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_ACCX_LD_XP_QUP_P (469) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_accx_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_ACCX_P (470) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_accx_p, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_QACC_LDBC_INCP_P (471) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_qacc_ldbc_incp_p, $qu, $as, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P (472) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_qacc_ldbc_incp_qup_p, $qu, $as, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_QACC_LD_IP_P (473) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_qacc_ld_ip_p, $qu, $as, $imm16, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_QACC_LD_IP_QUP_P (474) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_qacc_ld_ip_qup_p, $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_QACC_LD_XP_P (475) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_qacc_ld_xp_p, $qu, $as, $ad, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_QACC_LD_XP_QUP_P (476) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_qacc_ld_xp_qup_p, $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VMULAS_U8_QACC_P (477) - XTENSA_INS_INVALID - !xtensa_ee_vmulas_u8_qacc_p, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_S16_LD_INCP_P (478) - XTENSA_INS_INVALID - !xtensa_ee_vmul_s16_ld_incp_p, $qu, $as, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_S16_P (479) - XTENSA_INS_INVALID - !xtensa_ee_vmul_s16_p, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_S16_ST_INCP_P (480) - XTENSA_INS_INVALID - !xtensa_ee_vmul_s16_st_incp_p, $qv, $as, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_S8_LD_INCP_P (481) - XTENSA_INS_INVALID - !xtensa_ee_vmul_s8_ld_incp_p, $qu, $as, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_S8_P (482) - XTENSA_INS_INVALID - !xtensa_ee_vmul_s8_p, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_S8_ST_INCP_P (483) - XTENSA_INS_INVALID - !xtensa_ee_vmul_s8_st_incp_p, $qv, $as, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_U16_LD_INCP_P (484) - XTENSA_INS_INVALID - !xtensa_ee_vmul_u16_ld_incp_p, $qu, $as, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_U16_P (485) - XTENSA_INS_INVALID - !xtensa_ee_vmul_u16_p, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_U16_ST_INCP_P (486) - XTENSA_INS_INVALID - !xtensa_ee_vmul_u16_st_incp_p, $qv, $as, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_U8_LD_INCP_P (487) - XTENSA_INS_INVALID - !xtensa_ee_vmul_u8_ld_incp_p, $qu, $as, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_U8_P (488) - XTENSA_INS_INVALID - !xtensa_ee_vmul_u8_p, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VMUL_U8_ST_INCP_P (489) - XTENSA_INS_INVALID - !xtensa_ee_vmul_u8_st_incp_p, $qv, $as, $qz, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VPRELU_S16_P (490) - XTENSA_INS_INVALID - !xtensa_ee_vprelu_s16_p, $qz, $qx, $qy, $ay */ + 0 +}}}, +{{{ /* XTENSA_EE_VPRELU_S8_P (491) - XTENSA_INS_INVALID - !xtensa_ee_vprelu_s8_p, $qz, $qx, $qy, $ay */ + 0 +}}}, +{{{ /* XTENSA_EE_VRELU_S16_P (492) - XTENSA_INS_INVALID - !xtensa_ee_vrelu_s16_p, $qs, $ax, $ay */ + 0 +}}}, +{{{ /* XTENSA_EE_VRELU_S8_P (493) - XTENSA_INS_INVALID - !xtensa_ee_vrelu_s8_p, $qs, $ax, $ay */ + 0 +}}}, +{{{ /* XTENSA_EE_VSL_32_P (494) - XTENSA_INS_INVALID - !xtensa_ee_vsl_32_p, $qa, $qs */ + 0 +}}}, +{{{ /* XTENSA_EE_VSMULAS_S16_QACC_LD_INCP_P (495) - XTENSA_INS_INVALID - !xtensa_ee_vsmulas_s16_qacc_ld_incp_p, $qu, $as, $qx, $qy, $sel8 */ + 0 +}}}, +{{{ /* XTENSA_EE_VSMULAS_S16_QACC_P (496) - XTENSA_INS_INVALID - !xtensa_ee_vsmulas_s16_qacc_p, $qx, $qy, $sel8 */ + 0 +}}}, +{{{ /* XTENSA_EE_VSMULAS_S8_QACC_LD_INCP_P (497) - XTENSA_INS_INVALID - !xtensa_ee_vsmulas_s8_qacc_ld_incp_p, $qu, $as, $qx, $qy, $sel16 */ + 0 +}}}, +{{{ /* XTENSA_EE_VSMULAS_S8_QACC_P (498) - XTENSA_INS_INVALID - !xtensa_ee_vsmulas_s8_qacc_p, $qx, $qy, $sel16 */ + 0 +}}}, +{{{ /* XTENSA_EE_VSR_32_P (499) - XTENSA_INS_INVALID - !xtensa_ee_vsr_32_p, $qa, $qs */ + 0 +}}}, +{{{ /* XTENSA_EE_VST_128_IP_P (500) - XTENSA_INS_INVALID - !xtensa_ee_vst_128_ip_p, $qv, $as, $imm16 */ + 0 +}}}, +{{{ /* XTENSA_EE_VST_128_XP_P (501) - XTENSA_INS_INVALID - !xtensa_ee_vst_128_xp_p, $qv, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VST_H_64_IP_P (502) - XTENSA_INS_INVALID - !xtensa_ee_vst_h_64_ip_p, $qv, $as, $imm8 */ + 0 +}}}, +{{{ /* XTENSA_EE_VST_H_64_XP_P (503) - XTENSA_INS_INVALID - !xtensa_ee_vst_h_64_xp_p, $qv, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VST_L_64_IP_P (504) - XTENSA_INS_INVALID - !xtensa_ee_vst_l_64_ip_p, $qv, $as, $imm8 */ + 0 +}}}, +{{{ /* XTENSA_EE_VST_L_64_XP_P (505) - XTENSA_INS_INVALID - !xtensa_ee_vst_l_64_xp_p, $qv, $as, $ad */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S16_LD_INCP_P (506) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s16_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S16_P (507) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s16_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S16_ST_INCP_P (508) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s16_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S32_LD_INCP_P (509) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s32_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S32_P (510) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s32_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S32_ST_INCP_P (511) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s32_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S8_LD_INCP_P (512) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s8_ld_incp_p, $qu, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S8_P (513) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s8_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VSUBS_S8_ST_INCP_P (514) - XTENSA_INS_INVALID - !xtensa_ee_vsubs_s8_st_incp_p, $qv, $as, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_VUNZIP_16_P (515) - XTENSA_INS_INVALID - !xtensa_ee_vunzip_16_p, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VUNZIP_32_P (516) - XTENSA_INS_INVALID - !xtensa_ee_vunzip_32_p, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VUNZIP_8_P (517) - XTENSA_INS_INVALID - !xtensa_ee_vunzip_8_p, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VZIP_16_P (518) - XTENSA_INS_INVALID - !xtensa_ee_vzip_16_p, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VZIP_32_P (519) - XTENSA_INS_INVALID - !xtensa_ee_vzip_32_p, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_VZIP_8_P (520) - XTENSA_INS_INVALID - !xtensa_ee_vzip_8_p, $qs0, $qs1 */ + 0 +}}}, +{{{ /* XTENSA_EE_XORQ_P (521) - XTENSA_INS_INVALID - !xtensa_ee_xorq_p, $qa, $qx, $qy */ + 0 +}}}, +{{{ /* XTENSA_EE_ZERO_ACCX_P (522) - XTENSA_INS_INVALID - !xtensa_ee_zero_accx_p */ + 0 +}}}, +{{{ /* XTENSA_EE_ZERO_QACC_P (523) - XTENSA_INS_INVALID - !xtensa_ee_zero_qacc_p */ + 0 +}}}, +{{{ /* XTENSA_EE_ZERO_Q_P (524) - XTENSA_INS_INVALID - !xtensa_ee_zero_q_p, $qa */ + 0 +}}}, +{{{ /* XTENSA_EXTUI_BR2_P (525) - XTENSA_INS_INVALID - !extui_br2 $r, $s, $b */ + 0 +}}}, +{{{ /* XTENSA_EXTUI_BR4_P (526) - XTENSA_INS_INVALID - !extui_br4 $r, $s, $b */ + 0 +}}}, +{{{ /* XTENSA_EXTUI_BR_P (527) - XTENSA_INS_INVALID - !extui_br $r, $s, $b */ + 0 +}}}, +{{{ /* XTENSA_L8I_P (528) - XTENSA_INS_INVALID - !L8I_P $t, $addr */ + 0 +}}}, +{{{ /* XTENSA_LDDEC_P (529) - XTENSA_INS_INVALID - !xtensa_lddec_p, $mw, $s */ + 0 +}}}, +{{{ /* XTENSA_LDINC_P (530) - XTENSA_INS_INVALID - !xtensa_ldinc_p, $mw, $s */ + 0 +}}}, +{{{ /* XTENSA_LOOPBR (531) - XTENSA_INS_INVALID - !loopbr $elts, $target */ + 0 +}}}, +{{{ /* XTENSA_LOOPDEC (532) - XTENSA_INS_INVALID - !loopdec $eltsout, $eltsin */ + 0 +}}}, +{{{ /* XTENSA_LOOPEND (533) - XTENSA_INS_INVALID - !loopend $target */ + 0 +}}}, +{{{ /* XTENSA_LOOPINIT (534) - XTENSA_INS_INVALID - !loopinit $elts, $eltsin */ + 0 +}}}, +{{{ /* XTENSA_LOOPSTART (535) - XTENSA_INS_INVALID - !loopstart $s, $target */ + 0 +}}}, +{{{ /* XTENSA_MOVBA2_P (536) - XTENSA_INS_INVALID - !movba2 $r, $s */ + 0 +}}}, +{{{ /* XTENSA_MOVBA2_P2 (537) - XTENSA_INS_INVALID - !movba $r, $x, $y, $s */ + 0 +}}}, +{{{ /* XTENSA_MOVBA4_P (538) - XTENSA_INS_INVALID - !movba4 $r, $s */ + 0 +}}}, +{{{ /* XTENSA_MOVBA4_P2 (539) - XTENSA_INS_INVALID - !movba4 $r, $x, $y, $s */ + 0 +}}}, +{{{ /* XTENSA_MOVBA_P (540) - XTENSA_INS_INVALID - !movba $r, $s */ + 0 +}}}, +{{{ /* XTENSA_MOVBA_P2 (541) - XTENSA_INS_INVALID - !movba $r, $x, $y, $s */ + 0 +}}}, +{{{ /* XTENSA_MULA_DA_HH_LDDEC_P (542) - XTENSA_INS_INVALID - !xtensa_mula_da_hh_lddec_p, $mw, $s, $mx, $t */ + 0 +}}}, +{{{ /* XTENSA_MULA_DA_HH_LDINC_P (543) - XTENSA_INS_INVALID - !xtensa_mula_da_hh_ldinc_p, $mw, $s, $mx, $t */ + 0 +}}}, +{{{ /* XTENSA_MULA_DA_HL_LDDEC_P (544) - XTENSA_INS_INVALID - !xtensa_mula_da_hl_lddec_p, $mw, $s, $mx, $t */ + 0 +}}}, +{{{ /* XTENSA_MULA_DA_HL_LDINC_P (545) - XTENSA_INS_INVALID - !xtensa_mula_da_hl_ldinc_p, $mw, $s, $mx, $t */ + 0 +}}}, +{{{ /* XTENSA_MULA_DA_LH_LDDEC_P (546) - XTENSA_INS_INVALID - !xtensa_mula_da_lh_lddec_p, $mw, $s, $mx, $t */ + 0 +}}}, +{{{ /* XTENSA_MULA_DA_LH_LDINC_P (547) - XTENSA_INS_INVALID - !xtensa_mula_da_lh_ldinc_p, $mw, $s, $mx, $t */ + 0 +}}}, +{{{ /* XTENSA_MULA_DA_LL_LDDEC_P (548) - XTENSA_INS_INVALID - !xtensa_mula_da_ll_lddec_p, $mw, $s, $mx, $t */ + 0 +}}}, +{{{ /* XTENSA_MULA_DA_LL_LDINC_P (549) - XTENSA_INS_INVALID - !xtensa_mula_da_ll_ldinc_p, $mw, $s, $mx, $t */ + 0 +}}}, +{{{ /* XTENSA_MULA_DD_HH_LDDEC_P (550) - XTENSA_INS_INVALID - !xtensa_mula_dd_hh_lddec_p, $mw, $s, $mx, $my */ + 0 +}}}, +{{{ /* XTENSA_MULA_DD_HH_LDINC_P (551) - XTENSA_INS_INVALID - !xtensa_mula_dd_hh_ldinc_p, $mw, $s, $mx, $my */ + 0 +}}}, +{{{ /* XTENSA_MULA_DD_HL_LDDEC_P (552) - XTENSA_INS_INVALID - !xtensa_mula_dd_hl_lddec_p, $mw, $s, $mx, $my */ + 0 +}}}, +{{{ /* XTENSA_MULA_DD_HL_LDINC_P (553) - XTENSA_INS_INVALID - !xtensa_mula_dd_hl_ldinc_p, $mw, $s, $mx, $my */ + 0 +}}}, +{{{ /* XTENSA_MULA_DD_LH_LDDEC_P (554) - XTENSA_INS_INVALID - !xtensa_mula_dd_lh_lddec_p, $mw, $s, $mx, $my */ + 0 +}}}, +{{{ /* XTENSA_MULA_DD_LH_LDINC_P (555) - XTENSA_INS_INVALID - !xtensa_mula_dd_lh_ldinc_p, $mw, $s, $mx, $my */ + 0 +}}}, +{{{ /* XTENSA_MULA_DD_LL_LDDEC_P (556) - XTENSA_INS_INVALID - !xtensa_mula_dd_ll_lddec_p, $mw, $s, $mx, $my */ + 0 +}}}, +{{{ /* XTENSA_MULA_DD_LL_LDINC_P (557) - XTENSA_INS_INVALID - !xtensa_mula_dd_ll_ldinc_p, $mw, $s, $mx, $my */ + 0 +}}}, +{{{ /* XTENSA_RESTORE_BOOL (558) - XTENSA_INS_INVALID - !restore_bool $out, $mem */ + 0 +}}}, +{{{ /* XTENSA_SELECT (559) - XTENSA_INS_INVALID - !select $dst, $lhs, $rhs, $t, $f, $cond */ + 0 +}}}, +{{{ /* XTENSA_SELECT_CC_FP_FP (560) - XTENSA_INS_INVALID - !select_cc_fp_fp $dst, $lhs, $rhs, $t, $f, $cond */ + 0 +}}}, +{{{ /* XTENSA_SELECT_CC_FP_INT (561) - XTENSA_INS_INVALID - !select_cc_fp_int $dst, $lhs, $rhs, $t, $f, $cond */ + 0 +}}}, +{{{ /* XTENSA_SELECT_CC_INT_FP (562) - XTENSA_INS_INVALID - !select_cc_int_fp $dst, $lhs, $rhs, $t, $f, $cond */ + 0 +}}}, +{{{ /* XTENSA_SLLI_BR_P (563) - XTENSA_INS_INVALID - !slli_br $r, $s, $b */ + 0 +}}}, +{{{ /* XTENSA_SLL_P (564) - XTENSA_INS_INVALID - # SLL_P $r, $s, $sa */ + 0 +}}}, +{{{ /* XTENSA_SPILL_BOOL (565) - XTENSA_INS_INVALID - !spill_bool $b, $mem */ + 0 +}}}, +{{{ /* XTENSA_SRA_P (566) - XTENSA_INS_INVALID - # SRA_P $r, $t, $sa */ + 0 +}}}, +{{{ /* XTENSA_SRL_P (567) - XTENSA_INS_INVALID - # SRL_P $r, $t, $sa */ + 0 +}}}, +{{{ /* XTENSA_WSR_ACCHI_P (568) - XTENSA_INS_INVALID - !xtensa_wsr_acchi_p, $s */ + 0 +}}}, +{{{ /* XTENSA_WSR_ACCLO_P (569) - XTENSA_INS_INVALID - !xtensa_wsr_acclo_p, $s */ + 0 +}}}, +{{{ /* XTENSA_WSR_M0_P (570) - XTENSA_INS_INVALID - !xtensa_wsr_m0_p, $s */ + 0 +}}}, +{{{ /* XTENSA_WSR_M1_P (571) - XTENSA_INS_INVALID - !xtensa_wsr_m1_p, $s */ + 0 +}}}, +{{{ /* XTENSA_WSR_M2_P (572) - XTENSA_INS_INVALID - !xtensa_wsr_m2_p, $s */ + 0 +}}}, +{{{ /* XTENSA_WSR_M3_P (573) - XTENSA_INS_INVALID - !xtensa_wsr_m3_p, $s */ + 0 +}}}, +{{{ /* XTENSA_XSR_ACCHI_P (574) - XTENSA_INS_INVALID - !xtensa_xsr_acchi_p, $s */ + 0 +}}}, +{{{ /* XTENSA_XSR_ACCLO_P (575) - XTENSA_INS_INVALID - !xtensa_xsr_acclo_p, $s */ + 0 +}}}, +{{{ /* XTENSA_XSR_M0_P (576) - XTENSA_INS_INVALID - !xtensa_xsr_m0_p, $s */ + 0 +}}}, +{{{ /* XTENSA_XSR_M1_P (577) - XTENSA_INS_INVALID - !xtensa_xsr_m1_p, $s */ + 0 +}}}, +{{{ /* XTENSA_XSR_M2_P (578) - XTENSA_INS_INVALID - !xtensa_xsr_m2_p, $s */ + 0 +}}}, +{{{ /* XTENSA_XSR_M3_P (579) - XTENSA_INS_INVALID - !xtensa_xsr_m3_p, $s */ + 0 +}}}, +{{{ /* XTENSA_mv_QR_P (580) - XTENSA_INS_INVALID - !xtensa_mv_qr_p, $a, $b */ + 0 +}}}, +{ /* XTENSA_ABS (581) - XTENSA_INS_ABS - abs $r, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ABS_S (582) - XTENSA_INS_ABS_S - abs.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_ADD (583) - XTENSA_INS_ADD - add $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ADDEXPM_S (584) - XTENSA_INS_ADDEXPM_S - addexpm.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_ADDEXP_S (585) - XTENSA_INS_ADDEXP_S - addexp.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_ADDI (586) - XTENSA_INS_ADDI - addi $t, $s, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_ADDI_N (587) - XTENSA_INS_ADDI_N - addi.n $r, $s, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_ADDMI (588) - XTENSA_INS_ADDMI - addmi $t, $s, $imm_sh8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm_sh8 */ + { 0 } +}}, +{ /* XTENSA_ADDX2 (589) - XTENSA_INS_ADDX2 - addx2 $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ADDX4 (590) - XTENSA_INS_ADDX4 - addx4 $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ADDX8 (591) - XTENSA_INS_ADDX8 - addx8 $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ADD_N (592) - XTENSA_INS_ADD_N - add.n $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ADD_S (593) - XTENSA_INS_ADD_S - add.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_AE_ABS16S (594) - XTENSA_INS_AE_ABS16S - ae_abs16s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ABS24S (595) - XTENSA_INS_AE_ABS24S - ae_abs24s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ABS32 (596) - XTENSA_INS_AE_ABS32 - ae_abs32 $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ABS32S (597) - XTENSA_INS_AE_ABS32S - ae_abs32s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ABS64 (598) - XTENSA_INS_AE_ABS64 - ae_abs64 $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ABS64S (599) - XTENSA_INS_AE_ABS64S - ae_abs64s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADD16 (600) - XTENSA_INS_AE_ADD16 - ae_add16 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADD16S (601) - XTENSA_INS_AE_ADD16S - ae_add16s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADD24S (602) - XTENSA_INS_AE_ADD24S - ae_add24s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADD32 (603) - XTENSA_INS_AE_ADD32 - ae_add32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADD32S (604) - XTENSA_INS_AE_ADD32S - ae_add32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADD32_HL_LH (605) - XTENSA_INS_AE_ADD32_HL_LH - ae_add32_hl_lh $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADD64 (606) - XTENSA_INS_AE_ADD64 - ae_add64 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADD64S (607) - XTENSA_INS_AE_ADD64S - ae_add64s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADDBRBA32 (608) - XTENSA_INS_AE_ADDBRBA32 - ae_addbrba32 $arr, $art, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_ADDSUB32 (609) - XTENSA_INS_AE_ADDSUB32 - ae_addsub32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ADDSUB32S (610) - XTENSA_INS_AE_ADDSUB32S - ae_addsub32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_AND (611) - XTENSA_INS_AE_AND - ae_and $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_CVT32X2F16_10 (612) - XTENSA_INS_AE_CVT32X2F16_10 - ae_cvt32x2f16.10 $ae_to_dr_v, $ae_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_CVT32X2F16_32 (613) - XTENSA_INS_AE_CVT32X2F16_32 - ae_cvt32x2f16.32 $ae_to_dr_v, $ae_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_CVT48A32 (614) - XTENSA_INS_AE_CVT48A32 - ae_cvt48a32 $ae_ar_to_dr_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ar_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_CVT64A32 (615) - XTENSA_INS_AE_CVT64A32 - ae_cvt64a32 $ae_ar_to_dr_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ar_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_CVT64F32_H (616) - XTENSA_INS_AE_CVT64F32_H - ae_cvt64f32.h $ae_dr_to_dr_v, $ae_dr_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_CVTA32F24S_H (617) - XTENSA_INS_AE_CVTA32F24S_H - ae_cvta32f24s.h $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_CVTA32F24S_L (618) - XTENSA_INS_AE_CVTA32F24S_L - ae_cvta32f24s.l $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_CVTQ56A32S (619) - XTENSA_INS_AE_CVTQ56A32S - ae_cvtq56a32s $ae_ar_to_dr_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ar_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_CVTQ56P32S_H (620) - XTENSA_INS_AE_CVTQ56P32S_H - ae_cvtq56p32s.h $ae_dr_to_dr_v, $ae_dr_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_CVTQ56P32S_L (621) - XTENSA_INS_AE_CVTQ56P32S_L - ae_cvtq56p32s.l $ae_dr_to_dr_v, $ae_dr_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_DB (622) - XTENSA_INS_AE_DB - ae_db $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_DBI (623) - XTENSA_INS_AE_DBI - ae_dbi $ars, $ae_ohba */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba */ + { 0 } +}}, +{ /* XTENSA_AE_DBI_IC (624) - XTENSA_INS_AE_DBI_IC - ae_dbi.ic $ars, $ae_ohba */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba */ + { 0 } +}}, +{ /* XTENSA_AE_DBI_IP (625) - XTENSA_INS_AE_DBI_IP - ae_dbi.ip $ars, $ae_ohba */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba */ + { 0 } +}}, +{ /* XTENSA_AE_DB_IC (626) - XTENSA_INS_AE_DB_IC - ae_db.ic $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_DB_IP (627) - XTENSA_INS_AE_DB_IP - ae_db.ip $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_DIV64D32_H (628) - XTENSA_INS_AE_DIV64D32_H - ae_div64d32.h $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_DIV64D32_L (629) - XTENSA_INS_AE_DIV64D32_L - ae_div64d32.l $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_EQ16 (630) - XTENSA_INS_AE_EQ16 - ae_eq16 $br4, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i1, CS_DATA_TYPE_LAST } }, /* br4 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_EQ32 (631) - XTENSA_INS_AE_EQ32 - ae_eq32 $br2, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* br2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_EQ64 (632) - XTENSA_INS_AE_EQ64 - ae_eq64 $br, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* br */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_L16M_I (633) - XTENSA_INS_AE_L16M_I - ae_l16m.i $ae_ls_v, $ars, $ae_immls16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls16 */ + { 0 } +}}, +{ /* XTENSA_AE_L16M_IU (634) - XTENSA_INS_AE_L16M_IU - ae_l16m.iu $ae_ls_v, $ars, $ae_immls16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls16 */ + { 0 } +}}, +{ /* XTENSA_AE_L16M_X (635) - XTENSA_INS_AE_L16M_X - ae_l16m.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16M_XC (636) - XTENSA_INS_AE_L16M_XC - ae_l16m.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16M_XU (637) - XTENSA_INS_AE_L16M_XU - ae_l16m.xu $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16X2M_I (638) - XTENSA_INS_AE_L16X2M_I - ae_l16x2m.i $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_L16X2M_IU (639) - XTENSA_INS_AE_L16X2M_IU - ae_l16x2m.iu $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_L16X2M_X (640) - XTENSA_INS_AE_L16X2M_X - ae_l16x2m.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16X2M_XC (641) - XTENSA_INS_AE_L16X2M_XC - ae_l16x2m.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16X2M_XU (642) - XTENSA_INS_AE_L16X2M_XU - ae_l16x2m.xu $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16X4_I (643) - XTENSA_INS_AE_L16X4_I - ae_l16x4.i $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_L16X4_IP (644) - XTENSA_INS_AE_L16X4_IP - ae_l16x4.ip $ae_ls_v, $ars, $ae_immls64pos */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64pos */ + { 0 } +}}, +{ /* XTENSA_AE_L16X4_RIC (645) - XTENSA_INS_AE_L16X4_RIC - ae_l16x4.ric $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_L16X4_RIP (646) - XTENSA_INS_AE_L16X4_RIP - ae_l16x4.rip $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_L16X4_X (647) - XTENSA_INS_AE_L16X4_X - ae_l16x4.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16X4_XC (648) - XTENSA_INS_AE_L16X4_XC - ae_l16x4.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16X4_XP (649) - XTENSA_INS_AE_L16X4_XP - ae_l16x4.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16_I (650) - XTENSA_INS_AE_L16_I - ae_l16.i $ae_ls_v, $ars, $ae_immls16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls16 */ + { 0 } +}}, +{ /* XTENSA_AE_L16_IP (651) - XTENSA_INS_AE_L16_IP - ae_l16.ip $ae_ls_v, $ars, $ae_immls16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls16 */ + { 0 } +}}, +{ /* XTENSA_AE_L16_X (652) - XTENSA_INS_AE_L16_X - ae_l16.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16_XC (653) - XTENSA_INS_AE_L16_XC - ae_l16.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L16_XP (654) - XTENSA_INS_AE_L16_XP - ae_l16.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32F24_I (655) - XTENSA_INS_AE_L32F24_I - ae_l32f24.i $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_L32F24_IP (656) - XTENSA_INS_AE_L32F24_IP - ae_l32f24.ip $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_L32F24_X (657) - XTENSA_INS_AE_L32F24_X - ae_l32f24.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32F24_XC (658) - XTENSA_INS_AE_L32F24_XC - ae_l32f24.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32F24_XP (659) - XTENSA_INS_AE_L32F24_XP - ae_l32f24.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32M_I (660) - XTENSA_INS_AE_L32M_I - ae_l32m.i $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_L32M_IU (661) - XTENSA_INS_AE_L32M_IU - ae_l32m.iu $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_L32M_X (662) - XTENSA_INS_AE_L32M_X - ae_l32m.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32M_XC (663) - XTENSA_INS_AE_L32M_XC - ae_l32m.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32M_XU (664) - XTENSA_INS_AE_L32M_XU - ae_l32m.xu $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2F24_I (665) - XTENSA_INS_AE_L32X2F24_I - ae_l32x2f24.i $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2F24_IP (666) - XTENSA_INS_AE_L32X2F24_IP - ae_l32x2f24.ip $ae_ls_v, $ars, $ae_immls64pos */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64pos */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2F24_RIC (667) - XTENSA_INS_AE_L32X2F24_RIC - ae_l32x2f24.ric $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2F24_RIP (668) - XTENSA_INS_AE_L32X2F24_RIP - ae_l32x2f24.rip $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2F24_X (669) - XTENSA_INS_AE_L32X2F24_X - ae_l32x2f24.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2F24_XC (670) - XTENSA_INS_AE_L32X2F24_XC - ae_l32x2f24.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2F24_XP (671) - XTENSA_INS_AE_L32X2F24_XP - ae_l32x2f24.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2_I (672) - XTENSA_INS_AE_L32X2_I - ae_l32x2.i $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2_IP (673) - XTENSA_INS_AE_L32X2_IP - ae_l32x2.ip $ae_ls_v, $ars, $ae_immls64pos */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64pos */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2_RIC (674) - XTENSA_INS_AE_L32X2_RIC - ae_l32x2.ric $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2_RIP (675) - XTENSA_INS_AE_L32X2_RIP - ae_l32x2.rip $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2_X (676) - XTENSA_INS_AE_L32X2_X - ae_l32x2.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2_XC (677) - XTENSA_INS_AE_L32X2_XC - ae_l32x2.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32X2_XP (678) - XTENSA_INS_AE_L32X2_XP - ae_l32x2.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32_I (679) - XTENSA_INS_AE_L32_I - ae_l32.i $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_L32_IP (680) - XTENSA_INS_AE_L32_IP - ae_l32.ip $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_L32_X (681) - XTENSA_INS_AE_L32_X - ae_l32.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32_XC (682) - XTENSA_INS_AE_L32_XC - ae_l32.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L32_XP (683) - XTENSA_INS_AE_L32_XP - ae_l32.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L64_I (684) - XTENSA_INS_AE_L64_I - ae_l64.i $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_L64_IP (685) - XTENSA_INS_AE_L64_IP - ae_l64.ip $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_L64_X (686) - XTENSA_INS_AE_L64_X - ae_l64.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L64_XC (687) - XTENSA_INS_AE_L64_XC - ae_l64.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_L64_XP (688) - XTENSA_INS_AE_L64_XP - ae_l64.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_LA16X4NEG_PC (689) - XTENSA_INS_AE_LA16X4NEG_PC - ae_la16x4neg.pc $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA16X4POS_PC (690) - XTENSA_INS_AE_LA16X4POS_PC - ae_la16x4pos.pc $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA16X4_IC (691) - XTENSA_INS_AE_LA16X4_IC - ae_la16x4.ic $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA16X4_IP (692) - XTENSA_INS_AE_LA16X4_IP - ae_la16x4.ip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA16X4_RIC (693) - XTENSA_INS_AE_LA16X4_RIC - ae_la16x4.ric $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA16X4_RIP (694) - XTENSA_INS_AE_LA16X4_RIP - ae_la16x4.rip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24NEG_PC (695) - XTENSA_INS_AE_LA24NEG_PC - ae_la24neg.pc $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24POS_PC (696) - XTENSA_INS_AE_LA24POS_PC - ae_la24pos.pc $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24X2NEG_PC (697) - XTENSA_INS_AE_LA24X2NEG_PC - ae_la24x2neg.pc $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24X2POS_PC (698) - XTENSA_INS_AE_LA24X2POS_PC - ae_la24x2pos.pc $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24X2_IC (699) - XTENSA_INS_AE_LA24X2_IC - ae_la24x2.ic $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24X2_IP (700) - XTENSA_INS_AE_LA24X2_IP - ae_la24x2.ip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24X2_RIC (701) - XTENSA_INS_AE_LA24X2_RIC - ae_la24x2.ric $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24X2_RIP (702) - XTENSA_INS_AE_LA24X2_RIP - ae_la24x2.rip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24_IC (703) - XTENSA_INS_AE_LA24_IC - ae_la24.ic $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24_IP (704) - XTENSA_INS_AE_LA24_IP - ae_la24.ip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24_RIC (705) - XTENSA_INS_AE_LA24_RIC - ae_la24.ric $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA24_RIP (706) - XTENSA_INS_AE_LA24_RIP - ae_la24.rip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2F24_IC (707) - XTENSA_INS_AE_LA32X2F24_IC - ae_la32x2f24.ic $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2F24_IP (708) - XTENSA_INS_AE_LA32X2F24_IP - ae_la32x2f24.ip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2F24_RIC (709) - XTENSA_INS_AE_LA32X2F24_RIC - ae_la32x2f24.ric $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2F24_RIP (710) - XTENSA_INS_AE_LA32X2F24_RIP - ae_la32x2f24.rip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2NEG_PC (711) - XTENSA_INS_AE_LA32X2NEG_PC - ae_la32x2neg.pc $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2POS_PC (712) - XTENSA_INS_AE_LA32X2POS_PC - ae_la32x2pos.pc $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2_IC (713) - XTENSA_INS_AE_LA32X2_IC - ae_la32x2.ic $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2_IP (714) - XTENSA_INS_AE_LA32X2_IP - ae_la32x2.ip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2_RIC (715) - XTENSA_INS_AE_LA32X2_RIC - ae_la32x2.ric $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA32X2_RIP (716) - XTENSA_INS_AE_LA32X2_RIP - ae_la32x2.rip $ae_ls_av, $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_av */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LA64_PP (717) - XTENSA_INS_AE_LA64_PP - ae_la64.pp $ae_ls_uu, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_LALIGN64_I (718) - XTENSA_INS_AE_LALIGN64_I - ae_lalign64.i $ae_ls_uu, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_LB (719) - XTENSA_INS_AE_LB - ae_lb $arr, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_LBI (720) - XTENSA_INS_AE_LBI - ae_lbi $arr, $ae_ohba */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba */ + { 0 } +}}, +{ /* XTENSA_AE_LBK (721) - XTENSA_INS_AE_LBK - ae_lbk $arr, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_LBKI (722) - XTENSA_INS_AE_LBKI - ae_lbki $arr, $ars, $ae_ohba */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba */ + { 0 } +}}, +{ /* XTENSA_AE_LBS (723) - XTENSA_INS_AE_LBS - ae_lbs $arr, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_LBSI (724) - XTENSA_INS_AE_LBSI - ae_lbsi $arr, $ae_ohba */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba */ + { 0 } +}}, +{ /* XTENSA_AE_LE16 (725) - XTENSA_INS_AE_LE16 - ae_le16 $br4, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i1, CS_DATA_TYPE_LAST } }, /* br4 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_LE32 (726) - XTENSA_INS_AE_LE32 - ae_le32 $br2, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* br2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_LE64 (727) - XTENSA_INS_AE_LE64 - ae_le64 $br, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* br */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_LT16 (728) - XTENSA_INS_AE_LT16 - ae_lt16 $br4, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i1, CS_DATA_TYPE_LAST } }, /* br4 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_LT32 (729) - XTENSA_INS_AE_LT32 - ae_lt32 $br2, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* br2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_LT64 (730) - XTENSA_INS_AE_LT64 - ae_lt64 $br, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* br */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MAX32 (731) - XTENSA_INS_AE_MAX32 - ae_max32 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MAX64 (732) - XTENSA_INS_AE_MAX64 - ae_max64 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MAXABS32S (733) - XTENSA_INS_AE_MAXABS32S - ae_maxabs32s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MAXABS64S (734) - XTENSA_INS_AE_MAXABS64S - ae_maxabs64s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MIN32 (735) - XTENSA_INS_AE_MIN32 - ae_min32 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MIN64 (736) - XTENSA_INS_AE_MIN64 - ae_min64 $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MINABS32S (737) - XTENSA_INS_AE_MINABS32S - ae_minabs32s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MINABS64S (738) - XTENSA_INS_AE_MINABS64S - ae_minabs64s $ae_cmpp_v, $ae_cmpp_v0, $ae_cmpp_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmpp_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_MOV (739) - XTENSA_INS_AE_MOV - ae_mov $ae_to_dr_v, $ae_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVAD16_0 (740) - XTENSA_INS_AE_MOVAD16_0 - ae_movad16.0 $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVAD16_1 (741) - XTENSA_INS_AE_MOVAD16_1 - ae_movad16.1 $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVAD16_2 (742) - XTENSA_INS_AE_MOVAD16_2 - ae_movad16.2 $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVAD16_3 (743) - XTENSA_INS_AE_MOVAD16_3 - ae_movad16.3 $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVAD32_H (744) - XTENSA_INS_AE_MOVAD32_H - ae_movad32.h $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVAD32_L (745) - XTENSA_INS_AE_MOVAD32_L - ae_movad32.l $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVALIGN (746) - XTENSA_INS_AE_MOVALIGN - ae_movalign $ae_uu_uu, $ae_uu_v */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_uu_uu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_uu_v */ + { 0 } +}}, +{ /* XTENSA_AE_MOVDA16 (747) - XTENSA_INS_AE_MOVDA16 - ae_movda16 $ae_ar_to_dr_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ar_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_MOVDA16X2 (748) - XTENSA_INS_AE_MOVDA16X2 - ae_movda16x2 $ae_ar_to_dr_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ar_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_MOVDA32 (749) - XTENSA_INS_AE_MOVDA32 - ae_movda32 $ae_ar_to_dr_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ar_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_MOVDA32X2 (750) - XTENSA_INS_AE_MOVDA32X2 - ae_movda32x2 $ae_ar_to_dr_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ar_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_MOVF16X4 (751) - XTENSA_INS_AE_MOVF16X4 - ae_movf16x4 $ae_cmov_v, $ae_cmov_v0, $bt4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i1, CS_DATA_TYPE_LAST } }, /* bt4 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVF32X2 (752) - XTENSA_INS_AE_MOVF32X2 - ae_movf32x2 $ae_cmov_v, $ae_cmov_v0, $bt2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* bt2 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVF64 (753) - XTENSA_INS_AE_MOVF64 - ae_movf64 $ae_cmov_v, $ae_cmov_v0, $bt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* bt */ + { 0 } +}}, +{ /* XTENSA_AE_MOVI (754) - XTENSA_INS_AE_MOVI - ae_movi $ae_ar_to_dr_v, $movi_imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ar_to_dr_v */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* movi_imm */ + { 0 } +}}, +{ /* XTENSA_AE_MOVT16X4 (755) - XTENSA_INS_AE_MOVT16X4 - ae_movt16x4 $ae_cmov_v, $ae_cmov_v0, $bt4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i1, CS_DATA_TYPE_LAST } }, /* bt4 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVT32X2 (756) - XTENSA_INS_AE_MOVT32X2 - ae_movt32x2 $ae_cmov_v, $ae_cmov_v0, $bt2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* bt2 */ + { 0 } +}}, +{ /* XTENSA_AE_MOVT64 (757) - XTENSA_INS_AE_MOVT64 - ae_movt64 $ae_cmov_v, $ae_cmov_v0, $bt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_cmov_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* bt */ + { 0 } +}}, +{ /* XTENSA_AE_MUL16X4 (758) - XTENSA_INS_AE_MUL16X4 - ae_mul16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32U_LL (759) - XTENSA_INS_AE_MUL32U_LL - ae_mul32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_H0 (760) - XTENSA_INS_AE_MUL32X16_H0 - ae_mul32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_H0_S2 (761) - XTENSA_INS_AE_MUL32X16_H0_S2 - ae_mul32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_H1 (762) - XTENSA_INS_AE_MUL32X16_H1 - ae_mul32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_H1_S2 (763) - XTENSA_INS_AE_MUL32X16_H1_S2 - ae_mul32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_H2 (764) - XTENSA_INS_AE_MUL32X16_H2 - ae_mul32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_H2_S2 (765) - XTENSA_INS_AE_MUL32X16_H2_S2 - ae_mul32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_H3 (766) - XTENSA_INS_AE_MUL32X16_H3 - ae_mul32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_H3_S2 (767) - XTENSA_INS_AE_MUL32X16_H3_S2 - ae_mul32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_L0 (768) - XTENSA_INS_AE_MUL32X16_L0 - ae_mul32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_L0_S2 (769) - XTENSA_INS_AE_MUL32X16_L0_S2 - ae_mul32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_L1 (770) - XTENSA_INS_AE_MUL32X16_L1 - ae_mul32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_L1_S2 (771) - XTENSA_INS_AE_MUL32X16_L1_S2 - ae_mul32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_L2 (772) - XTENSA_INS_AE_MUL32X16_L2 - ae_mul32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_L2_S2 (773) - XTENSA_INS_AE_MUL32X16_L2_S2 - ae_mul32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_L3 (774) - XTENSA_INS_AE_MUL32X16_L3 - ae_mul32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32X16_L3_S2 (775) - XTENSA_INS_AE_MUL32X16_L3_S2 - ae_mul32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32_HH (776) - XTENSA_INS_AE_MUL32_HH - ae_mul32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32_LH (777) - XTENSA_INS_AE_MUL32_LH - ae_mul32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32_LL (778) - XTENSA_INS_AE_MUL32_LL - ae_mul32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MUL32_LL_S2 (779) - XTENSA_INS_AE_MUL32_LL_S2 - ae_mul32.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA16X4 (780) - XTENSA_INS_AE_MULA16X4 - ae_mula16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32U_LL (781) - XTENSA_INS_AE_MULA32U_LL - ae_mula32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_H0 (782) - XTENSA_INS_AE_MULA32X16_H0 - ae_mula32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_H0_S2 (783) - XTENSA_INS_AE_MULA32X16_H0_S2 - ae_mula32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_H1 (784) - XTENSA_INS_AE_MULA32X16_H1 - ae_mula32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_H1_S2 (785) - XTENSA_INS_AE_MULA32X16_H1_S2 - ae_mula32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_H2 (786) - XTENSA_INS_AE_MULA32X16_H2 - ae_mula32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_H2_S2 (787) - XTENSA_INS_AE_MULA32X16_H2_S2 - ae_mula32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_H3 (788) - XTENSA_INS_AE_MULA32X16_H3 - ae_mula32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_H3_S2 (789) - XTENSA_INS_AE_MULA32X16_H3_S2 - ae_mula32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_L0 (790) - XTENSA_INS_AE_MULA32X16_L0 - ae_mula32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_L0_S2 (791) - XTENSA_INS_AE_MULA32X16_L0_S2 - ae_mula32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_L1 (792) - XTENSA_INS_AE_MULA32X16_L1 - ae_mula32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_L1_S2 (793) - XTENSA_INS_AE_MULA32X16_L1_S2 - ae_mula32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_L2 (794) - XTENSA_INS_AE_MULA32X16_L2 - ae_mula32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_L2_S2 (795) - XTENSA_INS_AE_MULA32X16_L2_S2 - ae_mula32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_L3 (796) - XTENSA_INS_AE_MULA32X16_L3 - ae_mula32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32X16_L3_S2 (797) - XTENSA_INS_AE_MULA32X16_L3_S2 - ae_mula32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32_HH (798) - XTENSA_INS_AE_MULA32_HH - ae_mula32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32_LH (799) - XTENSA_INS_AE_MULA32_LH - ae_mula32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32_LL (800) - XTENSA_INS_AE_MULA32_LL - ae_mula32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULA32_LL_S2 (801) - XTENSA_INS_AE_MULA32_LL_S2 - ae_mula32.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD24_HH_LL (802) - XTENSA_INS_AE_MULAAD24_HH_LL - ae_mulaad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD24_HH_LL_S2 (803) - XTENSA_INS_AE_MULAAD24_HH_LL_S2 - ae_mulaad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD24_HL_LH (804) - XTENSA_INS_AE_MULAAD24_HL_LH - ae_mulaad24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD24_HL_LH_S2 (805) - XTENSA_INS_AE_MULAAD24_HL_LH_S2 - ae_mulaad24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD32X16_H0_L1 (806) - XTENSA_INS_AE_MULAAD32X16_H0_L1 - ae_mulaad32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD32X16_H0_L1_S2 (807) - XTENSA_INS_AE_MULAAD32X16_H0_L1_S2 - ae_mulaad32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD32X16_H1_L0 (808) - XTENSA_INS_AE_MULAAD32X16_H1_L0 - ae_mulaad32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD32X16_H1_L0_S2 (809) - XTENSA_INS_AE_MULAAD32X16_H1_L0_S2 - ae_mulaad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD32X16_H2_L3 (810) - XTENSA_INS_AE_MULAAD32X16_H2_L3 - ae_mulaad32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD32X16_H2_L3_S2 (811) - XTENSA_INS_AE_MULAAD32X16_H2_L3_S2 - ae_mulaad32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD32X16_H3_L2 (812) - XTENSA_INS_AE_MULAAD32X16_H3_L2 - ae_mulaad32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAD32X16_H3_L2_S2 (813) - XTENSA_INS_AE_MULAAD32X16_H3_L2_S2 - ae_mulaad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD16SS_11_00 (814) - XTENSA_INS_AE_MULAAFD16SS_11_00 - ae_mulaafd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD16SS_11_00_S2 (815) - XTENSA_INS_AE_MULAAFD16SS_11_00_S2 - ae_mulaafd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD16SS_13_02 (816) - XTENSA_INS_AE_MULAAFD16SS_13_02 - ae_mulaafd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD16SS_13_02_S2 (817) - XTENSA_INS_AE_MULAAFD16SS_13_02_S2 - ae_mulaafd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD16SS_33_22 (818) - XTENSA_INS_AE_MULAAFD16SS_33_22 - ae_mulaafd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD16SS_33_22_S2 (819) - XTENSA_INS_AE_MULAAFD16SS_33_22_S2 - ae_mulaafd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD24_HH_LL (820) - XTENSA_INS_AE_MULAAFD24_HH_LL - ae_mulaafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD24_HH_LL_S2 (821) - XTENSA_INS_AE_MULAAFD24_HH_LL_S2 - ae_mulaafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD24_HL_LH (822) - XTENSA_INS_AE_MULAAFD24_HL_LH - ae_mulaafd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD24_HL_LH_S2 (823) - XTENSA_INS_AE_MULAAFD24_HL_LH_S2 - ae_mulaafd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD32X16_H0_L1 (824) - XTENSA_INS_AE_MULAAFD32X16_H0_L1 - ae_mulaafd32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD32X16_H0_L1_S2 (825) - XTENSA_INS_AE_MULAAFD32X16_H0_L1_S2 - ae_mulaafd32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD32X16_H1_L0 (826) - XTENSA_INS_AE_MULAAFD32X16_H1_L0 - ae_mulaafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD32X16_H1_L0_S2 (827) - XTENSA_INS_AE_MULAAFD32X16_H1_L0_S2 - ae_mulaafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD32X16_H2_L3 (828) - XTENSA_INS_AE_MULAAFD32X16_H2_L3 - ae_mulaafd32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD32X16_H2_L3_S2 (829) - XTENSA_INS_AE_MULAAFD32X16_H2_L3_S2 - ae_mulaafd32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD32X16_H3_L2 (830) - XTENSA_INS_AE_MULAAFD32X16_H3_L2 - ae_mulaafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAAFD32X16_H3_L2_S2 (831) - XTENSA_INS_AE_MULAAFD32X16_H3_L2_S2 - ae_mulaafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAC24 (832) - XTENSA_INS_AE_MULAC24 - ae_mulac24 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAC32X16_H (833) - XTENSA_INS_AE_MULAC32X16_H - ae_mulac32x16.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAC32X16_L (834) - XTENSA_INS_AE_MULAC32X16_L - ae_mulac32x16.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_00 (835) - XTENSA_INS_AE_MULAF16SS_00 - ae_mulaf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_00_S2 (836) - XTENSA_INS_AE_MULAF16SS_00_S2 - ae_mulaf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_10 (837) - XTENSA_INS_AE_MULAF16SS_10 - ae_mulaf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_11 (838) - XTENSA_INS_AE_MULAF16SS_11 - ae_mulaf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_20 (839) - XTENSA_INS_AE_MULAF16SS_20 - ae_mulaf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_21 (840) - XTENSA_INS_AE_MULAF16SS_21 - ae_mulaf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_22 (841) - XTENSA_INS_AE_MULAF16SS_22 - ae_mulaf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_30 (842) - XTENSA_INS_AE_MULAF16SS_30 - ae_mulaf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_31 (843) - XTENSA_INS_AE_MULAF16SS_31 - ae_mulaf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_32 (844) - XTENSA_INS_AE_MULAF16SS_32 - ae_mulaf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16SS_33 (845) - XTENSA_INS_AE_MULAF16SS_33 - ae_mulaf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF16X4SS (846) - XTENSA_INS_AE_MULAF16X4SS - ae_mulaf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32R_HH (847) - XTENSA_INS_AE_MULAF32R_HH - ae_mulaf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32R_LH (848) - XTENSA_INS_AE_MULAF32R_LH - ae_mulaf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32R_LL (849) - XTENSA_INS_AE_MULAF32R_LL - ae_mulaf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32R_LL_S2 (850) - XTENSA_INS_AE_MULAF32R_LL_S2 - ae_mulaf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32S_HH (851) - XTENSA_INS_AE_MULAF32S_HH - ae_mulaf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32S_LH (852) - XTENSA_INS_AE_MULAF32S_LH - ae_mulaf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32S_LL (853) - XTENSA_INS_AE_MULAF32S_LL - ae_mulaf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32S_LL_S2 (854) - XTENSA_INS_AE_MULAF32S_LL_S2 - ae_mulaf32s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_H0 (855) - XTENSA_INS_AE_MULAF32X16_H0 - ae_mulaf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_H0_S2 (856) - XTENSA_INS_AE_MULAF32X16_H0_S2 - ae_mulaf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_H1 (857) - XTENSA_INS_AE_MULAF32X16_H1 - ae_mulaf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_H1_S2 (858) - XTENSA_INS_AE_MULAF32X16_H1_S2 - ae_mulaf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_H2 (859) - XTENSA_INS_AE_MULAF32X16_H2 - ae_mulaf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_H2_S2 (860) - XTENSA_INS_AE_MULAF32X16_H2_S2 - ae_mulaf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_H3 (861) - XTENSA_INS_AE_MULAF32X16_H3 - ae_mulaf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_H3_S2 (862) - XTENSA_INS_AE_MULAF32X16_H3_S2 - ae_mulaf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_L0 (863) - XTENSA_INS_AE_MULAF32X16_L0 - ae_mulaf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_L0_S2 (864) - XTENSA_INS_AE_MULAF32X16_L0_S2 - ae_mulaf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_L1 (865) - XTENSA_INS_AE_MULAF32X16_L1 - ae_mulaf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_L1_S2 (866) - XTENSA_INS_AE_MULAF32X16_L1_S2 - ae_mulaf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_L2 (867) - XTENSA_INS_AE_MULAF32X16_L2 - ae_mulaf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_L2_S2 (868) - XTENSA_INS_AE_MULAF32X16_L2_S2 - ae_mulaf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_L3 (869) - XTENSA_INS_AE_MULAF32X16_L3 - ae_mulaf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF32X16_L3_S2 (870) - XTENSA_INS_AE_MULAF32X16_L3_S2 - ae_mulaf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF48Q32SP16S_L (871) - XTENSA_INS_AE_MULAF48Q32SP16S_L - ae_mulaf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF48Q32SP16S_L_S2 (872) - XTENSA_INS_AE_MULAF48Q32SP16S_L_S2 - ae_mulaf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF48Q32SP16U_L (873) - XTENSA_INS_AE_MULAF48Q32SP16U_L - ae_mulaf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAF48Q32SP16U_L_S2 (874) - XTENSA_INS_AE_MULAF48Q32SP16U_L_S2 - ae_mulaf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFC24RA (875) - XTENSA_INS_AE_MULAFC24RA - ae_mulafc24ra $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFC32X16RAS_H (876) - XTENSA_INS_AE_MULAFC32X16RAS_H - ae_mulafc32x16ras.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFC32X16RAS_L (877) - XTENSA_INS_AE_MULAFC32X16RAS_L - ae_mulafc32x16ras.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFD24X2_FIR_H (878) - XTENSA_INS_AE_MULAFD24X2_FIR_H - ae_mulafd24x2.fir.h $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFD24X2_FIR_L (879) - XTENSA_INS_AE_MULAFD24X2_FIR_L - ae_mulafd24x2.fir.l $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFD32X16X2_FIR_HH (880) - XTENSA_INS_AE_MULAFD32X16X2_FIR_HH - ae_mulafd32x16x2.fir.hh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFD32X16X2_FIR_HL (881) - XTENSA_INS_AE_MULAFD32X16X2_FIR_HL - ae_mulafd32x16x2.fir.hl $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFD32X16X2_FIR_LH (882) - XTENSA_INS_AE_MULAFD32X16X2_FIR_LH - ae_mulafd32x16x2.fir.lh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFD32X16X2_FIR_LL (883) - XTENSA_INS_AE_MULAFD32X16X2_FIR_LL - ae_mulafd32x16x2.fir.ll $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP24X2R (884) - XTENSA_INS_AE_MULAFP24X2R - ae_mulafp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP24X2RA (885) - XTENSA_INS_AE_MULAFP24X2RA - ae_mulafp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP24X2RA_S2 (886) - XTENSA_INS_AE_MULAFP24X2RA_S2 - ae_mulafp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP24X2R_S2 (887) - XTENSA_INS_AE_MULAFP24X2R_S2 - ae_mulafp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X16X2RAS_H (888) - XTENSA_INS_AE_MULAFP32X16X2RAS_H - ae_mulafp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X16X2RAS_H_S2 (889) - XTENSA_INS_AE_MULAFP32X16X2RAS_H_S2 - ae_mulafp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X16X2RAS_L (890) - XTENSA_INS_AE_MULAFP32X16X2RAS_L - ae_mulafp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X16X2RAS_L_S2 (891) - XTENSA_INS_AE_MULAFP32X16X2RAS_L_S2 - ae_mulafp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X16X2RS_H (892) - XTENSA_INS_AE_MULAFP32X16X2RS_H - ae_mulafp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X16X2RS_H_S2 (893) - XTENSA_INS_AE_MULAFP32X16X2RS_H_S2 - ae_mulafp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X16X2RS_L (894) - XTENSA_INS_AE_MULAFP32X16X2RS_L - ae_mulafp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X16X2RS_L_S2 (895) - XTENSA_INS_AE_MULAFP32X16X2RS_L_S2 - ae_mulafp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X2RAS (896) - XTENSA_INS_AE_MULAFP32X2RAS - ae_mulafp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFP32X2RS (897) - XTENSA_INS_AE_MULAFP32X2RS - ae_mulafp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFQ32SP24S_H_S2 (898) - XTENSA_INS_AE_MULAFQ32SP24S_H_S2 - ae_mulafq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAFQ32SP24S_L_S2 (899) - XTENSA_INS_AE_MULAFQ32SP24S_L_S2 - ae_mulafq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAP24X2 (900) - XTENSA_INS_AE_MULAP24X2 - ae_mulap24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAP24X2_S2 (901) - XTENSA_INS_AE_MULAP24X2_S2 - ae_mulap24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAP32X16X2_H (902) - XTENSA_INS_AE_MULAP32X16X2_H - ae_mulap32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAP32X16X2_L (903) - XTENSA_INS_AE_MULAP32X16X2_L - ae_mulap32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAP32X2 (904) - XTENSA_INS_AE_MULAP32X2 - ae_mulap32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAQ32SP16S_L_S2 (905) - XTENSA_INS_AE_MULAQ32SP16S_L_S2 - ae_mulaq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAQ32SP16U_L_S2 (906) - XTENSA_INS_AE_MULAQ32SP16U_L_S2 - ae_mulaq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULARFQ32SP24S_H_S2 (907) - XTENSA_INS_AE_MULARFQ32SP24S_H_S2 - ae_mularfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULARFQ32SP24S_L_S2 (908) - XTENSA_INS_AE_MULARFQ32SP24S_L_S2 - ae_mularfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAS32F48P16S_HH (909) - XTENSA_INS_AE_MULAS32F48P16S_HH - ae_mulas32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAS32F48P16S_HH_S2 (910) - XTENSA_INS_AE_MULAS32F48P16S_HH_S2 - ae_mulas32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAS32F48P16S_LH (911) - XTENSA_INS_AE_MULAS32F48P16S_LH - ae_mulas32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAS32F48P16S_LH_S2 (912) - XTENSA_INS_AE_MULAS32F48P16S_LH_S2 - ae_mulas32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAS32F48P16S_LL (913) - XTENSA_INS_AE_MULAS32F48P16S_LL - ae_mulas32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULAS32F48P16S_LL_S2 (914) - XTENSA_INS_AE_MULAS32F48P16S_LL_S2 - ae_mulas32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASD24_HH_LL (915) - XTENSA_INS_AE_MULASD24_HH_LL - ae_mulasd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASD24_HH_LL_S2 (916) - XTENSA_INS_AE_MULASD24_HH_LL_S2 - ae_mulasd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASD24_HL_LH (917) - XTENSA_INS_AE_MULASD24_HL_LH - ae_mulasd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASD24_HL_LH_S2 (918) - XTENSA_INS_AE_MULASD24_HL_LH_S2 - ae_mulasd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASD32X16_H1_L0 (919) - XTENSA_INS_AE_MULASD32X16_H1_L0 - ae_mulasd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASD32X16_H1_L0_S2 (920) - XTENSA_INS_AE_MULASD32X16_H1_L0_S2 - ae_mulasd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASD32X16_H3_L2 (921) - XTENSA_INS_AE_MULASD32X16_H3_L2 - ae_mulasd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASD32X16_H3_L2_S2 (922) - XTENSA_INS_AE_MULASD32X16_H3_L2_S2 - ae_mulasd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASFD24_HH_LL (923) - XTENSA_INS_AE_MULASFD24_HH_LL - ae_mulasfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASFD24_HH_LL_S2 (924) - XTENSA_INS_AE_MULASFD24_HH_LL_S2 - ae_mulasfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASFD24_HL_LH (925) - XTENSA_INS_AE_MULASFD24_HL_LH - ae_mulasfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASFD24_HL_LH_S2 (926) - XTENSA_INS_AE_MULASFD24_HL_LH_S2 - ae_mulasfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASFD32X16_H1_L0 (927) - XTENSA_INS_AE_MULASFD32X16_H1_L0 - ae_mulasfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASFD32X16_H1_L0_S2 (928) - XTENSA_INS_AE_MULASFD32X16_H1_L0_S2 - ae_mulasfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASFD32X16_H3_L2 (929) - XTENSA_INS_AE_MULASFD32X16_H3_L2 - ae_mulasfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULASFD32X16_H3_L2_S2 (930) - XTENSA_INS_AE_MULASFD32X16_H3_L2_S2 - ae_mulasfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULC24 (931) - XTENSA_INS_AE_MULC24 - ae_mulc24 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULC32X16_H (932) - XTENSA_INS_AE_MULC32X16_H - ae_mulc32x16.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULC32X16_L (933) - XTENSA_INS_AE_MULC32X16_L - ae_mulc32x16.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_00 (934) - XTENSA_INS_AE_MULF16SS_00 - ae_mulf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_00_S2 (935) - XTENSA_INS_AE_MULF16SS_00_S2 - ae_mulf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_10 (936) - XTENSA_INS_AE_MULF16SS_10 - ae_mulf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_11 (937) - XTENSA_INS_AE_MULF16SS_11 - ae_mulf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_20 (938) - XTENSA_INS_AE_MULF16SS_20 - ae_mulf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_21 (939) - XTENSA_INS_AE_MULF16SS_21 - ae_mulf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_22 (940) - XTENSA_INS_AE_MULF16SS_22 - ae_mulf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_30 (941) - XTENSA_INS_AE_MULF16SS_30 - ae_mulf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_31 (942) - XTENSA_INS_AE_MULF16SS_31 - ae_mulf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_32 (943) - XTENSA_INS_AE_MULF16SS_32 - ae_mulf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16SS_33 (944) - XTENSA_INS_AE_MULF16SS_33 - ae_mulf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF16X4SS (945) - XTENSA_INS_AE_MULF16X4SS - ae_mulf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32R_HH (946) - XTENSA_INS_AE_MULF32R_HH - ae_mulf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32R_LH (947) - XTENSA_INS_AE_MULF32R_LH - ae_mulf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32R_LL (948) - XTENSA_INS_AE_MULF32R_LL - ae_mulf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32R_LL_S2 (949) - XTENSA_INS_AE_MULF32R_LL_S2 - ae_mulf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32S_HH (950) - XTENSA_INS_AE_MULF32S_HH - ae_mulf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32S_LH (951) - XTENSA_INS_AE_MULF32S_LH - ae_mulf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32S_LL (952) - XTENSA_INS_AE_MULF32S_LL - ae_mulf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32S_LL_S2 (953) - XTENSA_INS_AE_MULF32S_LL_S2 - ae_mulf32s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_H0 (954) - XTENSA_INS_AE_MULF32X16_H0 - ae_mulf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_H0_S2 (955) - XTENSA_INS_AE_MULF32X16_H0_S2 - ae_mulf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_H1 (956) - XTENSA_INS_AE_MULF32X16_H1 - ae_mulf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_H1_S2 (957) - XTENSA_INS_AE_MULF32X16_H1_S2 - ae_mulf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_H2 (958) - XTENSA_INS_AE_MULF32X16_H2 - ae_mulf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_H2_S2 (959) - XTENSA_INS_AE_MULF32X16_H2_S2 - ae_mulf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_H3 (960) - XTENSA_INS_AE_MULF32X16_H3 - ae_mulf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_H3_S2 (961) - XTENSA_INS_AE_MULF32X16_H3_S2 - ae_mulf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_L0 (962) - XTENSA_INS_AE_MULF32X16_L0 - ae_mulf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_L0_S2 (963) - XTENSA_INS_AE_MULF32X16_L0_S2 - ae_mulf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_L1 (964) - XTENSA_INS_AE_MULF32X16_L1 - ae_mulf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_L1_S2 (965) - XTENSA_INS_AE_MULF32X16_L1_S2 - ae_mulf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_L2 (966) - XTENSA_INS_AE_MULF32X16_L2 - ae_mulf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_L2_S2 (967) - XTENSA_INS_AE_MULF32X16_L2_S2 - ae_mulf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_L3 (968) - XTENSA_INS_AE_MULF32X16_L3 - ae_mulf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF32X16_L3_S2 (969) - XTENSA_INS_AE_MULF32X16_L3_S2 - ae_mulf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF48Q32SP16S_L (970) - XTENSA_INS_AE_MULF48Q32SP16S_L - ae_mulf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF48Q32SP16S_L_S2 (971) - XTENSA_INS_AE_MULF48Q32SP16S_L_S2 - ae_mulf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF48Q32SP16U_L (972) - XTENSA_INS_AE_MULF48Q32SP16U_L - ae_mulf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULF48Q32SP16U_L_S2 (973) - XTENSA_INS_AE_MULF48Q32SP16U_L_S2 - ae_mulf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFC24RA (974) - XTENSA_INS_AE_MULFC24RA - ae_mulfc24ra $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFC32X16RAS_H (975) - XTENSA_INS_AE_MULFC32X16RAS_H - ae_mulfc32x16ras.h $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFC32X16RAS_L (976) - XTENSA_INS_AE_MULFC32X16RAS_L - ae_mulfc32x16ras.l $opnd_ae_sem_mul_x4_q0, $opnd_ae_sem_mul_x4_d0, $opnd_ae_sem_mul_x4_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x4_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFD24X2_FIR_H (977) - XTENSA_INS_AE_MULFD24X2_FIR_H - ae_mulfd24x2.fir.h $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFD24X2_FIR_L (978) - XTENSA_INS_AE_MULFD24X2_FIR_L - ae_mulfd24x2.fir.l $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFD32X16X2_FIR_HH (979) - XTENSA_INS_AE_MULFD32X16X2_FIR_HH - ae_mulfd32x16x2.fir.hh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFD32X16X2_FIR_HL (980) - XTENSA_INS_AE_MULFD32X16X2_FIR_HL - ae_mulfd32x16x2.fir.hl $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFD32X16X2_FIR_LH (981) - XTENSA_INS_AE_MULFD32X16X2_FIR_LH - ae_mulfd32x16x2.fir.lh $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFD32X16X2_FIR_LL (982) - XTENSA_INS_AE_MULFD32X16X2_FIR_LL - ae_mulfd32x16x2.fir.ll $ae_mul_q0, $ae_mul_q1, $ae_mul_d0, $ae_mul_d1, $ae_mul_d2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d2 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP16X4RAS (983) - XTENSA_INS_AE_MULFP16X4RAS - ae_mulfp16x4ras $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP16X4S (984) - XTENSA_INS_AE_MULFP16X4S - ae_mulfp16x4s $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP24X2R (985) - XTENSA_INS_AE_MULFP24X2R - ae_mulfp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP24X2RA (986) - XTENSA_INS_AE_MULFP24X2RA - ae_mulfp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP24X2RA_S2 (987) - XTENSA_INS_AE_MULFP24X2RA_S2 - ae_mulfp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP24X2R_S2 (988) - XTENSA_INS_AE_MULFP24X2R_S2 - ae_mulfp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X16X2RAS_H (989) - XTENSA_INS_AE_MULFP32X16X2RAS_H - ae_mulfp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X16X2RAS_H_S2 (990) - XTENSA_INS_AE_MULFP32X16X2RAS_H_S2 - ae_mulfp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X16X2RAS_L (991) - XTENSA_INS_AE_MULFP32X16X2RAS_L - ae_mulfp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X16X2RAS_L_S2 (992) - XTENSA_INS_AE_MULFP32X16X2RAS_L_S2 - ae_mulfp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X16X2RS_H (993) - XTENSA_INS_AE_MULFP32X16X2RS_H - ae_mulfp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X16X2RS_H_S2 (994) - XTENSA_INS_AE_MULFP32X16X2RS_H_S2 - ae_mulfp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X16X2RS_L (995) - XTENSA_INS_AE_MULFP32X16X2RS_L - ae_mulfp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X16X2RS_L_S2 (996) - XTENSA_INS_AE_MULFP32X16X2RS_L_S2 - ae_mulfp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X2RAS (997) - XTENSA_INS_AE_MULFP32X2RAS - ae_mulfp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFP32X2RS (998) - XTENSA_INS_AE_MULFP32X2RS - ae_mulfp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFQ32SP24S_H_S2 (999) - XTENSA_INS_AE_MULFQ32SP24S_H_S2 - ae_mulfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULFQ32SP24S_L_S2 (1000) - XTENSA_INS_AE_MULFQ32SP24S_L_S2 - ae_mulfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULP24X2 (1001) - XTENSA_INS_AE_MULP24X2 - ae_mulp24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULP24X2_S2 (1002) - XTENSA_INS_AE_MULP24X2_S2 - ae_mulp24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULP32X16X2_H (1003) - XTENSA_INS_AE_MULP32X16X2_H - ae_mulp32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULP32X16X2_L (1004) - XTENSA_INS_AE_MULP32X16X2_L - ae_mulp32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULP32X2 (1005) - XTENSA_INS_AE_MULP32X2 - ae_mulp32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULQ32SP16S_L_S2 (1006) - XTENSA_INS_AE_MULQ32SP16S_L_S2 - ae_mulq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULQ32SP16U_L_S2 (1007) - XTENSA_INS_AE_MULQ32SP16U_L_S2 - ae_mulq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULRFQ32SP24S_H_S2 (1008) - XTENSA_INS_AE_MULRFQ32SP24S_H_S2 - ae_mulrfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULRFQ32SP24S_L_S2 (1009) - XTENSA_INS_AE_MULRFQ32SP24S_L_S2 - ae_mulrfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS16X4 (1010) - XTENSA_INS_AE_MULS16X4 - ae_muls16x4 $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32F48P16S_HH (1011) - XTENSA_INS_AE_MULS32F48P16S_HH - ae_muls32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32F48P16S_HH_S2 (1012) - XTENSA_INS_AE_MULS32F48P16S_HH_S2 - ae_muls32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32F48P16S_LH (1013) - XTENSA_INS_AE_MULS32F48P16S_LH - ae_muls32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32F48P16S_LH_S2 (1014) - XTENSA_INS_AE_MULS32F48P16S_LH_S2 - ae_muls32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32F48P16S_LL (1015) - XTENSA_INS_AE_MULS32F48P16S_LL - ae_muls32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32F48P16S_LL_S2 (1016) - XTENSA_INS_AE_MULS32F48P16S_LL_S2 - ae_muls32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32U_LL (1017) - XTENSA_INS_AE_MULS32U_LL - ae_muls32u.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_H0 (1018) - XTENSA_INS_AE_MULS32X16_H0 - ae_muls32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_H0_S2 (1019) - XTENSA_INS_AE_MULS32X16_H0_S2 - ae_muls32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_H1 (1020) - XTENSA_INS_AE_MULS32X16_H1 - ae_muls32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_H1_S2 (1021) - XTENSA_INS_AE_MULS32X16_H1_S2 - ae_muls32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_H2 (1022) - XTENSA_INS_AE_MULS32X16_H2 - ae_muls32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_H2_S2 (1023) - XTENSA_INS_AE_MULS32X16_H2_S2 - ae_muls32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_H3 (1024) - XTENSA_INS_AE_MULS32X16_H3 - ae_muls32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_H3_S2 (1025) - XTENSA_INS_AE_MULS32X16_H3_S2 - ae_muls32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_L0 (1026) - XTENSA_INS_AE_MULS32X16_L0 - ae_muls32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_L0_S2 (1027) - XTENSA_INS_AE_MULS32X16_L0_S2 - ae_muls32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_L1 (1028) - XTENSA_INS_AE_MULS32X16_L1 - ae_muls32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_L1_S2 (1029) - XTENSA_INS_AE_MULS32X16_L1_S2 - ae_muls32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_L2 (1030) - XTENSA_INS_AE_MULS32X16_L2 - ae_muls32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_L2_S2 (1031) - XTENSA_INS_AE_MULS32X16_L2_S2 - ae_muls32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_L3 (1032) - XTENSA_INS_AE_MULS32X16_L3 - ae_muls32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32X16_L3_S2 (1033) - XTENSA_INS_AE_MULS32X16_L3_S2 - ae_muls32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32_HH (1034) - XTENSA_INS_AE_MULS32_HH - ae_muls32.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32_LH (1035) - XTENSA_INS_AE_MULS32_LH - ae_muls32.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULS32_LL (1036) - XTENSA_INS_AE_MULS32_LL - ae_muls32.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAD24_HH_LL (1037) - XTENSA_INS_AE_MULSAD24_HH_LL - ae_mulsad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAD24_HH_LL_S2 (1038) - XTENSA_INS_AE_MULSAD24_HH_LL_S2 - ae_mulsad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAD32X16_H1_L0 (1039) - XTENSA_INS_AE_MULSAD32X16_H1_L0 - ae_mulsad32x16.h1.l0 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAD32X16_H1_L0_S2 (1040) - XTENSA_INS_AE_MULSAD32X16_H1_L0_S2 - ae_mulsad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAD32X16_H3_L2 (1041) - XTENSA_INS_AE_MULSAD32X16_H3_L2 - ae_mulsad32x16.h3.l2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAD32X16_H3_L2_S2 (1042) - XTENSA_INS_AE_MULSAD32X16_H3_L2_S2 - ae_mulsad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAFD24_HH_LL (1043) - XTENSA_INS_AE_MULSAFD24_HH_LL - ae_mulsafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAFD24_HH_LL_S2 (1044) - XTENSA_INS_AE_MULSAFD24_HH_LL_S2 - ae_mulsafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAFD32X16_H1_L0 (1045) - XTENSA_INS_AE_MULSAFD32X16_H1_L0 - ae_mulsafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAFD32X16_H1_L0_S2 (1046) - XTENSA_INS_AE_MULSAFD32X16_H1_L0_S2 - ae_mulsafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAFD32X16_H3_L2 (1047) - XTENSA_INS_AE_MULSAFD32X16_H3_L2 - ae_mulsafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSAFD32X16_H3_L2_S2 (1048) - XTENSA_INS_AE_MULSAFD32X16_H3_L2_S2 - ae_mulsafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_00 (1049) - XTENSA_INS_AE_MULSF16SS_00 - ae_mulsf16ss.00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_00_S2 (1050) - XTENSA_INS_AE_MULSF16SS_00_S2 - ae_mulsf16ss.00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_10 (1051) - XTENSA_INS_AE_MULSF16SS_10 - ae_mulsf16ss.10 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_11 (1052) - XTENSA_INS_AE_MULSF16SS_11 - ae_mulsf16ss.11 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_20 (1053) - XTENSA_INS_AE_MULSF16SS_20 - ae_mulsf16ss.20 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_21 (1054) - XTENSA_INS_AE_MULSF16SS_21 - ae_mulsf16ss.21 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_22 (1055) - XTENSA_INS_AE_MULSF16SS_22 - ae_mulsf16ss.22 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_30 (1056) - XTENSA_INS_AE_MULSF16SS_30 - ae_mulsf16ss.30 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_31 (1057) - XTENSA_INS_AE_MULSF16SS_31 - ae_mulsf16ss.31 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_32 (1058) - XTENSA_INS_AE_MULSF16SS_32 - ae_mulsf16ss.32 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16SS_33 (1059) - XTENSA_INS_AE_MULSF16SS_33 - ae_mulsf16ss.33 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF16X4SS (1060) - XTENSA_INS_AE_MULSF16X4SS - ae_mulsf16x4ss $ae_mul_q1, $ae_mul_q0, $ae_mul_d1, $ae_mul_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32R_HH (1061) - XTENSA_INS_AE_MULSF32R_HH - ae_mulsf32r.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32R_LH (1062) - XTENSA_INS_AE_MULSF32R_LH - ae_mulsf32r.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32R_LL (1063) - XTENSA_INS_AE_MULSF32R_LL - ae_mulsf32r.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32R_LL_S2 (1064) - XTENSA_INS_AE_MULSF32R_LL_S2 - ae_mulsf32r.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32S_HH (1065) - XTENSA_INS_AE_MULSF32S_HH - ae_mulsf32s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32S_LH (1066) - XTENSA_INS_AE_MULSF32S_LH - ae_mulsf32s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32S_LL (1067) - XTENSA_INS_AE_MULSF32S_LL - ae_mulsf32s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_H0 (1068) - XTENSA_INS_AE_MULSF32X16_H0 - ae_mulsf32x16.h0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_H0_S2 (1069) - XTENSA_INS_AE_MULSF32X16_H0_S2 - ae_mulsf32x16.h0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_H1 (1070) - XTENSA_INS_AE_MULSF32X16_H1 - ae_mulsf32x16.h1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_H1_S2 (1071) - XTENSA_INS_AE_MULSF32X16_H1_S2 - ae_mulsf32x16.h1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_H2 (1072) - XTENSA_INS_AE_MULSF32X16_H2 - ae_mulsf32x16.h2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_H2_S2 (1073) - XTENSA_INS_AE_MULSF32X16_H2_S2 - ae_mulsf32x16.h2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_H3 (1074) - XTENSA_INS_AE_MULSF32X16_H3 - ae_mulsf32x16.h3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_H3_S2 (1075) - XTENSA_INS_AE_MULSF32X16_H3_S2 - ae_mulsf32x16.h3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_L0 (1076) - XTENSA_INS_AE_MULSF32X16_L0 - ae_mulsf32x16.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_L0_S2 (1077) - XTENSA_INS_AE_MULSF32X16_L0_S2 - ae_mulsf32x16.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_L1 (1078) - XTENSA_INS_AE_MULSF32X16_L1 - ae_mulsf32x16.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_L1_S2 (1079) - XTENSA_INS_AE_MULSF32X16_L1_S2 - ae_mulsf32x16.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_L2 (1080) - XTENSA_INS_AE_MULSF32X16_L2 - ae_mulsf32x16.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_L2_S2 (1081) - XTENSA_INS_AE_MULSF32X16_L2_S2 - ae_mulsf32x16.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_L3 (1082) - XTENSA_INS_AE_MULSF32X16_L3 - ae_mulsf32x16.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF32X16_L3_S2 (1083) - XTENSA_INS_AE_MULSF32X16_L3_S2 - ae_mulsf32x16.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF48Q32SP16S_L (1084) - XTENSA_INS_AE_MULSF48Q32SP16S_L - ae_mulsf48q32sp16s.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF48Q32SP16S_L_S2 (1085) - XTENSA_INS_AE_MULSF48Q32SP16S_L_S2 - ae_mulsf48q32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF48Q32SP16U_L (1086) - XTENSA_INS_AE_MULSF48Q32SP16U_L - ae_mulsf48q32sp16u.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSF48Q32SP16U_L_S2 (1087) - XTENSA_INS_AE_MULSF48Q32SP16U_L_S2 - ae_mulsf48q32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP24X2R (1088) - XTENSA_INS_AE_MULSFP24X2R - ae_mulsfp24x2r $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP24X2RA (1089) - XTENSA_INS_AE_MULSFP24X2RA - ae_mulsfp24x2ra $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP24X2RA_S2 (1090) - XTENSA_INS_AE_MULSFP24X2RA_S2 - ae_mulsfp24x2ra_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP24X2R_S2 (1091) - XTENSA_INS_AE_MULSFP24X2R_S2 - ae_mulsfp24x2r_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X16X2RAS_H (1092) - XTENSA_INS_AE_MULSFP32X16X2RAS_H - ae_mulsfp32x16x2ras.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X16X2RAS_H_S2 (1093) - XTENSA_INS_AE_MULSFP32X16X2RAS_H_S2 - ae_mulsfp32x16x2ras.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X16X2RAS_L (1094) - XTENSA_INS_AE_MULSFP32X16X2RAS_L - ae_mulsfp32x16x2ras.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X16X2RAS_L_S2 (1095) - XTENSA_INS_AE_MULSFP32X16X2RAS_L_S2 - ae_mulsfp32x16x2ras.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X16X2RS_H (1096) - XTENSA_INS_AE_MULSFP32X16X2RS_H - ae_mulsfp32x16x2rs.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X16X2RS_H_S2 (1097) - XTENSA_INS_AE_MULSFP32X16X2RS_H_S2 - ae_mulsfp32x16x2rs.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X16X2RS_L (1098) - XTENSA_INS_AE_MULSFP32X16X2RS_L - ae_mulsfp32x16x2rs.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X16X2RS_L_S2 (1099) - XTENSA_INS_AE_MULSFP32X16X2RS_L_S2 - ae_mulsfp32x16x2rs.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X2RAS (1100) - XTENSA_INS_AE_MULSFP32X2RAS - ae_mulsfp32x2ras $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFP32X2RS (1101) - XTENSA_INS_AE_MULSFP32X2RS - ae_mulsfp32x2rs $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFQ32SP24S_H_S2 (1102) - XTENSA_INS_AE_MULSFQ32SP24S_H_S2 - ae_mulsfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSFQ32SP24S_L_S2 (1103) - XTENSA_INS_AE_MULSFQ32SP24S_L_S2 - ae_mulsfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSP24X2 (1104) - XTENSA_INS_AE_MULSP24X2 - ae_mulsp24x2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSP24X2_S2 (1105) - XTENSA_INS_AE_MULSP24X2_S2 - ae_mulsp24x2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSP32X16X2_H (1106) - XTENSA_INS_AE_MULSP32X16X2_H - ae_mulsp32x16x2.h $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSP32X16X2_L (1107) - XTENSA_INS_AE_MULSP32X16X2_L - ae_mulsp32x16x2.l $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSP32X2 (1108) - XTENSA_INS_AE_MULSP32X2 - ae_mulsp32x2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSQ32SP16S_L_S2 (1109) - XTENSA_INS_AE_MULSQ32SP16S_L_S2 - ae_mulsq32sp16s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSQ32SP16U_L_S2 (1110) - XTENSA_INS_AE_MULSQ32SP16U_L_S2 - ae_mulsq32sp16u.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSRFQ32SP24S_H_S2 (1111) - XTENSA_INS_AE_MULSRFQ32SP24S_H_S2 - ae_mulsrfq32sp24s.h_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSRFQ32SP24S_L_S2 (1112) - XTENSA_INS_AE_MULSRFQ32SP24S_L_S2 - ae_mulsrfq32sp24s.l_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSS32F48P16S_HH (1113) - XTENSA_INS_AE_MULSS32F48P16S_HH - ae_mulss32f48p16s.hh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSS32F48P16S_HH_S2 (1114) - XTENSA_INS_AE_MULSS32F48P16S_HH_S2 - ae_mulss32f48p16s.hh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSS32F48P16S_LH (1115) - XTENSA_INS_AE_MULSS32F48P16S_LH - ae_mulss32f48p16s.lh $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSS32F48P16S_LH_S2 (1116) - XTENSA_INS_AE_MULSS32F48P16S_LH_S2 - ae_mulss32f48p16s.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSS32F48P16S_LL (1117) - XTENSA_INS_AE_MULSS32F48P16S_LL - ae_mulss32f48p16s.ll $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSS32F48P16S_LL_S2 (1118) - XTENSA_INS_AE_MULSS32F48P16S_LL_S2 - ae_mulss32f48p16s.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSD24_HH_LL (1119) - XTENSA_INS_AE_MULSSD24_HH_LL - ae_mulssd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSD24_HH_LL_S2 (1120) - XTENSA_INS_AE_MULSSD24_HH_LL_S2 - ae_mulssd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSD24_HL_LH (1121) - XTENSA_INS_AE_MULSSD24_HL_LH - ae_mulssd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSD24_HL_LH_S2 (1122) - XTENSA_INS_AE_MULSSD24_HL_LH_S2 - ae_mulssd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSD32X16_H1_L0 (1123) - XTENSA_INS_AE_MULSSD32X16_H1_L0 - ae_mulssd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSD32X16_H1_L0_S2 (1124) - XTENSA_INS_AE_MULSSD32X16_H1_L0_S2 - ae_mulssd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSD32X16_H3_L2 (1125) - XTENSA_INS_AE_MULSSD32X16_H3_L2 - ae_mulssd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSD32X16_H3_L2_S2 (1126) - XTENSA_INS_AE_MULSSD32X16_H3_L2_S2 - ae_mulssd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD16SS_11_00 (1127) - XTENSA_INS_AE_MULSSFD16SS_11_00 - ae_mulssfd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD16SS_11_00_S2 (1128) - XTENSA_INS_AE_MULSSFD16SS_11_00_S2 - ae_mulssfd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD16SS_13_02 (1129) - XTENSA_INS_AE_MULSSFD16SS_13_02 - ae_mulssfd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD16SS_13_02_S2 (1130) - XTENSA_INS_AE_MULSSFD16SS_13_02_S2 - ae_mulssfd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD16SS_33_22 (1131) - XTENSA_INS_AE_MULSSFD16SS_33_22 - ae_mulssfd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD16SS_33_22_S2 (1132) - XTENSA_INS_AE_MULSSFD16SS_33_22_S2 - ae_mulssfd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD24_HH_LL (1133) - XTENSA_INS_AE_MULSSFD24_HH_LL - ae_mulssfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD24_HH_LL_S2 (1134) - XTENSA_INS_AE_MULSSFD24_HH_LL_S2 - ae_mulssfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD24_HL_LH (1135) - XTENSA_INS_AE_MULSSFD24_HL_LH - ae_mulssfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD24_HL_LH_S2 (1136) - XTENSA_INS_AE_MULSSFD24_HL_LH_S2 - ae_mulssfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD32X16_H1_L0 (1137) - XTENSA_INS_AE_MULSSFD32X16_H1_L0 - ae_mulssfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD32X16_H1_L0_S2 (1138) - XTENSA_INS_AE_MULSSFD32X16_H1_L0_S2 - ae_mulssfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD32X16_H3_L2 (1139) - XTENSA_INS_AE_MULSSFD32X16_H3_L2 - ae_mulssfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULSSFD32X16_H3_L2_S2 (1140) - XTENSA_INS_AE_MULSSFD32X16_H3_L2_S2 - ae_mulssfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD24_HH_LL (1141) - XTENSA_INS_AE_MULZAAD24_HH_LL - ae_mulzaad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD24_HH_LL_S2 (1142) - XTENSA_INS_AE_MULZAAD24_HH_LL_S2 - ae_mulzaad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD24_HL_LH (1143) - XTENSA_INS_AE_MULZAAD24_HL_LH - ae_mulzaad24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD24_HL_LH_S2 (1144) - XTENSA_INS_AE_MULZAAD24_HL_LH_S2 - ae_mulzaad24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD32X16_H0_L1 (1145) - XTENSA_INS_AE_MULZAAD32X16_H0_L1 - ae_mulzaad32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD32X16_H0_L1_S2 (1146) - XTENSA_INS_AE_MULZAAD32X16_H0_L1_S2 - ae_mulzaad32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD32X16_H1_L0 (1147) - XTENSA_INS_AE_MULZAAD32X16_H1_L0 - ae_mulzaad32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD32X16_H1_L0_S2 (1148) - XTENSA_INS_AE_MULZAAD32X16_H1_L0_S2 - ae_mulzaad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD32X16_H2_L3 (1149) - XTENSA_INS_AE_MULZAAD32X16_H2_L3 - ae_mulzaad32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD32X16_H2_L3_S2 (1150) - XTENSA_INS_AE_MULZAAD32X16_H2_L3_S2 - ae_mulzaad32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD32X16_H3_L2 (1151) - XTENSA_INS_AE_MULZAAD32X16_H3_L2 - ae_mulzaad32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAD32X16_H3_L2_S2 (1152) - XTENSA_INS_AE_MULZAAD32X16_H3_L2_S2 - ae_mulzaad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD16SS_11_00 (1153) - XTENSA_INS_AE_MULZAAFD16SS_11_00 - ae_mulzaafd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD16SS_11_00_S2 (1154) - XTENSA_INS_AE_MULZAAFD16SS_11_00_S2 - ae_mulzaafd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD16SS_13_02 (1155) - XTENSA_INS_AE_MULZAAFD16SS_13_02 - ae_mulzaafd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD16SS_13_02_S2 (1156) - XTENSA_INS_AE_MULZAAFD16SS_13_02_S2 - ae_mulzaafd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD16SS_33_22 (1157) - XTENSA_INS_AE_MULZAAFD16SS_33_22 - ae_mulzaafd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD16SS_33_22_S2 (1158) - XTENSA_INS_AE_MULZAAFD16SS_33_22_S2 - ae_mulzaafd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD24_HH_LL (1159) - XTENSA_INS_AE_MULZAAFD24_HH_LL - ae_mulzaafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD24_HH_LL_S2 (1160) - XTENSA_INS_AE_MULZAAFD24_HH_LL_S2 - ae_mulzaafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD24_HL_LH (1161) - XTENSA_INS_AE_MULZAAFD24_HL_LH - ae_mulzaafd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD24_HL_LH_S2 (1162) - XTENSA_INS_AE_MULZAAFD24_HL_LH_S2 - ae_mulzaafd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD32X16_H0_L1 (1163) - XTENSA_INS_AE_MULZAAFD32X16_H0_L1 - ae_mulzaafd32x16.h0.l1 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD32X16_H0_L1_S2 (1164) - XTENSA_INS_AE_MULZAAFD32X16_H0_L1_S2 - ae_mulzaafd32x16.h0.l1_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD32X16_H1_L0 (1165) - XTENSA_INS_AE_MULZAAFD32X16_H1_L0 - ae_mulzaafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD32X16_H1_L0_S2 (1166) - XTENSA_INS_AE_MULZAAFD32X16_H1_L0_S2 - ae_mulzaafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD32X16_H2_L3 (1167) - XTENSA_INS_AE_MULZAAFD32X16_H2_L3 - ae_mulzaafd32x16.h2.l3 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD32X16_H2_L3_S2 (1168) - XTENSA_INS_AE_MULZAAFD32X16_H2_L3_S2 - ae_mulzaafd32x16.h2.l3_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD32X16_H3_L2 (1169) - XTENSA_INS_AE_MULZAAFD32X16_H3_L2 - ae_mulzaafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZAAFD32X16_H3_L2_S2 (1170) - XTENSA_INS_AE_MULZAAFD32X16_H3_L2_S2 - ae_mulzaafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASD24_HH_LL (1171) - XTENSA_INS_AE_MULZASD24_HH_LL - ae_mulzasd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASD24_HH_LL_S2 (1172) - XTENSA_INS_AE_MULZASD24_HH_LL_S2 - ae_mulzasd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASD24_HL_LH (1173) - XTENSA_INS_AE_MULZASD24_HL_LH - ae_mulzasd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASD24_HL_LH_S2 (1174) - XTENSA_INS_AE_MULZASD24_HL_LH_S2 - ae_mulzasd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASD32X16_H1_L0 (1175) - XTENSA_INS_AE_MULZASD32X16_H1_L0 - ae_mulzasd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASD32X16_H1_L0_S2 (1176) - XTENSA_INS_AE_MULZASD32X16_H1_L0_S2 - ae_mulzasd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASD32X16_H3_L2 (1177) - XTENSA_INS_AE_MULZASD32X16_H3_L2 - ae_mulzasd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASD32X16_H3_L2_S2 (1178) - XTENSA_INS_AE_MULZASD32X16_H3_L2_S2 - ae_mulzasd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASFD24_HH_LL (1179) - XTENSA_INS_AE_MULZASFD24_HH_LL - ae_mulzasfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASFD24_HH_LL_S2 (1180) - XTENSA_INS_AE_MULZASFD24_HH_LL_S2 - ae_mulzasfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASFD24_HL_LH (1181) - XTENSA_INS_AE_MULZASFD24_HL_LH - ae_mulzasfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASFD24_HL_LH_S2 (1182) - XTENSA_INS_AE_MULZASFD24_HL_LH_S2 - ae_mulzasfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASFD32X16_H1_L0 (1183) - XTENSA_INS_AE_MULZASFD32X16_H1_L0 - ae_mulzasfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASFD32X16_H1_L0_S2 (1184) - XTENSA_INS_AE_MULZASFD32X16_H1_L0_S2 - ae_mulzasfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASFD32X16_H3_L2 (1185) - XTENSA_INS_AE_MULZASFD32X16_H3_L2 - ae_mulzasfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZASFD32X16_H3_L2_S2 (1186) - XTENSA_INS_AE_MULZASFD32X16_H3_L2_S2 - ae_mulzasfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAD24_HH_LL (1187) - XTENSA_INS_AE_MULZSAD24_HH_LL - ae_mulzsad24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAD24_HH_LL_S2 (1188) - XTENSA_INS_AE_MULZSAD24_HH_LL_S2 - ae_mulzsad24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAD32X16_H1_L0 (1189) - XTENSA_INS_AE_MULZSAD32X16_H1_L0 - ae_mulzsad32x16.h1.l0 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAD32X16_H1_L0_S2 (1190) - XTENSA_INS_AE_MULZSAD32X16_H1_L0_S2 - ae_mulzsad32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAD32X16_H3_L2 (1191) - XTENSA_INS_AE_MULZSAD32X16_H3_L2 - ae_mulzsad32x16.h3.l2 $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAD32X16_H3_L2_S2 (1192) - XTENSA_INS_AE_MULZSAD32X16_H3_L2_S2 - ae_mulzsad32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAFD24_HH_LL (1193) - XTENSA_INS_AE_MULZSAFD24_HH_LL - ae_mulzsafd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAFD24_HH_LL_S2 (1194) - XTENSA_INS_AE_MULZSAFD24_HH_LL_S2 - ae_mulzsafd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAFD32X16_H1_L0 (1195) - XTENSA_INS_AE_MULZSAFD32X16_H1_L0 - ae_mulzsafd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAFD32X16_H1_L0_S2 (1196) - XTENSA_INS_AE_MULZSAFD32X16_H1_L0_S2 - ae_mulzsafd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAFD32X16_H3_L2 (1197) - XTENSA_INS_AE_MULZSAFD32X16_H3_L2 - ae_mulzsafd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSAFD32X16_H3_L2_S2 (1198) - XTENSA_INS_AE_MULZSAFD32X16_H3_L2_S2 - ae_mulzsafd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSD24_HH_LL (1199) - XTENSA_INS_AE_MULZSSD24_HH_LL - ae_mulzssd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSD24_HH_LL_S2 (1200) - XTENSA_INS_AE_MULZSSD24_HH_LL_S2 - ae_mulzssd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSD24_HL_LH (1201) - XTENSA_INS_AE_MULZSSD24_HL_LH - ae_mulzssd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSD24_HL_LH_S2 (1202) - XTENSA_INS_AE_MULZSSD24_HL_LH_S2 - ae_mulzssd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSD32X16_H1_L0 (1203) - XTENSA_INS_AE_MULZSSD32X16_H1_L0 - ae_mulzssd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSD32X16_H1_L0_S2 (1204) - XTENSA_INS_AE_MULZSSD32X16_H1_L0_S2 - ae_mulzssd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSD32X16_H3_L2 (1205) - XTENSA_INS_AE_MULZSSD32X16_H3_L2 - ae_mulzssd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSD32X16_H3_L2_S2 (1206) - XTENSA_INS_AE_MULZSSD32X16_H3_L2_S2 - ae_mulzssd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD16SS_11_00 (1207) - XTENSA_INS_AE_MULZSSFD16SS_11_00 - ae_mulzssfd16ss.11_00 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD16SS_11_00_S2 (1208) - XTENSA_INS_AE_MULZSSFD16SS_11_00_S2 - ae_mulzssfd16ss.11_00_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD16SS_13_02 (1209) - XTENSA_INS_AE_MULZSSFD16SS_13_02 - ae_mulzssfd16ss.13_02 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD16SS_13_02_S2 (1210) - XTENSA_INS_AE_MULZSSFD16SS_13_02_S2 - ae_mulzssfd16ss.13_02_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD16SS_33_22 (1211) - XTENSA_INS_AE_MULZSSFD16SS_33_22 - ae_mulzssfd16ss.33_22 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD16SS_33_22_S2 (1212) - XTENSA_INS_AE_MULZSSFD16SS_33_22_S2 - ae_mulzssfd16ss.33_22_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD24_HH_LL (1213) - XTENSA_INS_AE_MULZSSFD24_HH_LL - ae_mulzssfd24.hh.ll $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD24_HH_LL_S2 (1214) - XTENSA_INS_AE_MULZSSFD24_HH_LL_S2 - ae_mulzssfd24.hh.ll_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD24_HL_LH (1215) - XTENSA_INS_AE_MULZSSFD24_HL_LH - ae_mulzssfd24.hl.lh $ae_mul_q0, $ae_mul_d0, $ae_mul_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD24_HL_LH_S2 (1216) - XTENSA_INS_AE_MULZSSFD24_HL_LH_S2 - ae_mulzssfd24.hl.lh_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD32X16_H1_L0 (1217) - XTENSA_INS_AE_MULZSSFD32X16_H1_L0 - ae_mulzssfd32x16.h1.l0 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD32X16_H1_L0_S2 (1218) - XTENSA_INS_AE_MULZSSFD32X16_H1_L0_S2 - ae_mulzssfd32x16.h1.l0_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD32X16_H3_L2 (1219) - XTENSA_INS_AE_MULZSSFD32X16_H3_L2 - ae_mulzssfd32x16.h3.l2 $opnd_ae_sem_mul_x2_S1_q0, $opnd_ae_sem_mul_x2_S1_d0, $opnd_ae_sem_mul_x2_S1_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* opnd_ae_sem_mul_x2_S1_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_MULZSSFD32X16_H3_L2_S2 (1220) - XTENSA_INS_AE_MULZSSFD32X16_H3_L2_S2 - ae_mulzssfd32x16.h3.l2_s2 $ae_mul_S2_q0, $ae_mul_S2_d0, $ae_mul_S2_d1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_q0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_mul_S2_d1 */ + { 0 } +}}, +{ /* XTENSA_AE_NAND (1221) - XTENSA_INS_AE_NAND - ae_nand $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_NEG16S (1222) - XTENSA_INS_AE_NEG16S - ae_neg16s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_NEG24S (1223) - XTENSA_INS_AE_NEG24S - ae_neg24s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_NEG32 (1224) - XTENSA_INS_AE_NEG32 - ae_neg32 $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_NEG32S (1225) - XTENSA_INS_AE_NEG32S - ae_neg32s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_NEG64 (1226) - XTENSA_INS_AE_NEG64 - ae_neg64 $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_NEG64S (1227) - XTENSA_INS_AE_NEG64S - ae_neg64s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_NSA64 (1228) - XTENSA_INS_AE_NSA64 - ae_nsa64 $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_NSAZ16_0 (1229) - XTENSA_INS_AE_NSAZ16_0 - ae_nsaz16.0 $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_NSAZ32_L (1230) - XTENSA_INS_AE_NSAZ32_L - ae_nsaz32.l $arr, $ae_dr_to_ar_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_ar_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_OR (1231) - XTENSA_INS_AE_OR - ae_or $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_PKSR24 (1232) - XTENSA_INS_AE_PKSR24 - ae_pksr24 $ae_pks_d, $ae_pks_s, $ae_imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_pks_d_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_pks_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_pks_s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_imm2 */ + { 0 } +}}, +{ /* XTENSA_AE_PKSR32 (1233) - XTENSA_INS_AE_PKSR32 - ae_pksr32 $ae_pks_d, $ae_pks_s, $ae_imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_pks_d_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_pks_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_pks_s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_imm2 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUND16X4F32SASYM (1234) - XTENSA_INS_AE_ROUND16X4F32SASYM - ae_round16x4f32sasym $ae_arth_v, $ae_arth_v1, $ae_arth_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUND16X4F32SSYM (1235) - XTENSA_INS_AE_ROUND16X4F32SSYM - ae_round16x4f32ssym $ae_arth_v, $ae_arth_v1, $ae_arth_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUND24X2F48SASYM (1236) - XTENSA_INS_AE_ROUND24X2F48SASYM - ae_round24x2f48sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUND24X2F48SSYM (1237) - XTENSA_INS_AE_ROUND24X2F48SSYM - ae_round24x2f48ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUND32X2F48SASYM (1238) - XTENSA_INS_AE_ROUND32X2F48SASYM - ae_round32x2f48sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUND32X2F48SSYM (1239) - XTENSA_INS_AE_ROUND32X2F48SSYM - ae_round32x2f48ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUND32X2F64SASYM (1240) - XTENSA_INS_AE_ROUND32X2F64SASYM - ae_round32x2f64sasym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUND32X2F64SSYM (1241) - XTENSA_INS_AE_ROUND32X2F64SSYM - ae_round32x2f64ssym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUNDSP16F24ASYM (1242) - XTENSA_INS_AE_ROUNDSP16F24ASYM - ae_roundsp16f24asym $ae_arth_v, $ae_arth_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUNDSP16F24SYM (1243) - XTENSA_INS_AE_ROUNDSP16F24SYM - ae_roundsp16f24sym $ae_arth_v, $ae_arth_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUNDSP16Q48X2ASYM (1244) - XTENSA_INS_AE_ROUNDSP16Q48X2ASYM - ae_roundsp16q48x2asym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUNDSP16Q48X2SYM (1245) - XTENSA_INS_AE_ROUNDSP16Q48X2SYM - ae_roundsp16q48x2sym $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUNDSQ32F48ASYM (1246) - XTENSA_INS_AE_ROUNDSQ32F48ASYM - ae_roundsq32f48asym $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ROUNDSQ32F48SYM (1247) - XTENSA_INS_AE_ROUNDSQ32F48SYM - ae_roundsq32f48sym $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_S16M_L_I (1248) - XTENSA_INS_AE_S16M_L_I - ae_s16m.l.i $ae_ls_v, $ars, $ae_immls16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls16 */ + { 0 } +}}, +{ /* XTENSA_AE_S16M_L_IU (1249) - XTENSA_INS_AE_S16M_L_IU - ae_s16m.l.iu $ae_ls_v, $ars, $ae_immls16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls16 */ + { 0 } +}}, +{ /* XTENSA_AE_S16M_L_X (1250) - XTENSA_INS_AE_S16M_L_X - ae_s16m.l.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16M_L_XC (1251) - XTENSA_INS_AE_S16M_L_XC - ae_s16m.l.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16M_L_XU (1252) - XTENSA_INS_AE_S16M_L_XU - ae_s16m.l.xu $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16X2M_I (1253) - XTENSA_INS_AE_S16X2M_I - ae_s16x2m.i $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S16X2M_IU (1254) - XTENSA_INS_AE_S16X2M_IU - ae_s16x2m.iu $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S16X2M_X (1255) - XTENSA_INS_AE_S16X2M_X - ae_s16x2m.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16X2M_XC (1256) - XTENSA_INS_AE_S16X2M_XC - ae_s16x2m.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16X2M_XU (1257) - XTENSA_INS_AE_S16X2M_XU - ae_s16x2m.xu $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16X4_I (1258) - XTENSA_INS_AE_S16X4_I - ae_s16x4.i $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_S16X4_IP (1259) - XTENSA_INS_AE_S16X4_IP - ae_s16x4.ip $ae_ls_v, $ars, $ae_immls64pos */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64pos */ + { 0 } +}}, +{ /* XTENSA_AE_S16X4_RIC (1260) - XTENSA_INS_AE_S16X4_RIC - ae_s16x4.ric $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_S16X4_RIP (1261) - XTENSA_INS_AE_S16X4_RIP - ae_s16x4.rip $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_S16X4_X (1262) - XTENSA_INS_AE_S16X4_X - ae_s16x4.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16X4_XC (1263) - XTENSA_INS_AE_S16X4_XC - ae_s16x4.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16X4_XP (1264) - XTENSA_INS_AE_S16X4_XP - ae_s16x4.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16_0_I (1265) - XTENSA_INS_AE_S16_0_I - ae_s16.0.i $ae_ls_v, $ars, $ae_immls16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls16 */ + { 0 } +}}, +{ /* XTENSA_AE_S16_0_IP (1266) - XTENSA_INS_AE_S16_0_IP - ae_s16.0.ip $ae_ls_v, $ars, $ae_immls16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls16 */ + { 0 } +}}, +{ /* XTENSA_AE_S16_0_X (1267) - XTENSA_INS_AE_S16_0_X - ae_s16.0.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16_0_XC (1268) - XTENSA_INS_AE_S16_0_XC - ae_s16.0.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S16_0_XP (1269) - XTENSA_INS_AE_S16_0_XP - ae_s16.0.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S24RA64S_I (1270) - XTENSA_INS_AE_S24RA64S_I - ae_s24ra64s.i $ae_ls_v1, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S24RA64S_IP (1271) - XTENSA_INS_AE_S24RA64S_IP - ae_s24ra64s.ip $ae_ls_v1, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S24RA64S_X (1272) - XTENSA_INS_AE_S24RA64S_X - ae_s24ra64s.x $ae_ls_v1, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S24RA64S_XC (1273) - XTENSA_INS_AE_S24RA64S_XC - ae_s24ra64s.xc $ae_ls_v1, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S24RA64S_XP (1274) - XTENSA_INS_AE_S24RA64S_XP - ae_s24ra64s.xp $ae_ls_v1, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S24X2RA64S_IP (1275) - XTENSA_INS_AE_S24X2RA64S_IP - ae_s24x2ra64s.ip $ae_ls_v2, $ae_ls_v1, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_S32F24_L_I (1276) - XTENSA_INS_AE_S32F24_L_I - ae_s32f24.l.i $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S32F24_L_IP (1277) - XTENSA_INS_AE_S32F24_L_IP - ae_s32f24.l.ip $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S32F24_L_X (1278) - XTENSA_INS_AE_S32F24_L_X - ae_s32f24.l.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32F24_L_XC (1279) - XTENSA_INS_AE_S32F24_L_XC - ae_s32f24.l.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32F24_L_XP (1280) - XTENSA_INS_AE_S32F24_L_XP - ae_s32f24.l.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32M_I (1281) - XTENSA_INS_AE_S32M_I - ae_s32m.i $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S32M_IU (1282) - XTENSA_INS_AE_S32M_IU - ae_s32m.iu $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S32M_X (1283) - XTENSA_INS_AE_S32M_X - ae_s32m.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32M_XC (1284) - XTENSA_INS_AE_S32M_XC - ae_s32m.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32M_XU (1285) - XTENSA_INS_AE_S32M_XU - ae_s32m.xu $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32RA64S_I (1286) - XTENSA_INS_AE_S32RA64S_I - ae_s32ra64s.i $ae_ls_v1, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S32RA64S_IP (1287) - XTENSA_INS_AE_S32RA64S_IP - ae_s32ra64s.ip $ae_ls_v1, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S32RA64S_X (1288) - XTENSA_INS_AE_S32RA64S_X - ae_s32ra64s.x $ae_ls_v1, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32RA64S_XC (1289) - XTENSA_INS_AE_S32RA64S_XC - ae_s32ra64s.xc $ae_ls_v1, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32RA64S_XP (1290) - XTENSA_INS_AE_S32RA64S_XP - ae_s32ra64s.xp $ae_ls_v1, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2F24_I (1291) - XTENSA_INS_AE_S32X2F24_I - ae_s32x2f24.i $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2F24_IP (1292) - XTENSA_INS_AE_S32X2F24_IP - ae_s32x2f24.ip $ae_ls_v, $ars, $ae_immls64pos */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64pos */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2F24_RIC (1293) - XTENSA_INS_AE_S32X2F24_RIC - ae_s32x2f24.ric $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2F24_RIP (1294) - XTENSA_INS_AE_S32X2F24_RIP - ae_s32x2f24.rip $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2F24_X (1295) - XTENSA_INS_AE_S32X2F24_X - ae_s32x2f24.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2F24_XC (1296) - XTENSA_INS_AE_S32X2F24_XC - ae_s32x2f24.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2F24_XP (1297) - XTENSA_INS_AE_S32X2F24_XP - ae_s32x2f24.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2RA64S_IP (1298) - XTENSA_INS_AE_S32X2RA64S_IP - ae_s32x2ra64s.ip $ae_ls_v2, $ae_ls_v1, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2_I (1299) - XTENSA_INS_AE_S32X2_I - ae_s32x2.i $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2_IP (1300) - XTENSA_INS_AE_S32X2_IP - ae_s32x2.ip $ae_ls_v, $ars, $ae_immls64pos */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64pos */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2_RIC (1301) - XTENSA_INS_AE_S32X2_RIC - ae_s32x2.ric $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2_RIP (1302) - XTENSA_INS_AE_S32X2_RIP - ae_s32x2.rip $ae_ls_v, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2_X (1303) - XTENSA_INS_AE_S32X2_X - ae_s32x2.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2_XC (1304) - XTENSA_INS_AE_S32X2_XC - ae_s32x2.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32X2_XP (1305) - XTENSA_INS_AE_S32X2_XP - ae_s32x2.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32_L_I (1306) - XTENSA_INS_AE_S32_L_I - ae_s32.l.i $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S32_L_IP (1307) - XTENSA_INS_AE_S32_L_IP - ae_s32.l.ip $ae_ls_v, $ars, $ae_immls32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls32 */ + { 0 } +}}, +{ /* XTENSA_AE_S32_L_X (1308) - XTENSA_INS_AE_S32_L_X - ae_s32.l.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32_L_XC (1309) - XTENSA_INS_AE_S32_L_XC - ae_s32.l.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S32_L_XP (1310) - XTENSA_INS_AE_S32_L_XP - ae_s32.l.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S64_I (1311) - XTENSA_INS_AE_S64_I - ae_s64.i $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_S64_IP (1312) - XTENSA_INS_AE_S64_IP - ae_s64.ip $ae_ls_v, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_S64_X (1313) - XTENSA_INS_AE_S64_X - ae_s64.x $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S64_XC (1314) - XTENSA_INS_AE_S64_XC - ae_s64.xc $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_S64_XP (1315) - XTENSA_INS_AE_S64_XP - ae_s64.xp $ae_ls_v, $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_SA16X4_IC (1316) - XTENSA_INS_AE_SA16X4_IC - ae_sa16x4.ic $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA16X4_IP (1317) - XTENSA_INS_AE_SA16X4_IP - ae_sa16x4.ip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA16X4_RIC (1318) - XTENSA_INS_AE_SA16X4_RIC - ae_sa16x4.ric $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA16X4_RIP (1319) - XTENSA_INS_AE_SA16X4_RIP - ae_sa16x4.rip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA24X2_IC (1320) - XTENSA_INS_AE_SA24X2_IC - ae_sa24x2.ic $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA24X2_IP (1321) - XTENSA_INS_AE_SA24X2_IP - ae_sa24x2.ip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA24X2_RIC (1322) - XTENSA_INS_AE_SA24X2_RIC - ae_sa24x2.ric $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA24X2_RIP (1323) - XTENSA_INS_AE_SA24X2_RIP - ae_sa24x2.rip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA24_L_IC (1324) - XTENSA_INS_AE_SA24_L_IC - ae_sa24.l.ic $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA24_L_IP (1325) - XTENSA_INS_AE_SA24_L_IP - ae_sa24.l.ip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA24_L_RIC (1326) - XTENSA_INS_AE_SA24_L_RIC - ae_sa24.l.ric $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA24_L_RIP (1327) - XTENSA_INS_AE_SA24_L_RIP - ae_sa24.l.rip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA32X2F24_IC (1328) - XTENSA_INS_AE_SA32X2F24_IC - ae_sa32x2f24.ic $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA32X2F24_IP (1329) - XTENSA_INS_AE_SA32X2F24_IP - ae_sa32x2f24.ip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA32X2F24_RIC (1330) - XTENSA_INS_AE_SA32X2F24_RIC - ae_sa32x2f24.ric $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA32X2F24_RIP (1331) - XTENSA_INS_AE_SA32X2F24_RIP - ae_sa32x2f24.rip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA32X2_IC (1332) - XTENSA_INS_AE_SA32X2_IC - ae_sa32x2.ic $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA32X2_IP (1333) - XTENSA_INS_AE_SA32X2_IP - ae_sa32x2.ip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA32X2_RIC (1334) - XTENSA_INS_AE_SA32X2_RIC - ae_sa32x2.ric $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA32X2_RIP (1335) - XTENSA_INS_AE_SA32X2_RIP - ae_sa32x2.rip $ae_ls_v, $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_ls_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA64NEG_FP (1336) - XTENSA_INS_AE_SA64NEG_FP - ae_sa64neg.fp $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SA64POS_FP (1337) - XTENSA_INS_AE_SA64POS_FP - ae_sa64pos.fp $ae_ls_su, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SALIGN64_I (1338) - XTENSA_INS_AE_SALIGN64_I - ae_salign64.i $ae_ls_su, $ars, $ae_immls64 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_ls_su */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_immls64 */ + { 0 } +}}, +{ /* XTENSA_AE_SAT16X4 (1339) - XTENSA_INS_AE_SAT16X4 - ae_sat16x4 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SAT24S (1340) - XTENSA_INS_AE_SAT24S - ae_sat24s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SAT48S (1341) - XTENSA_INS_AE_SAT48S - ae_sat48s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SATQ56S (1342) - XTENSA_INS_AE_SATQ56S - ae_satq56s $ae_arth_v, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SB (1343) - XTENSA_INS_AE_SB - ae_sb $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_SBF (1344) - XTENSA_INS_AE_SBF - ae_sbf $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SBF_IC (1345) - XTENSA_INS_AE_SBF_IC - ae_sbf.ic $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SBF_IP (1346) - XTENSA_INS_AE_SBF_IP - ae_sbf.ip $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SBI (1347) - XTENSA_INS_AE_SBI - ae_sbi $ars, $art, $ae_ohba2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba2 */ + { 0 } +}}, +{ /* XTENSA_AE_SBI_IC (1348) - XTENSA_INS_AE_SBI_IC - ae_sbi.ic $ars, $art, $ae_ohba2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba2 */ + { 0 } +}}, +{ /* XTENSA_AE_SBI_IP (1349) - XTENSA_INS_AE_SBI_IP - ae_sbi.ip $ars, $art, $ae_ohba2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_ohba2 */ + { 0 } +}}, +{ /* XTENSA_AE_SB_IC (1350) - XTENSA_INS_AE_SB_IC - ae_sb.ic $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_SB_IP (1351) - XTENSA_INS_AE_SB_IP - ae_sb.ip $ars, $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_SEL16I (1352) - XTENSA_INS_AE_SEL16I - ae_sel16i $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1, $ae_selimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_selimm */ + { 0 } +}}, +{ /* XTENSA_AE_SEL16I_N (1353) - XTENSA_INS_AE_SEL16I_N - ae_sel16i.n $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1, $ae_selimm_N */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_selimm_N */ + { 0 } +}}, +{ /* XTENSA_AE_SEXT32 (1354) - XTENSA_INS_AE_SEXT32 - ae_sext32 $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_opnd_tp7 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_opnd_tp7 */ + { 0 } +}}, +{ /* XTENSA_AE_SEXT32X2D16_10 (1355) - XTENSA_INS_AE_SEXT32X2D16_10 - ae_sext32x2d16.10 $ae_to_dr_v, $ae_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_SEXT32X2D16_32 (1356) - XTENSA_INS_AE_SEXT32X2D16_32 - ae_sext32x2d16.32 $ae_to_dr_v, $ae_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_SHA32 (1357) - XTENSA_INS_AE_SHA32 - ae_sha32 $arr, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SHORTSWAP (1358) - XTENSA_INS_AE_SHORTSWAP - ae_shortswap $ae_to_dr_v, $ae_to_dr_v0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_to_dr_v0 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAA16S (1359) - XTENSA_INS_AE_SLAA16S - ae_slaa16s $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SLAA32 (1360) - XTENSA_INS_AE_SLAA32 - ae_slaa32 $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SLAA32S (1361) - XTENSA_INS_AE_SLAA32S - ae_slaa32s $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SLAA64 (1362) - XTENSA_INS_AE_SLAA64 - ae_slaa64 $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SLAA64S (1363) - XTENSA_INS_AE_SLAA64S - ae_slaa64s $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SLAAQ56 (1364) - XTENSA_INS_AE_SLAAQ56 - ae_slaaq56 $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SLAI16S (1365) - XTENSA_INS_AE_SLAI16S - ae_slai16s $ae_shift_d, $ae_shift_d0, $ae_osa16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa16 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAI24 (1366) - XTENSA_INS_AE_SLAI24 - ae_slai24 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAI24S (1367) - XTENSA_INS_AE_SLAI24S - ae_slai24s $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAI32 (1368) - XTENSA_INS_AE_SLAI32 - ae_slai32 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAI32S (1369) - XTENSA_INS_AE_SLAI32S - ae_slai32s $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAI64 (1370) - XTENSA_INS_AE_SLAI64 - ae_slai64 $ae_shift_d, $ae_shift_d0, $ae_osa64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa64 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAI64S (1371) - XTENSA_INS_AE_SLAI64S - ae_slai64s $ae_shift_d, $ae_shift_d0, $ae_osa64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa64 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAISQ56S (1372) - XTENSA_INS_AE_SLAISQ56S - ae_slaisq56s $ae_shift_d, $ae_shift_d0, $ae_osa64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa64 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAS24 (1373) - XTENSA_INS_AE_SLAS24 - ae_slas24 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAS24S (1374) - XTENSA_INS_AE_SLAS24S - ae_slas24s $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAS32 (1375) - XTENSA_INS_AE_SLAS32 - ae_slas32 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAS32S (1376) - XTENSA_INS_AE_SLAS32S - ae_slas32s $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAS64 (1377) - XTENSA_INS_AE_SLAS64 - ae_slas64 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SLAS64S (1378) - XTENSA_INS_AE_SLAS64S - ae_slas64s $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SLASQ56 (1379) - XTENSA_INS_AE_SLASQ56 - ae_slasq56 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SLASSQ56S (1380) - XTENSA_INS_AE_SLASSQ56S - ae_slassq56s $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SRA64_32 (1381) - XTENSA_INS_AE_SRA64_32 - ae_sra64_32 $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRAA16RS (1382) - XTENSA_INS_AE_SRAA16RS - ae_sraa16rs $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRAA16S (1383) - XTENSA_INS_AE_SRAA16S - ae_sraa16s $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRAA32 (1384) - XTENSA_INS_AE_SRAA32 - ae_sraa32 $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRAA32RS (1385) - XTENSA_INS_AE_SRAA32RS - ae_sraa32rs $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRAA32S (1386) - XTENSA_INS_AE_SRAA32S - ae_sraa32s $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRAA64 (1387) - XTENSA_INS_AE_SRAA64 - ae_sraa64 $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRAI16 (1388) - XTENSA_INS_AE_SRAI16 - ae_srai16 $ae_shift_d, $ae_shift_d0, $ae_osa16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa16 */ + { 0 } +}}, +{ /* XTENSA_AE_SRAI16R (1389) - XTENSA_INS_AE_SRAI16R - ae_srai16r $ae_shift_d, $ae_shift_d0, $ae_osa16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa16 */ + { 0 } +}}, +{ /* XTENSA_AE_SRAI24 (1390) - XTENSA_INS_AE_SRAI24 - ae_srai24 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SRAI32 (1391) - XTENSA_INS_AE_SRAI32 - ae_srai32 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SRAI32R (1392) - XTENSA_INS_AE_SRAI32R - ae_srai32r $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SRAI64 (1393) - XTENSA_INS_AE_SRAI64 - ae_srai64 $ae_shift_d, $ae_shift_d0, $ae_osa64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa64 */ + { 0 } +}}, +{ /* XTENSA_AE_SRAS24 (1394) - XTENSA_INS_AE_SRAS24 - ae_sras24 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SRAS32 (1395) - XTENSA_INS_AE_SRAS32 - ae_sras32 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SRAS64 (1396) - XTENSA_INS_AE_SRAS64 - ae_sras64 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SRLA32 (1397) - XTENSA_INS_AE_SRLA32 - ae_srla32 $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRLA64 (1398) - XTENSA_INS_AE_SRLA64 - ae_srla64 $ae_shift_d, $ae_shift_d0, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_SRLI24 (1399) - XTENSA_INS_AE_SRLI24 - ae_srli24 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SRLI32 (1400) - XTENSA_INS_AE_SRLI32 - ae_srli32 $ae_shift_d, $ae_shift_d0, $ae_osa32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa32 */ + { 0 } +}}, +{ /* XTENSA_AE_SRLI64 (1401) - XTENSA_INS_AE_SRLI64 - ae_srli64 $ae_shift_d, $ae_shift_d0, $ae_osa64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa64 */ + { 0 } +}}, +{ /* XTENSA_AE_SRLS24 (1402) - XTENSA_INS_AE_SRLS24 - ae_srls24 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SRLS32 (1403) - XTENSA_INS_AE_SRLS32 - ae_srls32 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SRLS64 (1404) - XTENSA_INS_AE_SRLS64 - ae_srls64 $ae_shift_d, $ae_shift_d0 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { 0 } +}}, +{ /* XTENSA_AE_SUB16 (1405) - XTENSA_INS_AE_SUB16 - ae_sub16 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SUB16S (1406) - XTENSA_INS_AE_SUB16S - ae_sub16s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SUB24S (1407) - XTENSA_INS_AE_SUB24S - ae_sub24s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SUB32 (1408) - XTENSA_INS_AE_SUB32 - ae_sub32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SUB32S (1409) - XTENSA_INS_AE_SUB32S - ae_sub32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SUB64 (1410) - XTENSA_INS_AE_SUB64 - ae_sub64 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SUB64S (1411) - XTENSA_INS_AE_SUB64S - ae_sub64s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SUBADD32 (1412) - XTENSA_INS_AE_SUBADD32 - ae_subadd32 $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_SUBADD32S (1413) - XTENSA_INS_AE_SUBADD32S - ae_subadd32s $ae_arth_v, $ae_arth_v0, $ae_arth_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_arth_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_TRUNCA32F64S_L (1414) - XTENSA_INS_AE_TRUNCA32F64S_L - ae_trunca32f64s.l $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_sd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_TRUNCA32X2F64S (1415) - XTENSA_INS_AE_TRUNCA32X2F64S - ae_trunca32x2f64s $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_sd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_TRUNCI32F64S_L (1416) - XTENSA_INS_AE_TRUNCI32F64S_L - ae_trunci32f64s.l $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ae_osa16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_sd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa16 */ + { 0 } +}}, +{ /* XTENSA_AE_TRUNCI32X2F64S (1417) - XTENSA_INS_AE_TRUNCI32X2F64S - ae_trunci32x2f64s $ae_shift_d, $ae_shift_d0, $ae_shift_sd, $ae_osa16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_d0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_shift_sd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ae_osa16 */ + { 0 } +}}, +{ /* XTENSA_AE_VLDL16C (1418) - XTENSA_INS_AE_VLDL16C - ae_vldl16c $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLDL16C_IC (1419) - XTENSA_INS_AE_VLDL16C_IC - ae_vldl16c.ic $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLDL16C_IP (1420) - XTENSA_INS_AE_VLDL16C_IP - ae_vldl16c.ip $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLDL16T (1421) - XTENSA_INS_AE_VLDL16T - ae_vldl16t $br, $art, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* br */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLDL32T (1422) - XTENSA_INS_AE_VLDL32T - ae_vldl32t $br, $art, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* br */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLDSHT (1423) - XTENSA_INS_AE_VLDSHT - ae_vldsht $art */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_AE_VLEL16T (1424) - XTENSA_INS_AE_VLEL16T - ae_vlel16t $br, $art, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* br */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLEL32T (1425) - XTENSA_INS_AE_VLEL32T - ae_vlel32t $br, $art, $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* br */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLES16C (1426) - XTENSA_INS_AE_VLES16C - ae_vles16c $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLES16C_IC (1427) - XTENSA_INS_AE_VLES16C_IC - ae_vles16c.ic $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_VLES16C_IP (1428) - XTENSA_INS_AE_VLES16C_IP - ae_vles16c.ip $ars */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars_out */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ars */ + { 0 } +}}, +{ /* XTENSA_AE_XOR (1429) - XTENSA_INS_AE_XOR - ae_xor $ae_dr_to_dr_v, $ae_dr_to_dr_v0, $ae_dr_to_dr_v1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v1i32, CS_DATA_TYPE_LAST } }, /* ae_dr_to_dr_v1 */ + { 0 } +}}, +{ /* XTENSA_AE_ZALIGN64 (1430) - XTENSA_INS_AE_ZALIGN64 - ae_zalign64 $ae_uu_uu */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i8, CS_DATA_TYPE_LAST } }, /* ae_uu_uu */ + { 0 } +}}, +{ /* XTENSA_ALL4 (1431) - XTENSA_INS_ALL4 - all4 $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_ALL8 (1432) - XTENSA_INS_ALL8 - all8 $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_AND (1433) - XTENSA_INS_AND - and $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ANDB (1434) - XTENSA_INS_ANDB - andb $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ANDBC (1435) - XTENSA_INS_ANDBC - andbc $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ANY4 (1436) - XTENSA_INS_ANY4 - any4 $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_ANY8 (1437) - XTENSA_INS_ANY8 - any8 $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_BALL (1438) - XTENSA_INS_BALL - ball $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BANY (1439) - XTENSA_INS_BANY - bany $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BBC (1440) - XTENSA_INS_BBC - bbc $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BBCI (1441) - XTENSA_INS_BBCI - bbci $s, $imm, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BBS (1442) - XTENSA_INS_BBS - bbs $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BBSI (1443) - XTENSA_INS_BBSI - bbsi $s, $imm, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BEQ (1444) - XTENSA_INS_BEQ - beq $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BEQI (1445) - XTENSA_INS_BEQI - beqi $s, $imm, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BEQZ (1446) - XTENSA_INS_BEQZ - beqz $s, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BF (1447) - XTENSA_INS_BF - bf $b, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* b */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BGE (1448) - XTENSA_INS_BGE - bge $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BGEI (1449) - XTENSA_INS_BGEI - bgei $s, $imm, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BGEU (1450) - XTENSA_INS_BGEU - bgeu $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BGEUI (1451) - XTENSA_INS_BGEUI - bgeui $s, $imm, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BGEZ (1452) - XTENSA_INS_BGEZ - bgez $s, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BLT (1453) - XTENSA_INS_BLT - blt $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BLTI (1454) - XTENSA_INS_BLTI - blti $s, $imm, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BLTU (1455) - XTENSA_INS_BLTU - bltu $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BLTUI (1456) - XTENSA_INS_BLTUI - bltui $s, $imm, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BLTZ (1457) - XTENSA_INS_BLTZ - bltz $s, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BNALL (1458) - XTENSA_INS_BNALL - bnall $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BNE (1459) - XTENSA_INS_BNE - bne $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BNEI (1460) - XTENSA_INS_BNEI - bnei $s, $imm, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BNEZ (1461) - XTENSA_INS_BNEZ - bnez $s, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BNONE (1462) - XTENSA_INS_BNONE - bnone $s, $t, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_BREAK (1463) - XTENSA_INS_BREAK - break $s, $t */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_BREAK_N (1464) - XTENSA_INS_BREAK_N - break.n $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_BT (1465) - XTENSA_INS_BT - bt $b, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* b */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_CALL0 (1466) - XTENSA_INS_CALL0 - call0 $offset */ +{ + { CS_OP_INVALID | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* XTENSA_CALL12 (1467) - XTENSA_INS_CALL12 - call12 $offset */ +{ + { CS_OP_INVALID | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* XTENSA_CALL4 (1468) - XTENSA_INS_CALL4 - call4 $offset */ +{ + { CS_OP_INVALID | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* XTENSA_CALL8 (1469) - XTENSA_INS_CALL8 - call8 $offset */ +{ + { CS_OP_INVALID | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* XTENSA_CALLX0 (1470) - XTENSA_INS_CALLX0 - callx0 $s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_CALLX12 (1471) - XTENSA_INS_CALLX12 - callx12 $s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_CALLX4 (1472) - XTENSA_INS_CALLX4 - callx4 $s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_CALLX8 (1473) - XTENSA_INS_CALLX8 - callx8 $s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_CEIL_S (1474) - XTENSA_INS_CEIL_S - ceil.s $r, $s, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_CLAMPS (1475) - XTENSA_INS_CLAMPS - clamps $r, $s, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_CLR_BIT_GPIO_OUT (1476) - XTENSA_INS_CLR_BIT_GPIO_OUT - clr_bit_gpio_out $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_CONST_S (1477) - XTENSA_INS_CONST_S - const.s $r, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_DIV0_S (1478) - XTENSA_INS_DIV0_S - div0.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_DIVN_S (1479) - XTENSA_INS_DIVN_S - divn.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_DSYNC (1480) - XTENSA_INS_DSYNC - dsync */ +{ + { 0 } +}}, +{ /* XTENSA_EE_ANDQ (1481) - XTENSA_INS_EE_ANDQ - ee.andq $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_BITREV (1482) - XTENSA_INS_EE_BITREV - ee.bitrev $qa, $ax */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* axr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ax */ + { 0 } +}}, +{ /* XTENSA_EE_CLR_BIT_GPIO_OUT (1483) - XTENSA_INS_EE_CLR_BIT_GPIO_OUT - ee.clr_bit_gpio_out $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_EE_CMUL_S16 (1484) - XTENSA_INS_EE_CMUL_S16 - ee.cmul.s16 $qz, $qx, $qy, $sel4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel4 */ + { 0 } +}}, +{ /* XTENSA_EE_CMUL_S16_LD_INCP (1485) - XTENSA_INS_EE_CMUL_S16_LD_INCP - ee.cmul.s16.ld.incp $qu, $as, $qz, $qx, $qy, $sel4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel4 */ + { 0 } +}}, +{ /* XTENSA_EE_CMUL_S16_ST_INCP (1486) - XTENSA_INS_EE_CMUL_S16_ST_INCP - ee.cmul.s16.st.incp $qv, $as, $qz, $qx, $qy, $sel4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel4 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_AMS_S16_LD_INCP (1487) - XTENSA_INS_EE_FFT_AMS_S16_LD_INCP - ee.fft.ams.s16.ld.incp $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel2 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_AMS_S16_LD_INCP_UAUP (1488) - XTENSA_INS_EE_FFT_AMS_S16_LD_INCP_UAUP - ee.fft.ams.s16.ld.incp.uaup $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel2 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_AMS_S16_LD_R32_DECP (1489) - XTENSA_INS_EE_FFT_AMS_S16_LD_R32_DECP - ee.fft.ams.s16.ld.r32.decp $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel2 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_AMS_S16_ST_INCP (1490) - XTENSA_INS_EE_FFT_AMS_S16_ST_INCP - ee.fft.ams.s16.st.incp $qv, $qz1, $as0, $as, $qx, $qy, $qm, $sel2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel2 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_CMUL_S16_LD_XP (1491) - XTENSA_INS_EE_FFT_CMUL_S16_LD_XP - ee.fft.cmul.s16.ld.xp $qu, $as, $ad, $qz, $qx, $qy, $sel8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel8 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_CMUL_S16_ST_XP (1492) - XTENSA_INS_EE_FFT_CMUL_S16_ST_XP - ee.fft.cmul.s16.st.xp $qx, $qy, $qv, $as, $ad, $sel8, $upd4, $sar4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel8 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* upd4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sar4 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_R2BF_S16 (1493) - XTENSA_INS_EE_FFT_R2BF_S16 - ee.fft.r2bf.s16 $qa0, $qa1, $qx, $qy, $sel2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel2 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_R2BF_S16_ST_INCP (1494) - XTENSA_INS_EE_FFT_R2BF_S16_ST_INCP - ee.fft.r2bf.s16.st.incp $qa0, $qx, $qy, $as, $sar4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sar4 */ + { 0 } +}}, +{ /* XTENSA_EE_FFT_VST_R32_DECP (1495) - XTENSA_INS_EE_FFT_VST_R32_DECP - ee.fft.vst.r32.decp $qv, $as, $sar2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sar2 */ + { 0 } +}}, +{ /* XTENSA_EE_GET_GPIO_IN (1496) - XTENSA_INS_EE_GET_GPIO_IN - ee.get_gpio_in $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_EE_LDF_128_IP (1497) - XTENSA_INS_EE_LDF_128_IP - ee.ldf.128.ip $fu3, $fu2, $fu1, $fu0, $as, $imm16f */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu3 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu2 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16f */ + { 0 } +}}, +{ /* XTENSA_EE_LDF_128_XP (1498) - XTENSA_INS_EE_LDF_128_XP - ee.ldf.128.xp $fu3, $fu2, $fu1, $fu0, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu3 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu2 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_LDF_64_IP (1499) - XTENSA_INS_EE_LDF_64_IP - ee.ldf.64.ip $fu1, $fu0, $as, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_EE_LDF_64_XP (1500) - XTENSA_INS_EE_LDF_64_XP - ee.ldf.64.xp $fu1, $fu0, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fu0 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_LDQA_S16_128_IP (1501) - XTENSA_INS_EE_LDQA_S16_128_IP - ee.ldqa.s16.128.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_LDQA_S16_128_XP (1502) - XTENSA_INS_EE_LDQA_S16_128_XP - ee.ldqa.s16.128.xp $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_LDQA_S8_128_IP (1503) - XTENSA_INS_EE_LDQA_S8_128_IP - ee.ldqa.s8.128.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_LDQA_S8_128_XP (1504) - XTENSA_INS_EE_LDQA_S8_128_XP - ee.ldqa.s8.128.xp $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_LDQA_U16_128_IP (1505) - XTENSA_INS_EE_LDQA_U16_128_IP - ee.ldqa.u16.128.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_LDQA_U16_128_XP (1506) - XTENSA_INS_EE_LDQA_U16_128_XP - ee.ldqa.u16.128.xp $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_LDQA_U8_128_IP (1507) - XTENSA_INS_EE_LDQA_U8_128_IP - ee.ldqa.u8.128.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_LDQA_U8_128_XP (1508) - XTENSA_INS_EE_LDQA_U8_128_XP - ee.ldqa.u8.128.xp $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_LDXQ_32 (1509) - XTENSA_INS_EE_LDXQ_32 - ee.ldxq.32 $qu, $qs, $as, $sel4, $sel8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel8 */ + { 0 } +}}, +{ /* XTENSA_EE_LD_128_USAR_IP (1510) - XTENSA_INS_EE_LD_128_USAR_IP - ee.ld.128.usar.ip $qu, $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_LD_128_USAR_XP (1511) - XTENSA_INS_EE_LD_128_USAR_XP - ee.ld.128.usar.xp $qu, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_LD_ACCX_IP (1512) - XTENSA_INS_EE_LD_ACCX_IP - ee.ld.accx.ip $as, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_EE_LD_QACC_H_H_32_IP (1513) - XTENSA_INS_EE_LD_QACC_H_H_32_IP - ee.ld.qacc_h.h.32.ip $as, $imm4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm4 */ + { 0 } +}}, +{ /* XTENSA_EE_LD_QACC_H_L_128_IP (1514) - XTENSA_INS_EE_LD_QACC_H_L_128_IP - ee.ld.qacc_h.l.128.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_LD_QACC_L_H_32_IP (1515) - XTENSA_INS_EE_LD_QACC_L_H_32_IP - ee.ld.qacc_l.h.32.ip $as, $imm4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm4 */ + { 0 } +}}, +{ /* XTENSA_EE_LD_QACC_L_L_128_IP (1516) - XTENSA_INS_EE_LD_QACC_L_L_128_IP - ee.ld.qacc_l.l.128.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_LD_UA_STATE_IP (1517) - XTENSA_INS_EE_LD_UA_STATE_IP - ee.ld.ua_state.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_MOVI_32_A (1518) - XTENSA_INS_EE_MOVI_32_A - ee.movi.32.a $qs, $au, $sel4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* au */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel4 */ + { 0 } +}}, +{ /* XTENSA_EE_MOVI_32_Q (1519) - XTENSA_INS_EE_MOVI_32_Q - ee.movi.32.q $qu, $as, $sel4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel4 */ + { 0 } +}}, +{ /* XTENSA_EE_MOV_S16_QACC (1520) - XTENSA_INS_EE_MOV_S16_QACC - ee.mov.s16.qacc $qs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { 0 } +}}, +{ /* XTENSA_EE_MOV_S8_QACC (1521) - XTENSA_INS_EE_MOV_S8_QACC - ee.mov.s8.qacc $qs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { 0 } +}}, +{ /* XTENSA_EE_MOV_U16_QACC (1522) - XTENSA_INS_EE_MOV_U16_QACC - ee.mov.u16.qacc $qs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { 0 } +}}, +{ /* XTENSA_EE_MOV_U8_QACC (1523) - XTENSA_INS_EE_MOV_U8_QACC - ee.mov.u8.qacc $qs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { 0 } +}}, +{ /* XTENSA_EE_NOTQ (1524) - XTENSA_INS_EE_NOTQ - ee.notq $qa, $qx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { 0 } +}}, +{ /* XTENSA_EE_ORQ (1525) - XTENSA_INS_EE_ORQ - ee.orq $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_SET_BIT_GPIO_OUT (1526) - XTENSA_INS_EE_SET_BIT_GPIO_OUT - ee.set_bit_gpio_out $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_EE_SLCI_2Q (1527) - XTENSA_INS_EE_SLCI_2Q - ee.slci.2q $qs1, $qs0, $sar16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sar16 */ + { 0 } +}}, +{ /* XTENSA_EE_SLCXXP_2Q (1528) - XTENSA_INS_EE_SLCXXP_2Q - ee.slcxxp.2q $qs1, $qs0, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_SRCI_2Q (1529) - XTENSA_INS_EE_SRCI_2Q - ee.srci.2q $qs1, $qs0, $sar16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sar16 */ + { 0 } +}}, +{ /* XTENSA_EE_SRCMB_S16_QACC (1530) - XTENSA_INS_EE_SRCMB_S16_QACC - ee.srcmb.s16.qacc $qu, $as, $sel2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel2 */ + { 0 } +}}, +{ /* XTENSA_EE_SRCMB_S8_QACC (1531) - XTENSA_INS_EE_SRCMB_S8_QACC - ee.srcmb.s8.qacc $qu, $as, $sel2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel2 */ + { 0 } +}}, +{ /* XTENSA_EE_SRCQ_128_ST_INCP (1532) - XTENSA_INS_EE_SRCQ_128_ST_INCP - ee.srcq.128.st.incp $qs0, $qs1, $as */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { 0 } +}}, +{ /* XTENSA_EE_SRCXXP_2Q (1533) - XTENSA_INS_EE_SRCXXP_2Q - ee.srcxxp.2q $qs1, $qs0, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_SRC_Q (1534) - XTENSA_INS_EE_SRC_Q - ee.src.q $qa, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_SRC_Q_LD_IP (1535) - XTENSA_INS_EE_SRC_Q_LD_IP - ee.src.q.ld.ip $qu, $as, $imm16, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_SRC_Q_LD_XP (1536) - XTENSA_INS_EE_SRC_Q_LD_XP - ee.src.q.ld.xp $qu, $as, $ad, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_SRC_Q_QUP (1537) - XTENSA_INS_EE_SRC_Q_QUP - ee.src.q.qup $qa, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_SRS_ACCX (1538) - XTENSA_INS_EE_SRS_ACCX - ee.srs.accx $au, $as, $sel2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* au */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel2 */ + { 0 } +}}, +{ /* XTENSA_EE_STF_128_IP (1539) - XTENSA_INS_EE_STF_128_IP - ee.stf.128.ip $fv3, $fv2, $fv1, $fv0, $as, $imm16f */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16f */ + { 0 } +}}, +{ /* XTENSA_EE_STF_128_XP (1540) - XTENSA_INS_EE_STF_128_XP - ee.stf.128.xp $fv3, $fv2, $fv1, $fv0, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_STF_64_IP (1541) - XTENSA_INS_EE_STF_64_IP - ee.stf.64.ip $fv1, $fv0, $as, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_EE_STF_64_XP (1542) - XTENSA_INS_EE_STF_64_XP - ee.stf.64.xp $fv1, $fv0, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fv0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_STXQ_32 (1543) - XTENSA_INS_EE_STXQ_32 - ee.stxq.32 $qv, $qs, $as, $sel4, $sel8 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel8 */ + { 0 } +}}, +{ /* XTENSA_EE_ST_ACCX_IP (1544) - XTENSA_INS_EE_ST_ACCX_IP - ee.st.accx.ip $as, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_EE_ST_QACC_H_H_32_IP (1545) - XTENSA_INS_EE_ST_QACC_H_H_32_IP - ee.st.qacc_h.h.32.ip $as, $imm4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm4 */ + { 0 } +}}, +{ /* XTENSA_EE_ST_QACC_H_L_128_IP (1546) - XTENSA_INS_EE_ST_QACC_H_L_128_IP - ee.st.qacc_h.l.128.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_ST_QACC_L_H_32_IP (1547) - XTENSA_INS_EE_ST_QACC_L_H_32_IP - ee.st.qacc_l.h.32.ip $as, $imm4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm4 */ + { 0 } +}}, +{ /* XTENSA_EE_ST_QACC_L_L_128_IP (1548) - XTENSA_INS_EE_ST_QACC_L_L_128_IP - ee.st.qacc_l.l.128.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_ST_UA_STATE_IP (1549) - XTENSA_INS_EE_ST_UA_STATE_IP - ee.st.ua_state.ip $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S16 (1550) - XTENSA_INS_EE_VADDS_S16 - ee.vadds.s16 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S16_LD_INCP (1551) - XTENSA_INS_EE_VADDS_S16_LD_INCP - ee.vadds.s16.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S16_ST_INCP (1552) - XTENSA_INS_EE_VADDS_S16_ST_INCP - ee.vadds.s16.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S32 (1553) - XTENSA_INS_EE_VADDS_S32 - ee.vadds.s32 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S32_LD_INCP (1554) - XTENSA_INS_EE_VADDS_S32_LD_INCP - ee.vadds.s32.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S32_ST_INCP (1555) - XTENSA_INS_EE_VADDS_S32_ST_INCP - ee.vadds.s32.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S8 (1556) - XTENSA_INS_EE_VADDS_S8 - ee.vadds.s8 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S8_LD_INCP (1557) - XTENSA_INS_EE_VADDS_S8_LD_INCP - ee.vadds.s8.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VADDS_S8_ST_INCP (1558) - XTENSA_INS_EE_VADDS_S8_ST_INCP - ee.vadds.s8.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_EQ_S16 (1559) - XTENSA_INS_EE_VCMP_EQ_S16 - ee.vcmp.eq.s16 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_EQ_S32 (1560) - XTENSA_INS_EE_VCMP_EQ_S32 - ee.vcmp.eq.s32 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_EQ_S8 (1561) - XTENSA_INS_EE_VCMP_EQ_S8 - ee.vcmp.eq.s8 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_GT_S16 (1562) - XTENSA_INS_EE_VCMP_GT_S16 - ee.vcmp.gt.s16 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_GT_S32 (1563) - XTENSA_INS_EE_VCMP_GT_S32 - ee.vcmp.gt.s32 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_GT_S8 (1564) - XTENSA_INS_EE_VCMP_GT_S8 - ee.vcmp.gt.s8 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_LT_S16 (1565) - XTENSA_INS_EE_VCMP_LT_S16 - ee.vcmp.lt.s16 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_LT_S32 (1566) - XTENSA_INS_EE_VCMP_LT_S32 - ee.vcmp.lt.s32 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VCMP_LT_S8 (1567) - XTENSA_INS_EE_VCMP_LT_S8 - ee.vcmp.lt.s8 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_16 (1568) - XTENSA_INS_EE_VLDBC_16 - ee.vldbc.16 $qu, $as */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_16_IP (1569) - XTENSA_INS_EE_VLDBC_16_IP - ee.vldbc.16.ip $qu, $as, $imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_16_XP (1570) - XTENSA_INS_EE_VLDBC_16_XP - ee.vldbc.16.xp $qu, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_32 (1571) - XTENSA_INS_EE_VLDBC_32 - ee.vldbc.32 $qu, $as */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_32_IP (1572) - XTENSA_INS_EE_VLDBC_32_IP - ee.vldbc.32.ip $qu, $as, $imm4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm4 */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_32_XP (1573) - XTENSA_INS_EE_VLDBC_32_XP - ee.vldbc.32.xp $qu, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_8 (1574) - XTENSA_INS_EE_VLDBC_8 - ee.vldbc.8 $qu, $as */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_8_IP (1575) - XTENSA_INS_EE_VLDBC_8_IP - ee.vldbc.8.ip $qu, $as, $imm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm1 */ + { 0 } +}}, +{ /* XTENSA_EE_VLDBC_8_XP (1576) - XTENSA_INS_EE_VLDBC_8_XP - ee.vldbc.8.xp $qu, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VLDHBC_16_INCP (1577) - XTENSA_INS_EE_VLDHBC_16_INCP - ee.vldhbc.16.incp $qu, $qu1, $as */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { 0 } +}}, +{ /* XTENSA_EE_VLD_128_IP (1578) - XTENSA_INS_EE_VLD_128_IP - ee.vld.128.ip $qu, $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_VLD_128_XP (1579) - XTENSA_INS_EE_VLD_128_XP - ee.vld.128.xp $qu, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VLD_H_64_IP (1580) - XTENSA_INS_EE_VLD_H_64_IP - ee.vld.h.64.ip $qu, $as, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_EE_VLD_H_64_XP (1581) - XTENSA_INS_EE_VLD_H_64_XP - ee.vld.h.64.xp $qu, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VLD_L_64_IP (1582) - XTENSA_INS_EE_VLD_L_64_IP - ee.vld.l.64.ip $qu, $as, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_EE_VLD_L_64_XP (1583) - XTENSA_INS_EE_VLD_L_64_XP - ee.vld.l.64.xp $qu, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S16 (1584) - XTENSA_INS_EE_VMAX_S16 - ee.vmax.s16 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S16_LD_INCP (1585) - XTENSA_INS_EE_VMAX_S16_LD_INCP - ee.vmax.s16.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S16_ST_INCP (1586) - XTENSA_INS_EE_VMAX_S16_ST_INCP - ee.vmax.s16.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S32 (1587) - XTENSA_INS_EE_VMAX_S32 - ee.vmax.s32 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S32_LD_INCP (1588) - XTENSA_INS_EE_VMAX_S32_LD_INCP - ee.vmax.s32.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S32_ST_INCP (1589) - XTENSA_INS_EE_VMAX_S32_ST_INCP - ee.vmax.s32.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S8 (1590) - XTENSA_INS_EE_VMAX_S8 - ee.vmax.s8 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S8_LD_INCP (1591) - XTENSA_INS_EE_VMAX_S8_LD_INCP - ee.vmax.s8.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMAX_S8_ST_INCP (1592) - XTENSA_INS_EE_VMAX_S8_ST_INCP - ee.vmax.s8.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S16 (1593) - XTENSA_INS_EE_VMIN_S16 - ee.vmin.s16 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S16_LD_INCP (1594) - XTENSA_INS_EE_VMIN_S16_LD_INCP - ee.vmin.s16.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S16_ST_INCP (1595) - XTENSA_INS_EE_VMIN_S16_ST_INCP - ee.vmin.s16.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S32 (1596) - XTENSA_INS_EE_VMIN_S32 - ee.vmin.s32 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S32_LD_INCP (1597) - XTENSA_INS_EE_VMIN_S32_LD_INCP - ee.vmin.s32.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S32_ST_INCP (1598) - XTENSA_INS_EE_VMIN_S32_ST_INCP - ee.vmin.s32.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S8 (1599) - XTENSA_INS_EE_VMIN_S8 - ee.vmin.s8 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S8_LD_INCP (1600) - XTENSA_INS_EE_VMIN_S8_LD_INCP - ee.vmin.s8.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMIN_S8_ST_INCP (1601) - XTENSA_INS_EE_VMIN_S8_ST_INCP - ee.vmin.s8.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_ACCX (1602) - XTENSA_INS_EE_VMULAS_S16_ACCX - ee.vmulas.s16.accx $qx, $qy */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_ACCX_LD_IP (1603) - XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP - ee.vmulas.s16.accx.ld.ip $qu, $as, $imm16, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_ACCX_LD_IP_QUP (1604) - XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP_QUP - ee.vmulas.s16.accx.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_ACCX_LD_XP (1605) - XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP - ee.vmulas.s16.accx.ld.xp $qu, $as, $ad, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_ACCX_LD_XP_QUP (1606) - XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP_QUP - ee.vmulas.s16.accx.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_QACC (1607) - XTENSA_INS_EE_VMULAS_S16_QACC - ee.vmulas.s16.qacc $qx, $qy */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_QACC_LDBC_INCP (1608) - XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP - ee.vmulas.s16.qacc.ldbc.incp $qu, $as, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_QACC_LDBC_INCP_QUP (1609) - XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP_QUP - ee.vmulas.s16.qacc.ldbc.incp.qup $qu, $as, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_QACC_LD_IP (1610) - XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP - ee.vmulas.s16.qacc.ld.ip $qu, $as, $imm16, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_QACC_LD_IP_QUP (1611) - XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP_QUP - ee.vmulas.s16.qacc.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_QACC_LD_XP (1612) - XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP - ee.vmulas.s16.qacc.ld.xp $qu, $as, $ad, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S16_QACC_LD_XP_QUP (1613) - XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP_QUP - ee.vmulas.s16.qacc.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_ACCX (1614) - XTENSA_INS_EE_VMULAS_S8_ACCX - ee.vmulas.s8.accx $qx, $qy */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_ACCX_LD_IP (1615) - XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP - ee.vmulas.s8.accx.ld.ip $qu, $as, $imm16, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_ACCX_LD_IP_QUP (1616) - XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP_QUP - ee.vmulas.s8.accx.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_ACCX_LD_XP (1617) - XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP - ee.vmulas.s8.accx.ld.xp $qu, $as, $ad, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_ACCX_LD_XP_QUP (1618) - XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP_QUP - ee.vmulas.s8.accx.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_QACC (1619) - XTENSA_INS_EE_VMULAS_S8_QACC - ee.vmulas.s8.qacc $qx, $qy */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_QACC_LDBC_INCP (1620) - XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP - ee.vmulas.s8.qacc.ldbc.incp $qu, $as, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_QACC_LDBC_INCP_QUP (1621) - XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP_QUP - ee.vmulas.s8.qacc.ldbc.incp.qup $qu, $as, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_QACC_LD_IP (1622) - XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP - ee.vmulas.s8.qacc.ld.ip $qu, $as, $imm16, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_QACC_LD_IP_QUP (1623) - XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP_QUP - ee.vmulas.s8.qacc.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_QACC_LD_XP (1624) - XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP - ee.vmulas.s8.qacc.ld.xp $qu, $as, $ad, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_S8_QACC_LD_XP_QUP (1625) - XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP_QUP - ee.vmulas.s8.qacc.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_ACCX (1626) - XTENSA_INS_EE_VMULAS_U16_ACCX - ee.vmulas.u16.accx $qx, $qy */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_ACCX_LD_IP (1627) - XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP - ee.vmulas.u16.accx.ld.ip $qu, $as, $imm16, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_ACCX_LD_IP_QUP (1628) - XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP_QUP - ee.vmulas.u16.accx.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_ACCX_LD_XP (1629) - XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP - ee.vmulas.u16.accx.ld.xp $qu, $as, $ad, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_ACCX_LD_XP_QUP (1630) - XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP_QUP - ee.vmulas.u16.accx.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_QACC (1631) - XTENSA_INS_EE_VMULAS_U16_QACC - ee.vmulas.u16.qacc $qx, $qy */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_QACC_LDBC_INCP (1632) - XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP - ee.vmulas.u16.qacc.ldbc.incp $qu, $as, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_QACC_LDBC_INCP_QUP (1633) - XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP_QUP - ee.vmulas.u16.qacc.ldbc.incp.qup $qu, $as, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_QACC_LD_IP (1634) - XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP - ee.vmulas.u16.qacc.ld.ip $qu, $as, $imm16, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_QACC_LD_IP_QUP (1635) - XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP_QUP - ee.vmulas.u16.qacc.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_QACC_LD_XP (1636) - XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP - ee.vmulas.u16.qacc.ld.xp $qu, $as, $ad, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U16_QACC_LD_XP_QUP (1637) - XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP_QUP - ee.vmulas.u16.qacc.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_ACCX (1638) - XTENSA_INS_EE_VMULAS_U8_ACCX - ee.vmulas.u8.accx $qx, $qy */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_ACCX_LD_IP (1639) - XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP - ee.vmulas.u8.accx.ld.ip $qu, $as, $imm16, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_ACCX_LD_IP_QUP (1640) - XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP_QUP - ee.vmulas.u8.accx.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_ACCX_LD_XP (1641) - XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP - ee.vmulas.u8.accx.ld.xp $qu, $as, $ad, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_ACCX_LD_XP_QUP (1642) - XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP_QUP - ee.vmulas.u8.accx.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_QACC (1643) - XTENSA_INS_EE_VMULAS_U8_QACC - ee.vmulas.u8.qacc $qx, $qy */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_QACC_LDBC_INCP (1644) - XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP - ee.vmulas.u8.qacc.ldbc.incp $qu, $as, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_QACC_LDBC_INCP_QUP (1645) - XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP_QUP - ee.vmulas.u8.qacc.ldbc.incp.qup $qu, $as, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_QACC_LD_IP (1646) - XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP - ee.vmulas.u8.qacc.ld.ip $qu, $as, $imm16, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_QACC_LD_IP_QUP (1647) - XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP_QUP - ee.vmulas.u8.qacc.ld.ip.qup $qu, $as, $imm16, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_QACC_LD_XP (1648) - XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP - ee.vmulas.u8.qacc.ld.xp $qu, $as, $ad, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMULAS_U8_QACC_LD_XP_QUP (1649) - XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP_QUP - ee.vmulas.u8.qacc.ld.xp.qup $qu, $as, $ad, $qx, $qy, $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_S16 (1650) - XTENSA_INS_EE_VMUL_S16 - ee.vmul.s16 $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_S16_LD_INCP (1651) - XTENSA_INS_EE_VMUL_S16_LD_INCP - ee.vmul.s16.ld.incp $qu, $as, $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_S16_ST_INCP (1652) - XTENSA_INS_EE_VMUL_S16_ST_INCP - ee.vmul.s16.st.incp $qv, $as, $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_S8 (1653) - XTENSA_INS_EE_VMUL_S8 - ee.vmul.s8 $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_S8_LD_INCP (1654) - XTENSA_INS_EE_VMUL_S8_LD_INCP - ee.vmul.s8.ld.incp $qu, $as, $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_S8_ST_INCP (1655) - XTENSA_INS_EE_VMUL_S8_ST_INCP - ee.vmul.s8.st.incp $qv, $as, $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_U16 (1656) - XTENSA_INS_EE_VMUL_U16 - ee.vmul.u16 $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_U16_LD_INCP (1657) - XTENSA_INS_EE_VMUL_U16_LD_INCP - ee.vmul.u16.ld.incp $qu, $as, $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_U16_ST_INCP (1658) - XTENSA_INS_EE_VMUL_U16_ST_INCP - ee.vmul.u16.st.incp $qv, $as, $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_U8 (1659) - XTENSA_INS_EE_VMUL_U8 - ee.vmul.u8 $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_U8_LD_INCP (1660) - XTENSA_INS_EE_VMUL_U8_LD_INCP - ee.vmul.u8.ld.incp $qu, $as, $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VMUL_U8_ST_INCP (1661) - XTENSA_INS_EE_VMUL_U8_ST_INCP - ee.vmul.u8.st.incp $qv, $as, $qz, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VPRELU_S16 (1662) - XTENSA_INS_EE_VPRELU_S16 - ee.vprelu.s16 $qz, $qx, $qy, $ay */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ay */ + { 0 } +}}, +{ /* XTENSA_EE_VPRELU_S8 (1663) - XTENSA_INS_EE_VPRELU_S8 - ee.vprelu.s8 $qz, $qx, $qy, $ay */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ay */ + { 0 } +}}, +{ /* XTENSA_EE_VRELU_S16 (1664) - XTENSA_INS_EE_VRELU_S16 - ee.vrelu.s16 $qs, $ax, $ay */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qsr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ax */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ay */ + { 0 } +}}, +{ /* XTENSA_EE_VRELU_S8 (1665) - XTENSA_INS_EE_VRELU_S8 - ee.vrelu.s8 $qs, $ax, $ay */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qsr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ax */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ay */ + { 0 } +}}, +{ /* XTENSA_EE_VSL_32 (1666) - XTENSA_INS_EE_VSL_32 - ee.vsl.32 $qa, $qs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { 0 } +}}, +{ /* XTENSA_EE_VSMULAS_S16_QACC (1667) - XTENSA_INS_EE_VSMULAS_S16_QACC - ee.vsmulas.s16.qacc $qx, $qy, $sel8 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel8 */ + { 0 } +}}, +{ /* XTENSA_EE_VSMULAS_S16_QACC_LD_INCP (1668) - XTENSA_INS_EE_VSMULAS_S16_QACC_LD_INCP - ee.vsmulas.s16.qacc.ld.incp $qu, $as, $qx, $qy, $sel8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel8 */ + { 0 } +}}, +{ /* XTENSA_EE_VSMULAS_S8_QACC (1669) - XTENSA_INS_EE_VSMULAS_S8_QACC - ee.vsmulas.s8.qacc $qx, $qy, $sel16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel16 */ + { 0 } +}}, +{ /* XTENSA_EE_VSMULAS_S8_QACC_LD_INCP (1670) - XTENSA_INS_EE_VSMULAS_S8_QACC_LD_INCP - ee.vsmulas.s8.qacc.ld.incp $qu, $as, $qx, $qy, $sel16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel16 */ + { 0 } +}}, +{ /* XTENSA_EE_VSR_32 (1671) - XTENSA_INS_EE_VSR_32 - ee.vsr.32 $qa, $qs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs */ + { 0 } +}}, +{ /* XTENSA_EE_VST_128_IP (1672) - XTENSA_INS_EE_VST_128_IP - ee.vst.128.ip $qv, $as, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* XTENSA_EE_VST_128_XP (1673) - XTENSA_INS_EE_VST_128_XP - ee.vst.128.xp $qv, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VST_H_64_IP (1674) - XTENSA_INS_EE_VST_H_64_IP - ee.vst.h.64.ip $qv, $as, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_EE_VST_H_64_XP (1675) - XTENSA_INS_EE_VST_H_64_XP - ee.vst.h.64.xp $qv, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VST_L_64_IP (1676) - XTENSA_INS_EE_VST_L_64_IP - ee.vst.l.64.ip $qv, $as, $imm8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* XTENSA_EE_VST_L_64_XP (1677) - XTENSA_INS_EE_VST_L_64_XP - ee.vst.l.64.xp $qv, $as, $ad */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ad */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S16 (1678) - XTENSA_INS_EE_VSUBS_S16 - ee.vsubs.s16 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S16_LD_INCP (1679) - XTENSA_INS_EE_VSUBS_S16_LD_INCP - ee.vsubs.s16.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S16_ST_INCP (1680) - XTENSA_INS_EE_VSUBS_S16_ST_INCP - ee.vsubs.s16.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S32 (1681) - XTENSA_INS_EE_VSUBS_S32 - ee.vsubs.s32 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S32_LD_INCP (1682) - XTENSA_INS_EE_VSUBS_S32_LD_INCP - ee.vsubs.s32.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S32_ST_INCP (1683) - XTENSA_INS_EE_VSUBS_S32_ST_INCP - ee.vsubs.s32.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S8 (1684) - XTENSA_INS_EE_VSUBS_S8 - ee.vsubs.s8 $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S8_LD_INCP (1685) - XTENSA_INS_EE_VSUBS_S8_LD_INCP - ee.vsubs.s8.ld.incp $qu, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qu */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VSUBS_S8_ST_INCP (1686) - XTENSA_INS_EE_VSUBS_S8_ST_INCP - ee.vsubs.s8.st.incp $qv, $as, $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* asr */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qv */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* as */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_VUNZIP_16 (1687) - XTENSA_INS_EE_VUNZIP_16 - ee.vunzip.16 $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VUNZIP_32 (1688) - XTENSA_INS_EE_VUNZIP_32 - ee.vunzip.32 $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VUNZIP_8 (1689) - XTENSA_INS_EE_VUNZIP_8 - ee.vunzip.8 $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VZIP_16 (1690) - XTENSA_INS_EE_VZIP_16 - ee.vzip.16 $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VZIP_32 (1691) - XTENSA_INS_EE_VZIP_32 - ee.vzip.32 $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_VZIP_8 (1692) - XTENSA_INS_EE_VZIP_8 - ee.vzip.8 $qs0, $qs1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs0 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qs1 */ + { 0 } +}}, +{ /* XTENSA_EE_WR_MASK_GPIO_OUT (1693) - XTENSA_INS_EE_WR_MASK_GPIO_OUT - ee.wr_mask_gpio_out $t, $s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_EE_XORQ (1694) - XTENSA_INS_EE_XORQ - ee.xorq $qa, $qx, $qy */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qy */ + { 0 } +}}, +{ /* XTENSA_EE_ZERO_ACCX (1695) - XTENSA_INS_EE_ZERO_ACCX - ee.zero.accx */ +{ + { 0 } +}}, +{ /* XTENSA_EE_ZERO_Q (1696) - XTENSA_INS_EE_ZERO_Q - ee.zero.q $qa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* qa */ + { 0 } +}}, +{ /* XTENSA_EE_ZERO_QACC (1697) - XTENSA_INS_EE_ZERO_QACC - ee.zero.qacc */ +{ + { 0 } +}}, +{ /* XTENSA_ENTRY (1698) - XTENSA_INS_ENTRY - entry $s, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_ESYNC (1699) - XTENSA_INS_ESYNC - esync */ +{ + { 0 } +}}, +{ /* XTENSA_EXCW (1700) - XTENSA_INS_EXCW - excw */ +{ + { 0 } +}}, +{ /* XTENSA_EXTUI (1701) - XTENSA_INS_EXTUI - extui $r, $t, $imm1, $imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ + { 0 } +}}, +{ /* XTENSA_EXTW (1702) - XTENSA_INS_EXTW - extw */ +{ + { 0 } +}}, +{ /* XTENSA_FLOAT_S (1703) - XTENSA_INS_FLOAT_S - float.s $r, $s, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_FLOOR_S (1704) - XTENSA_INS_FLOOR_S - floor.s $r, $s, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_GET_GPIO_IN (1705) - XTENSA_INS_GET_GPIO_IN - get_gpio_in $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ILL (1706) - XTENSA_INS_ILL - ill */ +{ + { 0 } +}}, +{ /* XTENSA_ILL_N (1707) - XTENSA_INS_ILL_N - ill.n */ +{ + { 0 } +}}, +{ /* XTENSA_ISYNC (1708) - XTENSA_INS_ISYNC - isync */ +{ + { 0 } +}}, +{ /* XTENSA_J (1709) - XTENSA_INS_J - j $offset */ +{ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* XTENSA_JX (1710) - XTENSA_INS_JX - jx $s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_L16SI (1711) - XTENSA_INS_L16SI - l16si $t, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m16 */ + { 0 } +}}, +{ /* XTENSA_L16UI (1712) - XTENSA_INS_L16UI - l16ui $t, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m16 */ + { 0 } +}}, +{ /* XTENSA_L32E (1713) - XTENSA_INS_L32E - l32e $t, $s, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_L32I (1714) - XTENSA_INS_L32I - l32i $t, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ + { 0 } +}}, +{ /* XTENSA_L32I_N (1715) - XTENSA_INS_L32I_N - l32i.n $t, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset4m32 */ + { 0 } +}}, +{ /* XTENSA_L32R (1716) - XTENSA_INS_L32R - l32r $t, $label */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* label */ + { 0 } +}}, +{ /* XTENSA_L8UI (1717) - XTENSA_INS_L8UI - l8ui $t, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m8 */ + { 0 } +}}, +{ /* XTENSA_LDDEC (1718) - XTENSA_INS_LDDEC - lddec $w, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_LDINC (1719) - XTENSA_INS_LDINC - ldinc $w, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{{{ /* XTENSA_LEA_ADD (1720) - XTENSA_INS_INVALID - addi $t, $addr */ + 0 +}}}, +{ /* XTENSA_LOOP (1721) - XTENSA_INS_LOOP - loop $s, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_LOOPGTZ (1722) - XTENSA_INS_LOOPGTZ - loopgtz $s, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_LOOPNEZ (1723) - XTENSA_INS_LOOPNEZ - loopnez $s, $target */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* XTENSA_LSI (1724) - XTENSA_INS_LSI - lsi $t, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ + { 0 } +}}, +{ /* XTENSA_LSIP (1725) - XTENSA_INS_LSIP - lsip $t, $s, $off */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ds */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */ + { 0 } +}}, +{ /* XTENSA_LSX (1726) - XTENSA_INS_LSX - lsx $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_LSXP (1727) - XTENSA_INS_LSXP - lsxp $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ds */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MADDN_S (1728) - XTENSA_INS_MADDN_S - maddn.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MADD_S (1729) - XTENSA_INS_MADD_S - madd.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MAX (1730) - XTENSA_INS_MAX - max $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MAXU (1731) - XTENSA_INS_MAXU - maxu $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MEMW (1732) - XTENSA_INS_MEMW - memw */ +{ + { 0 } +}}, +{ /* XTENSA_MIN (1733) - XTENSA_INS_MIN - min $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MINU (1734) - XTENSA_INS_MINU - minu $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MKDADJ_S (1735) - XTENSA_INS_MKDADJ_S - mkdadj.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_MKSADJ_S (1736) - XTENSA_INS_MKSADJ_S - mksadj.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_MOVEQZ (1737) - XTENSA_INS_MOVEQZ - moveqz $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVEQZ_S (1738) - XTENSA_INS_MOVEQZ_S - moveqz.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVF (1739) - XTENSA_INS_MOVF - movf $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVF_S (1740) - XTENSA_INS_MOVF_S - movf.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVGEZ (1741) - XTENSA_INS_MOVGEZ - movgez $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVGEZ_S (1742) - XTENSA_INS_MOVGEZ_S - movgez.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVI (1743) - XTENSA_INS_MOVI - movi $t, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_MOVI_N (1744) - XTENSA_INS_MOVI_N - movi.n $s, $imm7 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm7 */ + { 0 } +}}, +{ /* XTENSA_MOVLTZ (1745) - XTENSA_INS_MOVLTZ - movltz $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVLTZ_S (1746) - XTENSA_INS_MOVLTZ_S - movltz.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVNEZ (1747) - XTENSA_INS_MOVNEZ - movnez $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVNEZ_S (1748) - XTENSA_INS_MOVNEZ_S - movnez.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVSP (1749) - XTENSA_INS_MOVSP - movsp $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_MOVT (1750) - XTENSA_INS_MOVT - movt $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOVT_S (1751) - XTENSA_INS_MOVT_S - movt.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MOV_N (1752) - XTENSA_INS_MOV_N - mov.n $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_MOV_S (1753) - XTENSA_INS_MOV_S - mov.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_MSUB_S (1754) - XTENSA_INS_MSUB_S - msub.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL16S (1755) - XTENSA_INS_MUL16S - mul16s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL16U (1756) - XTENSA_INS_MUL16U - mul16u $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_AA_HH (1757) - XTENSA_INS_MULA_AA_HH - mula.aa.hh $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_AA_HL (1758) - XTENSA_INS_MULA_AA_HL - mula.aa.hl $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_AA_LH (1759) - XTENSA_INS_MULA_AA_LH - mula.aa.lh $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_AA_LL (1760) - XTENSA_INS_MULA_AA_LL - mula.aa.ll $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_AD_HH (1761) - XTENSA_INS_MULA_AD_HH - mula.ad.hh $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_AD_HL (1762) - XTENSA_INS_MULA_AD_HL - mula.ad.hl $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_AD_LH (1763) - XTENSA_INS_MULA_AD_LH - mula.ad.lh $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_AD_LL (1764) - XTENSA_INS_MULA_AD_LL - mula.ad.ll $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_HH (1765) - XTENSA_INS_MULA_DA_HH - mula.da.hh $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_HH_LDDEC (1766) - XTENSA_INS_MULA_DA_HH_LDDEC - mula.da.hh.lddec $w, $s, $x, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_HH_LDINC (1767) - XTENSA_INS_MULA_DA_HH_LDINC - mula.da.hh.ldinc $w, $s, $x, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_HL (1768) - XTENSA_INS_MULA_DA_HL - mula.da.hl $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_HL_LDDEC (1769) - XTENSA_INS_MULA_DA_HL_LDDEC - mula.da.hl.lddec $w, $s, $x, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_HL_LDINC (1770) - XTENSA_INS_MULA_DA_HL_LDINC - mula.da.hl.ldinc $w, $s, $x, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_LH (1771) - XTENSA_INS_MULA_DA_LH - mula.da.lh $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_LH_LDDEC (1772) - XTENSA_INS_MULA_DA_LH_LDDEC - mula.da.lh.lddec $w, $s, $x, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_LH_LDINC (1773) - XTENSA_INS_MULA_DA_LH_LDINC - mula.da.lh.ldinc $w, $s, $x, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_LL (1774) - XTENSA_INS_MULA_DA_LL - mula.da.ll $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_LL_LDDEC (1775) - XTENSA_INS_MULA_DA_LL_LDDEC - mula.da.ll.lddec $w, $s, $x, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DA_LL_LDINC (1776) - XTENSA_INS_MULA_DA_LL_LDINC - mula.da.ll.ldinc $w, $s, $x, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_HH (1777) - XTENSA_INS_MULA_DD_HH - mula.dd.hh $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_HH_LDDEC (1778) - XTENSA_INS_MULA_DD_HH_LDDEC - mula.dd.hh.lddec $w, $s, $x, $y */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_HH_LDINC (1779) - XTENSA_INS_MULA_DD_HH_LDINC - mula.dd.hh.ldinc $w, $s, $x, $y */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_HL (1780) - XTENSA_INS_MULA_DD_HL - mula.dd.hl $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_HL_LDDEC (1781) - XTENSA_INS_MULA_DD_HL_LDDEC - mula.dd.hl.lddec $w, $s, $x, $y */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_HL_LDINC (1782) - XTENSA_INS_MULA_DD_HL_LDINC - mula.dd.hl.ldinc $w, $s, $x, $y */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_LH (1783) - XTENSA_INS_MULA_DD_LH - mula.dd.lh $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_LH_LDDEC (1784) - XTENSA_INS_MULA_DD_LH_LDDEC - mula.dd.lh.lddec $w, $s, $x, $y */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_LH_LDINC (1785) - XTENSA_INS_MULA_DD_LH_LDINC - mula.dd.lh.ldinc $w, $s, $x, $y */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_LL (1786) - XTENSA_INS_MULA_DD_LL - mula.dd.ll $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_LL_LDDEC (1787) - XTENSA_INS_MULA_DD_LL_LDDEC - mula.dd.ll.lddec $w, $s, $x, $y */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULA_DD_LL_LDINC (1788) - XTENSA_INS_MULA_DD_LL_LDINC - mula.dd.ll.ldinc $w, $s, $x, $y */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* w */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULL (1789) - XTENSA_INS_MULL - mull $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULSH (1790) - XTENSA_INS_MULSH - mulsh $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_AA_HH (1791) - XTENSA_INS_MULS_AA_HH - muls.aa.hh $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_AA_HL (1792) - XTENSA_INS_MULS_AA_HL - muls.aa.hl $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_AA_LH (1793) - XTENSA_INS_MULS_AA_LH - muls.aa.lh $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_AA_LL (1794) - XTENSA_INS_MULS_AA_LL - muls.aa.ll $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_AD_HH (1795) - XTENSA_INS_MULS_AD_HH - muls.ad.hh $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULS_AD_HL (1796) - XTENSA_INS_MULS_AD_HL - muls.ad.hl $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULS_AD_LH (1797) - XTENSA_INS_MULS_AD_LH - muls.ad.lh $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULS_AD_LL (1798) - XTENSA_INS_MULS_AD_LL - muls.ad.ll $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULS_DA_HH (1799) - XTENSA_INS_MULS_DA_HH - muls.da.hh $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_DA_HL (1800) - XTENSA_INS_MULS_DA_HL - muls.da.hl $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_DA_LH (1801) - XTENSA_INS_MULS_DA_LH - muls.da.lh $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_DA_LL (1802) - XTENSA_INS_MULS_DA_LL - muls.da.ll $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MULS_DD_HH (1803) - XTENSA_INS_MULS_DD_HH - muls.dd.hh $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULS_DD_HL (1804) - XTENSA_INS_MULS_DD_HL - muls.dd.hl $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULS_DD_LH (1805) - XTENSA_INS_MULS_DD_LH - muls.dd.lh $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULS_DD_LL (1806) - XTENSA_INS_MULS_DD_LL - muls.dd.ll $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MULUH (1807) - XTENSA_INS_MULUH - muluh $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_AA_HH (1808) - XTENSA_INS_MUL_AA_HH - mul.aa.hh $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_AA_HL (1809) - XTENSA_INS_MUL_AA_HL - mul.aa.hl $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_AA_LH (1810) - XTENSA_INS_MUL_AA_LH - mul.aa.lh $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_AA_LL (1811) - XTENSA_INS_MUL_AA_LL - mul.aa.ll $s, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_AD_HH (1812) - XTENSA_INS_MUL_AD_HH - mul.ad.hh $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MUL_AD_HL (1813) - XTENSA_INS_MUL_AD_HL - mul.ad.hl $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MUL_AD_LH (1814) - XTENSA_INS_MUL_AD_LH - mul.ad.lh $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MUL_AD_LL (1815) - XTENSA_INS_MUL_AD_LL - mul.ad.ll $s, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MUL_DA_HH (1816) - XTENSA_INS_MUL_DA_HH - mul.da.hh $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_DA_HL (1817) - XTENSA_INS_MUL_DA_HL - mul.da.hl $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_DA_LH (1818) - XTENSA_INS_MUL_DA_LH - mul.da.lh $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_DA_LL (1819) - XTENSA_INS_MUL_DA_LL - mul.da.ll $x, $t */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_MUL_DD_HH (1820) - XTENSA_INS_MUL_DD_HH - mul.dd.hh $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MUL_DD_HL (1821) - XTENSA_INS_MUL_DD_HL - mul.dd.hl $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MUL_DD_LH (1822) - XTENSA_INS_MUL_DD_LH - mul.dd.lh $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MUL_DD_LL (1823) - XTENSA_INS_MUL_DD_LL - mul.dd.ll $x, $y */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* x */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* y */ + { 0 } +}}, +{ /* XTENSA_MUL_S (1824) - XTENSA_INS_MUL_S - mul.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_NEG (1825) - XTENSA_INS_NEG - neg $r, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_NEG_S (1826) - XTENSA_INS_NEG_S - neg.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_NEXP01_S (1827) - XTENSA_INS_NEXP01_S - nexp01.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_NOP (1828) - XTENSA_INS_NOP - nop */ +{ + { 0 } +}}, +{ /* XTENSA_NSA (1829) - XTENSA_INS_NSA - nsa $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_NSAU (1830) - XTENSA_INS_NSAU - nsau $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_OEQ_S (1831) - XTENSA_INS_OEQ_S - oeq.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_OLE_S (1832) - XTENSA_INS_OLE_S - ole.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_OLT_S (1833) - XTENSA_INS_OLT_S - olt.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_OR (1834) - XTENSA_INS_OR - or $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ORB (1835) - XTENSA_INS_ORB - orb $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ORBC (1836) - XTENSA_INS_ORBC - orbc $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_QUOS (1837) - XTENSA_INS_QUOS - quos $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_QUOU (1838) - XTENSA_INS_QUOU - quou $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_RECIP0_S (1839) - XTENSA_INS_RECIP0_S - recip0.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_REMS (1840) - XTENSA_INS_REMS - rems $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_REMU (1841) - XTENSA_INS_REMU - remu $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_RER (1842) - XTENSA_INS_RER - rer $t, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_RET (1843) - XTENSA_INS_RET - ret */ +{ + { 0 } +}}, +{ /* XTENSA_RETW (1844) - XTENSA_INS_RETW - retw */ +{ + { 0 } +}}, +{ /* XTENSA_RETW_N (1845) - XTENSA_INS_RETW_N - retw.n */ +{ + { 0 } +}}, +{ /* XTENSA_RET_N (1846) - XTENSA_INS_RET_N - ret.n */ +{ + { 0 } +}}, +{ /* XTENSA_RFDE (1847) - XTENSA_INS_RFDE - rfde */ +{ + { 0 } +}}, +{ /* XTENSA_RFE (1848) - XTENSA_INS_RFE - rfe */ +{ + { 0 } +}}, +{ /* XTENSA_RFI (1849) - XTENSA_INS_RFI - rfi $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_RFR (1850) - XTENSA_INS_RFR - rfr $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_RFWO (1851) - XTENSA_INS_RFWO - rfwo */ +{ + { 0 } +}}, +{ /* XTENSA_RFWU (1852) - XTENSA_INS_RFWU - rfwu */ +{ + { 0 } +}}, +{ /* XTENSA_ROTW (1853) - XTENSA_INS_ROTW - rotw $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_ROUND_S (1854) - XTENSA_INS_ROUND_S - round.s $r, $s, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_RSIL (1855) - XTENSA_INS_RSIL - rsil $t, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_RSQRT0_S (1856) - XTENSA_INS_RSQRT0_S - rsqrt0.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_RSR (1857) - XTENSA_INS_RSR - rsr $t, $sr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sr */ + { 0 } +}}, +{ /* XTENSA_RSYNC (1858) - XTENSA_INS_RSYNC - rsync */ +{ + { 0 } +}}, +{ /* XTENSA_RUR (1859) - XTENSA_INS_RUR - rur $r, $ur */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ur */ + { 0 } +}}, +{ /* XTENSA_RUR_ACCX_0 (1860) - XTENSA_INS_RUR_ACCX_0 - rur.accx_0 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_ACCX_1 (1861) - XTENSA_INS_RUR_ACCX_1 - rur.accx_1 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_BITHEAD (1862) - XTENSA_INS_RUR_AE_BITHEAD - rur.ae_bithead $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_BITPTR (1863) - XTENSA_INS_RUR_AE_BITPTR - rur.ae_bitptr $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_BITSUSED (1864) - XTENSA_INS_RUR_AE_BITSUSED - rur.ae_bitsused $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_CBEGIN0 (1865) - XTENSA_INS_RUR_AE_CBEGIN0 - rur.ae_cbegin0 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_CEND0 (1866) - XTENSA_INS_RUR_AE_CEND0 - rur.ae_cend0 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_CWRAP (1867) - XTENSA_INS_RUR_AE_CWRAP - rur.ae_cwrap $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_CW_SD_NO (1868) - XTENSA_INS_RUR_AE_CW_SD_NO - rur.ae_cw_sd_no $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_FIRST_TS (1869) - XTENSA_INS_RUR_AE_FIRST_TS - rur.ae_first_ts $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_NEXTOFFSET (1870) - XTENSA_INS_RUR_AE_NEXTOFFSET - rur.ae_nextoffset $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_OVERFLOW (1871) - XTENSA_INS_RUR_AE_OVERFLOW - rur.ae_overflow $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_OVF_SAR (1872) - XTENSA_INS_RUR_AE_OVF_SAR - rur.ae_ovf_sar $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_SAR (1873) - XTENSA_INS_RUR_AE_SAR - rur.ae_sar $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_SEARCHDONE (1874) - XTENSA_INS_RUR_AE_SEARCHDONE - rur.ae_searchdone $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_TABLESIZE (1875) - XTENSA_INS_RUR_AE_TABLESIZE - rur.ae_tablesize $art */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ + { 0 } +}}, +{ /* XTENSA_RUR_AE_TS_FTS_BU_BP (1876) - XTENSA_INS_RUR_AE_TS_FTS_BU_BP - rur.ae_ts_fts_bu_bp $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_FFT_BIT_WIDTH (1877) - XTENSA_INS_RUR_FFT_BIT_WIDTH - rur.fft_bit_width $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_GPIO_OUT (1878) - XTENSA_INS_RUR_GPIO_OUT - rur.gpio_out $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_H_0 (1879) - XTENSA_INS_RUR_QACC_H_0 - rur.qacc_h_0 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_H_1 (1880) - XTENSA_INS_RUR_QACC_H_1 - rur.qacc_h_1 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_H_2 (1881) - XTENSA_INS_RUR_QACC_H_2 - rur.qacc_h_2 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_H_3 (1882) - XTENSA_INS_RUR_QACC_H_3 - rur.qacc_h_3 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_H_4 (1883) - XTENSA_INS_RUR_QACC_H_4 - rur.qacc_h_4 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_L_0 (1884) - XTENSA_INS_RUR_QACC_L_0 - rur.qacc_l_0 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_L_1 (1885) - XTENSA_INS_RUR_QACC_L_1 - rur.qacc_l_1 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_L_2 (1886) - XTENSA_INS_RUR_QACC_L_2 - rur.qacc_l_2 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_L_3 (1887) - XTENSA_INS_RUR_QACC_L_3 - rur.qacc_l_3 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_QACC_L_4 (1888) - XTENSA_INS_RUR_QACC_L_4 - rur.qacc_l_4 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_SAR_BYTE (1889) - XTENSA_INS_RUR_SAR_BYTE - rur.sar_byte $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_UA_STATE_0 (1890) - XTENSA_INS_RUR_UA_STATE_0 - rur.ua_state_0 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_UA_STATE_1 (1891) - XTENSA_INS_RUR_UA_STATE_1 - rur.ua_state_1 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_UA_STATE_2 (1892) - XTENSA_INS_RUR_UA_STATE_2 - rur.ua_state_2 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_RUR_UA_STATE_3 (1893) - XTENSA_INS_RUR_UA_STATE_3 - rur.ua_state_3 $arr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* arr */ + { 0 } +}}, +{ /* XTENSA_S16I (1894) - XTENSA_INS_S16I - s16i $t, $addr */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m16 */ { 0 } }}, -{ /* XTENSA_ADD (272) - XTENSA_INS_ADD - add $r, $s, $t */ +{ /* XTENSA_S32C1I (1895) - XTENSA_INS_S32C1I - s32c1i $t, $addr */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* a */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ { 0 } }}, -{ /* XTENSA_ADDI (273) - XTENSA_INS_ADDI - addi $t, $s, $imm8 */ +{ /* XTENSA_S32E (1896) - XTENSA_INS_S32E - s32e $t, $s, $imm */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ { 0 } }}, -{ /* XTENSA_ADDMI (274) - XTENSA_INS_ADDMI - addmi $t, $s, $imm_sh8 */ +{ /* XTENSA_S32I (1897) - XTENSA_INS_S32I - s32i $t, $addr */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm_sh8 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ { 0 } }}, -{ /* XTENSA_ADDX2 (275) - XTENSA_INS_ADDX2 - addx2 $r, $s, $t */ +{ /* XTENSA_S32I_N (1898) - XTENSA_INS_S32I_N - s32i.n $t, $addr */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset4m32 */ { 0 } }}, -{ /* XTENSA_ADDX4 (276) - XTENSA_INS_ADDX4 - addx4 $r, $s, $t */ +{ /* XTENSA_S8I (1899) - XTENSA_INS_S8I - s8i $t, $addr */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m8 */ + { 0 } +}}, +{ /* XTENSA_SET_BIT_GPIO_OUT (1900) - XTENSA_INS_SET_BIT_GPIO_OUT - set_bit_gpio_out $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ { 0 } }}, -{ /* XTENSA_ADDX8 (277) - XTENSA_INS_ADDX8 - addx8 $r, $s, $t */ +{ /* XTENSA_SEXT (1901) - XTENSA_INS_SEXT - sext $r, $s, $imm */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA_SIMCALL (1902) - XTENSA_INS_SIMCALL - simcall */ +{ { 0 } }}, -{ /* XTENSA_AND (278) - XTENSA_INS_AND - and $r, $s, $t */ +{ /* XTENSA_SLL (1903) - XTENSA_INS_SLL - sll $r, $s */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_BALL (279) - XTENSA_INS_BALL - ball $s, $t, $target */ +{ /* XTENSA_SLLI (1904) - XTENSA_INS_SLLI - slli $r, $s, $sa */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* XTENSA_SQRT0_S (1905) - XTENSA_INS_SQRT0_S - sqrt0.s $r, $s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_SRA (1906) - XTENSA_INS_SRA - sra $r, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BANY (280) - XTENSA_INS_BANY - bany $s, $t, $target */ +{ /* XTENSA_SRAI (1907) - XTENSA_INS_SRAI - srai $r, $t, $sa */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ { 0 } }}, -{ /* XTENSA_BBC (281) - XTENSA_INS_BBC - bbc $s, $t, $target */ +{ /* XTENSA_SRC (1908) - XTENSA_INS_SRC - src $r, $s, $t */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BBCI (282) - XTENSA_INS_BBCI - bbci $s, $imm, $target */ +{ /* XTENSA_SRL (1909) - XTENSA_INS_SRL - srl $r, $t */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_BBS (283) - XTENSA_INS_BBS - bbs $s, $t, $target */ +{ /* XTENSA_SRLI (1910) - XTENSA_INS_SRLI - srli $r, $t, $sa */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ { 0 } }}, -{ /* XTENSA_BBSI (284) - XTENSA_INS_BBSI - bbsi $s, $imm, $target */ +{ /* XTENSA_SSA8L (1911) - XTENSA_INS_SSA8L - ssa8l $s */ { { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_SSAI (1912) - XTENSA_INS_SSAI - ssai $imm */ +{ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BEQ (285) - XTENSA_INS_BEQ - beq $s, $t, $target */ +{ /* XTENSA_SSI (1913) - XTENSA_INS_SSI - ssi $t, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ + { 0 } +}}, +{ /* XTENSA_SSIP (1914) - XTENSA_INS_SSIP - ssip $t, $s, $off */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ds */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off */ { 0 } }}, -{ /* XTENSA_BEQI (286) - XTENSA_INS_BEQI - beqi $s, $imm, $target */ +{ /* XTENSA_SSL (1915) - XTENSA_INS_SSL - ssl $s */ { { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BEQZ (287) - XTENSA_INS_BEQZ - beqz $s, $target */ +{ /* XTENSA_SSR (1916) - XTENSA_INS_SSR - ssr $s */ { { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BGE (288) - XTENSA_INS_BGE - bge $s, $t, $target */ +{ /* XTENSA_SSX (1917) - XTENSA_INS_SSX - ssx $r, $s, $t */ { + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BGEI (289) - XTENSA_INS_BGEI - bgei $s, $imm, $target */ +{ /* XTENSA_SSXP (1918) - XTENSA_INS_SSXP - ssxp $r, $s, $t */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ds */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_BGEU (290) - XTENSA_INS_BGEU - bgeu $s, $t, $target */ +{ /* XTENSA_SUB (1919) - XTENSA_INS_SUB - sub $r, $s, $t */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BGEUI (291) - XTENSA_INS_BGEUI - bgeui $s, $imm, $target */ +{ /* XTENSA_SUBX2 (1920) - XTENSA_INS_SUBX2 - subx2 $r, $s, $t */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_BGEZ (292) - XTENSA_INS_BGEZ - bgez $s, $target */ +{ /* XTENSA_SUBX4 (1921) - XTENSA_INS_SUBX4 - subx4 $r, $s, $t */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_BLT (293) - XTENSA_INS_BLT - blt $s, $t, $target */ +{ /* XTENSA_SUBX8 (1922) - XTENSA_INS_SUBX8 - subx8 $r, $s, $t */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BLTI (294) - XTENSA_INS_BLTI - blti $s, $imm, $target */ +{ /* XTENSA_SUB_S (1923) - XTENSA_INS_SUB_S - sub.s $r, $s, $t */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_SYSCALL (1924) - XTENSA_INS_SYSCALL - syscall */ +{ + { 0 } +}}, +{ /* XTENSA_TRUNC_S (1925) - XTENSA_INS_TRUNC_S - trunc.s $r, $s, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BLTU (295) - XTENSA_INS_BLTU - bltu $s, $t, $target */ +{ /* XTENSA_UEQ_S (1926) - XTENSA_INS_UEQ_S - ueq.s $r, $s, $t */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_BLTUI (296) - XTENSA_INS_BLTUI - bltui $s, $imm, $target */ +{ /* XTENSA_UFLOAT_S (1927) - XTENSA_INS_UFLOAT_S - ufloat.s $r, $s, $imm */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BLTZ (297) - XTENSA_INS_BLTZ - bltz $s, $target */ +{ /* XTENSA_ULE_S (1928) - XTENSA_INS_ULE_S - ule.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_ULT_S (1929) - XTENSA_INS_ULT_S - ult.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_UMUL_AA_HH (1930) - XTENSA_INS_UMUL_AA_HH - umul.aa.hh $s, $t */ { { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_BNALL (298) - XTENSA_INS_BNALL - bnall $s, $t, $target */ +{ /* XTENSA_UMUL_AA_HL (1931) - XTENSA_INS_UMUL_AA_HL - umul.aa.hl $s, $t */ { { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BNE (299) - XTENSA_INS_BNE - bne $s, $t, $target */ +{ /* XTENSA_UMUL_AA_LH (1932) - XTENSA_INS_UMUL_AA_LH - umul.aa.lh $s, $t */ { { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BNEI (300) - XTENSA_INS_BNEI - bnei $s, $imm, $target */ +{ /* XTENSA_UMUL_AA_LL (1933) - XTENSA_INS_UMUL_AA_LL - umul.aa.ll $s, $t */ { { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_UN_S (1934) - XTENSA_INS_UN_S - un.s $r, $s, $t */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_UTRUNC_S (1935) - XTENSA_INS_UTRUNC_S - utrunc.s $r, $s, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ { 0 } }}, -{ /* XTENSA_BNEZ (301) - XTENSA_INS_BNEZ - bnez $s, $target */ +{ /* XTENSA_WAITI (1936) - XTENSA_INS_WAITI - waiti $imm */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ { 0 } }}, -{ /* XTENSA_BNONE (302) - XTENSA_INS_BNONE - bnone $s, $t, $target */ +{ /* XTENSA_WDTLB (1937) - XTENSA_INS_WDTLB - wdtlb $t, $s */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { 0 } +}}, +{ /* XTENSA_WER (1938) - XTENSA_INS_WER - wer $t, $s */ +{ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { 0 } }}, -{ /* XTENSA_CALL0 (303) - XTENSA_INS_CALL0 - call0 $offset */ +{ /* XTENSA_WFR (1939) - XTENSA_INS_WFR - wfr $r, $s */ { - { CS_OP_INVALID | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { 0 } }}, -{ /* XTENSA_CALLX0 (304) - XTENSA_INS_CALLX0 - callx0 $s */ +{ /* XTENSA_WITLB (1940) - XTENSA_INS_WITLB - witlb $t, $s */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { 0 } }}, -{ /* XTENSA_DSYNC (305) - XTENSA_INS_DSYNC - dsync */ +{ /* XTENSA_WR_MASK_GPIO_OUT (1941) - XTENSA_INS_WR_MASK_GPIO_OUT - wr_mask_gpio_out $s, $t */ { + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_ESYNC (306) - XTENSA_INS_ESYNC - esync */ +{ /* XTENSA_WSR (1942) - XTENSA_INS_WSR - wsr $t, $sr */ { + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_EXTUI (307) - XTENSA_INS_EXTUI - extui $r, $t, $imm1, $imm2 */ +{ /* XTENSA_WUR (1943) - XTENSA_INS_WUR - wur $t, $ur */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ur */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm1 */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ { 0 } }}, -{ /* XTENSA_EXTW (308) - XTENSA_INS_EXTW - extw */ +{ /* XTENSA_WUR_ACCX_0 (1944) - XTENSA_INS_WUR_ACCX_0 - wur.accx_0 $art */ { + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_ISYNC (309) - XTENSA_INS_ISYNC - isync */ +{ /* XTENSA_WUR_ACCX_1 (1945) - XTENSA_INS_WUR_ACCX_1 - wur.accx_1 $art */ { + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_J (310) - XTENSA_INS_J - j $offset */ +{ /* XTENSA_WUR_AE_BITHEAD (1946) - XTENSA_INS_WUR_AE_BITHEAD - wur.ae_bithead $art */ { - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_JX (311) - XTENSA_INS_JX - jx $s */ +{ /* XTENSA_WUR_AE_BITPTR (1947) - XTENSA_INS_WUR_AE_BITPTR - wur.ae_bitptr $art */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_L16SI (312) - XTENSA_INS_L16SI - l16si $t, $addr */ +{ /* XTENSA_WUR_AE_BITSUSED (1948) - XTENSA_INS_WUR_AE_BITSUSED - wur.ae_bitsused $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ - { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_L16UI (313) - XTENSA_INS_L16UI - l16ui $t, $addr */ +{ /* XTENSA_WUR_AE_CBEGIN0 (1949) - XTENSA_INS_WUR_AE_CBEGIN0 - wur.ae_cbegin0 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ - { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_L32I (314) - XTENSA_INS_L32I - l32i $t, $addr */ +{ /* XTENSA_WUR_AE_CEND0 (1950) - XTENSA_INS_WUR_AE_CEND0 - wur.ae_cend0 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ - { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_L32R (315) - XTENSA_INS_L32R - l32r $t, $label */ +{ /* XTENSA_WUR_AE_CWRAP (1951) - XTENSA_INS_WUR_AE_CWRAP - wur.ae_cwrap $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_L8UI (316) - XTENSA_INS_L8UI - l8ui $t, $addr */ +{ /* XTENSA_WUR_AE_CW_SD_NO (1952) - XTENSA_INS_WUR_AE_CW_SD_NO - wur.ae_cw_sd_no $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ - { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m8 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_MEMW (317) - XTENSA_INS_MEMW - memw */ +{ /* XTENSA_WUR_AE_FIRST_TS (1953) - XTENSA_INS_WUR_AE_FIRST_TS - wur.ae_first_ts $art */ { + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_MOVEQZ (318) - XTENSA_INS_MOVEQZ - moveqz $r, $s, $t */ +{ /* XTENSA_WUR_AE_NEXTOFFSET (1954) - XTENSA_INS_WUR_AE_NEXTOFFSET - wur.ae_nextoffset $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_MOVGEZ (319) - XTENSA_INS_MOVGEZ - movgez $r, $s, $t */ +{ /* XTENSA_WUR_AE_OVERFLOW (1955) - XTENSA_INS_WUR_AE_OVERFLOW - wur.ae_overflow $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_MOVI (320) - XTENSA_INS_MOVI - movi $t, $imm */ +{ /* XTENSA_WUR_AE_OVF_SAR (1956) - XTENSA_INS_WUR_AE_OVF_SAR - wur.ae_ovf_sar $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_MOVLTZ (321) - XTENSA_INS_MOVLTZ - movltz $r, $s, $t */ +{ /* XTENSA_WUR_AE_SAR (1957) - XTENSA_INS_WUR_AE_SAR - wur.ae_sar $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_MOVNEZ (322) - XTENSA_INS_MOVNEZ - movnez $r, $s, $t */ +{ /* XTENSA_WUR_AE_SEARCHDONE (1958) - XTENSA_INS_WUR_AE_SEARCHDONE - wur.ae_searchdone $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_NEG (323) - XTENSA_INS_NEG - neg $r, $t */ +{ /* XTENSA_WUR_AE_TABLESIZE (1959) - XTENSA_INS_WUR_AE_TABLESIZE - wur.ae_tablesize $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_NOP (324) - XTENSA_INS_NOP - nop */ +{ /* XTENSA_WUR_AE_TS_FTS_BU_BP (1960) - XTENSA_INS_WUR_AE_TS_FTS_BU_BP - wur.ae_ts_fts_bu_bp $art */ { + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_OR (325) - XTENSA_INS_OR - or $r, $s, $t */ +{ /* XTENSA_WUR_FCR (1961) - XTENSA_INS_WUR_FCR - wur.fcr $t */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_RET (326) - XTENSA_INS_RET - ret */ +{ /* XTENSA_WUR_FFT_BIT_WIDTH (1962) - XTENSA_INS_WUR_FFT_BIT_WIDTH - wur.fft_bit_width $art */ { + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_RSR (327) - XTENSA_INS_RSR - rsr $t, $sr */ +{ /* XTENSA_WUR_FSR (1963) - XTENSA_INS_WUR_FSR - wur.fsr $t */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_RSYNC (328) - XTENSA_INS_RSYNC - rsync */ +{ /* XTENSA_WUR_GPIO_OUT (1964) - XTENSA_INS_WUR_GPIO_OUT - wur.gpio_out $art */ { + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_S16I (329) - XTENSA_INS_S16I - s16i $t, $addr */ +{ /* XTENSA_WUR_QACC_H_0 (1965) - XTENSA_INS_WUR_QACC_H_0 - wur.qacc_h_0 $art */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ - { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_S32I (330) - XTENSA_INS_S32I - s32i $t, $addr */ +{ /* XTENSA_WUR_QACC_H_1 (1966) - XTENSA_INS_WUR_QACC_H_1 - wur.qacc_h_1 $art */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ - { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_S8I (331) - XTENSA_INS_S8I - s8i $t, $addr */ +{ /* XTENSA_WUR_QACC_H_2 (1967) - XTENSA_INS_WUR_QACC_H_2 - wur.qacc_h_2 $art */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ - { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m8 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SLL (332) - XTENSA_INS_SLL - sll $r, $s */ +{ /* XTENSA_WUR_QACC_H_3 (1968) - XTENSA_INS_WUR_QACC_H_3 - wur.qacc_h_3 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SLLI (333) - XTENSA_INS_SLLI - slli $r, $s, $sa */ +{ /* XTENSA_WUR_QACC_H_4 (1969) - XTENSA_INS_WUR_QACC_H_4 - wur.qacc_h_4 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SRA (334) - XTENSA_INS_SRA - sra $r, $t */ +{ /* XTENSA_WUR_QACC_L_0 (1970) - XTENSA_INS_WUR_QACC_L_0 - wur.qacc_l_0 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SRAI (335) - XTENSA_INS_SRAI - srai $r, $t, $sa */ +{ /* XTENSA_WUR_QACC_L_1 (1971) - XTENSA_INS_WUR_QACC_L_1 - wur.qacc_l_1 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SRC (336) - XTENSA_INS_SRC - src $r, $s, $t */ +{ /* XTENSA_WUR_QACC_L_2 (1972) - XTENSA_INS_WUR_QACC_L_2 - wur.qacc_l_2 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SRL (337) - XTENSA_INS_SRL - srl $r, $t */ +{ /* XTENSA_WUR_QACC_L_3 (1973) - XTENSA_INS_WUR_QACC_L_3 - wur.qacc_l_3 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SRLI (338) - XTENSA_INS_SRLI - srli $r, $t, $sa */ +{ /* XTENSA_WUR_QACC_L_4 (1974) - XTENSA_INS_WUR_QACC_L_4 - wur.qacc_l_4 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SSA8L (339) - XTENSA_INS_SSA8L - ssa8l $s */ +{ /* XTENSA_WUR_SAR_BYTE (1975) - XTENSA_INS_WUR_SAR_BYTE - wur.sar_byte $art */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SSAI (340) - XTENSA_INS_SSAI - ssai $imm */ +{ /* XTENSA_WUR_UA_STATE_0 (1976) - XTENSA_INS_WUR_UA_STATE_0 - wur.ua_state_0 $art */ { - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SSL (341) - XTENSA_INS_SSL - ssl $s */ +{ /* XTENSA_WUR_UA_STATE_1 (1977) - XTENSA_INS_WUR_UA_STATE_1 - wur.ua_state_1 $art */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SSR (342) - XTENSA_INS_SSR - ssr $s */ +{ /* XTENSA_WUR_UA_STATE_2 (1978) - XTENSA_INS_WUR_UA_STATE_2 - wur.ua_state_2 $art */ { - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SUB (343) - XTENSA_INS_SUB - sub $r, $s, $t */ +{ /* XTENSA_WUR_UA_STATE_3 (1979) - XTENSA_INS_WUR_UA_STATE_3 - wur.ua_state_3 $art */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* art */ { 0 } }}, -{ /* XTENSA_SUBX2 (344) - XTENSA_INS_SUBX2 - subx2 $r, $s, $t */ +{ /* XTENSA_XOR (1980) - XTENSA_INS_XOR - xor $r, $s, $t */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ { 0 } }}, -{ /* XTENSA_SUBX4 (345) - XTENSA_INS_SUBX4 - subx4 $r, $s, $t */ +{ /* XTENSA_XORB (1981) - XTENSA_INS_XORB - xorb $r, $s, $t */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* r */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* s */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v1i1, CS_DATA_TYPE_LAST } }, /* t */ + { 0 } +}}, +{ /* XTENSA_XSR (1982) - XTENSA_INS_XSR - xsr $t, $sr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ard */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* srd */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sr */ { 0 } }}, -{ /* XTENSA_SUBX8 (346) - XTENSA_INS_SUBX8 - subx8 $r, $s, $t */ +{ /* XTENSA__L32I (1983) - XTENSA_INS__L32I - _l32i $t, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ + { 0 } +}}, +{ /* XTENSA__L32I_N (1984) - XTENSA_INS__L32I_N - _l32i.n $t, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset4m32 */ + { 0 } +}}, +{ /* XTENSA__MOVI (1985) - XTENSA_INS__MOVI - _movi $t, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* XTENSA__S32I (1986) - XTENSA_INS__S32I - _s32i $t, $addr */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset8m32 */ { 0 } }}, -{ /* XTENSA_WSR (347) - XTENSA_INS_WSR - wsr $t, $sr */ +{ /* XTENSA__S32I_N (1987) - XTENSA_INS__S32I_N - _s32i.n $t, $addr */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sr */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - AR */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - offset4m32 */ { 0 } }}, -{ /* XTENSA_XOR (348) - XTENSA_INS_XOR - xor $r, $s, $t */ +{ /* XTENSA__SLLI (1988) - XTENSA_INS__SLLI - _slli $r, $s, $sa */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ { 0 } }}, -{ /* XTENSA_XSR (349) - XTENSA_INS_XSR - xsr $t, $sr */ +{ /* XTENSA__SRLI (1989) - XTENSA_INS__SRLI - _srli $r, $t, $sa */ { - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ard */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* srd */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* t */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sr */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* XTENSA_mv_QR (1990) - XTENSA_INS_MV_QR - mv.qr $a, $b */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* a */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_LAST } }, /* b */ { 0 } }}, diff --git a/arch/Xtensa/XtensaGenCSOpGroup.inc b/arch/Xtensa/XtensaGenCSOpGroup.inc index a39edcaae4..03e9cca116 100644 --- a/arch/Xtensa/XtensaGenCSOpGroup.inc +++ b/arch/Xtensa/XtensaGenCSOpGroup.inc @@ -11,18 +11,47 @@ /* Capstone's LLVM TableGen Backends: */ /* https://github.com/capstone-engine/llvm-capstone */ - XTENSA_OP_GROUP_OPERAND = 0, - XTENSA_OP_GROUP_IMM8_ASMOPERAND = 1, - XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND = 2, - XTENSA_OP_GROUP_BRANCHTARGET = 3, - XTENSA_OP_GROUP_UIMM5_ASMOPERAND = 4, - XTENSA_OP_GROUP_B4CONST_ASMOPERAND = 5, - XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND = 6, - XTENSA_OP_GROUP_CALLOPERAND = 7, - XTENSA_OP_GROUP_IMM1_16_ASMOPERAND = 8, - XTENSA_OP_GROUP_JUMPTARGET = 9, - XTENSA_OP_GROUP_MEMOPERAND = 10, - XTENSA_OP_GROUP_L32RTARGET = 11, - XTENSA_OP_GROUP_IMM12M_ASMOPERAND = 12, - XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND = 13, - XTENSA_OP_GROUP_UIMM4_ASMOPERAND = 14, + Xtensa_OP_GROUP_Operand = 0, + Xtensa_OP_GROUP_BranchTarget = 1, + Xtensa_OP_GROUP_Imm8_AsmOperand = 2, + Xtensa_OP_GROUP_Select_4_AsmOperand = 3, + Xtensa_OP_GROUP_Select_2_AsmOperand = 4, + Xtensa_OP_GROUP_Select_8_AsmOperand = 5, + Xtensa_OP_GROUP_Offset_16_16_AsmOperand = 6, + Xtensa_OP_GROUP_Offset_256_8_AsmOperand = 7, + Xtensa_OP_GROUP_Offset_256_16_AsmOperand = 8, + Xtensa_OP_GROUP_Offset_256_4_AsmOperand = 9, + Xtensa_OP_GROUP_Select_16_AsmOperand = 10, + Xtensa_OP_GROUP_Offset_128_2_AsmOperand = 11, + Xtensa_OP_GROUP_Offset_128_1_AsmOperand = 12, + Xtensa_OP_GROUP_Offset_64_16_AsmOperand = 13, + Xtensa_OP_GROUP_MemOperand = 14, + Xtensa_OP_GROUP_Imm1n_15_AsmOperand = 15, + Xtensa_OP_GROUP_Imm8_sh8_AsmOperand = 16, + Xtensa_OP_GROUP_Imm1_16_AsmOperand = 17, + Xtensa_OP_GROUP_ImmOperand_minus16_14_2 = 18, + Xtensa_OP_GROUP_ImmOperand_minus32_28_4 = 19, + Xtensa_OP_GROUP_ImmOperand_minus64_56_8 = 20, + Xtensa_OP_GROUP_ImmOperand_0_56_8 = 21, + Xtensa_OP_GROUP_ImmOperand_minus16_47_1 = 22, + Xtensa_OP_GROUP_ImmOperand_0_3_1 = 23, + Xtensa_OP_GROUP_Uimm4_AsmOperand = 24, + Xtensa_OP_GROUP_Imm7_22_AsmOperand = 25, + Xtensa_OP_GROUP_Uimm5_AsmOperand = 26, + Xtensa_OP_GROUP_ImmOperand_0_63_1 = 27, + Xtensa_OP_GROUP_B4const_AsmOperand = 28, + Xtensa_OP_GROUP_B4constu_AsmOperand = 29, + Xtensa_OP_GROUP_CallOperand = 30, + Xtensa_OP_GROUP_Select_256_AsmOperand = 31, + Xtensa_OP_GROUP_Entry_Imm12_AsmOperand = 32, + Xtensa_OP_GROUP_JumpTarget = 33, + Xtensa_OP_GROUP_Imm64n_4n_AsmOperand = 34, + Xtensa_OP_GROUP_L32RTarget = 35, + Xtensa_OP_GROUP_LoopTarget = 36, + Xtensa_OP_GROUP_Offset8m32_AsmOperand = 37, + Xtensa_OP_GROUP_Imm12m_AsmOperand = 38, + Xtensa_OP_GROUP_Imm32n_95_AsmOperand = 39, + Xtensa_OP_GROUP_Imm8n_7_AsmOperand = 40, + Xtensa_OP_GROUP_Shimm0_31_AsmOperand = 41, + Xtensa_OP_GROUP_Imm12_AsmOperand = 42, + Xtensa_OP_GROUP_Shimm1_31_AsmOperand = 43, diff --git a/arch/Xtensa/XtensaGenDisassemblerTables.inc b/arch/Xtensa/XtensaGenDisassemblerTables.inc index e3f1de354d..b88fe08bab 100644 --- a/arch/Xtensa/XtensaGenDisassemblerTables.inc +++ b/arch/Xtensa/XtensaGenDisassemblerTables.inc @@ -12,6 +12,7 @@ /* https://github.com/capstone-engine/llvm-capstone */ #include "../../MCInst.h" +#include "../../cs_priv.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. @@ -31,274 +32,7065 @@ static bool Check(DecodeStatus *Out, const DecodeStatus In) { return *Out != MCDisassembler_Fail; } +static const uint8_t DecoderTable16[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 17 +/* 8 */ MCD_OPC_CheckPredicate, 0, 163, 0, 0, // Skip to: 176 +/* 13 */ MCD_OPC_Decode, 179, 13, 0, // Opcode: L32I_N +/* 17 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 31 +/* 22 */ MCD_OPC_CheckPredicate, 0, 149, 0, 0, // Skip to: 176 +/* 27 */ MCD_OPC_Decode, 234, 14, 0, // Opcode: S32I_N +/* 31 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 45 +/* 36 */ MCD_OPC_CheckPredicate, 0, 135, 0, 0, // Skip to: 176 +/* 41 */ MCD_OPC_Decode, 208, 4, 1, // Opcode: ADD_N +/* 45 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 59 +/* 50 */ MCD_OPC_CheckPredicate, 0, 121, 0, 0, // Skip to: 176 +/* 55 */ MCD_OPC_Decode, 203, 4, 2, // Opcode: ADDI_N +/* 59 */ MCD_OPC_FilterValue, 12, 40, 0, 0, // Skip to: 104 +/* 64 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 67 */ MCD_OPC_FilterValue, 0, 104, 0, 0, // Skip to: 176 +/* 72 */ MCD_OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 95 +/* 77 */ MCD_OPC_CheckField, 12, 4, 15, 11, 0, 0, // Skip to: 95 +/* 84 */ MCD_OPC_CheckField, 4, 3, 2, 4, 0, 0, // Skip to: 95 +/* 91 */ MCD_OPC_Decode, 184, 11, 3, // Opcode: BREAK_N +/* 95 */ MCD_OPC_CheckPredicate, 0, 76, 0, 0, // Skip to: 176 +/* 100 */ MCD_OPC_Decode, 208, 13, 4, // Opcode: MOVI_N +/* 104 */ MCD_OPC_FilterValue, 13, 67, 0, 0, // Skip to: 176 +/* 109 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 112 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 126 +/* 117 */ MCD_OPC_CheckPredicate, 0, 54, 0, 0, // Skip to: 176 +/* 122 */ MCD_OPC_Decode, 216, 13, 5, // Opcode: MOV_N +/* 126 */ MCD_OPC_FilterValue, 15, 45, 0, 0, // Skip to: 176 +/* 131 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... +/* 134 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 148 +/* 139 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 176 +/* 144 */ MCD_OPC_Decode, 182, 14, 6, // Opcode: RET_N +/* 148 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 162 +/* 153 */ MCD_OPC_CheckPredicate, 2, 18, 0, 0, // Skip to: 176 +/* 158 */ MCD_OPC_Decode, 181, 14, 6, // Opcode: RETW_N +/* 162 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 176 +/* 167 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 176 +/* 172 */ MCD_OPC_Decode, 171, 13, 6, // Opcode: ILL_N +/* 176 */ MCD_OPC_Fail, + 0 +}; + static const uint8_t DecoderTable24[] = { /* 0 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3 */ MCD_OPC_FilterValue, 0, 11, 3, 0, // Skip to: 787 +/* 3 */ MCD_OPC_FilterValue, 0, 112, 10, 0, // Skip to: 2680 /* 8 */ MCD_OPC_ExtractField, 17, 3, // Inst{19-17} ... -/* 11 */ MCD_OPC_FilterValue, 0, 146, 2, 0, // Skip to: 674 +/* 11 */ MCD_OPC_FilterValue, 0, 77, 4, 0, // Skip to: 1117 /* 16 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 19 */ MCD_OPC_FilterValue, 0, 198, 0, 0, // Skip to: 222 +/* 19 */ MCD_OPC_FilterValue, 0, 223, 1, 0, // Skip to: 503 /* 24 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 27 */ MCD_OPC_FilterValue, 0, 181, 0, 0, // Skip to: 213 +/* 27 */ MCD_OPC_FilterValue, 0, 206, 1, 0, // Skip to: 494 /* 32 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 35 */ MCD_OPC_FilterValue, 0, 164, 0, 0, // Skip to: 204 -/* 40 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 43 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 59 -/* 48 */ MCD_OPC_CheckField, 8, 8, 32, 144, 4, 0, // Skip to: 1223 -/* 55 */ MCD_OPC_Decode, 181, 2, 0, // Opcode: ISYNC -/* 59 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 75 -/* 64 */ MCD_OPC_CheckField, 8, 8, 32, 128, 4, 0, // Skip to: 1223 -/* 71 */ MCD_OPC_Decode, 200, 2, 0, // Opcode: RSYNC -/* 75 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 91 -/* 80 */ MCD_OPC_CheckField, 8, 8, 32, 112, 4, 0, // Skip to: 1223 -/* 87 */ MCD_OPC_Decode, 178, 2, 0, // Opcode: ESYNC -/* 91 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 107 -/* 96 */ MCD_OPC_CheckField, 8, 8, 32, 96, 4, 0, // Skip to: 1223 -/* 103 */ MCD_OPC_Decode, 177, 2, 0, // Opcode: DSYNC -/* 107 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 123 -/* 112 */ MCD_OPC_CheckField, 8, 8, 0, 80, 4, 0, // Skip to: 1223 -/* 119 */ MCD_OPC_Decode, 198, 2, 0, // Opcode: RET -/* 123 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 139 -/* 128 */ MCD_OPC_CheckField, 12, 4, 0, 64, 4, 0, // Skip to: 1223 -/* 135 */ MCD_OPC_Decode, 183, 2, 1, // Opcode: JX -/* 139 */ MCD_OPC_FilterValue, 12, 28, 0, 0, // Skip to: 172 -/* 144 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 147 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 156 -/* 152 */ MCD_OPC_Decode, 176, 2, 1, // Opcode: CALLX0 -/* 156 */ MCD_OPC_FilterValue, 2, 38, 4, 0, // Skip to: 1223 -/* 161 */ MCD_OPC_CheckField, 8, 4, 0, 31, 4, 0, // Skip to: 1223 -/* 168 */ MCD_OPC_Decode, 189, 2, 0, // Opcode: MEMW -/* 172 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 188 -/* 177 */ MCD_OPC_CheckField, 8, 8, 32, 15, 4, 0, // Skip to: 1223 -/* 184 */ MCD_OPC_Decode, 180, 2, 0, // Opcode: EXTW -/* 188 */ MCD_OPC_FilterValue, 15, 6, 4, 0, // Skip to: 1223 -/* 193 */ MCD_OPC_CheckField, 8, 8, 32, 255, 3, 0, // Skip to: 1223 -/* 200 */ MCD_OPC_Decode, 196, 2, 0, // Opcode: NOP -/* 204 */ MCD_OPC_FilterValue, 1, 246, 3, 0, // Skip to: 1223 -/* 209 */ MCD_OPC_Decode, 150, 2, 2, // Opcode: AND -/* 213 */ MCD_OPC_FilterValue, 1, 237, 3, 0, // Skip to: 1223 -/* 218 */ MCD_OPC_Decode, 205, 2, 3, // Opcode: SLLI -/* 222 */ MCD_OPC_FilterValue, 1, 38, 0, 0, // Skip to: 265 -/* 227 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 230 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 256 -/* 235 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 238 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 247 -/* 243 */ MCD_OPC_Decode, 197, 2, 2, // Opcode: OR -/* 247 */ MCD_OPC_FilterValue, 1, 203, 3, 0, // Skip to: 1223 -/* 252 */ MCD_OPC_Decode, 220, 2, 2, // Opcode: XOR -/* 256 */ MCD_OPC_FilterValue, 1, 194, 3, 0, // Skip to: 1223 -/* 261 */ MCD_OPC_Decode, 207, 2, 4, // Opcode: SRAI -/* 265 */ MCD_OPC_FilterValue, 2, 119, 0, 0, // Skip to: 389 -/* 270 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 273 */ MCD_OPC_FilterValue, 0, 95, 0, 0, // Skip to: 373 -/* 278 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 281 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 304 -/* 286 */ MCD_OPC_CheckField, 20, 1, 0, 162, 3, 0, // Skip to: 1223 -/* 293 */ MCD_OPC_CheckField, 4, 4, 0, 155, 3, 0, // Skip to: 1223 -/* 300 */ MCD_OPC_Decode, 214, 2, 1, // Opcode: SSR -/* 304 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 327 -/* 309 */ MCD_OPC_CheckField, 20, 1, 0, 139, 3, 0, // Skip to: 1223 -/* 316 */ MCD_OPC_CheckField, 4, 4, 0, 132, 3, 0, // Skip to: 1223 -/* 323 */ MCD_OPC_Decode, 213, 2, 1, // Opcode: SSL -/* 327 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 350 -/* 332 */ MCD_OPC_CheckField, 20, 1, 0, 116, 3, 0, // Skip to: 1223 -/* 339 */ MCD_OPC_CheckField, 4, 4, 0, 109, 3, 0, // Skip to: 1223 -/* 346 */ MCD_OPC_Decode, 211, 2, 1, // Opcode: SSA8L -/* 350 */ MCD_OPC_FilterValue, 4, 100, 3, 0, // Skip to: 1223 -/* 355 */ MCD_OPC_CheckField, 20, 1, 0, 93, 3, 0, // Skip to: 1223 -/* 362 */ MCD_OPC_CheckField, 5, 3, 0, 86, 3, 0, // Skip to: 1223 -/* 369 */ MCD_OPC_Decode, 212, 2, 5, // Opcode: SSAI -/* 373 */ MCD_OPC_FilterValue, 1, 77, 3, 0, // Skip to: 1223 -/* 378 */ MCD_OPC_CheckField, 20, 1, 0, 70, 3, 0, // Skip to: 1223 -/* 385 */ MCD_OPC_Decode, 210, 2, 6, // Opcode: SRLI -/* 389 */ MCD_OPC_FilterValue, 3, 59, 0, 0, // Skip to: 453 -/* 394 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 397 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 437 -/* 402 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 405 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 421 -/* 410 */ MCD_OPC_CheckField, 20, 1, 0, 38, 3, 0, // Skip to: 1223 -/* 417 */ MCD_OPC_Decode, 195, 2, 7, // Opcode: NEG -/* 421 */ MCD_OPC_FilterValue, 1, 29, 3, 0, // Skip to: 1223 -/* 426 */ MCD_OPC_CheckField, 20, 1, 0, 22, 3, 0, // Skip to: 1223 -/* 433 */ MCD_OPC_Decode, 143, 2, 7, // Opcode: ABS -/* 437 */ MCD_OPC_FilterValue, 1, 13, 3, 0, // Skip to: 1223 -/* 442 */ MCD_OPC_CheckField, 20, 1, 0, 6, 3, 0, // Skip to: 1223 -/* 449 */ MCD_OPC_Decode, 221, 2, 8, // Opcode: XSR -/* 453 */ MCD_OPC_FilterValue, 4, 62, 0, 0, // Skip to: 520 -/* 458 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 461 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 487 -/* 466 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 469 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 478 -/* 474 */ MCD_OPC_Decode, 144, 2, 2, // Opcode: ADD -/* 478 */ MCD_OPC_FilterValue, 1, 228, 2, 0, // Skip to: 1223 -/* 483 */ MCD_OPC_Decode, 147, 2, 2, // Opcode: ADDX2 -/* 487 */ MCD_OPC_FilterValue, 1, 219, 2, 0, // Skip to: 1223 -/* 492 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 495 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 504 -/* 500 */ MCD_OPC_Decode, 208, 2, 2, // Opcode: SRC -/* 504 */ MCD_OPC_FilterValue, 1, 202, 2, 0, // Skip to: 1223 -/* 509 */ MCD_OPC_CheckField, 8, 4, 0, 195, 2, 0, // Skip to: 1223 -/* 516 */ MCD_OPC_Decode, 209, 2, 7, // Opcode: SRL -/* 520 */ MCD_OPC_FilterValue, 5, 69, 0, 0, // Skip to: 594 -/* 525 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 528 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 554 -/* 533 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 536 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 545 -/* 541 */ MCD_OPC_Decode, 148, 2, 2, // Opcode: ADDX4 -/* 545 */ MCD_OPC_FilterValue, 1, 161, 2, 0, // Skip to: 1223 -/* 550 */ MCD_OPC_Decode, 149, 2, 2, // Opcode: ADDX8 -/* 554 */ MCD_OPC_FilterValue, 1, 152, 2, 0, // Skip to: 1223 -/* 559 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 562 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 578 -/* 567 */ MCD_OPC_CheckField, 4, 4, 0, 137, 2, 0, // Skip to: 1223 -/* 574 */ MCD_OPC_Decode, 204, 2, 9, // Opcode: SLL -/* 578 */ MCD_OPC_FilterValue, 1, 128, 2, 0, // Skip to: 1223 -/* 583 */ MCD_OPC_CheckField, 8, 4, 0, 121, 2, 0, // Skip to: 1223 -/* 590 */ MCD_OPC_Decode, 206, 2, 7, // Opcode: SRA -/* 594 */ MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 634 -/* 599 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 602 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 618 -/* 607 */ MCD_OPC_CheckField, 16, 1, 0, 97, 2, 0, // Skip to: 1223 -/* 614 */ MCD_OPC_Decode, 215, 2, 2, // Opcode: SUB -/* 618 */ MCD_OPC_FilterValue, 1, 88, 2, 0, // Skip to: 1223 -/* 623 */ MCD_OPC_CheckField, 16, 1, 0, 81, 2, 0, // Skip to: 1223 -/* 630 */ MCD_OPC_Decode, 216, 2, 2, // Opcode: SUBX2 -/* 634 */ MCD_OPC_FilterValue, 7, 72, 2, 0, // Skip to: 1223 -/* 639 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 642 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 658 -/* 647 */ MCD_OPC_CheckField, 16, 1, 0, 57, 2, 0, // Skip to: 1223 -/* 654 */ MCD_OPC_Decode, 217, 2, 2, // Opcode: SUBX4 -/* 658 */ MCD_OPC_FilterValue, 1, 48, 2, 0, // Skip to: 1223 -/* 663 */ MCD_OPC_CheckField, 16, 1, 0, 41, 2, 0, // Skip to: 1223 -/* 670 */ MCD_OPC_Decode, 218, 2, 2, // Opcode: SUBX8 -/* 674 */ MCD_OPC_FilterValue, 1, 99, 0, 0, // Skip to: 778 -/* 679 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 682 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 698 -/* 687 */ MCD_OPC_CheckField, 16, 1, 1, 17, 2, 0, // Skip to: 1223 -/* 694 */ MCD_OPC_Decode, 199, 2, 10, // Opcode: RSR -/* 698 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 714 -/* 703 */ MCD_OPC_CheckField, 16, 1, 1, 1, 2, 0, // Skip to: 1223 -/* 710 */ MCD_OPC_Decode, 219, 2, 11, // Opcode: WSR -/* 714 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 730 -/* 719 */ MCD_OPC_CheckField, 16, 1, 1, 241, 1, 0, // Skip to: 1223 -/* 726 */ MCD_OPC_Decode, 190, 2, 2, // Opcode: MOVEQZ -/* 730 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 746 -/* 735 */ MCD_OPC_CheckField, 16, 1, 1, 225, 1, 0, // Skip to: 1223 -/* 742 */ MCD_OPC_Decode, 194, 2, 2, // Opcode: MOVNEZ -/* 746 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 762 -/* 751 */ MCD_OPC_CheckField, 16, 1, 1, 209, 1, 0, // Skip to: 1223 -/* 758 */ MCD_OPC_Decode, 193, 2, 2, // Opcode: MOVLTZ -/* 762 */ MCD_OPC_FilterValue, 11, 200, 1, 0, // Skip to: 1223 -/* 767 */ MCD_OPC_CheckField, 16, 1, 1, 193, 1, 0, // Skip to: 1223 -/* 774 */ MCD_OPC_Decode, 191, 2, 2, // Opcode: MOVGEZ -/* 778 */ MCD_OPC_FilterValue, 2, 184, 1, 0, // Skip to: 1223 -/* 783 */ MCD_OPC_Decode, 179, 2, 12, // Opcode: EXTUI -/* 787 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 796 -/* 792 */ MCD_OPC_Decode, 187, 2, 13, // Opcode: L32R -/* 796 */ MCD_OPC_FilterValue, 2, 93, 0, 0, // Skip to: 894 -/* 801 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 804 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 813 -/* 809 */ MCD_OPC_Decode, 188, 2, 14, // Opcode: L8UI -/* 813 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 822 -/* 818 */ MCD_OPC_Decode, 185, 2, 15, // Opcode: L16UI -/* 822 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 831 -/* 827 */ MCD_OPC_Decode, 186, 2, 16, // Opcode: L32I -/* 831 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 840 -/* 836 */ MCD_OPC_Decode, 203, 2, 14, // Opcode: S8I -/* 840 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 849 -/* 845 */ MCD_OPC_Decode, 201, 2, 15, // Opcode: S16I -/* 849 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 858 -/* 854 */ MCD_OPC_Decode, 202, 2, 16, // Opcode: S32I -/* 858 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 867 -/* 863 */ MCD_OPC_Decode, 184, 2, 15, // Opcode: L16SI -/* 867 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 876 -/* 872 */ MCD_OPC_Decode, 192, 2, 17, // Opcode: MOVI -/* 876 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 885 -/* 881 */ MCD_OPC_Decode, 145, 2, 18, // Opcode: ADDI -/* 885 */ MCD_OPC_FilterValue, 13, 77, 1, 0, // Skip to: 1223 -/* 890 */ MCD_OPC_Decode, 146, 2, 19, // Opcode: ADDMI -/* 894 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 910 -/* 899 */ MCD_OPC_CheckField, 4, 2, 0, 61, 1, 0, // Skip to: 1223 -/* 906 */ MCD_OPC_Decode, 175, 2, 20, // Opcode: CALL0 -/* 910 */ MCD_OPC_FilterValue, 6, 126, 0, 0, // Skip to: 1041 -/* 915 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 918 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 927 -/* 923 */ MCD_OPC_Decode, 182, 2, 21, // Opcode: J -/* 927 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 971 -/* 932 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 935 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 944 -/* 940 */ MCD_OPC_Decode, 159, 2, 22, // Opcode: BEQZ -/* 944 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 953 -/* 949 */ MCD_OPC_Decode, 173, 2, 22, // Opcode: BNEZ -/* 953 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 962 -/* 958 */ MCD_OPC_Decode, 169, 2, 22, // Opcode: BLTZ -/* 962 */ MCD_OPC_FilterValue, 3, 0, 1, 0, // Skip to: 1223 -/* 967 */ MCD_OPC_Decode, 164, 2, 22, // Opcode: BGEZ -/* 971 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 1015 -/* 976 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 979 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 988 -/* 984 */ MCD_OPC_Decode, 158, 2, 23, // Opcode: BEQI -/* 988 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 997 -/* 993 */ MCD_OPC_Decode, 172, 2, 23, // Opcode: BNEI -/* 997 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1006 -/* 1002 */ MCD_OPC_Decode, 166, 2, 23, // Opcode: BLTI -/* 1006 */ MCD_OPC_FilterValue, 3, 212, 0, 0, // Skip to: 1223 -/* 1011 */ MCD_OPC_Decode, 161, 2, 23, // Opcode: BGEI -/* 1015 */ MCD_OPC_FilterValue, 3, 203, 0, 0, // Skip to: 1223 -/* 1020 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 1023 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1032 -/* 1028 */ MCD_OPC_Decode, 168, 2, 24, // Opcode: BLTUI -/* 1032 */ MCD_OPC_FilterValue, 3, 186, 0, 0, // Skip to: 1223 -/* 1037 */ MCD_OPC_Decode, 163, 2, 24, // Opcode: BGEUI -/* 1041 */ MCD_OPC_FilterValue, 7, 177, 0, 0, // Skip to: 1223 -/* 1046 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 1049 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 1075 -/* 1054 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1057 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1066 -/* 1062 */ MCD_OPC_Decode, 174, 2, 25, // Opcode: BNONE -/* 1066 */ MCD_OPC_FilterValue, 1, 152, 0, 0, // Skip to: 1223 -/* 1071 */ MCD_OPC_Decode, 157, 2, 25, // Opcode: BEQ -/* 1075 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 1101 -/* 1080 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1083 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1092 -/* 1088 */ MCD_OPC_Decode, 165, 2, 25, // Opcode: BLT -/* 1092 */ MCD_OPC_FilterValue, 1, 126, 0, 0, // Skip to: 1223 -/* 1097 */ MCD_OPC_Decode, 167, 2, 25, // Opcode: BLTU -/* 1101 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 1127 -/* 1106 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1109 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1118 -/* 1114 */ MCD_OPC_Decode, 151, 2, 25, // Opcode: BALL -/* 1118 */ MCD_OPC_FilterValue, 1, 100, 0, 0, // Skip to: 1223 -/* 1123 */ MCD_OPC_Decode, 153, 2, 25, // Opcode: BBC -/* 1127 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1136 -/* 1132 */ MCD_OPC_Decode, 154, 2, 26, // Opcode: BBCI -/* 1136 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 1162 -/* 1141 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1144 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1153 -/* 1149 */ MCD_OPC_Decode, 152, 2, 25, // Opcode: BANY -/* 1153 */ MCD_OPC_FilterValue, 1, 65, 0, 0, // Skip to: 1223 -/* 1158 */ MCD_OPC_Decode, 171, 2, 25, // Opcode: BNE -/* 1162 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 1188 -/* 1167 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1170 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1179 -/* 1175 */ MCD_OPC_Decode, 160, 2, 25, // Opcode: BGE -/* 1179 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 1223 -/* 1184 */ MCD_OPC_Decode, 162, 2, 25, // Opcode: BGEU -/* 1188 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 1214 -/* 1193 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1196 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1205 -/* 1201 */ MCD_OPC_Decode, 170, 2, 25, // Opcode: BNALL -/* 1205 */ MCD_OPC_FilterValue, 1, 13, 0, 0, // Skip to: 1223 -/* 1210 */ MCD_OPC_Decode, 155, 2, 25, // Opcode: BBS -/* 1214 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1223 -/* 1219 */ MCD_OPC_Decode, 156, 2, 26, // Opcode: BBSI -/* 1223 */ MCD_OPC_Fail, +/* 35 */ MCD_OPC_FilterValue, 0, 189, 1, 0, // Skip to: 485 +/* 40 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 43 */ MCD_OPC_FilterValue, 0, 116, 0, 0, // Skip to: 164 +/* 48 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 51 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 67 +/* 56 */ MCD_OPC_CheckField, 8, 4, 0, 251, 19, 0, // Skip to: 5178 +/* 63 */ MCD_OPC_Decode, 170, 13, 6, // Opcode: ILL +/* 67 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 83 +/* 72 */ MCD_OPC_CheckField, 8, 4, 0, 235, 19, 0, // Skip to: 5178 +/* 79 */ MCD_OPC_Decode, 179, 14, 6, // Opcode: RET +/* 83 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 104 +/* 88 */ MCD_OPC_CheckPredicate, 3, 221, 19, 0, // Skip to: 5178 +/* 93 */ MCD_OPC_CheckField, 8, 4, 0, 214, 19, 0, // Skip to: 5178 +/* 100 */ MCD_OPC_Decode, 180, 14, 6, // Opcode: RETW +/* 104 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 113 +/* 109 */ MCD_OPC_Decode, 174, 13, 7, // Opcode: JX +/* 113 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 122 +/* 118 */ MCD_OPC_Decode, 190, 11, 7, // Opcode: CALLX0 +/* 122 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 136 +/* 127 */ MCD_OPC_CheckPredicate, 3, 182, 19, 0, // Skip to: 5178 +/* 132 */ MCD_OPC_Decode, 192, 11, 7, // Opcode: CALLX4 +/* 136 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 150 +/* 141 */ MCD_OPC_CheckPredicate, 3, 168, 19, 0, // Skip to: 5178 +/* 146 */ MCD_OPC_Decode, 193, 11, 7, // Opcode: CALLX8 +/* 150 */ MCD_OPC_FilterValue, 15, 159, 19, 0, // Skip to: 5178 +/* 155 */ MCD_OPC_CheckPredicate, 3, 154, 19, 0, // Skip to: 5178 +/* 160 */ MCD_OPC_Decode, 191, 11, 7, // Opcode: CALLX12 +/* 164 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 178 +/* 169 */ MCD_OPC_CheckPredicate, 3, 140, 19, 0, // Skip to: 5178 +/* 174 */ MCD_OPC_Decode, 213, 13, 5, // Opcode: MOVSP +/* 178 */ MCD_OPC_FilterValue, 2, 80, 0, 0, // Skip to: 263 +/* 183 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... +/* 186 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 195 +/* 191 */ MCD_OPC_Decode, 172, 13, 6, // Opcode: ISYNC +/* 195 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 204 +/* 200 */ MCD_OPC_Decode, 194, 14, 6, // Opcode: RSYNC +/* 204 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 213 +/* 209 */ MCD_OPC_Decode, 163, 13, 6, // Opcode: ESYNC +/* 213 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 222 +/* 218 */ MCD_OPC_Decode, 200, 11, 6, // Opcode: DSYNC +/* 222 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 236 +/* 227 */ MCD_OPC_CheckPredicate, 4, 82, 19, 0, // Skip to: 5178 +/* 232 */ MCD_OPC_Decode, 164, 13, 6, // Opcode: EXCW +/* 236 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 245 +/* 241 */ MCD_OPC_Decode, 196, 13, 6, // Opcode: MEMW +/* 245 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 254 +/* 250 */ MCD_OPC_Decode, 166, 13, 6, // Opcode: EXTW +/* 254 */ MCD_OPC_FilterValue, 15, 55, 19, 0, // Skip to: 5178 +/* 259 */ MCD_OPC_Decode, 164, 14, 6, // Opcode: NOP +/* 263 */ MCD_OPC_FilterValue, 3, 81, 0, 0, // Skip to: 349 +/* 268 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 271 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 335 +/* 276 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 279 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 293 +/* 284 */ MCD_OPC_CheckPredicate, 4, 25, 19, 0, // Skip to: 5178 +/* 289 */ MCD_OPC_Decode, 184, 14, 6, // Opcode: RFE +/* 293 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 307 +/* 298 */ MCD_OPC_CheckPredicate, 4, 11, 19, 0, // Skip to: 5178 +/* 303 */ MCD_OPC_Decode, 183, 14, 6, // Opcode: RFDE +/* 307 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 321 +/* 312 */ MCD_OPC_CheckPredicate, 3, 253, 18, 0, // Skip to: 5178 +/* 317 */ MCD_OPC_Decode, 187, 14, 6, // Opcode: RFWO +/* 321 */ MCD_OPC_FilterValue, 5, 244, 18, 0, // Skip to: 5178 +/* 326 */ MCD_OPC_CheckPredicate, 3, 239, 18, 0, // Skip to: 5178 +/* 331 */ MCD_OPC_Decode, 188, 14, 6, // Opcode: RFWU +/* 335 */ MCD_OPC_FilterValue, 1, 230, 18, 0, // Skip to: 5178 +/* 340 */ MCD_OPC_CheckPredicate, 5, 225, 18, 0, // Skip to: 5178 +/* 345 */ MCD_OPC_Decode, 185, 14, 3, // Opcode: RFI +/* 349 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 363 +/* 354 */ MCD_OPC_CheckPredicate, 6, 211, 18, 0, // Skip to: 5178 +/* 359 */ MCD_OPC_Decode, 183, 11, 8, // Opcode: BREAK +/* 363 */ MCD_OPC_FilterValue, 5, 26, 0, 0, // Skip to: 394 +/* 368 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... +/* 371 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 385 +/* 376 */ MCD_OPC_CheckPredicate, 4, 189, 18, 0, // Skip to: 5178 +/* 381 */ MCD_OPC_Decode, 132, 15, 6, // Opcode: SYSCALL +/* 385 */ MCD_OPC_FilterValue, 16, 180, 18, 0, // Skip to: 5178 +/* 390 */ MCD_OPC_Decode, 238, 14, 6, // Opcode: SIMCALL +/* 394 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 408 +/* 399 */ MCD_OPC_CheckPredicate, 5, 166, 18, 0, // Skip to: 5178 +/* 404 */ MCD_OPC_Decode, 191, 14, 9, // Opcode: RSIL +/* 408 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 429 +/* 413 */ MCD_OPC_CheckPredicate, 5, 152, 18, 0, // Skip to: 5178 +/* 418 */ MCD_OPC_CheckField, 4, 4, 0, 145, 18, 0, // Skip to: 5178 +/* 425 */ MCD_OPC_Decode, 144, 15, 3, // Opcode: WAITI +/* 429 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 443 +/* 434 */ MCD_OPC_CheckPredicate, 7, 131, 18, 0, // Skip to: 5178 +/* 439 */ MCD_OPC_Decode, 156, 11, 10, // Opcode: ANY4 +/* 443 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 457 +/* 448 */ MCD_OPC_CheckPredicate, 7, 117, 18, 0, // Skip to: 5178 +/* 453 */ MCD_OPC_Decode, 151, 11, 10, // Opcode: ALL4 +/* 457 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 471 +/* 462 */ MCD_OPC_CheckPredicate, 7, 103, 18, 0, // Skip to: 5178 +/* 467 */ MCD_OPC_Decode, 157, 11, 10, // Opcode: ANY8 +/* 471 */ MCD_OPC_FilterValue, 11, 94, 18, 0, // Skip to: 5178 +/* 476 */ MCD_OPC_CheckPredicate, 7, 89, 18, 0, // Skip to: 5178 +/* 481 */ MCD_OPC_Decode, 152, 11, 10, // Opcode: ALL8 +/* 485 */ MCD_OPC_FilterValue, 1, 80, 18, 0, // Skip to: 5178 +/* 490 */ MCD_OPC_Decode, 153, 11, 1, // Opcode: AND +/* 494 */ MCD_OPC_FilterValue, 1, 71, 18, 0, // Skip to: 5178 +/* 499 */ MCD_OPC_Decode, 240, 14, 11, // Opcode: SLLI +/* 503 */ MCD_OPC_FilterValue, 1, 38, 0, 0, // Skip to: 546 +/* 508 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 511 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 537 +/* 516 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 519 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 528 +/* 524 */ MCD_OPC_Decode, 170, 14, 1, // Opcode: OR +/* 528 */ MCD_OPC_FilterValue, 1, 37, 18, 0, // Skip to: 5178 +/* 533 */ MCD_OPC_Decode, 188, 15, 1, // Opcode: XOR +/* 537 */ MCD_OPC_FilterValue, 1, 28, 18, 0, // Skip to: 5178 +/* 542 */ MCD_OPC_Decode, 243, 14, 12, // Opcode: SRAI +/* 546 */ MCD_OPC_FilterValue, 2, 251, 0, 0, // Skip to: 802 +/* 551 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 554 */ MCD_OPC_FilterValue, 0, 227, 0, 0, // Skip to: 786 +/* 559 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 562 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 585 +/* 567 */ MCD_OPC_CheckField, 20, 1, 0, 252, 17, 0, // Skip to: 5178 +/* 574 */ MCD_OPC_CheckField, 4, 4, 0, 245, 17, 0, // Skip to: 5178 +/* 581 */ MCD_OPC_Decode, 252, 14, 7, // Opcode: SSR +/* 585 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 608 +/* 590 */ MCD_OPC_CheckField, 20, 1, 0, 229, 17, 0, // Skip to: 5178 +/* 597 */ MCD_OPC_CheckField, 4, 4, 0, 222, 17, 0, // Skip to: 5178 +/* 604 */ MCD_OPC_Decode, 251, 14, 7, // Opcode: SSL +/* 608 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 631 +/* 613 */ MCD_OPC_CheckField, 20, 1, 0, 206, 17, 0, // Skip to: 5178 +/* 620 */ MCD_OPC_CheckField, 4, 4, 0, 199, 17, 0, // Skip to: 5178 +/* 627 */ MCD_OPC_Decode, 247, 14, 7, // Opcode: SSA8L +/* 631 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 654 +/* 636 */ MCD_OPC_CheckField, 20, 1, 0, 183, 17, 0, // Skip to: 5178 +/* 643 */ MCD_OPC_CheckField, 5, 3, 0, 176, 17, 0, // Skip to: 5178 +/* 650 */ MCD_OPC_Decode, 248, 14, 13, // Opcode: SSAI +/* 654 */ MCD_OPC_FilterValue, 6, 26, 0, 0, // Skip to: 685 +/* 659 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 662 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 671 +/* 667 */ MCD_OPC_Decode, 178, 14, 5, // Opcode: RER +/* 671 */ MCD_OPC_FilterValue, 1, 150, 17, 0, // Skip to: 5178 +/* 676 */ MCD_OPC_CheckPredicate, 8, 145, 17, 0, // Skip to: 5178 +/* 681 */ MCD_OPC_Decode, 148, 15, 5, // Opcode: WITLB +/* 685 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 701 +/* 690 */ MCD_OPC_CheckField, 20, 1, 0, 129, 17, 0, // Skip to: 5178 +/* 697 */ MCD_OPC_Decode, 146, 15, 5, // Opcode: WER +/* 701 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 729 +/* 706 */ MCD_OPC_CheckPredicate, 3, 115, 17, 0, // Skip to: 5178 +/* 711 */ MCD_OPC_CheckField, 20, 1, 0, 108, 17, 0, // Skip to: 5178 +/* 718 */ MCD_OPC_CheckField, 8, 4, 0, 101, 17, 0, // Skip to: 5178 +/* 725 */ MCD_OPC_Decode, 189, 14, 14, // Opcode: ROTW +/* 729 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 765 +/* 734 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 737 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 751 +/* 742 */ MCD_OPC_CheckPredicate, 9, 79, 17, 0, // Skip to: 5178 +/* 747 */ MCD_OPC_Decode, 165, 14, 5, // Opcode: NSA +/* 751 */ MCD_OPC_FilterValue, 1, 70, 17, 0, // Skip to: 5178 +/* 756 */ MCD_OPC_CheckPredicate, 8, 65, 17, 0, // Skip to: 5178 +/* 761 */ MCD_OPC_Decode, 145, 15, 5, // Opcode: WDTLB +/* 765 */ MCD_OPC_FilterValue, 15, 56, 17, 0, // Skip to: 5178 +/* 770 */ MCD_OPC_CheckPredicate, 9, 51, 17, 0, // Skip to: 5178 +/* 775 */ MCD_OPC_CheckField, 20, 1, 0, 44, 17, 0, // Skip to: 5178 +/* 782 */ MCD_OPC_Decode, 166, 14, 5, // Opcode: NSAU +/* 786 */ MCD_OPC_FilterValue, 1, 35, 17, 0, // Skip to: 5178 +/* 791 */ MCD_OPC_CheckField, 20, 1, 0, 28, 17, 0, // Skip to: 5178 +/* 798 */ MCD_OPC_Decode, 246, 14, 15, // Opcode: SRLI +/* 802 */ MCD_OPC_FilterValue, 3, 59, 0, 0, // Skip to: 866 +/* 807 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 810 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 850 +/* 815 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 818 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 834 +/* 823 */ MCD_OPC_CheckField, 20, 1, 0, 252, 16, 0, // Skip to: 5178 +/* 830 */ MCD_OPC_Decode, 161, 14, 16, // Opcode: NEG +/* 834 */ MCD_OPC_FilterValue, 1, 243, 16, 0, // Skip to: 5178 +/* 839 */ MCD_OPC_CheckField, 20, 1, 0, 236, 16, 0, // Skip to: 5178 +/* 846 */ MCD_OPC_Decode, 197, 4, 16, // Opcode: ABS +/* 850 */ MCD_OPC_FilterValue, 1, 227, 16, 0, // Skip to: 5178 +/* 855 */ MCD_OPC_CheckField, 20, 1, 0, 220, 16, 0, // Skip to: 5178 +/* 862 */ MCD_OPC_Decode, 190, 15, 17, // Opcode: XSR +/* 866 */ MCD_OPC_FilterValue, 4, 62, 0, 0, // Skip to: 933 +/* 871 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 874 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 900 +/* 879 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 882 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 891 +/* 887 */ MCD_OPC_Decode, 199, 4, 1, // Opcode: ADD +/* 891 */ MCD_OPC_FilterValue, 1, 186, 16, 0, // Skip to: 5178 +/* 896 */ MCD_OPC_Decode, 205, 4, 1, // Opcode: ADDX2 +/* 900 */ MCD_OPC_FilterValue, 1, 177, 16, 0, // Skip to: 5178 +/* 905 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 908 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 917 +/* 913 */ MCD_OPC_Decode, 244, 14, 1, // Opcode: SRC +/* 917 */ MCD_OPC_FilterValue, 1, 160, 16, 0, // Skip to: 5178 +/* 922 */ MCD_OPC_CheckField, 8, 4, 0, 153, 16, 0, // Skip to: 5178 +/* 929 */ MCD_OPC_Decode, 245, 14, 16, // Opcode: SRL +/* 933 */ MCD_OPC_FilterValue, 5, 69, 0, 0, // Skip to: 1007 +/* 938 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 941 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 967 +/* 946 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 949 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 958 +/* 954 */ MCD_OPC_Decode, 206, 4, 1, // Opcode: ADDX4 +/* 958 */ MCD_OPC_FilterValue, 1, 119, 16, 0, // Skip to: 5178 +/* 963 */ MCD_OPC_Decode, 207, 4, 1, // Opcode: ADDX8 +/* 967 */ MCD_OPC_FilterValue, 1, 110, 16, 0, // Skip to: 5178 +/* 972 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 975 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 991 +/* 980 */ MCD_OPC_CheckField, 4, 4, 0, 95, 16, 0, // Skip to: 5178 +/* 987 */ MCD_OPC_Decode, 239, 14, 18, // Opcode: SLL +/* 991 */ MCD_OPC_FilterValue, 1, 86, 16, 0, // Skip to: 5178 +/* 996 */ MCD_OPC_CheckField, 8, 4, 0, 79, 16, 0, // Skip to: 5178 +/* 1003 */ MCD_OPC_Decode, 242, 14, 16, // Opcode: SRA +/* 1007 */ MCD_OPC_FilterValue, 6, 65, 0, 0, // Skip to: 1077 +/* 1012 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1015 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 1041 +/* 1020 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1023 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1032 +/* 1028 */ MCD_OPC_Decode, 255, 14, 1, // Opcode: SUB +/* 1032 */ MCD_OPC_FilterValue, 1, 45, 16, 0, // Skip to: 5178 +/* 1037 */ MCD_OPC_Decode, 128, 15, 1, // Opcode: SUBX2 +/* 1041 */ MCD_OPC_FilterValue, 1, 36, 16, 0, // Skip to: 5178 +/* 1046 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1049 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1063 +/* 1054 */ MCD_OPC_CheckPredicate, 10, 23, 16, 0, // Skip to: 5178 +/* 1059 */ MCD_OPC_Decode, 220, 13, 1, // Opcode: MUL16U +/* 1063 */ MCD_OPC_FilterValue, 1, 14, 16, 0, // Skip to: 5178 +/* 1068 */ MCD_OPC_CheckPredicate, 10, 9, 16, 0, // Skip to: 5178 +/* 1073 */ MCD_OPC_Decode, 219, 13, 1, // Opcode: MUL16S +/* 1077 */ MCD_OPC_FilterValue, 7, 0, 16, 0, // Skip to: 5178 +/* 1082 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1085 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1101 +/* 1090 */ MCD_OPC_CheckField, 16, 1, 0, 241, 15, 0, // Skip to: 5178 +/* 1097 */ MCD_OPC_Decode, 129, 15, 1, // Opcode: SUBX4 +/* 1101 */ MCD_OPC_FilterValue, 1, 232, 15, 0, // Skip to: 5178 +/* 1106 */ MCD_OPC_CheckField, 16, 1, 0, 225, 15, 0, // Skip to: 5178 +/* 1113 */ MCD_OPC_Decode, 130, 15, 1, // Opcode: SUBX8 +/* 1117 */ MCD_OPC_FilterValue, 1, 246, 1, 0, // Skip to: 1624 +/* 1122 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 1125 */ MCD_OPC_FilterValue, 0, 26, 0, 0, // Skip to: 1156 +/* 1130 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1133 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1147 +/* 1138 */ MCD_OPC_CheckPredicate, 7, 195, 15, 0, // Skip to: 5178 +/* 1143 */ MCD_OPC_Decode, 154, 11, 19, // Opcode: ANDB +/* 1147 */ MCD_OPC_FilterValue, 1, 186, 15, 0, // Skip to: 5178 +/* 1152 */ MCD_OPC_Decode, 193, 14, 20, // Opcode: RSR +/* 1156 */ MCD_OPC_FilterValue, 1, 26, 0, 0, // Skip to: 1187 +/* 1161 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1164 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1178 +/* 1169 */ MCD_OPC_CheckPredicate, 7, 164, 15, 0, // Skip to: 5178 +/* 1174 */ MCD_OPC_Decode, 155, 11, 19, // Opcode: ANDBC +/* 1178 */ MCD_OPC_FilterValue, 1, 155, 15, 0, // Skip to: 5178 +/* 1183 */ MCD_OPC_Decode, 150, 15, 21, // Opcode: WSR +/* 1187 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1223 +/* 1192 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1195 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1209 +/* 1200 */ MCD_OPC_CheckPredicate, 7, 133, 15, 0, // Skip to: 5178 +/* 1205 */ MCD_OPC_Decode, 171, 14, 19, // Opcode: ORB +/* 1209 */ MCD_OPC_FilterValue, 1, 124, 15, 0, // Skip to: 5178 +/* 1214 */ MCD_OPC_CheckPredicate, 11, 119, 15, 0, // Skip to: 5178 +/* 1219 */ MCD_OPC_Decode, 237, 14, 22, // Opcode: SEXT +/* 1223 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 1259 +/* 1228 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1231 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1245 +/* 1236 */ MCD_OPC_CheckPredicate, 7, 97, 15, 0, // Skip to: 5178 +/* 1241 */ MCD_OPC_Decode, 172, 14, 19, // Opcode: ORBC +/* 1245 */ MCD_OPC_FilterValue, 1, 88, 15, 0, // Skip to: 5178 +/* 1250 */ MCD_OPC_CheckPredicate, 12, 83, 15, 0, // Skip to: 5178 +/* 1255 */ MCD_OPC_Decode, 195, 11, 22, // Opcode: CLAMPS +/* 1259 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 1295 +/* 1264 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1281 +/* 1272 */ MCD_OPC_CheckPredicate, 7, 61, 15, 0, // Skip to: 5178 +/* 1277 */ MCD_OPC_Decode, 189, 15, 19, // Opcode: XORB +/* 1281 */ MCD_OPC_FilterValue, 1, 52, 15, 0, // Skip to: 5178 +/* 1286 */ MCD_OPC_CheckPredicate, 13, 47, 15, 0, // Skip to: 5178 +/* 1291 */ MCD_OPC_Decode, 197, 13, 1, // Opcode: MIN +/* 1295 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 1316 +/* 1300 */ MCD_OPC_CheckPredicate, 13, 33, 15, 0, // Skip to: 5178 +/* 1305 */ MCD_OPC_CheckField, 16, 1, 1, 26, 15, 0, // Skip to: 5178 +/* 1312 */ MCD_OPC_Decode, 194, 13, 1, // Opcode: MAX +/* 1316 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 1337 +/* 1321 */ MCD_OPC_CheckPredicate, 13, 12, 15, 0, // Skip to: 5178 +/* 1326 */ MCD_OPC_CheckField, 16, 1, 1, 5, 15, 0, // Skip to: 5178 +/* 1333 */ MCD_OPC_Decode, 198, 13, 1, // Opcode: MINU +/* 1337 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 1358 +/* 1342 */ MCD_OPC_CheckPredicate, 13, 247, 14, 0, // Skip to: 5178 +/* 1347 */ MCD_OPC_CheckField, 16, 1, 1, 240, 14, 0, // Skip to: 5178 +/* 1354 */ MCD_OPC_Decode, 195, 13, 1, // Opcode: MAXU +/* 1358 */ MCD_OPC_FilterValue, 8, 26, 0, 0, // Skip to: 1389 +/* 1363 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1366 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1380 +/* 1371 */ MCD_OPC_CheckPredicate, 14, 218, 14, 0, // Skip to: 5178 +/* 1376 */ MCD_OPC_Decode, 253, 13, 1, // Opcode: MULL +/* 1380 */ MCD_OPC_FilterValue, 1, 209, 14, 0, // Skip to: 5178 +/* 1385 */ MCD_OPC_Decode, 201, 13, 1, // Opcode: MOVEQZ +/* 1389 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 1405 +/* 1394 */ MCD_OPC_CheckField, 16, 1, 1, 193, 14, 0, // Skip to: 5178 +/* 1401 */ MCD_OPC_Decode, 211, 13, 1, // Opcode: MOVNEZ +/* 1405 */ MCD_OPC_FilterValue, 10, 26, 0, 0, // Skip to: 1436 +/* 1410 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1413 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1427 +/* 1418 */ MCD_OPC_CheckPredicate, 15, 171, 14, 0, // Skip to: 5178 +/* 1423 */ MCD_OPC_Decode, 143, 14, 1, // Opcode: MULUH +/* 1427 */ MCD_OPC_FilterValue, 1, 162, 14, 0, // Skip to: 5178 +/* 1432 */ MCD_OPC_Decode, 209, 13, 1, // Opcode: MOVLTZ +/* 1436 */ MCD_OPC_FilterValue, 11, 26, 0, 0, // Skip to: 1467 +/* 1441 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1444 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1458 +/* 1449 */ MCD_OPC_CheckPredicate, 15, 140, 14, 0, // Skip to: 5178 +/* 1454 */ MCD_OPC_Decode, 254, 13, 1, // Opcode: MULSH +/* 1458 */ MCD_OPC_FilterValue, 1, 131, 14, 0, // Skip to: 5178 +/* 1463 */ MCD_OPC_Decode, 205, 13, 1, // Opcode: MOVGEZ +/* 1467 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 1503 +/* 1472 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1475 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1489 +/* 1480 */ MCD_OPC_CheckPredicate, 16, 109, 14, 0, // Skip to: 5178 +/* 1485 */ MCD_OPC_Decode, 174, 14, 1, // Opcode: QUOU +/* 1489 */ MCD_OPC_FilterValue, 1, 100, 14, 0, // Skip to: 5178 +/* 1494 */ MCD_OPC_CheckPredicate, 7, 95, 14, 0, // Skip to: 5178 +/* 1499 */ MCD_OPC_Decode, 203, 13, 23, // Opcode: MOVF +/* 1503 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1539 +/* 1508 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1511 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1525 +/* 1516 */ MCD_OPC_CheckPredicate, 16, 73, 14, 0, // Skip to: 5178 +/* 1521 */ MCD_OPC_Decode, 173, 14, 1, // Opcode: QUOS +/* 1525 */ MCD_OPC_FilterValue, 1, 64, 14, 0, // Skip to: 5178 +/* 1530 */ MCD_OPC_CheckPredicate, 7, 59, 14, 0, // Skip to: 5178 +/* 1535 */ MCD_OPC_Decode, 214, 13, 23, // Opcode: MOVT +/* 1539 */ MCD_OPC_FilterValue, 14, 26, 0, 0, // Skip to: 1570 +/* 1544 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1547 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1561 +/* 1552 */ MCD_OPC_CheckPredicate, 16, 37, 14, 0, // Skip to: 5178 +/* 1557 */ MCD_OPC_Decode, 177, 14, 1, // Opcode: REMU +/* 1561 */ MCD_OPC_FilterValue, 1, 28, 14, 0, // Skip to: 5178 +/* 1566 */ MCD_OPC_Decode, 195, 14, 24, // Opcode: RUR +/* 1570 */ MCD_OPC_FilterValue, 15, 19, 14, 0, // Skip to: 5178 +/* 1575 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1578 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1592 +/* 1583 */ MCD_OPC_CheckPredicate, 16, 6, 14, 0, // Skip to: 5178 +/* 1588 */ MCD_OPC_Decode, 176, 14, 1, // Opcode: REMS +/* 1592 */ MCD_OPC_FilterValue, 1, 253, 13, 0, // Skip to: 5178 +/* 1597 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 1600 */ MCD_OPC_FilterValue, 232, 1, 4, 0, 0, // Skip to: 1610 +/* 1606 */ MCD_OPC_Decode, 169, 15, 25, // Opcode: WUR_FCR +/* 1610 */ MCD_OPC_FilterValue, 233, 1, 4, 0, 0, // Skip to: 1620 +/* 1616 */ MCD_OPC_Decode, 171, 15, 25, // Opcode: WUR_FSR +/* 1620 */ MCD_OPC_Decode, 151, 15, 26, // Opcode: WUR +/* 1624 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1633 +/* 1629 */ MCD_OPC_Decode, 165, 13, 27, // Opcode: EXTUI +/* 1633 */ MCD_OPC_FilterValue, 3, 94, 0, 0, // Skip to: 1732 +/* 1638 */ MCD_OPC_ExtractField, 12, 5, // Inst{16-12} ... +/* 1641 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1662 +/* 1646 */ MCD_OPC_CheckPredicate, 17, 199, 13, 0, // Skip to: 5178 +/* 1651 */ MCD_OPC_CheckField, 20, 4, 0, 192, 13, 0, // Skip to: 5178 +/* 1658 */ MCD_OPC_Decode, 196, 11, 28, // Opcode: CLR_BIT_GPIO_OUT +/* 1662 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1683 +/* 1667 */ MCD_OPC_CheckPredicate, 17, 178, 13, 0, // Skip to: 5178 +/* 1672 */ MCD_OPC_CheckField, 20, 4, 0, 171, 13, 0, // Skip to: 5178 +/* 1679 */ MCD_OPC_Decode, 236, 14, 28, // Opcode: SET_BIT_GPIO_OUT +/* 1683 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 1704 +/* 1688 */ MCD_OPC_CheckPredicate, 17, 157, 13, 0, // Skip to: 5178 +/* 1693 */ MCD_OPC_CheckField, 20, 4, 0, 150, 13, 0, // Skip to: 5178 +/* 1700 */ MCD_OPC_Decode, 149, 15, 29, // Opcode: WR_MASK_GPIO_OUT +/* 1704 */ MCD_OPC_FilterValue, 3, 141, 13, 0, // Skip to: 5178 +/* 1709 */ MCD_OPC_CheckPredicate, 17, 136, 13, 0, // Skip to: 5178 +/* 1714 */ MCD_OPC_CheckField, 20, 4, 0, 129, 13, 0, // Skip to: 5178 +/* 1721 */ MCD_OPC_CheckField, 8, 4, 0, 122, 13, 0, // Skip to: 5178 +/* 1728 */ MCD_OPC_Decode, 169, 13, 25, // Opcode: GET_GPIO_IN +/* 1732 */ MCD_OPC_FilterValue, 4, 117, 0, 0, // Skip to: 1854 +/* 1737 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 1740 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1776 +/* 1745 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1748 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1762 +/* 1753 */ MCD_OPC_CheckPredicate, 18, 92, 13, 0, // Skip to: 5178 +/* 1758 */ MCD_OPC_Decode, 190, 13, 30, // Opcode: LSX +/* 1762 */ MCD_OPC_FilterValue, 1, 83, 13, 0, // Skip to: 5178 +/* 1767 */ MCD_OPC_CheckPredicate, 3, 78, 13, 0, // Skip to: 5178 +/* 1772 */ MCD_OPC_Decode, 177, 13, 31, // Opcode: L32E +/* 1776 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1797 +/* 1781 */ MCD_OPC_CheckPredicate, 18, 64, 13, 0, // Skip to: 5178 +/* 1786 */ MCD_OPC_CheckField, 16, 1, 0, 57, 13, 0, // Skip to: 5178 +/* 1793 */ MCD_OPC_Decode, 191, 13, 32, // Opcode: LSXP +/* 1797 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 1833 +/* 1802 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1805 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1819 +/* 1810 */ MCD_OPC_CheckPredicate, 18, 35, 13, 0, // Skip to: 5178 +/* 1815 */ MCD_OPC_Decode, 253, 14, 30, // Opcode: SSX +/* 1819 */ MCD_OPC_FilterValue, 1, 26, 13, 0, // Skip to: 5178 +/* 1824 */ MCD_OPC_CheckPredicate, 3, 21, 13, 0, // Skip to: 5178 +/* 1829 */ MCD_OPC_Decode, 232, 14, 31, // Opcode: S32E +/* 1833 */ MCD_OPC_FilterValue, 5, 12, 13, 0, // Skip to: 5178 +/* 1838 */ MCD_OPC_CheckPredicate, 18, 7, 13, 0, // Skip to: 5178 +/* 1843 */ MCD_OPC_CheckField, 16, 1, 0, 0, 13, 0, // Skip to: 5178 +/* 1850 */ MCD_OPC_Decode, 254, 14, 33, // Opcode: SSXP +/* 1854 */ MCD_OPC_FilterValue, 5, 247, 12, 0, // Skip to: 5178 +/* 1859 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 1862 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1883 +/* 1867 */ MCD_OPC_CheckPredicate, 18, 234, 12, 0, // Skip to: 5178 +/* 1872 */ MCD_OPC_CheckField, 16, 1, 0, 227, 12, 0, // Skip to: 5178 +/* 1879 */ MCD_OPC_Decode, 209, 4, 34, // Opcode: ADD_S +/* 1883 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 1919 +/* 1888 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1891 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1905 +/* 1896 */ MCD_OPC_CheckPredicate, 18, 205, 12, 0, // Skip to: 5178 +/* 1901 */ MCD_OPC_Decode, 131, 15, 34, // Opcode: SUB_S +/* 1905 */ MCD_OPC_FilterValue, 1, 196, 12, 0, // Skip to: 5178 +/* 1910 */ MCD_OPC_CheckPredicate, 18, 191, 12, 0, // Skip to: 5178 +/* 1915 */ MCD_OPC_Decode, 142, 15, 35, // Opcode: UN_S +/* 1919 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1955 +/* 1924 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1927 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1941 +/* 1932 */ MCD_OPC_CheckPredicate, 18, 169, 12, 0, // Skip to: 5178 +/* 1937 */ MCD_OPC_Decode, 160, 14, 34, // Opcode: MUL_S +/* 1941 */ MCD_OPC_FilterValue, 1, 160, 12, 0, // Skip to: 5178 +/* 1946 */ MCD_OPC_CheckPredicate, 18, 155, 12, 0, // Skip to: 5178 +/* 1951 */ MCD_OPC_Decode, 167, 14, 35, // Opcode: OEQ_S +/* 1955 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 1976 +/* 1960 */ MCD_OPC_CheckPredicate, 18, 141, 12, 0, // Skip to: 5178 +/* 1965 */ MCD_OPC_CheckField, 16, 1, 1, 134, 12, 0, // Skip to: 5178 +/* 1972 */ MCD_OPC_Decode, 134, 15, 35, // Opcode: UEQ_S +/* 1976 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 2012 +/* 1981 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1984 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1998 +/* 1989 */ MCD_OPC_CheckPredicate, 18, 112, 12, 0, // Skip to: 5178 +/* 1994 */ MCD_OPC_Decode, 193, 13, 36, // Opcode: MADD_S +/* 1998 */ MCD_OPC_FilterValue, 1, 103, 12, 0, // Skip to: 5178 +/* 2003 */ MCD_OPC_CheckPredicate, 18, 98, 12, 0, // Skip to: 5178 +/* 2008 */ MCD_OPC_Decode, 169, 14, 35, // Opcode: OLT_S +/* 2012 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 2048 +/* 2017 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2020 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2034 +/* 2025 */ MCD_OPC_CheckPredicate, 18, 76, 12, 0, // Skip to: 5178 +/* 2030 */ MCD_OPC_Decode, 218, 13, 36, // Opcode: MSUB_S +/* 2034 */ MCD_OPC_FilterValue, 1, 67, 12, 0, // Skip to: 5178 +/* 2039 */ MCD_OPC_CheckPredicate, 18, 62, 12, 0, // Skip to: 5178 +/* 2044 */ MCD_OPC_Decode, 137, 15, 35, // Opcode: ULT_S +/* 2048 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2084 +/* 2053 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2056 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2070 +/* 2061 */ MCD_OPC_CheckPredicate, 18, 40, 12, 0, // Skip to: 5178 +/* 2066 */ MCD_OPC_Decode, 192, 13, 36, // Opcode: MADDN_S +/* 2070 */ MCD_OPC_FilterValue, 1, 31, 12, 0, // Skip to: 5178 +/* 2075 */ MCD_OPC_CheckPredicate, 18, 26, 12, 0, // Skip to: 5178 +/* 2080 */ MCD_OPC_Decode, 168, 14, 35, // Opcode: OLE_S +/* 2084 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 2120 +/* 2089 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2092 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2106 +/* 2097 */ MCD_OPC_CheckPredicate, 18, 4, 12, 0, // Skip to: 5178 +/* 2102 */ MCD_OPC_Decode, 199, 11, 36, // Opcode: DIVN_S +/* 2106 */ MCD_OPC_FilterValue, 1, 251, 11, 0, // Skip to: 5178 +/* 2111 */ MCD_OPC_CheckPredicate, 18, 246, 11, 0, // Skip to: 5178 +/* 2116 */ MCD_OPC_Decode, 136, 15, 35, // Opcode: ULE_S +/* 2120 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2156 +/* 2125 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2128 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2142 +/* 2133 */ MCD_OPC_CheckPredicate, 18, 224, 11, 0, // Skip to: 5178 +/* 2138 */ MCD_OPC_Decode, 190, 14, 37, // Opcode: ROUND_S +/* 2142 */ MCD_OPC_FilterValue, 1, 215, 11, 0, // Skip to: 5178 +/* 2147 */ MCD_OPC_CheckPredicate, 18, 210, 11, 0, // Skip to: 5178 +/* 2152 */ MCD_OPC_Decode, 202, 13, 38, // Opcode: MOVEQZ_S +/* 2156 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 2192 +/* 2161 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2164 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2178 +/* 2169 */ MCD_OPC_CheckPredicate, 18, 188, 11, 0, // Skip to: 5178 +/* 2174 */ MCD_OPC_Decode, 133, 15, 37, // Opcode: TRUNC_S +/* 2178 */ MCD_OPC_FilterValue, 1, 179, 11, 0, // Skip to: 5178 +/* 2183 */ MCD_OPC_CheckPredicate, 18, 174, 11, 0, // Skip to: 5178 +/* 2188 */ MCD_OPC_Decode, 212, 13, 38, // Opcode: MOVNEZ_S +/* 2192 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2228 +/* 2197 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2200 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2214 +/* 2205 */ MCD_OPC_CheckPredicate, 18, 152, 11, 0, // Skip to: 5178 +/* 2210 */ MCD_OPC_Decode, 168, 13, 37, // Opcode: FLOOR_S +/* 2214 */ MCD_OPC_FilterValue, 1, 143, 11, 0, // Skip to: 5178 +/* 2219 */ MCD_OPC_CheckPredicate, 18, 138, 11, 0, // Skip to: 5178 +/* 2224 */ MCD_OPC_Decode, 210, 13, 38, // Opcode: MOVLTZ_S +/* 2228 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2264 +/* 2233 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2236 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2250 +/* 2241 */ MCD_OPC_CheckPredicate, 18, 116, 11, 0, // Skip to: 5178 +/* 2246 */ MCD_OPC_Decode, 194, 11, 37, // Opcode: CEIL_S +/* 2250 */ MCD_OPC_FilterValue, 1, 107, 11, 0, // Skip to: 5178 +/* 2255 */ MCD_OPC_CheckPredicate, 18, 102, 11, 0, // Skip to: 5178 +/* 2260 */ MCD_OPC_Decode, 206, 13, 38, // Opcode: MOVGEZ_S +/* 2264 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 2300 +/* 2269 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2272 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2286 +/* 2277 */ MCD_OPC_CheckPredicate, 18, 80, 11, 0, // Skip to: 5178 +/* 2282 */ MCD_OPC_Decode, 167, 13, 39, // Opcode: FLOAT_S +/* 2286 */ MCD_OPC_FilterValue, 1, 71, 11, 0, // Skip to: 5178 +/* 2291 */ MCD_OPC_CheckPredicate, 19, 66, 11, 0, // Skip to: 5178 +/* 2296 */ MCD_OPC_Decode, 204, 13, 40, // Opcode: MOVF_S +/* 2300 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 2336 +/* 2305 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 2308 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2322 +/* 2313 */ MCD_OPC_CheckPredicate, 18, 44, 11, 0, // Skip to: 5178 +/* 2318 */ MCD_OPC_Decode, 135, 15, 39, // Opcode: UFLOAT_S +/* 2322 */ MCD_OPC_FilterValue, 1, 35, 11, 0, // Skip to: 5178 +/* 2327 */ MCD_OPC_CheckPredicate, 19, 30, 11, 0, // Skip to: 5178 +/* 2332 */ MCD_OPC_Decode, 215, 13, 40, // Opcode: MOVT_S +/* 2336 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 2357 +/* 2341 */ MCD_OPC_CheckPredicate, 18, 16, 11, 0, // Skip to: 5178 +/* 2346 */ MCD_OPC_CheckField, 16, 1, 0, 9, 11, 0, // Skip to: 5178 +/* 2353 */ MCD_OPC_Decode, 143, 15, 37, // Opcode: UTRUNC_S +/* 2357 */ MCD_OPC_FilterValue, 15, 0, 11, 0, // Skip to: 5178 +/* 2362 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 2365 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2386 +/* 2370 */ MCD_OPC_CheckPredicate, 18, 243, 10, 0, // Skip to: 5178 +/* 2375 */ MCD_OPC_CheckField, 16, 1, 0, 236, 10, 0, // Skip to: 5178 +/* 2382 */ MCD_OPC_Decode, 217, 13, 41, // Opcode: MOV_S +/* 2386 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2407 +/* 2391 */ MCD_OPC_CheckPredicate, 18, 222, 10, 0, // Skip to: 5178 +/* 2396 */ MCD_OPC_CheckField, 16, 1, 0, 215, 10, 0, // Skip to: 5178 +/* 2403 */ MCD_OPC_Decode, 198, 4, 41, // Opcode: ABS_S +/* 2407 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2428 +/* 2412 */ MCD_OPC_CheckPredicate, 18, 201, 10, 0, // Skip to: 5178 +/* 2417 */ MCD_OPC_CheckField, 16, 1, 0, 194, 10, 0, // Skip to: 5178 +/* 2424 */ MCD_OPC_Decode, 197, 11, 42, // Opcode: CONST_S +/* 2428 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2449 +/* 2433 */ MCD_OPC_CheckPredicate, 18, 180, 10, 0, // Skip to: 5178 +/* 2438 */ MCD_OPC_CheckField, 16, 1, 0, 173, 10, 0, // Skip to: 5178 +/* 2445 */ MCD_OPC_Decode, 186, 14, 43, // Opcode: RFR +/* 2449 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 2470 +/* 2454 */ MCD_OPC_CheckPredicate, 18, 159, 10, 0, // Skip to: 5178 +/* 2459 */ MCD_OPC_CheckField, 16, 1, 0, 152, 10, 0, // Skip to: 5178 +/* 2466 */ MCD_OPC_Decode, 147, 15, 44, // Opcode: WFR +/* 2470 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2491 +/* 2475 */ MCD_OPC_CheckPredicate, 18, 138, 10, 0, // Skip to: 5178 +/* 2480 */ MCD_OPC_CheckField, 16, 1, 0, 131, 10, 0, // Skip to: 5178 +/* 2487 */ MCD_OPC_Decode, 162, 14, 41, // Opcode: NEG_S +/* 2491 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 2512 +/* 2496 */ MCD_OPC_CheckPredicate, 18, 117, 10, 0, // Skip to: 5178 +/* 2501 */ MCD_OPC_CheckField, 16, 1, 0, 110, 10, 0, // Skip to: 5178 +/* 2508 */ MCD_OPC_Decode, 198, 11, 41, // Opcode: DIV0_S +/* 2512 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 2533 +/* 2517 */ MCD_OPC_CheckPredicate, 18, 96, 10, 0, // Skip to: 5178 +/* 2522 */ MCD_OPC_CheckField, 16, 1, 0, 89, 10, 0, // Skip to: 5178 +/* 2529 */ MCD_OPC_Decode, 175, 14, 41, // Opcode: RECIP0_S +/* 2533 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 2554 +/* 2538 */ MCD_OPC_CheckPredicate, 18, 75, 10, 0, // Skip to: 5178 +/* 2543 */ MCD_OPC_CheckField, 16, 1, 0, 68, 10, 0, // Skip to: 5178 +/* 2550 */ MCD_OPC_Decode, 241, 14, 41, // Opcode: SQRT0_S +/* 2554 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 2575 +/* 2559 */ MCD_OPC_CheckPredicate, 18, 54, 10, 0, // Skip to: 5178 +/* 2564 */ MCD_OPC_CheckField, 16, 1, 0, 47, 10, 0, // Skip to: 5178 +/* 2571 */ MCD_OPC_Decode, 192, 14, 41, // Opcode: RSQRT0_S +/* 2575 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 2596 +/* 2580 */ MCD_OPC_CheckPredicate, 18, 33, 10, 0, // Skip to: 5178 +/* 2585 */ MCD_OPC_CheckField, 16, 1, 0, 26, 10, 0, // Skip to: 5178 +/* 2592 */ MCD_OPC_Decode, 163, 14, 41, // Opcode: NEXP01_S +/* 2596 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 2617 +/* 2601 */ MCD_OPC_CheckPredicate, 18, 12, 10, 0, // Skip to: 5178 +/* 2606 */ MCD_OPC_CheckField, 16, 1, 0, 5, 10, 0, // Skip to: 5178 +/* 2613 */ MCD_OPC_Decode, 200, 13, 41, // Opcode: MKSADJ_S +/* 2617 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 2638 +/* 2622 */ MCD_OPC_CheckPredicate, 18, 247, 9, 0, // Skip to: 5178 +/* 2627 */ MCD_OPC_CheckField, 16, 1, 0, 240, 9, 0, // Skip to: 5178 +/* 2634 */ MCD_OPC_Decode, 199, 13, 45, // Opcode: MKDADJ_S +/* 2638 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 2659 +/* 2643 */ MCD_OPC_CheckPredicate, 18, 226, 9, 0, // Skip to: 5178 +/* 2648 */ MCD_OPC_CheckField, 16, 1, 0, 219, 9, 0, // Skip to: 5178 +/* 2655 */ MCD_OPC_Decode, 201, 4, 45, // Opcode: ADDEXP_S +/* 2659 */ MCD_OPC_FilterValue, 15, 210, 9, 0, // Skip to: 5178 +/* 2664 */ MCD_OPC_CheckPredicate, 18, 205, 9, 0, // Skip to: 5178 +/* 2669 */ MCD_OPC_CheckField, 16, 1, 0, 198, 9, 0, // Skip to: 5178 +/* 2676 */ MCD_OPC_Decode, 200, 4, 45, // Opcode: ADDEXPM_S +/* 2680 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2689 +/* 2685 */ MCD_OPC_Decode, 180, 13, 46, // Opcode: L32R +/* 2689 */ MCD_OPC_FilterValue, 2, 107, 0, 0, // Skip to: 2801 +/* 2694 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2697 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2706 +/* 2702 */ MCD_OPC_Decode, 181, 13, 47, // Opcode: L8UI +/* 2706 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2715 +/* 2711 */ MCD_OPC_Decode, 176, 13, 48, // Opcode: L16UI +/* 2715 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2724 +/* 2720 */ MCD_OPC_Decode, 178, 13, 49, // Opcode: L32I +/* 2724 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 2733 +/* 2729 */ MCD_OPC_Decode, 235, 14, 47, // Opcode: S8I +/* 2733 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 2742 +/* 2738 */ MCD_OPC_Decode, 230, 14, 48, // Opcode: S16I +/* 2742 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 2751 +/* 2747 */ MCD_OPC_Decode, 233, 14, 49, // Opcode: S32I +/* 2751 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 2760 +/* 2756 */ MCD_OPC_Decode, 175, 13, 48, // Opcode: L16SI +/* 2760 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 2769 +/* 2765 */ MCD_OPC_Decode, 207, 13, 50, // Opcode: MOVI +/* 2769 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 2778 +/* 2774 */ MCD_OPC_Decode, 202, 4, 51, // Opcode: ADDI +/* 2778 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 2787 +/* 2783 */ MCD_OPC_Decode, 204, 4, 52, // Opcode: ADDMI +/* 2787 */ MCD_OPC_FilterValue, 14, 82, 9, 0, // Skip to: 5178 +/* 2792 */ MCD_OPC_CheckPredicate, 20, 77, 9, 0, // Skip to: 5178 +/* 2797 */ MCD_OPC_Decode, 231, 14, 53, // Opcode: S32C1I +/* 2801 */ MCD_OPC_FilterValue, 3, 59, 0, 0, // Skip to: 2865 +/* 2806 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2809 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2823 +/* 2814 */ MCD_OPC_CheckPredicate, 18, 55, 9, 0, // Skip to: 5178 +/* 2819 */ MCD_OPC_Decode, 188, 13, 54, // Opcode: LSI +/* 2823 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2837 +/* 2828 */ MCD_OPC_CheckPredicate, 18, 41, 9, 0, // Skip to: 5178 +/* 2833 */ MCD_OPC_Decode, 249, 14, 54, // Opcode: SSI +/* 2837 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2851 +/* 2842 */ MCD_OPC_CheckPredicate, 18, 27, 9, 0, // Skip to: 5178 +/* 2847 */ MCD_OPC_Decode, 189, 13, 55, // Opcode: LSIP +/* 2851 */ MCD_OPC_FilterValue, 12, 18, 9, 0, // Skip to: 5178 +/* 2856 */ MCD_OPC_CheckPredicate, 18, 13, 9, 0, // Skip to: 5178 +/* 2861 */ MCD_OPC_Decode, 250, 14, 56, // Opcode: SSIP +/* 2865 */ MCD_OPC_FilterValue, 4, 52, 7, 0, // Skip to: 4714 +/* 2870 */ MCD_OPC_ExtractField, 15, 9, // Inst{23-15} ... +/* 2873 */ MCD_OPC_FilterValue, 16, 23, 0, 0, // Skip to: 2901 +/* 2878 */ MCD_OPC_CheckPredicate, 21, 247, 8, 0, // Skip to: 5178 +/* 2883 */ MCD_OPC_CheckField, 7, 1, 0, 240, 8, 0, // Skip to: 5178 +/* 2890 */ MCD_OPC_CheckField, 4, 2, 0, 233, 8, 0, // Skip to: 5178 +/* 2897 */ MCD_OPC_Decode, 252, 13, 57, // Opcode: MULA_DD_LL_LDINC +/* 2901 */ MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 2929 +/* 2906 */ MCD_OPC_CheckPredicate, 21, 219, 8, 0, // Skip to: 5178 +/* 2911 */ MCD_OPC_CheckField, 7, 1, 0, 212, 8, 0, // Skip to: 5178 +/* 2918 */ MCD_OPC_CheckField, 4, 2, 0, 205, 8, 0, // Skip to: 5178 +/* 2925 */ MCD_OPC_Decode, 246, 13, 57, // Opcode: MULA_DD_HL_LDINC +/* 2929 */ MCD_OPC_FilterValue, 20, 23, 0, 0, // Skip to: 2957 +/* 2934 */ MCD_OPC_CheckPredicate, 21, 191, 8, 0, // Skip to: 5178 +/* 2939 */ MCD_OPC_CheckField, 7, 1, 0, 184, 8, 0, // Skip to: 5178 +/* 2946 */ MCD_OPC_CheckField, 4, 2, 0, 177, 8, 0, // Skip to: 5178 +/* 2953 */ MCD_OPC_Decode, 249, 13, 57, // Opcode: MULA_DD_LH_LDINC +/* 2957 */ MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 2985 +/* 2962 */ MCD_OPC_CheckPredicate, 21, 163, 8, 0, // Skip to: 5178 +/* 2967 */ MCD_OPC_CheckField, 7, 1, 0, 156, 8, 0, // Skip to: 5178 +/* 2974 */ MCD_OPC_CheckField, 4, 2, 0, 149, 8, 0, // Skip to: 5178 +/* 2981 */ MCD_OPC_Decode, 243, 13, 57, // Opcode: MULA_DD_HH_LDINC +/* 2985 */ MCD_OPC_FilterValue, 48, 23, 0, 0, // Skip to: 3013 +/* 2990 */ MCD_OPC_CheckPredicate, 21, 135, 8, 0, // Skip to: 5178 +/* 2995 */ MCD_OPC_CheckField, 7, 1, 0, 128, 8, 0, // Skip to: 5178 +/* 3002 */ MCD_OPC_CheckField, 4, 2, 0, 121, 8, 0, // Skip to: 5178 +/* 3009 */ MCD_OPC_Decode, 251, 13, 57, // Opcode: MULA_DD_LL_LDDEC +/* 3013 */ MCD_OPC_FilterValue, 50, 23, 0, 0, // Skip to: 3041 +/* 3018 */ MCD_OPC_CheckPredicate, 21, 107, 8, 0, // Skip to: 5178 +/* 3023 */ MCD_OPC_CheckField, 7, 1, 0, 100, 8, 0, // Skip to: 5178 +/* 3030 */ MCD_OPC_CheckField, 4, 2, 0, 93, 8, 0, // Skip to: 5178 +/* 3037 */ MCD_OPC_Decode, 245, 13, 57, // Opcode: MULA_DD_HL_LDDEC +/* 3041 */ MCD_OPC_FilterValue, 52, 23, 0, 0, // Skip to: 3069 +/* 3046 */ MCD_OPC_CheckPredicate, 21, 79, 8, 0, // Skip to: 5178 +/* 3051 */ MCD_OPC_CheckField, 7, 1, 0, 72, 8, 0, // Skip to: 5178 +/* 3058 */ MCD_OPC_CheckField, 4, 2, 0, 65, 8, 0, // Skip to: 5178 +/* 3065 */ MCD_OPC_Decode, 248, 13, 57, // Opcode: MULA_DD_LH_LDDEC +/* 3069 */ MCD_OPC_FilterValue, 54, 23, 0, 0, // Skip to: 3097 +/* 3074 */ MCD_OPC_CheckPredicate, 21, 51, 8, 0, // Skip to: 5178 +/* 3079 */ MCD_OPC_CheckField, 7, 1, 0, 44, 8, 0, // Skip to: 5178 +/* 3086 */ MCD_OPC_CheckField, 4, 2, 0, 37, 8, 0, // Skip to: 5178 +/* 3093 */ MCD_OPC_Decode, 242, 13, 57, // Opcode: MULA_DD_HH_LDDEC +/* 3097 */ MCD_OPC_FilterValue, 72, 23, 0, 0, // Skip to: 3125 +/* 3102 */ MCD_OPC_CheckPredicate, 21, 23, 8, 0, // Skip to: 5178 +/* 3107 */ MCD_OPC_CheckField, 7, 7, 0, 16, 8, 0, // Skip to: 5178 +/* 3114 */ MCD_OPC_CheckField, 4, 2, 0, 9, 8, 0, // Skip to: 5178 +/* 3121 */ MCD_OPC_Decode, 159, 14, 58, // Opcode: MUL_DD_LL +/* 3125 */ MCD_OPC_FilterValue, 74, 23, 0, 0, // Skip to: 3153 +/* 3130 */ MCD_OPC_CheckPredicate, 21, 251, 7, 0, // Skip to: 5178 +/* 3135 */ MCD_OPC_CheckField, 7, 7, 0, 244, 7, 0, // Skip to: 5178 +/* 3142 */ MCD_OPC_CheckField, 4, 2, 0, 237, 7, 0, // Skip to: 5178 +/* 3149 */ MCD_OPC_Decode, 157, 14, 58, // Opcode: MUL_DD_HL +/* 3153 */ MCD_OPC_FilterValue, 76, 23, 0, 0, // Skip to: 3181 +/* 3158 */ MCD_OPC_CheckPredicate, 21, 223, 7, 0, // Skip to: 5178 +/* 3163 */ MCD_OPC_CheckField, 7, 7, 0, 216, 7, 0, // Skip to: 5178 +/* 3170 */ MCD_OPC_CheckField, 4, 2, 0, 209, 7, 0, // Skip to: 5178 +/* 3177 */ MCD_OPC_Decode, 158, 14, 58, // Opcode: MUL_DD_LH +/* 3181 */ MCD_OPC_FilterValue, 78, 23, 0, 0, // Skip to: 3209 +/* 3186 */ MCD_OPC_CheckPredicate, 21, 195, 7, 0, // Skip to: 5178 +/* 3191 */ MCD_OPC_CheckField, 7, 7, 0, 188, 7, 0, // Skip to: 5178 +/* 3198 */ MCD_OPC_CheckField, 4, 2, 0, 181, 7, 0, // Skip to: 5178 +/* 3205 */ MCD_OPC_Decode, 156, 14, 58, // Opcode: MUL_DD_HH +/* 3209 */ MCD_OPC_FilterValue, 80, 23, 0, 0, // Skip to: 3237 +/* 3214 */ MCD_OPC_CheckPredicate, 21, 167, 7, 0, // Skip to: 5178 +/* 3219 */ MCD_OPC_CheckField, 7, 7, 0, 160, 7, 0, // Skip to: 5178 +/* 3226 */ MCD_OPC_CheckField, 4, 2, 0, 153, 7, 0, // Skip to: 5178 +/* 3233 */ MCD_OPC_Decode, 250, 13, 58, // Opcode: MULA_DD_LL +/* 3237 */ MCD_OPC_FilterValue, 82, 23, 0, 0, // Skip to: 3265 +/* 3242 */ MCD_OPC_CheckPredicate, 21, 139, 7, 0, // Skip to: 5178 +/* 3247 */ MCD_OPC_CheckField, 7, 7, 0, 132, 7, 0, // Skip to: 5178 +/* 3254 */ MCD_OPC_CheckField, 4, 2, 0, 125, 7, 0, // Skip to: 5178 +/* 3261 */ MCD_OPC_Decode, 244, 13, 58, // Opcode: MULA_DD_HL +/* 3265 */ MCD_OPC_FilterValue, 84, 23, 0, 0, // Skip to: 3293 +/* 3270 */ MCD_OPC_CheckPredicate, 21, 111, 7, 0, // Skip to: 5178 +/* 3275 */ MCD_OPC_CheckField, 7, 7, 0, 104, 7, 0, // Skip to: 5178 +/* 3282 */ MCD_OPC_CheckField, 4, 2, 0, 97, 7, 0, // Skip to: 5178 +/* 3289 */ MCD_OPC_Decode, 247, 13, 58, // Opcode: MULA_DD_LH +/* 3293 */ MCD_OPC_FilterValue, 86, 23, 0, 0, // Skip to: 3321 +/* 3298 */ MCD_OPC_CheckPredicate, 21, 83, 7, 0, // Skip to: 5178 +/* 3303 */ MCD_OPC_CheckField, 7, 7, 0, 76, 7, 0, // Skip to: 5178 +/* 3310 */ MCD_OPC_CheckField, 4, 2, 0, 69, 7, 0, // Skip to: 5178 +/* 3317 */ MCD_OPC_Decode, 241, 13, 58, // Opcode: MULA_DD_HH +/* 3321 */ MCD_OPC_FilterValue, 88, 23, 0, 0, // Skip to: 3349 +/* 3326 */ MCD_OPC_CheckPredicate, 21, 55, 7, 0, // Skip to: 5178 +/* 3331 */ MCD_OPC_CheckField, 7, 7, 0, 48, 7, 0, // Skip to: 5178 +/* 3338 */ MCD_OPC_CheckField, 4, 2, 0, 41, 7, 0, // Skip to: 5178 +/* 3345 */ MCD_OPC_Decode, 142, 14, 58, // Opcode: MULS_DD_LL +/* 3349 */ MCD_OPC_FilterValue, 90, 23, 0, 0, // Skip to: 3377 +/* 3354 */ MCD_OPC_CheckPredicate, 21, 27, 7, 0, // Skip to: 5178 +/* 3359 */ MCD_OPC_CheckField, 7, 7, 0, 20, 7, 0, // Skip to: 5178 +/* 3366 */ MCD_OPC_CheckField, 4, 2, 0, 13, 7, 0, // Skip to: 5178 +/* 3373 */ MCD_OPC_Decode, 140, 14, 58, // Opcode: MULS_DD_HL +/* 3377 */ MCD_OPC_FilterValue, 92, 23, 0, 0, // Skip to: 3405 +/* 3382 */ MCD_OPC_CheckPredicate, 21, 255, 6, 0, // Skip to: 5178 +/* 3387 */ MCD_OPC_CheckField, 7, 7, 0, 248, 6, 0, // Skip to: 5178 +/* 3394 */ MCD_OPC_CheckField, 4, 2, 0, 241, 6, 0, // Skip to: 5178 +/* 3401 */ MCD_OPC_Decode, 141, 14, 58, // Opcode: MULS_DD_LH +/* 3405 */ MCD_OPC_FilterValue, 94, 23, 0, 0, // Skip to: 3433 +/* 3410 */ MCD_OPC_CheckPredicate, 21, 227, 6, 0, // Skip to: 5178 +/* 3415 */ MCD_OPC_CheckField, 7, 7, 0, 220, 6, 0, // Skip to: 5178 +/* 3422 */ MCD_OPC_CheckField, 4, 2, 0, 213, 6, 0, // Skip to: 5178 +/* 3429 */ MCD_OPC_Decode, 139, 14, 58, // Opcode: MULS_DD_HH +/* 3433 */ MCD_OPC_FilterValue, 104, 30, 0, 0, // Skip to: 3468 +/* 3438 */ MCD_OPC_CheckPredicate, 21, 199, 6, 0, // Skip to: 5178 +/* 3443 */ MCD_OPC_CheckField, 12, 3, 0, 192, 6, 0, // Skip to: 5178 +/* 3450 */ MCD_OPC_CheckField, 7, 1, 0, 185, 6, 0, // Skip to: 5178 +/* 3457 */ MCD_OPC_CheckField, 4, 2, 0, 178, 6, 0, // Skip to: 5178 +/* 3464 */ MCD_OPC_Decode, 151, 14, 59, // Opcode: MUL_AD_LL +/* 3468 */ MCD_OPC_FilterValue, 106, 30, 0, 0, // Skip to: 3503 +/* 3473 */ MCD_OPC_CheckPredicate, 21, 164, 6, 0, // Skip to: 5178 +/* 3478 */ MCD_OPC_CheckField, 12, 3, 0, 157, 6, 0, // Skip to: 5178 +/* 3485 */ MCD_OPC_CheckField, 7, 1, 0, 150, 6, 0, // Skip to: 5178 +/* 3492 */ MCD_OPC_CheckField, 4, 2, 0, 143, 6, 0, // Skip to: 5178 +/* 3499 */ MCD_OPC_Decode, 149, 14, 59, // Opcode: MUL_AD_HL +/* 3503 */ MCD_OPC_FilterValue, 108, 30, 0, 0, // Skip to: 3538 +/* 3508 */ MCD_OPC_CheckPredicate, 21, 129, 6, 0, // Skip to: 5178 +/* 3513 */ MCD_OPC_CheckField, 12, 3, 0, 122, 6, 0, // Skip to: 5178 +/* 3520 */ MCD_OPC_CheckField, 7, 1, 0, 115, 6, 0, // Skip to: 5178 +/* 3527 */ MCD_OPC_CheckField, 4, 2, 0, 108, 6, 0, // Skip to: 5178 +/* 3534 */ MCD_OPC_Decode, 150, 14, 59, // Opcode: MUL_AD_LH +/* 3538 */ MCD_OPC_FilterValue, 110, 30, 0, 0, // Skip to: 3573 +/* 3543 */ MCD_OPC_CheckPredicate, 21, 94, 6, 0, // Skip to: 5178 +/* 3548 */ MCD_OPC_CheckField, 12, 3, 0, 87, 6, 0, // Skip to: 5178 +/* 3555 */ MCD_OPC_CheckField, 7, 1, 0, 80, 6, 0, // Skip to: 5178 +/* 3562 */ MCD_OPC_CheckField, 4, 2, 0, 73, 6, 0, // Skip to: 5178 +/* 3569 */ MCD_OPC_Decode, 148, 14, 59, // Opcode: MUL_AD_HH +/* 3573 */ MCD_OPC_FilterValue, 112, 30, 0, 0, // Skip to: 3608 +/* 3578 */ MCD_OPC_CheckPredicate, 21, 59, 6, 0, // Skip to: 5178 +/* 3583 */ MCD_OPC_CheckField, 12, 3, 0, 52, 6, 0, // Skip to: 5178 +/* 3590 */ MCD_OPC_CheckField, 7, 1, 0, 45, 6, 0, // Skip to: 5178 +/* 3597 */ MCD_OPC_CheckField, 4, 2, 0, 38, 6, 0, // Skip to: 5178 +/* 3604 */ MCD_OPC_Decode, 228, 13, 59, // Opcode: MULA_AD_LL +/* 3608 */ MCD_OPC_FilterValue, 114, 30, 0, 0, // Skip to: 3643 +/* 3613 */ MCD_OPC_CheckPredicate, 21, 24, 6, 0, // Skip to: 5178 +/* 3618 */ MCD_OPC_CheckField, 12, 3, 0, 17, 6, 0, // Skip to: 5178 +/* 3625 */ MCD_OPC_CheckField, 7, 1, 0, 10, 6, 0, // Skip to: 5178 +/* 3632 */ MCD_OPC_CheckField, 4, 2, 0, 3, 6, 0, // Skip to: 5178 +/* 3639 */ MCD_OPC_Decode, 226, 13, 59, // Opcode: MULA_AD_HL +/* 3643 */ MCD_OPC_FilterValue, 116, 30, 0, 0, // Skip to: 3678 +/* 3648 */ MCD_OPC_CheckPredicate, 21, 245, 5, 0, // Skip to: 5178 +/* 3653 */ MCD_OPC_CheckField, 12, 3, 0, 238, 5, 0, // Skip to: 5178 +/* 3660 */ MCD_OPC_CheckField, 7, 1, 0, 231, 5, 0, // Skip to: 5178 +/* 3667 */ MCD_OPC_CheckField, 4, 2, 0, 224, 5, 0, // Skip to: 5178 +/* 3674 */ MCD_OPC_Decode, 227, 13, 59, // Opcode: MULA_AD_LH +/* 3678 */ MCD_OPC_FilterValue, 118, 30, 0, 0, // Skip to: 3713 +/* 3683 */ MCD_OPC_CheckPredicate, 21, 210, 5, 0, // Skip to: 5178 +/* 3688 */ MCD_OPC_CheckField, 12, 3, 0, 203, 5, 0, // Skip to: 5178 +/* 3695 */ MCD_OPC_CheckField, 7, 1, 0, 196, 5, 0, // Skip to: 5178 +/* 3702 */ MCD_OPC_CheckField, 4, 2, 0, 189, 5, 0, // Skip to: 5178 +/* 3709 */ MCD_OPC_Decode, 225, 13, 59, // Opcode: MULA_AD_HH +/* 3713 */ MCD_OPC_FilterValue, 120, 30, 0, 0, // Skip to: 3748 +/* 3718 */ MCD_OPC_CheckPredicate, 21, 175, 5, 0, // Skip to: 5178 +/* 3723 */ MCD_OPC_CheckField, 12, 3, 0, 168, 5, 0, // Skip to: 5178 +/* 3730 */ MCD_OPC_CheckField, 7, 1, 0, 161, 5, 0, // Skip to: 5178 +/* 3737 */ MCD_OPC_CheckField, 4, 2, 0, 154, 5, 0, // Skip to: 5178 +/* 3744 */ MCD_OPC_Decode, 134, 14, 59, // Opcode: MULS_AD_LL +/* 3748 */ MCD_OPC_FilterValue, 122, 30, 0, 0, // Skip to: 3783 +/* 3753 */ MCD_OPC_CheckPredicate, 21, 140, 5, 0, // Skip to: 5178 +/* 3758 */ MCD_OPC_CheckField, 12, 3, 0, 133, 5, 0, // Skip to: 5178 +/* 3765 */ MCD_OPC_CheckField, 7, 1, 0, 126, 5, 0, // Skip to: 5178 +/* 3772 */ MCD_OPC_CheckField, 4, 2, 0, 119, 5, 0, // Skip to: 5178 +/* 3779 */ MCD_OPC_Decode, 132, 14, 59, // Opcode: MULS_AD_HL +/* 3783 */ MCD_OPC_FilterValue, 124, 30, 0, 0, // Skip to: 3818 +/* 3788 */ MCD_OPC_CheckPredicate, 21, 105, 5, 0, // Skip to: 5178 +/* 3793 */ MCD_OPC_CheckField, 12, 3, 0, 98, 5, 0, // Skip to: 5178 +/* 3800 */ MCD_OPC_CheckField, 7, 1, 0, 91, 5, 0, // Skip to: 5178 +/* 3807 */ MCD_OPC_CheckField, 4, 2, 0, 84, 5, 0, // Skip to: 5178 +/* 3814 */ MCD_OPC_Decode, 133, 14, 59, // Opcode: MULS_AD_LH +/* 3818 */ MCD_OPC_FilterValue, 126, 30, 0, 0, // Skip to: 3853 +/* 3823 */ MCD_OPC_CheckPredicate, 21, 70, 5, 0, // Skip to: 5178 +/* 3828 */ MCD_OPC_CheckField, 12, 3, 0, 63, 5, 0, // Skip to: 5178 +/* 3835 */ MCD_OPC_CheckField, 7, 1, 0, 56, 5, 0, // Skip to: 5178 +/* 3842 */ MCD_OPC_CheckField, 4, 2, 0, 49, 5, 0, // Skip to: 5178 +/* 3849 */ MCD_OPC_Decode, 131, 14, 59, // Opcode: MULS_AD_HH +/* 3853 */ MCD_OPC_FilterValue, 144, 1, 9, 0, 0, // Skip to: 3868 +/* 3859 */ MCD_OPC_CheckPredicate, 21, 34, 5, 0, // Skip to: 5178 +/* 3864 */ MCD_OPC_Decode, 240, 13, 60, // Opcode: MULA_DA_LL_LDINC +/* 3868 */ MCD_OPC_FilterValue, 146, 1, 9, 0, 0, // Skip to: 3883 +/* 3874 */ MCD_OPC_CheckPredicate, 21, 19, 5, 0, // Skip to: 5178 +/* 3879 */ MCD_OPC_Decode, 234, 13, 60, // Opcode: MULA_DA_HL_LDINC +/* 3883 */ MCD_OPC_FilterValue, 148, 1, 9, 0, 0, // Skip to: 3898 +/* 3889 */ MCD_OPC_CheckPredicate, 21, 4, 5, 0, // Skip to: 5178 +/* 3894 */ MCD_OPC_Decode, 237, 13, 60, // Opcode: MULA_DA_LH_LDINC +/* 3898 */ MCD_OPC_FilterValue, 150, 1, 9, 0, 0, // Skip to: 3913 +/* 3904 */ MCD_OPC_CheckPredicate, 21, 245, 4, 0, // Skip to: 5178 +/* 3909 */ MCD_OPC_Decode, 231, 13, 60, // Opcode: MULA_DA_HH_LDINC +/* 3913 */ MCD_OPC_FilterValue, 176, 1, 9, 0, 0, // Skip to: 3928 +/* 3919 */ MCD_OPC_CheckPredicate, 21, 230, 4, 0, // Skip to: 5178 +/* 3924 */ MCD_OPC_Decode, 239, 13, 61, // Opcode: MULA_DA_LL_LDDEC +/* 3928 */ MCD_OPC_FilterValue, 178, 1, 9, 0, 0, // Skip to: 3943 +/* 3934 */ MCD_OPC_CheckPredicate, 21, 215, 4, 0, // Skip to: 5178 +/* 3939 */ MCD_OPC_Decode, 233, 13, 61, // Opcode: MULA_DA_HL_LDDEC +/* 3943 */ MCD_OPC_FilterValue, 180, 1, 9, 0, 0, // Skip to: 3958 +/* 3949 */ MCD_OPC_CheckPredicate, 21, 200, 4, 0, // Skip to: 5178 +/* 3954 */ MCD_OPC_Decode, 236, 13, 61, // Opcode: MULA_DA_LH_LDDEC +/* 3958 */ MCD_OPC_FilterValue, 182, 1, 9, 0, 0, // Skip to: 3973 +/* 3964 */ MCD_OPC_CheckPredicate, 21, 185, 4, 0, // Skip to: 5178 +/* 3969 */ MCD_OPC_Decode, 230, 13, 61, // Opcode: MULA_DA_HH_LDDEC +/* 3973 */ MCD_OPC_FilterValue, 200, 1, 16, 0, 0, // Skip to: 3995 +/* 3979 */ MCD_OPC_CheckPredicate, 21, 170, 4, 0, // Skip to: 5178 +/* 3984 */ MCD_OPC_CheckField, 8, 6, 0, 163, 4, 0, // Skip to: 5178 +/* 3991 */ MCD_OPC_Decode, 155, 14, 62, // Opcode: MUL_DA_LL +/* 3995 */ MCD_OPC_FilterValue, 202, 1, 38, 0, 0, // Skip to: 4039 +/* 4001 */ MCD_OPC_ExtractField, 8, 6, // Inst{13-8} ... +/* 4004 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4018 +/* 4009 */ MCD_OPC_CheckPredicate, 21, 140, 4, 0, // Skip to: 5178 +/* 4014 */ MCD_OPC_Decode, 153, 14, 62, // Opcode: MUL_DA_HL +/* 4018 */ MCD_OPC_FilterValue, 8, 131, 4, 0, // Skip to: 5178 +/* 4023 */ MCD_OPC_CheckPredicate, 22, 126, 4, 0, // Skip to: 5178 +/* 4028 */ MCD_OPC_CheckField, 14, 1, 0, 119, 4, 0, // Skip to: 5178 +/* 4035 */ MCD_OPC_Decode, 216, 11, 25, // Opcode: EE_GET_GPIO_IN +/* 4039 */ MCD_OPC_FilterValue, 204, 1, 16, 0, 0, // Skip to: 4061 +/* 4045 */ MCD_OPC_CheckPredicate, 21, 104, 4, 0, // Skip to: 5178 +/* 4050 */ MCD_OPC_CheckField, 8, 6, 0, 97, 4, 0, // Skip to: 5178 +/* 4057 */ MCD_OPC_Decode, 154, 14, 62, // Opcode: MUL_DA_LH +/* 4061 */ MCD_OPC_FilterValue, 206, 1, 16, 0, 0, // Skip to: 4083 +/* 4067 */ MCD_OPC_CheckPredicate, 21, 82, 4, 0, // Skip to: 5178 +/* 4072 */ MCD_OPC_CheckField, 8, 6, 0, 75, 4, 0, // Skip to: 5178 +/* 4079 */ MCD_OPC_Decode, 152, 14, 62, // Opcode: MUL_DA_HH +/* 4083 */ MCD_OPC_FilterValue, 208, 1, 16, 0, 0, // Skip to: 4105 +/* 4089 */ MCD_OPC_CheckPredicate, 21, 60, 4, 0, // Skip to: 5178 +/* 4094 */ MCD_OPC_CheckField, 8, 6, 0, 53, 4, 0, // Skip to: 5178 +/* 4101 */ MCD_OPC_Decode, 238, 13, 62, // Opcode: MULA_DA_LL +/* 4105 */ MCD_OPC_FilterValue, 210, 1, 16, 0, 0, // Skip to: 4127 +/* 4111 */ MCD_OPC_CheckPredicate, 21, 38, 4, 0, // Skip to: 5178 +/* 4116 */ MCD_OPC_CheckField, 8, 6, 0, 31, 4, 0, // Skip to: 5178 +/* 4123 */ MCD_OPC_Decode, 232, 13, 62, // Opcode: MULA_DA_HL +/* 4127 */ MCD_OPC_FilterValue, 212, 1, 16, 0, 0, // Skip to: 4149 +/* 4133 */ MCD_OPC_CheckPredicate, 21, 16, 4, 0, // Skip to: 5178 +/* 4138 */ MCD_OPC_CheckField, 8, 6, 0, 9, 4, 0, // Skip to: 5178 +/* 4145 */ MCD_OPC_Decode, 235, 13, 62, // Opcode: MULA_DA_LH +/* 4149 */ MCD_OPC_FilterValue, 214, 1, 16, 0, 0, // Skip to: 4171 +/* 4155 */ MCD_OPC_CheckPredicate, 21, 250, 3, 0, // Skip to: 5178 +/* 4160 */ MCD_OPC_CheckField, 8, 6, 0, 243, 3, 0, // Skip to: 5178 +/* 4167 */ MCD_OPC_Decode, 229, 13, 62, // Opcode: MULA_DA_HH +/* 4171 */ MCD_OPC_FilterValue, 216, 1, 16, 0, 0, // Skip to: 4193 +/* 4177 */ MCD_OPC_CheckPredicate, 21, 228, 3, 0, // Skip to: 5178 +/* 4182 */ MCD_OPC_CheckField, 8, 6, 0, 221, 3, 0, // Skip to: 5178 +/* 4189 */ MCD_OPC_Decode, 138, 14, 62, // Opcode: MULS_DA_LL +/* 4193 */ MCD_OPC_FilterValue, 218, 1, 16, 0, 0, // Skip to: 4215 +/* 4199 */ MCD_OPC_CheckPredicate, 21, 206, 3, 0, // Skip to: 5178 +/* 4204 */ MCD_OPC_CheckField, 8, 6, 0, 199, 3, 0, // Skip to: 5178 +/* 4211 */ MCD_OPC_Decode, 136, 14, 62, // Opcode: MULS_DA_HL +/* 4215 */ MCD_OPC_FilterValue, 220, 1, 16, 0, 0, // Skip to: 4237 +/* 4221 */ MCD_OPC_CheckPredicate, 21, 184, 3, 0, // Skip to: 5178 +/* 4226 */ MCD_OPC_CheckField, 8, 6, 0, 177, 3, 0, // Skip to: 5178 +/* 4233 */ MCD_OPC_Decode, 137, 14, 62, // Opcode: MULS_DA_LH +/* 4237 */ MCD_OPC_FilterValue, 222, 1, 16, 0, 0, // Skip to: 4259 +/* 4243 */ MCD_OPC_CheckPredicate, 21, 162, 3, 0, // Skip to: 5178 +/* 4248 */ MCD_OPC_CheckField, 8, 6, 0, 155, 3, 0, // Skip to: 5178 +/* 4255 */ MCD_OPC_Decode, 135, 14, 62, // Opcode: MULS_DA_HH +/* 4259 */ MCD_OPC_FilterValue, 224, 1, 16, 0, 0, // Skip to: 4281 +/* 4265 */ MCD_OPC_CheckPredicate, 21, 140, 3, 0, // Skip to: 5178 +/* 4270 */ MCD_OPC_CheckField, 12, 3, 0, 133, 3, 0, // Skip to: 5178 +/* 4277 */ MCD_OPC_Decode, 141, 15, 29, // Opcode: UMUL_AA_LL +/* 4281 */ MCD_OPC_FilterValue, 226, 1, 16, 0, 0, // Skip to: 4303 +/* 4287 */ MCD_OPC_CheckPredicate, 21, 118, 3, 0, // Skip to: 5178 +/* 4292 */ MCD_OPC_CheckField, 12, 3, 0, 111, 3, 0, // Skip to: 5178 +/* 4299 */ MCD_OPC_Decode, 139, 15, 29, // Opcode: UMUL_AA_HL +/* 4303 */ MCD_OPC_FilterValue, 228, 1, 31, 0, 0, // Skip to: 4340 +/* 4309 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 4312 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4326 +/* 4317 */ MCD_OPC_CheckPredicate, 21, 88, 3, 0, // Skip to: 5178 +/* 4322 */ MCD_OPC_Decode, 140, 15, 29, // Opcode: UMUL_AA_LH +/* 4326 */ MCD_OPC_FilterValue, 4, 79, 3, 0, // Skip to: 5178 +/* 4331 */ MCD_OPC_CheckPredicate, 22, 74, 3, 0, // Skip to: 5178 +/* 4336 */ MCD_OPC_Decode, 157, 13, 5, // Opcode: EE_WR_MASK_GPIO_OUT +/* 4340 */ MCD_OPC_FilterValue, 230, 1, 16, 0, 0, // Skip to: 4362 +/* 4346 */ MCD_OPC_CheckPredicate, 21, 59, 3, 0, // Skip to: 5178 +/* 4351 */ MCD_OPC_CheckField, 12, 3, 0, 52, 3, 0, // Skip to: 5178 +/* 4358 */ MCD_OPC_Decode, 138, 15, 29, // Opcode: UMUL_AA_HH +/* 4362 */ MCD_OPC_FilterValue, 232, 1, 16, 0, 0, // Skip to: 4384 +/* 4368 */ MCD_OPC_CheckPredicate, 21, 37, 3, 0, // Skip to: 5178 +/* 4373 */ MCD_OPC_CheckField, 12, 3, 0, 30, 3, 0, // Skip to: 5178 +/* 4380 */ MCD_OPC_Decode, 147, 14, 29, // Opcode: MUL_AA_LL +/* 4384 */ MCD_OPC_FilterValue, 234, 1, 31, 0, 0, // Skip to: 4421 +/* 4390 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 4393 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4407 +/* 4398 */ MCD_OPC_CheckPredicate, 21, 7, 3, 0, // Skip to: 5178 +/* 4403 */ MCD_OPC_Decode, 145, 14, 29, // Opcode: MUL_AA_HL +/* 4407 */ MCD_OPC_FilterValue, 4, 254, 2, 0, // Skip to: 5178 +/* 4412 */ MCD_OPC_CheckPredicate, 22, 249, 2, 0, // Skip to: 5178 +/* 4417 */ MCD_OPC_Decode, 246, 11, 28, // Opcode: EE_SET_BIT_GPIO_OUT +/* 4421 */ MCD_OPC_FilterValue, 236, 1, 31, 0, 0, // Skip to: 4458 +/* 4427 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 4430 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4444 +/* 4435 */ MCD_OPC_CheckPredicate, 21, 226, 2, 0, // Skip to: 5178 +/* 4440 */ MCD_OPC_Decode, 146, 14, 29, // Opcode: MUL_AA_LH +/* 4444 */ MCD_OPC_FilterValue, 4, 217, 2, 0, // Skip to: 5178 +/* 4449 */ MCD_OPC_CheckPredicate, 22, 212, 2, 0, // Skip to: 5178 +/* 4454 */ MCD_OPC_Decode, 203, 11, 28, // Opcode: EE_CLR_BIT_GPIO_OUT +/* 4458 */ MCD_OPC_FilterValue, 238, 1, 16, 0, 0, // Skip to: 4480 +/* 4464 */ MCD_OPC_CheckPredicate, 21, 197, 2, 0, // Skip to: 5178 +/* 4469 */ MCD_OPC_CheckField, 12, 3, 0, 190, 2, 0, // Skip to: 5178 +/* 4476 */ MCD_OPC_Decode, 144, 14, 29, // Opcode: MUL_AA_HH +/* 4480 */ MCD_OPC_FilterValue, 240, 1, 16, 0, 0, // Skip to: 4502 +/* 4486 */ MCD_OPC_CheckPredicate, 21, 175, 2, 0, // Skip to: 5178 +/* 4491 */ MCD_OPC_CheckField, 12, 3, 0, 168, 2, 0, // Skip to: 5178 +/* 4498 */ MCD_OPC_Decode, 224, 13, 29, // Opcode: MULA_AA_LL +/* 4502 */ MCD_OPC_FilterValue, 242, 1, 16, 0, 0, // Skip to: 4524 +/* 4508 */ MCD_OPC_CheckPredicate, 21, 153, 2, 0, // Skip to: 5178 +/* 4513 */ MCD_OPC_CheckField, 12, 3, 0, 146, 2, 0, // Skip to: 5178 +/* 4520 */ MCD_OPC_Decode, 222, 13, 29, // Opcode: MULA_AA_HL +/* 4524 */ MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 4546 +/* 4530 */ MCD_OPC_CheckPredicate, 21, 131, 2, 0, // Skip to: 5178 +/* 4535 */ MCD_OPC_CheckField, 12, 3, 0, 124, 2, 0, // Skip to: 5178 +/* 4542 */ MCD_OPC_Decode, 223, 13, 29, // Opcode: MULA_AA_LH +/* 4546 */ MCD_OPC_FilterValue, 246, 1, 16, 0, 0, // Skip to: 4568 +/* 4552 */ MCD_OPC_CheckPredicate, 21, 109, 2, 0, // Skip to: 5178 +/* 4557 */ MCD_OPC_CheckField, 12, 3, 0, 102, 2, 0, // Skip to: 5178 +/* 4564 */ MCD_OPC_Decode, 221, 13, 29, // Opcode: MULA_AA_HH +/* 4568 */ MCD_OPC_FilterValue, 248, 1, 16, 0, 0, // Skip to: 4590 +/* 4574 */ MCD_OPC_CheckPredicate, 21, 87, 2, 0, // Skip to: 5178 +/* 4579 */ MCD_OPC_CheckField, 12, 3, 0, 80, 2, 0, // Skip to: 5178 +/* 4586 */ MCD_OPC_Decode, 130, 14, 29, // Opcode: MULS_AA_LL +/* 4590 */ MCD_OPC_FilterValue, 250, 1, 16, 0, 0, // Skip to: 4612 +/* 4596 */ MCD_OPC_CheckPredicate, 21, 65, 2, 0, // Skip to: 5178 +/* 4601 */ MCD_OPC_CheckField, 12, 3, 0, 58, 2, 0, // Skip to: 5178 +/* 4608 */ MCD_OPC_Decode, 128, 14, 29, // Opcode: MULS_AA_HL +/* 4612 */ MCD_OPC_FilterValue, 252, 1, 16, 0, 0, // Skip to: 4634 +/* 4618 */ MCD_OPC_CheckPredicate, 21, 43, 2, 0, // Skip to: 5178 +/* 4623 */ MCD_OPC_CheckField, 12, 3, 0, 36, 2, 0, // Skip to: 5178 +/* 4630 */ MCD_OPC_Decode, 129, 14, 29, // Opcode: MULS_AA_LH +/* 4634 */ MCD_OPC_FilterValue, 254, 1, 16, 0, 0, // Skip to: 4656 +/* 4640 */ MCD_OPC_CheckPredicate, 21, 21, 2, 0, // Skip to: 5178 +/* 4645 */ MCD_OPC_CheckField, 12, 3, 0, 14, 2, 0, // Skip to: 5178 +/* 4652 */ MCD_OPC_Decode, 255, 13, 29, // Opcode: MULS_AA_HH +/* 4656 */ MCD_OPC_FilterValue, 128, 2, 23, 0, 0, // Skip to: 4685 +/* 4662 */ MCD_OPC_CheckPredicate, 21, 255, 1, 0, // Skip to: 5178 +/* 4667 */ MCD_OPC_CheckField, 14, 1, 0, 248, 1, 0, // Skip to: 5178 +/* 4674 */ MCD_OPC_CheckField, 4, 4, 0, 241, 1, 0, // Skip to: 5178 +/* 4681 */ MCD_OPC_Decode, 183, 13, 63, // Opcode: LDINC +/* 4685 */ MCD_OPC_FilterValue, 160, 2, 231, 1, 0, // Skip to: 5178 +/* 4691 */ MCD_OPC_CheckPredicate, 21, 226, 1, 0, // Skip to: 5178 +/* 4696 */ MCD_OPC_CheckField, 14, 1, 0, 219, 1, 0, // Skip to: 5178 +/* 4703 */ MCD_OPC_CheckField, 4, 4, 0, 212, 1, 0, // Skip to: 5178 +/* 4710 */ MCD_OPC_Decode, 182, 13, 63, // Opcode: LDDEC +/* 4714 */ MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 4773 +/* 4719 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 4722 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4731 +/* 4727 */ MCD_OPC_Decode, 186, 11, 64, // Opcode: CALL0 +/* 4731 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4745 +/* 4736 */ MCD_OPC_CheckPredicate, 3, 181, 1, 0, // Skip to: 5178 +/* 4741 */ MCD_OPC_Decode, 188, 11, 64, // Opcode: CALL4 +/* 4745 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4759 +/* 4750 */ MCD_OPC_CheckPredicate, 3, 167, 1, 0, // Skip to: 5178 +/* 4755 */ MCD_OPC_Decode, 189, 11, 64, // Opcode: CALL8 +/* 4759 */ MCD_OPC_FilterValue, 3, 158, 1, 0, // Skip to: 5178 +/* 4764 */ MCD_OPC_CheckPredicate, 3, 153, 1, 0, // Skip to: 5178 +/* 4769 */ MCD_OPC_Decode, 187, 11, 64, // Opcode: CALL12 +/* 4773 */ MCD_OPC_FilterValue, 6, 218, 0, 0, // Skip to: 4996 +/* 4778 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 4781 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4790 +/* 4786 */ MCD_OPC_Decode, 173, 13, 65, // Opcode: J +/* 4790 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 4834 +/* 4795 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 4798 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4807 +/* 4803 */ MCD_OPC_Decode, 166, 11, 66, // Opcode: BEQZ +/* 4807 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4816 +/* 4812 */ MCD_OPC_Decode, 181, 11, 66, // Opcode: BNEZ +/* 4816 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4825 +/* 4821 */ MCD_OPC_Decode, 177, 11, 66, // Opcode: BLTZ +/* 4825 */ MCD_OPC_FilterValue, 3, 92, 1, 0, // Skip to: 5178 +/* 4830 */ MCD_OPC_Decode, 172, 11, 66, // Opcode: BGEZ +/* 4834 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 4878 +/* 4839 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 4842 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4851 +/* 4847 */ MCD_OPC_Decode, 165, 11, 67, // Opcode: BEQI +/* 4851 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4860 +/* 4856 */ MCD_OPC_Decode, 180, 11, 67, // Opcode: BNEI +/* 4860 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4869 +/* 4865 */ MCD_OPC_Decode, 174, 11, 67, // Opcode: BLTI +/* 4869 */ MCD_OPC_FilterValue, 3, 48, 1, 0, // Skip to: 5178 +/* 4874 */ MCD_OPC_Decode, 169, 11, 67, // Opcode: BGEI +/* 4878 */ MCD_OPC_FilterValue, 3, 39, 1, 0, // Skip to: 5178 +/* 4883 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 4886 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4900 +/* 4891 */ MCD_OPC_CheckPredicate, 3, 26, 1, 0, // Skip to: 5178 +/* 4896 */ MCD_OPC_Decode, 162, 13, 68, // Opcode: ENTRY +/* 4900 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 4978 +/* 4905 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4908 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4922 +/* 4913 */ MCD_OPC_CheckPredicate, 7, 4, 1, 0, // Skip to: 5178 +/* 4918 */ MCD_OPC_Decode, 167, 11, 69, // Opcode: BF +/* 4922 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4936 +/* 4927 */ MCD_OPC_CheckPredicate, 7, 246, 0, 0, // Skip to: 5178 +/* 4932 */ MCD_OPC_Decode, 185, 11, 69, // Opcode: BT +/* 4936 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 4950 +/* 4941 */ MCD_OPC_CheckPredicate, 23, 232, 0, 0, // Skip to: 5178 +/* 4946 */ MCD_OPC_Decode, 185, 13, 70, // Opcode: LOOP +/* 4950 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 4964 +/* 4955 */ MCD_OPC_CheckPredicate, 23, 218, 0, 0, // Skip to: 5178 +/* 4960 */ MCD_OPC_Decode, 187, 13, 70, // Opcode: LOOPNEZ +/* 4964 */ MCD_OPC_FilterValue, 10, 209, 0, 0, // Skip to: 5178 +/* 4969 */ MCD_OPC_CheckPredicate, 23, 204, 0, 0, // Skip to: 5178 +/* 4974 */ MCD_OPC_Decode, 186, 13, 70, // Opcode: LOOPGTZ +/* 4978 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4987 +/* 4983 */ MCD_OPC_Decode, 176, 11, 71, // Opcode: BLTUI +/* 4987 */ MCD_OPC_FilterValue, 3, 186, 0, 0, // Skip to: 5178 +/* 4992 */ MCD_OPC_Decode, 171, 11, 71, // Opcode: BGEUI +/* 4996 */ MCD_OPC_FilterValue, 7, 177, 0, 0, // Skip to: 5178 +/* 5001 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5004 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 5030 +/* 5009 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 5012 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5021 +/* 5017 */ MCD_OPC_Decode, 182, 11, 72, // Opcode: BNONE +/* 5021 */ MCD_OPC_FilterValue, 1, 152, 0, 0, // Skip to: 5178 +/* 5026 */ MCD_OPC_Decode, 164, 11, 72, // Opcode: BEQ +/* 5030 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 5056 +/* 5035 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 5038 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5047 +/* 5043 */ MCD_OPC_Decode, 173, 11, 72, // Opcode: BLT +/* 5047 */ MCD_OPC_FilterValue, 1, 126, 0, 0, // Skip to: 5178 +/* 5052 */ MCD_OPC_Decode, 175, 11, 72, // Opcode: BLTU +/* 5056 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 5082 +/* 5061 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 5064 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5073 +/* 5069 */ MCD_OPC_Decode, 158, 11, 72, // Opcode: BALL +/* 5073 */ MCD_OPC_FilterValue, 1, 100, 0, 0, // Skip to: 5178 +/* 5078 */ MCD_OPC_Decode, 160, 11, 72, // Opcode: BBC +/* 5082 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 5091 +/* 5087 */ MCD_OPC_Decode, 161, 11, 73, // Opcode: BBCI +/* 5091 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 5117 +/* 5096 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 5099 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5108 +/* 5104 */ MCD_OPC_Decode, 159, 11, 72, // Opcode: BANY +/* 5108 */ MCD_OPC_FilterValue, 1, 65, 0, 0, // Skip to: 5178 +/* 5113 */ MCD_OPC_Decode, 179, 11, 72, // Opcode: BNE +/* 5117 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 5143 +/* 5122 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 5125 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5134 +/* 5130 */ MCD_OPC_Decode, 168, 11, 72, // Opcode: BGE +/* 5134 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 5178 +/* 5139 */ MCD_OPC_Decode, 170, 11, 72, // Opcode: BGEU +/* 5143 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 5169 +/* 5148 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 5151 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5160 +/* 5156 */ MCD_OPC_Decode, 178, 11, 72, // Opcode: BNALL +/* 5160 */ MCD_OPC_FilterValue, 1, 13, 0, 0, // Skip to: 5178 +/* 5165 */ MCD_OPC_Decode, 162, 11, 72, // Opcode: BBS +/* 5169 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 5178 +/* 5174 */ MCD_OPC_Decode, 163, 11, 73, // Opcode: BBSI +/* 5178 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableESP32S324[] = { +/* 0 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 3 */ MCD_OPC_FilterValue, 0, 108, 0, 0, // Skip to: 116 +/* 8 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 46 +/* 16 */ MCD_OPC_CheckPredicate, 22, 64, 16, 0, // Skip to: 4181 +/* 21 */ MCD_OPC_CheckField, 23, 1, 0, 57, 16, 0, // Skip to: 4181 +/* 28 */ MCD_OPC_CheckField, 15, 1, 0, 50, 16, 0, // Skip to: 4181 +/* 35 */ MCD_OPC_CheckField, 0, 4, 4, 43, 16, 0, // Skip to: 4181 +/* 42 */ MCD_OPC_Decode, 236, 11, 74, // Opcode: EE_LD_QACC_L_L_128_IP +/* 46 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 81 +/* 51 */ MCD_OPC_CheckPredicate, 22, 29, 16, 0, // Skip to: 4181 +/* 56 */ MCD_OPC_CheckField, 23, 1, 0, 22, 16, 0, // Skip to: 4181 +/* 63 */ MCD_OPC_CheckField, 15, 1, 0, 15, 16, 0, // Skip to: 4181 +/* 70 */ MCD_OPC_CheckField, 0, 4, 4, 8, 16, 0, // Skip to: 4181 +/* 77 */ MCD_OPC_Decode, 237, 11, 74, // Opcode: EE_LD_UA_STATE_IP +/* 81 */ MCD_OPC_FilterValue, 3, 255, 15, 0, // Skip to: 4181 +/* 86 */ MCD_OPC_CheckPredicate, 22, 250, 15, 0, // Skip to: 4181 +/* 91 */ MCD_OPC_CheckField, 22, 2, 1, 243, 15, 0, // Skip to: 4181 +/* 98 */ MCD_OPC_CheckField, 12, 4, 4, 236, 15, 0, // Skip to: 4181 +/* 105 */ MCD_OPC_CheckField, 0, 4, 4, 229, 15, 0, // Skip to: 4181 +/* 112 */ MCD_OPC_Decode, 228, 11, 75, // Opcode: EE_LDQA_U8_128_XP +/* 116 */ MCD_OPC_FilterValue, 1, 123, 0, 0, // Skip to: 244 +/* 121 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 124 */ MCD_OPC_FilterValue, 0, 94, 0, 0, // Skip to: 223 +/* 129 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 132 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 160 +/* 137 */ MCD_OPC_CheckPredicate, 22, 199, 15, 0, // Skip to: 4181 +/* 142 */ MCD_OPC_CheckField, 15, 1, 0, 192, 15, 0, // Skip to: 4181 +/* 149 */ MCD_OPC_CheckField, 0, 4, 4, 185, 15, 0, // Skip to: 4181 +/* 156 */ MCD_OPC_Decode, 221, 11, 74, // Opcode: EE_LDQA_S16_128_IP +/* 160 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 188 +/* 165 */ MCD_OPC_CheckPredicate, 22, 171, 15, 0, // Skip to: 4181 +/* 170 */ MCD_OPC_CheckField, 15, 1, 0, 164, 15, 0, // Skip to: 4181 +/* 177 */ MCD_OPC_CheckField, 0, 4, 4, 157, 15, 0, // Skip to: 4181 +/* 184 */ MCD_OPC_Decode, 223, 11, 74, // Opcode: EE_LDQA_S8_128_IP +/* 188 */ MCD_OPC_FilterValue, 3, 148, 15, 0, // Skip to: 4181 +/* 193 */ MCD_OPC_CheckPredicate, 22, 143, 15, 0, // Skip to: 4181 +/* 198 */ MCD_OPC_CheckField, 22, 1, 1, 136, 15, 0, // Skip to: 4181 +/* 205 */ MCD_OPC_CheckField, 12, 4, 4, 129, 15, 0, // Skip to: 4181 +/* 212 */ MCD_OPC_CheckField, 0, 4, 4, 122, 15, 0, // Skip to: 4181 +/* 219 */ MCD_OPC_Decode, 224, 11, 75, // Opcode: EE_LDQA_S8_128_XP +/* 223 */ MCD_OPC_FilterValue, 1, 113, 15, 0, // Skip to: 4181 +/* 228 */ MCD_OPC_CheckPredicate, 22, 108, 15, 0, // Skip to: 4181 +/* 233 */ MCD_OPC_CheckField, 0, 4, 4, 101, 15, 0, // Skip to: 4181 +/* 240 */ MCD_OPC_Decode, 230, 11, 76, // Opcode: EE_LD_128_USAR_IP +/* 244 */ MCD_OPC_FilterValue, 2, 88, 0, 0, // Skip to: 337 +/* 249 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 252 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 316 +/* 257 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 260 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 288 +/* 265 */ MCD_OPC_CheckPredicate, 22, 71, 15, 0, // Skip to: 4181 +/* 270 */ MCD_OPC_CheckField, 15, 1, 0, 64, 15, 0, // Skip to: 4181 +/* 277 */ MCD_OPC_CheckField, 0, 4, 4, 57, 15, 0, // Skip to: 4181 +/* 284 */ MCD_OPC_Decode, 136, 12, 77, // Opcode: EE_ST_ACCX_IP +/* 288 */ MCD_OPC_FilterValue, 1, 48, 15, 0, // Skip to: 4181 +/* 293 */ MCD_OPC_CheckPredicate, 22, 43, 15, 0, // Skip to: 4181 +/* 298 */ MCD_OPC_CheckField, 15, 1, 0, 36, 15, 0, // Skip to: 4181 +/* 305 */ MCD_OPC_CheckField, 0, 4, 4, 29, 15, 0, // Skip to: 4181 +/* 312 */ MCD_OPC_Decode, 137, 12, 78, // Opcode: EE_ST_QACC_H_H_32_IP +/* 316 */ MCD_OPC_FilterValue, 1, 20, 15, 0, // Skip to: 4181 +/* 321 */ MCD_OPC_CheckPredicate, 22, 15, 15, 0, // Skip to: 4181 +/* 326 */ MCD_OPC_CheckField, 0, 4, 4, 8, 15, 0, // Skip to: 4181 +/* 333 */ MCD_OPC_Decode, 164, 12, 79, // Opcode: EE_VLDBC_32_IP +/* 337 */ MCD_OPC_FilterValue, 3, 48, 3, 0, // Skip to: 1158 +/* 342 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 345 */ MCD_OPC_FilterValue, 0, 19, 3, 0, // Skip to: 1137 +/* 350 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 353 */ MCD_OPC_FilterValue, 0, 15, 1, 0, // Skip to: 629 +/* 358 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 361 */ MCD_OPC_FilterValue, 14, 227, 0, 0, // Skip to: 593 +/* 366 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 369 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 383 +/* 374 */ MCD_OPC_CheckPredicate, 22, 218, 14, 0, // Skip to: 4181 +/* 379 */ MCD_OPC_Decode, 196, 14, 80, // Opcode: RUR_ACCX_0 +/* 383 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 397 +/* 388 */ MCD_OPC_CheckPredicate, 22, 204, 14, 0, // Skip to: 4181 +/* 393 */ MCD_OPC_Decode, 197, 14, 80, // Opcode: RUR_ACCX_1 +/* 397 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 411 +/* 402 */ MCD_OPC_CheckPredicate, 22, 190, 14, 0, // Skip to: 4181 +/* 407 */ MCD_OPC_Decode, 215, 14, 80, // Opcode: RUR_QACC_H_0 +/* 411 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 425 +/* 416 */ MCD_OPC_CheckPredicate, 22, 176, 14, 0, // Skip to: 4181 +/* 421 */ MCD_OPC_Decode, 216, 14, 80, // Opcode: RUR_QACC_H_1 +/* 425 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 439 +/* 430 */ MCD_OPC_CheckPredicate, 22, 162, 14, 0, // Skip to: 4181 +/* 435 */ MCD_OPC_Decode, 217, 14, 80, // Opcode: RUR_QACC_H_2 +/* 439 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 453 +/* 444 */ MCD_OPC_CheckPredicate, 22, 148, 14, 0, // Skip to: 4181 +/* 449 */ MCD_OPC_Decode, 218, 14, 80, // Opcode: RUR_QACC_H_3 +/* 453 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 467 +/* 458 */ MCD_OPC_CheckPredicate, 22, 134, 14, 0, // Skip to: 4181 +/* 463 */ MCD_OPC_Decode, 219, 14, 80, // Opcode: RUR_QACC_H_4 +/* 467 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 481 +/* 472 */ MCD_OPC_CheckPredicate, 22, 120, 14, 0, // Skip to: 4181 +/* 477 */ MCD_OPC_Decode, 220, 14, 80, // Opcode: RUR_QACC_L_0 +/* 481 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 495 +/* 486 */ MCD_OPC_CheckPredicate, 22, 106, 14, 0, // Skip to: 4181 +/* 491 */ MCD_OPC_Decode, 221, 14, 80, // Opcode: RUR_QACC_L_1 +/* 495 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 509 +/* 500 */ MCD_OPC_CheckPredicate, 22, 92, 14, 0, // Skip to: 4181 +/* 505 */ MCD_OPC_Decode, 222, 14, 80, // Opcode: RUR_QACC_L_2 +/* 509 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 523 +/* 514 */ MCD_OPC_CheckPredicate, 22, 78, 14, 0, // Skip to: 4181 +/* 519 */ MCD_OPC_Decode, 223, 14, 80, // Opcode: RUR_QACC_L_3 +/* 523 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 537 +/* 528 */ MCD_OPC_CheckPredicate, 22, 64, 14, 0, // Skip to: 4181 +/* 533 */ MCD_OPC_Decode, 224, 14, 80, // Opcode: RUR_QACC_L_4 +/* 537 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 551 +/* 542 */ MCD_OPC_CheckPredicate, 22, 50, 14, 0, // Skip to: 4181 +/* 547 */ MCD_OPC_Decode, 214, 14, 80, // Opcode: RUR_GPIO_OUT +/* 551 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 565 +/* 556 */ MCD_OPC_CheckPredicate, 22, 36, 14, 0, // Skip to: 4181 +/* 561 */ MCD_OPC_Decode, 225, 14, 80, // Opcode: RUR_SAR_BYTE +/* 565 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 579 +/* 570 */ MCD_OPC_CheckPredicate, 22, 22, 14, 0, // Skip to: 4181 +/* 575 */ MCD_OPC_Decode, 213, 14, 80, // Opcode: RUR_FFT_BIT_WIDTH +/* 579 */ MCD_OPC_FilterValue, 15, 13, 14, 0, // Skip to: 4181 +/* 584 */ MCD_OPC_CheckPredicate, 22, 8, 14, 0, // Skip to: 4181 +/* 589 */ MCD_OPC_Decode, 226, 14, 80, // Opcode: RUR_UA_STATE_0 +/* 593 */ MCD_OPC_FilterValue, 15, 255, 13, 0, // Skip to: 4181 +/* 598 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 601 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 615 +/* 606 */ MCD_OPC_CheckPredicate, 22, 242, 13, 0, // Skip to: 4181 +/* 611 */ MCD_OPC_Decode, 152, 15, 25, // Opcode: WUR_ACCX_0 +/* 615 */ MCD_OPC_FilterValue, 1, 233, 13, 0, // Skip to: 4181 +/* 620 */ MCD_OPC_CheckPredicate, 22, 228, 13, 0, // Skip to: 4181 +/* 625 */ MCD_OPC_Decode, 185, 15, 25, // Opcode: WUR_UA_STATE_1 +/* 629 */ MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 723 +/* 634 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 637 */ MCD_OPC_FilterValue, 14, 45, 0, 0, // Skip to: 687 +/* 642 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 645 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 659 +/* 650 */ MCD_OPC_CheckPredicate, 22, 198, 13, 0, // Skip to: 4181 +/* 655 */ MCD_OPC_Decode, 227, 14, 80, // Opcode: RUR_UA_STATE_1 +/* 659 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 673 +/* 664 */ MCD_OPC_CheckPredicate, 22, 184, 13, 0, // Skip to: 4181 +/* 669 */ MCD_OPC_Decode, 228, 14, 80, // Opcode: RUR_UA_STATE_2 +/* 673 */ MCD_OPC_FilterValue, 2, 175, 13, 0, // Skip to: 4181 +/* 678 */ MCD_OPC_CheckPredicate, 22, 170, 13, 0, // Skip to: 4181 +/* 683 */ MCD_OPC_Decode, 229, 14, 80, // Opcode: RUR_UA_STATE_3 +/* 687 */ MCD_OPC_FilterValue, 15, 161, 13, 0, // Skip to: 4181 +/* 692 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 695 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 709 +/* 700 */ MCD_OPC_CheckPredicate, 22, 148, 13, 0, // Skip to: 4181 +/* 705 */ MCD_OPC_Decode, 153, 15, 25, // Opcode: WUR_ACCX_1 +/* 709 */ MCD_OPC_FilterValue, 1, 139, 13, 0, // Skip to: 4181 +/* 714 */ MCD_OPC_CheckPredicate, 22, 134, 13, 0, // Skip to: 4181 +/* 719 */ MCD_OPC_Decode, 186, 15, 25, // Opcode: WUR_UA_STATE_2 +/* 723 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 773 +/* 728 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 731 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 752 +/* 736 */ MCD_OPC_CheckPredicate, 22, 112, 13, 0, // Skip to: 4181 +/* 741 */ MCD_OPC_CheckField, 20, 4, 15, 105, 13, 0, // Skip to: 4181 +/* 748 */ MCD_OPC_Decode, 173, 15, 25, // Opcode: WUR_QACC_H_0 +/* 752 */ MCD_OPC_FilterValue, 1, 96, 13, 0, // Skip to: 4181 +/* 757 */ MCD_OPC_CheckPredicate, 22, 91, 13, 0, // Skip to: 4181 +/* 762 */ MCD_OPC_CheckField, 20, 4, 15, 84, 13, 0, // Skip to: 4181 +/* 769 */ MCD_OPC_Decode, 187, 15, 25, // Opcode: WUR_UA_STATE_3 +/* 773 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 801 +/* 778 */ MCD_OPC_CheckPredicate, 22, 70, 13, 0, // Skip to: 4181 +/* 783 */ MCD_OPC_CheckField, 20, 4, 15, 63, 13, 0, // Skip to: 4181 +/* 790 */ MCD_OPC_CheckField, 12, 4, 0, 56, 13, 0, // Skip to: 4181 +/* 797 */ MCD_OPC_Decode, 174, 15, 25, // Opcode: WUR_QACC_H_1 +/* 801 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 829 +/* 806 */ MCD_OPC_CheckPredicate, 22, 42, 13, 0, // Skip to: 4181 +/* 811 */ MCD_OPC_CheckField, 20, 4, 15, 35, 13, 0, // Skip to: 4181 +/* 818 */ MCD_OPC_CheckField, 12, 4, 0, 28, 13, 0, // Skip to: 4181 +/* 825 */ MCD_OPC_Decode, 175, 15, 25, // Opcode: WUR_QACC_H_2 +/* 829 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 857 +/* 834 */ MCD_OPC_CheckPredicate, 22, 14, 13, 0, // Skip to: 4181 +/* 839 */ MCD_OPC_CheckField, 20, 4, 15, 7, 13, 0, // Skip to: 4181 +/* 846 */ MCD_OPC_CheckField, 12, 4, 0, 0, 13, 0, // Skip to: 4181 +/* 853 */ MCD_OPC_Decode, 176, 15, 25, // Opcode: WUR_QACC_H_3 +/* 857 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 885 +/* 862 */ MCD_OPC_CheckPredicate, 22, 242, 12, 0, // Skip to: 4181 +/* 867 */ MCD_OPC_CheckField, 20, 4, 15, 235, 12, 0, // Skip to: 4181 +/* 874 */ MCD_OPC_CheckField, 12, 4, 0, 228, 12, 0, // Skip to: 4181 +/* 881 */ MCD_OPC_Decode, 177, 15, 25, // Opcode: WUR_QACC_H_4 +/* 885 */ MCD_OPC_FilterValue, 7, 23, 0, 0, // Skip to: 913 +/* 890 */ MCD_OPC_CheckPredicate, 22, 214, 12, 0, // Skip to: 4181 +/* 895 */ MCD_OPC_CheckField, 20, 4, 15, 207, 12, 0, // Skip to: 4181 +/* 902 */ MCD_OPC_CheckField, 12, 4, 0, 200, 12, 0, // Skip to: 4181 +/* 909 */ MCD_OPC_Decode, 178, 15, 25, // Opcode: WUR_QACC_L_0 +/* 913 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 941 +/* 918 */ MCD_OPC_CheckPredicate, 22, 186, 12, 0, // Skip to: 4181 +/* 923 */ MCD_OPC_CheckField, 20, 4, 15, 179, 12, 0, // Skip to: 4181 +/* 930 */ MCD_OPC_CheckField, 12, 4, 0, 172, 12, 0, // Skip to: 4181 +/* 937 */ MCD_OPC_Decode, 179, 15, 25, // Opcode: WUR_QACC_L_1 +/* 941 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 969 +/* 946 */ MCD_OPC_CheckPredicate, 22, 158, 12, 0, // Skip to: 4181 +/* 951 */ MCD_OPC_CheckField, 20, 4, 15, 151, 12, 0, // Skip to: 4181 +/* 958 */ MCD_OPC_CheckField, 12, 4, 0, 144, 12, 0, // Skip to: 4181 +/* 965 */ MCD_OPC_Decode, 180, 15, 25, // Opcode: WUR_QACC_L_2 +/* 969 */ MCD_OPC_FilterValue, 10, 23, 0, 0, // Skip to: 997 +/* 974 */ MCD_OPC_CheckPredicate, 22, 130, 12, 0, // Skip to: 4181 +/* 979 */ MCD_OPC_CheckField, 20, 4, 15, 123, 12, 0, // Skip to: 4181 +/* 986 */ MCD_OPC_CheckField, 12, 4, 0, 116, 12, 0, // Skip to: 4181 +/* 993 */ MCD_OPC_Decode, 181, 15, 25, // Opcode: WUR_QACC_L_3 +/* 997 */ MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 1025 +/* 1002 */ MCD_OPC_CheckPredicate, 22, 102, 12, 0, // Skip to: 4181 +/* 1007 */ MCD_OPC_CheckField, 20, 4, 15, 95, 12, 0, // Skip to: 4181 +/* 1014 */ MCD_OPC_CheckField, 12, 4, 0, 88, 12, 0, // Skip to: 4181 +/* 1021 */ MCD_OPC_Decode, 182, 15, 25, // Opcode: WUR_QACC_L_4 +/* 1025 */ MCD_OPC_FilterValue, 12, 23, 0, 0, // Skip to: 1053 +/* 1030 */ MCD_OPC_CheckPredicate, 22, 74, 12, 0, // Skip to: 4181 +/* 1035 */ MCD_OPC_CheckField, 20, 4, 15, 67, 12, 0, // Skip to: 4181 +/* 1042 */ MCD_OPC_CheckField, 12, 4, 0, 60, 12, 0, // Skip to: 4181 +/* 1049 */ MCD_OPC_Decode, 172, 15, 25, // Opcode: WUR_GPIO_OUT +/* 1053 */ MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 1081 +/* 1058 */ MCD_OPC_CheckPredicate, 22, 46, 12, 0, // Skip to: 4181 +/* 1063 */ MCD_OPC_CheckField, 20, 4, 15, 39, 12, 0, // Skip to: 4181 +/* 1070 */ MCD_OPC_CheckField, 12, 4, 0, 32, 12, 0, // Skip to: 4181 +/* 1077 */ MCD_OPC_Decode, 183, 15, 25, // Opcode: WUR_SAR_BYTE +/* 1081 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 1109 +/* 1086 */ MCD_OPC_CheckPredicate, 22, 18, 12, 0, // Skip to: 4181 +/* 1091 */ MCD_OPC_CheckField, 20, 4, 15, 11, 12, 0, // Skip to: 4181 +/* 1098 */ MCD_OPC_CheckField, 12, 4, 0, 4, 12, 0, // Skip to: 4181 +/* 1105 */ MCD_OPC_Decode, 170, 15, 25, // Opcode: WUR_FFT_BIT_WIDTH +/* 1109 */ MCD_OPC_FilterValue, 15, 251, 11, 0, // Skip to: 4181 +/* 1114 */ MCD_OPC_CheckPredicate, 22, 246, 11, 0, // Skip to: 4181 +/* 1119 */ MCD_OPC_CheckField, 20, 4, 15, 239, 11, 0, // Skip to: 4181 +/* 1126 */ MCD_OPC_CheckField, 12, 4, 0, 232, 11, 0, // Skip to: 4181 +/* 1133 */ MCD_OPC_Decode, 184, 15, 25, // Opcode: WUR_UA_STATE_0 +/* 1137 */ MCD_OPC_FilterValue, 4, 223, 11, 0, // Skip to: 4181 +/* 1142 */ MCD_OPC_CheckPredicate, 22, 218, 11, 0, // Skip to: 4181 +/* 1147 */ MCD_OPC_CheckField, 23, 1, 1, 211, 11, 0, // Skip to: 4181 +/* 1154 */ MCD_OPC_Decode, 170, 12, 76, // Opcode: EE_VLD_128_IP +/* 1158 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 1186 +/* 1163 */ MCD_OPC_CheckPredicate, 22, 197, 11, 0, // Skip to: 4181 +/* 1168 */ MCD_OPC_CheckField, 23, 1, 1, 190, 11, 0, // Skip to: 4181 +/* 1175 */ MCD_OPC_CheckField, 0, 4, 4, 183, 11, 0, // Skip to: 4181 +/* 1182 */ MCD_OPC_Decode, 140, 13, 81, // Opcode: EE_VST_L_64_IP +/* 1186 */ MCD_OPC_FilterValue, 5, 169, 0, 0, // Skip to: 1360 +/* 1191 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1194 */ MCD_OPC_FilterValue, 0, 111, 0, 0, // Skip to: 1310 +/* 1199 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 1202 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1230 +/* 1207 */ MCD_OPC_CheckPredicate, 22, 153, 11, 0, // Skip to: 4181 +/* 1212 */ MCD_OPC_CheckField, 15, 1, 0, 146, 11, 0, // Skip to: 4181 +/* 1219 */ MCD_OPC_CheckField, 0, 4, 4, 139, 11, 0, // Skip to: 4181 +/* 1226 */ MCD_OPC_Decode, 225, 11, 74, // Opcode: EE_LDQA_U16_128_IP +/* 1230 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 1258 +/* 1235 */ MCD_OPC_CheckPredicate, 22, 125, 11, 0, // Skip to: 4181 +/* 1240 */ MCD_OPC_CheckField, 15, 1, 0, 118, 11, 0, // Skip to: 4181 +/* 1247 */ MCD_OPC_CheckField, 0, 4, 4, 111, 11, 0, // Skip to: 4181 +/* 1254 */ MCD_OPC_Decode, 227, 11, 74, // Opcode: EE_LDQA_U8_128_IP +/* 1258 */ MCD_OPC_FilterValue, 2, 102, 11, 0, // Skip to: 4181 +/* 1263 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 1266 */ MCD_OPC_FilterValue, 132, 16, 16, 0, 0, // Skip to: 1288 +/* 1272 */ MCD_OPC_CheckPredicate, 22, 88, 11, 0, // Skip to: 4181 +/* 1277 */ MCD_OPC_CheckField, 22, 1, 0, 81, 11, 0, // Skip to: 4181 +/* 1284 */ MCD_OPC_Decode, 159, 13, 6, // Opcode: EE_ZERO_ACCX +/* 1288 */ MCD_OPC_FilterValue, 196, 16, 71, 11, 0, // Skip to: 4181 +/* 1294 */ MCD_OPC_CheckPredicate, 22, 66, 11, 0, // Skip to: 4181 +/* 1299 */ MCD_OPC_CheckField, 22, 1, 0, 59, 11, 0, // Skip to: 4181 +/* 1306 */ MCD_OPC_Decode, 161, 13, 6, // Opcode: EE_ZERO_QACC +/* 1310 */ MCD_OPC_FilterValue, 1, 50, 11, 0, // Skip to: 4181 +/* 1315 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1318 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1339 +/* 1323 */ MCD_OPC_CheckPredicate, 22, 37, 11, 0, // Skip to: 4181 +/* 1328 */ MCD_OPC_CheckField, 0, 4, 4, 30, 11, 0, // Skip to: 4181 +/* 1335 */ MCD_OPC_Decode, 161, 12, 82, // Opcode: EE_VLDBC_16_IP +/* 1339 */ MCD_OPC_FilterValue, 1, 21, 11, 0, // Skip to: 4181 +/* 1344 */ MCD_OPC_CheckPredicate, 22, 16, 11, 0, // Skip to: 4181 +/* 1349 */ MCD_OPC_CheckField, 0, 4, 4, 9, 11, 0, // Skip to: 4181 +/* 1356 */ MCD_OPC_Decode, 167, 12, 83, // Opcode: EE_VLDBC_8_IP +/* 1360 */ MCD_OPC_FilterValue, 6, 111, 0, 0, // Skip to: 1476 +/* 1365 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1368 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1382 +/* 1373 */ MCD_OPC_CheckPredicate, 22, 243, 10, 0, // Skip to: 4181 +/* 1378 */ MCD_OPC_Decode, 220, 11, 84, // Opcode: EE_LDF_64_XP +/* 1382 */ MCD_OPC_FilterValue, 4, 234, 10, 0, // Skip to: 4181 +/* 1387 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1390 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 1440 +/* 1395 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 1398 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1419 +/* 1403 */ MCD_OPC_CheckPredicate, 22, 213, 10, 0, // Skip to: 4181 +/* 1408 */ MCD_OPC_CheckField, 15, 1, 0, 206, 10, 0, // Skip to: 4181 +/* 1415 */ MCD_OPC_Decode, 234, 11, 74, // Opcode: EE_LD_QACC_H_L_128_IP +/* 1419 */ MCD_OPC_FilterValue, 1, 197, 10, 0, // Skip to: 4181 +/* 1424 */ MCD_OPC_CheckPredicate, 22, 192, 10, 0, // Skip to: 4181 +/* 1429 */ MCD_OPC_CheckField, 15, 1, 0, 185, 10, 0, // Skip to: 4181 +/* 1436 */ MCD_OPC_Decode, 235, 11, 78, // Opcode: EE_LD_QACC_L_H_32_IP +/* 1440 */ MCD_OPC_FilterValue, 1, 176, 10, 0, // Skip to: 4181 +/* 1445 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1448 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1462 +/* 1453 */ MCD_OPC_CheckPredicate, 22, 163, 10, 0, // Skip to: 4181 +/* 1458 */ MCD_OPC_Decode, 248, 11, 85, // Opcode: EE_SLCXXP_2Q +/* 1462 */ MCD_OPC_FilterValue, 1, 154, 10, 0, // Skip to: 4181 +/* 1467 */ MCD_OPC_CheckPredicate, 22, 149, 10, 0, // Skip to: 4181 +/* 1472 */ MCD_OPC_Decode, 253, 11, 85, // Opcode: EE_SRCXXP_2Q +/* 1476 */ MCD_OPC_FilterValue, 7, 81, 0, 0, // Skip to: 1562 +/* 1481 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1484 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1498 +/* 1489 */ MCD_OPC_CheckPredicate, 22, 127, 10, 0, // Skip to: 4181 +/* 1494 */ MCD_OPC_Decode, 134, 12, 86, // Opcode: EE_STF_64_XP +/* 1498 */ MCD_OPC_FilterValue, 4, 118, 10, 0, // Skip to: 4181 +/* 1503 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 1506 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1520 +/* 1511 */ MCD_OPC_CheckPredicate, 22, 105, 10, 0, // Skip to: 4181 +/* 1516 */ MCD_OPC_Decode, 200, 12, 87, // Opcode: EE_VMULAS_S16_QACC_LDBC_INCP +/* 1520 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1534 +/* 1525 */ MCD_OPC_CheckPredicate, 22, 91, 10, 0, // Skip to: 4181 +/* 1530 */ MCD_OPC_Decode, 212, 12, 87, // Opcode: EE_VMULAS_S8_QACC_LDBC_INCP +/* 1534 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1548 +/* 1539 */ MCD_OPC_CheckPredicate, 22, 77, 10, 0, // Skip to: 4181 +/* 1544 */ MCD_OPC_Decode, 224, 12, 87, // Opcode: EE_VMULAS_U16_QACC_LDBC_INCP +/* 1548 */ MCD_OPC_FilterValue, 7, 68, 10, 0, // Skip to: 4181 +/* 1553 */ MCD_OPC_CheckPredicate, 22, 63, 10, 0, // Skip to: 4181 +/* 1558 */ MCD_OPC_Decode, 236, 12, 87, // Opcode: EE_VMULAS_U8_QACC_LDBC_INCP +/* 1562 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 1590 +/* 1567 */ MCD_OPC_CheckPredicate, 22, 49, 10, 0, // Skip to: 4181 +/* 1572 */ MCD_OPC_CheckField, 23, 1, 1, 42, 10, 0, // Skip to: 4181 +/* 1579 */ MCD_OPC_CheckField, 0, 4, 4, 35, 10, 0, // Skip to: 4181 +/* 1586 */ MCD_OPC_Decode, 172, 12, 88, // Opcode: EE_VLD_H_64_IP +/* 1590 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 1618 +/* 1595 */ MCD_OPC_CheckPredicate, 22, 21, 10, 0, // Skip to: 4181 +/* 1600 */ MCD_OPC_CheckField, 23, 1, 1, 14, 10, 0, // Skip to: 4181 +/* 1607 */ MCD_OPC_CheckField, 0, 4, 4, 7, 10, 0, // Skip to: 4181 +/* 1614 */ MCD_OPC_Decode, 174, 12, 88, // Opcode: EE_VLD_L_64_IP +/* 1618 */ MCD_OPC_FilterValue, 10, 24, 1, 0, // Skip to: 1903 +/* 1623 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1626 */ MCD_OPC_FilterValue, 0, 251, 0, 0, // Skip to: 1882 +/* 1631 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 1634 */ MCD_OPC_FilterValue, 0, 105, 0, 0, // Skip to: 1744 +/* 1639 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 1642 */ MCD_OPC_FilterValue, 132, 1, 45, 0, 0, // Skip to: 1693 +/* 1648 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1651 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1672 +/* 1656 */ MCD_OPC_CheckPredicate, 22, 216, 9, 0, // Skip to: 4181 +/* 1661 */ MCD_OPC_CheckField, 15, 1, 0, 209, 9, 0, // Skip to: 4181 +/* 1668 */ MCD_OPC_Decode, 218, 12, 89, // Opcode: EE_VMULAS_U16_ACCX +/* 1672 */ MCD_OPC_FilterValue, 1, 200, 9, 0, // Skip to: 4181 +/* 1677 */ MCD_OPC_CheckPredicate, 22, 195, 9, 0, // Skip to: 4181 +/* 1682 */ MCD_OPC_CheckField, 15, 1, 0, 188, 9, 0, // Skip to: 4181 +/* 1689 */ MCD_OPC_Decode, 223, 12, 89, // Opcode: EE_VMULAS_U16_QACC +/* 1693 */ MCD_OPC_FilterValue, 196, 1, 178, 9, 0, // Skip to: 4181 +/* 1699 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1702 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1723 +/* 1707 */ MCD_OPC_CheckPredicate, 22, 165, 9, 0, // Skip to: 4181 +/* 1712 */ MCD_OPC_CheckField, 15, 1, 0, 158, 9, 0, // Skip to: 4181 +/* 1719 */ MCD_OPC_Decode, 230, 12, 89, // Opcode: EE_VMULAS_U8_ACCX +/* 1723 */ MCD_OPC_FilterValue, 1, 149, 9, 0, // Skip to: 4181 +/* 1728 */ MCD_OPC_CheckPredicate, 22, 144, 9, 0, // Skip to: 4181 +/* 1733 */ MCD_OPC_CheckField, 15, 1, 0, 137, 9, 0, // Skip to: 4181 +/* 1740 */ MCD_OPC_Decode, 235, 12, 89, // Opcode: EE_VMULAS_U8_QACC +/* 1744 */ MCD_OPC_FilterValue, 1, 105, 0, 0, // Skip to: 1854 +/* 1749 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 1752 */ MCD_OPC_FilterValue, 132, 1, 45, 0, 0, // Skip to: 1803 +/* 1758 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1761 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1782 +/* 1766 */ MCD_OPC_CheckPredicate, 22, 106, 9, 0, // Skip to: 4181 +/* 1771 */ MCD_OPC_CheckField, 15, 1, 0, 99, 9, 0, // Skip to: 4181 +/* 1778 */ MCD_OPC_Decode, 194, 12, 89, // Opcode: EE_VMULAS_S16_ACCX +/* 1782 */ MCD_OPC_FilterValue, 1, 90, 9, 0, // Skip to: 4181 +/* 1787 */ MCD_OPC_CheckPredicate, 22, 85, 9, 0, // Skip to: 4181 +/* 1792 */ MCD_OPC_CheckField, 15, 1, 0, 78, 9, 0, // Skip to: 4181 +/* 1799 */ MCD_OPC_Decode, 199, 12, 89, // Opcode: EE_VMULAS_S16_QACC +/* 1803 */ MCD_OPC_FilterValue, 196, 1, 68, 9, 0, // Skip to: 4181 +/* 1809 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1812 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1833 +/* 1817 */ MCD_OPC_CheckPredicate, 22, 55, 9, 0, // Skip to: 4181 +/* 1822 */ MCD_OPC_CheckField, 15, 1, 0, 48, 9, 0, // Skip to: 4181 +/* 1829 */ MCD_OPC_Decode, 206, 12, 89, // Opcode: EE_VMULAS_S8_ACCX +/* 1833 */ MCD_OPC_FilterValue, 1, 39, 9, 0, // Skip to: 4181 +/* 1838 */ MCD_OPC_CheckPredicate, 22, 34, 9, 0, // Skip to: 4181 +/* 1843 */ MCD_OPC_CheckField, 15, 1, 0, 27, 9, 0, // Skip to: 4181 +/* 1850 */ MCD_OPC_Decode, 211, 12, 89, // Opcode: EE_VMULAS_S8_QACC +/* 1854 */ MCD_OPC_FilterValue, 7, 18, 9, 0, // Skip to: 4181 +/* 1859 */ MCD_OPC_CheckPredicate, 22, 13, 9, 0, // Skip to: 4181 +/* 1864 */ MCD_OPC_CheckField, 12, 4, 4, 6, 9, 0, // Skip to: 4181 +/* 1871 */ MCD_OPC_CheckField, 0, 4, 4, 255, 8, 0, // Skip to: 4181 +/* 1878 */ MCD_OPC_Decode, 226, 11, 75, // Opcode: EE_LDQA_U16_128_XP +/* 1882 */ MCD_OPC_FilterValue, 1, 246, 8, 0, // Skip to: 4181 +/* 1887 */ MCD_OPC_CheckPredicate, 22, 241, 8, 0, // Skip to: 4181 +/* 1892 */ MCD_OPC_CheckField, 0, 4, 4, 234, 8, 0, // Skip to: 4181 +/* 1899 */ MCD_OPC_Decode, 136, 13, 90, // Opcode: EE_VST_128_IP +/* 1903 */ MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 1931 +/* 1908 */ MCD_OPC_CheckPredicate, 22, 220, 8, 0, // Skip to: 4181 +/* 1913 */ MCD_OPC_CheckField, 23, 1, 1, 213, 8, 0, // Skip to: 4181 +/* 1920 */ MCD_OPC_CheckField, 0, 4, 4, 206, 8, 0, // Skip to: 4181 +/* 1927 */ MCD_OPC_Decode, 138, 13, 81, // Opcode: EE_VST_H_64_IP +/* 1931 */ MCD_OPC_FilterValue, 12, 169, 1, 0, // Skip to: 2361 +/* 1936 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1939 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 2003 +/* 1944 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 1947 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1975 +/* 1952 */ MCD_OPC_CheckPredicate, 22, 176, 8, 0, // Skip to: 4181 +/* 1957 */ MCD_OPC_CheckField, 15, 1, 0, 169, 8, 0, // Skip to: 4181 +/* 1964 */ MCD_OPC_CheckField, 0, 4, 4, 162, 8, 0, // Skip to: 4181 +/* 1971 */ MCD_OPC_Decode, 140, 12, 74, // Opcode: EE_ST_QACC_L_L_128_IP +/* 1975 */ MCD_OPC_FilterValue, 1, 153, 8, 0, // Skip to: 4181 +/* 1980 */ MCD_OPC_CheckPredicate, 22, 148, 8, 0, // Skip to: 4181 +/* 1985 */ MCD_OPC_CheckField, 15, 1, 0, 141, 8, 0, // Skip to: 4181 +/* 1992 */ MCD_OPC_CheckField, 0, 4, 4, 134, 8, 0, // Skip to: 4181 +/* 1999 */ MCD_OPC_Decode, 141, 12, 74, // Opcode: EE_ST_UA_STATE_IP +/* 2003 */ MCD_OPC_FilterValue, 1, 125, 8, 0, // Skip to: 4181 +/* 2008 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2011 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2061 +/* 2016 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 2019 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2040 +/* 2024 */ MCD_OPC_CheckPredicate, 22, 104, 8, 0, // Skip to: 4181 +/* 2029 */ MCD_OPC_CheckField, 0, 4, 4, 97, 8, 0, // Skip to: 4181 +/* 2036 */ MCD_OPC_Decode, 254, 12, 91, // Opcode: EE_VPRELU_S16 +/* 2040 */ MCD_OPC_FilterValue, 1, 88, 8, 0, // Skip to: 4181 +/* 2045 */ MCD_OPC_CheckPredicate, 22, 83, 8, 0, // Skip to: 4181 +/* 2050 */ MCD_OPC_CheckField, 0, 4, 4, 76, 8, 0, // Skip to: 4181 +/* 2057 */ MCD_OPC_Decode, 255, 12, 91, // Opcode: EE_VPRELU_S8 +/* 2061 */ MCD_OPC_FilterValue, 1, 67, 8, 0, // Skip to: 4181 +/* 2066 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 2069 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2090 +/* 2074 */ MCD_OPC_CheckPredicate, 22, 54, 8, 0, // Skip to: 4181 +/* 2079 */ MCD_OPC_CheckField, 0, 4, 4, 47, 8, 0, // Skip to: 4181 +/* 2086 */ MCD_OPC_Decode, 213, 11, 92, // Opcode: EE_FFT_R2BF_S16 +/* 2090 */ MCD_OPC_FilterValue, 1, 38, 8, 0, // Skip to: 4181 +/* 2095 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 2098 */ MCD_OPC_FilterValue, 0, 145, 0, 0, // Skip to: 2248 +/* 2103 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 2106 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2127 +/* 2111 */ MCD_OPC_CheckPredicate, 22, 17, 8, 0, // Skip to: 4181 +/* 2116 */ MCD_OPC_CheckField, 0, 4, 4, 10, 8, 0, // Skip to: 4181 +/* 2123 */ MCD_OPC_Decode, 169, 12, 93, // Opcode: EE_VLDHBC_16_INCP +/* 2127 */ MCD_OPC_FilterValue, 1, 1, 8, 0, // Skip to: 4181 +/* 2132 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 2135 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2156 +/* 2140 */ MCD_OPC_CheckPredicate, 22, 244, 7, 0, // Skip to: 4181 +/* 2145 */ MCD_OPC_CheckField, 0, 4, 4, 237, 7, 0, // Skip to: 4181 +/* 2152 */ MCD_OPC_Decode, 254, 11, 94, // Opcode: EE_SRC_Q +/* 2156 */ MCD_OPC_FilterValue, 1, 228, 7, 0, // Skip to: 4181 +/* 2161 */ MCD_OPC_ExtractField, 0, 7, // Inst{6-0} ... +/* 2164 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2178 +/* 2169 */ MCD_OPC_CheckPredicate, 22, 215, 7, 0, // Skip to: 4181 +/* 2174 */ MCD_OPC_Decode, 151, 13, 95, // Opcode: EE_VUNZIP_16 +/* 2178 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 2192 +/* 2183 */ MCD_OPC_CheckPredicate, 22, 201, 7, 0, // Skip to: 4181 +/* 2188 */ MCD_OPC_Decode, 152, 13, 95, // Opcode: EE_VUNZIP_32 +/* 2192 */ MCD_OPC_FilterValue, 36, 9, 0, 0, // Skip to: 2206 +/* 2197 */ MCD_OPC_CheckPredicate, 22, 187, 7, 0, // Skip to: 4181 +/* 2202 */ MCD_OPC_Decode, 153, 13, 95, // Opcode: EE_VUNZIP_8 +/* 2206 */ MCD_OPC_FilterValue, 52, 9, 0, 0, // Skip to: 2220 +/* 2211 */ MCD_OPC_CheckPredicate, 22, 173, 7, 0, // Skip to: 4181 +/* 2216 */ MCD_OPC_Decode, 154, 13, 95, // Opcode: EE_VZIP_16 +/* 2220 */ MCD_OPC_FilterValue, 68, 9, 0, 0, // Skip to: 2234 +/* 2225 */ MCD_OPC_CheckPredicate, 22, 159, 7, 0, // Skip to: 4181 +/* 2230 */ MCD_OPC_Decode, 155, 13, 95, // Opcode: EE_VZIP_32 +/* 2234 */ MCD_OPC_FilterValue, 84, 150, 7, 0, // Skip to: 4181 +/* 2239 */ MCD_OPC_CheckPredicate, 22, 145, 7, 0, // Skip to: 4181 +/* 2244 */ MCD_OPC_Decode, 156, 13, 95, // Opcode: EE_VZIP_8 +/* 2248 */ MCD_OPC_FilterValue, 1, 52, 0, 0, // Skip to: 2305 +/* 2253 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 2256 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2277 +/* 2261 */ MCD_OPC_CheckPredicate, 22, 123, 7, 0, // Skip to: 4181 +/* 2266 */ MCD_OPC_CheckField, 0, 4, 4, 116, 7, 0, // Skip to: 4181 +/* 2273 */ MCD_OPC_Decode, 247, 11, 96, // Opcode: EE_SLCI_2Q +/* 2277 */ MCD_OPC_FilterValue, 1, 107, 7, 0, // Skip to: 4181 +/* 2282 */ MCD_OPC_CheckPredicate, 22, 102, 7, 0, // Skip to: 4181 +/* 2287 */ MCD_OPC_CheckField, 7, 1, 0, 95, 7, 0, // Skip to: 4181 +/* 2294 */ MCD_OPC_CheckField, 0, 4, 4, 88, 7, 0, // Skip to: 4181 +/* 2301 */ MCD_OPC_Decode, 129, 12, 97, // Opcode: EE_SRC_Q_QUP +/* 2305 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 2333 +/* 2310 */ MCD_OPC_CheckPredicate, 22, 74, 7, 0, // Skip to: 4181 +/* 2315 */ MCD_OPC_CheckField, 8, 1, 0, 67, 7, 0, // Skip to: 4181 +/* 2322 */ MCD_OPC_CheckField, 0, 4, 4, 60, 7, 0, // Skip to: 4181 +/* 2329 */ MCD_OPC_Decode, 249, 11, 96, // Opcode: EE_SRCI_2Q +/* 2333 */ MCD_OPC_FilterValue, 3, 51, 7, 0, // Skip to: 4181 +/* 2338 */ MCD_OPC_CheckPredicate, 22, 46, 7, 0, // Skip to: 4181 +/* 2343 */ MCD_OPC_CheckField, 8, 1, 0, 39, 7, 0, // Skip to: 4181 +/* 2350 */ MCD_OPC_CheckField, 0, 4, 4, 32, 7, 0, // Skip to: 4181 +/* 2357 */ MCD_OPC_Decode, 252, 11, 98, // Opcode: EE_SRCQ_128_ST_INCP +/* 2361 */ MCD_OPC_FilterValue, 13, 101, 3, 0, // Skip to: 3235 +/* 2366 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 2369 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 2433 +/* 2374 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 2377 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 2405 +/* 2382 */ MCD_OPC_CheckPredicate, 22, 2, 7, 0, // Skip to: 4181 +/* 2387 */ MCD_OPC_CheckField, 15, 1, 0, 251, 6, 0, // Skip to: 4181 +/* 2394 */ MCD_OPC_CheckField, 0, 4, 4, 244, 6, 0, // Skip to: 4181 +/* 2401 */ MCD_OPC_Decode, 138, 12, 74, // Opcode: EE_ST_QACC_H_L_128_IP +/* 2405 */ MCD_OPC_FilterValue, 1, 235, 6, 0, // Skip to: 4181 +/* 2410 */ MCD_OPC_CheckPredicate, 22, 230, 6, 0, // Skip to: 4181 +/* 2415 */ MCD_OPC_CheckField, 15, 1, 0, 223, 6, 0, // Skip to: 4181 +/* 2422 */ MCD_OPC_CheckField, 0, 4, 4, 216, 6, 0, // Skip to: 4181 +/* 2429 */ MCD_OPC_Decode, 139, 12, 78, // Opcode: EE_ST_QACC_L_H_32_IP +/* 2433 */ MCD_OPC_FilterValue, 1, 207, 6, 0, // Skip to: 4181 +/* 2438 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2441 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2491 +/* 2446 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2449 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2470 +/* 2454 */ MCD_OPC_CheckPredicate, 22, 186, 6, 0, // Skip to: 4181 +/* 2459 */ MCD_OPC_CheckField, 0, 4, 4, 179, 6, 0, // Skip to: 4181 +/* 2466 */ MCD_OPC_Decode, 231, 11, 99, // Opcode: EE_LD_128_USAR_XP +/* 2470 */ MCD_OPC_FilterValue, 1, 170, 6, 0, // Skip to: 4181 +/* 2475 */ MCD_OPC_CheckPredicate, 22, 165, 6, 0, // Skip to: 4181 +/* 2480 */ MCD_OPC_CheckField, 0, 4, 4, 158, 6, 0, // Skip to: 4181 +/* 2487 */ MCD_OPC_Decode, 139, 13, 100, // Opcode: EE_VST_H_64_XP +/* 2491 */ MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 2541 +/* 2496 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2499 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2520 +/* 2504 */ MCD_OPC_CheckPredicate, 22, 136, 6, 0, // Skip to: 4181 +/* 2509 */ MCD_OPC_CheckField, 0, 4, 4, 129, 6, 0, // Skip to: 4181 +/* 2516 */ MCD_OPC_Decode, 165, 12, 99, // Opcode: EE_VLDBC_32_XP +/* 2520 */ MCD_OPC_FilterValue, 1, 120, 6, 0, // Skip to: 4181 +/* 2525 */ MCD_OPC_CheckPredicate, 22, 115, 6, 0, // Skip to: 4181 +/* 2530 */ MCD_OPC_CheckField, 0, 4, 4, 108, 6, 0, // Skip to: 4181 +/* 2537 */ MCD_OPC_Decode, 128, 13, 101, // Opcode: EE_VRELU_S16 +/* 2541 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 2569 +/* 2546 */ MCD_OPC_CheckPredicate, 22, 94, 6, 0, // Skip to: 4181 +/* 2551 */ MCD_OPC_CheckField, 22, 1, 0, 87, 6, 0, // Skip to: 4181 +/* 2558 */ MCD_OPC_CheckField, 0, 4, 4, 80, 6, 0, // Skip to: 4181 +/* 2565 */ MCD_OPC_Decode, 171, 12, 99, // Opcode: EE_VLD_128_XP +/* 2569 */ MCD_OPC_FilterValue, 3, 203, 0, 0, // Skip to: 2777 +/* 2574 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2577 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2598 +/* 2582 */ MCD_OPC_CheckPredicate, 22, 58, 6, 0, // Skip to: 4181 +/* 2587 */ MCD_OPC_CheckField, 0, 4, 4, 51, 6, 0, // Skip to: 4181 +/* 2594 */ MCD_OPC_Decode, 175, 12, 99, // Opcode: EE_VLD_L_64_XP +/* 2598 */ MCD_OPC_FilterValue, 1, 42, 6, 0, // Skip to: 4181 +/* 2603 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 2606 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2627 +/* 2611 */ MCD_OPC_CheckPredicate, 22, 29, 6, 0, // Skip to: 4181 +/* 2616 */ MCD_OPC_CheckField, 0, 4, 4, 22, 6, 0, // Skip to: 4181 +/* 2623 */ MCD_OPC_Decode, 201, 11, 102, // Opcode: EE_ANDQ +/* 2627 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2648 +/* 2632 */ MCD_OPC_CheckPredicate, 22, 8, 6, 0, // Skip to: 4181 +/* 2637 */ MCD_OPC_CheckField, 0, 4, 4, 1, 6, 0, // Skip to: 4181 +/* 2644 */ MCD_OPC_Decode, 158, 13, 102, // Opcode: EE_XORQ +/* 2648 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2669 +/* 2653 */ MCD_OPC_CheckPredicate, 22, 243, 5, 0, // Skip to: 4181 +/* 2658 */ MCD_OPC_CheckField, 0, 4, 4, 236, 5, 0, // Skip to: 4181 +/* 2665 */ MCD_OPC_Decode, 239, 11, 103, // Opcode: EE_MOVI_32_Q +/* 2669 */ MCD_OPC_FilterValue, 3, 227, 5, 0, // Skip to: 4181 +/* 2674 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 2677 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2698 +/* 2682 */ MCD_OPC_CheckPredicate, 22, 214, 5, 0, // Skip to: 4181 +/* 2687 */ MCD_OPC_CheckField, 0, 4, 4, 207, 5, 0, // Skip to: 4181 +/* 2694 */ MCD_OPC_Decode, 215, 11, 104, // Opcode: EE_FFT_VST_R32_DECP +/* 2698 */ MCD_OPC_FilterValue, 1, 198, 5, 0, // Skip to: 4181 +/* 2703 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 2706 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2727 +/* 2711 */ MCD_OPC_CheckPredicate, 22, 185, 5, 0, // Skip to: 4181 +/* 2716 */ MCD_OPC_CheckField, 0, 4, 4, 178, 5, 0, // Skip to: 4181 +/* 2723 */ MCD_OPC_Decode, 166, 12, 105, // Opcode: EE_VLDBC_8 +/* 2727 */ MCD_OPC_FilterValue, 1, 169, 5, 0, // Skip to: 4181 +/* 2732 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 2735 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2756 +/* 2740 */ MCD_OPC_CheckPredicate, 22, 156, 5, 0, // Skip to: 4181 +/* 2745 */ MCD_OPC_CheckField, 0, 4, 4, 149, 5, 0, // Skip to: 4181 +/* 2752 */ MCD_OPC_Decode, 130, 13, 106, // Opcode: EE_VSL_32 +/* 2756 */ MCD_OPC_FilterValue, 1, 140, 5, 0, // Skip to: 4181 +/* 2761 */ MCD_OPC_CheckPredicate, 22, 135, 5, 0, // Skip to: 4181 +/* 2766 */ MCD_OPC_CheckField, 0, 4, 4, 128, 5, 0, // Skip to: 4181 +/* 2773 */ MCD_OPC_Decode, 135, 13, 106, // Opcode: EE_VSR_32 +/* 2777 */ MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 2827 +/* 2782 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2785 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2806 +/* 2790 */ MCD_OPC_CheckPredicate, 22, 106, 5, 0, // Skip to: 4181 +/* 2795 */ MCD_OPC_CheckField, 0, 4, 4, 99, 5, 0, // Skip to: 4181 +/* 2802 */ MCD_OPC_Decode, 162, 12, 99, // Opcode: EE_VLDBC_16_XP +/* 2806 */ MCD_OPC_FilterValue, 1, 90, 5, 0, // Skip to: 4181 +/* 2811 */ MCD_OPC_CheckPredicate, 22, 85, 5, 0, // Skip to: 4181 +/* 2816 */ MCD_OPC_CheckField, 0, 4, 4, 78, 5, 0, // Skip to: 4181 +/* 2823 */ MCD_OPC_Decode, 141, 13, 100, // Opcode: EE_VST_L_64_XP +/* 2827 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 2877 +/* 2832 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2835 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2856 +/* 2840 */ MCD_OPC_CheckPredicate, 22, 56, 5, 0, // Skip to: 4181 +/* 2845 */ MCD_OPC_CheckField, 0, 4, 4, 49, 5, 0, // Skip to: 4181 +/* 2852 */ MCD_OPC_Decode, 168, 12, 99, // Opcode: EE_VLDBC_8_XP +/* 2856 */ MCD_OPC_FilterValue, 1, 40, 5, 0, // Skip to: 4181 +/* 2861 */ MCD_OPC_CheckPredicate, 22, 35, 5, 0, // Skip to: 4181 +/* 2866 */ MCD_OPC_CheckField, 0, 4, 4, 28, 5, 0, // Skip to: 4181 +/* 2873 */ MCD_OPC_Decode, 129, 13, 101, // Opcode: EE_VRELU_S8 +/* 2877 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 2905 +/* 2882 */ MCD_OPC_CheckPredicate, 22, 14, 5, 0, // Skip to: 4181 +/* 2887 */ MCD_OPC_CheckField, 22, 1, 0, 7, 5, 0, // Skip to: 4181 +/* 2894 */ MCD_OPC_CheckField, 0, 4, 4, 0, 5, 0, // Skip to: 4181 +/* 2901 */ MCD_OPC_Decode, 173, 12, 99, // Opcode: EE_VLD_H_64_XP +/* 2905 */ MCD_OPC_FilterValue, 7, 247, 4, 0, // Skip to: 4181 +/* 2910 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2913 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2934 +/* 2918 */ MCD_OPC_CheckPredicate, 22, 234, 4, 0, // Skip to: 4181 +/* 2923 */ MCD_OPC_CheckField, 0, 4, 4, 227, 4, 0, // Skip to: 4181 +/* 2930 */ MCD_OPC_Decode, 137, 13, 100, // Opcode: EE_VST_128_XP +/* 2934 */ MCD_OPC_FilterValue, 1, 218, 4, 0, // Skip to: 4181 +/* 2939 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 2942 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2963 +/* 2947 */ MCD_OPC_CheckPredicate, 22, 205, 4, 0, // Skip to: 4181 +/* 2952 */ MCD_OPC_CheckField, 0, 4, 4, 198, 4, 0, // Skip to: 4181 +/* 2959 */ MCD_OPC_Decode, 245, 11, 102, // Opcode: EE_ORQ +/* 2963 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2984 +/* 2968 */ MCD_OPC_CheckPredicate, 22, 184, 4, 0, // Skip to: 4181 +/* 2973 */ MCD_OPC_CheckField, 0, 4, 4, 177, 4, 0, // Skip to: 4181 +/* 2980 */ MCD_OPC_Decode, 238, 11, 107, // Opcode: EE_MOVI_32_A +/* 2984 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 3034 +/* 2989 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 2992 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3013 +/* 2997 */ MCD_OPC_CheckPredicate, 22, 155, 4, 0, // Skip to: 4181 +/* 3002 */ MCD_OPC_CheckField, 0, 4, 4, 148, 4, 0, // Skip to: 4181 +/* 3009 */ MCD_OPC_Decode, 250, 11, 108, // Opcode: EE_SRCMB_S16_QACC +/* 3013 */ MCD_OPC_FilterValue, 1, 139, 4, 0, // Skip to: 4181 +/* 3018 */ MCD_OPC_CheckPredicate, 22, 134, 4, 0, // Skip to: 4181 +/* 3023 */ MCD_OPC_CheckField, 0, 4, 4, 127, 4, 0, // Skip to: 4181 +/* 3030 */ MCD_OPC_Decode, 251, 11, 108, // Opcode: EE_SRCMB_S8_QACC +/* 3034 */ MCD_OPC_FilterValue, 3, 118, 4, 0, // Skip to: 4181 +/* 3039 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 3042 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3063 +/* 3047 */ MCD_OPC_CheckPredicate, 22, 105, 4, 0, // Skip to: 4181 +/* 3052 */ MCD_OPC_CheckField, 0, 4, 4, 98, 4, 0, // Skip to: 4181 +/* 3059 */ MCD_OPC_Decode, 160, 12, 105, // Opcode: EE_VLDBC_16 +/* 3063 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3084 +/* 3068 */ MCD_OPC_CheckPredicate, 22, 84, 4, 0, // Skip to: 4181 +/* 3073 */ MCD_OPC_CheckField, 0, 4, 4, 77, 4, 0, // Skip to: 4181 +/* 3080 */ MCD_OPC_Decode, 163, 12, 105, // Opcode: EE_VLDBC_32 +/* 3084 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 3105 +/* 3089 */ MCD_OPC_CheckPredicate, 22, 63, 4, 0, // Skip to: 4181 +/* 3094 */ MCD_OPC_CheckField, 0, 4, 4, 56, 4, 0, // Skip to: 4181 +/* 3101 */ MCD_OPC_Decode, 202, 11, 109, // Opcode: EE_BITREV +/* 3105 */ MCD_OPC_FilterValue, 3, 47, 4, 0, // Skip to: 4181 +/* 3110 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 3113 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3134 +/* 3118 */ MCD_OPC_CheckPredicate, 22, 34, 4, 0, // Skip to: 4181 +/* 3123 */ MCD_OPC_CheckField, 0, 4, 4, 27, 4, 0, // Skip to: 4181 +/* 3130 */ MCD_OPC_Decode, 244, 11, 110, // Opcode: EE_NOTQ +/* 3134 */ MCD_OPC_FilterValue, 1, 18, 4, 0, // Skip to: 4181 +/* 3139 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 3142 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3178 +/* 3147 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 3150 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3164 +/* 3155 */ MCD_OPC_CheckPredicate, 22, 253, 3, 0, // Skip to: 4181 +/* 3160 */ MCD_OPC_Decode, 240, 11, 111, // Opcode: EE_MOV_S16_QACC +/* 3164 */ MCD_OPC_FilterValue, 20, 244, 3, 0, // Skip to: 4181 +/* 3169 */ MCD_OPC_CheckPredicate, 22, 239, 3, 0, // Skip to: 4181 +/* 3174 */ MCD_OPC_Decode, 241, 11, 111, // Opcode: EE_MOV_S8_QACC +/* 3178 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 3214 +/* 3183 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 3186 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3200 +/* 3191 */ MCD_OPC_CheckPredicate, 22, 217, 3, 0, // Skip to: 4181 +/* 3196 */ MCD_OPC_Decode, 242, 11, 111, // Opcode: EE_MOV_U16_QACC +/* 3200 */ MCD_OPC_FilterValue, 20, 208, 3, 0, // Skip to: 4181 +/* 3205 */ MCD_OPC_CheckPredicate, 22, 203, 3, 0, // Skip to: 4181 +/* 3210 */ MCD_OPC_Decode, 243, 11, 111, // Opcode: EE_MOV_U8_QACC +/* 3214 */ MCD_OPC_FilterValue, 2, 194, 3, 0, // Skip to: 4181 +/* 3219 */ MCD_OPC_CheckPredicate, 22, 189, 3, 0, // Skip to: 4181 +/* 3224 */ MCD_OPC_CheckField, 0, 5, 4, 182, 3, 0, // Skip to: 4181 +/* 3231 */ MCD_OPC_Decode, 160, 13, 111, // Opcode: EE_ZERO_Q +/* 3235 */ MCD_OPC_FilterValue, 14, 131, 3, 0, // Skip to: 4139 +/* 3240 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 3243 */ MCD_OPC_FilterValue, 0, 137, 0, 0, // Skip to: 3385 +/* 3248 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 3251 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3279 +/* 3256 */ MCD_OPC_CheckPredicate, 22, 152, 3, 0, // Skip to: 4181 +/* 3261 */ MCD_OPC_CheckField, 15, 1, 0, 145, 3, 0, // Skip to: 4181 +/* 3268 */ MCD_OPC_CheckField, 0, 4, 4, 138, 3, 0, // Skip to: 4181 +/* 3275 */ MCD_OPC_Decode, 232, 11, 77, // Opcode: EE_LD_ACCX_IP +/* 3279 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 3307 +/* 3284 */ MCD_OPC_CheckPredicate, 22, 124, 3, 0, // Skip to: 4181 +/* 3289 */ MCD_OPC_CheckField, 15, 1, 0, 117, 3, 0, // Skip to: 4181 +/* 3296 */ MCD_OPC_CheckField, 0, 4, 4, 110, 3, 0, // Skip to: 4181 +/* 3303 */ MCD_OPC_Decode, 233, 11, 78, // Opcode: EE_LD_QACC_H_H_32_IP +/* 3307 */ MCD_OPC_FilterValue, 3, 101, 3, 0, // Skip to: 4181 +/* 3312 */ MCD_OPC_ExtractField, 12, 2, // Inst{13-12} ... +/* 3315 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 3350 +/* 3320 */ MCD_OPC_CheckPredicate, 22, 88, 3, 0, // Skip to: 4181 +/* 3325 */ MCD_OPC_CheckField, 22, 1, 1, 81, 3, 0, // Skip to: 4181 +/* 3332 */ MCD_OPC_CheckField, 14, 2, 1, 74, 3, 0, // Skip to: 4181 +/* 3339 */ MCD_OPC_CheckField, 0, 4, 4, 67, 3, 0, // Skip to: 4181 +/* 3346 */ MCD_OPC_Decode, 222, 11, 75, // Opcode: EE_LDQA_S16_128_XP +/* 3350 */ MCD_OPC_FilterValue, 1, 58, 3, 0, // Skip to: 4181 +/* 3355 */ MCD_OPC_CheckPredicate, 22, 53, 3, 0, // Skip to: 4181 +/* 3360 */ MCD_OPC_CheckField, 22, 1, 1, 46, 3, 0, // Skip to: 4181 +/* 3367 */ MCD_OPC_CheckField, 15, 1, 0, 39, 3, 0, // Skip to: 4181 +/* 3374 */ MCD_OPC_CheckField, 0, 4, 4, 32, 3, 0, // Skip to: 4181 +/* 3381 */ MCD_OPC_Decode, 130, 12, 112, // Opcode: EE_SRS_ACCX +/* 3385 */ MCD_OPC_FilterValue, 1, 23, 3, 0, // Skip to: 4181 +/* 3390 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 3393 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 3521 +/* 3398 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3401 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3429 +/* 3406 */ MCD_OPC_CheckPredicate, 22, 2, 3, 0, // Skip to: 4181 +/* 3411 */ MCD_OPC_CheckField, 22, 1, 0, 251, 2, 0, // Skip to: 4181 +/* 3418 */ MCD_OPC_CheckField, 0, 4, 4, 244, 2, 0, // Skip to: 4181 +/* 3425 */ MCD_OPC_Decode, 204, 11, 113, // Opcode: EE_CMUL_S16 +/* 3429 */ MCD_OPC_FilterValue, 1, 235, 2, 0, // Skip to: 4181 +/* 3434 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3437 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3458 +/* 3442 */ MCD_OPC_CheckPredicate, 22, 222, 2, 0, // Skip to: 4181 +/* 3447 */ MCD_OPC_CheckField, 22, 1, 0, 215, 2, 0, // Skip to: 4181 +/* 3454 */ MCD_OPC_Decode, 158, 12, 114, // Opcode: EE_VCMP_LT_S32 +/* 3458 */ MCD_OPC_FilterValue, 20, 16, 0, 0, // Skip to: 3479 +/* 3463 */ MCD_OPC_CheckPredicate, 22, 201, 2, 0, // Skip to: 4181 +/* 3468 */ MCD_OPC_CheckField, 22, 1, 0, 194, 2, 0, // Skip to: 4181 +/* 3475 */ MCD_OPC_Decode, 159, 12, 114, // Opcode: EE_VCMP_LT_S8 +/* 3479 */ MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 3500 +/* 3484 */ MCD_OPC_CheckPredicate, 22, 180, 2, 0, // Skip to: 4181 +/* 3489 */ MCD_OPC_CheckField, 22, 1, 0, 173, 2, 0, // Skip to: 4181 +/* 3496 */ MCD_OPC_Decode, 176, 12, 114, // Opcode: EE_VMAX_S16 +/* 3500 */ MCD_OPC_FilterValue, 52, 164, 2, 0, // Skip to: 4181 +/* 3505 */ MCD_OPC_CheckPredicate, 22, 159, 2, 0, // Skip to: 4181 +/* 3510 */ MCD_OPC_CheckField, 22, 1, 0, 152, 2, 0, // Skip to: 4181 +/* 3517 */ MCD_OPC_Decode, 179, 12, 114, // Opcode: EE_VMAX_S32 +/* 3521 */ MCD_OPC_FilterValue, 1, 197, 0, 0, // Skip to: 3723 +/* 3526 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 3529 */ MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 3615 +/* 3534 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3537 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3565 +/* 3542 */ MCD_OPC_CheckPredicate, 22, 122, 2, 0, // Skip to: 4181 +/* 3547 */ MCD_OPC_CheckField, 22, 1, 0, 115, 2, 0, // Skip to: 4181 +/* 3554 */ MCD_OPC_CheckField, 0, 4, 4, 108, 2, 0, // Skip to: 4181 +/* 3561 */ MCD_OPC_Decode, 133, 13, 115, // Opcode: EE_VSMULAS_S8_QACC +/* 3565 */ MCD_OPC_FilterValue, 1, 99, 2, 0, // Skip to: 4181 +/* 3570 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 3573 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3594 +/* 3578 */ MCD_OPC_CheckPredicate, 22, 86, 2, 0, // Skip to: 4181 +/* 3583 */ MCD_OPC_CheckField, 22, 1, 0, 79, 2, 0, // Skip to: 4181 +/* 3590 */ MCD_OPC_Decode, 182, 12, 114, // Opcode: EE_VMAX_S8 +/* 3594 */ MCD_OPC_FilterValue, 20, 70, 2, 0, // Skip to: 4181 +/* 3599 */ MCD_OPC_CheckPredicate, 22, 65, 2, 0, // Skip to: 4181 +/* 3604 */ MCD_OPC_CheckField, 22, 1, 0, 58, 2, 0, // Skip to: 4181 +/* 3611 */ MCD_OPC_Decode, 185, 12, 114, // Opcode: EE_VMIN_S16 +/* 3615 */ MCD_OPC_FilterValue, 1, 49, 2, 0, // Skip to: 4181 +/* 3620 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 3623 */ MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 3673 +/* 3628 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3631 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3652 +/* 3636 */ MCD_OPC_CheckPredicate, 22, 28, 2, 0, // Skip to: 4181 +/* 3641 */ MCD_OPC_CheckField, 22, 1, 0, 21, 2, 0, // Skip to: 4181 +/* 3648 */ MCD_OPC_Decode, 142, 12, 114, // Opcode: EE_VADDS_S16 +/* 3652 */ MCD_OPC_FilterValue, 1, 12, 2, 0, // Skip to: 4181 +/* 3657 */ MCD_OPC_CheckPredicate, 22, 7, 2, 0, // Skip to: 4181 +/* 3662 */ MCD_OPC_CheckField, 22, 1, 0, 0, 2, 0, // Skip to: 4181 +/* 3669 */ MCD_OPC_Decode, 188, 12, 114, // Opcode: EE_VMIN_S32 +/* 3673 */ MCD_OPC_FilterValue, 20, 247, 1, 0, // Skip to: 4181 +/* 3678 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3681 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3702 +/* 3686 */ MCD_OPC_CheckPredicate, 22, 234, 1, 0, // Skip to: 4181 +/* 3691 */ MCD_OPC_CheckField, 22, 1, 0, 227, 1, 0, // Skip to: 4181 +/* 3698 */ MCD_OPC_Decode, 145, 12, 114, // Opcode: EE_VADDS_S32 +/* 3702 */ MCD_OPC_FilterValue, 1, 218, 1, 0, // Skip to: 4181 +/* 3707 */ MCD_OPC_CheckPredicate, 22, 213, 1, 0, // Skip to: 4181 +/* 3712 */ MCD_OPC_CheckField, 22, 1, 0, 206, 1, 0, // Skip to: 4181 +/* 3719 */ MCD_OPC_Decode, 191, 12, 114, // Opcode: EE_VMIN_S8 +/* 3723 */ MCD_OPC_FilterValue, 2, 203, 0, 0, // Skip to: 3931 +/* 3728 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3731 */ MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 3781 +/* 3736 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3739 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3760 +/* 3744 */ MCD_OPC_CheckPredicate, 22, 176, 1, 0, // Skip to: 4181 +/* 3749 */ MCD_OPC_CheckField, 22, 1, 0, 169, 1, 0, // Skip to: 4181 +/* 3756 */ MCD_OPC_Decode, 148, 12, 114, // Opcode: EE_VADDS_S8 +/* 3760 */ MCD_OPC_FilterValue, 1, 160, 1, 0, // Skip to: 4181 +/* 3765 */ MCD_OPC_CheckPredicate, 22, 155, 1, 0, // Skip to: 4181 +/* 3770 */ MCD_OPC_CheckField, 22, 1, 0, 148, 1, 0, // Skip to: 4181 +/* 3777 */ MCD_OPC_Decode, 242, 12, 114, // Opcode: EE_VMUL_S16 +/* 3781 */ MCD_OPC_FilterValue, 20, 45, 0, 0, // Skip to: 3831 +/* 3786 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3789 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3810 +/* 3794 */ MCD_OPC_CheckPredicate, 22, 126, 1, 0, // Skip to: 4181 +/* 3799 */ MCD_OPC_CheckField, 22, 1, 0, 119, 1, 0, // Skip to: 4181 +/* 3806 */ MCD_OPC_Decode, 151, 12, 114, // Opcode: EE_VCMP_EQ_S16 +/* 3810 */ MCD_OPC_FilterValue, 1, 110, 1, 0, // Skip to: 4181 +/* 3815 */ MCD_OPC_CheckPredicate, 22, 105, 1, 0, // Skip to: 4181 +/* 3820 */ MCD_OPC_CheckField, 22, 1, 0, 98, 1, 0, // Skip to: 4181 +/* 3827 */ MCD_OPC_Decode, 245, 12, 114, // Opcode: EE_VMUL_S8 +/* 3831 */ MCD_OPC_FilterValue, 36, 45, 0, 0, // Skip to: 3881 +/* 3836 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3839 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3860 +/* 3844 */ MCD_OPC_CheckPredicate, 22, 76, 1, 0, // Skip to: 4181 +/* 3849 */ MCD_OPC_CheckField, 22, 1, 0, 69, 1, 0, // Skip to: 4181 +/* 3856 */ MCD_OPC_Decode, 152, 12, 114, // Opcode: EE_VCMP_EQ_S32 +/* 3860 */ MCD_OPC_FilterValue, 1, 60, 1, 0, // Skip to: 4181 +/* 3865 */ MCD_OPC_CheckPredicate, 22, 55, 1, 0, // Skip to: 4181 +/* 3870 */ MCD_OPC_CheckField, 22, 1, 0, 48, 1, 0, // Skip to: 4181 +/* 3877 */ MCD_OPC_Decode, 248, 12, 114, // Opcode: EE_VMUL_U16 +/* 3881 */ MCD_OPC_FilterValue, 52, 39, 1, 0, // Skip to: 4181 +/* 3886 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3889 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3910 +/* 3894 */ MCD_OPC_CheckPredicate, 22, 26, 1, 0, // Skip to: 4181 +/* 3899 */ MCD_OPC_CheckField, 22, 1, 0, 19, 1, 0, // Skip to: 4181 +/* 3906 */ MCD_OPC_Decode, 153, 12, 114, // Opcode: EE_VCMP_EQ_S8 +/* 3910 */ MCD_OPC_FilterValue, 1, 10, 1, 0, // Skip to: 4181 +/* 3915 */ MCD_OPC_CheckPredicate, 22, 5, 1, 0, // Skip to: 4181 +/* 3920 */ MCD_OPC_CheckField, 22, 1, 0, 254, 0, 0, // Skip to: 4181 +/* 3927 */ MCD_OPC_Decode, 251, 12, 114, // Opcode: EE_VMUL_U8 +/* 3931 */ MCD_OPC_FilterValue, 3, 245, 0, 0, // Skip to: 4181 +/* 3936 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3939 */ MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 3989 +/* 3944 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3947 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3968 +/* 3952 */ MCD_OPC_CheckPredicate, 22, 224, 0, 0, // Skip to: 4181 +/* 3957 */ MCD_OPC_CheckField, 22, 1, 0, 217, 0, 0, // Skip to: 4181 +/* 3964 */ MCD_OPC_Decode, 154, 12, 114, // Opcode: EE_VCMP_GT_S16 +/* 3968 */ MCD_OPC_FilterValue, 1, 208, 0, 0, // Skip to: 4181 +/* 3973 */ MCD_OPC_CheckPredicate, 22, 203, 0, 0, // Skip to: 4181 +/* 3978 */ MCD_OPC_CheckField, 22, 1, 0, 196, 0, 0, // Skip to: 4181 +/* 3985 */ MCD_OPC_Decode, 131, 13, 116, // Opcode: EE_VSMULAS_S16_QACC +/* 3989 */ MCD_OPC_FilterValue, 20, 45, 0, 0, // Skip to: 4039 +/* 3994 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3997 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4018 +/* 4002 */ MCD_OPC_CheckPredicate, 22, 174, 0, 0, // Skip to: 4181 +/* 4007 */ MCD_OPC_CheckField, 22, 1, 0, 167, 0, 0, // Skip to: 4181 +/* 4014 */ MCD_OPC_Decode, 155, 12, 114, // Opcode: EE_VCMP_GT_S32 +/* 4018 */ MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 4181 +/* 4023 */ MCD_OPC_CheckPredicate, 22, 153, 0, 0, // Skip to: 4181 +/* 4028 */ MCD_OPC_CheckField, 22, 1, 0, 146, 0, 0, // Skip to: 4181 +/* 4035 */ MCD_OPC_Decode, 142, 13, 114, // Opcode: EE_VSUBS_S16 +/* 4039 */ MCD_OPC_FilterValue, 36, 45, 0, 0, // Skip to: 4089 +/* 4044 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 4047 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4068 +/* 4052 */ MCD_OPC_CheckPredicate, 22, 124, 0, 0, // Skip to: 4181 +/* 4057 */ MCD_OPC_CheckField, 22, 1, 0, 117, 0, 0, // Skip to: 4181 +/* 4064 */ MCD_OPC_Decode, 156, 12, 114, // Opcode: EE_VCMP_GT_S8 +/* 4068 */ MCD_OPC_FilterValue, 1, 108, 0, 0, // Skip to: 4181 +/* 4073 */ MCD_OPC_CheckPredicate, 22, 103, 0, 0, // Skip to: 4181 +/* 4078 */ MCD_OPC_CheckField, 22, 1, 0, 96, 0, 0, // Skip to: 4181 +/* 4085 */ MCD_OPC_Decode, 145, 13, 114, // Opcode: EE_VSUBS_S32 +/* 4089 */ MCD_OPC_FilterValue, 52, 87, 0, 0, // Skip to: 4181 +/* 4094 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 4097 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4118 +/* 4102 */ MCD_OPC_CheckPredicate, 22, 74, 0, 0, // Skip to: 4181 +/* 4107 */ MCD_OPC_CheckField, 22, 1, 0, 67, 0, 0, // Skip to: 4181 +/* 4114 */ MCD_OPC_Decode, 157, 12, 114, // Opcode: EE_VCMP_LT_S16 +/* 4118 */ MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 4181 +/* 4123 */ MCD_OPC_CheckPredicate, 22, 53, 0, 0, // Skip to: 4181 +/* 4128 */ MCD_OPC_CheckField, 22, 1, 0, 46, 0, 0, // Skip to: 4181 +/* 4135 */ MCD_OPC_Decode, 148, 13, 114, // Opcode: EE_VSUBS_S8 +/* 4139 */ MCD_OPC_FilterValue, 15, 37, 0, 0, // Skip to: 4181 +/* 4144 */ MCD_OPC_CheckPredicate, 22, 32, 0, 0, // Skip to: 4181 +/* 4149 */ MCD_OPC_CheckField, 22, 2, 2, 25, 0, 0, // Skip to: 4181 +/* 4156 */ MCD_OPC_CheckField, 12, 3, 0, 18, 0, 0, // Skip to: 4181 +/* 4163 */ MCD_OPC_CheckField, 6, 4, 0, 11, 0, 0, // Skip to: 4181 +/* 4170 */ MCD_OPC_CheckField, 0, 5, 4, 4, 0, 0, // Skip to: 4181 +/* 4177 */ MCD_OPC_Decode, 198, 15, 117, // Opcode: mv_QR +/* 4181 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableESP32S332[] = { +/* 0 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... +/* 3 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 24 +/* 8 */ MCD_OPC_CheckPredicate, 22, 102, 9, 0, // Skip to: 2419 +/* 13 */ MCD_OPC_CheckField, 1, 3, 7, 95, 9, 0, // Skip to: 2419 +/* 20 */ MCD_OPC_Decode, 196, 12, 118, // Opcode: EE_VMULAS_S16_ACCX_LD_IP_QUP +/* 24 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 45 +/* 29 */ MCD_OPC_CheckPredicate, 22, 81, 9, 0, // Skip to: 2419 +/* 34 */ MCD_OPC_CheckField, 1, 3, 7, 74, 9, 0, // Skip to: 2419 +/* 41 */ MCD_OPC_Decode, 203, 12, 118, // Opcode: EE_VMULAS_S16_QACC_LD_IP_QUP +/* 45 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 66 +/* 50 */ MCD_OPC_CheckPredicate, 22, 60, 9, 0, // Skip to: 2419 +/* 55 */ MCD_OPC_CheckField, 1, 3, 7, 53, 9, 0, // Skip to: 2419 +/* 62 */ MCD_OPC_Decode, 208, 12, 118, // Opcode: EE_VMULAS_S8_ACCX_LD_IP_QUP +/* 66 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 87 +/* 71 */ MCD_OPC_CheckPredicate, 22, 39, 9, 0, // Skip to: 2419 +/* 76 */ MCD_OPC_CheckField, 1, 3, 7, 32, 9, 0, // Skip to: 2419 +/* 83 */ MCD_OPC_Decode, 215, 12, 118, // Opcode: EE_VMULAS_S8_QACC_LD_IP_QUP +/* 87 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 108 +/* 92 */ MCD_OPC_CheckPredicate, 22, 18, 9, 0, // Skip to: 2419 +/* 97 */ MCD_OPC_CheckField, 1, 3, 7, 11, 9, 0, // Skip to: 2419 +/* 104 */ MCD_OPC_Decode, 220, 12, 118, // Opcode: EE_VMULAS_U16_ACCX_LD_IP_QUP +/* 108 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 129 +/* 113 */ MCD_OPC_CheckPredicate, 22, 253, 8, 0, // Skip to: 2419 +/* 118 */ MCD_OPC_CheckField, 1, 3, 7, 246, 8, 0, // Skip to: 2419 +/* 125 */ MCD_OPC_Decode, 227, 12, 118, // Opcode: EE_VMULAS_U16_QACC_LD_IP_QUP +/* 129 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 150 +/* 134 */ MCD_OPC_CheckPredicate, 22, 232, 8, 0, // Skip to: 2419 +/* 139 */ MCD_OPC_CheckField, 1, 3, 7, 225, 8, 0, // Skip to: 2419 +/* 146 */ MCD_OPC_Decode, 232, 12, 118, // Opcode: EE_VMULAS_U8_ACCX_LD_IP_QUP +/* 150 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 171 +/* 155 */ MCD_OPC_CheckPredicate, 22, 211, 8, 0, // Skip to: 2419 +/* 160 */ MCD_OPC_CheckField, 1, 3, 7, 204, 8, 0, // Skip to: 2419 +/* 167 */ MCD_OPC_Decode, 239, 12, 118, // Opcode: EE_VMULAS_U8_QACC_LD_IP_QUP +/* 171 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 221 +/* 176 */ MCD_OPC_ExtractField, 27, 1, // Inst{27} ... +/* 179 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 200 +/* 184 */ MCD_OPC_CheckPredicate, 22, 182, 8, 0, // Skip to: 2419 +/* 189 */ MCD_OPC_CheckField, 1, 3, 7, 175, 8, 0, // Skip to: 2419 +/* 196 */ MCD_OPC_Decode, 217, 11, 119, // Opcode: EE_LDF_128_IP +/* 200 */ MCD_OPC_FilterValue, 1, 166, 8, 0, // Skip to: 2419 +/* 205 */ MCD_OPC_CheckPredicate, 22, 161, 8, 0, // Skip to: 2419 +/* 210 */ MCD_OPC_CheckField, 1, 3, 7, 154, 8, 0, // Skip to: 2419 +/* 217 */ MCD_OPC_Decode, 218, 11, 120, // Opcode: EE_LDF_128_XP +/* 221 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 271 +/* 226 */ MCD_OPC_ExtractField, 27, 1, // Inst{27} ... +/* 229 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 250 +/* 234 */ MCD_OPC_CheckPredicate, 22, 132, 8, 0, // Skip to: 2419 +/* 239 */ MCD_OPC_CheckField, 1, 3, 7, 125, 8, 0, // Skip to: 2419 +/* 246 */ MCD_OPC_Decode, 131, 12, 121, // Opcode: EE_STF_128_IP +/* 250 */ MCD_OPC_FilterValue, 1, 116, 8, 0, // Skip to: 2419 +/* 255 */ MCD_OPC_CheckPredicate, 22, 111, 8, 0, // Skip to: 2419 +/* 260 */ MCD_OPC_CheckField, 1, 3, 7, 104, 8, 0, // Skip to: 2419 +/* 267 */ MCD_OPC_Decode, 132, 12, 122, // Opcode: EE_STF_128_XP +/* 271 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 321 +/* 276 */ MCD_OPC_ExtractField, 27, 1, // Inst{27} ... +/* 279 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 300 +/* 284 */ MCD_OPC_CheckPredicate, 22, 82, 8, 0, // Skip to: 2419 +/* 289 */ MCD_OPC_CheckField, 1, 3, 7, 75, 8, 0, // Skip to: 2419 +/* 296 */ MCD_OPC_Decode, 210, 11, 123, // Opcode: EE_FFT_AMS_S16_ST_INCP +/* 300 */ MCD_OPC_FilterValue, 1, 66, 8, 0, // Skip to: 2419 +/* 305 */ MCD_OPC_CheckPredicate, 22, 61, 8, 0, // Skip to: 2419 +/* 310 */ MCD_OPC_CheckField, 1, 3, 7, 54, 8, 0, // Skip to: 2419 +/* 317 */ MCD_OPC_Decode, 212, 11, 124, // Opcode: EE_FFT_CMUL_S16_ST_XP +/* 321 */ MCD_OPC_FilterValue, 11, 87, 0, 0, // Skip to: 413 +/* 326 */ MCD_OPC_ExtractField, 26, 2, // Inst{27-26} ... +/* 329 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 350 +/* 334 */ MCD_OPC_CheckPredicate, 22, 32, 8, 0, // Skip to: 2419 +/* 339 */ MCD_OPC_CheckField, 1, 3, 7, 25, 8, 0, // Skip to: 2419 +/* 346 */ MCD_OPC_Decode, 198, 12, 125, // Opcode: EE_VMULAS_S16_ACCX_LD_XP_QUP +/* 350 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 371 +/* 355 */ MCD_OPC_CheckPredicate, 22, 11, 8, 0, // Skip to: 2419 +/* 360 */ MCD_OPC_CheckField, 1, 3, 7, 4, 8, 0, // Skip to: 2419 +/* 367 */ MCD_OPC_Decode, 205, 12, 125, // Opcode: EE_VMULAS_S16_QACC_LD_XP_QUP +/* 371 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 392 +/* 376 */ MCD_OPC_CheckPredicate, 22, 246, 7, 0, // Skip to: 2419 +/* 381 */ MCD_OPC_CheckField, 1, 3, 7, 239, 7, 0, // Skip to: 2419 +/* 388 */ MCD_OPC_Decode, 210, 12, 125, // Opcode: EE_VMULAS_S8_ACCX_LD_XP_QUP +/* 392 */ MCD_OPC_FilterValue, 3, 230, 7, 0, // Skip to: 2419 +/* 397 */ MCD_OPC_CheckPredicate, 22, 225, 7, 0, // Skip to: 2419 +/* 402 */ MCD_OPC_CheckField, 1, 3, 7, 218, 7, 0, // Skip to: 2419 +/* 409 */ MCD_OPC_Decode, 217, 12, 125, // Opcode: EE_VMULAS_S8_QACC_LD_XP_QUP +/* 413 */ MCD_OPC_FilterValue, 12, 87, 0, 0, // Skip to: 505 +/* 418 */ MCD_OPC_ExtractField, 26, 2, // Inst{27-26} ... +/* 421 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 442 +/* 426 */ MCD_OPC_CheckPredicate, 22, 196, 7, 0, // Skip to: 2419 +/* 431 */ MCD_OPC_CheckField, 1, 3, 7, 189, 7, 0, // Skip to: 2419 +/* 438 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: EE_VMULAS_U16_ACCX_LD_XP_QUP +/* 442 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 463 +/* 447 */ MCD_OPC_CheckPredicate, 22, 175, 7, 0, // Skip to: 2419 +/* 452 */ MCD_OPC_CheckField, 1, 3, 7, 168, 7, 0, // Skip to: 2419 +/* 459 */ MCD_OPC_Decode, 229, 12, 125, // Opcode: EE_VMULAS_U16_QACC_LD_XP_QUP +/* 463 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 484 +/* 468 */ MCD_OPC_CheckPredicate, 22, 154, 7, 0, // Skip to: 2419 +/* 473 */ MCD_OPC_CheckField, 1, 3, 7, 147, 7, 0, // Skip to: 2419 +/* 480 */ MCD_OPC_Decode, 234, 12, 125, // Opcode: EE_VMULAS_U8_ACCX_LD_XP_QUP +/* 484 */ MCD_OPC_FilterValue, 3, 138, 7, 0, // Skip to: 2419 +/* 489 */ MCD_OPC_CheckPredicate, 22, 133, 7, 0, // Skip to: 2419 +/* 494 */ MCD_OPC_CheckField, 1, 3, 7, 126, 7, 0, // Skip to: 2419 +/* 501 */ MCD_OPC_Decode, 241, 12, 125, // Opcode: EE_VMULAS_U8_QACC_LD_XP_QUP +/* 505 */ MCD_OPC_FilterValue, 13, 87, 0, 0, // Skip to: 597 +/* 510 */ MCD_OPC_ExtractField, 26, 2, // Inst{27-26} ... +/* 513 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 534 +/* 518 */ MCD_OPC_CheckPredicate, 22, 104, 7, 0, // Skip to: 2419 +/* 523 */ MCD_OPC_CheckField, 1, 3, 7, 97, 7, 0, // Skip to: 2419 +/* 530 */ MCD_OPC_Decode, 207, 11, 126, // Opcode: EE_FFT_AMS_S16_LD_INCP +/* 534 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 555 +/* 539 */ MCD_OPC_CheckPredicate, 22, 83, 7, 0, // Skip to: 2419 +/* 544 */ MCD_OPC_CheckField, 1, 3, 7, 76, 7, 0, // Skip to: 2419 +/* 551 */ MCD_OPC_Decode, 208, 11, 126, // Opcode: EE_FFT_AMS_S16_LD_INCP_UAUP +/* 555 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 576 +/* 560 */ MCD_OPC_CheckPredicate, 22, 62, 7, 0, // Skip to: 2419 +/* 565 */ MCD_OPC_CheckField, 1, 3, 7, 55, 7, 0, // Skip to: 2419 +/* 572 */ MCD_OPC_Decode, 209, 11, 126, // Opcode: EE_FFT_AMS_S16_LD_R32_DECP +/* 576 */ MCD_OPC_FilterValue, 3, 46, 7, 0, // Skip to: 2419 +/* 581 */ MCD_OPC_CheckPredicate, 22, 41, 7, 0, // Skip to: 2419 +/* 586 */ MCD_OPC_CheckField, 1, 3, 7, 34, 7, 0, // Skip to: 2419 +/* 593 */ MCD_OPC_Decode, 211, 11, 127, // Opcode: EE_FFT_CMUL_S16_LD_XP +/* 597 */ MCD_OPC_FilterValue, 14, 57, 5, 0, // Skip to: 1939 +/* 602 */ MCD_OPC_ExtractField, 26, 2, // Inst{27-26} ... +/* 605 */ MCD_OPC_FilterValue, 0, 212, 2, 0, // Skip to: 1334 +/* 610 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 613 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 635 +/* 618 */ MCD_OPC_CheckPredicate, 22, 4, 7, 0, // Skip to: 2419 +/* 623 */ MCD_OPC_CheckField, 1, 3, 7, 253, 6, 0, // Skip to: 2419 +/* 630 */ MCD_OPC_Decode, 255, 11, 128, 1, // Opcode: EE_SRC_Q_LD_IP +/* 635 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 687 +/* 640 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 643 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 665 +/* 648 */ MCD_OPC_CheckPredicate, 22, 230, 6, 0, // Skip to: 2419 +/* 653 */ MCD_OPC_CheckField, 1, 3, 7, 223, 6, 0, // Skip to: 2419 +/* 660 */ MCD_OPC_Decode, 219, 11, 129, 1, // Opcode: EE_LDF_64_IP +/* 665 */ MCD_OPC_FilterValue, 1, 213, 6, 0, // Skip to: 2419 +/* 670 */ MCD_OPC_CheckPredicate, 22, 208, 6, 0, // Skip to: 2419 +/* 675 */ MCD_OPC_CheckField, 1, 3, 7, 201, 6, 0, // Skip to: 2419 +/* 682 */ MCD_OPC_Decode, 133, 12, 130, 1, // Opcode: EE_STF_64_IP +/* 687 */ MCD_OPC_FilterValue, 2, 91, 0, 0, // Skip to: 783 +/* 692 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 695 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 717 +/* 700 */ MCD_OPC_CheckPredicate, 22, 178, 6, 0, // Skip to: 2419 +/* 705 */ MCD_OPC_CheckField, 1, 3, 7, 171, 6, 0, // Skip to: 2419 +/* 712 */ MCD_OPC_Decode, 201, 12, 131, 1, // Opcode: EE_VMULAS_S16_QACC_LDBC_INCP_QUP +/* 717 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 739 +/* 722 */ MCD_OPC_CheckPredicate, 22, 156, 6, 0, // Skip to: 2419 +/* 727 */ MCD_OPC_CheckField, 1, 3, 7, 149, 6, 0, // Skip to: 2419 +/* 734 */ MCD_OPC_Decode, 213, 12, 131, 1, // Opcode: EE_VMULAS_S8_QACC_LDBC_INCP_QUP +/* 739 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 761 +/* 744 */ MCD_OPC_CheckPredicate, 22, 134, 6, 0, // Skip to: 2419 +/* 749 */ MCD_OPC_CheckField, 1, 3, 7, 127, 6, 0, // Skip to: 2419 +/* 756 */ MCD_OPC_Decode, 225, 12, 131, 1, // Opcode: EE_VMULAS_U16_QACC_LDBC_INCP_QUP +/* 761 */ MCD_OPC_FilterValue, 3, 117, 6, 0, // Skip to: 2419 +/* 766 */ MCD_OPC_CheckPredicate, 22, 112, 6, 0, // Skip to: 2419 +/* 771 */ MCD_OPC_CheckField, 1, 3, 7, 105, 6, 0, // Skip to: 2419 +/* 778 */ MCD_OPC_Decode, 237, 12, 131, 1, // Opcode: EE_VMULAS_U8_QACC_LDBC_INCP_QUP +/* 783 */ MCD_OPC_FilterValue, 3, 95, 6, 0, // Skip to: 2419 +/* 788 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 791 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 917 +/* 796 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 799 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 821 +/* 804 */ MCD_OPC_CheckPredicate, 22, 74, 6, 0, // Skip to: 2419 +/* 809 */ MCD_OPC_CheckField, 1, 3, 7, 67, 6, 0, // Skip to: 2419 +/* 816 */ MCD_OPC_Decode, 205, 11, 132, 1, // Opcode: EE_CMUL_S16_LD_INCP +/* 821 */ MCD_OPC_FilterValue, 1, 57, 6, 0, // Skip to: 2419 +/* 826 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 829 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 851 +/* 834 */ MCD_OPC_CheckPredicate, 22, 44, 6, 0, // Skip to: 2419 +/* 839 */ MCD_OPC_CheckField, 1, 3, 7, 37, 6, 0, // Skip to: 2419 +/* 846 */ MCD_OPC_Decode, 149, 12, 133, 1, // Opcode: EE_VADDS_S8_LD_INCP +/* 851 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 873 +/* 856 */ MCD_OPC_CheckPredicate, 22, 22, 6, 0, // Skip to: 2419 +/* 861 */ MCD_OPC_CheckField, 1, 3, 7, 15, 6, 0, // Skip to: 2419 +/* 868 */ MCD_OPC_Decode, 177, 12, 133, 1, // Opcode: EE_VMAX_S16_LD_INCP +/* 873 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 895 +/* 878 */ MCD_OPC_CheckPredicate, 22, 0, 6, 0, // Skip to: 2419 +/* 883 */ MCD_OPC_CheckField, 1, 3, 7, 249, 5, 0, // Skip to: 2419 +/* 890 */ MCD_OPC_Decode, 180, 12, 133, 1, // Opcode: EE_VMAX_S32_LD_INCP +/* 895 */ MCD_OPC_FilterValue, 3, 239, 5, 0, // Skip to: 2419 +/* 900 */ MCD_OPC_CheckPredicate, 22, 234, 5, 0, // Skip to: 2419 +/* 905 */ MCD_OPC_CheckField, 1, 3, 7, 227, 5, 0, // Skip to: 2419 +/* 912 */ MCD_OPC_Decode, 183, 12, 133, 1, // Opcode: EE_VMAX_S8_LD_INCP +/* 917 */ MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1103 +/* 922 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 925 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 947 +/* 930 */ MCD_OPC_CheckPredicate, 22, 204, 5, 0, // Skip to: 2419 +/* 935 */ MCD_OPC_CheckField, 1, 3, 7, 197, 5, 0, // Skip to: 2419 +/* 942 */ MCD_OPC_Decode, 134, 13, 134, 1, // Opcode: EE_VSMULAS_S8_QACC_LD_INCP +/* 947 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 999 +/* 952 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 955 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 977 +/* 960 */ MCD_OPC_CheckPredicate, 22, 174, 5, 0, // Skip to: 2419 +/* 965 */ MCD_OPC_CheckField, 1, 3, 7, 167, 5, 0, // Skip to: 2419 +/* 972 */ MCD_OPC_Decode, 143, 12, 133, 1, // Opcode: EE_VADDS_S16_LD_INCP +/* 977 */ MCD_OPC_FilterValue, 1, 157, 5, 0, // Skip to: 2419 +/* 982 */ MCD_OPC_CheckPredicate, 22, 152, 5, 0, // Skip to: 2419 +/* 987 */ MCD_OPC_CheckField, 1, 3, 7, 145, 5, 0, // Skip to: 2419 +/* 994 */ MCD_OPC_Decode, 146, 12, 133, 1, // Opcode: EE_VADDS_S32_LD_INCP +/* 999 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 1051 +/* 1004 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1007 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1029 +/* 1012 */ MCD_OPC_CheckPredicate, 22, 122, 5, 0, // Skip to: 2419 +/* 1017 */ MCD_OPC_CheckField, 1, 3, 7, 115, 5, 0, // Skip to: 2419 +/* 1024 */ MCD_OPC_Decode, 186, 12, 133, 1, // Opcode: EE_VMIN_S16_LD_INCP +/* 1029 */ MCD_OPC_FilterValue, 1, 105, 5, 0, // Skip to: 2419 +/* 1034 */ MCD_OPC_CheckPredicate, 22, 100, 5, 0, // Skip to: 2419 +/* 1039 */ MCD_OPC_CheckField, 1, 3, 7, 93, 5, 0, // Skip to: 2419 +/* 1046 */ MCD_OPC_Decode, 189, 12, 133, 1, // Opcode: EE_VMIN_S32_LD_INCP +/* 1051 */ MCD_OPC_FilterValue, 3, 83, 5, 0, // Skip to: 2419 +/* 1056 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1059 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1081 +/* 1064 */ MCD_OPC_CheckPredicate, 22, 70, 5, 0, // Skip to: 2419 +/* 1069 */ MCD_OPC_CheckField, 1, 3, 7, 63, 5, 0, // Skip to: 2419 +/* 1076 */ MCD_OPC_Decode, 192, 12, 133, 1, // Opcode: EE_VMIN_S8_LD_INCP +/* 1081 */ MCD_OPC_FilterValue, 1, 53, 5, 0, // Skip to: 2419 +/* 1086 */ MCD_OPC_CheckPredicate, 22, 48, 5, 0, // Skip to: 2419 +/* 1091 */ MCD_OPC_CheckField, 1, 3, 7, 41, 5, 0, // Skip to: 2419 +/* 1098 */ MCD_OPC_Decode, 243, 12, 133, 1, // Opcode: EE_VMUL_S16_LD_INCP +/* 1103 */ MCD_OPC_FilterValue, 2, 107, 0, 0, // Skip to: 1215 +/* 1108 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 1111 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1163 +/* 1116 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1119 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1141 +/* 1124 */ MCD_OPC_CheckPredicate, 22, 10, 5, 0, // Skip to: 2419 +/* 1129 */ MCD_OPC_CheckField, 1, 3, 7, 3, 5, 0, // Skip to: 2419 +/* 1136 */ MCD_OPC_Decode, 246, 12, 133, 1, // Opcode: EE_VMUL_S8_LD_INCP +/* 1141 */ MCD_OPC_FilterValue, 1, 249, 4, 0, // Skip to: 2419 +/* 1146 */ MCD_OPC_CheckPredicate, 22, 244, 4, 0, // Skip to: 2419 +/* 1151 */ MCD_OPC_CheckField, 1, 3, 7, 237, 4, 0, // Skip to: 2419 +/* 1158 */ MCD_OPC_Decode, 249, 12, 133, 1, // Opcode: EE_VMUL_U16_LD_INCP +/* 1163 */ MCD_OPC_FilterValue, 1, 227, 4, 0, // Skip to: 2419 +/* 1168 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1171 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1193 +/* 1176 */ MCD_OPC_CheckPredicate, 22, 214, 4, 0, // Skip to: 2419 +/* 1181 */ MCD_OPC_CheckField, 1, 3, 7, 207, 4, 0, // Skip to: 2419 +/* 1188 */ MCD_OPC_Decode, 143, 13, 133, 1, // Opcode: EE_VSUBS_S16_LD_INCP +/* 1193 */ MCD_OPC_FilterValue, 1, 197, 4, 0, // Skip to: 2419 +/* 1198 */ MCD_OPC_CheckPredicate, 22, 192, 4, 0, // Skip to: 2419 +/* 1203 */ MCD_OPC_CheckField, 1, 3, 7, 185, 4, 0, // Skip to: 2419 +/* 1210 */ MCD_OPC_Decode, 146, 13, 133, 1, // Opcode: EE_VSUBS_S32_LD_INCP +/* 1215 */ MCD_OPC_FilterValue, 3, 175, 4, 0, // Skip to: 2419 +/* 1220 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 1223 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1275 +/* 1228 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1231 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1253 +/* 1236 */ MCD_OPC_CheckPredicate, 22, 154, 4, 0, // Skip to: 2419 +/* 1241 */ MCD_OPC_CheckField, 1, 3, 7, 147, 4, 0, // Skip to: 2419 +/* 1248 */ MCD_OPC_Decode, 252, 12, 133, 1, // Opcode: EE_VMUL_U8_LD_INCP +/* 1253 */ MCD_OPC_FilterValue, 1, 137, 4, 0, // Skip to: 2419 +/* 1258 */ MCD_OPC_CheckPredicate, 22, 132, 4, 0, // Skip to: 2419 +/* 1263 */ MCD_OPC_CheckField, 1, 3, 7, 125, 4, 0, // Skip to: 2419 +/* 1270 */ MCD_OPC_Decode, 132, 13, 135, 1, // Opcode: EE_VSMULAS_S16_QACC_LD_INCP +/* 1275 */ MCD_OPC_FilterValue, 1, 115, 4, 0, // Skip to: 2419 +/* 1280 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1283 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1305 +/* 1288 */ MCD_OPC_CheckPredicate, 22, 102, 4, 0, // Skip to: 2419 +/* 1293 */ MCD_OPC_CheckField, 1, 3, 7, 95, 4, 0, // Skip to: 2419 +/* 1300 */ MCD_OPC_Decode, 149, 13, 133, 1, // Opcode: EE_VSUBS_S8_LD_INCP +/* 1305 */ MCD_OPC_FilterValue, 1, 85, 4, 0, // Skip to: 2419 +/* 1310 */ MCD_OPC_CheckPredicate, 22, 80, 4, 0, // Skip to: 2419 +/* 1315 */ MCD_OPC_CheckField, 25, 1, 0, 73, 4, 0, // Skip to: 2419 +/* 1322 */ MCD_OPC_CheckField, 1, 3, 7, 66, 4, 0, // Skip to: 2419 +/* 1329 */ MCD_OPC_Decode, 229, 11, 136, 1, // Opcode: EE_LDXQ_32 +/* 1334 */ MCD_OPC_FilterValue, 1, 140, 1, 0, // Skip to: 1735 +/* 1339 */ MCD_OPC_ExtractField, 25, 1, // Inst{25} ... +/* 1342 */ MCD_OPC_FilterValue, 0, 96, 1, 0, // Skip to: 1699 +/* 1347 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 1350 */ MCD_OPC_FilterValue, 0, 128, 0, 0, // Skip to: 1483 +/* 1355 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 1358 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1387 +/* 1363 */ MCD_OPC_CheckPredicate, 22, 27, 4, 0, // Skip to: 2419 +/* 1368 */ MCD_OPC_CheckField, 10, 2, 0, 20, 4, 0, // Skip to: 2419 +/* 1375 */ MCD_OPC_CheckField, 1, 3, 7, 13, 4, 0, // Skip to: 2419 +/* 1382 */ MCD_OPC_Decode, 206, 11, 137, 1, // Opcode: EE_CMUL_S16_ST_INCP +/* 1387 */ MCD_OPC_FilterValue, 1, 3, 4, 0, // Skip to: 2419 +/* 1392 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1395 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1417 +/* 1400 */ MCD_OPC_CheckPredicate, 22, 246, 3, 0, // Skip to: 2419 +/* 1405 */ MCD_OPC_CheckField, 1, 3, 7, 239, 3, 0, // Skip to: 2419 +/* 1412 */ MCD_OPC_Decode, 181, 12, 138, 1, // Opcode: EE_VMAX_S32_ST_INCP +/* 1417 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1439 +/* 1422 */ MCD_OPC_CheckPredicate, 22, 224, 3, 0, // Skip to: 2419 +/* 1427 */ MCD_OPC_CheckField, 1, 3, 7, 217, 3, 0, // Skip to: 2419 +/* 1434 */ MCD_OPC_Decode, 187, 12, 138, 1, // Opcode: EE_VMIN_S16_ST_INCP +/* 1439 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1461 +/* 1444 */ MCD_OPC_CheckPredicate, 22, 202, 3, 0, // Skip to: 2419 +/* 1449 */ MCD_OPC_CheckField, 1, 3, 7, 195, 3, 0, // Skip to: 2419 +/* 1456 */ MCD_OPC_Decode, 193, 12, 138, 1, // Opcode: EE_VMIN_S8_ST_INCP +/* 1461 */ MCD_OPC_FilterValue, 3, 185, 3, 0, // Skip to: 2419 +/* 1466 */ MCD_OPC_CheckPredicate, 22, 180, 3, 0, // Skip to: 2419 +/* 1471 */ MCD_OPC_CheckField, 1, 3, 7, 173, 3, 0, // Skip to: 2419 +/* 1478 */ MCD_OPC_Decode, 247, 12, 138, 1, // Opcode: EE_VMUL_S8_ST_INCP +/* 1483 */ MCD_OPC_FilterValue, 1, 163, 3, 0, // Skip to: 2419 +/* 1488 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1491 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1543 +/* 1496 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 1499 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1521 +/* 1504 */ MCD_OPC_CheckPredicate, 22, 142, 3, 0, // Skip to: 2419 +/* 1509 */ MCD_OPC_CheckField, 1, 3, 7, 135, 3, 0, // Skip to: 2419 +/* 1516 */ MCD_OPC_Decode, 144, 12, 138, 1, // Opcode: EE_VADDS_S16_ST_INCP +/* 1521 */ MCD_OPC_FilterValue, 1, 125, 3, 0, // Skip to: 2419 +/* 1526 */ MCD_OPC_CheckPredicate, 22, 120, 3, 0, // Skip to: 2419 +/* 1531 */ MCD_OPC_CheckField, 1, 3, 7, 113, 3, 0, // Skip to: 2419 +/* 1538 */ MCD_OPC_Decode, 184, 12, 138, 1, // Opcode: EE_VMAX_S8_ST_INCP +/* 1543 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 1595 +/* 1548 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 1551 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1573 +/* 1556 */ MCD_OPC_CheckPredicate, 22, 90, 3, 0, // Skip to: 2419 +/* 1561 */ MCD_OPC_CheckField, 1, 3, 7, 83, 3, 0, // Skip to: 2419 +/* 1568 */ MCD_OPC_Decode, 147, 12, 138, 1, // Opcode: EE_VADDS_S32_ST_INCP +/* 1573 */ MCD_OPC_FilterValue, 1, 73, 3, 0, // Skip to: 2419 +/* 1578 */ MCD_OPC_CheckPredicate, 22, 68, 3, 0, // Skip to: 2419 +/* 1583 */ MCD_OPC_CheckField, 1, 3, 7, 61, 3, 0, // Skip to: 2419 +/* 1590 */ MCD_OPC_Decode, 190, 12, 138, 1, // Opcode: EE_VMIN_S32_ST_INCP +/* 1595 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 1647 +/* 1600 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 1603 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1625 +/* 1608 */ MCD_OPC_CheckPredicate, 22, 38, 3, 0, // Skip to: 2419 +/* 1613 */ MCD_OPC_CheckField, 1, 3, 7, 31, 3, 0, // Skip to: 2419 +/* 1620 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: EE_VADDS_S8_ST_INCP +/* 1625 */ MCD_OPC_FilterValue, 1, 21, 3, 0, // Skip to: 2419 +/* 1630 */ MCD_OPC_CheckPredicate, 22, 16, 3, 0, // Skip to: 2419 +/* 1635 */ MCD_OPC_CheckField, 1, 3, 7, 9, 3, 0, // Skip to: 2419 +/* 1642 */ MCD_OPC_Decode, 244, 12, 138, 1, // Opcode: EE_VMUL_S16_ST_INCP +/* 1647 */ MCD_OPC_FilterValue, 3, 255, 2, 0, // Skip to: 2419 +/* 1652 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 1655 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1677 +/* 1660 */ MCD_OPC_CheckPredicate, 22, 242, 2, 0, // Skip to: 2419 +/* 1665 */ MCD_OPC_CheckField, 1, 3, 7, 235, 2, 0, // Skip to: 2419 +/* 1672 */ MCD_OPC_Decode, 178, 12, 138, 1, // Opcode: EE_VMAX_S16_ST_INCP +/* 1677 */ MCD_OPC_FilterValue, 1, 225, 2, 0, // Skip to: 2419 +/* 1682 */ MCD_OPC_CheckPredicate, 22, 220, 2, 0, // Skip to: 2419 +/* 1687 */ MCD_OPC_CheckField, 1, 3, 7, 213, 2, 0, // Skip to: 2419 +/* 1694 */ MCD_OPC_Decode, 250, 12, 138, 1, // Opcode: EE_VMUL_U16_ST_INCP +/* 1699 */ MCD_OPC_FilterValue, 1, 203, 2, 0, // Skip to: 2419 +/* 1704 */ MCD_OPC_CheckPredicate, 22, 198, 2, 0, // Skip to: 2419 +/* 1709 */ MCD_OPC_CheckField, 16, 3, 0, 191, 2, 0, // Skip to: 2419 +/* 1716 */ MCD_OPC_CheckField, 8, 4, 0, 184, 2, 0, // Skip to: 2419 +/* 1723 */ MCD_OPC_CheckField, 1, 3, 7, 177, 2, 0, // Skip to: 2419 +/* 1730 */ MCD_OPC_Decode, 135, 12, 139, 1, // Opcode: EE_STXQ_32 +/* 1735 */ MCD_OPC_FilterValue, 2, 167, 2, 0, // Skip to: 2419 +/* 1740 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 1743 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1779 +/* 1748 */ MCD_OPC_CheckPredicate, 22, 154, 2, 0, // Skip to: 2419 +/* 1753 */ MCD_OPC_CheckField, 23, 3, 0, 147, 2, 0, // Skip to: 2419 +/* 1760 */ MCD_OPC_CheckField, 12, 2, 0, 140, 2, 0, // Skip to: 2419 +/* 1767 */ MCD_OPC_CheckField, 1, 3, 7, 133, 2, 0, // Skip to: 2419 +/* 1774 */ MCD_OPC_Decode, 128, 12, 140, 1, // Opcode: EE_SRC_Q_LD_XP +/* 1779 */ MCD_OPC_FilterValue, 1, 123, 2, 0, // Skip to: 2419 +/* 1784 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1787 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1816 +/* 1792 */ MCD_OPC_CheckPredicate, 22, 110, 2, 0, // Skip to: 2419 +/* 1797 */ MCD_OPC_CheckField, 24, 2, 0, 103, 2, 0, // Skip to: 2419 +/* 1804 */ MCD_OPC_CheckField, 1, 3, 7, 96, 2, 0, // Skip to: 2419 +/* 1811 */ MCD_OPC_Decode, 253, 12, 138, 1, // Opcode: EE_VMUL_U8_ST_INCP +/* 1816 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 1845 +/* 1821 */ MCD_OPC_CheckPredicate, 22, 81, 2, 0, // Skip to: 2419 +/* 1826 */ MCD_OPC_CheckField, 24, 2, 0, 74, 2, 0, // Skip to: 2419 +/* 1833 */ MCD_OPC_CheckField, 1, 3, 7, 67, 2, 0, // Skip to: 2419 +/* 1840 */ MCD_OPC_Decode, 144, 13, 138, 1, // Opcode: EE_VSUBS_S16_ST_INCP +/* 1845 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 1874 +/* 1850 */ MCD_OPC_CheckPredicate, 22, 52, 2, 0, // Skip to: 2419 +/* 1855 */ MCD_OPC_CheckField, 24, 2, 0, 45, 2, 0, // Skip to: 2419 +/* 1862 */ MCD_OPC_CheckField, 1, 3, 7, 38, 2, 0, // Skip to: 2419 +/* 1869 */ MCD_OPC_Decode, 147, 13, 138, 1, // Opcode: EE_VSUBS_S32_ST_INCP +/* 1874 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 1903 +/* 1879 */ MCD_OPC_CheckPredicate, 22, 23, 2, 0, // Skip to: 2419 +/* 1884 */ MCD_OPC_CheckField, 24, 2, 0, 16, 2, 0, // Skip to: 2419 +/* 1891 */ MCD_OPC_CheckField, 1, 3, 7, 9, 2, 0, // Skip to: 2419 +/* 1898 */ MCD_OPC_Decode, 150, 13, 138, 1, // Opcode: EE_VSUBS_S8_ST_INCP +/* 1903 */ MCD_OPC_FilterValue, 4, 255, 1, 0, // Skip to: 2419 +/* 1908 */ MCD_OPC_CheckPredicate, 22, 250, 1, 0, // Skip to: 2419 +/* 1913 */ MCD_OPC_CheckField, 24, 2, 0, 243, 1, 0, // Skip to: 2419 +/* 1920 */ MCD_OPC_CheckField, 13, 1, 0, 236, 1, 0, // Skip to: 2419 +/* 1927 */ MCD_OPC_CheckField, 1, 3, 7, 229, 1, 0, // Skip to: 2419 +/* 1934 */ MCD_OPC_Decode, 214, 11, 141, 1, // Opcode: EE_FFT_R2BF_S16_ST_INCP +/* 1939 */ MCD_OPC_FilterValue, 15, 219, 1, 0, // Skip to: 2419 +/* 1944 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 1947 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 2006 +/* 1952 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 1955 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1977 +/* 1960 */ MCD_OPC_CheckPredicate, 22, 198, 1, 0, // Skip to: 2419 +/* 1965 */ MCD_OPC_CheckField, 1, 3, 7, 191, 1, 0, // Skip to: 2419 +/* 1972 */ MCD_OPC_Decode, 195, 12, 142, 1, // Opcode: EE_VMULAS_S16_ACCX_LD_IP +/* 1977 */ MCD_OPC_FilterValue, 1, 181, 1, 0, // Skip to: 2419 +/* 1982 */ MCD_OPC_CheckPredicate, 22, 176, 1, 0, // Skip to: 2419 +/* 1987 */ MCD_OPC_CheckField, 26, 2, 0, 169, 1, 0, // Skip to: 2419 +/* 1994 */ MCD_OPC_CheckField, 1, 3, 7, 162, 1, 0, // Skip to: 2419 +/* 2001 */ MCD_OPC_Decode, 197, 12, 143, 1, // Opcode: EE_VMULAS_S16_ACCX_LD_XP +/* 2006 */ MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 2065 +/* 2011 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 2014 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2036 +/* 2019 */ MCD_OPC_CheckPredicate, 22, 139, 1, 0, // Skip to: 2419 +/* 2024 */ MCD_OPC_CheckField, 1, 3, 7, 132, 1, 0, // Skip to: 2419 +/* 2031 */ MCD_OPC_Decode, 202, 12, 142, 1, // Opcode: EE_VMULAS_S16_QACC_LD_IP +/* 2036 */ MCD_OPC_FilterValue, 1, 122, 1, 0, // Skip to: 2419 +/* 2041 */ MCD_OPC_CheckPredicate, 22, 117, 1, 0, // Skip to: 2419 +/* 2046 */ MCD_OPC_CheckField, 26, 2, 0, 110, 1, 0, // Skip to: 2419 +/* 2053 */ MCD_OPC_CheckField, 1, 3, 7, 103, 1, 0, // Skip to: 2419 +/* 2060 */ MCD_OPC_Decode, 204, 12, 143, 1, // Opcode: EE_VMULAS_S16_QACC_LD_XP +/* 2065 */ MCD_OPC_FilterValue, 2, 54, 0, 0, // Skip to: 2124 +/* 2070 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 2073 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2095 +/* 2078 */ MCD_OPC_CheckPredicate, 22, 80, 1, 0, // Skip to: 2419 +/* 2083 */ MCD_OPC_CheckField, 1, 3, 7, 73, 1, 0, // Skip to: 2419 +/* 2090 */ MCD_OPC_Decode, 207, 12, 142, 1, // Opcode: EE_VMULAS_S8_ACCX_LD_IP +/* 2095 */ MCD_OPC_FilterValue, 1, 63, 1, 0, // Skip to: 2419 +/* 2100 */ MCD_OPC_CheckPredicate, 22, 58, 1, 0, // Skip to: 2419 +/* 2105 */ MCD_OPC_CheckField, 26, 2, 0, 51, 1, 0, // Skip to: 2419 +/* 2112 */ MCD_OPC_CheckField, 1, 3, 7, 44, 1, 0, // Skip to: 2419 +/* 2119 */ MCD_OPC_Decode, 209, 12, 143, 1, // Opcode: EE_VMULAS_S8_ACCX_LD_XP +/* 2124 */ MCD_OPC_FilterValue, 3, 54, 0, 0, // Skip to: 2183 +/* 2129 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 2132 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2154 +/* 2137 */ MCD_OPC_CheckPredicate, 22, 21, 1, 0, // Skip to: 2419 +/* 2142 */ MCD_OPC_CheckField, 1, 3, 7, 14, 1, 0, // Skip to: 2419 +/* 2149 */ MCD_OPC_Decode, 214, 12, 142, 1, // Opcode: EE_VMULAS_S8_QACC_LD_IP +/* 2154 */ MCD_OPC_FilterValue, 1, 4, 1, 0, // Skip to: 2419 +/* 2159 */ MCD_OPC_CheckPredicate, 22, 255, 0, 0, // Skip to: 2419 +/* 2164 */ MCD_OPC_CheckField, 26, 2, 0, 248, 0, 0, // Skip to: 2419 +/* 2171 */ MCD_OPC_CheckField, 1, 3, 7, 241, 0, 0, // Skip to: 2419 +/* 2178 */ MCD_OPC_Decode, 216, 12, 143, 1, // Opcode: EE_VMULAS_S8_QACC_LD_XP +/* 2183 */ MCD_OPC_FilterValue, 4, 54, 0, 0, // Skip to: 2242 +/* 2188 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 2191 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2213 +/* 2196 */ MCD_OPC_CheckPredicate, 22, 218, 0, 0, // Skip to: 2419 +/* 2201 */ MCD_OPC_CheckField, 1, 3, 7, 211, 0, 0, // Skip to: 2419 +/* 2208 */ MCD_OPC_Decode, 219, 12, 142, 1, // Opcode: EE_VMULAS_U16_ACCX_LD_IP +/* 2213 */ MCD_OPC_FilterValue, 1, 201, 0, 0, // Skip to: 2419 +/* 2218 */ MCD_OPC_CheckPredicate, 22, 196, 0, 0, // Skip to: 2419 +/* 2223 */ MCD_OPC_CheckField, 26, 2, 0, 189, 0, 0, // Skip to: 2419 +/* 2230 */ MCD_OPC_CheckField, 1, 3, 7, 182, 0, 0, // Skip to: 2419 +/* 2237 */ MCD_OPC_Decode, 221, 12, 143, 1, // Opcode: EE_VMULAS_U16_ACCX_LD_XP +/* 2242 */ MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 2301 +/* 2247 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 2250 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2272 +/* 2255 */ MCD_OPC_CheckPredicate, 22, 159, 0, 0, // Skip to: 2419 +/* 2260 */ MCD_OPC_CheckField, 1, 3, 7, 152, 0, 0, // Skip to: 2419 +/* 2267 */ MCD_OPC_Decode, 226, 12, 142, 1, // Opcode: EE_VMULAS_U16_QACC_LD_IP +/* 2272 */ MCD_OPC_FilterValue, 1, 142, 0, 0, // Skip to: 2419 +/* 2277 */ MCD_OPC_CheckPredicate, 22, 137, 0, 0, // Skip to: 2419 +/* 2282 */ MCD_OPC_CheckField, 26, 2, 0, 130, 0, 0, // Skip to: 2419 +/* 2289 */ MCD_OPC_CheckField, 1, 3, 7, 123, 0, 0, // Skip to: 2419 +/* 2296 */ MCD_OPC_Decode, 228, 12, 143, 1, // Opcode: EE_VMULAS_U16_QACC_LD_XP +/* 2301 */ MCD_OPC_FilterValue, 6, 54, 0, 0, // Skip to: 2360 +/* 2306 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 2309 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2331 +/* 2314 */ MCD_OPC_CheckPredicate, 22, 100, 0, 0, // Skip to: 2419 +/* 2319 */ MCD_OPC_CheckField, 1, 3, 7, 93, 0, 0, // Skip to: 2419 +/* 2326 */ MCD_OPC_Decode, 231, 12, 142, 1, // Opcode: EE_VMULAS_U8_ACCX_LD_IP +/* 2331 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 2419 +/* 2336 */ MCD_OPC_CheckPredicate, 22, 78, 0, 0, // Skip to: 2419 +/* 2341 */ MCD_OPC_CheckField, 26, 2, 0, 71, 0, 0, // Skip to: 2419 +/* 2348 */ MCD_OPC_CheckField, 1, 3, 7, 64, 0, 0, // Skip to: 2419 +/* 2355 */ MCD_OPC_Decode, 233, 12, 143, 1, // Opcode: EE_VMULAS_U8_ACCX_LD_XP +/* 2360 */ MCD_OPC_FilterValue, 7, 54, 0, 0, // Skip to: 2419 +/* 2365 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 2368 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2390 +/* 2373 */ MCD_OPC_CheckPredicate, 22, 41, 0, 0, // Skip to: 2419 +/* 2378 */ MCD_OPC_CheckField, 1, 3, 7, 34, 0, 0, // Skip to: 2419 +/* 2385 */ MCD_OPC_Decode, 238, 12, 142, 1, // Opcode: EE_VMULAS_U8_QACC_LD_IP +/* 2390 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2419 +/* 2395 */ MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 2419 +/* 2400 */ MCD_OPC_CheckField, 26, 2, 0, 12, 0, 0, // Skip to: 2419 +/* 2407 */ MCD_OPC_CheckField, 1, 3, 7, 5, 0, 0, // Skip to: 2419 +/* 2414 */ MCD_OPC_Decode, 240, 12, 143, 1, // Opcode: EE_VMULAS_U8_QACC_LD_XP +/* 2419 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableFallback16[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 17 +/* 8 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 31 +/* 13 */ MCD_OPC_Decode, 192, 15, 0, // Opcode: _L32I_N +/* 17 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 31 +/* 22 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 31 +/* 27 */ MCD_OPC_Decode, 195, 15, 0, // Opcode: _S32I_N +/* 31 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableFallback24[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 44 +/* 8 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 11 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 27 +/* 16 */ MCD_OPC_CheckField, 16, 4, 1, 56, 0, 0, // Skip to: 79 +/* 23 */ MCD_OPC_Decode, 196, 15, 11, // Opcode: _SLLI +/* 27 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 79 +/* 32 */ MCD_OPC_CheckField, 16, 5, 1, 40, 0, 0, // Skip to: 79 +/* 39 */ MCD_OPC_Decode, 197, 15, 144, 1, // Opcode: _SRLI +/* 44 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 79 +/* 49 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 52 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 61 +/* 57 */ MCD_OPC_Decode, 191, 15, 49, // Opcode: _L32I +/* 61 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 70 +/* 66 */ MCD_OPC_Decode, 194, 15, 49, // Opcode: _S32I +/* 70 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 79 +/* 75 */ MCD_OPC_Decode, 193, 15, 50, // Opcode: _MOVI +/* 79 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableHIFI324[] = { +/* 0 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3 */ MCD_OPC_FilterValue, 0, 137, 1, 0, // Skip to: 401 +/* 8 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 11 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 33 +/* 16 */ MCD_OPC_CheckPredicate, 24, 188, 20, 0, // Skip to: 5329 +/* 21 */ MCD_OPC_CheckField, 0, 4, 4, 181, 20, 0, // Skip to: 5329 +/* 28 */ MCD_OPC_Decode, 146, 10, 145, 1, // Opcode: AE_S32X2RA64S_IP +/* 33 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 55 +/* 38 */ MCD_OPC_CheckPredicate, 24, 166, 20, 0, // Skip to: 5329 +/* 43 */ MCD_OPC_CheckField, 0, 4, 4, 159, 20, 0, // Skip to: 5329 +/* 50 */ MCD_OPC_Decode, 159, 10, 146, 1, // Opcode: AE_S64_I +/* 55 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 77 +/* 60 */ MCD_OPC_CheckPredicate, 24, 144, 20, 0, // Skip to: 5329 +/* 65 */ MCD_OPC_CheckField, 0, 4, 4, 137, 20, 0, // Skip to: 5329 +/* 72 */ MCD_OPC_Decode, 160, 10, 147, 1, // Opcode: AE_S64_IP +/* 77 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 99 +/* 82 */ MCD_OPC_CheckPredicate, 24, 122, 20, 0, // Skip to: 5329 +/* 87 */ MCD_OPC_CheckField, 0, 4, 4, 115, 20, 0, // Skip to: 5329 +/* 94 */ MCD_OPC_Decode, 251, 9, 145, 1, // Opcode: AE_S24X2RA64S_IP +/* 99 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 121 +/* 104 */ MCD_OPC_CheckPredicate, 24, 100, 20, 0, // Skip to: 5329 +/* 109 */ MCD_OPC_CheckField, 0, 4, 4, 93, 20, 0, // Skip to: 5329 +/* 116 */ MCD_OPC_Decode, 138, 10, 148, 1, // Opcode: AE_S32RA64S_XP +/* 121 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 143 +/* 126 */ MCD_OPC_CheckPredicate, 24, 78, 20, 0, // Skip to: 5329 +/* 131 */ MCD_OPC_CheckField, 0, 4, 4, 71, 20, 0, // Skip to: 5329 +/* 138 */ MCD_OPC_Decode, 209, 10, 149, 1, // Opcode: AE_SLAA32S +/* 143 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 165 +/* 148 */ MCD_OPC_CheckPredicate, 24, 56, 20, 0, // Skip to: 5329 +/* 153 */ MCD_OPC_CheckField, 0, 4, 4, 49, 20, 0, // Skip to: 5329 +/* 160 */ MCD_OPC_Decode, 232, 10, 149, 1, // Opcode: AE_SRAA32 +/* 165 */ MCD_OPC_FilterValue, 12, 91, 0, 0, // Skip to: 261 +/* 170 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 173 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 195 +/* 178 */ MCD_OPC_CheckPredicate, 24, 26, 20, 0, // Skip to: 5329 +/* 183 */ MCD_OPC_CheckField, 0, 4, 4, 19, 20, 0, // Skip to: 5329 +/* 190 */ MCD_OPC_Decode, 195, 5, 150, 1, // Opcode: AE_LA32X2F24_IC +/* 195 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 217 +/* 200 */ MCD_OPC_CheckPredicate, 24, 4, 20, 0, // Skip to: 5329 +/* 205 */ MCD_OPC_CheckField, 0, 4, 4, 253, 19, 0, // Skip to: 5329 +/* 212 */ MCD_OPC_Decode, 196, 5, 150, 1, // Opcode: AE_LA32X2F24_IP +/* 217 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 239 +/* 222 */ MCD_OPC_CheckPredicate, 24, 238, 19, 0, // Skip to: 5329 +/* 227 */ MCD_OPC_CheckField, 0, 4, 4, 231, 19, 0, // Skip to: 5329 +/* 234 */ MCD_OPC_Decode, 165, 10, 151, 1, // Opcode: AE_SA16X4_IP +/* 239 */ MCD_OPC_FilterValue, 3, 221, 19, 0, // Skip to: 5329 +/* 244 */ MCD_OPC_CheckPredicate, 24, 216, 19, 0, // Skip to: 5329 +/* 249 */ MCD_OPC_CheckField, 0, 4, 4, 209, 19, 0, // Skip to: 5329 +/* 256 */ MCD_OPC_Decode, 181, 10, 151, 1, // Opcode: AE_SA32X2_IP +/* 261 */ MCD_OPC_FilterValue, 13, 91, 0, 0, // Skip to: 357 +/* 266 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 269 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 291 +/* 274 */ MCD_OPC_CheckPredicate, 24, 186, 19, 0, // Skip to: 5329 +/* 279 */ MCD_OPC_CheckField, 0, 4, 4, 179, 19, 0, // Skip to: 5329 +/* 286 */ MCD_OPC_Decode, 187, 5, 150, 1, // Opcode: AE_LA24X2_IC +/* 291 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 313 +/* 296 */ MCD_OPC_CheckPredicate, 24, 164, 19, 0, // Skip to: 5329 +/* 301 */ MCD_OPC_CheckField, 0, 4, 4, 157, 19, 0, // Skip to: 5329 +/* 308 */ MCD_OPC_Decode, 188, 5, 150, 1, // Opcode: AE_LA24X2_IP +/* 313 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 335 +/* 318 */ MCD_OPC_CheckPredicate, 24, 142, 19, 0, // Skip to: 5329 +/* 323 */ MCD_OPC_CheckField, 0, 4, 4, 135, 19, 0, // Skip to: 5329 +/* 330 */ MCD_OPC_Decode, 201, 5, 150, 1, // Opcode: AE_LA32X2_IC +/* 335 */ MCD_OPC_FilterValue, 3, 125, 19, 0, // Skip to: 5329 +/* 340 */ MCD_OPC_CheckPredicate, 24, 120, 19, 0, // Skip to: 5329 +/* 345 */ MCD_OPC_CheckField, 0, 4, 4, 113, 19, 0, // Skip to: 5329 +/* 352 */ MCD_OPC_Decode, 202, 5, 150, 1, // Opcode: AE_LA32X2_IP +/* 357 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 379 +/* 362 */ MCD_OPC_CheckPredicate, 24, 98, 19, 0, // Skip to: 5329 +/* 367 */ MCD_OPC_CheckField, 0, 4, 4, 91, 19, 0, // Skip to: 5329 +/* 374 */ MCD_OPC_Decode, 142, 11, 152, 1, // Opcode: AE_VLDL32T +/* 379 */ MCD_OPC_FilterValue, 15, 81, 19, 0, // Skip to: 5329 +/* 384 */ MCD_OPC_CheckPredicate, 24, 76, 19, 0, // Skip to: 5329 +/* 389 */ MCD_OPC_CheckField, 0, 4, 4, 69, 19, 0, // Skip to: 5329 +/* 396 */ MCD_OPC_Decode, 141, 11, 152, 1, // Opcode: AE_VLDL16T +/* 401 */ MCD_OPC_FilterValue, 1, 135, 0, 0, // Skip to: 541 +/* 406 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 409 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 431 +/* 414 */ MCD_OPC_CheckPredicate, 24, 46, 19, 0, // Skip to: 5329 +/* 419 */ MCD_OPC_CheckField, 0, 4, 4, 39, 19, 0, // Skip to: 5329 +/* 426 */ MCD_OPC_Decode, 236, 5, 153, 1, // Opcode: AE_MOVDA16X2 +/* 431 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 453 +/* 436 */ MCD_OPC_CheckPredicate, 24, 24, 19, 0, // Skip to: 5329 +/* 441 */ MCD_OPC_CheckField, 0, 4, 4, 17, 19, 0, // Skip to: 5329 +/* 448 */ MCD_OPC_Decode, 238, 5, 153, 1, // Opcode: AE_MOVDA32X2 +/* 453 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 475 +/* 458 */ MCD_OPC_CheckPredicate, 24, 2, 19, 0, // Skip to: 5329 +/* 463 */ MCD_OPC_CheckField, 0, 4, 4, 251, 18, 0, // Skip to: 5329 +/* 470 */ MCD_OPC_Decode, 207, 9, 154, 1, // Opcode: AE_OR +/* 475 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 497 +/* 480 */ MCD_OPC_CheckPredicate, 24, 236, 18, 0, // Skip to: 5329 +/* 485 */ MCD_OPC_CheckField, 0, 4, 4, 229, 18, 0, // Skip to: 5329 +/* 492 */ MCD_OPC_Decode, 202, 10, 155, 1, // Opcode: AE_SEXT32 +/* 497 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 519 +/* 502 */ MCD_OPC_CheckPredicate, 24, 214, 18, 0, // Skip to: 5329 +/* 507 */ MCD_OPC_CheckField, 0, 8, 20, 207, 18, 0, // Skip to: 5329 +/* 514 */ MCD_OPC_Decode, 204, 10, 156, 1, // Opcode: AE_SEXT32X2D16_32 +/* 519 */ MCD_OPC_FilterValue, 14, 197, 18, 0, // Skip to: 5329 +/* 524 */ MCD_OPC_CheckPredicate, 24, 192, 18, 0, // Skip to: 5329 +/* 529 */ MCD_OPC_CheckField, 0, 4, 4, 185, 18, 0, // Skip to: 5329 +/* 536 */ MCD_OPC_Decode, 149, 11, 154, 1, // Opcode: AE_XOR +/* 541 */ MCD_OPC_FilterValue, 2, 208, 2, 0, // Skip to: 1266 +/* 546 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 549 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 571 +/* 554 */ MCD_OPC_CheckPredicate, 24, 162, 18, 0, // Skip to: 5329 +/* 559 */ MCD_OPC_CheckField, 0, 4, 4, 155, 18, 0, // Skip to: 5329 +/* 566 */ MCD_OPC_Decode, 208, 10, 149, 1, // Opcode: AE_SLAA32 +/* 571 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 593 +/* 576 */ MCD_OPC_CheckPredicate, 24, 140, 18, 0, // Skip to: 5329 +/* 581 */ MCD_OPC_CheckField, 0, 4, 4, 133, 18, 0, // Skip to: 5329 +/* 588 */ MCD_OPC_Decode, 212, 10, 149, 1, // Opcode: AE_SLAAQ56 +/* 593 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 615 +/* 598 */ MCD_OPC_CheckPredicate, 24, 118, 18, 0, // Skip to: 5329 +/* 603 */ MCD_OPC_CheckField, 0, 4, 4, 111, 18, 0, // Skip to: 5329 +/* 610 */ MCD_OPC_Decode, 210, 10, 149, 1, // Opcode: AE_SLAA64 +/* 615 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 637 +/* 620 */ MCD_OPC_CheckPredicate, 24, 96, 18, 0, // Skip to: 5329 +/* 625 */ MCD_OPC_CheckField, 0, 4, 4, 89, 18, 0, // Skip to: 5329 +/* 632 */ MCD_OPC_Decode, 207, 10, 149, 1, // Opcode: AE_SLAA16S +/* 637 */ MCD_OPC_FilterValue, 4, 91, 0, 0, // Skip to: 733 +/* 642 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 645 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 667 +/* 650 */ MCD_OPC_CheckPredicate, 24, 66, 18, 0, // Skip to: 5329 +/* 655 */ MCD_OPC_CheckField, 0, 4, 4, 59, 18, 0, // Skip to: 5329 +/* 662 */ MCD_OPC_Decode, 221, 10, 157, 1, // Opcode: AE_SLAS24 +/* 667 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 689 +/* 672 */ MCD_OPC_CheckPredicate, 24, 44, 18, 0, // Skip to: 5329 +/* 677 */ MCD_OPC_CheckField, 0, 4, 4, 37, 18, 0, // Skip to: 5329 +/* 684 */ MCD_OPC_Decode, 227, 10, 157, 1, // Opcode: AE_SLASQ56 +/* 689 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 711 +/* 694 */ MCD_OPC_CheckPredicate, 24, 22, 18, 0, // Skip to: 5329 +/* 699 */ MCD_OPC_CheckField, 0, 4, 4, 15, 18, 0, // Skip to: 5329 +/* 706 */ MCD_OPC_Decode, 226, 10, 157, 1, // Opcode: AE_SLAS64S +/* 711 */ MCD_OPC_FilterValue, 14, 5, 18, 0, // Skip to: 5329 +/* 716 */ MCD_OPC_CheckPredicate, 24, 0, 18, 0, // Skip to: 5329 +/* 721 */ MCD_OPC_CheckField, 0, 4, 4, 249, 17, 0, // Skip to: 5329 +/* 728 */ MCD_OPC_Decode, 242, 10, 157, 1, // Opcode: AE_SRAS24 +/* 733 */ MCD_OPC_FilterValue, 5, 131, 0, 0, // Skip to: 869 +/* 738 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 741 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 757 +/* 747 */ MCD_OPC_CheckPredicate, 24, 225, 17, 0, // Skip to: 5329 +/* 752 */ MCD_OPC_Decode, 228, 5, 158, 1, // Opcode: AE_MOVAD16_0 +/* 757 */ MCD_OPC_FilterValue, 148, 1, 10, 0, 0, // Skip to: 773 +/* 763 */ MCD_OPC_CheckPredicate, 24, 209, 17, 0, // Skip to: 5329 +/* 768 */ MCD_OPC_Decode, 230, 5, 158, 1, // Opcode: AE_MOVAD16_2 +/* 773 */ MCD_OPC_FilterValue, 164, 1, 10, 0, 0, // Skip to: 789 +/* 779 */ MCD_OPC_CheckPredicate, 24, 193, 17, 0, // Skip to: 5329 +/* 784 */ MCD_OPC_Decode, 231, 5, 158, 1, // Opcode: AE_MOVAD16_3 +/* 789 */ MCD_OPC_FilterValue, 180, 1, 10, 0, 0, // Skip to: 805 +/* 795 */ MCD_OPC_CheckPredicate, 24, 177, 17, 0, // Skip to: 5329 +/* 800 */ MCD_OPC_Decode, 232, 5, 158, 1, // Opcode: AE_MOVAD32_H +/* 805 */ MCD_OPC_FilterValue, 196, 1, 10, 0, 0, // Skip to: 821 +/* 811 */ MCD_OPC_CheckPredicate, 24, 161, 17, 0, // Skip to: 5329 +/* 816 */ MCD_OPC_Decode, 233, 5, 158, 1, // Opcode: AE_MOVAD32_L +/* 821 */ MCD_OPC_FilterValue, 212, 1, 10, 0, 0, // Skip to: 837 +/* 827 */ MCD_OPC_CheckPredicate, 24, 145, 17, 0, // Skip to: 5329 +/* 832 */ MCD_OPC_Decode, 204, 9, 158, 1, // Opcode: AE_NSA64 +/* 837 */ MCD_OPC_FilterValue, 228, 1, 10, 0, 0, // Skip to: 853 +/* 843 */ MCD_OPC_CheckPredicate, 24, 129, 17, 0, // Skip to: 5329 +/* 848 */ MCD_OPC_Decode, 205, 9, 158, 1, // Opcode: AE_NSAZ16_0 +/* 853 */ MCD_OPC_FilterValue, 244, 1, 118, 17, 0, // Skip to: 5329 +/* 859 */ MCD_OPC_CheckPredicate, 24, 113, 17, 0, // Skip to: 5329 +/* 864 */ MCD_OPC_Decode, 206, 9, 158, 1, // Opcode: AE_NSAZ32_L +/* 869 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 898 +/* 874 */ MCD_OPC_CheckPredicate, 24, 98, 17, 0, // Skip to: 5329 +/* 879 */ MCD_OPC_CheckField, 8, 2, 2, 91, 17, 0, // Skip to: 5329 +/* 886 */ MCD_OPC_CheckField, 0, 4, 4, 84, 17, 0, // Skip to: 5329 +/* 893 */ MCD_OPC_Decode, 208, 9, 159, 1, // Opcode: AE_PKSR24 +/* 898 */ MCD_OPC_FilterValue, 7, 54, 0, 0, // Skip to: 957 +/* 903 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 906 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 935 +/* 911 */ MCD_OPC_CheckPredicate, 24, 61, 17, 0, // Skip to: 5329 +/* 916 */ MCD_OPC_CheckField, 10, 2, 2, 54, 17, 0, // Skip to: 5329 +/* 923 */ MCD_OPC_CheckField, 0, 4, 4, 47, 17, 0, // Skip to: 5329 +/* 930 */ MCD_OPC_Decode, 214, 4, 157, 1, // Opcode: AE_ABS64 +/* 935 */ MCD_OPC_FilterValue, 2, 37, 17, 0, // Skip to: 5329 +/* 940 */ MCD_OPC_CheckPredicate, 24, 32, 17, 0, // Skip to: 5329 +/* 945 */ MCD_OPC_CheckField, 0, 4, 4, 25, 17, 0, // Skip to: 5329 +/* 952 */ MCD_OPC_Decode, 209, 9, 159, 1, // Opcode: AE_PKSR32 +/* 957 */ MCD_OPC_FilterValue, 8, 47, 0, 0, // Skip to: 1009 +/* 962 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 965 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 987 +/* 970 */ MCD_OPC_CheckPredicate, 24, 2, 17, 0, // Skip to: 5329 +/* 975 */ MCD_OPC_CheckField, 0, 4, 4, 251, 16, 0, // Skip to: 5329 +/* 982 */ MCD_OPC_Decode, 234, 5, 160, 1, // Opcode: AE_MOVALIGN +/* 987 */ MCD_OPC_FilterValue, 19, 241, 16, 0, // Skip to: 5329 +/* 992 */ MCD_OPC_CheckPredicate, 24, 236, 16, 0, // Skip to: 5329 +/* 997 */ MCD_OPC_CheckField, 0, 6, 4, 229, 16, 0, // Skip to: 5329 +/* 1004 */ MCD_OPC_Decode, 150, 11, 161, 1, // Opcode: AE_ZALIGN64 +/* 1009 */ MCD_OPC_FilterValue, 11, 223, 0, 0, // Skip to: 1237 +/* 1014 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1017 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1039 +/* 1022 */ MCD_OPC_CheckPredicate, 24, 206, 16, 0, // Skip to: 5329 +/* 1027 */ MCD_OPC_CheckField, 0, 4, 4, 199, 16, 0, // Skip to: 5329 +/* 1034 */ MCD_OPC_Decode, 211, 4, 157, 1, // Opcode: AE_ABS24S +/* 1039 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1061 +/* 1044 */ MCD_OPC_CheckPredicate, 24, 184, 16, 0, // Skip to: 5329 +/* 1049 */ MCD_OPC_CheckField, 0, 4, 4, 177, 16, 0, // Skip to: 5329 +/* 1056 */ MCD_OPC_Decode, 210, 4, 157, 1, // Opcode: AE_ABS16S +/* 1061 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1083 +/* 1066 */ MCD_OPC_CheckPredicate, 24, 162, 16, 0, // Skip to: 5329 +/* 1071 */ MCD_OPC_CheckField, 0, 4, 4, 155, 16, 0, // Skip to: 5329 +/* 1078 */ MCD_OPC_Decode, 213, 4, 157, 1, // Opcode: AE_ABS32S +/* 1083 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1105 +/* 1088 */ MCD_OPC_CheckPredicate, 24, 140, 16, 0, // Skip to: 5329 +/* 1093 */ MCD_OPC_CheckField, 0, 4, 4, 133, 16, 0, // Skip to: 5329 +/* 1100 */ MCD_OPC_Decode, 245, 4, 162, 1, // Opcode: AE_DIV64D32_L +/* 1105 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1127 +/* 1110 */ MCD_OPC_CheckPredicate, 24, 118, 16, 0, // Skip to: 5329 +/* 1115 */ MCD_OPC_CheckField, 0, 4, 4, 111, 16, 0, // Skip to: 5329 +/* 1122 */ MCD_OPC_Decode, 202, 9, 157, 1, // Opcode: AE_NEG64 +/* 1127 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1149 +/* 1132 */ MCD_OPC_CheckPredicate, 24, 96, 16, 0, // Skip to: 5329 +/* 1137 */ MCD_OPC_CheckField, 0, 4, 4, 89, 16, 0, // Skip to: 5329 +/* 1144 */ MCD_OPC_Decode, 198, 9, 157, 1, // Opcode: AE_NEG16S +/* 1149 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1171 +/* 1154 */ MCD_OPC_CheckPredicate, 24, 74, 16, 0, // Skip to: 5329 +/* 1159 */ MCD_OPC_CheckField, 0, 4, 4, 67, 16, 0, // Skip to: 5329 +/* 1166 */ MCD_OPC_Decode, 201, 9, 157, 1, // Opcode: AE_NEG32S +/* 1171 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1193 +/* 1176 */ MCD_OPC_CheckPredicate, 24, 52, 16, 0, // Skip to: 5329 +/* 1181 */ MCD_OPC_CheckField, 0, 4, 4, 45, 16, 0, // Skip to: 5329 +/* 1188 */ MCD_OPC_Decode, 222, 9, 157, 1, // Opcode: AE_ROUNDSQ32F48ASYM +/* 1193 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 1215 +/* 1198 */ MCD_OPC_CheckPredicate, 24, 30, 16, 0, // Skip to: 5329 +/* 1203 */ MCD_OPC_CheckField, 0, 4, 4, 23, 16, 0, // Skip to: 5329 +/* 1210 */ MCD_OPC_Decode, 223, 9, 157, 1, // Opcode: AE_ROUNDSQ32F48SYM +/* 1215 */ MCD_OPC_FilterValue, 10, 13, 16, 0, // Skip to: 5329 +/* 1220 */ MCD_OPC_CheckPredicate, 24, 8, 16, 0, // Skip to: 5329 +/* 1225 */ MCD_OPC_CheckField, 0, 4, 4, 1, 16, 0, // Skip to: 5329 +/* 1232 */ MCD_OPC_Decode, 189, 10, 157, 1, // Opcode: AE_SAT48S +/* 1237 */ MCD_OPC_FilterValue, 12, 247, 15, 0, // Skip to: 5329 +/* 1242 */ MCD_OPC_CheckPredicate, 24, 242, 15, 0, // Skip to: 5329 +/* 1247 */ MCD_OPC_CheckField, 7, 1, 1, 235, 15, 0, // Skip to: 5329 +/* 1254 */ MCD_OPC_CheckField, 0, 4, 4, 228, 15, 0, // Skip to: 5329 +/* 1261 */ MCD_OPC_Decode, 154, 5, 163, 1, // Opcode: AE_L32X2F24_IP +/* 1266 */ MCD_OPC_FilterValue, 3, 243, 1, 0, // Skip to: 1770 +/* 1271 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 1274 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1296 +/* 1279 */ MCD_OPC_CheckPredicate, 24, 205, 15, 0, // Skip to: 5329 +/* 1284 */ MCD_OPC_CheckField, 0, 4, 4, 198, 15, 0, // Skip to: 5329 +/* 1291 */ MCD_OPC_Decode, 219, 4, 154, 1, // Opcode: AE_ADD32 +/* 1296 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1318 +/* 1301 */ MCD_OPC_CheckPredicate, 24, 183, 15, 0, // Skip to: 5329 +/* 1306 */ MCD_OPC_CheckField, 0, 4, 4, 176, 15, 0, // Skip to: 5329 +/* 1313 */ MCD_OPC_Decode, 222, 4, 154, 1, // Opcode: AE_ADD64 +/* 1318 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1340 +/* 1323 */ MCD_OPC_CheckPredicate, 24, 161, 15, 0, // Skip to: 5329 +/* 1328 */ MCD_OPC_CheckField, 0, 4, 4, 154, 15, 0, // Skip to: 5329 +/* 1335 */ MCD_OPC_Decode, 218, 4, 154, 1, // Opcode: AE_ADD24S +/* 1340 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1362 +/* 1345 */ MCD_OPC_CheckPredicate, 24, 139, 15, 0, // Skip to: 5329 +/* 1350 */ MCD_OPC_CheckField, 0, 4, 4, 132, 15, 0, // Skip to: 5329 +/* 1357 */ MCD_OPC_Decode, 217, 4, 154, 1, // Opcode: AE_ADD16S +/* 1362 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 1390 +/* 1367 */ MCD_OPC_CheckPredicate, 24, 117, 15, 0, // Skip to: 5329 +/* 1372 */ MCD_OPC_CheckField, 8, 8, 16, 110, 15, 0, // Skip to: 5329 +/* 1379 */ MCD_OPC_CheckField, 0, 4, 4, 103, 15, 0, // Skip to: 5329 +/* 1386 */ MCD_OPC_Decode, 143, 11, 25, // Opcode: AE_VLDSHT +/* 1390 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 1419 +/* 1395 */ MCD_OPC_CheckPredicate, 24, 89, 15, 0, // Skip to: 5329 +/* 1400 */ MCD_OPC_CheckField, 6, 2, 2, 82, 15, 0, // Skip to: 5329 +/* 1407 */ MCD_OPC_CheckField, 0, 4, 4, 75, 15, 0, // Skip to: 5329 +/* 1414 */ MCD_OPC_Decode, 182, 5, 150, 1, // Opcode: AE_LA16X4_RIP +/* 1419 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1441 +/* 1424 */ MCD_OPC_CheckPredicate, 24, 60, 15, 0, // Skip to: 5329 +/* 1429 */ MCD_OPC_CheckField, 0, 8, 132, 1, 52, 15, 0, // Skip to: 5329 +/* 1437 */ MCD_OPC_Decode, 205, 10, 18, // Opcode: AE_SHA32 +/* 1441 */ MCD_OPC_FilterValue, 7, 47, 0, 0, // Skip to: 1493 +/* 1446 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1449 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1471 +/* 1454 */ MCD_OPC_CheckPredicate, 24, 30, 15, 0, // Skip to: 5329 +/* 1459 */ MCD_OPC_CheckField, 0, 4, 4, 23, 15, 0, // Skip to: 5329 +/* 1466 */ MCD_OPC_Decode, 179, 5, 150, 1, // Opcode: AE_LA16X4_IC +/* 1471 */ MCD_OPC_FilterValue, 3, 13, 15, 0, // Skip to: 5329 +/* 1476 */ MCD_OPC_CheckPredicate, 24, 8, 15, 0, // Skip to: 5329 +/* 1481 */ MCD_OPC_CheckField, 0, 4, 4, 1, 15, 0, // Skip to: 5329 +/* 1488 */ MCD_OPC_Decode, 180, 5, 150, 1, // Opcode: AE_LA16X4_IP +/* 1493 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 1515 +/* 1498 */ MCD_OPC_CheckPredicate, 24, 242, 14, 0, // Skip to: 5329 +/* 1503 */ MCD_OPC_CheckField, 0, 5, 20, 235, 14, 0, // Skip to: 5329 +/* 1510 */ MCD_OPC_Decode, 240, 5, 164, 1, // Opcode: AE_MOVF32X2 +/* 1515 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 1537 +/* 1520 */ MCD_OPC_CheckPredicate, 24, 220, 14, 0, // Skip to: 5329 +/* 1525 */ MCD_OPC_CheckField, 0, 5, 20, 213, 14, 0, // Skip to: 5329 +/* 1532 */ MCD_OPC_Decode, 244, 5, 164, 1, // Opcode: AE_MOVT32X2 +/* 1537 */ MCD_OPC_FilterValue, 12, 48, 0, 0, // Skip to: 1590 +/* 1542 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 1545 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 1560 +/* 1550 */ MCD_OPC_CheckPredicate, 24, 190, 14, 0, // Skip to: 5329 +/* 1555 */ MCD_OPC_Decode, 230, 4, 165, 1, // Opcode: AE_CVT48A32 +/* 1560 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 1575 +/* 1565 */ MCD_OPC_CheckPredicate, 24, 175, 14, 0, // Skip to: 5329 +/* 1570 */ MCD_OPC_Decode, 235, 5, 165, 1, // Opcode: AE_MOVDA16 +/* 1575 */ MCD_OPC_FilterValue, 52, 165, 14, 0, // Skip to: 5329 +/* 1580 */ MCD_OPC_CheckPredicate, 24, 160, 14, 0, // Skip to: 5329 +/* 1585 */ MCD_OPC_Decode, 237, 5, 165, 1, // Opcode: AE_MOVDA32 +/* 1590 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1658 +/* 1595 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1598 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1636 +/* 1603 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1606 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 1621 +/* 1611 */ MCD_OPC_CheckPredicate, 24, 129, 14, 0, // Skip to: 5329 +/* 1616 */ MCD_OPC_Decode, 163, 5, 166, 1, // Opcode: AE_L32X2_RIP +/* 1621 */ MCD_OPC_FilterValue, 36, 119, 14, 0, // Skip to: 5329 +/* 1626 */ MCD_OPC_CheckPredicate, 24, 114, 14, 0, // Skip to: 5329 +/* 1631 */ MCD_OPC_Decode, 156, 5, 166, 1, // Opcode: AE_L32X2F24_RIP +/* 1636 */ MCD_OPC_FilterValue, 2, 104, 14, 0, // Skip to: 5329 +/* 1641 */ MCD_OPC_CheckPredicate, 24, 99, 14, 0, // Skip to: 5329 +/* 1646 */ MCD_OPC_CheckField, 0, 4, 4, 92, 14, 0, // Skip to: 5329 +/* 1653 */ MCD_OPC_Decode, 242, 5, 167, 1, // Opcode: AE_MOVI +/* 1658 */ MCD_OPC_FilterValue, 14, 78, 0, 0, // Skip to: 1741 +/* 1663 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1666 */ MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 1719 +/* 1671 */ MCD_OPC_ExtractField, 0, 7, // Inst{6-0} ... +/* 1674 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 1689 +/* 1679 */ MCD_OPC_CheckPredicate, 24, 61, 14, 0, // Skip to: 5329 +/* 1684 */ MCD_OPC_Decode, 227, 5, 156, 1, // Opcode: AE_MOV +/* 1689 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 1704 +/* 1694 */ MCD_OPC_CheckPredicate, 24, 46, 14, 0, // Skip to: 5329 +/* 1699 */ MCD_OPC_Decode, 236, 4, 156, 1, // Opcode: AE_CVTQ56P32S_H +/* 1704 */ MCD_OPC_FilterValue, 52, 36, 14, 0, // Skip to: 5329 +/* 1709 */ MCD_OPC_CheckPredicate, 24, 31, 14, 0, // Skip to: 5329 +/* 1714 */ MCD_OPC_Decode, 237, 4, 156, 1, // Opcode: AE_CVTQ56P32S_L +/* 1719 */ MCD_OPC_FilterValue, 1, 21, 14, 0, // Skip to: 5329 +/* 1724 */ MCD_OPC_CheckPredicate, 24, 16, 14, 0, // Skip to: 5329 +/* 1729 */ MCD_OPC_CheckField, 0, 4, 4, 9, 14, 0, // Skip to: 5329 +/* 1736 */ MCD_OPC_Decode, 161, 5, 163, 1, // Opcode: AE_L32X2_IP +/* 1741 */ MCD_OPC_FilterValue, 15, 255, 13, 0, // Skip to: 5329 +/* 1746 */ MCD_OPC_CheckPredicate, 24, 250, 13, 0, // Skip to: 5329 +/* 1751 */ MCD_OPC_CheckField, 6, 2, 3, 243, 13, 0, // Skip to: 5329 +/* 1758 */ MCD_OPC_CheckField, 0, 4, 4, 236, 13, 0, // Skip to: 5329 +/* 1765 */ MCD_OPC_Decode, 177, 10, 151, 1, // Opcode: AE_SA32X2F24_IP +/* 1770 */ MCD_OPC_FilterValue, 4, 11, 1, 0, // Skip to: 2042 +/* 1775 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 1778 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1800 +/* 1783 */ MCD_OPC_CheckPredicate, 24, 213, 13, 0, // Skip to: 5329 +/* 1788 */ MCD_OPC_CheckField, 0, 4, 4, 206, 13, 0, // Skip to: 5329 +/* 1795 */ MCD_OPC_Decode, 220, 4, 154, 1, // Opcode: AE_ADD32S +/* 1800 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1822 +/* 1805 */ MCD_OPC_CheckPredicate, 24, 191, 13, 0, // Skip to: 5329 +/* 1810 */ MCD_OPC_CheckField, 0, 4, 4, 184, 13, 0, // Skip to: 5329 +/* 1817 */ MCD_OPC_Decode, 227, 4, 154, 1, // Opcode: AE_AND +/* 1822 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1844 +/* 1827 */ MCD_OPC_CheckPredicate, 24, 169, 13, 0, // Skip to: 5329 +/* 1832 */ MCD_OPC_CheckField, 0, 4, 4, 162, 13, 0, // Skip to: 5329 +/* 1839 */ MCD_OPC_Decode, 210, 9, 168, 1, // Opcode: AE_ROUND16X4F32SASYM +/* 1844 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1866 +/* 1849 */ MCD_OPC_CheckPredicate, 24, 147, 13, 0, // Skip to: 5329 +/* 1854 */ MCD_OPC_CheckField, 0, 4, 4, 140, 13, 0, // Skip to: 5329 +/* 1861 */ MCD_OPC_Decode, 220, 9, 154, 1, // Opcode: AE_ROUNDSP16Q48X2ASYM +/* 1866 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1888 +/* 1871 */ MCD_OPC_CheckPredicate, 24, 125, 13, 0, // Skip to: 5329 +/* 1876 */ MCD_OPC_CheckField, 0, 4, 4, 118, 13, 0, // Skip to: 5329 +/* 1883 */ MCD_OPC_Decode, 212, 9, 154, 1, // Opcode: AE_ROUND24X2F48SASYM +/* 1888 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1910 +/* 1893 */ MCD_OPC_CheckPredicate, 24, 103, 13, 0, // Skip to: 5329 +/* 1898 */ MCD_OPC_CheckField, 0, 4, 4, 96, 13, 0, // Skip to: 5329 +/* 1905 */ MCD_OPC_Decode, 213, 9, 154, 1, // Opcode: AE_ROUND24X2F48SSYM +/* 1910 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1932 +/* 1915 */ MCD_OPC_CheckPredicate, 24, 81, 13, 0, // Skip to: 5329 +/* 1920 */ MCD_OPC_CheckField, 0, 4, 4, 74, 13, 0, // Skip to: 5329 +/* 1927 */ MCD_OPC_Decode, 173, 5, 169, 1, // Opcode: AE_L64_IP +/* 1932 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1954 +/* 1937 */ MCD_OPC_CheckPredicate, 24, 59, 13, 0, // Skip to: 5329 +/* 1942 */ MCD_OPC_CheckField, 0, 4, 4, 52, 13, 0, // Skip to: 5329 +/* 1949 */ MCD_OPC_Decode, 216, 9, 154, 1, // Opcode: AE_ROUND32X2F64SASYM +/* 1954 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1976 +/* 1959 */ MCD_OPC_CheckPredicate, 24, 37, 13, 0, // Skip to: 5329 +/* 1964 */ MCD_OPC_CheckField, 0, 4, 4, 30, 13, 0, // Skip to: 5329 +/* 1971 */ MCD_OPC_Decode, 128, 11, 154, 1, // Opcode: AE_SUB32 +/* 1976 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1998 +/* 1981 */ MCD_OPC_CheckPredicate, 24, 15, 13, 0, // Skip to: 5329 +/* 1986 */ MCD_OPC_CheckField, 0, 4, 4, 8, 13, 0, // Skip to: 5329 +/* 1993 */ MCD_OPC_Decode, 130, 11, 154, 1, // Opcode: AE_SUB64 +/* 1998 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2020 +/* 2003 */ MCD_OPC_CheckPredicate, 24, 249, 12, 0, // Skip to: 5329 +/* 2008 */ MCD_OPC_CheckField, 0, 4, 4, 242, 12, 0, // Skip to: 5329 +/* 2015 */ MCD_OPC_Decode, 254, 10, 154, 1, // Opcode: AE_SUB16S +/* 2020 */ MCD_OPC_FilterValue, 15, 232, 12, 0, // Skip to: 5329 +/* 2025 */ MCD_OPC_CheckPredicate, 24, 227, 12, 0, // Skip to: 5329 +/* 2030 */ MCD_OPC_CheckField, 0, 4, 4, 220, 12, 0, // Skip to: 5329 +/* 2037 */ MCD_OPC_Decode, 129, 11, 154, 1, // Opcode: AE_SUB32S +/* 2042 */ MCD_OPC_FilterValue, 5, 187, 0, 0, // Skip to: 2234 +/* 2047 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 2050 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2072 +/* 2055 */ MCD_OPC_CheckPredicate, 24, 197, 12, 0, // Skip to: 5329 +/* 2060 */ MCD_OPC_CheckField, 0, 4, 4, 190, 12, 0, // Skip to: 5329 +/* 2067 */ MCD_OPC_Decode, 215, 5, 170, 1, // Opcode: AE_LE64 +/* 2072 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2094 +/* 2077 */ MCD_OPC_CheckPredicate, 24, 175, 12, 0, // Skip to: 5329 +/* 2082 */ MCD_OPC_CheckField, 0, 4, 4, 168, 12, 0, // Skip to: 5329 +/* 2089 */ MCD_OPC_Decode, 218, 5, 170, 1, // Opcode: AE_LT64 +/* 2094 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 2116 +/* 2099 */ MCD_OPC_CheckPredicate, 24, 153, 12, 0, // Skip to: 5329 +/* 2104 */ MCD_OPC_CheckField, 0, 4, 4, 146, 12, 0, // Skip to: 5329 +/* 2111 */ MCD_OPC_Decode, 219, 5, 154, 1, // Opcode: AE_MAX32 +/* 2116 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2138 +/* 2121 */ MCD_OPC_CheckPredicate, 24, 131, 12, 0, // Skip to: 5329 +/* 2126 */ MCD_OPC_CheckField, 0, 4, 4, 124, 12, 0, // Skip to: 5329 +/* 2133 */ MCD_OPC_Decode, 223, 5, 154, 1, // Opcode: AE_MIN32 +/* 2138 */ MCD_OPC_FilterValue, 4, 47, 0, 0, // Skip to: 2190 +/* 2143 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 2146 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2168 +/* 2151 */ MCD_OPC_CheckPredicate, 24, 101, 12, 0, // Skip to: 5329 +/* 2156 */ MCD_OPC_CheckField, 0, 4, 4, 94, 12, 0, // Skip to: 5329 +/* 2163 */ MCD_OPC_Decode, 247, 4, 171, 1, // Opcode: AE_EQ32 +/* 2168 */ MCD_OPC_FilterValue, 1, 84, 12, 0, // Skip to: 5329 +/* 2173 */ MCD_OPC_CheckPredicate, 24, 79, 12, 0, // Skip to: 5329 +/* 2178 */ MCD_OPC_CheckField, 0, 4, 4, 72, 12, 0, // Skip to: 5329 +/* 2185 */ MCD_OPC_Decode, 217, 5, 171, 1, // Opcode: AE_LT32 +/* 2190 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2212 +/* 2195 */ MCD_OPC_CheckPredicate, 24, 57, 12, 0, // Skip to: 5329 +/* 2200 */ MCD_OPC_CheckField, 0, 4, 4, 50, 12, 0, // Skip to: 5329 +/* 2207 */ MCD_OPC_Decode, 196, 10, 172, 1, // Opcode: AE_SBI_IC +/* 2212 */ MCD_OPC_FilterValue, 7, 40, 12, 0, // Skip to: 5329 +/* 2217 */ MCD_OPC_CheckPredicate, 24, 35, 12, 0, // Skip to: 5329 +/* 2222 */ MCD_OPC_CheckField, 0, 4, 4, 28, 12, 0, // Skip to: 5329 +/* 2229 */ MCD_OPC_Decode, 197, 10, 172, 1, // Opcode: AE_SBI_IP +/* 2234 */ MCD_OPC_FilterValue, 6, 85, 2, 0, // Skip to: 2836 +/* 2239 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 2242 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2264 +/* 2247 */ MCD_OPC_CheckPredicate, 24, 5, 12, 0, // Skip to: 5329 +/* 2252 */ MCD_OPC_CheckField, 0, 4, 4, 254, 11, 0, // Skip to: 5329 +/* 2259 */ MCD_OPC_Decode, 245, 5, 173, 1, // Opcode: AE_MOVT64 +/* 2264 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 2316 +/* 2269 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 2272 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2294 +/* 2277 */ MCD_OPC_CheckPredicate, 24, 231, 11, 0, // Skip to: 5329 +/* 2282 */ MCD_OPC_CheckField, 0, 4, 4, 224, 11, 0, // Skip to: 5329 +/* 2289 */ MCD_OPC_Decode, 148, 10, 174, 1, // Opcode: AE_S32X2_IP +/* 2294 */ MCD_OPC_FilterValue, 1, 214, 11, 0, // Skip to: 5329 +/* 2299 */ MCD_OPC_CheckPredicate, 24, 209, 11, 0, // Skip to: 5329 +/* 2304 */ MCD_OPC_CheckField, 0, 4, 4, 202, 11, 0, // Skip to: 5329 +/* 2311 */ MCD_OPC_Decode, 140, 10, 174, 1, // Opcode: AE_S32X2F24_IP +/* 2316 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2338 +/* 2321 */ MCD_OPC_CheckPredicate, 24, 187, 11, 0, // Skip to: 5329 +/* 2326 */ MCD_OPC_CheckField, 0, 4, 4, 180, 11, 0, // Skip to: 5329 +/* 2333 */ MCD_OPC_Decode, 195, 10, 172, 1, // Opcode: AE_SBI +/* 2338 */ MCD_OPC_FilterValue, 7, 143, 1, 0, // Skip to: 2742 +/* 2343 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 2346 */ MCD_OPC_FilterValue, 234, 1, 16, 0, 0, // Skip to: 2368 +/* 2352 */ MCD_OPC_CheckPredicate, 24, 156, 11, 0, // Skip to: 5329 +/* 2357 */ MCD_OPC_CheckField, 0, 4, 4, 149, 11, 0, // Skip to: 5329 +/* 2364 */ MCD_OPC_Decode, 207, 14, 25, // Opcode: RUR_AE_OVERFLOW +/* 2368 */ MCD_OPC_FilterValue, 235, 1, 16, 0, 0, // Skip to: 2390 +/* 2374 */ MCD_OPC_CheckPredicate, 24, 134, 11, 0, // Skip to: 5329 +/* 2379 */ MCD_OPC_CheckField, 0, 4, 4, 127, 11, 0, // Skip to: 5329 +/* 2386 */ MCD_OPC_Decode, 163, 15, 25, // Opcode: WUR_AE_OVERFLOW +/* 2390 */ MCD_OPC_FilterValue, 236, 1, 16, 0, 0, // Skip to: 2412 +/* 2396 */ MCD_OPC_CheckPredicate, 24, 112, 11, 0, // Skip to: 5329 +/* 2401 */ MCD_OPC_CheckField, 0, 4, 4, 105, 11, 0, // Skip to: 5329 +/* 2408 */ MCD_OPC_Decode, 209, 14, 25, // Opcode: RUR_AE_SAR +/* 2412 */ MCD_OPC_FilterValue, 237, 1, 16, 0, 0, // Skip to: 2434 +/* 2418 */ MCD_OPC_CheckPredicate, 24, 90, 11, 0, // Skip to: 5329 +/* 2423 */ MCD_OPC_CheckField, 0, 4, 4, 83, 11, 0, // Skip to: 5329 +/* 2430 */ MCD_OPC_Decode, 165, 15, 25, // Opcode: WUR_AE_SAR +/* 2434 */ MCD_OPC_FilterValue, 238, 1, 16, 0, 0, // Skip to: 2456 +/* 2440 */ MCD_OPC_CheckPredicate, 24, 68, 11, 0, // Skip to: 5329 +/* 2445 */ MCD_OPC_CheckField, 0, 4, 4, 61, 11, 0, // Skip to: 5329 +/* 2452 */ MCD_OPC_Decode, 199, 14, 25, // Opcode: RUR_AE_BITPTR +/* 2456 */ MCD_OPC_FilterValue, 239, 1, 16, 0, 0, // Skip to: 2478 +/* 2462 */ MCD_OPC_CheckPredicate, 24, 46, 11, 0, // Skip to: 5329 +/* 2467 */ MCD_OPC_CheckField, 0, 4, 4, 39, 11, 0, // Skip to: 5329 +/* 2474 */ MCD_OPC_Decode, 155, 15, 25, // Opcode: WUR_AE_BITPTR +/* 2478 */ MCD_OPC_FilterValue, 240, 1, 16, 0, 0, // Skip to: 2500 +/* 2484 */ MCD_OPC_CheckPredicate, 24, 24, 11, 0, // Skip to: 5329 +/* 2489 */ MCD_OPC_CheckField, 0, 4, 4, 17, 11, 0, // Skip to: 5329 +/* 2496 */ MCD_OPC_Decode, 200, 14, 25, // Opcode: RUR_AE_BITSUSED +/* 2500 */ MCD_OPC_FilterValue, 241, 1, 16, 0, 0, // Skip to: 2522 +/* 2506 */ MCD_OPC_CheckPredicate, 24, 2, 11, 0, // Skip to: 5329 +/* 2511 */ MCD_OPC_CheckField, 0, 4, 4, 251, 10, 0, // Skip to: 5329 +/* 2518 */ MCD_OPC_Decode, 156, 15, 25, // Opcode: WUR_AE_BITSUSED +/* 2522 */ MCD_OPC_FilterValue, 242, 1, 16, 0, 0, // Skip to: 2544 +/* 2528 */ MCD_OPC_CheckPredicate, 24, 236, 10, 0, // Skip to: 5329 +/* 2533 */ MCD_OPC_CheckField, 0, 4, 4, 229, 10, 0, // Skip to: 5329 +/* 2540 */ MCD_OPC_Decode, 211, 14, 25, // Opcode: RUR_AE_TABLESIZE +/* 2544 */ MCD_OPC_FilterValue, 243, 1, 16, 0, 0, // Skip to: 2566 +/* 2550 */ MCD_OPC_CheckPredicate, 24, 214, 10, 0, // Skip to: 5329 +/* 2555 */ MCD_OPC_CheckField, 0, 4, 4, 207, 10, 0, // Skip to: 5329 +/* 2562 */ MCD_OPC_Decode, 167, 15, 25, // Opcode: WUR_AE_TABLESIZE +/* 2566 */ MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 2588 +/* 2572 */ MCD_OPC_CheckPredicate, 24, 192, 10, 0, // Skip to: 5329 +/* 2577 */ MCD_OPC_CheckField, 0, 4, 4, 185, 10, 0, // Skip to: 5329 +/* 2584 */ MCD_OPC_Decode, 205, 14, 25, // Opcode: RUR_AE_FIRST_TS +/* 2588 */ MCD_OPC_FilterValue, 245, 1, 16, 0, 0, // Skip to: 2610 +/* 2594 */ MCD_OPC_CheckPredicate, 24, 170, 10, 0, // Skip to: 5329 +/* 2599 */ MCD_OPC_CheckField, 0, 4, 4, 163, 10, 0, // Skip to: 5329 +/* 2606 */ MCD_OPC_Decode, 161, 15, 25, // Opcode: WUR_AE_FIRST_TS +/* 2610 */ MCD_OPC_FilterValue, 246, 1, 16, 0, 0, // Skip to: 2632 +/* 2616 */ MCD_OPC_CheckPredicate, 24, 148, 10, 0, // Skip to: 5329 +/* 2621 */ MCD_OPC_CheckField, 0, 4, 4, 141, 10, 0, // Skip to: 5329 +/* 2628 */ MCD_OPC_Decode, 206, 14, 25, // Opcode: RUR_AE_NEXTOFFSET +/* 2632 */ MCD_OPC_FilterValue, 247, 1, 16, 0, 0, // Skip to: 2654 +/* 2638 */ MCD_OPC_CheckPredicate, 24, 126, 10, 0, // Skip to: 5329 +/* 2643 */ MCD_OPC_CheckField, 0, 4, 4, 119, 10, 0, // Skip to: 5329 +/* 2650 */ MCD_OPC_Decode, 162, 15, 25, // Opcode: WUR_AE_NEXTOFFSET +/* 2654 */ MCD_OPC_FilterValue, 248, 1, 16, 0, 0, // Skip to: 2676 +/* 2660 */ MCD_OPC_CheckPredicate, 24, 104, 10, 0, // Skip to: 5329 +/* 2665 */ MCD_OPC_CheckField, 0, 4, 4, 97, 10, 0, // Skip to: 5329 +/* 2672 */ MCD_OPC_Decode, 210, 14, 25, // Opcode: RUR_AE_SEARCHDONE +/* 2676 */ MCD_OPC_FilterValue, 249, 1, 16, 0, 0, // Skip to: 2698 +/* 2682 */ MCD_OPC_CheckPredicate, 24, 82, 10, 0, // Skip to: 5329 +/* 2687 */ MCD_OPC_CheckField, 0, 4, 4, 75, 10, 0, // Skip to: 5329 +/* 2694 */ MCD_OPC_Decode, 166, 15, 25, // Opcode: WUR_AE_SEARCHDONE +/* 2698 */ MCD_OPC_FilterValue, 250, 1, 16, 0, 0, // Skip to: 2720 +/* 2704 */ MCD_OPC_CheckPredicate, 24, 60, 10, 0, // Skip to: 5329 +/* 2709 */ MCD_OPC_CheckField, 0, 4, 4, 53, 10, 0, // Skip to: 5329 +/* 2716 */ MCD_OPC_Decode, 203, 14, 25, // Opcode: RUR_AE_CWRAP +/* 2720 */ MCD_OPC_FilterValue, 251, 1, 43, 10, 0, // Skip to: 5329 +/* 2726 */ MCD_OPC_CheckPredicate, 24, 38, 10, 0, // Skip to: 5329 +/* 2731 */ MCD_OPC_CheckField, 0, 4, 4, 31, 10, 0, // Skip to: 5329 +/* 2738 */ MCD_OPC_Decode, 159, 15, 25, // Opcode: WUR_AE_CWRAP +/* 2742 */ MCD_OPC_FilterValue, 9, 22, 10, 0, // Skip to: 5329 +/* 2747 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 2750 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2771 +/* 2755 */ MCD_OPC_CheckPredicate, 24, 9, 10, 0, // Skip to: 5329 +/* 2760 */ MCD_OPC_CheckField, 0, 4, 4, 2, 10, 0, // Skip to: 5329 +/* 2767 */ MCD_OPC_Decode, 207, 5, 16, // Opcode: AE_LB +/* 2771 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2793 +/* 2776 */ MCD_OPC_CheckPredicate, 24, 244, 9, 0, // Skip to: 5329 +/* 2781 */ MCD_OPC_CheckField, 0, 4, 4, 237, 9, 0, // Skip to: 5329 +/* 2788 */ MCD_OPC_Decode, 208, 5, 175, 1, // Opcode: AE_LBI +/* 2793 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2814 +/* 2798 */ MCD_OPC_CheckPredicate, 24, 222, 9, 0, // Skip to: 5329 +/* 2803 */ MCD_OPC_CheckField, 0, 4, 4, 215, 9, 0, // Skip to: 5329 +/* 2810 */ MCD_OPC_Decode, 211, 5, 16, // Opcode: AE_LBS +/* 2814 */ MCD_OPC_FilterValue, 7, 206, 9, 0, // Skip to: 5329 +/* 2819 */ MCD_OPC_CheckPredicate, 24, 201, 9, 0, // Skip to: 5329 +/* 2824 */ MCD_OPC_CheckField, 0, 4, 4, 194, 9, 0, // Skip to: 5329 +/* 2831 */ MCD_OPC_Decode, 212, 5, 175, 1, // Opcode: AE_LBSI +/* 2836 */ MCD_OPC_FilterValue, 7, 176, 1, 0, // Skip to: 3273 +/* 2841 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 2844 */ MCD_OPC_FilterValue, 113, 24, 0, 0, // Skip to: 2873 +/* 2849 */ MCD_OPC_CheckPredicate, 24, 171, 9, 0, // Skip to: 5329 +/* 2854 */ MCD_OPC_CheckField, 6, 2, 3, 164, 9, 0, // Skip to: 5329 +/* 2861 */ MCD_OPC_CheckField, 0, 4, 4, 157, 9, 0, // Skip to: 5329 +/* 2868 */ MCD_OPC_Decode, 200, 5, 176, 1, // Opcode: AE_LA32X2POS_PC +/* 2873 */ MCD_OPC_FilterValue, 114, 24, 0, 0, // Skip to: 2902 +/* 2878 */ MCD_OPC_CheckPredicate, 24, 142, 9, 0, // Skip to: 5329 +/* 2883 */ MCD_OPC_CheckField, 6, 2, 3, 135, 9, 0, // Skip to: 5329 +/* 2890 */ MCD_OPC_CheckField, 0, 4, 4, 128, 9, 0, // Skip to: 5329 +/* 2897 */ MCD_OPC_Decode, 205, 5, 177, 1, // Opcode: AE_LA64_PP +/* 2902 */ MCD_OPC_FilterValue, 115, 24, 0, 0, // Skip to: 2931 +/* 2907 */ MCD_OPC_CheckPredicate, 24, 113, 9, 0, // Skip to: 5329 +/* 2912 */ MCD_OPC_CheckField, 6, 2, 3, 106, 9, 0, // Skip to: 5329 +/* 2919 */ MCD_OPC_CheckField, 0, 4, 4, 99, 9, 0, // Skip to: 5329 +/* 2926 */ MCD_OPC_Decode, 185, 10, 178, 1, // Opcode: AE_SA64POS_FP +/* 2931 */ MCD_OPC_FilterValue, 116, 17, 0, 0, // Skip to: 2953 +/* 2936 */ MCD_OPC_CheckPredicate, 24, 84, 9, 0, // Skip to: 5329 +/* 2941 */ MCD_OPC_CheckField, 0, 4, 4, 77, 9, 0, // Skip to: 5329 +/* 2948 */ MCD_OPC_Decode, 238, 4, 179, 1, // Opcode: AE_DB +/* 2953 */ MCD_OPC_FilterValue, 117, 17, 0, 0, // Skip to: 2975 +/* 2958 */ MCD_OPC_CheckPredicate, 24, 62, 9, 0, // Skip to: 5329 +/* 2963 */ MCD_OPC_CheckField, 0, 4, 4, 55, 9, 0, // Skip to: 5329 +/* 2970 */ MCD_OPC_Decode, 239, 4, 180, 1, // Opcode: AE_DBI +/* 2975 */ MCD_OPC_FilterValue, 118, 17, 0, 0, // Skip to: 2997 +/* 2980 */ MCD_OPC_CheckPredicate, 24, 40, 9, 0, // Skip to: 5329 +/* 2985 */ MCD_OPC_CheckField, 0, 4, 4, 33, 9, 0, // Skip to: 5329 +/* 2992 */ MCD_OPC_Decode, 242, 4, 179, 1, // Opcode: AE_DB_IC +/* 2997 */ MCD_OPC_FilterValue, 119, 17, 0, 0, // Skip to: 3019 +/* 3002 */ MCD_OPC_CheckPredicate, 24, 18, 9, 0, // Skip to: 5329 +/* 3007 */ MCD_OPC_CheckField, 0, 4, 4, 11, 9, 0, // Skip to: 5329 +/* 3014 */ MCD_OPC_Decode, 240, 4, 180, 1, // Opcode: AE_DBI_IC +/* 3019 */ MCD_OPC_FilterValue, 120, 17, 0, 0, // Skip to: 3041 +/* 3024 */ MCD_OPC_CheckPredicate, 24, 252, 8, 0, // Skip to: 5329 +/* 3029 */ MCD_OPC_CheckField, 0, 4, 4, 245, 8, 0, // Skip to: 5329 +/* 3036 */ MCD_OPC_Decode, 243, 4, 179, 1, // Opcode: AE_DB_IP +/* 3041 */ MCD_OPC_FilterValue, 121, 17, 0, 0, // Skip to: 3063 +/* 3046 */ MCD_OPC_CheckPredicate, 24, 230, 8, 0, // Skip to: 5329 +/* 3051 */ MCD_OPC_CheckField, 0, 4, 4, 223, 8, 0, // Skip to: 5329 +/* 3058 */ MCD_OPC_Decode, 241, 4, 180, 1, // Opcode: AE_DBI_IP +/* 3063 */ MCD_OPC_FilterValue, 122, 17, 0, 0, // Skip to: 3085 +/* 3068 */ MCD_OPC_CheckPredicate, 24, 208, 8, 0, // Skip to: 5329 +/* 3073 */ MCD_OPC_CheckField, 0, 4, 4, 201, 8, 0, // Skip to: 5329 +/* 3080 */ MCD_OPC_Decode, 191, 10, 179, 1, // Opcode: AE_SB +/* 3085 */ MCD_OPC_FilterValue, 123, 17, 0, 0, // Skip to: 3107 +/* 3090 */ MCD_OPC_CheckPredicate, 24, 186, 8, 0, // Skip to: 5329 +/* 3095 */ MCD_OPC_CheckField, 0, 4, 4, 179, 8, 0, // Skip to: 5329 +/* 3102 */ MCD_OPC_Decode, 198, 10, 179, 1, // Opcode: AE_SB_IC +/* 3107 */ MCD_OPC_FilterValue, 124, 17, 0, 0, // Skip to: 3129 +/* 3112 */ MCD_OPC_CheckPredicate, 24, 164, 8, 0, // Skip to: 5329 +/* 3117 */ MCD_OPC_CheckField, 0, 4, 4, 157, 8, 0, // Skip to: 5329 +/* 3124 */ MCD_OPC_Decode, 199, 10, 179, 1, // Opcode: AE_SB_IP +/* 3129 */ MCD_OPC_FilterValue, 126, 147, 8, 0, // Skip to: 5329 +/* 3134 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 3137 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 3152 +/* 3142 */ MCD_OPC_CheckPredicate, 24, 134, 8, 0, // Skip to: 5329 +/* 3147 */ MCD_OPC_Decode, 146, 11, 181, 1, // Opcode: AE_VLES16C +/* 3152 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 3167 +/* 3157 */ MCD_OPC_CheckPredicate, 24, 119, 8, 0, // Skip to: 5329 +/* 3162 */ MCD_OPC_Decode, 192, 10, 181, 1, // Opcode: AE_SBF +/* 3167 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 3182 +/* 3172 */ MCD_OPC_CheckPredicate, 24, 104, 8, 0, // Skip to: 5329 +/* 3177 */ MCD_OPC_Decode, 147, 11, 181, 1, // Opcode: AE_VLES16C_IC +/* 3182 */ MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 3197 +/* 3187 */ MCD_OPC_CheckPredicate, 24, 89, 8, 0, // Skip to: 5329 +/* 3192 */ MCD_OPC_Decode, 193, 10, 181, 1, // Opcode: AE_SBF_IC +/* 3197 */ MCD_OPC_FilterValue, 68, 10, 0, 0, // Skip to: 3212 +/* 3202 */ MCD_OPC_CheckPredicate, 24, 74, 8, 0, // Skip to: 5329 +/* 3207 */ MCD_OPC_Decode, 148, 11, 181, 1, // Opcode: AE_VLES16C_IP +/* 3212 */ MCD_OPC_FilterValue, 84, 10, 0, 0, // Skip to: 3227 +/* 3217 */ MCD_OPC_CheckPredicate, 24, 59, 8, 0, // Skip to: 5329 +/* 3222 */ MCD_OPC_Decode, 194, 10, 181, 1, // Opcode: AE_SBF_IP +/* 3227 */ MCD_OPC_FilterValue, 100, 10, 0, 0, // Skip to: 3242 +/* 3232 */ MCD_OPC_CheckPredicate, 24, 44, 8, 0, // Skip to: 5329 +/* 3237 */ MCD_OPC_Decode, 138, 11, 181, 1, // Opcode: AE_VLDL16C +/* 3242 */ MCD_OPC_FilterValue, 116, 10, 0, 0, // Skip to: 3257 +/* 3247 */ MCD_OPC_CheckPredicate, 24, 29, 8, 0, // Skip to: 5329 +/* 3252 */ MCD_OPC_Decode, 139, 11, 181, 1, // Opcode: AE_VLDL16C_IC +/* 3257 */ MCD_OPC_FilterValue, 132, 1, 18, 8, 0, // Skip to: 5329 +/* 3263 */ MCD_OPC_CheckPredicate, 24, 13, 8, 0, // Skip to: 5329 +/* 3268 */ MCD_OPC_Decode, 140, 11, 181, 1, // Opcode: AE_VLDL16C_IP +/* 3273 */ MCD_OPC_FilterValue, 8, 171, 0, 0, // Skip to: 3449 +/* 3278 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 3281 */ MCD_OPC_FilterValue, 0, 97, 0, 0, // Skip to: 3383 +/* 3286 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 3289 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3318 +/* 3294 */ MCD_OPC_CheckPredicate, 24, 238, 7, 0, // Skip to: 5329 +/* 3299 */ MCD_OPC_CheckField, 7, 1, 1, 231, 7, 0, // Skip to: 5329 +/* 3306 */ MCD_OPC_CheckField, 0, 4, 4, 224, 7, 0, // Skip to: 5329 +/* 3313 */ MCD_OPC_Decode, 235, 9, 174, 1, // Opcode: AE_S16X4_IP +/* 3318 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3340 +/* 3323 */ MCD_OPC_CheckPredicate, 24, 209, 7, 0, // Skip to: 5329 +/* 3328 */ MCD_OPC_CheckField, 0, 4, 4, 202, 7, 0, // Skip to: 5329 +/* 3335 */ MCD_OPC_Decode, 235, 10, 149, 1, // Opcode: AE_SRAA64 +/* 3340 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3362 +/* 3345 */ MCD_OPC_CheckPredicate, 24, 187, 7, 0, // Skip to: 5329 +/* 3350 */ MCD_OPC_CheckField, 0, 4, 4, 180, 7, 0, // Skip to: 5329 +/* 3357 */ MCD_OPC_Decode, 234, 10, 149, 1, // Opcode: AE_SRAA32S +/* 3362 */ MCD_OPC_FilterValue, 3, 170, 7, 0, // Skip to: 5329 +/* 3367 */ MCD_OPC_CheckPredicate, 24, 165, 7, 0, // Skip to: 5329 +/* 3372 */ MCD_OPC_CheckField, 0, 4, 4, 158, 7, 0, // Skip to: 5329 +/* 3379 */ MCD_OPC_Decode, 209, 5, 1, // Opcode: AE_LBK +/* 3383 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3405 +/* 3388 */ MCD_OPC_CheckPredicate, 24, 144, 7, 0, // Skip to: 5329 +/* 3393 */ MCD_OPC_CheckField, 0, 4, 4, 137, 7, 0, // Skip to: 5329 +/* 3400 */ MCD_OPC_Decode, 220, 10, 182, 1, // Opcode: AE_SLAISQ56S +/* 3405 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3427 +/* 3410 */ MCD_OPC_CheckPredicate, 24, 122, 7, 0, // Skip to: 5329 +/* 3415 */ MCD_OPC_CheckField, 0, 4, 4, 115, 7, 0, // Skip to: 5329 +/* 3422 */ MCD_OPC_Decode, 218, 10, 182, 1, // Opcode: AE_SLAI64 +/* 3427 */ MCD_OPC_FilterValue, 3, 105, 7, 0, // Skip to: 5329 +/* 3432 */ MCD_OPC_CheckPredicate, 24, 100, 7, 0, // Skip to: 5329 +/* 3437 */ MCD_OPC_CheckField, 0, 4, 4, 93, 7, 0, // Skip to: 5329 +/* 3444 */ MCD_OPC_Decode, 241, 10, 182, 1, // Opcode: AE_SRAI64 +/* 3449 */ MCD_OPC_FilterValue, 9, 193, 0, 0, // Skip to: 3647 +/* 3454 */ MCD_OPC_ExtractField, 17, 3, // Inst{19-17} ... +/* 3457 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3493 +/* 3462 */ MCD_OPC_CheckPredicate, 24, 70, 7, 0, // Skip to: 5329 +/* 3467 */ MCD_OPC_CheckField, 16, 1, 0, 63, 7, 0, // Skip to: 5329 +/* 3474 */ MCD_OPC_CheckField, 7, 1, 1, 56, 7, 0, // Skip to: 5329 +/* 3481 */ MCD_OPC_CheckField, 0, 4, 4, 49, 7, 0, // Skip to: 5329 +/* 3488 */ MCD_OPC_Decode, 132, 5, 163, 1, // Opcode: AE_L16X4_IP +/* 3493 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3515 +/* 3498 */ MCD_OPC_CheckPredicate, 24, 34, 7, 0, // Skip to: 5329 +/* 3503 */ MCD_OPC_CheckField, 0, 4, 4, 27, 7, 0, // Skip to: 5329 +/* 3510 */ MCD_OPC_Decode, 248, 10, 183, 1, // Opcode: AE_SRLI32 +/* 3515 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3537 +/* 3520 */ MCD_OPC_CheckPredicate, 24, 12, 7, 0, // Skip to: 5329 +/* 3525 */ MCD_OPC_CheckField, 0, 4, 4, 5, 7, 0, // Skip to: 5329 +/* 3532 */ MCD_OPC_Decode, 214, 10, 183, 1, // Opcode: AE_SLAI24 +/* 3537 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3559 +/* 3542 */ MCD_OPC_CheckPredicate, 24, 246, 6, 0, // Skip to: 5329 +/* 3547 */ MCD_OPC_CheckField, 0, 4, 4, 239, 6, 0, // Skip to: 5329 +/* 3554 */ MCD_OPC_Decode, 216, 10, 183, 1, // Opcode: AE_SLAI32 +/* 3559 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3581 +/* 3564 */ MCD_OPC_CheckPredicate, 24, 224, 6, 0, // Skip to: 5329 +/* 3569 */ MCD_OPC_CheckField, 0, 4, 4, 217, 6, 0, // Skip to: 5329 +/* 3576 */ MCD_OPC_Decode, 215, 10, 183, 1, // Opcode: AE_SLAI24S +/* 3581 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3603 +/* 3586 */ MCD_OPC_CheckPredicate, 24, 202, 6, 0, // Skip to: 5329 +/* 3591 */ MCD_OPC_CheckField, 0, 4, 4, 195, 6, 0, // Skip to: 5329 +/* 3598 */ MCD_OPC_Decode, 217, 10, 183, 1, // Opcode: AE_SLAI32S +/* 3603 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3625 +/* 3608 */ MCD_OPC_CheckPredicate, 24, 180, 6, 0, // Skip to: 5329 +/* 3613 */ MCD_OPC_CheckField, 0, 4, 4, 173, 6, 0, // Skip to: 5329 +/* 3620 */ MCD_OPC_Decode, 238, 10, 183, 1, // Opcode: AE_SRAI24 +/* 3625 */ MCD_OPC_FilterValue, 7, 163, 6, 0, // Skip to: 5329 +/* 3630 */ MCD_OPC_CheckPredicate, 24, 158, 6, 0, // Skip to: 5329 +/* 3635 */ MCD_OPC_CheckField, 0, 4, 4, 151, 6, 0, // Skip to: 5329 +/* 3642 */ MCD_OPC_Decode, 239, 10, 183, 1, // Opcode: AE_SRAI32 +/* 3647 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3669 +/* 3652 */ MCD_OPC_CheckPredicate, 24, 136, 6, 0, // Skip to: 5329 +/* 3657 */ MCD_OPC_CheckField, 0, 4, 4, 129, 6, 0, // Skip to: 5329 +/* 3664 */ MCD_OPC_Decode, 200, 10, 184, 1, // Opcode: AE_SEL16I +/* 3669 */ MCD_OPC_FilterValue, 11, 99, 1, 0, // Skip to: 4029 +/* 3674 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 3677 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3699 +/* 3682 */ MCD_OPC_CheckPredicate, 24, 106, 6, 0, // Skip to: 5329 +/* 3687 */ MCD_OPC_CheckField, 0, 4, 4, 99, 6, 0, // Skip to: 5329 +/* 3694 */ MCD_OPC_Decode, 138, 5, 146, 1, // Opcode: AE_L16_I +/* 3699 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3721 +/* 3704 */ MCD_OPC_CheckPredicate, 24, 84, 6, 0, // Skip to: 5329 +/* 3709 */ MCD_OPC_CheckField, 0, 4, 4, 77, 6, 0, // Skip to: 5329 +/* 3716 */ MCD_OPC_Decode, 249, 4, 146, 1, // Opcode: AE_L16M_I +/* 3721 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3743 +/* 3726 */ MCD_OPC_CheckPredicate, 24, 62, 6, 0, // Skip to: 5329 +/* 3731 */ MCD_OPC_CheckField, 0, 4, 4, 55, 6, 0, // Skip to: 5329 +/* 3738 */ MCD_OPC_Decode, 250, 4, 169, 1, // Opcode: AE_L16M_IU +/* 3743 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3765 +/* 3748 */ MCD_OPC_CheckPredicate, 24, 40, 6, 0, // Skip to: 5329 +/* 3753 */ MCD_OPC_CheckField, 0, 4, 4, 33, 6, 0, // Skip to: 5329 +/* 3760 */ MCD_OPC_Decode, 253, 4, 185, 1, // Opcode: AE_L16M_XU +/* 3765 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3787 +/* 3770 */ MCD_OPC_CheckPredicate, 24, 18, 6, 0, // Skip to: 5329 +/* 3775 */ MCD_OPC_CheckField, 0, 4, 4, 11, 6, 0, // Skip to: 5329 +/* 3782 */ MCD_OPC_Decode, 139, 5, 169, 1, // Opcode: AE_L16_IP +/* 3787 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3809 +/* 3792 */ MCD_OPC_CheckPredicate, 24, 252, 5, 0, // Skip to: 5329 +/* 3797 */ MCD_OPC_CheckField, 0, 4, 4, 245, 5, 0, // Skip to: 5329 +/* 3804 */ MCD_OPC_Decode, 146, 5, 185, 1, // Opcode: AE_L32F24_XC +/* 3809 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3831 +/* 3814 */ MCD_OPC_CheckPredicate, 24, 230, 5, 0, // Skip to: 5329 +/* 3819 */ MCD_OPC_CheckField, 0, 4, 4, 223, 5, 0, // Skip to: 5329 +/* 3826 */ MCD_OPC_Decode, 143, 5, 146, 1, // Opcode: AE_L32F24_I +/* 3831 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3853 +/* 3836 */ MCD_OPC_CheckPredicate, 24, 208, 5, 0, // Skip to: 5329 +/* 3841 */ MCD_OPC_CheckField, 0, 4, 4, 201, 5, 0, // Skip to: 5329 +/* 3848 */ MCD_OPC_Decode, 144, 5, 169, 1, // Opcode: AE_L32F24_IP +/* 3853 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3875 +/* 3858 */ MCD_OPC_CheckPredicate, 24, 186, 5, 0, // Skip to: 5329 +/* 3863 */ MCD_OPC_CheckField, 0, 4, 4, 179, 5, 0, // Skip to: 5329 +/* 3870 */ MCD_OPC_Decode, 254, 4, 146, 1, // Opcode: AE_L16X2M_I +/* 3875 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 3897 +/* 3880 */ MCD_OPC_CheckPredicate, 24, 164, 5, 0, // Skip to: 5329 +/* 3885 */ MCD_OPC_CheckField, 0, 4, 4, 157, 5, 0, // Skip to: 5329 +/* 3892 */ MCD_OPC_Decode, 255, 4, 169, 1, // Opcode: AE_L16X2M_IU +/* 3897 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3919 +/* 3902 */ MCD_OPC_CheckPredicate, 24, 142, 5, 0, // Skip to: 5329 +/* 3907 */ MCD_OPC_CheckField, 0, 4, 4, 135, 5, 0, // Skip to: 5329 +/* 3914 */ MCD_OPC_Decode, 128, 5, 153, 1, // Opcode: AE_L16X2M_X +/* 3919 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3941 +/* 3924 */ MCD_OPC_CheckPredicate, 24, 120, 5, 0, // Skip to: 5329 +/* 3929 */ MCD_OPC_CheckField, 0, 4, 4, 113, 5, 0, // Skip to: 5329 +/* 3936 */ MCD_OPC_Decode, 130, 5, 185, 1, // Opcode: AE_L16X2M_XU +/* 3941 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3963 +/* 3946 */ MCD_OPC_CheckPredicate, 24, 98, 5, 0, // Skip to: 5329 +/* 3951 */ MCD_OPC_CheckField, 0, 4, 4, 91, 5, 0, // Skip to: 5329 +/* 3958 */ MCD_OPC_Decode, 170, 5, 185, 1, // Opcode: AE_L32_XC +/* 3963 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3985 +/* 3968 */ MCD_OPC_CheckPredicate, 24, 76, 5, 0, // Skip to: 5329 +/* 3973 */ MCD_OPC_CheckField, 0, 4, 4, 69, 5, 0, // Skip to: 5329 +/* 3980 */ MCD_OPC_Decode, 167, 5, 146, 1, // Opcode: AE_L32_I +/* 3985 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4007 +/* 3990 */ MCD_OPC_CheckPredicate, 24, 54, 5, 0, // Skip to: 5329 +/* 3995 */ MCD_OPC_CheckField, 0, 4, 4, 47, 5, 0, // Skip to: 5329 +/* 4002 */ MCD_OPC_Decode, 168, 5, 169, 1, // Opcode: AE_L32_IP +/* 4007 */ MCD_OPC_FilterValue, 15, 37, 5, 0, // Skip to: 5329 +/* 4012 */ MCD_OPC_CheckPredicate, 24, 32, 5, 0, // Skip to: 5329 +/* 4017 */ MCD_OPC_CheckField, 0, 4, 4, 25, 5, 0, // Skip to: 5329 +/* 4024 */ MCD_OPC_Decode, 169, 5, 153, 1, // Opcode: AE_L32_X +/* 4029 */ MCD_OPC_FilterValue, 12, 99, 1, 0, // Skip to: 4389 +/* 4034 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 4037 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4059 +/* 4042 */ MCD_OPC_CheckPredicate, 24, 2, 5, 0, // Skip to: 5329 +/* 4047 */ MCD_OPC_CheckField, 0, 4, 4, 251, 4, 0, // Skip to: 5329 +/* 4054 */ MCD_OPC_Decode, 165, 5, 185, 1, // Opcode: AE_L32X2_XC +/* 4059 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4081 +/* 4064 */ MCD_OPC_CheckPredicate, 24, 236, 4, 0, // Skip to: 5329 +/* 4069 */ MCD_OPC_CheckField, 0, 4, 4, 229, 4, 0, // Skip to: 5329 +/* 4076 */ MCD_OPC_Decode, 160, 5, 146, 1, // Opcode: AE_L32X2_I +/* 4081 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4103 +/* 4086 */ MCD_OPC_CheckPredicate, 24, 214, 4, 0, // Skip to: 5329 +/* 4091 */ MCD_OPC_CheckField, 0, 4, 4, 207, 4, 0, // Skip to: 5329 +/* 4098 */ MCD_OPC_Decode, 164, 5, 153, 1, // Opcode: AE_L32X2_X +/* 4103 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4125 +/* 4108 */ MCD_OPC_CheckPredicate, 24, 192, 4, 0, // Skip to: 5329 +/* 4113 */ MCD_OPC_CheckField, 0, 4, 4, 185, 4, 0, // Skip to: 5329 +/* 4120 */ MCD_OPC_Decode, 166, 5, 185, 1, // Opcode: AE_L32X2_XP +/* 4125 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4147 +/* 4130 */ MCD_OPC_CheckPredicate, 24, 170, 4, 0, // Skip to: 5329 +/* 4135 */ MCD_OPC_CheckField, 0, 4, 4, 163, 4, 0, // Skip to: 5329 +/* 4142 */ MCD_OPC_Decode, 158, 5, 185, 1, // Opcode: AE_L32X2F24_XC +/* 4147 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4169 +/* 4152 */ MCD_OPC_CheckPredicate, 24, 148, 4, 0, // Skip to: 5329 +/* 4157 */ MCD_OPC_CheckField, 0, 4, 4, 141, 4, 0, // Skip to: 5329 +/* 4164 */ MCD_OPC_Decode, 153, 5, 146, 1, // Opcode: AE_L32X2F24_I +/* 4169 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4191 +/* 4174 */ MCD_OPC_CheckPredicate, 24, 126, 4, 0, // Skip to: 5329 +/* 4179 */ MCD_OPC_CheckField, 0, 4, 4, 119, 4, 0, // Skip to: 5329 +/* 4186 */ MCD_OPC_Decode, 157, 5, 153, 1, // Opcode: AE_L32X2F24_X +/* 4191 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4213 +/* 4196 */ MCD_OPC_CheckPredicate, 24, 104, 4, 0, // Skip to: 5329 +/* 4201 */ MCD_OPC_CheckField, 0, 4, 4, 97, 4, 0, // Skip to: 5329 +/* 4208 */ MCD_OPC_Decode, 159, 5, 185, 1, // Opcode: AE_L32X2F24_XP +/* 4213 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4235 +/* 4218 */ MCD_OPC_CheckPredicate, 24, 82, 4, 0, // Skip to: 5329 +/* 4223 */ MCD_OPC_CheckField, 0, 4, 4, 75, 4, 0, // Skip to: 5329 +/* 4230 */ MCD_OPC_Decode, 148, 5, 146, 1, // Opcode: AE_L32M_I +/* 4235 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4257 +/* 4240 */ MCD_OPC_CheckPredicate, 24, 60, 4, 0, // Skip to: 5329 +/* 4245 */ MCD_OPC_CheckField, 0, 4, 4, 53, 4, 0, // Skip to: 5329 +/* 4252 */ MCD_OPC_Decode, 149, 5, 169, 1, // Opcode: AE_L32M_IU +/* 4257 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4279 +/* 4262 */ MCD_OPC_CheckPredicate, 24, 38, 4, 0, // Skip to: 5329 +/* 4267 */ MCD_OPC_CheckField, 0, 4, 4, 31, 4, 0, // Skip to: 5329 +/* 4274 */ MCD_OPC_Decode, 150, 5, 153, 1, // Opcode: AE_L32M_X +/* 4279 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4301 +/* 4284 */ MCD_OPC_CheckPredicate, 24, 16, 4, 0, // Skip to: 5329 +/* 4289 */ MCD_OPC_CheckField, 0, 4, 4, 9, 4, 0, // Skip to: 5329 +/* 4296 */ MCD_OPC_Decode, 152, 5, 185, 1, // Opcode: AE_L32M_XU +/* 4301 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4323 +/* 4306 */ MCD_OPC_CheckPredicate, 24, 250, 3, 0, // Skip to: 5329 +/* 4311 */ MCD_OPC_CheckField, 0, 4, 4, 243, 3, 0, // Skip to: 5329 +/* 4318 */ MCD_OPC_Decode, 131, 5, 146, 1, // Opcode: AE_L16X4_I +/* 4323 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4345 +/* 4328 */ MCD_OPC_CheckPredicate, 24, 228, 3, 0, // Skip to: 5329 +/* 4333 */ MCD_OPC_CheckField, 0, 4, 4, 221, 3, 0, // Skip to: 5329 +/* 4340 */ MCD_OPC_Decode, 137, 5, 185, 1, // Opcode: AE_L16X4_XP +/* 4345 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4367 +/* 4350 */ MCD_OPC_CheckPredicate, 24, 206, 3, 0, // Skip to: 5329 +/* 4355 */ MCD_OPC_CheckField, 0, 4, 4, 199, 3, 0, // Skip to: 5329 +/* 4362 */ MCD_OPC_Decode, 210, 5, 186, 1, // Opcode: AE_LBKI +/* 4367 */ MCD_OPC_FilterValue, 15, 189, 3, 0, // Skip to: 5329 +/* 4372 */ MCD_OPC_CheckPredicate, 24, 184, 3, 0, // Skip to: 5329 +/* 4377 */ MCD_OPC_CheckField, 0, 4, 4, 177, 3, 0, // Skip to: 5329 +/* 4384 */ MCD_OPC_Decode, 172, 5, 146, 1, // Opcode: AE_L64_I +/* 4389 */ MCD_OPC_FilterValue, 13, 99, 1, 0, // Skip to: 4749 +/* 4394 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 4397 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4419 +/* 4402 */ MCD_OPC_CheckPredicate, 24, 154, 3, 0, // Skip to: 5329 +/* 4407 */ MCD_OPC_CheckField, 0, 4, 4, 147, 3, 0, // Skip to: 5329 +/* 4414 */ MCD_OPC_Decode, 145, 11, 187, 1, // Opcode: AE_VLEL32T +/* 4419 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4441 +/* 4424 */ MCD_OPC_CheckPredicate, 24, 132, 3, 0, // Skip to: 5329 +/* 4429 */ MCD_OPC_CheckField, 0, 4, 4, 125, 3, 0, // Skip to: 5329 +/* 4436 */ MCD_OPC_Decode, 144, 11, 187, 1, // Opcode: AE_VLEL16T +/* 4441 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4463 +/* 4446 */ MCD_OPC_CheckPredicate, 24, 110, 3, 0, // Skip to: 5329 +/* 4451 */ MCD_OPC_CheckField, 0, 4, 4, 103, 3, 0, // Skip to: 5329 +/* 4458 */ MCD_OPC_Decode, 241, 9, 146, 1, // Opcode: AE_S16_0_I +/* 4463 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4485 +/* 4468 */ MCD_OPC_CheckPredicate, 24, 88, 3, 0, // Skip to: 5329 +/* 4473 */ MCD_OPC_CheckField, 0, 4, 4, 81, 3, 0, // Skip to: 5329 +/* 4480 */ MCD_OPC_Decode, 242, 9, 147, 1, // Opcode: AE_S16_0_IP +/* 4485 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4507 +/* 4490 */ MCD_OPC_CheckPredicate, 24, 66, 3, 0, // Skip to: 5329 +/* 4495 */ MCD_OPC_CheckField, 0, 4, 4, 59, 3, 0, // Skip to: 5329 +/* 4502 */ MCD_OPC_Decode, 245, 9, 148, 1, // Opcode: AE_S16_0_XP +/* 4507 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4529 +/* 4512 */ MCD_OPC_CheckPredicate, 24, 44, 3, 0, // Skip to: 5329 +/* 4517 */ MCD_OPC_CheckField, 0, 4, 4, 37, 3, 0, // Skip to: 5329 +/* 4524 */ MCD_OPC_Decode, 224, 9, 146, 1, // Opcode: AE_S16M_L_I +/* 4529 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4551 +/* 4534 */ MCD_OPC_CheckPredicate, 24, 22, 3, 0, // Skip to: 5329 +/* 4539 */ MCD_OPC_CheckField, 0, 4, 4, 15, 3, 0, // Skip to: 5329 +/* 4546 */ MCD_OPC_Decode, 225, 9, 147, 1, // Opcode: AE_S16M_L_IU +/* 4551 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4573 +/* 4556 */ MCD_OPC_CheckPredicate, 24, 0, 3, 0, // Skip to: 5329 +/* 4561 */ MCD_OPC_CheckField, 0, 4, 4, 249, 2, 0, // Skip to: 5329 +/* 4568 */ MCD_OPC_Decode, 226, 9, 153, 1, // Opcode: AE_S16M_L_X +/* 4573 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4595 +/* 4578 */ MCD_OPC_CheckPredicate, 24, 234, 2, 0, // Skip to: 5329 +/* 4583 */ MCD_OPC_CheckField, 0, 4, 4, 227, 2, 0, // Skip to: 5329 +/* 4590 */ MCD_OPC_Decode, 229, 9, 146, 1, // Opcode: AE_S16X2M_I +/* 4595 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4617 +/* 4600 */ MCD_OPC_CheckPredicate, 24, 212, 2, 0, // Skip to: 5329 +/* 4605 */ MCD_OPC_CheckField, 0, 4, 4, 205, 2, 0, // Skip to: 5329 +/* 4612 */ MCD_OPC_Decode, 230, 9, 147, 1, // Opcode: AE_S16X2M_IU +/* 4617 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4639 +/* 4622 */ MCD_OPC_CheckPredicate, 24, 190, 2, 0, // Skip to: 5329 +/* 4627 */ MCD_OPC_CheckField, 0, 4, 4, 183, 2, 0, // Skip to: 5329 +/* 4634 */ MCD_OPC_Decode, 231, 9, 153, 1, // Opcode: AE_S16X2M_X +/* 4639 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4661 +/* 4644 */ MCD_OPC_CheckPredicate, 24, 168, 2, 0, // Skip to: 5329 +/* 4649 */ MCD_OPC_CheckField, 0, 4, 4, 161, 2, 0, // Skip to: 5329 +/* 4656 */ MCD_OPC_Decode, 233, 9, 148, 1, // Opcode: AE_S16X2M_XU +/* 4661 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4683 +/* 4666 */ MCD_OPC_CheckPredicate, 24, 146, 2, 0, // Skip to: 5329 +/* 4671 */ MCD_OPC_CheckField, 0, 4, 4, 139, 2, 0, // Skip to: 5329 +/* 4678 */ MCD_OPC_Decode, 234, 9, 146, 1, // Opcode: AE_S16X4_I +/* 4683 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4705 +/* 4688 */ MCD_OPC_CheckPredicate, 24, 124, 2, 0, // Skip to: 5329 +/* 4693 */ MCD_OPC_CheckField, 0, 4, 4, 117, 2, 0, // Skip to: 5329 +/* 4700 */ MCD_OPC_Decode, 250, 9, 148, 1, // Opcode: AE_S24RA64S_XP +/* 4705 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4727 +/* 4710 */ MCD_OPC_CheckPredicate, 24, 102, 2, 0, // Skip to: 5329 +/* 4715 */ MCD_OPC_CheckField, 0, 4, 4, 95, 2, 0, // Skip to: 5329 +/* 4722 */ MCD_OPC_Decode, 252, 9, 146, 1, // Opcode: AE_S32F24_L_I +/* 4727 */ MCD_OPC_FilterValue, 15, 85, 2, 0, // Skip to: 5329 +/* 4732 */ MCD_OPC_CheckPredicate, 24, 80, 2, 0, // Skip to: 5329 +/* 4737 */ MCD_OPC_CheckField, 0, 4, 4, 73, 2, 0, // Skip to: 5329 +/* 4744 */ MCD_OPC_Decode, 253, 9, 147, 1, // Opcode: AE_S32F24_L_IP +/* 4749 */ MCD_OPC_FilterValue, 14, 198, 1, 0, // Skip to: 5208 +/* 4754 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 4757 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4779 +/* 4762 */ MCD_OPC_CheckPredicate, 24, 50, 2, 0, // Skip to: 5329 +/* 4767 */ MCD_OPC_CheckField, 0, 4, 4, 43, 2, 0, // Skip to: 5329 +/* 4774 */ MCD_OPC_Decode, 154, 10, 146, 1, // Opcode: AE_S32_L_I +/* 4779 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4801 +/* 4784 */ MCD_OPC_CheckPredicate, 24, 28, 2, 0, // Skip to: 5329 +/* 4789 */ MCD_OPC_CheckField, 0, 4, 4, 21, 2, 0, // Skip to: 5329 +/* 4796 */ MCD_OPC_Decode, 155, 10, 147, 1, // Opcode: AE_S32_L_IP +/* 4801 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4823 +/* 4806 */ MCD_OPC_CheckPredicate, 24, 6, 2, 0, // Skip to: 5329 +/* 4811 */ MCD_OPC_CheckField, 0, 4, 4, 255, 1, 0, // Skip to: 5329 +/* 4818 */ MCD_OPC_Decode, 156, 10, 153, 1, // Opcode: AE_S32_L_X +/* 4823 */ MCD_OPC_FilterValue, 3, 116, 0, 0, // Skip to: 4944 +/* 4828 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4831 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 4929 +/* 4836 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... +/* 4839 */ MCD_OPC_FilterValue, 240, 1, 9, 0, 0, // Skip to: 4854 +/* 4845 */ MCD_OPC_CheckPredicate, 24, 223, 1, 0, // Skip to: 5329 +/* 4850 */ MCD_OPC_Decode, 208, 14, 80, // Opcode: RUR_AE_OVF_SAR +/* 4854 */ MCD_OPC_FilterValue, 241, 1, 9, 0, 0, // Skip to: 4869 +/* 4860 */ MCD_OPC_CheckPredicate, 24, 208, 1, 0, // Skip to: 5329 +/* 4865 */ MCD_OPC_Decode, 198, 14, 80, // Opcode: RUR_AE_BITHEAD +/* 4869 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 4884 +/* 4875 */ MCD_OPC_CheckPredicate, 24, 193, 1, 0, // Skip to: 5329 +/* 4880 */ MCD_OPC_Decode, 212, 14, 80, // Opcode: RUR_AE_TS_FTS_BU_BP +/* 4884 */ MCD_OPC_FilterValue, 243, 1, 9, 0, 0, // Skip to: 4899 +/* 4890 */ MCD_OPC_CheckPredicate, 24, 178, 1, 0, // Skip to: 5329 +/* 4895 */ MCD_OPC_Decode, 204, 14, 80, // Opcode: RUR_AE_CW_SD_NO +/* 4899 */ MCD_OPC_FilterValue, 246, 1, 9, 0, 0, // Skip to: 4914 +/* 4905 */ MCD_OPC_CheckPredicate, 24, 163, 1, 0, // Skip to: 5329 +/* 4910 */ MCD_OPC_Decode, 201, 14, 80, // Opcode: RUR_AE_CBEGIN0 +/* 4914 */ MCD_OPC_FilterValue, 247, 1, 153, 1, 0, // Skip to: 5329 +/* 4920 */ MCD_OPC_CheckPredicate, 24, 148, 1, 0, // Skip to: 5329 +/* 4925 */ MCD_OPC_Decode, 202, 14, 80, // Opcode: RUR_AE_CEND0 +/* 4929 */ MCD_OPC_FilterValue, 4, 139, 1, 0, // Skip to: 5329 +/* 4934 */ MCD_OPC_CheckPredicate, 24, 134, 1, 0, // Skip to: 5329 +/* 4939 */ MCD_OPC_Decode, 158, 10, 148, 1, // Opcode: AE_S32_L_XP +/* 4944 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4966 +/* 4949 */ MCD_OPC_CheckPredicate, 24, 119, 1, 0, // Skip to: 5329 +/* 4954 */ MCD_OPC_CheckField, 0, 4, 4, 112, 1, 0, // Skip to: 5329 +/* 4961 */ MCD_OPC_Decode, 129, 10, 146, 1, // Opcode: AE_S32M_I +/* 4966 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4988 +/* 4971 */ MCD_OPC_CheckPredicate, 24, 97, 1, 0, // Skip to: 5329 +/* 4976 */ MCD_OPC_CheckField, 0, 4, 4, 90, 1, 0, // Skip to: 5329 +/* 4983 */ MCD_OPC_Decode, 130, 10, 147, 1, // Opcode: AE_S32M_IU +/* 4988 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 5010 +/* 4993 */ MCD_OPC_CheckPredicate, 24, 75, 1, 0, // Skip to: 5329 +/* 4998 */ MCD_OPC_CheckField, 0, 4, 4, 68, 1, 0, // Skip to: 5329 +/* 5005 */ MCD_OPC_Decode, 131, 10, 153, 1, // Opcode: AE_S32M_X +/* 5010 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 5032 +/* 5015 */ MCD_OPC_CheckPredicate, 24, 53, 1, 0, // Skip to: 5329 +/* 5020 */ MCD_OPC_CheckField, 0, 4, 4, 46, 1, 0, // Skip to: 5329 +/* 5027 */ MCD_OPC_Decode, 133, 10, 148, 1, // Opcode: AE_S32M_XU +/* 5032 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 5054 +/* 5037 */ MCD_OPC_CheckPredicate, 24, 31, 1, 0, // Skip to: 5329 +/* 5042 */ MCD_OPC_CheckField, 0, 4, 4, 24, 1, 0, // Skip to: 5329 +/* 5049 */ MCD_OPC_Decode, 152, 10, 148, 1, // Opcode: AE_S32X2_XC +/* 5054 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 5076 +/* 5059 */ MCD_OPC_CheckPredicate, 24, 9, 1, 0, // Skip to: 5329 +/* 5064 */ MCD_OPC_CheckField, 0, 4, 4, 2, 1, 0, // Skip to: 5329 +/* 5071 */ MCD_OPC_Decode, 147, 10, 146, 1, // Opcode: AE_S32X2_I +/* 5076 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 5098 +/* 5081 */ MCD_OPC_CheckPredicate, 24, 243, 0, 0, // Skip to: 5329 +/* 5086 */ MCD_OPC_CheckField, 0, 4, 4, 236, 0, 0, // Skip to: 5329 +/* 5093 */ MCD_OPC_Decode, 151, 10, 153, 1, // Opcode: AE_S32X2_X +/* 5098 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 5120 +/* 5103 */ MCD_OPC_CheckPredicate, 24, 221, 0, 0, // Skip to: 5329 +/* 5108 */ MCD_OPC_CheckField, 0, 4, 4, 214, 0, 0, // Skip to: 5329 +/* 5115 */ MCD_OPC_Decode, 153, 10, 148, 1, // Opcode: AE_S32X2_XP +/* 5120 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5142 +/* 5125 */ MCD_OPC_CheckPredicate, 24, 199, 0, 0, // Skip to: 5329 +/* 5130 */ MCD_OPC_CheckField, 0, 4, 4, 192, 0, 0, // Skip to: 5329 +/* 5137 */ MCD_OPC_Decode, 144, 10, 148, 1, // Opcode: AE_S32X2F24_XC +/* 5142 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 5164 +/* 5147 */ MCD_OPC_CheckPredicate, 24, 177, 0, 0, // Skip to: 5329 +/* 5152 */ MCD_OPC_CheckField, 0, 4, 4, 170, 0, 0, // Skip to: 5329 +/* 5159 */ MCD_OPC_Decode, 139, 10, 146, 1, // Opcode: AE_S32X2F24_I +/* 5164 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5186 +/* 5169 */ MCD_OPC_CheckPredicate, 24, 155, 0, 0, // Skip to: 5329 +/* 5174 */ MCD_OPC_CheckField, 0, 4, 4, 148, 0, 0, // Skip to: 5329 +/* 5181 */ MCD_OPC_Decode, 143, 10, 153, 1, // Opcode: AE_S32X2F24_X +/* 5186 */ MCD_OPC_FilterValue, 15, 138, 0, 0, // Skip to: 5329 +/* 5191 */ MCD_OPC_CheckPredicate, 24, 133, 0, 0, // Skip to: 5329 +/* 5196 */ MCD_OPC_CheckField, 0, 4, 4, 126, 0, 0, // Skip to: 5329 +/* 5203 */ MCD_OPC_Decode, 145, 10, 148, 1, // Opcode: AE_S32X2F24_XP +/* 5208 */ MCD_OPC_FilterValue, 15, 116, 0, 0, // Skip to: 5329 +/* 5213 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5216 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 5314 +/* 5221 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... +/* 5224 */ MCD_OPC_FilterValue, 240, 7, 9, 0, 0, // Skip to: 5239 +/* 5230 */ MCD_OPC_CheckPredicate, 24, 94, 0, 0, // Skip to: 5329 +/* 5235 */ MCD_OPC_Decode, 164, 15, 25, // Opcode: WUR_AE_OVF_SAR +/* 5239 */ MCD_OPC_FilterValue, 241, 7, 9, 0, 0, // Skip to: 5254 +/* 5245 */ MCD_OPC_CheckPredicate, 24, 79, 0, 0, // Skip to: 5329 +/* 5250 */ MCD_OPC_Decode, 154, 15, 25, // Opcode: WUR_AE_BITHEAD +/* 5254 */ MCD_OPC_FilterValue, 242, 7, 9, 0, 0, // Skip to: 5269 +/* 5260 */ MCD_OPC_CheckPredicate, 24, 64, 0, 0, // Skip to: 5329 +/* 5265 */ MCD_OPC_Decode, 168, 15, 25, // Opcode: WUR_AE_TS_FTS_BU_BP +/* 5269 */ MCD_OPC_FilterValue, 243, 7, 9, 0, 0, // Skip to: 5284 +/* 5275 */ MCD_OPC_CheckPredicate, 24, 49, 0, 0, // Skip to: 5329 +/* 5280 */ MCD_OPC_Decode, 160, 15, 25, // Opcode: WUR_AE_CW_SD_NO +/* 5284 */ MCD_OPC_FilterValue, 246, 7, 9, 0, 0, // Skip to: 5299 +/* 5290 */ MCD_OPC_CheckPredicate, 24, 34, 0, 0, // Skip to: 5329 +/* 5295 */ MCD_OPC_Decode, 157, 15, 25, // Opcode: WUR_AE_CBEGIN0 +/* 5299 */ MCD_OPC_FilterValue, 247, 7, 24, 0, 0, // Skip to: 5329 +/* 5305 */ MCD_OPC_CheckPredicate, 24, 19, 0, 0, // Skip to: 5329 +/* 5310 */ MCD_OPC_Decode, 158, 15, 25, // Opcode: WUR_AE_CEND0 +/* 5314 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 5329 +/* 5319 */ MCD_OPC_CheckPredicate, 24, 5, 0, 0, // Skip to: 5329 +/* 5324 */ MCD_OPC_Decode, 135, 11, 188, 1, // Opcode: AE_TRUNCA32X2F64S +/* 5329 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableHIFI348[] = { +/* 0 */ MCD_OPC_ExtractField, 30, 18, // Inst{47-30} ... +/* 3 */ MCD_OPC_FilterValue, 128, 4, 24, 0, 0, // Skip to: 33 +/* 9 */ MCD_OPC_CheckPredicate, 24, 176, 30, 0, // Skip to: 7870 +/* 14 */ MCD_OPC_CheckField, 28, 2, 0, 169, 30, 0, // Skip to: 7870 +/* 21 */ MCD_OPC_CheckField, 0, 16, 14, 162, 30, 0, // Skip to: 7870 +/* 28 */ MCD_OPC_Decode, 247, 5, 189, 1, // Opcode: AE_MUL32U_LL +/* 33 */ MCD_OPC_FilterValue, 128, 8, 24, 0, 0, // Skip to: 63 +/* 39 */ MCD_OPC_CheckPredicate, 24, 146, 30, 0, // Skip to: 7870 +/* 44 */ MCD_OPC_CheckField, 28, 2, 0, 139, 30, 0, // Skip to: 7870 +/* 51 */ MCD_OPC_CheckField, 0, 16, 14, 132, 30, 0, // Skip to: 7870 +/* 58 */ MCD_OPC_Decode, 248, 5, 189, 1, // Opcode: AE_MUL32X16_H0 +/* 63 */ MCD_OPC_FilterValue, 128, 12, 24, 0, 0, // Skip to: 93 +/* 69 */ MCD_OPC_CheckPredicate, 24, 116, 30, 0, // Skip to: 7870 +/* 74 */ MCD_OPC_CheckField, 28, 2, 0, 109, 30, 0, // Skip to: 7870 +/* 81 */ MCD_OPC_CheckField, 0, 16, 14, 102, 30, 0, // Skip to: 7870 +/* 88 */ MCD_OPC_Decode, 250, 5, 189, 1, // Opcode: AE_MUL32X16_H1 +/* 93 */ MCD_OPC_FilterValue, 128, 16, 24, 0, 0, // Skip to: 123 +/* 99 */ MCD_OPC_CheckPredicate, 24, 86, 30, 0, // Skip to: 7870 +/* 104 */ MCD_OPC_CheckField, 28, 2, 0, 79, 30, 0, // Skip to: 7870 +/* 111 */ MCD_OPC_CheckField, 0, 16, 14, 72, 30, 0, // Skip to: 7870 +/* 118 */ MCD_OPC_Decode, 252, 5, 189, 1, // Opcode: AE_MUL32X16_H2 +/* 123 */ MCD_OPC_FilterValue, 128, 20, 24, 0, 0, // Skip to: 153 +/* 129 */ MCD_OPC_CheckPredicate, 24, 56, 30, 0, // Skip to: 7870 +/* 134 */ MCD_OPC_CheckField, 28, 2, 0, 49, 30, 0, // Skip to: 7870 +/* 141 */ MCD_OPC_CheckField, 0, 16, 14, 42, 30, 0, // Skip to: 7870 +/* 148 */ MCD_OPC_Decode, 254, 5, 189, 1, // Opcode: AE_MUL32X16_H3 +/* 153 */ MCD_OPC_FilterValue, 128, 24, 24, 0, 0, // Skip to: 183 +/* 159 */ MCD_OPC_CheckPredicate, 24, 26, 30, 0, // Skip to: 7870 +/* 164 */ MCD_OPC_CheckField, 28, 2, 0, 19, 30, 0, // Skip to: 7870 +/* 171 */ MCD_OPC_CheckField, 0, 16, 14, 12, 30, 0, // Skip to: 7870 +/* 178 */ MCD_OPC_Decode, 128, 6, 189, 1, // Opcode: AE_MUL32X16_L0 +/* 183 */ MCD_OPC_FilterValue, 128, 28, 24, 0, 0, // Skip to: 213 +/* 189 */ MCD_OPC_CheckPredicate, 24, 252, 29, 0, // Skip to: 7870 +/* 194 */ MCD_OPC_CheckField, 28, 2, 0, 245, 29, 0, // Skip to: 7870 +/* 201 */ MCD_OPC_CheckField, 0, 16, 14, 238, 29, 0, // Skip to: 7870 +/* 208 */ MCD_OPC_Decode, 130, 6, 189, 1, // Opcode: AE_MUL32X16_L1 +/* 213 */ MCD_OPC_FilterValue, 128, 32, 24, 0, 0, // Skip to: 243 +/* 219 */ MCD_OPC_CheckPredicate, 24, 222, 29, 0, // Skip to: 7870 +/* 224 */ MCD_OPC_CheckField, 28, 2, 0, 215, 29, 0, // Skip to: 7870 +/* 231 */ MCD_OPC_CheckField, 0, 16, 14, 208, 29, 0, // Skip to: 7870 +/* 238 */ MCD_OPC_Decode, 132, 6, 189, 1, // Opcode: AE_MUL32X16_L2 +/* 243 */ MCD_OPC_FilterValue, 128, 36, 24, 0, 0, // Skip to: 273 +/* 249 */ MCD_OPC_CheckPredicate, 24, 192, 29, 0, // Skip to: 7870 +/* 254 */ MCD_OPC_CheckField, 28, 2, 0, 185, 29, 0, // Skip to: 7870 +/* 261 */ MCD_OPC_CheckField, 0, 16, 14, 178, 29, 0, // Skip to: 7870 +/* 268 */ MCD_OPC_Decode, 134, 6, 189, 1, // Opcode: AE_MUL32X16_L3 +/* 273 */ MCD_OPC_FilterValue, 128, 40, 24, 0, 0, // Skip to: 303 +/* 279 */ MCD_OPC_CheckPredicate, 24, 162, 29, 0, // Skip to: 7870 +/* 284 */ MCD_OPC_CheckField, 28, 2, 0, 155, 29, 0, // Skip to: 7870 +/* 291 */ MCD_OPC_CheckField, 0, 16, 14, 148, 29, 0, // Skip to: 7870 +/* 298 */ MCD_OPC_Decode, 136, 6, 189, 1, // Opcode: AE_MUL32_HH +/* 303 */ MCD_OPC_FilterValue, 128, 44, 24, 0, 0, // Skip to: 333 +/* 309 */ MCD_OPC_CheckPredicate, 24, 132, 29, 0, // Skip to: 7870 +/* 314 */ MCD_OPC_CheckField, 28, 2, 0, 125, 29, 0, // Skip to: 7870 +/* 321 */ MCD_OPC_CheckField, 0, 16, 14, 118, 29, 0, // Skip to: 7870 +/* 328 */ MCD_OPC_Decode, 137, 6, 189, 1, // Opcode: AE_MUL32_LH +/* 333 */ MCD_OPC_FilterValue, 128, 48, 24, 0, 0, // Skip to: 363 +/* 339 */ MCD_OPC_CheckPredicate, 24, 102, 29, 0, // Skip to: 7870 +/* 344 */ MCD_OPC_CheckField, 28, 2, 0, 95, 29, 0, // Skip to: 7870 +/* 351 */ MCD_OPC_CheckField, 0, 16, 14, 88, 29, 0, // Skip to: 7870 +/* 358 */ MCD_OPC_Decode, 138, 6, 189, 1, // Opcode: AE_MUL32_LL +/* 363 */ MCD_OPC_FilterValue, 128, 56, 24, 0, 0, // Skip to: 393 +/* 369 */ MCD_OPC_CheckPredicate, 24, 72, 29, 0, // Skip to: 7870 +/* 374 */ MCD_OPC_CheckField, 28, 2, 0, 65, 29, 0, // Skip to: 7870 +/* 381 */ MCD_OPC_CheckField, 0, 16, 14, 58, 29, 0, // Skip to: 7870 +/* 388 */ MCD_OPC_Decode, 141, 6, 190, 1, // Opcode: AE_MULA32U_LL +/* 393 */ MCD_OPC_FilterValue, 128, 60, 24, 0, 0, // Skip to: 423 +/* 399 */ MCD_OPC_CheckPredicate, 24, 42, 29, 0, // Skip to: 7870 +/* 404 */ MCD_OPC_CheckField, 28, 2, 0, 35, 29, 0, // Skip to: 7870 +/* 411 */ MCD_OPC_CheckField, 0, 16, 14, 28, 29, 0, // Skip to: 7870 +/* 418 */ MCD_OPC_Decode, 142, 6, 190, 1, // Opcode: AE_MULA32X16_H0 +/* 423 */ MCD_OPC_FilterValue, 128, 64, 24, 0, 0, // Skip to: 453 +/* 429 */ MCD_OPC_CheckPredicate, 24, 12, 29, 0, // Skip to: 7870 +/* 434 */ MCD_OPC_CheckField, 28, 2, 0, 5, 29, 0, // Skip to: 7870 +/* 441 */ MCD_OPC_CheckField, 0, 16, 14, 254, 28, 0, // Skip to: 7870 +/* 448 */ MCD_OPC_Decode, 144, 6, 190, 1, // Opcode: AE_MULA32X16_H1 +/* 453 */ MCD_OPC_FilterValue, 128, 68, 24, 0, 0, // Skip to: 483 +/* 459 */ MCD_OPC_CheckPredicate, 24, 238, 28, 0, // Skip to: 7870 +/* 464 */ MCD_OPC_CheckField, 28, 2, 0, 231, 28, 0, // Skip to: 7870 +/* 471 */ MCD_OPC_CheckField, 0, 16, 14, 224, 28, 0, // Skip to: 7870 +/* 478 */ MCD_OPC_Decode, 146, 6, 190, 1, // Opcode: AE_MULA32X16_H2 +/* 483 */ MCD_OPC_FilterValue, 128, 72, 24, 0, 0, // Skip to: 513 +/* 489 */ MCD_OPC_CheckPredicate, 24, 208, 28, 0, // Skip to: 7870 +/* 494 */ MCD_OPC_CheckField, 28, 2, 0, 201, 28, 0, // Skip to: 7870 +/* 501 */ MCD_OPC_CheckField, 0, 16, 14, 194, 28, 0, // Skip to: 7870 +/* 508 */ MCD_OPC_Decode, 148, 6, 190, 1, // Opcode: AE_MULA32X16_H3 +/* 513 */ MCD_OPC_FilterValue, 128, 76, 24, 0, 0, // Skip to: 543 +/* 519 */ MCD_OPC_CheckPredicate, 24, 178, 28, 0, // Skip to: 7870 +/* 524 */ MCD_OPC_CheckField, 28, 2, 0, 171, 28, 0, // Skip to: 7870 +/* 531 */ MCD_OPC_CheckField, 0, 16, 14, 164, 28, 0, // Skip to: 7870 +/* 538 */ MCD_OPC_Decode, 150, 6, 190, 1, // Opcode: AE_MULA32X16_L0 +/* 543 */ MCD_OPC_FilterValue, 128, 80, 24, 0, 0, // Skip to: 573 +/* 549 */ MCD_OPC_CheckPredicate, 24, 148, 28, 0, // Skip to: 7870 +/* 554 */ MCD_OPC_CheckField, 28, 2, 0, 141, 28, 0, // Skip to: 7870 +/* 561 */ MCD_OPC_CheckField, 0, 16, 14, 134, 28, 0, // Skip to: 7870 +/* 568 */ MCD_OPC_Decode, 152, 6, 190, 1, // Opcode: AE_MULA32X16_L1 +/* 573 */ MCD_OPC_FilterValue, 128, 84, 24, 0, 0, // Skip to: 603 +/* 579 */ MCD_OPC_CheckPredicate, 24, 118, 28, 0, // Skip to: 7870 +/* 584 */ MCD_OPC_CheckField, 28, 2, 0, 111, 28, 0, // Skip to: 7870 +/* 591 */ MCD_OPC_CheckField, 0, 16, 14, 104, 28, 0, // Skip to: 7870 +/* 598 */ MCD_OPC_Decode, 154, 6, 190, 1, // Opcode: AE_MULA32X16_L2 +/* 603 */ MCD_OPC_FilterValue, 128, 88, 24, 0, 0, // Skip to: 633 +/* 609 */ MCD_OPC_CheckPredicate, 24, 88, 28, 0, // Skip to: 7870 +/* 614 */ MCD_OPC_CheckField, 28, 2, 0, 81, 28, 0, // Skip to: 7870 +/* 621 */ MCD_OPC_CheckField, 0, 16, 14, 74, 28, 0, // Skip to: 7870 +/* 628 */ MCD_OPC_Decode, 156, 6, 190, 1, // Opcode: AE_MULA32X16_L3 +/* 633 */ MCD_OPC_FilterValue, 128, 92, 24, 0, 0, // Skip to: 663 +/* 639 */ MCD_OPC_CheckPredicate, 24, 58, 28, 0, // Skip to: 7870 +/* 644 */ MCD_OPC_CheckField, 28, 2, 0, 51, 28, 0, // Skip to: 7870 +/* 651 */ MCD_OPC_CheckField, 0, 16, 14, 44, 28, 0, // Skip to: 7870 +/* 658 */ MCD_OPC_Decode, 158, 6, 190, 1, // Opcode: AE_MULA32_HH +/* 663 */ MCD_OPC_FilterValue, 128, 96, 24, 0, 0, // Skip to: 693 +/* 669 */ MCD_OPC_CheckPredicate, 24, 28, 28, 0, // Skip to: 7870 +/* 674 */ MCD_OPC_CheckField, 28, 2, 0, 21, 28, 0, // Skip to: 7870 +/* 681 */ MCD_OPC_CheckField, 0, 16, 14, 14, 28, 0, // Skip to: 7870 +/* 688 */ MCD_OPC_Decode, 159, 6, 190, 1, // Opcode: AE_MULA32_LH +/* 693 */ MCD_OPC_FilterValue, 128, 100, 24, 0, 0, // Skip to: 723 +/* 699 */ MCD_OPC_CheckPredicate, 24, 254, 27, 0, // Skip to: 7870 +/* 704 */ MCD_OPC_CheckField, 28, 2, 0, 247, 27, 0, // Skip to: 7870 +/* 711 */ MCD_OPC_CheckField, 0, 16, 14, 240, 27, 0, // Skip to: 7870 +/* 718 */ MCD_OPC_Decode, 160, 6, 190, 1, // Opcode: AE_MULA32_LL +/* 723 */ MCD_OPC_FilterValue, 128, 108, 24, 0, 0, // Skip to: 753 +/* 729 */ MCD_OPC_CheckPredicate, 24, 224, 27, 0, // Skip to: 7870 +/* 734 */ MCD_OPC_CheckField, 28, 2, 0, 217, 27, 0, // Skip to: 7870 +/* 741 */ MCD_OPC_CheckField, 0, 16, 14, 210, 27, 0, // Skip to: 7870 +/* 748 */ MCD_OPC_Decode, 166, 6, 190, 1, // Opcode: AE_MULAAD32X16_H0_L1 +/* 753 */ MCD_OPC_FilterValue, 128, 112, 24, 0, 0, // Skip to: 783 +/* 759 */ MCD_OPC_CheckPredicate, 24, 194, 27, 0, // Skip to: 7870 +/* 764 */ MCD_OPC_CheckField, 28, 2, 0, 187, 27, 0, // Skip to: 7870 +/* 771 */ MCD_OPC_CheckField, 0, 16, 14, 180, 27, 0, // Skip to: 7870 +/* 778 */ MCD_OPC_Decode, 168, 6, 190, 1, // Opcode: AE_MULAAD32X16_H1_L0 +/* 783 */ MCD_OPC_FilterValue, 128, 116, 24, 0, 0, // Skip to: 813 +/* 789 */ MCD_OPC_CheckPredicate, 24, 164, 27, 0, // Skip to: 7870 +/* 794 */ MCD_OPC_CheckField, 28, 2, 0, 157, 27, 0, // Skip to: 7870 +/* 801 */ MCD_OPC_CheckField, 0, 16, 14, 150, 27, 0, // Skip to: 7870 +/* 808 */ MCD_OPC_Decode, 170, 6, 190, 1, // Opcode: AE_MULAAD32X16_H2_L3 +/* 813 */ MCD_OPC_FilterValue, 128, 120, 24, 0, 0, // Skip to: 843 +/* 819 */ MCD_OPC_CheckPredicate, 24, 134, 27, 0, // Skip to: 7870 +/* 824 */ MCD_OPC_CheckField, 28, 2, 0, 127, 27, 0, // Skip to: 7870 +/* 831 */ MCD_OPC_CheckField, 0, 16, 14, 120, 27, 0, // Skip to: 7870 +/* 838 */ MCD_OPC_Decode, 172, 6, 190, 1, // Opcode: AE_MULAAD32X16_H3_L2 +/* 843 */ MCD_OPC_FilterValue, 128, 132, 1, 24, 0, 0, // Skip to: 874 +/* 850 */ MCD_OPC_CheckPredicate, 24, 103, 27, 0, // Skip to: 7870 +/* 855 */ MCD_OPC_CheckField, 28, 2, 0, 96, 27, 0, // Skip to: 7870 +/* 862 */ MCD_OPC_CheckField, 0, 16, 14, 89, 27, 0, // Skip to: 7870 +/* 869 */ MCD_OPC_Decode, 174, 6, 190, 1, // Opcode: AE_MULAAFD16SS_11_00 +/* 874 */ MCD_OPC_FilterValue, 128, 136, 1, 24, 0, 0, // Skip to: 905 +/* 881 */ MCD_OPC_CheckPredicate, 24, 72, 27, 0, // Skip to: 7870 +/* 886 */ MCD_OPC_CheckField, 28, 2, 0, 65, 27, 0, // Skip to: 7870 +/* 893 */ MCD_OPC_CheckField, 0, 16, 14, 58, 27, 0, // Skip to: 7870 +/* 900 */ MCD_OPC_Decode, 176, 6, 190, 1, // Opcode: AE_MULAAFD16SS_13_02 +/* 905 */ MCD_OPC_FilterValue, 128, 140, 1, 24, 0, 0, // Skip to: 936 +/* 912 */ MCD_OPC_CheckPredicate, 24, 41, 27, 0, // Skip to: 7870 +/* 917 */ MCD_OPC_CheckField, 28, 2, 0, 34, 27, 0, // Skip to: 7870 +/* 924 */ MCD_OPC_CheckField, 0, 16, 14, 27, 27, 0, // Skip to: 7870 +/* 931 */ MCD_OPC_Decode, 178, 6, 190, 1, // Opcode: AE_MULAAFD16SS_33_22 +/* 936 */ MCD_OPC_FilterValue, 128, 160, 1, 24, 0, 0, // Skip to: 967 +/* 943 */ MCD_OPC_CheckPredicate, 24, 10, 27, 0, // Skip to: 7870 +/* 948 */ MCD_OPC_CheckField, 28, 2, 0, 3, 27, 0, // Skip to: 7870 +/* 955 */ MCD_OPC_CheckField, 0, 16, 14, 252, 26, 0, // Skip to: 7870 +/* 962 */ MCD_OPC_Decode, 184, 6, 190, 1, // Opcode: AE_MULAAFD32X16_H0_L1 +/* 967 */ MCD_OPC_FilterValue, 128, 164, 1, 24, 0, 0, // Skip to: 998 +/* 974 */ MCD_OPC_CheckPredicate, 24, 235, 26, 0, // Skip to: 7870 +/* 979 */ MCD_OPC_CheckField, 28, 2, 0, 228, 26, 0, // Skip to: 7870 +/* 986 */ MCD_OPC_CheckField, 0, 16, 14, 221, 26, 0, // Skip to: 7870 +/* 993 */ MCD_OPC_Decode, 186, 6, 190, 1, // Opcode: AE_MULAAFD32X16_H1_L0 +/* 998 */ MCD_OPC_FilterValue, 128, 168, 1, 24, 0, 0, // Skip to: 1029 +/* 1005 */ MCD_OPC_CheckPredicate, 24, 204, 26, 0, // Skip to: 7870 +/* 1010 */ MCD_OPC_CheckField, 28, 2, 0, 197, 26, 0, // Skip to: 7870 +/* 1017 */ MCD_OPC_CheckField, 0, 16, 14, 190, 26, 0, // Skip to: 7870 +/* 1024 */ MCD_OPC_Decode, 188, 6, 190, 1, // Opcode: AE_MULAAFD32X16_H2_L3 +/* 1029 */ MCD_OPC_FilterValue, 128, 172, 1, 24, 0, 0, // Skip to: 1060 +/* 1036 */ MCD_OPC_CheckPredicate, 24, 173, 26, 0, // Skip to: 7870 +/* 1041 */ MCD_OPC_CheckField, 28, 2, 0, 166, 26, 0, // Skip to: 7870 +/* 1048 */ MCD_OPC_CheckField, 0, 16, 14, 159, 26, 0, // Skip to: 7870 +/* 1055 */ MCD_OPC_Decode, 190, 6, 190, 1, // Opcode: AE_MULAAFD32X16_H3_L2 +/* 1060 */ MCD_OPC_FilterValue, 128, 176, 1, 24, 0, 0, // Skip to: 1091 +/* 1067 */ MCD_OPC_CheckPredicate, 24, 142, 26, 0, // Skip to: 7870 +/* 1072 */ MCD_OPC_CheckField, 28, 2, 0, 135, 26, 0, // Skip to: 7870 +/* 1079 */ MCD_OPC_CheckField, 0, 16, 14, 128, 26, 0, // Skip to: 7870 +/* 1086 */ MCD_OPC_Decode, 195, 6, 190, 1, // Opcode: AE_MULAF16SS_00 +/* 1091 */ MCD_OPC_FilterValue, 128, 180, 1, 24, 0, 0, // Skip to: 1122 +/* 1098 */ MCD_OPC_CheckPredicate, 24, 111, 26, 0, // Skip to: 7870 +/* 1103 */ MCD_OPC_CheckField, 28, 2, 0, 104, 26, 0, // Skip to: 7870 +/* 1110 */ MCD_OPC_CheckField, 0, 16, 14, 97, 26, 0, // Skip to: 7870 +/* 1117 */ MCD_OPC_Decode, 207, 6, 190, 1, // Opcode: AE_MULAF32R_HH +/* 1122 */ MCD_OPC_FilterValue, 128, 184, 1, 24, 0, 0, // Skip to: 1153 +/* 1129 */ MCD_OPC_CheckPredicate, 24, 80, 26, 0, // Skip to: 7870 +/* 1134 */ MCD_OPC_CheckField, 28, 2, 0, 73, 26, 0, // Skip to: 7870 +/* 1141 */ MCD_OPC_CheckField, 0, 16, 14, 66, 26, 0, // Skip to: 7870 +/* 1148 */ MCD_OPC_Decode, 208, 6, 190, 1, // Opcode: AE_MULAF32R_LH +/* 1153 */ MCD_OPC_FilterValue, 128, 188, 1, 24, 0, 0, // Skip to: 1184 +/* 1160 */ MCD_OPC_CheckPredicate, 24, 49, 26, 0, // Skip to: 7870 +/* 1165 */ MCD_OPC_CheckField, 28, 2, 0, 42, 26, 0, // Skip to: 7870 +/* 1172 */ MCD_OPC_CheckField, 0, 16, 14, 35, 26, 0, // Skip to: 7870 +/* 1179 */ MCD_OPC_Decode, 209, 6, 190, 1, // Opcode: AE_MULAF32R_LL +/* 1184 */ MCD_OPC_FilterValue, 128, 192, 1, 24, 0, 0, // Skip to: 1215 +/* 1191 */ MCD_OPC_CheckPredicate, 24, 18, 26, 0, // Skip to: 7870 +/* 1196 */ MCD_OPC_CheckField, 28, 2, 0, 11, 26, 0, // Skip to: 7870 +/* 1203 */ MCD_OPC_CheckField, 0, 16, 14, 4, 26, 0, // Skip to: 7870 +/* 1210 */ MCD_OPC_Decode, 211, 6, 190, 1, // Opcode: AE_MULAF32S_HH +/* 1215 */ MCD_OPC_FilterValue, 128, 196, 1, 24, 0, 0, // Skip to: 1246 +/* 1222 */ MCD_OPC_CheckPredicate, 24, 243, 25, 0, // Skip to: 7870 +/* 1227 */ MCD_OPC_CheckField, 28, 2, 0, 236, 25, 0, // Skip to: 7870 +/* 1234 */ MCD_OPC_CheckField, 0, 16, 14, 229, 25, 0, // Skip to: 7870 +/* 1241 */ MCD_OPC_Decode, 212, 6, 190, 1, // Opcode: AE_MULAF32S_LH +/* 1246 */ MCD_OPC_FilterValue, 128, 200, 1, 24, 0, 0, // Skip to: 1277 +/* 1253 */ MCD_OPC_CheckPredicate, 24, 212, 25, 0, // Skip to: 7870 +/* 1258 */ MCD_OPC_CheckField, 28, 2, 0, 205, 25, 0, // Skip to: 7870 +/* 1265 */ MCD_OPC_CheckField, 0, 16, 14, 198, 25, 0, // Skip to: 7870 +/* 1272 */ MCD_OPC_Decode, 213, 6, 190, 1, // Opcode: AE_MULAF32S_LL +/* 1277 */ MCD_OPC_FilterValue, 128, 204, 1, 24, 0, 0, // Skip to: 1308 +/* 1284 */ MCD_OPC_CheckPredicate, 24, 181, 25, 0, // Skip to: 7870 +/* 1289 */ MCD_OPC_CheckField, 28, 2, 0, 174, 25, 0, // Skip to: 7870 +/* 1296 */ MCD_OPC_CheckField, 0, 16, 14, 167, 25, 0, // Skip to: 7870 +/* 1303 */ MCD_OPC_Decode, 215, 6, 190, 1, // Opcode: AE_MULAF32X16_H0 +/* 1308 */ MCD_OPC_FilterValue, 128, 208, 1, 24, 0, 0, // Skip to: 1339 +/* 1315 */ MCD_OPC_CheckPredicate, 24, 150, 25, 0, // Skip to: 7870 +/* 1320 */ MCD_OPC_CheckField, 28, 2, 0, 143, 25, 0, // Skip to: 7870 +/* 1327 */ MCD_OPC_CheckField, 0, 16, 14, 136, 25, 0, // Skip to: 7870 +/* 1334 */ MCD_OPC_Decode, 217, 6, 190, 1, // Opcode: AE_MULAF32X16_H1 +/* 1339 */ MCD_OPC_FilterValue, 128, 212, 1, 24, 0, 0, // Skip to: 1370 +/* 1346 */ MCD_OPC_CheckPredicate, 24, 119, 25, 0, // Skip to: 7870 +/* 1351 */ MCD_OPC_CheckField, 28, 2, 0, 112, 25, 0, // Skip to: 7870 +/* 1358 */ MCD_OPC_CheckField, 0, 16, 14, 105, 25, 0, // Skip to: 7870 +/* 1365 */ MCD_OPC_Decode, 219, 6, 190, 1, // Opcode: AE_MULAF32X16_H2 +/* 1370 */ MCD_OPC_FilterValue, 128, 216, 1, 24, 0, 0, // Skip to: 1401 +/* 1377 */ MCD_OPC_CheckPredicate, 24, 88, 25, 0, // Skip to: 7870 +/* 1382 */ MCD_OPC_CheckField, 28, 2, 0, 81, 25, 0, // Skip to: 7870 +/* 1389 */ MCD_OPC_CheckField, 0, 16, 14, 74, 25, 0, // Skip to: 7870 +/* 1396 */ MCD_OPC_Decode, 221, 6, 190, 1, // Opcode: AE_MULAF32X16_H3 +/* 1401 */ MCD_OPC_FilterValue, 128, 220, 1, 24, 0, 0, // Skip to: 1432 +/* 1408 */ MCD_OPC_CheckPredicate, 24, 57, 25, 0, // Skip to: 7870 +/* 1413 */ MCD_OPC_CheckField, 28, 2, 0, 50, 25, 0, // Skip to: 7870 +/* 1420 */ MCD_OPC_CheckField, 0, 16, 14, 43, 25, 0, // Skip to: 7870 +/* 1427 */ MCD_OPC_Decode, 223, 6, 190, 1, // Opcode: AE_MULAF32X16_L0 +/* 1432 */ MCD_OPC_FilterValue, 128, 224, 1, 24, 0, 0, // Skip to: 1463 +/* 1439 */ MCD_OPC_CheckPredicate, 24, 26, 25, 0, // Skip to: 7870 +/* 1444 */ MCD_OPC_CheckField, 28, 2, 0, 19, 25, 0, // Skip to: 7870 +/* 1451 */ MCD_OPC_CheckField, 0, 16, 14, 12, 25, 0, // Skip to: 7870 +/* 1458 */ MCD_OPC_Decode, 225, 6, 190, 1, // Opcode: AE_MULAF32X16_L1 +/* 1463 */ MCD_OPC_FilterValue, 128, 228, 1, 24, 0, 0, // Skip to: 1494 +/* 1470 */ MCD_OPC_CheckPredicate, 24, 251, 24, 0, // Skip to: 7870 +/* 1475 */ MCD_OPC_CheckField, 28, 2, 0, 244, 24, 0, // Skip to: 7870 +/* 1482 */ MCD_OPC_CheckField, 0, 16, 14, 237, 24, 0, // Skip to: 7870 +/* 1489 */ MCD_OPC_Decode, 227, 6, 190, 1, // Opcode: AE_MULAF32X16_L2 +/* 1494 */ MCD_OPC_FilterValue, 128, 232, 1, 24, 0, 0, // Skip to: 1525 +/* 1501 */ MCD_OPC_CheckPredicate, 24, 220, 24, 0, // Skip to: 7870 +/* 1506 */ MCD_OPC_CheckField, 28, 2, 0, 213, 24, 0, // Skip to: 7870 +/* 1513 */ MCD_OPC_CheckField, 0, 16, 14, 206, 24, 0, // Skip to: 7870 +/* 1520 */ MCD_OPC_Decode, 229, 6, 190, 1, // Opcode: AE_MULAF32X16_L3 +/* 1525 */ MCD_OPC_FilterValue, 128, 236, 1, 24, 0, 0, // Skip to: 1556 +/* 1532 */ MCD_OPC_CheckPredicate, 24, 189, 24, 0, // Skip to: 7870 +/* 1537 */ MCD_OPC_CheckField, 28, 2, 0, 182, 24, 0, // Skip to: 7870 +/* 1544 */ MCD_OPC_CheckField, 0, 16, 14, 175, 24, 0, // Skip to: 7870 +/* 1551 */ MCD_OPC_Decode, 231, 6, 190, 1, // Opcode: AE_MULAF48Q32SP16S_L +/* 1556 */ MCD_OPC_FilterValue, 128, 240, 1, 24, 0, 0, // Skip to: 1587 +/* 1563 */ MCD_OPC_CheckPredicate, 24, 158, 24, 0, // Skip to: 7870 +/* 1568 */ MCD_OPC_CheckField, 28, 2, 0, 151, 24, 0, // Skip to: 7870 +/* 1575 */ MCD_OPC_CheckField, 0, 16, 14, 144, 24, 0, // Skip to: 7870 +/* 1582 */ MCD_OPC_Decode, 233, 6, 190, 1, // Opcode: AE_MULAF48Q32SP16U_L +/* 1587 */ MCD_OPC_FilterValue, 128, 244, 1, 24, 0, 0, // Skip to: 1618 +/* 1594 */ MCD_OPC_CheckPredicate, 24, 127, 24, 0, // Skip to: 7870 +/* 1599 */ MCD_OPC_CheckField, 28, 2, 0, 120, 24, 0, // Skip to: 7870 +/* 1606 */ MCD_OPC_CheckField, 0, 16, 14, 113, 24, 0, // Skip to: 7870 +/* 1613 */ MCD_OPC_Decode, 244, 6, 190, 1, // Opcode: AE_MULAFP24X2R +/* 1618 */ MCD_OPC_FilterValue, 128, 248, 1, 24, 0, 0, // Skip to: 1649 +/* 1625 */ MCD_OPC_CheckPredicate, 24, 96, 24, 0, // Skip to: 7870 +/* 1630 */ MCD_OPC_CheckField, 28, 2, 0, 89, 24, 0, // Skip to: 7870 +/* 1637 */ MCD_OPC_CheckField, 0, 16, 14, 82, 24, 0, // Skip to: 7870 +/* 1644 */ MCD_OPC_Decode, 245, 6, 190, 1, // Opcode: AE_MULAFP24X2RA +/* 1649 */ MCD_OPC_FilterValue, 128, 252, 1, 24, 0, 0, // Skip to: 1680 +/* 1656 */ MCD_OPC_CheckPredicate, 24, 65, 24, 0, // Skip to: 7870 +/* 1661 */ MCD_OPC_CheckField, 28, 2, 0, 58, 24, 0, // Skip to: 7870 +/* 1668 */ MCD_OPC_CheckField, 0, 16, 14, 51, 24, 0, // Skip to: 7870 +/* 1675 */ MCD_OPC_Decode, 248, 6, 190, 1, // Opcode: AE_MULAFP32X16X2RAS_H +/* 1680 */ MCD_OPC_FilterValue, 128, 128, 2, 24, 0, 0, // Skip to: 1711 +/* 1687 */ MCD_OPC_CheckPredicate, 24, 34, 24, 0, // Skip to: 7870 +/* 1692 */ MCD_OPC_CheckField, 28, 2, 0, 27, 24, 0, // Skip to: 7870 +/* 1699 */ MCD_OPC_CheckField, 0, 16, 14, 20, 24, 0, // Skip to: 7870 +/* 1706 */ MCD_OPC_Decode, 250, 6, 190, 1, // Opcode: AE_MULAFP32X16X2RAS_L +/* 1711 */ MCD_OPC_FilterValue, 128, 132, 2, 24, 0, 0, // Skip to: 1742 +/* 1718 */ MCD_OPC_CheckPredicate, 24, 3, 24, 0, // Skip to: 7870 +/* 1723 */ MCD_OPC_CheckField, 28, 2, 0, 252, 23, 0, // Skip to: 7870 +/* 1730 */ MCD_OPC_CheckField, 0, 16, 14, 245, 23, 0, // Skip to: 7870 +/* 1737 */ MCD_OPC_Decode, 252, 6, 190, 1, // Opcode: AE_MULAFP32X16X2RS_H +/* 1742 */ MCD_OPC_FilterValue, 128, 136, 2, 24, 0, 0, // Skip to: 1773 +/* 1749 */ MCD_OPC_CheckPredicate, 24, 228, 23, 0, // Skip to: 7870 +/* 1754 */ MCD_OPC_CheckField, 28, 2, 0, 221, 23, 0, // Skip to: 7870 +/* 1761 */ MCD_OPC_CheckField, 0, 16, 14, 214, 23, 0, // Skip to: 7870 +/* 1768 */ MCD_OPC_Decode, 254, 6, 190, 1, // Opcode: AE_MULAFP32X16X2RS_L +/* 1773 */ MCD_OPC_FilterValue, 128, 148, 2, 24, 0, 0, // Skip to: 1804 +/* 1780 */ MCD_OPC_CheckPredicate, 24, 197, 23, 0, // Skip to: 7870 +/* 1785 */ MCD_OPC_CheckField, 28, 2, 0, 190, 23, 0, // Skip to: 7870 +/* 1792 */ MCD_OPC_CheckField, 0, 16, 14, 183, 23, 0, // Skip to: 7870 +/* 1799 */ MCD_OPC_Decode, 128, 7, 190, 1, // Opcode: AE_MULAFP32X2RAS +/* 1804 */ MCD_OPC_FilterValue, 128, 152, 2, 24, 0, 0, // Skip to: 1835 +/* 1811 */ MCD_OPC_CheckPredicate, 24, 166, 23, 0, // Skip to: 7870 +/* 1816 */ MCD_OPC_CheckField, 28, 2, 0, 159, 23, 0, // Skip to: 7870 +/* 1823 */ MCD_OPC_CheckField, 0, 16, 14, 152, 23, 0, // Skip to: 7870 +/* 1830 */ MCD_OPC_Decode, 129, 7, 190, 1, // Opcode: AE_MULAFP32X2RS +/* 1835 */ MCD_OPC_FilterValue, 128, 156, 2, 24, 0, 0, // Skip to: 1866 +/* 1842 */ MCD_OPC_CheckPredicate, 24, 135, 23, 0, // Skip to: 7870 +/* 1847 */ MCD_OPC_CheckField, 28, 2, 0, 128, 23, 0, // Skip to: 7870 +/* 1854 */ MCD_OPC_CheckField, 0, 16, 14, 121, 23, 0, // Skip to: 7870 +/* 1861 */ MCD_OPC_Decode, 134, 7, 190, 1, // Opcode: AE_MULAP32X16X2_H +/* 1866 */ MCD_OPC_FilterValue, 128, 160, 2, 24, 0, 0, // Skip to: 1897 +/* 1873 */ MCD_OPC_CheckPredicate, 24, 104, 23, 0, // Skip to: 7870 +/* 1878 */ MCD_OPC_CheckField, 28, 2, 0, 97, 23, 0, // Skip to: 7870 +/* 1885 */ MCD_OPC_CheckField, 0, 16, 14, 90, 23, 0, // Skip to: 7870 +/* 1892 */ MCD_OPC_Decode, 135, 7, 190, 1, // Opcode: AE_MULAP32X16X2_L +/* 1897 */ MCD_OPC_FilterValue, 128, 164, 2, 24, 0, 0, // Skip to: 1928 +/* 1904 */ MCD_OPC_CheckPredicate, 24, 73, 23, 0, // Skip to: 7870 +/* 1909 */ MCD_OPC_CheckField, 28, 2, 0, 66, 23, 0, // Skip to: 7870 +/* 1916 */ MCD_OPC_CheckField, 0, 16, 14, 59, 23, 0, // Skip to: 7870 +/* 1923 */ MCD_OPC_Decode, 136, 7, 190, 1, // Opcode: AE_MULAP32X2 +/* 1928 */ MCD_OPC_FilterValue, 128, 176, 2, 24, 0, 0, // Skip to: 1959 +/* 1935 */ MCD_OPC_CheckPredicate, 24, 42, 23, 0, // Skip to: 7870 +/* 1940 */ MCD_OPC_CheckField, 28, 2, 0, 35, 23, 0, // Skip to: 7870 +/* 1947 */ MCD_OPC_CheckField, 0, 16, 14, 28, 23, 0, // Skip to: 7870 +/* 1954 */ MCD_OPC_Decode, 141, 7, 190, 1, // Opcode: AE_MULAS32F48P16S_HH +/* 1959 */ MCD_OPC_FilterValue, 128, 180, 2, 24, 0, 0, // Skip to: 1990 +/* 1966 */ MCD_OPC_CheckPredicate, 24, 11, 23, 0, // Skip to: 7870 +/* 1971 */ MCD_OPC_CheckField, 28, 2, 0, 4, 23, 0, // Skip to: 7870 +/* 1978 */ MCD_OPC_CheckField, 0, 16, 14, 253, 22, 0, // Skip to: 7870 +/* 1985 */ MCD_OPC_Decode, 143, 7, 190, 1, // Opcode: AE_MULAS32F48P16S_LH +/* 1990 */ MCD_OPC_FilterValue, 128, 184, 2, 24, 0, 0, // Skip to: 2021 +/* 1997 */ MCD_OPC_CheckPredicate, 24, 236, 22, 0, // Skip to: 7870 +/* 2002 */ MCD_OPC_CheckField, 28, 2, 0, 229, 22, 0, // Skip to: 7870 +/* 2009 */ MCD_OPC_CheckField, 0, 16, 14, 222, 22, 0, // Skip to: 7870 +/* 2016 */ MCD_OPC_Decode, 145, 7, 190, 1, // Opcode: AE_MULAS32F48P16S_LL +/* 2021 */ MCD_OPC_FilterValue, 128, 188, 2, 24, 0, 0, // Skip to: 2052 +/* 2028 */ MCD_OPC_CheckPredicate, 24, 205, 22, 0, // Skip to: 7870 +/* 2033 */ MCD_OPC_CheckField, 28, 2, 0, 198, 22, 0, // Skip to: 7870 +/* 2040 */ MCD_OPC_CheckField, 0, 16, 14, 191, 22, 0, // Skip to: 7870 +/* 2047 */ MCD_OPC_Decode, 151, 7, 190, 1, // Opcode: AE_MULASD32X16_H1_L0 +/* 2052 */ MCD_OPC_FilterValue, 128, 192, 2, 24, 0, 0, // Skip to: 2083 +/* 2059 */ MCD_OPC_CheckPredicate, 24, 174, 22, 0, // Skip to: 7870 +/* 2064 */ MCD_OPC_CheckField, 28, 2, 0, 167, 22, 0, // Skip to: 7870 +/* 2071 */ MCD_OPC_CheckField, 0, 16, 14, 160, 22, 0, // Skip to: 7870 +/* 2078 */ MCD_OPC_Decode, 153, 7, 190, 1, // Opcode: AE_MULASD32X16_H3_L2 +/* 2083 */ MCD_OPC_FilterValue, 128, 220, 2, 24, 0, 0, // Skip to: 2114 +/* 2090 */ MCD_OPC_CheckPredicate, 24, 143, 22, 0, // Skip to: 7870 +/* 2095 */ MCD_OPC_CheckField, 28, 2, 0, 136, 22, 0, // Skip to: 7870 +/* 2102 */ MCD_OPC_CheckField, 0, 16, 14, 129, 22, 0, // Skip to: 7870 +/* 2109 */ MCD_OPC_Decode, 159, 7, 190, 1, // Opcode: AE_MULASFD32X16_H1_L0 +/* 2114 */ MCD_OPC_FilterValue, 128, 224, 2, 24, 0, 0, // Skip to: 2145 +/* 2121 */ MCD_OPC_CheckPredicate, 24, 112, 22, 0, // Skip to: 7870 +/* 2126 */ MCD_OPC_CheckField, 28, 2, 0, 105, 22, 0, // Skip to: 7870 +/* 2133 */ MCD_OPC_CheckField, 0, 16, 14, 98, 22, 0, // Skip to: 7870 +/* 2140 */ MCD_OPC_Decode, 161, 7, 190, 1, // Opcode: AE_MULASFD32X16_H3_L2 +/* 2145 */ MCD_OPC_FilterValue, 128, 228, 2, 24, 0, 0, // Skip to: 2176 +/* 2152 */ MCD_OPC_CheckPredicate, 24, 81, 22, 0, // Skip to: 7870 +/* 2157 */ MCD_OPC_CheckField, 28, 2, 0, 74, 22, 0, // Skip to: 7870 +/* 2164 */ MCD_OPC_CheckField, 0, 16, 14, 67, 22, 0, // Skip to: 7870 +/* 2171 */ MCD_OPC_Decode, 166, 7, 189, 1, // Opcode: AE_MULF16SS_00 +/* 2176 */ MCD_OPC_FilterValue, 128, 232, 2, 24, 0, 0, // Skip to: 2207 +/* 2183 */ MCD_OPC_CheckPredicate, 24, 50, 22, 0, // Skip to: 7870 +/* 2188 */ MCD_OPC_CheckField, 28, 2, 0, 43, 22, 0, // Skip to: 7870 +/* 2195 */ MCD_OPC_CheckField, 0, 16, 14, 36, 22, 0, // Skip to: 7870 +/* 2202 */ MCD_OPC_Decode, 178, 7, 189, 1, // Opcode: AE_MULF32R_HH +/* 2207 */ MCD_OPC_FilterValue, 128, 236, 2, 24, 0, 0, // Skip to: 2238 +/* 2214 */ MCD_OPC_CheckPredicate, 24, 19, 22, 0, // Skip to: 7870 +/* 2219 */ MCD_OPC_CheckField, 28, 2, 0, 12, 22, 0, // Skip to: 7870 +/* 2226 */ MCD_OPC_CheckField, 0, 16, 14, 5, 22, 0, // Skip to: 7870 +/* 2233 */ MCD_OPC_Decode, 179, 7, 189, 1, // Opcode: AE_MULF32R_LH +/* 2238 */ MCD_OPC_FilterValue, 128, 240, 2, 24, 0, 0, // Skip to: 2269 +/* 2245 */ MCD_OPC_CheckPredicate, 24, 244, 21, 0, // Skip to: 7870 +/* 2250 */ MCD_OPC_CheckField, 28, 2, 0, 237, 21, 0, // Skip to: 7870 +/* 2257 */ MCD_OPC_CheckField, 0, 16, 14, 230, 21, 0, // Skip to: 7870 +/* 2264 */ MCD_OPC_Decode, 180, 7, 189, 1, // Opcode: AE_MULF32R_LL +/* 2269 */ MCD_OPC_FilterValue, 128, 244, 2, 24, 0, 0, // Skip to: 2300 +/* 2276 */ MCD_OPC_CheckPredicate, 24, 213, 21, 0, // Skip to: 7870 +/* 2281 */ MCD_OPC_CheckField, 28, 2, 0, 206, 21, 0, // Skip to: 7870 +/* 2288 */ MCD_OPC_CheckField, 0, 16, 14, 199, 21, 0, // Skip to: 7870 +/* 2295 */ MCD_OPC_Decode, 182, 7, 189, 1, // Opcode: AE_MULF32S_HH +/* 2300 */ MCD_OPC_FilterValue, 128, 248, 2, 24, 0, 0, // Skip to: 2331 +/* 2307 */ MCD_OPC_CheckPredicate, 24, 182, 21, 0, // Skip to: 7870 +/* 2312 */ MCD_OPC_CheckField, 28, 2, 0, 175, 21, 0, // Skip to: 7870 +/* 2319 */ MCD_OPC_CheckField, 0, 16, 14, 168, 21, 0, // Skip to: 7870 +/* 2326 */ MCD_OPC_Decode, 183, 7, 189, 1, // Opcode: AE_MULF32S_LH +/* 2331 */ MCD_OPC_FilterValue, 128, 252, 2, 24, 0, 0, // Skip to: 2362 +/* 2338 */ MCD_OPC_CheckPredicate, 24, 151, 21, 0, // Skip to: 7870 +/* 2343 */ MCD_OPC_CheckField, 28, 2, 0, 144, 21, 0, // Skip to: 7870 +/* 2350 */ MCD_OPC_CheckField, 0, 16, 14, 137, 21, 0, // Skip to: 7870 +/* 2357 */ MCD_OPC_Decode, 184, 7, 189, 1, // Opcode: AE_MULF32S_LL +/* 2362 */ MCD_OPC_FilterValue, 128, 128, 3, 24, 0, 0, // Skip to: 2393 +/* 2369 */ MCD_OPC_CheckPredicate, 24, 120, 21, 0, // Skip to: 7870 +/* 2374 */ MCD_OPC_CheckField, 28, 2, 0, 113, 21, 0, // Skip to: 7870 +/* 2381 */ MCD_OPC_CheckField, 0, 16, 14, 106, 21, 0, // Skip to: 7870 +/* 2388 */ MCD_OPC_Decode, 186, 7, 189, 1, // Opcode: AE_MULF32X16_H0 +/* 2393 */ MCD_OPC_FilterValue, 128, 132, 3, 24, 0, 0, // Skip to: 2424 +/* 2400 */ MCD_OPC_CheckPredicate, 24, 89, 21, 0, // Skip to: 7870 +/* 2405 */ MCD_OPC_CheckField, 28, 2, 0, 82, 21, 0, // Skip to: 7870 +/* 2412 */ MCD_OPC_CheckField, 0, 16, 14, 75, 21, 0, // Skip to: 7870 +/* 2419 */ MCD_OPC_Decode, 188, 7, 189, 1, // Opcode: AE_MULF32X16_H1 +/* 2424 */ MCD_OPC_FilterValue, 128, 136, 3, 24, 0, 0, // Skip to: 2455 +/* 2431 */ MCD_OPC_CheckPredicate, 24, 58, 21, 0, // Skip to: 7870 +/* 2436 */ MCD_OPC_CheckField, 28, 2, 0, 51, 21, 0, // Skip to: 7870 +/* 2443 */ MCD_OPC_CheckField, 0, 16, 14, 44, 21, 0, // Skip to: 7870 +/* 2450 */ MCD_OPC_Decode, 190, 7, 189, 1, // Opcode: AE_MULF32X16_H2 +/* 2455 */ MCD_OPC_FilterValue, 128, 140, 3, 24, 0, 0, // Skip to: 2486 +/* 2462 */ MCD_OPC_CheckPredicate, 24, 27, 21, 0, // Skip to: 7870 +/* 2467 */ MCD_OPC_CheckField, 28, 2, 0, 20, 21, 0, // Skip to: 7870 +/* 2474 */ MCD_OPC_CheckField, 0, 16, 14, 13, 21, 0, // Skip to: 7870 +/* 2481 */ MCD_OPC_Decode, 192, 7, 189, 1, // Opcode: AE_MULF32X16_H3 +/* 2486 */ MCD_OPC_FilterValue, 128, 144, 3, 24, 0, 0, // Skip to: 2517 +/* 2493 */ MCD_OPC_CheckPredicate, 24, 252, 20, 0, // Skip to: 7870 +/* 2498 */ MCD_OPC_CheckField, 28, 2, 0, 245, 20, 0, // Skip to: 7870 +/* 2505 */ MCD_OPC_CheckField, 0, 16, 14, 238, 20, 0, // Skip to: 7870 +/* 2512 */ MCD_OPC_Decode, 194, 7, 189, 1, // Opcode: AE_MULF32X16_L0 +/* 2517 */ MCD_OPC_FilterValue, 128, 148, 3, 24, 0, 0, // Skip to: 2548 +/* 2524 */ MCD_OPC_CheckPredicate, 24, 221, 20, 0, // Skip to: 7870 +/* 2529 */ MCD_OPC_CheckField, 28, 2, 0, 214, 20, 0, // Skip to: 7870 +/* 2536 */ MCD_OPC_CheckField, 0, 16, 14, 207, 20, 0, // Skip to: 7870 +/* 2543 */ MCD_OPC_Decode, 196, 7, 189, 1, // Opcode: AE_MULF32X16_L1 +/* 2548 */ MCD_OPC_FilterValue, 128, 152, 3, 24, 0, 0, // Skip to: 2579 +/* 2555 */ MCD_OPC_CheckPredicate, 24, 190, 20, 0, // Skip to: 7870 +/* 2560 */ MCD_OPC_CheckField, 28, 2, 0, 183, 20, 0, // Skip to: 7870 +/* 2567 */ MCD_OPC_CheckField, 0, 16, 14, 176, 20, 0, // Skip to: 7870 +/* 2574 */ MCD_OPC_Decode, 198, 7, 189, 1, // Opcode: AE_MULF32X16_L2 +/* 2579 */ MCD_OPC_FilterValue, 128, 156, 3, 24, 0, 0, // Skip to: 2610 +/* 2586 */ MCD_OPC_CheckPredicate, 24, 159, 20, 0, // Skip to: 7870 +/* 2591 */ MCD_OPC_CheckField, 28, 2, 0, 152, 20, 0, // Skip to: 7870 +/* 2598 */ MCD_OPC_CheckField, 0, 16, 14, 145, 20, 0, // Skip to: 7870 +/* 2605 */ MCD_OPC_Decode, 200, 7, 189, 1, // Opcode: AE_MULF32X16_L3 +/* 2610 */ MCD_OPC_FilterValue, 128, 160, 3, 24, 0, 0, // Skip to: 2641 +/* 2617 */ MCD_OPC_CheckPredicate, 24, 128, 20, 0, // Skip to: 7870 +/* 2622 */ MCD_OPC_CheckField, 28, 2, 0, 121, 20, 0, // Skip to: 7870 +/* 2629 */ MCD_OPC_CheckField, 0, 16, 14, 114, 20, 0, // Skip to: 7870 +/* 2636 */ MCD_OPC_Decode, 202, 7, 189, 1, // Opcode: AE_MULF48Q32SP16S_L +/* 2641 */ MCD_OPC_FilterValue, 128, 164, 3, 24, 0, 0, // Skip to: 2672 +/* 2648 */ MCD_OPC_CheckPredicate, 24, 97, 20, 0, // Skip to: 7870 +/* 2653 */ MCD_OPC_CheckField, 28, 2, 0, 90, 20, 0, // Skip to: 7870 +/* 2660 */ MCD_OPC_CheckField, 0, 16, 14, 83, 20, 0, // Skip to: 7870 +/* 2667 */ MCD_OPC_Decode, 204, 7, 189, 1, // Opcode: AE_MULF48Q32SP16U_L +/* 2672 */ MCD_OPC_FilterValue, 128, 168, 3, 24, 0, 0, // Skip to: 2703 +/* 2679 */ MCD_OPC_CheckPredicate, 24, 66, 20, 0, // Skip to: 7870 +/* 2684 */ MCD_OPC_CheckField, 28, 2, 0, 59, 20, 0, // Skip to: 7870 +/* 2691 */ MCD_OPC_CheckField, 0, 16, 14, 52, 20, 0, // Skip to: 7870 +/* 2698 */ MCD_OPC_Decode, 217, 7, 189, 1, // Opcode: AE_MULFP24X2R +/* 2703 */ MCD_OPC_FilterValue, 128, 172, 3, 24, 0, 0, // Skip to: 2734 +/* 2710 */ MCD_OPC_CheckPredicate, 24, 35, 20, 0, // Skip to: 7870 +/* 2715 */ MCD_OPC_CheckField, 28, 2, 0, 28, 20, 0, // Skip to: 7870 +/* 2722 */ MCD_OPC_CheckField, 0, 16, 14, 21, 20, 0, // Skip to: 7870 +/* 2729 */ MCD_OPC_Decode, 218, 7, 189, 1, // Opcode: AE_MULFP24X2RA +/* 2734 */ MCD_OPC_FilterValue, 128, 176, 3, 24, 0, 0, // Skip to: 2765 +/* 2741 */ MCD_OPC_CheckPredicate, 24, 4, 20, 0, // Skip to: 7870 +/* 2746 */ MCD_OPC_CheckField, 28, 2, 0, 253, 19, 0, // Skip to: 7870 +/* 2753 */ MCD_OPC_CheckField, 0, 16, 14, 246, 19, 0, // Skip to: 7870 +/* 2760 */ MCD_OPC_Decode, 221, 7, 189, 1, // Opcode: AE_MULFP32X16X2RAS_H +/* 2765 */ MCD_OPC_FilterValue, 128, 180, 3, 24, 0, 0, // Skip to: 2796 +/* 2772 */ MCD_OPC_CheckPredicate, 24, 229, 19, 0, // Skip to: 7870 +/* 2777 */ MCD_OPC_CheckField, 28, 2, 0, 222, 19, 0, // Skip to: 7870 +/* 2784 */ MCD_OPC_CheckField, 0, 16, 14, 215, 19, 0, // Skip to: 7870 +/* 2791 */ MCD_OPC_Decode, 223, 7, 189, 1, // Opcode: AE_MULFP32X16X2RAS_L +/* 2796 */ MCD_OPC_FilterValue, 128, 184, 3, 24, 0, 0, // Skip to: 2827 +/* 2803 */ MCD_OPC_CheckPredicate, 24, 198, 19, 0, // Skip to: 7870 +/* 2808 */ MCD_OPC_CheckField, 28, 2, 0, 191, 19, 0, // Skip to: 7870 +/* 2815 */ MCD_OPC_CheckField, 0, 16, 14, 184, 19, 0, // Skip to: 7870 +/* 2822 */ MCD_OPC_Decode, 225, 7, 189, 1, // Opcode: AE_MULFP32X16X2RS_H +/* 2827 */ MCD_OPC_FilterValue, 128, 188, 3, 24, 0, 0, // Skip to: 2858 +/* 2834 */ MCD_OPC_CheckPredicate, 24, 167, 19, 0, // Skip to: 7870 +/* 2839 */ MCD_OPC_CheckField, 28, 2, 0, 160, 19, 0, // Skip to: 7870 +/* 2846 */ MCD_OPC_CheckField, 0, 16, 14, 153, 19, 0, // Skip to: 7870 +/* 2853 */ MCD_OPC_Decode, 227, 7, 189, 1, // Opcode: AE_MULFP32X16X2RS_L +/* 2858 */ MCD_OPC_FilterValue, 128, 200, 3, 24, 0, 0, // Skip to: 2889 +/* 2865 */ MCD_OPC_CheckPredicate, 24, 136, 19, 0, // Skip to: 7870 +/* 2870 */ MCD_OPC_CheckField, 28, 2, 0, 129, 19, 0, // Skip to: 7870 +/* 2877 */ MCD_OPC_CheckField, 0, 16, 14, 122, 19, 0, // Skip to: 7870 +/* 2884 */ MCD_OPC_Decode, 229, 7, 189, 1, // Opcode: AE_MULFP32X2RAS +/* 2889 */ MCD_OPC_FilterValue, 128, 204, 3, 24, 0, 0, // Skip to: 2920 +/* 2896 */ MCD_OPC_CheckPredicate, 24, 105, 19, 0, // Skip to: 7870 +/* 2901 */ MCD_OPC_CheckField, 28, 2, 0, 98, 19, 0, // Skip to: 7870 +/* 2908 */ MCD_OPC_CheckField, 0, 16, 14, 91, 19, 0, // Skip to: 7870 +/* 2915 */ MCD_OPC_Decode, 230, 7, 189, 1, // Opcode: AE_MULFP32X2RS +/* 2920 */ MCD_OPC_FilterValue, 128, 208, 3, 24, 0, 0, // Skip to: 2951 +/* 2927 */ MCD_OPC_CheckPredicate, 24, 74, 19, 0, // Skip to: 7870 +/* 2932 */ MCD_OPC_CheckField, 28, 2, 0, 67, 19, 0, // Skip to: 7870 +/* 2939 */ MCD_OPC_CheckField, 0, 16, 14, 60, 19, 0, // Skip to: 7870 +/* 2946 */ MCD_OPC_Decode, 235, 7, 189, 1, // Opcode: AE_MULP32X16X2_H +/* 2951 */ MCD_OPC_FilterValue, 128, 212, 3, 24, 0, 0, // Skip to: 2982 +/* 2958 */ MCD_OPC_CheckPredicate, 24, 43, 19, 0, // Skip to: 7870 +/* 2963 */ MCD_OPC_CheckField, 28, 2, 0, 36, 19, 0, // Skip to: 7870 +/* 2970 */ MCD_OPC_CheckField, 0, 16, 14, 29, 19, 0, // Skip to: 7870 +/* 2977 */ MCD_OPC_Decode, 236, 7, 189, 1, // Opcode: AE_MULP32X16X2_L +/* 2982 */ MCD_OPC_FilterValue, 128, 216, 3, 24, 0, 0, // Skip to: 3013 +/* 2989 */ MCD_OPC_CheckPredicate, 24, 12, 19, 0, // Skip to: 7870 +/* 2994 */ MCD_OPC_CheckField, 28, 2, 0, 5, 19, 0, // Skip to: 7870 +/* 3001 */ MCD_OPC_CheckField, 0, 16, 14, 254, 18, 0, // Skip to: 7870 +/* 3008 */ MCD_OPC_Decode, 237, 7, 189, 1, // Opcode: AE_MULP32X2 +/* 3013 */ MCD_OPC_FilterValue, 128, 228, 3, 24, 0, 0, // Skip to: 3044 +/* 3020 */ MCD_OPC_CheckPredicate, 24, 237, 18, 0, // Skip to: 7870 +/* 3025 */ MCD_OPC_CheckField, 28, 2, 0, 230, 18, 0, // Skip to: 7870 +/* 3032 */ MCD_OPC_CheckField, 0, 16, 14, 223, 18, 0, // Skip to: 7870 +/* 3039 */ MCD_OPC_Decode, 243, 7, 189, 1, // Opcode: AE_MULS32F48P16S_HH +/* 3044 */ MCD_OPC_FilterValue, 128, 232, 3, 24, 0, 0, // Skip to: 3075 +/* 3051 */ MCD_OPC_CheckPredicate, 24, 206, 18, 0, // Skip to: 7870 +/* 3056 */ MCD_OPC_CheckField, 28, 2, 0, 199, 18, 0, // Skip to: 7870 +/* 3063 */ MCD_OPC_CheckField, 0, 16, 14, 192, 18, 0, // Skip to: 7870 +/* 3070 */ MCD_OPC_Decode, 245, 7, 189, 1, // Opcode: AE_MULS32F48P16S_LH +/* 3075 */ MCD_OPC_FilterValue, 128, 236, 3, 24, 0, 0, // Skip to: 3106 +/* 3082 */ MCD_OPC_CheckPredicate, 24, 175, 18, 0, // Skip to: 7870 +/* 3087 */ MCD_OPC_CheckField, 28, 2, 0, 168, 18, 0, // Skip to: 7870 +/* 3094 */ MCD_OPC_CheckField, 0, 16, 14, 161, 18, 0, // Skip to: 7870 +/* 3101 */ MCD_OPC_Decode, 247, 7, 189, 1, // Opcode: AE_MULS32F48P16S_LL +/* 3106 */ MCD_OPC_FilterValue, 128, 240, 3, 24, 0, 0, // Skip to: 3137 +/* 3113 */ MCD_OPC_CheckPredicate, 24, 144, 18, 0, // Skip to: 7870 +/* 3118 */ MCD_OPC_CheckField, 28, 2, 0, 137, 18, 0, // Skip to: 7870 +/* 3125 */ MCD_OPC_CheckField, 0, 16, 14, 130, 18, 0, // Skip to: 7870 +/* 3132 */ MCD_OPC_Decode, 249, 7, 190, 1, // Opcode: AE_MULS32U_LL +/* 3137 */ MCD_OPC_FilterValue, 128, 244, 3, 24, 0, 0, // Skip to: 3168 +/* 3144 */ MCD_OPC_CheckPredicate, 24, 113, 18, 0, // Skip to: 7870 +/* 3149 */ MCD_OPC_CheckField, 28, 2, 0, 106, 18, 0, // Skip to: 7870 +/* 3156 */ MCD_OPC_CheckField, 0, 16, 14, 99, 18, 0, // Skip to: 7870 +/* 3163 */ MCD_OPC_Decode, 250, 7, 190, 1, // Opcode: AE_MULS32X16_H0 +/* 3168 */ MCD_OPC_FilterValue, 128, 248, 3, 24, 0, 0, // Skip to: 3199 +/* 3175 */ MCD_OPC_CheckPredicate, 24, 82, 18, 0, // Skip to: 7870 +/* 3180 */ MCD_OPC_CheckField, 28, 2, 0, 75, 18, 0, // Skip to: 7870 +/* 3187 */ MCD_OPC_CheckField, 0, 16, 14, 68, 18, 0, // Skip to: 7870 +/* 3194 */ MCD_OPC_Decode, 252, 7, 190, 1, // Opcode: AE_MULS32X16_H1 +/* 3199 */ MCD_OPC_FilterValue, 128, 252, 3, 24, 0, 0, // Skip to: 3230 +/* 3206 */ MCD_OPC_CheckPredicate, 24, 51, 18, 0, // Skip to: 7870 +/* 3211 */ MCD_OPC_CheckField, 28, 2, 0, 44, 18, 0, // Skip to: 7870 +/* 3218 */ MCD_OPC_CheckField, 0, 16, 14, 37, 18, 0, // Skip to: 7870 +/* 3225 */ MCD_OPC_Decode, 254, 7, 190, 1, // Opcode: AE_MULS32X16_H2 +/* 3230 */ MCD_OPC_FilterValue, 128, 128, 4, 24, 0, 0, // Skip to: 3261 +/* 3237 */ MCD_OPC_CheckPredicate, 24, 20, 18, 0, // Skip to: 7870 +/* 3242 */ MCD_OPC_CheckField, 28, 2, 0, 13, 18, 0, // Skip to: 7870 +/* 3249 */ MCD_OPC_CheckField, 0, 16, 14, 6, 18, 0, // Skip to: 7870 +/* 3256 */ MCD_OPC_Decode, 128, 8, 190, 1, // Opcode: AE_MULS32X16_H3 +/* 3261 */ MCD_OPC_FilterValue, 128, 132, 4, 24, 0, 0, // Skip to: 3292 +/* 3268 */ MCD_OPC_CheckPredicate, 24, 245, 17, 0, // Skip to: 7870 +/* 3273 */ MCD_OPC_CheckField, 28, 2, 0, 238, 17, 0, // Skip to: 7870 +/* 3280 */ MCD_OPC_CheckField, 0, 16, 14, 231, 17, 0, // Skip to: 7870 +/* 3287 */ MCD_OPC_Decode, 130, 8, 190, 1, // Opcode: AE_MULS32X16_L0 +/* 3292 */ MCD_OPC_FilterValue, 128, 136, 4, 24, 0, 0, // Skip to: 3323 +/* 3299 */ MCD_OPC_CheckPredicate, 24, 214, 17, 0, // Skip to: 7870 +/* 3304 */ MCD_OPC_CheckField, 28, 2, 0, 207, 17, 0, // Skip to: 7870 +/* 3311 */ MCD_OPC_CheckField, 0, 16, 14, 200, 17, 0, // Skip to: 7870 +/* 3318 */ MCD_OPC_Decode, 132, 8, 190, 1, // Opcode: AE_MULS32X16_L1 +/* 3323 */ MCD_OPC_FilterValue, 128, 140, 4, 24, 0, 0, // Skip to: 3354 +/* 3330 */ MCD_OPC_CheckPredicate, 24, 183, 17, 0, // Skip to: 7870 +/* 3335 */ MCD_OPC_CheckField, 28, 2, 0, 176, 17, 0, // Skip to: 7870 +/* 3342 */ MCD_OPC_CheckField, 0, 16, 14, 169, 17, 0, // Skip to: 7870 +/* 3349 */ MCD_OPC_Decode, 134, 8, 190, 1, // Opcode: AE_MULS32X16_L2 +/* 3354 */ MCD_OPC_FilterValue, 128, 144, 4, 24, 0, 0, // Skip to: 3385 +/* 3361 */ MCD_OPC_CheckPredicate, 24, 152, 17, 0, // Skip to: 7870 +/* 3366 */ MCD_OPC_CheckField, 28, 2, 0, 145, 17, 0, // Skip to: 7870 +/* 3373 */ MCD_OPC_CheckField, 0, 16, 14, 138, 17, 0, // Skip to: 7870 +/* 3380 */ MCD_OPC_Decode, 136, 8, 190, 1, // Opcode: AE_MULS32X16_L3 +/* 3385 */ MCD_OPC_FilterValue, 128, 148, 4, 24, 0, 0, // Skip to: 3416 +/* 3392 */ MCD_OPC_CheckPredicate, 24, 121, 17, 0, // Skip to: 7870 +/* 3397 */ MCD_OPC_CheckField, 28, 2, 0, 114, 17, 0, // Skip to: 7870 +/* 3404 */ MCD_OPC_CheckField, 0, 16, 14, 107, 17, 0, // Skip to: 7870 +/* 3411 */ MCD_OPC_Decode, 138, 8, 190, 1, // Opcode: AE_MULS32_HH +/* 3416 */ MCD_OPC_FilterValue, 128, 152, 4, 24, 0, 0, // Skip to: 3447 +/* 3423 */ MCD_OPC_CheckPredicate, 24, 90, 17, 0, // Skip to: 7870 +/* 3428 */ MCD_OPC_CheckField, 28, 2, 0, 83, 17, 0, // Skip to: 7870 +/* 3435 */ MCD_OPC_CheckField, 0, 16, 14, 76, 17, 0, // Skip to: 7870 +/* 3442 */ MCD_OPC_Decode, 139, 8, 190, 1, // Opcode: AE_MULS32_LH +/* 3447 */ MCD_OPC_FilterValue, 128, 156, 4, 24, 0, 0, // Skip to: 3478 +/* 3454 */ MCD_OPC_CheckPredicate, 24, 59, 17, 0, // Skip to: 7870 +/* 3459 */ MCD_OPC_CheckField, 28, 2, 0, 52, 17, 0, // Skip to: 7870 +/* 3466 */ MCD_OPC_CheckField, 0, 16, 14, 45, 17, 0, // Skip to: 7870 +/* 3473 */ MCD_OPC_Decode, 140, 8, 190, 1, // Opcode: AE_MULS32_LL +/* 3478 */ MCD_OPC_FilterValue, 128, 172, 4, 24, 0, 0, // Skip to: 3509 +/* 3485 */ MCD_OPC_CheckPredicate, 24, 28, 17, 0, // Skip to: 7870 +/* 3490 */ MCD_OPC_CheckField, 28, 2, 0, 21, 17, 0, // Skip to: 7870 +/* 3497 */ MCD_OPC_CheckField, 0, 16, 14, 14, 17, 0, // Skip to: 7870 +/* 3504 */ MCD_OPC_Decode, 149, 8, 190, 1, // Opcode: AE_MULSAFD32X16_H1_L0 +/* 3509 */ MCD_OPC_FilterValue, 128, 176, 4, 24, 0, 0, // Skip to: 3540 +/* 3516 */ MCD_OPC_CheckPredicate, 24, 253, 16, 0, // Skip to: 7870 +/* 3521 */ MCD_OPC_CheckField, 28, 2, 0, 246, 16, 0, // Skip to: 7870 +/* 3528 */ MCD_OPC_CheckField, 0, 16, 14, 239, 16, 0, // Skip to: 7870 +/* 3535 */ MCD_OPC_Decode, 151, 8, 190, 1, // Opcode: AE_MULSAFD32X16_H3_L2 +/* 3540 */ MCD_OPC_FilterValue, 128, 180, 4, 24, 0, 0, // Skip to: 3571 +/* 3547 */ MCD_OPC_CheckPredicate, 24, 222, 16, 0, // Skip to: 7870 +/* 3552 */ MCD_OPC_CheckField, 28, 2, 0, 215, 16, 0, // Skip to: 7870 +/* 3559 */ MCD_OPC_CheckField, 0, 16, 14, 208, 16, 0, // Skip to: 7870 +/* 3566 */ MCD_OPC_Decode, 153, 8, 190, 1, // Opcode: AE_MULSF16SS_00 +/* 3571 */ MCD_OPC_FilterValue, 128, 184, 4, 24, 0, 0, // Skip to: 3602 +/* 3578 */ MCD_OPC_CheckPredicate, 24, 191, 16, 0, // Skip to: 7870 +/* 3583 */ MCD_OPC_CheckField, 28, 2, 0, 184, 16, 0, // Skip to: 7870 +/* 3590 */ MCD_OPC_CheckField, 0, 16, 14, 177, 16, 0, // Skip to: 7870 +/* 3597 */ MCD_OPC_Decode, 165, 8, 190, 1, // Opcode: AE_MULSF32R_HH +/* 3602 */ MCD_OPC_FilterValue, 128, 188, 4, 24, 0, 0, // Skip to: 3633 +/* 3609 */ MCD_OPC_CheckPredicate, 24, 160, 16, 0, // Skip to: 7870 +/* 3614 */ MCD_OPC_CheckField, 28, 2, 0, 153, 16, 0, // Skip to: 7870 +/* 3621 */ MCD_OPC_CheckField, 0, 16, 14, 146, 16, 0, // Skip to: 7870 +/* 3628 */ MCD_OPC_Decode, 166, 8, 190, 1, // Opcode: AE_MULSF32R_LH +/* 3633 */ MCD_OPC_FilterValue, 128, 192, 4, 24, 0, 0, // Skip to: 3664 +/* 3640 */ MCD_OPC_CheckPredicate, 24, 129, 16, 0, // Skip to: 7870 +/* 3645 */ MCD_OPC_CheckField, 28, 2, 0, 122, 16, 0, // Skip to: 7870 +/* 3652 */ MCD_OPC_CheckField, 0, 16, 14, 115, 16, 0, // Skip to: 7870 +/* 3659 */ MCD_OPC_Decode, 167, 8, 190, 1, // Opcode: AE_MULSF32R_LL +/* 3664 */ MCD_OPC_FilterValue, 128, 196, 4, 24, 0, 0, // Skip to: 3695 +/* 3671 */ MCD_OPC_CheckPredicate, 24, 98, 16, 0, // Skip to: 7870 +/* 3676 */ MCD_OPC_CheckField, 28, 2, 0, 91, 16, 0, // Skip to: 7870 +/* 3683 */ MCD_OPC_CheckField, 0, 16, 14, 84, 16, 0, // Skip to: 7870 +/* 3690 */ MCD_OPC_Decode, 169, 8, 190, 1, // Opcode: AE_MULSF32S_HH +/* 3695 */ MCD_OPC_FilterValue, 128, 200, 4, 24, 0, 0, // Skip to: 3726 +/* 3702 */ MCD_OPC_CheckPredicate, 24, 67, 16, 0, // Skip to: 7870 +/* 3707 */ MCD_OPC_CheckField, 28, 2, 0, 60, 16, 0, // Skip to: 7870 +/* 3714 */ MCD_OPC_CheckField, 0, 16, 14, 53, 16, 0, // Skip to: 7870 +/* 3721 */ MCD_OPC_Decode, 170, 8, 190, 1, // Opcode: AE_MULSF32S_LH +/* 3726 */ MCD_OPC_FilterValue, 128, 204, 4, 24, 0, 0, // Skip to: 3757 +/* 3733 */ MCD_OPC_CheckPredicate, 24, 36, 16, 0, // Skip to: 7870 +/* 3738 */ MCD_OPC_CheckField, 28, 2, 0, 29, 16, 0, // Skip to: 7870 +/* 3745 */ MCD_OPC_CheckField, 0, 16, 14, 22, 16, 0, // Skip to: 7870 +/* 3752 */ MCD_OPC_Decode, 171, 8, 190, 1, // Opcode: AE_MULSF32S_LL +/* 3757 */ MCD_OPC_FilterValue, 128, 208, 4, 24, 0, 0, // Skip to: 3788 +/* 3764 */ MCD_OPC_CheckPredicate, 24, 5, 16, 0, // Skip to: 7870 +/* 3769 */ MCD_OPC_CheckField, 28, 2, 0, 254, 15, 0, // Skip to: 7870 +/* 3776 */ MCD_OPC_CheckField, 0, 16, 14, 247, 15, 0, // Skip to: 7870 +/* 3783 */ MCD_OPC_Decode, 172, 8, 190, 1, // Opcode: AE_MULSF32X16_H0 +/* 3788 */ MCD_OPC_FilterValue, 128, 212, 4, 24, 0, 0, // Skip to: 3819 +/* 3795 */ MCD_OPC_CheckPredicate, 24, 230, 15, 0, // Skip to: 7870 +/* 3800 */ MCD_OPC_CheckField, 28, 2, 0, 223, 15, 0, // Skip to: 7870 +/* 3807 */ MCD_OPC_CheckField, 0, 16, 14, 216, 15, 0, // Skip to: 7870 +/* 3814 */ MCD_OPC_Decode, 174, 8, 190, 1, // Opcode: AE_MULSF32X16_H1 +/* 3819 */ MCD_OPC_FilterValue, 128, 216, 4, 24, 0, 0, // Skip to: 3850 +/* 3826 */ MCD_OPC_CheckPredicate, 24, 199, 15, 0, // Skip to: 7870 +/* 3831 */ MCD_OPC_CheckField, 28, 2, 0, 192, 15, 0, // Skip to: 7870 +/* 3838 */ MCD_OPC_CheckField, 0, 16, 14, 185, 15, 0, // Skip to: 7870 +/* 3845 */ MCD_OPC_Decode, 176, 8, 190, 1, // Opcode: AE_MULSF32X16_H2 +/* 3850 */ MCD_OPC_FilterValue, 128, 220, 4, 24, 0, 0, // Skip to: 3881 +/* 3857 */ MCD_OPC_CheckPredicate, 24, 168, 15, 0, // Skip to: 7870 +/* 3862 */ MCD_OPC_CheckField, 28, 2, 0, 161, 15, 0, // Skip to: 7870 +/* 3869 */ MCD_OPC_CheckField, 0, 16, 14, 154, 15, 0, // Skip to: 7870 +/* 3876 */ MCD_OPC_Decode, 178, 8, 190, 1, // Opcode: AE_MULSF32X16_H3 +/* 3881 */ MCD_OPC_FilterValue, 128, 224, 4, 24, 0, 0, // Skip to: 3912 +/* 3888 */ MCD_OPC_CheckPredicate, 24, 137, 15, 0, // Skip to: 7870 +/* 3893 */ MCD_OPC_CheckField, 28, 2, 0, 130, 15, 0, // Skip to: 7870 +/* 3900 */ MCD_OPC_CheckField, 0, 16, 14, 123, 15, 0, // Skip to: 7870 +/* 3907 */ MCD_OPC_Decode, 180, 8, 190, 1, // Opcode: AE_MULSF32X16_L0 +/* 3912 */ MCD_OPC_FilterValue, 128, 228, 4, 24, 0, 0, // Skip to: 3943 +/* 3919 */ MCD_OPC_CheckPredicate, 24, 106, 15, 0, // Skip to: 7870 +/* 3924 */ MCD_OPC_CheckField, 28, 2, 0, 99, 15, 0, // Skip to: 7870 +/* 3931 */ MCD_OPC_CheckField, 0, 16, 14, 92, 15, 0, // Skip to: 7870 +/* 3938 */ MCD_OPC_Decode, 182, 8, 190, 1, // Opcode: AE_MULSF32X16_L1 +/* 3943 */ MCD_OPC_FilterValue, 128, 232, 4, 24, 0, 0, // Skip to: 3974 +/* 3950 */ MCD_OPC_CheckPredicate, 24, 75, 15, 0, // Skip to: 7870 +/* 3955 */ MCD_OPC_CheckField, 28, 2, 0, 68, 15, 0, // Skip to: 7870 +/* 3962 */ MCD_OPC_CheckField, 0, 16, 14, 61, 15, 0, // Skip to: 7870 +/* 3969 */ MCD_OPC_Decode, 184, 8, 190, 1, // Opcode: AE_MULSF32X16_L2 +/* 3974 */ MCD_OPC_FilterValue, 128, 236, 4, 24, 0, 0, // Skip to: 4005 +/* 3981 */ MCD_OPC_CheckPredicate, 24, 44, 15, 0, // Skip to: 7870 +/* 3986 */ MCD_OPC_CheckField, 28, 2, 0, 37, 15, 0, // Skip to: 7870 +/* 3993 */ MCD_OPC_CheckField, 0, 16, 14, 30, 15, 0, // Skip to: 7870 +/* 4000 */ MCD_OPC_Decode, 186, 8, 190, 1, // Opcode: AE_MULSF32X16_L3 +/* 4005 */ MCD_OPC_FilterValue, 128, 240, 4, 24, 0, 0, // Skip to: 4036 +/* 4012 */ MCD_OPC_CheckPredicate, 24, 13, 15, 0, // Skip to: 7870 +/* 4017 */ MCD_OPC_CheckField, 28, 2, 0, 6, 15, 0, // Skip to: 7870 +/* 4024 */ MCD_OPC_CheckField, 0, 16, 14, 255, 14, 0, // Skip to: 7870 +/* 4031 */ MCD_OPC_Decode, 188, 8, 190, 1, // Opcode: AE_MULSF48Q32SP16S_L +/* 4036 */ MCD_OPC_FilterValue, 128, 244, 4, 24, 0, 0, // Skip to: 4067 +/* 4043 */ MCD_OPC_CheckPredicate, 24, 238, 14, 0, // Skip to: 7870 +/* 4048 */ MCD_OPC_CheckField, 28, 2, 0, 231, 14, 0, // Skip to: 7870 +/* 4055 */ MCD_OPC_CheckField, 0, 16, 14, 224, 14, 0, // Skip to: 7870 +/* 4062 */ MCD_OPC_Decode, 190, 8, 190, 1, // Opcode: AE_MULSF48Q32SP16U_L +/* 4067 */ MCD_OPC_FilterValue, 128, 248, 4, 24, 0, 0, // Skip to: 4098 +/* 4074 */ MCD_OPC_CheckPredicate, 24, 207, 14, 0, // Skip to: 7870 +/* 4079 */ MCD_OPC_CheckField, 28, 2, 0, 200, 14, 0, // Skip to: 7870 +/* 4086 */ MCD_OPC_CheckField, 0, 16, 14, 193, 14, 0, // Skip to: 7870 +/* 4093 */ MCD_OPC_Decode, 192, 8, 190, 1, // Opcode: AE_MULSFP24X2R +/* 4098 */ MCD_OPC_FilterValue, 128, 252, 4, 24, 0, 0, // Skip to: 4129 +/* 4105 */ MCD_OPC_CheckPredicate, 24, 176, 14, 0, // Skip to: 7870 +/* 4110 */ MCD_OPC_CheckField, 28, 2, 0, 169, 14, 0, // Skip to: 7870 +/* 4117 */ MCD_OPC_CheckField, 0, 16, 14, 162, 14, 0, // Skip to: 7870 +/* 4124 */ MCD_OPC_Decode, 193, 8, 190, 1, // Opcode: AE_MULSFP24X2RA +/* 4129 */ MCD_OPC_FilterValue, 128, 128, 5, 24, 0, 0, // Skip to: 4160 +/* 4136 */ MCD_OPC_CheckPredicate, 24, 145, 14, 0, // Skip to: 7870 +/* 4141 */ MCD_OPC_CheckField, 28, 2, 0, 138, 14, 0, // Skip to: 7870 +/* 4148 */ MCD_OPC_CheckField, 0, 16, 14, 131, 14, 0, // Skip to: 7870 +/* 4155 */ MCD_OPC_Decode, 196, 8, 190, 1, // Opcode: AE_MULSFP32X16X2RAS_H +/* 4160 */ MCD_OPC_FilterValue, 128, 132, 5, 24, 0, 0, // Skip to: 4191 +/* 4167 */ MCD_OPC_CheckPredicate, 24, 114, 14, 0, // Skip to: 7870 +/* 4172 */ MCD_OPC_CheckField, 28, 2, 0, 107, 14, 0, // Skip to: 7870 +/* 4179 */ MCD_OPC_CheckField, 0, 16, 14, 100, 14, 0, // Skip to: 7870 +/* 4186 */ MCD_OPC_Decode, 198, 8, 190, 1, // Opcode: AE_MULSFP32X16X2RAS_L +/* 4191 */ MCD_OPC_FilterValue, 128, 136, 5, 24, 0, 0, // Skip to: 4222 +/* 4198 */ MCD_OPC_CheckPredicate, 24, 83, 14, 0, // Skip to: 7870 +/* 4203 */ MCD_OPC_CheckField, 28, 2, 0, 76, 14, 0, // Skip to: 7870 +/* 4210 */ MCD_OPC_CheckField, 0, 16, 14, 69, 14, 0, // Skip to: 7870 +/* 4217 */ MCD_OPC_Decode, 200, 8, 190, 1, // Opcode: AE_MULSFP32X16X2RS_H +/* 4222 */ MCD_OPC_FilterValue, 128, 140, 5, 24, 0, 0, // Skip to: 4253 +/* 4229 */ MCD_OPC_CheckPredicate, 24, 52, 14, 0, // Skip to: 7870 +/* 4234 */ MCD_OPC_CheckField, 28, 2, 0, 45, 14, 0, // Skip to: 7870 +/* 4241 */ MCD_OPC_CheckField, 0, 16, 14, 38, 14, 0, // Skip to: 7870 +/* 4248 */ MCD_OPC_Decode, 202, 8, 190, 1, // Opcode: AE_MULSFP32X16X2RS_L +/* 4253 */ MCD_OPC_FilterValue, 128, 152, 5, 24, 0, 0, // Skip to: 4284 +/* 4260 */ MCD_OPC_CheckPredicate, 24, 21, 14, 0, // Skip to: 7870 +/* 4265 */ MCD_OPC_CheckField, 28, 2, 0, 14, 14, 0, // Skip to: 7870 +/* 4272 */ MCD_OPC_CheckField, 0, 16, 14, 7, 14, 0, // Skip to: 7870 +/* 4279 */ MCD_OPC_Decode, 204, 8, 190, 1, // Opcode: AE_MULSFP32X2RAS +/* 4284 */ MCD_OPC_FilterValue, 128, 156, 5, 24, 0, 0, // Skip to: 4315 +/* 4291 */ MCD_OPC_CheckPredicate, 24, 246, 13, 0, // Skip to: 7870 +/* 4296 */ MCD_OPC_CheckField, 28, 2, 0, 239, 13, 0, // Skip to: 7870 +/* 4303 */ MCD_OPC_CheckField, 0, 16, 14, 232, 13, 0, // Skip to: 7870 +/* 4310 */ MCD_OPC_Decode, 205, 8, 190, 1, // Opcode: AE_MULSFP32X2RS +/* 4315 */ MCD_OPC_FilterValue, 128, 160, 5, 24, 0, 0, // Skip to: 4346 +/* 4322 */ MCD_OPC_CheckPredicate, 24, 215, 13, 0, // Skip to: 7870 +/* 4327 */ MCD_OPC_CheckField, 28, 2, 0, 208, 13, 0, // Skip to: 7870 +/* 4334 */ MCD_OPC_CheckField, 0, 16, 14, 201, 13, 0, // Skip to: 7870 +/* 4341 */ MCD_OPC_Decode, 210, 8, 190, 1, // Opcode: AE_MULSP32X16X2_H +/* 4346 */ MCD_OPC_FilterValue, 128, 164, 5, 24, 0, 0, // Skip to: 4377 +/* 4353 */ MCD_OPC_CheckPredicate, 24, 184, 13, 0, // Skip to: 7870 +/* 4358 */ MCD_OPC_CheckField, 28, 2, 0, 177, 13, 0, // Skip to: 7870 +/* 4365 */ MCD_OPC_CheckField, 0, 16, 14, 170, 13, 0, // Skip to: 7870 +/* 4372 */ MCD_OPC_Decode, 211, 8, 190, 1, // Opcode: AE_MULSP32X16X2_L +/* 4377 */ MCD_OPC_FilterValue, 128, 168, 5, 24, 0, 0, // Skip to: 4408 +/* 4384 */ MCD_OPC_CheckPredicate, 24, 153, 13, 0, // Skip to: 7870 +/* 4389 */ MCD_OPC_CheckField, 28, 2, 0, 146, 13, 0, // Skip to: 7870 +/* 4396 */ MCD_OPC_CheckField, 0, 16, 14, 139, 13, 0, // Skip to: 7870 +/* 4403 */ MCD_OPC_Decode, 212, 8, 190, 1, // Opcode: AE_MULSP32X2 +/* 4408 */ MCD_OPC_FilterValue, 128, 180, 5, 24, 0, 0, // Skip to: 4439 +/* 4415 */ MCD_OPC_CheckPredicate, 24, 122, 13, 0, // Skip to: 7870 +/* 4420 */ MCD_OPC_CheckField, 28, 2, 0, 115, 13, 0, // Skip to: 7870 +/* 4427 */ MCD_OPC_CheckField, 0, 16, 14, 108, 13, 0, // Skip to: 7870 +/* 4434 */ MCD_OPC_Decode, 217, 8, 190, 1, // Opcode: AE_MULSS32F48P16S_HH +/* 4439 */ MCD_OPC_FilterValue, 128, 184, 5, 24, 0, 0, // Skip to: 4470 +/* 4446 */ MCD_OPC_CheckPredicate, 24, 91, 13, 0, // Skip to: 7870 +/* 4451 */ MCD_OPC_CheckField, 28, 2, 0, 84, 13, 0, // Skip to: 7870 +/* 4458 */ MCD_OPC_CheckField, 0, 16, 14, 77, 13, 0, // Skip to: 7870 +/* 4465 */ MCD_OPC_Decode, 219, 8, 190, 1, // Opcode: AE_MULSS32F48P16S_LH +/* 4470 */ MCD_OPC_FilterValue, 128, 188, 5, 24, 0, 0, // Skip to: 4501 +/* 4477 */ MCD_OPC_CheckPredicate, 24, 60, 13, 0, // Skip to: 7870 +/* 4482 */ MCD_OPC_CheckField, 28, 2, 0, 53, 13, 0, // Skip to: 7870 +/* 4489 */ MCD_OPC_CheckField, 0, 16, 14, 46, 13, 0, // Skip to: 7870 +/* 4496 */ MCD_OPC_Decode, 221, 8, 190, 1, // Opcode: AE_MULSS32F48P16S_LL +/* 4501 */ MCD_OPC_FilterValue, 128, 192, 5, 24, 0, 0, // Skip to: 4532 +/* 4508 */ MCD_OPC_CheckPredicate, 24, 29, 13, 0, // Skip to: 7870 +/* 4513 */ MCD_OPC_CheckField, 28, 2, 0, 22, 13, 0, // Skip to: 7870 +/* 4520 */ MCD_OPC_CheckField, 0, 16, 14, 15, 13, 0, // Skip to: 7870 +/* 4527 */ MCD_OPC_Decode, 227, 8, 190, 1, // Opcode: AE_MULSSD32X16_H1_L0 +/* 4532 */ MCD_OPC_FilterValue, 128, 196, 5, 24, 0, 0, // Skip to: 4563 +/* 4539 */ MCD_OPC_CheckPredicate, 24, 254, 12, 0, // Skip to: 7870 +/* 4544 */ MCD_OPC_CheckField, 28, 2, 0, 247, 12, 0, // Skip to: 7870 +/* 4551 */ MCD_OPC_CheckField, 0, 16, 14, 240, 12, 0, // Skip to: 7870 +/* 4558 */ MCD_OPC_Decode, 229, 8, 190, 1, // Opcode: AE_MULSSD32X16_H3_L2 +/* 4563 */ MCD_OPC_FilterValue, 128, 208, 5, 24, 0, 0, // Skip to: 4594 +/* 4570 */ MCD_OPC_CheckPredicate, 24, 223, 12, 0, // Skip to: 7870 +/* 4575 */ MCD_OPC_CheckField, 28, 2, 0, 216, 12, 0, // Skip to: 7870 +/* 4582 */ MCD_OPC_CheckField, 0, 16, 14, 209, 12, 0, // Skip to: 7870 +/* 4589 */ MCD_OPC_Decode, 231, 8, 190, 1, // Opcode: AE_MULSSFD16SS_11_00 +/* 4594 */ MCD_OPC_FilterValue, 128, 212, 5, 24, 0, 0, // Skip to: 4625 +/* 4601 */ MCD_OPC_CheckPredicate, 24, 192, 12, 0, // Skip to: 7870 +/* 4606 */ MCD_OPC_CheckField, 28, 2, 0, 185, 12, 0, // Skip to: 7870 +/* 4613 */ MCD_OPC_CheckField, 0, 16, 14, 178, 12, 0, // Skip to: 7870 +/* 4620 */ MCD_OPC_Decode, 233, 8, 190, 1, // Opcode: AE_MULSSFD16SS_13_02 +/* 4625 */ MCD_OPC_FilterValue, 128, 216, 5, 24, 0, 0, // Skip to: 4656 +/* 4632 */ MCD_OPC_CheckPredicate, 24, 161, 12, 0, // Skip to: 7870 +/* 4637 */ MCD_OPC_CheckField, 28, 2, 0, 154, 12, 0, // Skip to: 7870 +/* 4644 */ MCD_OPC_CheckField, 0, 16, 14, 147, 12, 0, // Skip to: 7870 +/* 4651 */ MCD_OPC_Decode, 235, 8, 190, 1, // Opcode: AE_MULSSFD16SS_33_22 +/* 4656 */ MCD_OPC_FilterValue, 128, 236, 5, 24, 0, 0, // Skip to: 4687 +/* 4663 */ MCD_OPC_CheckPredicate, 24, 130, 12, 0, // Skip to: 7870 +/* 4668 */ MCD_OPC_CheckField, 28, 2, 0, 123, 12, 0, // Skip to: 7870 +/* 4675 */ MCD_OPC_CheckField, 0, 16, 14, 116, 12, 0, // Skip to: 7870 +/* 4682 */ MCD_OPC_Decode, 241, 8, 190, 1, // Opcode: AE_MULSSFD32X16_H1_L0 +/* 4687 */ MCD_OPC_FilterValue, 128, 240, 5, 24, 0, 0, // Skip to: 4718 +/* 4694 */ MCD_OPC_CheckPredicate, 24, 99, 12, 0, // Skip to: 7870 +/* 4699 */ MCD_OPC_CheckField, 28, 2, 0, 92, 12, 0, // Skip to: 7870 +/* 4706 */ MCD_OPC_CheckField, 0, 16, 14, 85, 12, 0, // Skip to: 7870 +/* 4713 */ MCD_OPC_Decode, 243, 8, 190, 1, // Opcode: AE_MULSSFD32X16_H3_L2 +/* 4718 */ MCD_OPC_FilterValue, 128, 248, 5, 24, 0, 0, // Skip to: 4749 +/* 4725 */ MCD_OPC_CheckPredicate, 24, 68, 12, 0, // Skip to: 7870 +/* 4730 */ MCD_OPC_CheckField, 28, 2, 0, 61, 12, 0, // Skip to: 7870 +/* 4737 */ MCD_OPC_CheckField, 0, 16, 14, 54, 12, 0, // Skip to: 7870 +/* 4744 */ MCD_OPC_Decode, 249, 8, 189, 1, // Opcode: AE_MULZAAD32X16_H0_L1 +/* 4749 */ MCD_OPC_FilterValue, 128, 252, 5, 24, 0, 0, // Skip to: 4780 +/* 4756 */ MCD_OPC_CheckPredicate, 24, 37, 12, 0, // Skip to: 7870 +/* 4761 */ MCD_OPC_CheckField, 28, 2, 0, 30, 12, 0, // Skip to: 7870 +/* 4768 */ MCD_OPC_CheckField, 0, 16, 14, 23, 12, 0, // Skip to: 7870 +/* 4775 */ MCD_OPC_Decode, 251, 8, 189, 1, // Opcode: AE_MULZAAD32X16_H1_L0 +/* 4780 */ MCD_OPC_FilterValue, 128, 128, 6, 24, 0, 0, // Skip to: 4811 +/* 4787 */ MCD_OPC_CheckPredicate, 24, 6, 12, 0, // Skip to: 7870 +/* 4792 */ MCD_OPC_CheckField, 28, 2, 0, 255, 11, 0, // Skip to: 7870 +/* 4799 */ MCD_OPC_CheckField, 0, 16, 14, 248, 11, 0, // Skip to: 7870 +/* 4806 */ MCD_OPC_Decode, 253, 8, 189, 1, // Opcode: AE_MULZAAD32X16_H2_L3 +/* 4811 */ MCD_OPC_FilterValue, 128, 132, 6, 24, 0, 0, // Skip to: 4842 +/* 4818 */ MCD_OPC_CheckPredicate, 24, 231, 11, 0, // Skip to: 7870 +/* 4823 */ MCD_OPC_CheckField, 28, 2, 0, 224, 11, 0, // Skip to: 7870 +/* 4830 */ MCD_OPC_CheckField, 0, 16, 14, 217, 11, 0, // Skip to: 7870 +/* 4837 */ MCD_OPC_Decode, 255, 8, 189, 1, // Opcode: AE_MULZAAD32X16_H3_L2 +/* 4842 */ MCD_OPC_FilterValue, 128, 144, 6, 24, 0, 0, // Skip to: 4873 +/* 4849 */ MCD_OPC_CheckPredicate, 24, 200, 11, 0, // Skip to: 7870 +/* 4854 */ MCD_OPC_CheckField, 28, 2, 0, 193, 11, 0, // Skip to: 7870 +/* 4861 */ MCD_OPC_CheckField, 0, 16, 14, 186, 11, 0, // Skip to: 7870 +/* 4868 */ MCD_OPC_Decode, 129, 9, 189, 1, // Opcode: AE_MULZAAFD16SS_11_00 +/* 4873 */ MCD_OPC_FilterValue, 128, 148, 6, 24, 0, 0, // Skip to: 4904 +/* 4880 */ MCD_OPC_CheckPredicate, 24, 169, 11, 0, // Skip to: 7870 +/* 4885 */ MCD_OPC_CheckField, 28, 2, 0, 162, 11, 0, // Skip to: 7870 +/* 4892 */ MCD_OPC_CheckField, 0, 16, 14, 155, 11, 0, // Skip to: 7870 +/* 4899 */ MCD_OPC_Decode, 131, 9, 189, 1, // Opcode: AE_MULZAAFD16SS_13_02 +/* 4904 */ MCD_OPC_FilterValue, 128, 152, 6, 24, 0, 0, // Skip to: 4935 +/* 4911 */ MCD_OPC_CheckPredicate, 24, 138, 11, 0, // Skip to: 7870 +/* 4916 */ MCD_OPC_CheckField, 28, 2, 0, 131, 11, 0, // Skip to: 7870 +/* 4923 */ MCD_OPC_CheckField, 0, 16, 14, 124, 11, 0, // Skip to: 7870 +/* 4930 */ MCD_OPC_Decode, 133, 9, 189, 1, // Opcode: AE_MULZAAFD16SS_33_22 +/* 4935 */ MCD_OPC_FilterValue, 128, 172, 6, 24, 0, 0, // Skip to: 4966 +/* 4942 */ MCD_OPC_CheckPredicate, 24, 107, 11, 0, // Skip to: 7870 +/* 4947 */ MCD_OPC_CheckField, 28, 2, 0, 100, 11, 0, // Skip to: 7870 +/* 4954 */ MCD_OPC_CheckField, 0, 16, 14, 93, 11, 0, // Skip to: 7870 +/* 4961 */ MCD_OPC_Decode, 139, 9, 189, 1, // Opcode: AE_MULZAAFD32X16_H0_L1 +/* 4966 */ MCD_OPC_FilterValue, 128, 176, 6, 24, 0, 0, // Skip to: 4997 +/* 4973 */ MCD_OPC_CheckPredicate, 24, 76, 11, 0, // Skip to: 7870 +/* 4978 */ MCD_OPC_CheckField, 28, 2, 0, 69, 11, 0, // Skip to: 7870 +/* 4985 */ MCD_OPC_CheckField, 0, 16, 14, 62, 11, 0, // Skip to: 7870 +/* 4992 */ MCD_OPC_Decode, 141, 9, 189, 1, // Opcode: AE_MULZAAFD32X16_H1_L0 +/* 4997 */ MCD_OPC_FilterValue, 128, 180, 6, 24, 0, 0, // Skip to: 5028 +/* 5004 */ MCD_OPC_CheckPredicate, 24, 45, 11, 0, // Skip to: 7870 +/* 5009 */ MCD_OPC_CheckField, 28, 2, 0, 38, 11, 0, // Skip to: 7870 +/* 5016 */ MCD_OPC_CheckField, 0, 16, 14, 31, 11, 0, // Skip to: 7870 +/* 5023 */ MCD_OPC_Decode, 143, 9, 189, 1, // Opcode: AE_MULZAAFD32X16_H2_L3 +/* 5028 */ MCD_OPC_FilterValue, 128, 184, 6, 24, 0, 0, // Skip to: 5059 +/* 5035 */ MCD_OPC_CheckPredicate, 24, 14, 11, 0, // Skip to: 7870 +/* 5040 */ MCD_OPC_CheckField, 28, 2, 0, 7, 11, 0, // Skip to: 7870 +/* 5047 */ MCD_OPC_CheckField, 0, 16, 14, 0, 11, 0, // Skip to: 7870 +/* 5054 */ MCD_OPC_Decode, 145, 9, 189, 1, // Opcode: AE_MULZAAFD32X16_H3_L2 +/* 5059 */ MCD_OPC_FilterValue, 128, 188, 6, 24, 0, 0, // Skip to: 5090 +/* 5066 */ MCD_OPC_CheckPredicate, 24, 239, 10, 0, // Skip to: 7870 +/* 5071 */ MCD_OPC_CheckField, 28, 2, 0, 232, 10, 0, // Skip to: 7870 +/* 5078 */ MCD_OPC_CheckField, 0, 16, 14, 225, 10, 0, // Skip to: 7870 +/* 5085 */ MCD_OPC_Decode, 151, 9, 189, 1, // Opcode: AE_MULZASD32X16_H1_L0 +/* 5090 */ MCD_OPC_FilterValue, 128, 192, 6, 24, 0, 0, // Skip to: 5121 +/* 5097 */ MCD_OPC_CheckPredicate, 24, 208, 10, 0, // Skip to: 7870 +/* 5102 */ MCD_OPC_CheckField, 28, 2, 0, 201, 10, 0, // Skip to: 7870 +/* 5109 */ MCD_OPC_CheckField, 0, 16, 14, 194, 10, 0, // Skip to: 7870 +/* 5116 */ MCD_OPC_Decode, 153, 9, 189, 1, // Opcode: AE_MULZASD32X16_H3_L2 +/* 5121 */ MCD_OPC_FilterValue, 128, 220, 6, 24, 0, 0, // Skip to: 5152 +/* 5128 */ MCD_OPC_CheckPredicate, 24, 177, 10, 0, // Skip to: 7870 +/* 5133 */ MCD_OPC_CheckField, 28, 2, 0, 170, 10, 0, // Skip to: 7870 +/* 5140 */ MCD_OPC_CheckField, 0, 16, 14, 163, 10, 0, // Skip to: 7870 +/* 5147 */ MCD_OPC_Decode, 159, 9, 189, 1, // Opcode: AE_MULZASFD32X16_H1_L0 +/* 5152 */ MCD_OPC_FilterValue, 128, 224, 6, 24, 0, 0, // Skip to: 5183 +/* 5159 */ MCD_OPC_CheckPredicate, 24, 146, 10, 0, // Skip to: 7870 +/* 5164 */ MCD_OPC_CheckField, 28, 2, 0, 139, 10, 0, // Skip to: 7870 +/* 5171 */ MCD_OPC_CheckField, 0, 16, 14, 132, 10, 0, // Skip to: 7870 +/* 5178 */ MCD_OPC_Decode, 161, 9, 189, 1, // Opcode: AE_MULZASFD32X16_H3_L2 +/* 5183 */ MCD_OPC_FilterValue, 128, 240, 6, 24, 0, 0, // Skip to: 5214 +/* 5190 */ MCD_OPC_CheckPredicate, 24, 115, 10, 0, // Skip to: 7870 +/* 5195 */ MCD_OPC_CheckField, 28, 2, 0, 108, 10, 0, // Skip to: 7870 +/* 5202 */ MCD_OPC_CheckField, 0, 16, 14, 101, 10, 0, // Skip to: 7870 +/* 5209 */ MCD_OPC_Decode, 171, 9, 189, 1, // Opcode: AE_MULZSAFD32X16_H1_L0 +/* 5214 */ MCD_OPC_FilterValue, 128, 244, 6, 24, 0, 0, // Skip to: 5245 +/* 5221 */ MCD_OPC_CheckPredicate, 24, 84, 10, 0, // Skip to: 7870 +/* 5226 */ MCD_OPC_CheckField, 28, 2, 0, 77, 10, 0, // Skip to: 7870 +/* 5233 */ MCD_OPC_CheckField, 0, 16, 14, 70, 10, 0, // Skip to: 7870 +/* 5240 */ MCD_OPC_Decode, 173, 9, 189, 1, // Opcode: AE_MULZSAFD32X16_H3_L2 +/* 5245 */ MCD_OPC_FilterValue, 128, 248, 6, 24, 0, 0, // Skip to: 5276 +/* 5252 */ MCD_OPC_CheckPredicate, 24, 53, 10, 0, // Skip to: 7870 +/* 5257 */ MCD_OPC_CheckField, 28, 2, 0, 46, 10, 0, // Skip to: 7870 +/* 5264 */ MCD_OPC_CheckField, 0, 16, 14, 39, 10, 0, // Skip to: 7870 +/* 5271 */ MCD_OPC_Decode, 179, 9, 189, 1, // Opcode: AE_MULZSSD32X16_H1_L0 +/* 5276 */ MCD_OPC_FilterValue, 128, 252, 6, 24, 0, 0, // Skip to: 5307 +/* 5283 */ MCD_OPC_CheckPredicate, 24, 22, 10, 0, // Skip to: 7870 +/* 5288 */ MCD_OPC_CheckField, 28, 2, 0, 15, 10, 0, // Skip to: 7870 +/* 5295 */ MCD_OPC_CheckField, 0, 16, 14, 8, 10, 0, // Skip to: 7870 +/* 5302 */ MCD_OPC_Decode, 181, 9, 189, 1, // Opcode: AE_MULZSSD32X16_H3_L2 +/* 5307 */ MCD_OPC_FilterValue, 128, 136, 7, 24, 0, 0, // Skip to: 5338 +/* 5314 */ MCD_OPC_CheckPredicate, 24, 247, 9, 0, // Skip to: 7870 +/* 5319 */ MCD_OPC_CheckField, 28, 2, 0, 240, 9, 0, // Skip to: 7870 +/* 5326 */ MCD_OPC_CheckField, 0, 16, 14, 233, 9, 0, // Skip to: 7870 +/* 5333 */ MCD_OPC_Decode, 183, 9, 189, 1, // Opcode: AE_MULZSSFD16SS_11_00 +/* 5338 */ MCD_OPC_FilterValue, 128, 140, 7, 24, 0, 0, // Skip to: 5369 +/* 5345 */ MCD_OPC_CheckPredicate, 24, 216, 9, 0, // Skip to: 7870 +/* 5350 */ MCD_OPC_CheckField, 28, 2, 0, 209, 9, 0, // Skip to: 7870 +/* 5357 */ MCD_OPC_CheckField, 0, 16, 14, 202, 9, 0, // Skip to: 7870 +/* 5364 */ MCD_OPC_Decode, 185, 9, 189, 1, // Opcode: AE_MULZSSFD16SS_13_02 +/* 5369 */ MCD_OPC_FilterValue, 128, 144, 7, 24, 0, 0, // Skip to: 5400 +/* 5376 */ MCD_OPC_CheckPredicate, 24, 185, 9, 0, // Skip to: 7870 +/* 5381 */ MCD_OPC_CheckField, 28, 2, 0, 178, 9, 0, // Skip to: 7870 +/* 5388 */ MCD_OPC_CheckField, 0, 16, 14, 171, 9, 0, // Skip to: 7870 +/* 5395 */ MCD_OPC_Decode, 187, 9, 189, 1, // Opcode: AE_MULZSSFD16SS_33_22 +/* 5400 */ MCD_OPC_FilterValue, 128, 164, 7, 24, 0, 0, // Skip to: 5431 +/* 5407 */ MCD_OPC_CheckPredicate, 24, 154, 9, 0, // Skip to: 7870 +/* 5412 */ MCD_OPC_CheckField, 28, 2, 0, 147, 9, 0, // Skip to: 7870 +/* 5419 */ MCD_OPC_CheckField, 0, 16, 14, 140, 9, 0, // Skip to: 7870 +/* 5426 */ MCD_OPC_Decode, 193, 9, 189, 1, // Opcode: AE_MULZSSFD32X16_H1_L0 +/* 5431 */ MCD_OPC_FilterValue, 128, 168, 7, 24, 0, 0, // Skip to: 5462 +/* 5438 */ MCD_OPC_CheckPredicate, 24, 123, 9, 0, // Skip to: 7870 +/* 5443 */ MCD_OPC_CheckField, 28, 2, 0, 116, 9, 0, // Skip to: 7870 +/* 5450 */ MCD_OPC_CheckField, 0, 16, 14, 109, 9, 0, // Skip to: 7870 +/* 5457 */ MCD_OPC_Decode, 195, 9, 189, 1, // Opcode: AE_MULZSSFD32X16_H3_L2 +/* 5462 */ MCD_OPC_FilterValue, 128, 176, 7, 24, 0, 0, // Skip to: 5493 +/* 5469 */ MCD_OPC_CheckPredicate, 24, 92, 9, 0, // Skip to: 7870 +/* 5474 */ MCD_OPC_CheckField, 28, 2, 0, 85, 9, 0, // Skip to: 7870 +/* 5481 */ MCD_OPC_CheckField, 0, 16, 14, 78, 9, 0, // Skip to: 7870 +/* 5488 */ MCD_OPC_Decode, 193, 6, 191, 1, // Opcode: AE_MULAC32X16_H +/* 5493 */ MCD_OPC_FilterValue, 128, 180, 7, 24, 0, 0, // Skip to: 5524 +/* 5500 */ MCD_OPC_CheckPredicate, 24, 61, 9, 0, // Skip to: 7870 +/* 5505 */ MCD_OPC_CheckField, 28, 2, 0, 54, 9, 0, // Skip to: 7870 +/* 5512 */ MCD_OPC_CheckField, 0, 16, 14, 47, 9, 0, // Skip to: 7870 +/* 5519 */ MCD_OPC_Decode, 194, 6, 191, 1, // Opcode: AE_MULAC32X16_L +/* 5524 */ MCD_OPC_FilterValue, 128, 184, 7, 24, 0, 0, // Skip to: 5555 +/* 5531 */ MCD_OPC_CheckPredicate, 24, 30, 9, 0, // Skip to: 7870 +/* 5536 */ MCD_OPC_CheckField, 28, 2, 0, 23, 9, 0, // Skip to: 7870 +/* 5543 */ MCD_OPC_CheckField, 0, 16, 14, 16, 9, 0, // Skip to: 7870 +/* 5550 */ MCD_OPC_Decode, 235, 6, 191, 1, // Opcode: AE_MULAFC24RA +/* 5555 */ MCD_OPC_FilterValue, 128, 192, 7, 24, 0, 0, // Skip to: 5586 +/* 5562 */ MCD_OPC_CheckPredicate, 24, 255, 8, 0, // Skip to: 7870 +/* 5567 */ MCD_OPC_CheckField, 28, 2, 0, 248, 8, 0, // Skip to: 7870 +/* 5574 */ MCD_OPC_CheckField, 0, 16, 14, 241, 8, 0, // Skip to: 7870 +/* 5581 */ MCD_OPC_Decode, 236, 6, 191, 1, // Opcode: AE_MULAFC32X16RAS_H +/* 5586 */ MCD_OPC_FilterValue, 128, 196, 7, 24, 0, 0, // Skip to: 5617 +/* 5593 */ MCD_OPC_CheckPredicate, 24, 224, 8, 0, // Skip to: 7870 +/* 5598 */ MCD_OPC_CheckField, 28, 2, 0, 217, 8, 0, // Skip to: 7870 +/* 5605 */ MCD_OPC_CheckField, 0, 16, 14, 210, 8, 0, // Skip to: 7870 +/* 5612 */ MCD_OPC_Decode, 237, 6, 191, 1, // Opcode: AE_MULAFC32X16RAS_L +/* 5617 */ MCD_OPC_FilterValue, 128, 204, 7, 24, 0, 0, // Skip to: 5648 +/* 5624 */ MCD_OPC_CheckPredicate, 24, 193, 8, 0, // Skip to: 7870 +/* 5629 */ MCD_OPC_CheckField, 28, 2, 0, 186, 8, 0, // Skip to: 7870 +/* 5636 */ MCD_OPC_CheckField, 0, 16, 14, 179, 8, 0, // Skip to: 7870 +/* 5643 */ MCD_OPC_Decode, 164, 7, 192, 1, // Opcode: AE_MULC32X16_H +/* 5648 */ MCD_OPC_FilterValue, 128, 208, 7, 24, 0, 0, // Skip to: 5679 +/* 5655 */ MCD_OPC_CheckPredicate, 24, 162, 8, 0, // Skip to: 7870 +/* 5660 */ MCD_OPC_CheckField, 28, 2, 0, 155, 8, 0, // Skip to: 7870 +/* 5667 */ MCD_OPC_CheckField, 0, 16, 14, 148, 8, 0, // Skip to: 7870 +/* 5674 */ MCD_OPC_Decode, 165, 7, 192, 1, // Opcode: AE_MULC32X16_L +/* 5679 */ MCD_OPC_FilterValue, 128, 212, 7, 24, 0, 0, // Skip to: 5710 +/* 5686 */ MCD_OPC_CheckPredicate, 24, 131, 8, 0, // Skip to: 7870 +/* 5691 */ MCD_OPC_CheckField, 28, 2, 0, 124, 8, 0, // Skip to: 7870 +/* 5698 */ MCD_OPC_CheckField, 0, 16, 14, 117, 8, 0, // Skip to: 7870 +/* 5705 */ MCD_OPC_Decode, 206, 7, 192, 1, // Opcode: AE_MULFC24RA +/* 5710 */ MCD_OPC_FilterValue, 128, 220, 7, 24, 0, 0, // Skip to: 5741 +/* 5717 */ MCD_OPC_CheckPredicate, 24, 100, 8, 0, // Skip to: 7870 +/* 5722 */ MCD_OPC_CheckField, 28, 2, 0, 93, 8, 0, // Skip to: 7870 +/* 5729 */ MCD_OPC_CheckField, 0, 16, 14, 86, 8, 0, // Skip to: 7870 +/* 5736 */ MCD_OPC_Decode, 207, 7, 192, 1, // Opcode: AE_MULFC32X16RAS_H +/* 5741 */ MCD_OPC_FilterValue, 128, 224, 7, 24, 0, 0, // Skip to: 5772 +/* 5748 */ MCD_OPC_CheckPredicate, 24, 69, 8, 0, // Skip to: 7870 +/* 5753 */ MCD_OPC_CheckField, 28, 2, 0, 62, 8, 0, // Skip to: 7870 +/* 5760 */ MCD_OPC_CheckField, 0, 16, 14, 55, 8, 0, // Skip to: 7870 +/* 5767 */ MCD_OPC_Decode, 208, 7, 192, 1, // Opcode: AE_MULFC32X16RAS_L +/* 5772 */ MCD_OPC_FilterValue, 246, 128, 12, 25, 0, 0, // Skip to: 5804 +/* 5779 */ MCD_OPC_CheckPredicate, 24, 38, 8, 0, // Skip to: 7870 +/* 5784 */ MCD_OPC_CheckField, 16, 14, 128, 96, 30, 8, 0, // Skip to: 7870 +/* 5792 */ MCD_OPC_CheckField, 0, 4, 14, 23, 8, 0, // Skip to: 7870 +/* 5799 */ MCD_OPC_Decode, 251, 4, 153, 1, // Opcode: AE_L16M_X +/* 5804 */ MCD_OPC_FilterValue, 247, 128, 12, 48, 0, 0, // Skip to: 5859 +/* 5811 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 5814 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5836 +/* 5819 */ MCD_OPC_CheckPredicate, 24, 254, 7, 0, // Skip to: 7870 +/* 5824 */ MCD_OPC_CheckField, 0, 4, 14, 247, 7, 0, // Skip to: 7870 +/* 5831 */ MCD_OPC_Decode, 252, 4, 185, 1, // Opcode: AE_L16M_XC +/* 5836 */ MCD_OPC_FilterValue, 128, 96, 236, 7, 0, // Skip to: 7870 +/* 5842 */ MCD_OPC_CheckPredicate, 24, 231, 7, 0, // Skip to: 7870 +/* 5847 */ MCD_OPC_CheckField, 0, 4, 14, 224, 7, 0, // Skip to: 7870 +/* 5854 */ MCD_OPC_Decode, 129, 5, 185, 1, // Opcode: AE_L16X2M_XC +/* 5859 */ MCD_OPC_FilterValue, 248, 128, 12, 49, 0, 0, // Skip to: 5915 +/* 5866 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 5869 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 5892 +/* 5875 */ MCD_OPC_CheckPredicate, 24, 198, 7, 0, // Skip to: 7870 +/* 5880 */ MCD_OPC_CheckField, 0, 4, 14, 191, 7, 0, // Skip to: 7870 +/* 5887 */ MCD_OPC_Decode, 135, 5, 153, 1, // Opcode: AE_L16X4_X +/* 5892 */ MCD_OPC_FilterValue, 128, 64, 180, 7, 0, // Skip to: 7870 +/* 5898 */ MCD_OPC_CheckPredicate, 24, 175, 7, 0, // Skip to: 7870 +/* 5903 */ MCD_OPC_CheckField, 0, 4, 14, 168, 7, 0, // Skip to: 7870 +/* 5910 */ MCD_OPC_Decode, 136, 5, 185, 1, // Opcode: AE_L16X4_XC +/* 5915 */ MCD_OPC_FilterValue, 249, 128, 12, 94, 0, 0, // Skip to: 6016 +/* 5922 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 5925 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5947 +/* 5930 */ MCD_OPC_CheckPredicate, 24, 143, 7, 0, // Skip to: 7870 +/* 5935 */ MCD_OPC_CheckField, 0, 4, 14, 136, 7, 0, // Skip to: 7870 +/* 5942 */ MCD_OPC_Decode, 140, 5, 153, 1, // Opcode: AE_L16_X +/* 5947 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 5970 +/* 5953 */ MCD_OPC_CheckPredicate, 24, 120, 7, 0, // Skip to: 7870 +/* 5958 */ MCD_OPC_CheckField, 0, 4, 14, 113, 7, 0, // Skip to: 7870 +/* 5965 */ MCD_OPC_Decode, 141, 5, 185, 1, // Opcode: AE_L16_XC +/* 5970 */ MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 5993 +/* 5976 */ MCD_OPC_CheckPredicate, 24, 97, 7, 0, // Skip to: 7870 +/* 5981 */ MCD_OPC_CheckField, 0, 4, 14, 90, 7, 0, // Skip to: 7870 +/* 5988 */ MCD_OPC_Decode, 142, 5, 185, 1, // Opcode: AE_L16_XP +/* 5993 */ MCD_OPC_FilterValue, 128, 96, 79, 7, 0, // Skip to: 7870 +/* 5999 */ MCD_OPC_CheckPredicate, 24, 74, 7, 0, // Skip to: 7870 +/* 6004 */ MCD_OPC_CheckField, 0, 4, 14, 67, 7, 0, // Skip to: 7870 +/* 6011 */ MCD_OPC_Decode, 145, 5, 153, 1, // Opcode: AE_L32F24_X +/* 6016 */ MCD_OPC_FilterValue, 250, 128, 12, 49, 0, 0, // Skip to: 6072 +/* 6023 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6026 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6049 +/* 6032 */ MCD_OPC_CheckPredicate, 24, 41, 7, 0, // Skip to: 7870 +/* 6037 */ MCD_OPC_CheckField, 0, 4, 14, 34, 7, 0, // Skip to: 7870 +/* 6044 */ MCD_OPC_Decode, 147, 5, 185, 1, // Opcode: AE_L32F24_XP +/* 6049 */ MCD_OPC_FilterValue, 128, 96, 23, 7, 0, // Skip to: 7870 +/* 6055 */ MCD_OPC_CheckPredicate, 24, 18, 7, 0, // Skip to: 7870 +/* 6060 */ MCD_OPC_CheckField, 0, 4, 14, 11, 7, 0, // Skip to: 7870 +/* 6067 */ MCD_OPC_Decode, 151, 5, 185, 1, // Opcode: AE_L32M_XC +/* 6072 */ MCD_OPC_FilterValue, 253, 128, 12, 72, 0, 0, // Skip to: 6151 +/* 6079 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6082 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6105 +/* 6088 */ MCD_OPC_CheckPredicate, 24, 241, 6, 0, // Skip to: 7870 +/* 6093 */ MCD_OPC_CheckField, 0, 4, 14, 234, 6, 0, // Skip to: 7870 +/* 6100 */ MCD_OPC_Decode, 171, 5, 185, 1, // Opcode: AE_L32_XP +/* 6105 */ MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 6128 +/* 6111 */ MCD_OPC_CheckPredicate, 24, 218, 6, 0, // Skip to: 7870 +/* 6116 */ MCD_OPC_CheckField, 0, 4, 14, 211, 6, 0, // Skip to: 7870 +/* 6123 */ MCD_OPC_Decode, 174, 5, 153, 1, // Opcode: AE_L64_X +/* 6128 */ MCD_OPC_FilterValue, 128, 96, 200, 6, 0, // Skip to: 7870 +/* 6134 */ MCD_OPC_CheckPredicate, 24, 195, 6, 0, // Skip to: 7870 +/* 6139 */ MCD_OPC_CheckField, 0, 4, 14, 188, 6, 0, // Skip to: 7870 +/* 6146 */ MCD_OPC_Decode, 175, 5, 185, 1, // Opcode: AE_L64_XC +/* 6151 */ MCD_OPC_FilterValue, 254, 128, 12, 71, 0, 0, // Skip to: 6229 +/* 6158 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6161 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6183 +/* 6166 */ MCD_OPC_CheckPredicate, 24, 163, 6, 0, // Skip to: 7870 +/* 6171 */ MCD_OPC_CheckField, 0, 4, 14, 156, 6, 0, // Skip to: 7870 +/* 6178 */ MCD_OPC_Decode, 176, 5, 185, 1, // Opcode: AE_L64_XP +/* 6183 */ MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 6206 +/* 6189 */ MCD_OPC_CheckPredicate, 24, 140, 6, 0, // Skip to: 7870 +/* 6194 */ MCD_OPC_CheckField, 0, 4, 14, 133, 6, 0, // Skip to: 7870 +/* 6201 */ MCD_OPC_Decode, 227, 9, 148, 1, // Opcode: AE_S16M_L_XC +/* 6206 */ MCD_OPC_FilterValue, 128, 96, 122, 6, 0, // Skip to: 7870 +/* 6212 */ MCD_OPC_CheckPredicate, 24, 117, 6, 0, // Skip to: 7870 +/* 6217 */ MCD_OPC_CheckField, 0, 4, 14, 110, 6, 0, // Skip to: 7870 +/* 6224 */ MCD_OPC_Decode, 228, 9, 148, 1, // Opcode: AE_S16M_L_XU +/* 6229 */ MCD_OPC_FilterValue, 255, 128, 12, 49, 0, 0, // Skip to: 6285 +/* 6236 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6239 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6262 +/* 6245 */ MCD_OPC_CheckPredicate, 24, 84, 6, 0, // Skip to: 7870 +/* 6250 */ MCD_OPC_CheckField, 0, 4, 14, 77, 6, 0, // Skip to: 7870 +/* 6257 */ MCD_OPC_Decode, 232, 9, 148, 1, // Opcode: AE_S16X2M_XC +/* 6262 */ MCD_OPC_FilterValue, 128, 96, 66, 6, 0, // Skip to: 7870 +/* 6268 */ MCD_OPC_CheckPredicate, 24, 61, 6, 0, // Skip to: 7870 +/* 6273 */ MCD_OPC_CheckField, 0, 4, 14, 54, 6, 0, // Skip to: 7870 +/* 6280 */ MCD_OPC_Decode, 238, 9, 153, 1, // Opcode: AE_S16X4_X +/* 6285 */ MCD_OPC_FilterValue, 128, 129, 12, 94, 0, 0, // Skip to: 6386 +/* 6292 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6295 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6317 +/* 6300 */ MCD_OPC_CheckPredicate, 24, 29, 6, 0, // Skip to: 7870 +/* 6305 */ MCD_OPC_CheckField, 0, 4, 14, 22, 6, 0, // Skip to: 7870 +/* 6312 */ MCD_OPC_Decode, 239, 9, 148, 1, // Opcode: AE_S16X4_XC +/* 6317 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6340 +/* 6323 */ MCD_OPC_CheckPredicate, 24, 6, 6, 0, // Skip to: 7870 +/* 6328 */ MCD_OPC_CheckField, 0, 4, 14, 255, 5, 0, // Skip to: 7870 +/* 6335 */ MCD_OPC_Decode, 240, 9, 148, 1, // Opcode: AE_S16X4_XP +/* 6340 */ MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 6363 +/* 6346 */ MCD_OPC_CheckPredicate, 24, 239, 5, 0, // Skip to: 7870 +/* 6351 */ MCD_OPC_CheckField, 0, 4, 14, 232, 5, 0, // Skip to: 7870 +/* 6358 */ MCD_OPC_Decode, 243, 9, 153, 1, // Opcode: AE_S16_0_X +/* 6363 */ MCD_OPC_FilterValue, 128, 96, 221, 5, 0, // Skip to: 7870 +/* 6369 */ MCD_OPC_CheckPredicate, 24, 216, 5, 0, // Skip to: 7870 +/* 6374 */ MCD_OPC_CheckField, 0, 4, 14, 209, 5, 0, // Skip to: 7870 +/* 6381 */ MCD_OPC_Decode, 244, 9, 148, 1, // Opcode: AE_S16_0_XC +/* 6386 */ MCD_OPC_FilterValue, 129, 129, 12, 49, 0, 0, // Skip to: 6442 +/* 6393 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6396 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6419 +/* 6402 */ MCD_OPC_CheckPredicate, 24, 183, 5, 0, // Skip to: 7870 +/* 6407 */ MCD_OPC_CheckField, 0, 4, 14, 176, 5, 0, // Skip to: 7870 +/* 6414 */ MCD_OPC_Decode, 248, 9, 153, 1, // Opcode: AE_S24RA64S_X +/* 6419 */ MCD_OPC_FilterValue, 128, 64, 165, 5, 0, // Skip to: 7870 +/* 6425 */ MCD_OPC_CheckPredicate, 24, 160, 5, 0, // Skip to: 7870 +/* 6430 */ MCD_OPC_CheckField, 0, 4, 14, 153, 5, 0, // Skip to: 7870 +/* 6437 */ MCD_OPC_Decode, 249, 9, 148, 1, // Opcode: AE_S24RA64S_XC +/* 6442 */ MCD_OPC_FilterValue, 130, 129, 12, 71, 0, 0, // Skip to: 6520 +/* 6449 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6452 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6474 +/* 6457 */ MCD_OPC_CheckPredicate, 24, 128, 5, 0, // Skip to: 7870 +/* 6462 */ MCD_OPC_CheckField, 0, 4, 14, 121, 5, 0, // Skip to: 7870 +/* 6469 */ MCD_OPC_Decode, 254, 9, 153, 1, // Opcode: AE_S32F24_L_X +/* 6474 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6497 +/* 6480 */ MCD_OPC_CheckPredicate, 24, 105, 5, 0, // Skip to: 7870 +/* 6485 */ MCD_OPC_CheckField, 0, 4, 14, 98, 5, 0, // Skip to: 7870 +/* 6492 */ MCD_OPC_Decode, 255, 9, 148, 1, // Opcode: AE_S32F24_L_XC +/* 6497 */ MCD_OPC_FilterValue, 128, 64, 87, 5, 0, // Skip to: 7870 +/* 6503 */ MCD_OPC_CheckPredicate, 24, 82, 5, 0, // Skip to: 7870 +/* 6508 */ MCD_OPC_CheckField, 0, 4, 14, 75, 5, 0, // Skip to: 7870 +/* 6515 */ MCD_OPC_Decode, 128, 10, 148, 1, // Opcode: AE_S32F24_L_XP +/* 6520 */ MCD_OPC_FilterValue, 131, 129, 12, 71, 0, 0, // Skip to: 6598 +/* 6527 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6530 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6552 +/* 6535 */ MCD_OPC_CheckPredicate, 24, 50, 5, 0, // Skip to: 7870 +/* 6540 */ MCD_OPC_CheckField, 0, 4, 14, 43, 5, 0, // Skip to: 7870 +/* 6547 */ MCD_OPC_Decode, 132, 10, 148, 1, // Opcode: AE_S32M_XC +/* 6552 */ MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 6575 +/* 6558 */ MCD_OPC_CheckPredicate, 24, 27, 5, 0, // Skip to: 7870 +/* 6563 */ MCD_OPC_CheckField, 0, 4, 14, 20, 5, 0, // Skip to: 7870 +/* 6570 */ MCD_OPC_Decode, 136, 10, 153, 1, // Opcode: AE_S32RA64S_X +/* 6575 */ MCD_OPC_FilterValue, 128, 96, 9, 5, 0, // Skip to: 7870 +/* 6581 */ MCD_OPC_CheckPredicate, 24, 4, 5, 0, // Skip to: 7870 +/* 6586 */ MCD_OPC_CheckField, 0, 4, 14, 253, 4, 0, // Skip to: 7870 +/* 6593 */ MCD_OPC_Decode, 137, 10, 148, 1, // Opcode: AE_S32RA64S_XC +/* 6598 */ MCD_OPC_FilterValue, 134, 129, 12, 25, 0, 0, // Skip to: 6630 +/* 6605 */ MCD_OPC_CheckPredicate, 24, 236, 4, 0, // Skip to: 7870 +/* 6610 */ MCD_OPC_CheckField, 16, 14, 128, 64, 228, 4, 0, // Skip to: 7870 +/* 6618 */ MCD_OPC_CheckField, 0, 4, 14, 221, 4, 0, // Skip to: 7870 +/* 6625 */ MCD_OPC_Decode, 157, 10, 148, 1, // Opcode: AE_S32_L_XC +/* 6630 */ MCD_OPC_FilterValue, 135, 129, 12, 71, 0, 0, // Skip to: 6708 +/* 6637 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6640 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6662 +/* 6645 */ MCD_OPC_CheckPredicate, 24, 196, 4, 0, // Skip to: 7870 +/* 6650 */ MCD_OPC_CheckField, 0, 4, 14, 189, 4, 0, // Skip to: 7870 +/* 6657 */ MCD_OPC_Decode, 161, 10, 153, 1, // Opcode: AE_S64_X +/* 6662 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6685 +/* 6668 */ MCD_OPC_CheckPredicate, 24, 173, 4, 0, // Skip to: 7870 +/* 6673 */ MCD_OPC_CheckField, 0, 4, 14, 166, 4, 0, // Skip to: 7870 +/* 6680 */ MCD_OPC_Decode, 162, 10, 148, 1, // Opcode: AE_S64_XC +/* 6685 */ MCD_OPC_FilterValue, 128, 64, 155, 4, 0, // Skip to: 7870 +/* 6691 */ MCD_OPC_CheckPredicate, 24, 150, 4, 0, // Skip to: 7870 +/* 6696 */ MCD_OPC_CheckField, 0, 4, 14, 143, 4, 0, // Skip to: 7870 +/* 6703 */ MCD_OPC_Decode, 163, 10, 148, 1, // Opcode: AE_S64_XP +/* 6708 */ MCD_OPC_FilterValue, 141, 129, 12, 49, 0, 0, // Skip to: 6764 +/* 6715 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6718 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6741 +/* 6724 */ MCD_OPC_CheckPredicate, 24, 117, 4, 0, // Skip to: 7870 +/* 6729 */ MCD_OPC_CheckField, 0, 4, 14, 110, 4, 0, // Skip to: 7870 +/* 6736 */ MCD_OPC_Decode, 246, 9, 146, 1, // Opcode: AE_S24RA64S_I +/* 6741 */ MCD_OPC_FilterValue, 128, 64, 99, 4, 0, // Skip to: 7870 +/* 6747 */ MCD_OPC_CheckPredicate, 24, 94, 4, 0, // Skip to: 7870 +/* 6752 */ MCD_OPC_CheckField, 0, 4, 14, 87, 4, 0, // Skip to: 7870 +/* 6759 */ MCD_OPC_Decode, 247, 9, 147, 1, // Opcode: AE_S24RA64S_IP +/* 6764 */ MCD_OPC_FilterValue, 143, 129, 12, 48, 0, 0, // Skip to: 6819 +/* 6771 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6774 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6796 +/* 6779 */ MCD_OPC_CheckPredicate, 24, 62, 4, 0, // Skip to: 7870 +/* 6784 */ MCD_OPC_CheckField, 0, 4, 14, 55, 4, 0, // Skip to: 7870 +/* 6791 */ MCD_OPC_Decode, 134, 10, 146, 1, // Opcode: AE_S32RA64S_I +/* 6796 */ MCD_OPC_FilterValue, 128, 32, 44, 4, 0, // Skip to: 7870 +/* 6802 */ MCD_OPC_CheckPredicate, 24, 39, 4, 0, // Skip to: 7870 +/* 6807 */ MCD_OPC_CheckField, 0, 4, 14, 32, 4, 0, // Skip to: 7870 +/* 6814 */ MCD_OPC_Decode, 135, 10, 147, 1, // Opcode: AE_S32RA64S_IP +/* 6819 */ MCD_OPC_FilterValue, 148, 129, 12, 71, 0, 0, // Skip to: 6897 +/* 6826 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6829 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6851 +/* 6834 */ MCD_OPC_CheckPredicate, 24, 7, 4, 0, // Skip to: 7870 +/* 6839 */ MCD_OPC_CheckField, 0, 6, 30, 0, 4, 0, // Skip to: 7870 +/* 6846 */ MCD_OPC_Decode, 179, 10, 193, 1, // Opcode: AE_SA32X2F24_RIP +/* 6851 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6874 +/* 6857 */ MCD_OPC_CheckPredicate, 24, 240, 3, 0, // Skip to: 7870 +/* 6862 */ MCD_OPC_CheckField, 0, 6, 30, 233, 3, 0, // Skip to: 7870 +/* 6869 */ MCD_OPC_Decode, 180, 10, 193, 1, // Opcode: AE_SA32X2_IC +/* 6874 */ MCD_OPC_FilterValue, 128, 96, 222, 3, 0, // Skip to: 7870 +/* 6880 */ MCD_OPC_CheckPredicate, 24, 217, 3, 0, // Skip to: 7870 +/* 6885 */ MCD_OPC_CheckField, 0, 6, 30, 210, 3, 0, // Skip to: 7870 +/* 6892 */ MCD_OPC_Decode, 182, 10, 193, 1, // Opcode: AE_SA32X2_RIC +/* 6897 */ MCD_OPC_FilterValue, 149, 129, 12, 202, 0, 0, // Skip to: 7106 +/* 6904 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 6907 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 6945 +/* 6912 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 6915 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 6930 +/* 6920 */ MCD_OPC_CheckPredicate, 24, 177, 3, 0, // Skip to: 7870 +/* 6925 */ MCD_OPC_Decode, 183, 10, 193, 1, // Opcode: AE_SA32X2_RIP +/* 6930 */ MCD_OPC_FilterValue, 46, 167, 3, 0, // Skip to: 7870 +/* 6935 */ MCD_OPC_CheckPredicate, 24, 162, 3, 0, // Skip to: 7870 +/* 6940 */ MCD_OPC_Decode, 194, 5, 194, 1, // Opcode: AE_LA24_RIP +/* 6945 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6968 +/* 6951 */ MCD_OPC_CheckPredicate, 24, 146, 3, 0, // Skip to: 7870 +/* 6956 */ MCD_OPC_CheckField, 0, 6, 62, 139, 3, 0, // Skip to: 7870 +/* 6963 */ MCD_OPC_Decode, 197, 5, 194, 1, // Opcode: AE_LA32X2F24_RIC +/* 6968 */ MCD_OPC_FilterValue, 128, 64, 40, 0, 0, // Skip to: 7014 +/* 6974 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 6977 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 6999 +/* 6982 */ MCD_OPC_CheckPredicate, 24, 115, 3, 0, // Skip to: 7870 +/* 6987 */ MCD_OPC_CheckField, 6, 2, 3, 108, 3, 0, // Skip to: 7870 +/* 6994 */ MCD_OPC_Decode, 155, 5, 166, 1, // Opcode: AE_L32X2F24_RIC +/* 6999 */ MCD_OPC_FilterValue, 46, 98, 3, 0, // Skip to: 7870 +/* 7004 */ MCD_OPC_CheckPredicate, 24, 93, 3, 0, // Skip to: 7870 +/* 7009 */ MCD_OPC_Decode, 198, 5, 194, 1, // Opcode: AE_LA32X2F24_RIP +/* 7014 */ MCD_OPC_FilterValue, 128, 96, 82, 3, 0, // Skip to: 7870 +/* 7020 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 7023 */ MCD_OPC_FilterValue, 30, 63, 0, 0, // Skip to: 7091 +/* 7028 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7031 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7046 +/* 7036 */ MCD_OPC_CheckPredicate, 24, 61, 3, 0, // Skip to: 7870 +/* 7041 */ MCD_OPC_Decode, 162, 5, 166, 1, // Opcode: AE_L32X2_RIC +/* 7046 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7061 +/* 7051 */ MCD_OPC_CheckPredicate, 24, 46, 3, 0, // Skip to: 7870 +/* 7056 */ MCD_OPC_Decode, 141, 10, 195, 1, // Opcode: AE_S32X2F24_RIC +/* 7061 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7076 +/* 7066 */ MCD_OPC_CheckPredicate, 24, 31, 3, 0, // Skip to: 7870 +/* 7071 */ MCD_OPC_Decode, 142, 10, 195, 1, // Opcode: AE_S32X2F24_RIP +/* 7076 */ MCD_OPC_FilterValue, 3, 21, 3, 0, // Skip to: 7870 +/* 7081 */ MCD_OPC_CheckPredicate, 24, 16, 3, 0, // Skip to: 7870 +/* 7086 */ MCD_OPC_Decode, 149, 10, 195, 1, // Opcode: AE_S32X2_RIC +/* 7091 */ MCD_OPC_FilterValue, 62, 6, 3, 0, // Skip to: 7870 +/* 7096 */ MCD_OPC_CheckPredicate, 24, 1, 3, 0, // Skip to: 7870 +/* 7101 */ MCD_OPC_Decode, 203, 5, 194, 1, // Opcode: AE_LA32X2_RIC +/* 7106 */ MCD_OPC_FilterValue, 150, 129, 12, 142, 0, 0, // Skip to: 7255 +/* 7113 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 7116 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7154 +/* 7121 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 7124 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7139 +/* 7129 */ MCD_OPC_CheckPredicate, 24, 224, 2, 0, // Skip to: 7870 +/* 7134 */ MCD_OPC_Decode, 204, 5, 194, 1, // Opcode: AE_LA32X2_RIP +/* 7139 */ MCD_OPC_FilterValue, 62, 214, 2, 0, // Skip to: 7870 +/* 7144 */ MCD_OPC_CheckPredicate, 24, 209, 2, 0, // Skip to: 7870 +/* 7149 */ MCD_OPC_Decode, 164, 10, 193, 1, // Opcode: AE_SA16X4_IC +/* 7154 */ MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 7177 +/* 7160 */ MCD_OPC_CheckPredicate, 24, 193, 2, 0, // Skip to: 7870 +/* 7165 */ MCD_OPC_CheckField, 0, 6, 62, 186, 2, 0, // Skip to: 7870 +/* 7172 */ MCD_OPC_Decode, 166, 10, 193, 1, // Opcode: AE_SA16X4_RIC +/* 7177 */ MCD_OPC_FilterValue, 128, 64, 33, 0, 0, // Skip to: 7216 +/* 7183 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 7186 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7201 +/* 7191 */ MCD_OPC_CheckPredicate, 24, 162, 2, 0, // Skip to: 7870 +/* 7196 */ MCD_OPC_Decode, 167, 10, 193, 1, // Opcode: AE_SA16X4_RIP +/* 7201 */ MCD_OPC_FilterValue, 62, 152, 2, 0, // Skip to: 7870 +/* 7206 */ MCD_OPC_CheckPredicate, 24, 147, 2, 0, // Skip to: 7870 +/* 7211 */ MCD_OPC_Decode, 168, 10, 193, 1, // Opcode: AE_SA24X2_IC +/* 7216 */ MCD_OPC_FilterValue, 128, 96, 136, 2, 0, // Skip to: 7870 +/* 7222 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 7225 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7240 +/* 7230 */ MCD_OPC_CheckPredicate, 24, 123, 2, 0, // Skip to: 7870 +/* 7235 */ MCD_OPC_Decode, 169, 10, 193, 1, // Opcode: AE_SA24X2_IP +/* 7240 */ MCD_OPC_FilterValue, 62, 113, 2, 0, // Skip to: 7870 +/* 7245 */ MCD_OPC_CheckPredicate, 24, 108, 2, 0, // Skip to: 7870 +/* 7250 */ MCD_OPC_Decode, 170, 10, 193, 1, // Opcode: AE_SA24X2_RIC +/* 7255 */ MCD_OPC_FilterValue, 151, 129, 12, 142, 0, 0, // Skip to: 7404 +/* 7262 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 7265 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7303 +/* 7270 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 7273 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7288 +/* 7278 */ MCD_OPC_CheckPredicate, 24, 75, 2, 0, // Skip to: 7870 +/* 7283 */ MCD_OPC_Decode, 171, 10, 193, 1, // Opcode: AE_SA24X2_RIP +/* 7288 */ MCD_OPC_FilterValue, 62, 65, 2, 0, // Skip to: 7870 +/* 7293 */ MCD_OPC_CheckPredicate, 24, 60, 2, 0, // Skip to: 7870 +/* 7298 */ MCD_OPC_Decode, 172, 10, 193, 1, // Opcode: AE_SA24_L_IC +/* 7303 */ MCD_OPC_FilterValue, 128, 32, 33, 0, 0, // Skip to: 7342 +/* 7309 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 7312 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7327 +/* 7317 */ MCD_OPC_CheckPredicate, 24, 36, 2, 0, // Skip to: 7870 +/* 7322 */ MCD_OPC_Decode, 173, 10, 193, 1, // Opcode: AE_SA24_L_IP +/* 7327 */ MCD_OPC_FilterValue, 62, 26, 2, 0, // Skip to: 7870 +/* 7332 */ MCD_OPC_CheckPredicate, 24, 21, 2, 0, // Skip to: 7870 +/* 7337 */ MCD_OPC_Decode, 174, 10, 193, 1, // Opcode: AE_SA24_L_RIC +/* 7342 */ MCD_OPC_FilterValue, 128, 64, 33, 0, 0, // Skip to: 7381 +/* 7348 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 7351 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7366 +/* 7356 */ MCD_OPC_CheckPredicate, 24, 253, 1, 0, // Skip to: 7870 +/* 7361 */ MCD_OPC_Decode, 175, 10, 193, 1, // Opcode: AE_SA24_L_RIP +/* 7366 */ MCD_OPC_FilterValue, 62, 243, 1, 0, // Skip to: 7870 +/* 7371 */ MCD_OPC_CheckPredicate, 24, 238, 1, 0, // Skip to: 7870 +/* 7376 */ MCD_OPC_Decode, 176, 10, 193, 1, // Opcode: AE_SA32X2F24_IC +/* 7381 */ MCD_OPC_FilterValue, 128, 96, 227, 1, 0, // Skip to: 7870 +/* 7387 */ MCD_OPC_CheckPredicate, 24, 222, 1, 0, // Skip to: 7870 +/* 7392 */ MCD_OPC_CheckField, 0, 6, 62, 215, 1, 0, // Skip to: 7870 +/* 7399 */ MCD_OPC_Decode, 178, 10, 193, 1, // Opcode: AE_SA32X2F24_RIC +/* 7404 */ MCD_OPC_FilterValue, 152, 129, 12, 26, 1, 0, // Skip to: 7693 +/* 7411 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 7414 */ MCD_OPC_FilterValue, 14, 57, 0, 0, // Skip to: 7476 +/* 7419 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 7422 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7460 +/* 7427 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7430 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7445 +/* 7435 */ MCD_OPC_CheckPredicate, 24, 174, 1, 0, // Skip to: 7870 +/* 7440 */ MCD_OPC_Decode, 177, 5, 196, 1, // Opcode: AE_LA16X4NEG_PC +/* 7445 */ MCD_OPC_FilterValue, 7, 164, 1, 0, // Skip to: 7870 +/* 7450 */ MCD_OPC_CheckPredicate, 24, 159, 1, 0, // Skip to: 7870 +/* 7455 */ MCD_OPC_Decode, 185, 5, 196, 1, // Opcode: AE_LA24X2NEG_PC +/* 7460 */ MCD_OPC_FilterValue, 128, 96, 148, 1, 0, // Skip to: 7870 +/* 7466 */ MCD_OPC_CheckPredicate, 24, 143, 1, 0, // Skip to: 7870 +/* 7471 */ MCD_OPC_Decode, 190, 5, 194, 1, // Opcode: AE_LA24X2_RIP +/* 7476 */ MCD_OPC_FilterValue, 30, 57, 0, 0, // Skip to: 7538 +/* 7481 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 7484 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7522 +/* 7489 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7492 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7507 +/* 7497 */ MCD_OPC_CheckPredicate, 24, 112, 1, 0, // Skip to: 7870 +/* 7502 */ MCD_OPC_Decode, 183, 5, 196, 1, // Opcode: AE_LA24NEG_PC +/* 7507 */ MCD_OPC_FilterValue, 7, 102, 1, 0, // Skip to: 7870 +/* 7512 */ MCD_OPC_CheckPredicate, 24, 97, 1, 0, // Skip to: 7870 +/* 7517 */ MCD_OPC_Decode, 199, 5, 196, 1, // Opcode: AE_LA32X2NEG_PC +/* 7522 */ MCD_OPC_FilterValue, 128, 96, 86, 1, 0, // Skip to: 7870 +/* 7528 */ MCD_OPC_CheckPredicate, 24, 81, 1, 0, // Skip to: 7870 +/* 7533 */ MCD_OPC_Decode, 192, 5, 194, 1, // Opcode: AE_LA24_IP +/* 7538 */ MCD_OPC_FilterValue, 46, 72, 0, 0, // Skip to: 7615 +/* 7543 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 7546 */ MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 7599 +/* 7551 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7554 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7569 +/* 7559 */ MCD_OPC_CheckPredicate, 24, 50, 1, 0, // Skip to: 7870 +/* 7564 */ MCD_OPC_Decode, 178, 5, 196, 1, // Opcode: AE_LA16X4POS_PC +/* 7569 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 7584 +/* 7574 */ MCD_OPC_CheckPredicate, 24, 35, 1, 0, // Skip to: 7870 +/* 7579 */ MCD_OPC_Decode, 186, 5, 196, 1, // Opcode: AE_LA24X2POS_PC +/* 7584 */ MCD_OPC_FilterValue, 11, 25, 1, 0, // Skip to: 7870 +/* 7589 */ MCD_OPC_CheckPredicate, 24, 20, 1, 0, // Skip to: 7870 +/* 7594 */ MCD_OPC_Decode, 184, 10, 197, 1, // Opcode: AE_SA64NEG_FP +/* 7599 */ MCD_OPC_FilterValue, 128, 96, 9, 1, 0, // Skip to: 7870 +/* 7605 */ MCD_OPC_CheckPredicate, 24, 4, 1, 0, // Skip to: 7870 +/* 7610 */ MCD_OPC_Decode, 191, 5, 194, 1, // Opcode: AE_LA24_IC +/* 7615 */ MCD_OPC_FilterValue, 62, 250, 0, 0, // Skip to: 7870 +/* 7620 */ MCD_OPC_ExtractField, 16, 14, // Inst{29-16} ... +/* 7623 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7645 +/* 7628 */ MCD_OPC_CheckPredicate, 24, 237, 0, 0, // Skip to: 7870 +/* 7633 */ MCD_OPC_CheckField, 12, 4, 3, 230, 0, 0, // Skip to: 7870 +/* 7640 */ MCD_OPC_Decode, 184, 5, 196, 1, // Opcode: AE_LA24POS_PC +/* 7645 */ MCD_OPC_FilterValue, 128, 32, 10, 0, 0, // Skip to: 7661 +/* 7651 */ MCD_OPC_CheckPredicate, 24, 214, 0, 0, // Skip to: 7870 +/* 7656 */ MCD_OPC_Decode, 181, 5, 194, 1, // Opcode: AE_LA16X4_RIC +/* 7661 */ MCD_OPC_FilterValue, 128, 64, 10, 0, 0, // Skip to: 7677 +/* 7667 */ MCD_OPC_CheckPredicate, 24, 198, 0, 0, // Skip to: 7870 +/* 7672 */ MCD_OPC_Decode, 189, 5, 194, 1, // Opcode: AE_LA24X2_RIC +/* 7677 */ MCD_OPC_FilterValue, 128, 96, 187, 0, 0, // Skip to: 7870 +/* 7683 */ MCD_OPC_CheckPredicate, 24, 182, 0, 0, // Skip to: 7870 +/* 7688 */ MCD_OPC_Decode, 193, 5, 194, 1, // Opcode: AE_LA24_RIC +/* 7693 */ MCD_OPC_FilterValue, 153, 129, 12, 47, 0, 0, // Skip to: 7747 +/* 7700 */ MCD_OPC_ExtractField, 12, 16, // Inst{27-12} ... +/* 7703 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7725 +/* 7708 */ MCD_OPC_CheckPredicate, 24, 157, 0, 0, // Skip to: 7870 +/* 7713 */ MCD_OPC_CheckField, 0, 4, 14, 150, 0, 0, // Skip to: 7870 +/* 7720 */ MCD_OPC_Decode, 206, 5, 198, 1, // Opcode: AE_LALIGN64_I +/* 7725 */ MCD_OPC_FilterValue, 4, 140, 0, 0, // Skip to: 7870 +/* 7730 */ MCD_OPC_CheckPredicate, 24, 135, 0, 0, // Skip to: 7870 +/* 7735 */ MCD_OPC_CheckField, 0, 4, 14, 128, 0, 0, // Skip to: 7870 +/* 7742 */ MCD_OPC_Decode, 186, 10, 198, 1, // Opcode: AE_SALIGN64_I +/* 7747 */ MCD_OPC_FilterValue, 154, 129, 12, 31, 0, 0, // Skip to: 7785 +/* 7754 */ MCD_OPC_CheckPredicate, 24, 111, 0, 0, // Skip to: 7870 +/* 7759 */ MCD_OPC_CheckField, 16, 14, 0, 104, 0, 0, // Skip to: 7870 +/* 7766 */ MCD_OPC_CheckField, 8, 4, 8, 97, 0, 0, // Skip to: 7870 +/* 7773 */ MCD_OPC_CheckField, 0, 4, 14, 90, 0, 0, // Skip to: 7870 +/* 7780 */ MCD_OPC_Decode, 229, 5, 199, 1, // Opcode: AE_MOVAD16_1 +/* 7785 */ MCD_OPC_FilterValue, 128, 208, 14, 24, 0, 0, // Skip to: 7816 +/* 7792 */ MCD_OPC_CheckPredicate, 24, 73, 0, 0, // Skip to: 7870 +/* 7797 */ MCD_OPC_CheckField, 28, 2, 0, 66, 0, 0, // Skip to: 7870 +/* 7804 */ MCD_OPC_CheckField, 0, 16, 14, 59, 0, 0, // Skip to: 7870 +/* 7811 */ MCD_OPC_Decode, 224, 4, 200, 1, // Opcode: AE_ADDBRBA32 +/* 7816 */ MCD_OPC_FilterValue, 128, 226, 15, 47, 0, 0, // Skip to: 7870 +/* 7823 */ MCD_OPC_ExtractField, 24, 6, // Inst{29-24} ... +/* 7826 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 7848 +/* 7831 */ MCD_OPC_CheckPredicate, 24, 34, 0, 0, // Skip to: 7870 +/* 7836 */ MCD_OPC_CheckField, 0, 16, 14, 27, 0, 0, // Skip to: 7870 +/* 7843 */ MCD_OPC_Decode, 231, 4, 201, 1, // Opcode: AE_CVT64A32 +/* 7848 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 7870 +/* 7853 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 7870 +/* 7858 */ MCD_OPC_CheckField, 0, 16, 14, 5, 0, 0, // Skip to: 7870 +/* 7865 */ MCD_OPC_Decode, 235, 4, 201, 1, // Opcode: AE_CVTQ56A32S +/* 7870 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableHIFI364[] = { +/* 0 */ MCD_OPC_ExtractField, 58, 6, // Inst{63-58} ... +/* 3 */ MCD_OPC_FilterValue, 0, 98, 10, 0, // Skip to: 2666 +/* 8 */ MCD_OPC_ExtractField, 50, 8, // Inst{57-50} ... +/* 11 */ MCD_OPC_FilterValue, 0, 70, 1, 0, // Skip to: 342 +/* 16 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 19 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 55 +/* 24 */ MCD_OPC_CheckPredicate, 24, 76, 51, 0, // Skip to: 13161 +/* 29 */ MCD_OPC_CheckField, 40, 10, 0, 69, 51, 0, // Skip to: 13161 +/* 36 */ MCD_OPC_CheckField, 28, 4, 0, 62, 51, 0, // Skip to: 13161 +/* 43 */ MCD_OPC_CheckField, 8, 8, 0, 55, 51, 0, // Skip to: 13161 +/* 50 */ MCD_OPC_Decode, 238, 6, 202, 1, // Opcode: AE_MULAFD24X2_FIR_H +/* 55 */ MCD_OPC_FilterValue, 15, 38, 0, 0, // Skip to: 98 +/* 60 */ MCD_OPC_CheckPredicate, 24, 40, 51, 0, // Skip to: 13161 +/* 65 */ MCD_OPC_CheckField, 36, 12, 0, 33, 51, 0, // Skip to: 13161 +/* 72 */ MCD_OPC_CheckField, 28, 4, 0, 26, 51, 0, // Skip to: 13161 +/* 79 */ MCD_OPC_CheckField, 20, 4, 0, 19, 51, 0, // Skip to: 13161 +/* 86 */ MCD_OPC_CheckField, 8, 8, 0, 12, 51, 0, // Skip to: 13161 +/* 93 */ MCD_OPC_Decode, 201, 10, 203, 1, // Opcode: AE_SEL16I_N +/* 98 */ MCD_OPC_FilterValue, 47, 41, 0, 0, // Skip to: 144 +/* 103 */ MCD_OPC_ExtractField, 16, 34, // Inst{49-16} ... +/* 106 */ MCD_OPC_FilterValue, 128, 128, 128, 192, 12, 10, 0, 0, // Skip to: 125 +/* 115 */ MCD_OPC_CheckPredicate, 24, 241, 50, 0, // Skip to: 13161 +/* 120 */ MCD_OPC_Decode, 233, 4, 158, 1, // Opcode: AE_CVTA32F24S_H +/* 125 */ MCD_OPC_FilterValue, 128, 128, 128, 200, 13, 227, 50, 0, // Skip to: 13161 +/* 134 */ MCD_OPC_CheckPredicate, 24, 222, 50, 0, // Skip to: 13161 +/* 139 */ MCD_OPC_Decode, 133, 5, 166, 1, // Opcode: AE_L16X4_RIC +/* 144 */ MCD_OPC_FilterValue, 63, 21, 0, 0, // Skip to: 170 +/* 149 */ MCD_OPC_CheckPredicate, 24, 207, 50, 0, // Skip to: 13161 +/* 154 */ MCD_OPC_CheckField, 16, 34, 128, 128, 128, 200, 12, 196, 50, 0, // Skip to: 13161 +/* 165 */ MCD_OPC_Decode, 228, 4, 156, 1, // Opcode: AE_CVT32X2F16_10 +/* 170 */ MCD_OPC_FilterValue, 95, 21, 0, 0, // Skip to: 196 +/* 175 */ MCD_OPC_CheckPredicate, 24, 181, 50, 0, // Skip to: 13161 +/* 180 */ MCD_OPC_CheckField, 16, 34, 128, 128, 128, 200, 13, 170, 50, 0, // Skip to: 13161 +/* 191 */ MCD_OPC_Decode, 236, 9, 195, 1, // Opcode: AE_S16X4_RIC +/* 196 */ MCD_OPC_FilterValue, 111, 41, 0, 0, // Skip to: 242 +/* 201 */ MCD_OPC_ExtractField, 16, 34, // Inst{49-16} ... +/* 204 */ MCD_OPC_FilterValue, 128, 128, 128, 192, 12, 10, 0, 0, // Skip to: 223 +/* 213 */ MCD_OPC_CheckPredicate, 24, 143, 50, 0, // Skip to: 13161 +/* 218 */ MCD_OPC_Decode, 234, 4, 158, 1, // Opcode: AE_CVTA32F24S_L +/* 223 */ MCD_OPC_FilterValue, 128, 128, 128, 200, 13, 129, 50, 0, // Skip to: 13161 +/* 232 */ MCD_OPC_CheckPredicate, 24, 124, 50, 0, // Skip to: 13161 +/* 237 */ MCD_OPC_Decode, 134, 5, 166, 1, // Opcode: AE_L16X4_RIP +/* 242 */ MCD_OPC_FilterValue, 127, 41, 0, 0, // Skip to: 288 +/* 247 */ MCD_OPC_ExtractField, 16, 34, // Inst{49-16} ... +/* 250 */ MCD_OPC_FilterValue, 128, 128, 128, 200, 12, 10, 0, 0, // Skip to: 269 +/* 259 */ MCD_OPC_CheckPredicate, 24, 97, 50, 0, // Skip to: 13161 +/* 264 */ MCD_OPC_Decode, 229, 4, 156, 1, // Opcode: AE_CVT32X2F16_32 +/* 269 */ MCD_OPC_FilterValue, 128, 128, 128, 200, 13, 83, 50, 0, // Skip to: 13161 +/* 278 */ MCD_OPC_CheckPredicate, 24, 78, 50, 0, // Skip to: 13161 +/* 283 */ MCD_OPC_Decode, 237, 9, 195, 1, // Opcode: AE_S16X4_RIP +/* 288 */ MCD_OPC_FilterValue, 239, 1, 21, 0, 0, // Skip to: 315 +/* 294 */ MCD_OPC_CheckPredicate, 24, 62, 50, 0, // Skip to: 13161 +/* 299 */ MCD_OPC_CheckField, 16, 34, 128, 128, 128, 200, 12, 51, 50, 0, // Skip to: 13161 +/* 310 */ MCD_OPC_Decode, 203, 10, 156, 1, // Opcode: AE_SEXT32X2D16_10 +/* 315 */ MCD_OPC_FilterValue, 255, 1, 40, 50, 0, // Skip to: 13161 +/* 321 */ MCD_OPC_CheckPredicate, 24, 35, 50, 0, // Skip to: 13161 +/* 326 */ MCD_OPC_CheckField, 16, 34, 128, 128, 128, 200, 13, 24, 50, 0, // Skip to: 13161 +/* 337 */ MCD_OPC_Decode, 150, 10, 195, 1, // Opcode: AE_S32X2_RIP +/* 342 */ MCD_OPC_FilterValue, 7, 76, 0, 0, // Skip to: 423 +/* 347 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 350 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 386 +/* 355 */ MCD_OPC_CheckPredicate, 24, 1, 50, 0, // Skip to: 13161 +/* 360 */ MCD_OPC_CheckField, 28, 4, 0, 250, 49, 0, // Skip to: 13161 +/* 367 */ MCD_OPC_CheckField, 20, 4, 0, 243, 49, 0, // Skip to: 13161 +/* 374 */ MCD_OPC_CheckField, 0, 16, 15, 236, 49, 0, // Skip to: 13161 +/* 381 */ MCD_OPC_Decode, 162, 6, 204, 1, // Opcode: AE_MULAAD24_HH_LL +/* 386 */ MCD_OPC_FilterValue, 128, 32, 225, 49, 0, // Skip to: 13161 +/* 392 */ MCD_OPC_CheckPredicate, 24, 220, 49, 0, // Skip to: 13161 +/* 397 */ MCD_OPC_CheckField, 28, 4, 0, 213, 49, 0, // Skip to: 13161 +/* 404 */ MCD_OPC_CheckField, 20, 4, 0, 206, 49, 0, // Skip to: 13161 +/* 411 */ MCD_OPC_CheckField, 0, 16, 15, 199, 49, 0, // Skip to: 13161 +/* 418 */ MCD_OPC_Decode, 164, 6, 204, 1, // Opcode: AE_MULAAD24_HL_LH +/* 423 */ MCD_OPC_FilterValue, 9, 77, 0, 0, // Skip to: 505 +/* 428 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 431 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 468 +/* 437 */ MCD_OPC_CheckPredicate, 24, 175, 49, 0, // Skip to: 13161 +/* 442 */ MCD_OPC_CheckField, 28, 4, 0, 168, 49, 0, // Skip to: 13161 +/* 449 */ MCD_OPC_CheckField, 20, 4, 0, 161, 49, 0, // Skip to: 13161 +/* 456 */ MCD_OPC_CheckField, 0, 16, 15, 154, 49, 0, // Skip to: 13161 +/* 463 */ MCD_OPC_Decode, 180, 6, 204, 1, // Opcode: AE_MULAAFD24_HH_LL +/* 468 */ MCD_OPC_FilterValue, 128, 64, 143, 49, 0, // Skip to: 13161 +/* 474 */ MCD_OPC_CheckPredicate, 24, 138, 49, 0, // Skip to: 13161 +/* 479 */ MCD_OPC_CheckField, 28, 4, 0, 131, 49, 0, // Skip to: 13161 +/* 486 */ MCD_OPC_CheckField, 20, 4, 0, 124, 49, 0, // Skip to: 13161 +/* 493 */ MCD_OPC_CheckField, 0, 16, 15, 117, 49, 0, // Skip to: 13161 +/* 500 */ MCD_OPC_Decode, 182, 6, 204, 1, // Opcode: AE_MULAAFD24_HL_LH +/* 505 */ MCD_OPC_FilterValue, 10, 39, 0, 0, // Skip to: 549 +/* 510 */ MCD_OPC_CheckPredicate, 24, 102, 49, 0, // Skip to: 13161 +/* 515 */ MCD_OPC_CheckField, 36, 14, 128, 96, 94, 49, 0, // Skip to: 13161 +/* 523 */ MCD_OPC_CheckField, 28, 4, 0, 87, 49, 0, // Skip to: 13161 +/* 530 */ MCD_OPC_CheckField, 20, 4, 0, 80, 49, 0, // Skip to: 13161 +/* 537 */ MCD_OPC_CheckField, 0, 16, 15, 73, 49, 0, // Skip to: 13161 +/* 544 */ MCD_OPC_Decode, 192, 6, 204, 1, // Opcode: AE_MULAC24 +/* 549 */ MCD_OPC_FilterValue, 18, 39, 0, 0, // Skip to: 593 +/* 554 */ MCD_OPC_CheckPredicate, 24, 58, 49, 0, // Skip to: 13161 +/* 559 */ MCD_OPC_CheckField, 36, 14, 128, 64, 50, 49, 0, // Skip to: 13161 +/* 567 */ MCD_OPC_CheckField, 28, 4, 0, 43, 49, 0, // Skip to: 13161 +/* 574 */ MCD_OPC_CheckField, 20, 4, 0, 36, 49, 0, // Skip to: 13161 +/* 581 */ MCD_OPC_CheckField, 0, 16, 15, 29, 49, 0, // Skip to: 13161 +/* 588 */ MCD_OPC_Decode, 132, 7, 204, 1, // Opcode: AE_MULAP24X2 +/* 593 */ MCD_OPC_FilterValue, 20, 77, 0, 0, // Skip to: 675 +/* 598 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 601 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 638 +/* 607 */ MCD_OPC_CheckPredicate, 24, 5, 49, 0, // Skip to: 13161 +/* 612 */ MCD_OPC_CheckField, 28, 4, 0, 254, 48, 0, // Skip to: 13161 +/* 619 */ MCD_OPC_CheckField, 20, 4, 0, 247, 48, 0, // Skip to: 13161 +/* 626 */ MCD_OPC_CheckField, 0, 16, 15, 240, 48, 0, // Skip to: 13161 +/* 633 */ MCD_OPC_Decode, 147, 7, 204, 1, // Opcode: AE_MULASD24_HH_LL +/* 638 */ MCD_OPC_FilterValue, 128, 64, 229, 48, 0, // Skip to: 13161 +/* 644 */ MCD_OPC_CheckPredicate, 24, 224, 48, 0, // Skip to: 13161 +/* 649 */ MCD_OPC_CheckField, 28, 4, 0, 217, 48, 0, // Skip to: 13161 +/* 656 */ MCD_OPC_CheckField, 20, 4, 0, 210, 48, 0, // Skip to: 13161 +/* 663 */ MCD_OPC_CheckField, 0, 16, 15, 203, 48, 0, // Skip to: 13161 +/* 670 */ MCD_OPC_Decode, 149, 7, 204, 1, // Opcode: AE_MULASD24_HL_LH +/* 675 */ MCD_OPC_FilterValue, 21, 77, 0, 0, // Skip to: 757 +/* 680 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 683 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 720 +/* 689 */ MCD_OPC_CheckPredicate, 24, 179, 48, 0, // Skip to: 13161 +/* 694 */ MCD_OPC_CheckField, 28, 4, 0, 172, 48, 0, // Skip to: 13161 +/* 701 */ MCD_OPC_CheckField, 20, 4, 0, 165, 48, 0, // Skip to: 13161 +/* 708 */ MCD_OPC_CheckField, 0, 16, 15, 158, 48, 0, // Skip to: 13161 +/* 715 */ MCD_OPC_Decode, 155, 7, 204, 1, // Opcode: AE_MULASFD24_HH_LL +/* 720 */ MCD_OPC_FilterValue, 128, 64, 147, 48, 0, // Skip to: 13161 +/* 726 */ MCD_OPC_CheckPredicate, 24, 142, 48, 0, // Skip to: 13161 +/* 731 */ MCD_OPC_CheckField, 28, 4, 0, 135, 48, 0, // Skip to: 13161 +/* 738 */ MCD_OPC_CheckField, 20, 4, 0, 128, 48, 0, // Skip to: 13161 +/* 745 */ MCD_OPC_CheckField, 0, 16, 15, 121, 48, 0, // Skip to: 13161 +/* 752 */ MCD_OPC_Decode, 157, 7, 204, 1, // Opcode: AE_MULASFD24_HL_LH +/* 757 */ MCD_OPC_FilterValue, 22, 39, 0, 0, // Skip to: 801 +/* 762 */ MCD_OPC_CheckPredicate, 24, 106, 48, 0, // Skip to: 13161 +/* 767 */ MCD_OPC_CheckField, 36, 14, 128, 32, 98, 48, 0, // Skip to: 13161 +/* 775 */ MCD_OPC_CheckField, 28, 4, 0, 91, 48, 0, // Skip to: 13161 +/* 782 */ MCD_OPC_CheckField, 20, 4, 0, 84, 48, 0, // Skip to: 13161 +/* 789 */ MCD_OPC_CheckField, 0, 16, 15, 77, 48, 0, // Skip to: 13161 +/* 796 */ MCD_OPC_Decode, 163, 7, 205, 1, // Opcode: AE_MULC24 +/* 801 */ MCD_OPC_FilterValue, 30, 39, 0, 0, // Skip to: 845 +/* 806 */ MCD_OPC_CheckPredicate, 24, 62, 48, 0, // Skip to: 13161 +/* 811 */ MCD_OPC_CheckField, 36, 14, 128, 64, 54, 48, 0, // Skip to: 13161 +/* 819 */ MCD_OPC_CheckField, 28, 4, 0, 47, 48, 0, // Skip to: 13161 +/* 826 */ MCD_OPC_CheckField, 20, 4, 0, 40, 48, 0, // Skip to: 13161 +/* 833 */ MCD_OPC_CheckField, 0, 16, 15, 33, 48, 0, // Skip to: 13161 +/* 840 */ MCD_OPC_Decode, 233, 7, 205, 1, // Opcode: AE_MULP24X2 +/* 845 */ MCD_OPC_FilterValue, 32, 9, 1, 0, // Skip to: 1115 +/* 850 */ MCD_OPC_ExtractField, 32, 18, // Inst{49-32} ... +/* 853 */ MCD_OPC_FilterValue, 128, 4, 24, 0, 0, // Skip to: 883 +/* 859 */ MCD_OPC_CheckPredicate, 24, 9, 48, 0, // Skip to: 13161 +/* 864 */ MCD_OPC_CheckField, 16, 12, 0, 2, 48, 0, // Skip to: 13161 +/* 871 */ MCD_OPC_CheckField, 0, 4, 14, 251, 47, 0, // Skip to: 13161 +/* 878 */ MCD_OPC_Decode, 134, 11, 206, 1, // Opcode: AE_TRUNCA32F64S_L +/* 883 */ MCD_OPC_FilterValue, 128, 14, 24, 0, 0, // Skip to: 913 +/* 889 */ MCD_OPC_CheckPredicate, 24, 235, 47, 0, // Skip to: 13161 +/* 894 */ MCD_OPC_CheckField, 16, 12, 0, 228, 47, 0, // Skip to: 13161 +/* 901 */ MCD_OPC_CheckField, 0, 4, 14, 221, 47, 0, // Skip to: 13161 +/* 908 */ MCD_OPC_Decode, 136, 11, 207, 1, // Opcode: AE_TRUNCI32F64S_L +/* 913 */ MCD_OPC_FilterValue, 128, 16, 24, 0, 0, // Skip to: 943 +/* 919 */ MCD_OPC_CheckPredicate, 24, 205, 47, 0, // Skip to: 13161 +/* 924 */ MCD_OPC_CheckField, 16, 12, 0, 198, 47, 0, // Skip to: 13161 +/* 931 */ MCD_OPC_CheckField, 0, 4, 14, 191, 47, 0, // Skip to: 13161 +/* 938 */ MCD_OPC_Decode, 137, 11, 207, 1, // Opcode: AE_TRUNCI32X2F64S +/* 943 */ MCD_OPC_FilterValue, 128, 24, 47, 0, 0, // Skip to: 996 +/* 949 */ MCD_OPC_ExtractField, 12, 16, // Inst{27-12} ... +/* 952 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 974 +/* 957 */ MCD_OPC_CheckPredicate, 24, 167, 47, 0, // Skip to: 13161 +/* 962 */ MCD_OPC_CheckField, 0, 4, 14, 160, 47, 0, // Skip to: 13161 +/* 969 */ MCD_OPC_Decode, 211, 10, 208, 1, // Opcode: AE_SLAA64S +/* 974 */ MCD_OPC_FilterValue, 15, 150, 47, 0, // Skip to: 13161 +/* 979 */ MCD_OPC_CheckPredicate, 24, 145, 47, 0, // Skip to: 13161 +/* 984 */ MCD_OPC_CheckField, 0, 4, 14, 138, 47, 0, // Skip to: 13161 +/* 991 */ MCD_OPC_Decode, 229, 10, 208, 1, // Opcode: AE_SRA64_32 +/* 996 */ MCD_OPC_FilterValue, 128, 50, 127, 47, 0, // Skip to: 13161 +/* 1002 */ MCD_OPC_ExtractField, 12, 16, // Inst{27-12} ... +/* 1005 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1027 +/* 1010 */ MCD_OPC_CheckPredicate, 24, 114, 47, 0, // Skip to: 13161 +/* 1015 */ MCD_OPC_CheckField, 0, 4, 14, 107, 47, 0, // Skip to: 13161 +/* 1022 */ MCD_OPC_Decode, 230, 10, 208, 1, // Opcode: AE_SRAA16RS +/* 1027 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1049 +/* 1032 */ MCD_OPC_CheckPredicate, 24, 92, 47, 0, // Skip to: 13161 +/* 1037 */ MCD_OPC_CheckField, 0, 4, 14, 85, 47, 0, // Skip to: 13161 +/* 1044 */ MCD_OPC_Decode, 246, 10, 208, 1, // Opcode: AE_SRLA64 +/* 1049 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1071 +/* 1054 */ MCD_OPC_CheckPredicate, 24, 70, 47, 0, // Skip to: 13161 +/* 1059 */ MCD_OPC_CheckField, 0, 4, 14, 63, 47, 0, // Skip to: 13161 +/* 1066 */ MCD_OPC_Decode, 231, 10, 208, 1, // Opcode: AE_SRAA16S +/* 1071 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1093 +/* 1076 */ MCD_OPC_CheckPredicate, 24, 48, 47, 0, // Skip to: 13161 +/* 1081 */ MCD_OPC_CheckField, 0, 4, 14, 41, 47, 0, // Skip to: 13161 +/* 1088 */ MCD_OPC_Decode, 233, 10, 208, 1, // Opcode: AE_SRAA32RS +/* 1093 */ MCD_OPC_FilterValue, 14, 31, 47, 0, // Skip to: 13161 +/* 1098 */ MCD_OPC_CheckPredicate, 24, 26, 47, 0, // Skip to: 13161 +/* 1103 */ MCD_OPC_CheckField, 0, 4, 14, 19, 47, 0, // Skip to: 13161 +/* 1110 */ MCD_OPC_Decode, 245, 10, 208, 1, // Opcode: AE_SRLA32 +/* 1115 */ MCD_OPC_FilterValue, 35, 77, 0, 0, // Skip to: 1197 +/* 1120 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 1123 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1160 +/* 1129 */ MCD_OPC_CheckPredicate, 24, 251, 46, 0, // Skip to: 13161 +/* 1134 */ MCD_OPC_CheckField, 28, 4, 0, 244, 46, 0, // Skip to: 13161 +/* 1141 */ MCD_OPC_CheckField, 20, 4, 0, 237, 46, 0, // Skip to: 13161 +/* 1148 */ MCD_OPC_CheckField, 0, 16, 15, 230, 46, 0, // Skip to: 13161 +/* 1155 */ MCD_OPC_Decode, 141, 8, 204, 1, // Opcode: AE_MULSAD24_HH_LL +/* 1160 */ MCD_OPC_FilterValue, 128, 64, 219, 46, 0, // Skip to: 13161 +/* 1166 */ MCD_OPC_CheckPredicate, 24, 214, 46, 0, // Skip to: 13161 +/* 1171 */ MCD_OPC_CheckField, 28, 4, 0, 207, 46, 0, // Skip to: 13161 +/* 1178 */ MCD_OPC_CheckField, 20, 4, 0, 200, 46, 0, // Skip to: 13161 +/* 1185 */ MCD_OPC_CheckField, 0, 16, 15, 193, 46, 0, // Skip to: 13161 +/* 1192 */ MCD_OPC_Decode, 147, 8, 204, 1, // Opcode: AE_MULSAFD24_HH_LL +/* 1197 */ MCD_OPC_FilterValue, 42, 39, 0, 0, // Skip to: 1241 +/* 1202 */ MCD_OPC_CheckPredicate, 24, 178, 46, 0, // Skip to: 13161 +/* 1207 */ MCD_OPC_CheckField, 36, 14, 128, 64, 170, 46, 0, // Skip to: 13161 +/* 1215 */ MCD_OPC_CheckField, 28, 4, 0, 163, 46, 0, // Skip to: 13161 +/* 1222 */ MCD_OPC_CheckField, 20, 4, 0, 156, 46, 0, // Skip to: 13161 +/* 1229 */ MCD_OPC_CheckField, 0, 16, 15, 149, 46, 0, // Skip to: 13161 +/* 1236 */ MCD_OPC_Decode, 208, 8, 204, 1, // Opcode: AE_MULSP24X2 +/* 1241 */ MCD_OPC_FilterValue, 44, 39, 0, 0, // Skip to: 1285 +/* 1246 */ MCD_OPC_CheckPredicate, 24, 134, 46, 0, // Skip to: 13161 +/* 1251 */ MCD_OPC_CheckField, 36, 14, 128, 96, 126, 46, 0, // Skip to: 13161 +/* 1259 */ MCD_OPC_CheckField, 28, 4, 0, 119, 46, 0, // Skip to: 13161 +/* 1266 */ MCD_OPC_CheckField, 20, 4, 0, 112, 46, 0, // Skip to: 13161 +/* 1273 */ MCD_OPC_CheckField, 0, 16, 15, 105, 46, 0, // Skip to: 13161 +/* 1280 */ MCD_OPC_Decode, 223, 8, 204, 1, // Opcode: AE_MULSSD24_HH_LL +/* 1285 */ MCD_OPC_FilterValue, 45, 38, 0, 0, // Skip to: 1328 +/* 1290 */ MCD_OPC_CheckPredicate, 24, 90, 46, 0, // Skip to: 13161 +/* 1295 */ MCD_OPC_CheckField, 36, 14, 0, 83, 46, 0, // Skip to: 13161 +/* 1302 */ MCD_OPC_CheckField, 28, 4, 0, 76, 46, 0, // Skip to: 13161 +/* 1309 */ MCD_OPC_CheckField, 20, 4, 0, 69, 46, 0, // Skip to: 13161 +/* 1316 */ MCD_OPC_CheckField, 0, 16, 15, 62, 46, 0, // Skip to: 13161 +/* 1323 */ MCD_OPC_Decode, 225, 8, 204, 1, // Opcode: AE_MULSSD24_HL_LH +/* 1328 */ MCD_OPC_FilterValue, 46, 77, 0, 0, // Skip to: 1410 +/* 1333 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 1336 */ MCD_OPC_FilterValue, 128, 64, 31, 0, 0, // Skip to: 1373 +/* 1342 */ MCD_OPC_CheckPredicate, 24, 38, 46, 0, // Skip to: 13161 +/* 1347 */ MCD_OPC_CheckField, 28, 4, 0, 31, 46, 0, // Skip to: 13161 +/* 1354 */ MCD_OPC_CheckField, 20, 4, 0, 24, 46, 0, // Skip to: 13161 +/* 1361 */ MCD_OPC_CheckField, 0, 16, 15, 17, 46, 0, // Skip to: 13161 +/* 1368 */ MCD_OPC_Decode, 237, 8, 204, 1, // Opcode: AE_MULSSFD24_HH_LL +/* 1373 */ MCD_OPC_FilterValue, 128, 96, 6, 46, 0, // Skip to: 13161 +/* 1379 */ MCD_OPC_CheckPredicate, 24, 1, 46, 0, // Skip to: 13161 +/* 1384 */ MCD_OPC_CheckField, 28, 4, 0, 250, 45, 0, // Skip to: 13161 +/* 1391 */ MCD_OPC_CheckField, 20, 4, 0, 243, 45, 0, // Skip to: 13161 +/* 1398 */ MCD_OPC_CheckField, 0, 16, 15, 236, 45, 0, // Skip to: 13161 +/* 1405 */ MCD_OPC_Decode, 239, 8, 204, 1, // Opcode: AE_MULSSFD24_HL_LH +/* 1410 */ MCD_OPC_FilterValue, 47, 77, 0, 0, // Skip to: 1492 +/* 1415 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 1418 */ MCD_OPC_FilterValue, 128, 64, 31, 0, 0, // Skip to: 1455 +/* 1424 */ MCD_OPC_CheckPredicate, 24, 212, 45, 0, // Skip to: 13161 +/* 1429 */ MCD_OPC_CheckField, 28, 4, 0, 205, 45, 0, // Skip to: 13161 +/* 1436 */ MCD_OPC_CheckField, 20, 4, 0, 198, 45, 0, // Skip to: 13161 +/* 1443 */ MCD_OPC_CheckField, 0, 16, 15, 191, 45, 0, // Skip to: 13161 +/* 1450 */ MCD_OPC_Decode, 245, 8, 205, 1, // Opcode: AE_MULZAAD24_HH_LL +/* 1455 */ MCD_OPC_FilterValue, 128, 96, 180, 45, 0, // Skip to: 13161 +/* 1461 */ MCD_OPC_CheckPredicate, 24, 175, 45, 0, // Skip to: 13161 +/* 1466 */ MCD_OPC_CheckField, 28, 4, 0, 168, 45, 0, // Skip to: 13161 +/* 1473 */ MCD_OPC_CheckField, 20, 4, 0, 161, 45, 0, // Skip to: 13161 +/* 1480 */ MCD_OPC_CheckField, 0, 16, 15, 154, 45, 0, // Skip to: 13161 +/* 1487 */ MCD_OPC_Decode, 247, 8, 205, 1, // Opcode: AE_MULZAAD24_HL_LH +/* 1492 */ MCD_OPC_FilterValue, 49, 39, 0, 0, // Skip to: 1536 +/* 1497 */ MCD_OPC_CheckPredicate, 24, 139, 45, 0, // Skip to: 13161 +/* 1502 */ MCD_OPC_CheckField, 36, 14, 128, 96, 131, 45, 0, // Skip to: 13161 +/* 1510 */ MCD_OPC_CheckField, 28, 4, 0, 124, 45, 0, // Skip to: 13161 +/* 1517 */ MCD_OPC_CheckField, 20, 4, 0, 117, 45, 0, // Skip to: 13161 +/* 1524 */ MCD_OPC_CheckField, 0, 16, 15, 110, 45, 0, // Skip to: 13161 +/* 1531 */ MCD_OPC_Decode, 135, 9, 205, 1, // Opcode: AE_MULZAAFD24_HH_LL +/* 1536 */ MCD_OPC_FilterValue, 50, 38, 0, 0, // Skip to: 1579 +/* 1541 */ MCD_OPC_CheckPredicate, 24, 95, 45, 0, // Skip to: 13161 +/* 1546 */ MCD_OPC_CheckField, 36, 14, 0, 88, 45, 0, // Skip to: 13161 +/* 1553 */ MCD_OPC_CheckField, 28, 4, 0, 81, 45, 0, // Skip to: 13161 +/* 1560 */ MCD_OPC_CheckField, 20, 4, 0, 74, 45, 0, // Skip to: 13161 +/* 1567 */ MCD_OPC_CheckField, 0, 16, 15, 67, 45, 0, // Skip to: 13161 +/* 1574 */ MCD_OPC_Decode, 137, 9, 205, 1, // Opcode: AE_MULZAAFD24_HL_LH +/* 1579 */ MCD_OPC_FilterValue, 51, 77, 0, 0, // Skip to: 1661 +/* 1584 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 1587 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1624 +/* 1593 */ MCD_OPC_CheckPredicate, 24, 43, 45, 0, // Skip to: 13161 +/* 1598 */ MCD_OPC_CheckField, 28, 4, 0, 36, 45, 0, // Skip to: 13161 +/* 1605 */ MCD_OPC_CheckField, 20, 4, 0, 29, 45, 0, // Skip to: 13161 +/* 1612 */ MCD_OPC_CheckField, 0, 16, 15, 22, 45, 0, // Skip to: 13161 +/* 1619 */ MCD_OPC_Decode, 147, 9, 205, 1, // Opcode: AE_MULZASD24_HH_LL +/* 1624 */ MCD_OPC_FilterValue, 128, 64, 11, 45, 0, // Skip to: 13161 +/* 1630 */ MCD_OPC_CheckPredicate, 24, 6, 45, 0, // Skip to: 13161 +/* 1635 */ MCD_OPC_CheckField, 28, 4, 0, 255, 44, 0, // Skip to: 13161 +/* 1642 */ MCD_OPC_CheckField, 20, 4, 0, 248, 44, 0, // Skip to: 13161 +/* 1649 */ MCD_OPC_CheckField, 0, 16, 15, 241, 44, 0, // Skip to: 13161 +/* 1656 */ MCD_OPC_Decode, 149, 9, 205, 1, // Opcode: AE_MULZASD24_HL_LH +/* 1661 */ MCD_OPC_FilterValue, 52, 77, 0, 0, // Skip to: 1743 +/* 1666 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 1669 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1706 +/* 1675 */ MCD_OPC_CheckPredicate, 24, 217, 44, 0, // Skip to: 13161 +/* 1680 */ MCD_OPC_CheckField, 28, 4, 0, 210, 44, 0, // Skip to: 13161 +/* 1687 */ MCD_OPC_CheckField, 20, 4, 0, 203, 44, 0, // Skip to: 13161 +/* 1694 */ MCD_OPC_CheckField, 0, 16, 15, 196, 44, 0, // Skip to: 13161 +/* 1701 */ MCD_OPC_Decode, 155, 9, 205, 1, // Opcode: AE_MULZASFD24_HH_LL +/* 1706 */ MCD_OPC_FilterValue, 128, 64, 185, 44, 0, // Skip to: 13161 +/* 1712 */ MCD_OPC_CheckPredicate, 24, 180, 44, 0, // Skip to: 13161 +/* 1717 */ MCD_OPC_CheckField, 28, 4, 0, 173, 44, 0, // Skip to: 13161 +/* 1724 */ MCD_OPC_CheckField, 20, 4, 0, 166, 44, 0, // Skip to: 13161 +/* 1731 */ MCD_OPC_CheckField, 0, 16, 15, 159, 44, 0, // Skip to: 13161 +/* 1738 */ MCD_OPC_Decode, 157, 9, 205, 1, // Opcode: AE_MULZASFD24_HL_LH +/* 1743 */ MCD_OPC_FilterValue, 53, 77, 0, 0, // Skip to: 1825 +/* 1748 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 1751 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1788 +/* 1757 */ MCD_OPC_CheckPredicate, 24, 135, 44, 0, // Skip to: 13161 +/* 1762 */ MCD_OPC_CheckField, 28, 4, 0, 128, 44, 0, // Skip to: 13161 +/* 1769 */ MCD_OPC_CheckField, 20, 4, 0, 121, 44, 0, // Skip to: 13161 +/* 1776 */ MCD_OPC_CheckField, 0, 16, 15, 114, 44, 0, // Skip to: 13161 +/* 1783 */ MCD_OPC_Decode, 163, 9, 205, 1, // Opcode: AE_MULZSAD24_HH_LL +/* 1788 */ MCD_OPC_FilterValue, 128, 64, 103, 44, 0, // Skip to: 13161 +/* 1794 */ MCD_OPC_CheckPredicate, 24, 98, 44, 0, // Skip to: 13161 +/* 1799 */ MCD_OPC_CheckField, 28, 4, 0, 91, 44, 0, // Skip to: 13161 +/* 1806 */ MCD_OPC_CheckField, 20, 4, 0, 84, 44, 0, // Skip to: 13161 +/* 1813 */ MCD_OPC_CheckField, 0, 16, 15, 77, 44, 0, // Skip to: 13161 +/* 1820 */ MCD_OPC_Decode, 169, 9, 205, 1, // Opcode: AE_MULZSAFD24_HH_LL +/* 1825 */ MCD_OPC_FilterValue, 54, 77, 0, 0, // Skip to: 1907 +/* 1830 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 1833 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1870 +/* 1839 */ MCD_OPC_CheckPredicate, 24, 53, 44, 0, // Skip to: 13161 +/* 1844 */ MCD_OPC_CheckField, 28, 4, 0, 46, 44, 0, // Skip to: 13161 +/* 1851 */ MCD_OPC_CheckField, 20, 4, 0, 39, 44, 0, // Skip to: 13161 +/* 1858 */ MCD_OPC_CheckField, 0, 16, 15, 32, 44, 0, // Skip to: 13161 +/* 1865 */ MCD_OPC_Decode, 175, 9, 205, 1, // Opcode: AE_MULZSSD24_HH_LL +/* 1870 */ MCD_OPC_FilterValue, 128, 64, 21, 44, 0, // Skip to: 13161 +/* 1876 */ MCD_OPC_CheckPredicate, 24, 16, 44, 0, // Skip to: 13161 +/* 1881 */ MCD_OPC_CheckField, 28, 4, 0, 9, 44, 0, // Skip to: 13161 +/* 1888 */ MCD_OPC_CheckField, 20, 4, 0, 2, 44, 0, // Skip to: 13161 +/* 1895 */ MCD_OPC_CheckField, 0, 16, 15, 251, 43, 0, // Skip to: 13161 +/* 1902 */ MCD_OPC_Decode, 177, 9, 205, 1, // Opcode: AE_MULZSSD24_HL_LH +/* 1907 */ MCD_OPC_FilterValue, 56, 76, 0, 0, // Skip to: 1988 +/* 1912 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 1915 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1951 +/* 1920 */ MCD_OPC_CheckPredicate, 24, 228, 43, 0, // Skip to: 13161 +/* 1925 */ MCD_OPC_CheckField, 28, 4, 0, 221, 43, 0, // Skip to: 13161 +/* 1932 */ MCD_OPC_CheckField, 20, 4, 0, 214, 43, 0, // Skip to: 13161 +/* 1939 */ MCD_OPC_CheckField, 0, 16, 15, 207, 43, 0, // Skip to: 13161 +/* 1946 */ MCD_OPC_Decode, 189, 9, 205, 1, // Opcode: AE_MULZSSFD24_HH_LL +/* 1951 */ MCD_OPC_FilterValue, 128, 32, 196, 43, 0, // Skip to: 13161 +/* 1957 */ MCD_OPC_CheckPredicate, 24, 191, 43, 0, // Skip to: 13161 +/* 1962 */ MCD_OPC_CheckField, 28, 4, 0, 184, 43, 0, // Skip to: 13161 +/* 1969 */ MCD_OPC_CheckField, 20, 4, 0, 177, 43, 0, // Skip to: 13161 +/* 1976 */ MCD_OPC_CheckField, 0, 16, 15, 170, 43, 0, // Skip to: 13161 +/* 1983 */ MCD_OPC_Decode, 191, 9, 205, 1, // Opcode: AE_MULZSSFD24_HL_LH +/* 1988 */ MCD_OPC_FilterValue, 57, 38, 0, 0, // Skip to: 2031 +/* 1993 */ MCD_OPC_CheckPredicate, 24, 155, 43, 0, // Skip to: 13161 +/* 1998 */ MCD_OPC_CheckField, 36, 14, 0, 148, 43, 0, // Skip to: 13161 +/* 2005 */ MCD_OPC_CheckField, 28, 4, 0, 141, 43, 0, // Skip to: 13161 +/* 2012 */ MCD_OPC_CheckField, 20, 4, 0, 134, 43, 0, // Skip to: 13161 +/* 2019 */ MCD_OPC_CheckField, 0, 16, 15, 127, 43, 0, // Skip to: 13161 +/* 2026 */ MCD_OPC_Decode, 216, 4, 205, 1, // Opcode: AE_ADD16 +/* 2031 */ MCD_OPC_FilterValue, 58, 77, 0, 0, // Skip to: 2113 +/* 2036 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 2039 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 2076 +/* 2045 */ MCD_OPC_CheckPredicate, 24, 103, 43, 0, // Skip to: 13161 +/* 2050 */ MCD_OPC_CheckField, 28, 4, 0, 96, 43, 0, // Skip to: 13161 +/* 2057 */ MCD_OPC_CheckField, 20, 4, 0, 89, 43, 0, // Skip to: 13161 +/* 2064 */ MCD_OPC_CheckField, 0, 16, 15, 82, 43, 0, // Skip to: 13161 +/* 2071 */ MCD_OPC_Decode, 221, 4, 205, 1, // Opcode: AE_ADD32_HL_LH +/* 2076 */ MCD_OPC_FilterValue, 128, 96, 71, 43, 0, // Skip to: 13161 +/* 2082 */ MCD_OPC_CheckPredicate, 24, 66, 43, 0, // Skip to: 13161 +/* 2087 */ MCD_OPC_CheckField, 28, 4, 0, 59, 43, 0, // Skip to: 13161 +/* 2094 */ MCD_OPC_CheckField, 20, 4, 0, 52, 43, 0, // Skip to: 13161 +/* 2101 */ MCD_OPC_CheckField, 0, 16, 15, 45, 43, 0, // Skip to: 13161 +/* 2108 */ MCD_OPC_Decode, 223, 4, 205, 1, // Opcode: AE_ADD64S +/* 2113 */ MCD_OPC_FilterValue, 59, 114, 0, 0, // Skip to: 2232 +/* 2118 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 2121 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 2158 +/* 2127 */ MCD_OPC_CheckPredicate, 24, 21, 43, 0, // Skip to: 13161 +/* 2132 */ MCD_OPC_CheckField, 28, 4, 0, 14, 43, 0, // Skip to: 13161 +/* 2139 */ MCD_OPC_CheckField, 20, 4, 0, 7, 43, 0, // Skip to: 13161 +/* 2146 */ MCD_OPC_CheckField, 0, 16, 15, 0, 43, 0, // Skip to: 13161 +/* 2153 */ MCD_OPC_Decode, 225, 4, 205, 1, // Opcode: AE_ADDSUB32 +/* 2158 */ MCD_OPC_FilterValue, 128, 64, 31, 0, 0, // Skip to: 2195 +/* 2164 */ MCD_OPC_CheckPredicate, 24, 240, 42, 0, // Skip to: 13161 +/* 2169 */ MCD_OPC_CheckField, 28, 4, 0, 233, 42, 0, // Skip to: 13161 +/* 2176 */ MCD_OPC_CheckField, 20, 4, 0, 226, 42, 0, // Skip to: 13161 +/* 2183 */ MCD_OPC_CheckField, 0, 16, 15, 219, 42, 0, // Skip to: 13161 +/* 2190 */ MCD_OPC_Decode, 226, 4, 205, 1, // Opcode: AE_ADDSUB32S +/* 2195 */ MCD_OPC_FilterValue, 128, 96, 208, 42, 0, // Skip to: 13161 +/* 2201 */ MCD_OPC_CheckPredicate, 24, 203, 42, 0, // Skip to: 13161 +/* 2206 */ MCD_OPC_CheckField, 28, 4, 0, 196, 42, 0, // Skip to: 13161 +/* 2213 */ MCD_OPC_CheckField, 20, 4, 0, 189, 42, 0, // Skip to: 13161 +/* 2220 */ MCD_OPC_CheckField, 0, 16, 15, 182, 42, 0, // Skip to: 13161 +/* 2227 */ MCD_OPC_Decode, 253, 10, 205, 1, // Opcode: AE_SUB16 +/* 2232 */ MCD_OPC_FilterValue, 60, 39, 0, 0, // Skip to: 2276 +/* 2237 */ MCD_OPC_CheckPredicate, 24, 167, 42, 0, // Skip to: 13161 +/* 2242 */ MCD_OPC_CheckField, 36, 14, 128, 32, 159, 42, 0, // Skip to: 13161 +/* 2250 */ MCD_OPC_CheckField, 28, 4, 0, 152, 42, 0, // Skip to: 13161 +/* 2257 */ MCD_OPC_CheckField, 20, 4, 0, 145, 42, 0, // Skip to: 13161 +/* 2264 */ MCD_OPC_CheckField, 0, 16, 15, 138, 42, 0, // Skip to: 13161 +/* 2271 */ MCD_OPC_Decode, 255, 10, 205, 1, // Opcode: AE_SUB24S +/* 2276 */ MCD_OPC_FilterValue, 61, 114, 0, 0, // Skip to: 2395 +/* 2281 */ MCD_OPC_ExtractField, 36, 14, // Inst{49-36} ... +/* 2284 */ MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 2321 +/* 2290 */ MCD_OPC_CheckPredicate, 24, 114, 42, 0, // Skip to: 13161 +/* 2295 */ MCD_OPC_CheckField, 28, 4, 0, 107, 42, 0, // Skip to: 13161 +/* 2302 */ MCD_OPC_CheckField, 20, 4, 0, 100, 42, 0, // Skip to: 13161 +/* 2309 */ MCD_OPC_CheckField, 0, 16, 15, 93, 42, 0, // Skip to: 13161 +/* 2316 */ MCD_OPC_Decode, 131, 11, 205, 1, // Opcode: AE_SUB64S +/* 2321 */ MCD_OPC_FilterValue, 128, 64, 31, 0, 0, // Skip to: 2358 +/* 2327 */ MCD_OPC_CheckPredicate, 24, 77, 42, 0, // Skip to: 13161 +/* 2332 */ MCD_OPC_CheckField, 28, 4, 0, 70, 42, 0, // Skip to: 13161 +/* 2339 */ MCD_OPC_CheckField, 20, 4, 0, 63, 42, 0, // Skip to: 13161 +/* 2346 */ MCD_OPC_CheckField, 0, 16, 15, 56, 42, 0, // Skip to: 13161 +/* 2353 */ MCD_OPC_Decode, 132, 11, 205, 1, // Opcode: AE_SUBADD32 +/* 2358 */ MCD_OPC_FilterValue, 128, 96, 45, 42, 0, // Skip to: 13161 +/* 2364 */ MCD_OPC_CheckPredicate, 24, 40, 42, 0, // Skip to: 13161 +/* 2369 */ MCD_OPC_CheckField, 28, 4, 0, 33, 42, 0, // Skip to: 13161 +/* 2376 */ MCD_OPC_CheckField, 20, 4, 0, 26, 42, 0, // Skip to: 13161 +/* 2383 */ MCD_OPC_CheckField, 0, 16, 15, 19, 42, 0, // Skip to: 13161 +/* 2390 */ MCD_OPC_Decode, 133, 11, 205, 1, // Opcode: AE_SUBADD32S +/* 2395 */ MCD_OPC_FilterValue, 62, 156, 0, 0, // Skip to: 2556 +/* 2400 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 2403 */ MCD_OPC_FilterValue, 32, 25, 0, 0, // Skip to: 2433 +/* 2408 */ MCD_OPC_CheckPredicate, 24, 252, 41, 0, // Skip to: 13161 +/* 2413 */ MCD_OPC_CheckField, 36, 14, 128, 96, 244, 41, 0, // Skip to: 13161 +/* 2421 */ MCD_OPC_CheckField, 0, 16, 15, 237, 41, 0, // Skip to: 13161 +/* 2428 */ MCD_OPC_Decode, 212, 4, 209, 1, // Opcode: AE_ABS32 +/* 2433 */ MCD_OPC_FilterValue, 80, 25, 0, 0, // Skip to: 2463 +/* 2438 */ MCD_OPC_CheckPredicate, 24, 222, 41, 0, // Skip to: 13161 +/* 2443 */ MCD_OPC_CheckField, 36, 14, 128, 96, 214, 41, 0, // Skip to: 13161 +/* 2451 */ MCD_OPC_CheckField, 0, 16, 15, 207, 41, 0, // Skip to: 13161 +/* 2458 */ MCD_OPC_Decode, 215, 4, 209, 1, // Opcode: AE_ABS64S +/* 2463 */ MCD_OPC_FilterValue, 128, 1, 25, 0, 0, // Skip to: 2494 +/* 2469 */ MCD_OPC_CheckPredicate, 24, 191, 41, 0, // Skip to: 13161 +/* 2474 */ MCD_OPC_CheckField, 36, 14, 128, 96, 183, 41, 0, // Skip to: 13161 +/* 2482 */ MCD_OPC_CheckField, 0, 16, 15, 176, 41, 0, // Skip to: 13161 +/* 2489 */ MCD_OPC_Decode, 199, 9, 209, 1, // Opcode: AE_NEG24S +/* 2494 */ MCD_OPC_FilterValue, 144, 1, 25, 0, 0, // Skip to: 2525 +/* 2500 */ MCD_OPC_CheckPredicate, 24, 160, 41, 0, // Skip to: 13161 +/* 2505 */ MCD_OPC_CheckField, 36, 14, 128, 96, 152, 41, 0, // Skip to: 13161 +/* 2513 */ MCD_OPC_CheckField, 0, 16, 15, 145, 41, 0, // Skip to: 13161 +/* 2520 */ MCD_OPC_Decode, 200, 9, 209, 1, // Opcode: AE_NEG32 +/* 2525 */ MCD_OPC_FilterValue, 192, 1, 134, 41, 0, // Skip to: 13161 +/* 2531 */ MCD_OPC_CheckPredicate, 24, 129, 41, 0, // Skip to: 13161 +/* 2536 */ MCD_OPC_CheckField, 36, 14, 128, 96, 121, 41, 0, // Skip to: 13161 +/* 2544 */ MCD_OPC_CheckField, 0, 16, 15, 114, 41, 0, // Skip to: 13161 +/* 2551 */ MCD_OPC_Decode, 203, 9, 209, 1, // Opcode: AE_NEG64S +/* 2556 */ MCD_OPC_FilterValue, 64, 31, 0, 0, // Skip to: 2592 +/* 2561 */ MCD_OPC_CheckPredicate, 24, 99, 41, 0, // Skip to: 13161 +/* 2566 */ MCD_OPC_CheckField, 40, 10, 0, 92, 41, 0, // Skip to: 13161 +/* 2573 */ MCD_OPC_CheckField, 28, 4, 0, 85, 41, 0, // Skip to: 13161 +/* 2580 */ MCD_OPC_CheckField, 0, 16, 14, 78, 41, 0, // Skip to: 13161 +/* 2587 */ MCD_OPC_Decode, 239, 6, 202, 1, // Opcode: AE_MULAFD24X2_FIR_L +/* 2592 */ MCD_OPC_FilterValue, 128, 1, 31, 0, 0, // Skip to: 2629 +/* 2598 */ MCD_OPC_CheckPredicate, 24, 62, 41, 0, // Skip to: 13161 +/* 2603 */ MCD_OPC_CheckField, 40, 10, 0, 55, 41, 0, // Skip to: 13161 +/* 2610 */ MCD_OPC_CheckField, 28, 4, 0, 48, 41, 0, // Skip to: 13161 +/* 2617 */ MCD_OPC_CheckField, 0, 16, 14, 41, 41, 0, // Skip to: 13161 +/* 2624 */ MCD_OPC_Decode, 240, 6, 202, 1, // Opcode: AE_MULAFD32X16X2_FIR_HH +/* 2629 */ MCD_OPC_FilterValue, 192, 1, 30, 41, 0, // Skip to: 13161 +/* 2635 */ MCD_OPC_CheckPredicate, 24, 25, 41, 0, // Skip to: 13161 +/* 2640 */ MCD_OPC_CheckField, 40, 10, 0, 18, 41, 0, // Skip to: 13161 +/* 2647 */ MCD_OPC_CheckField, 28, 4, 0, 11, 41, 0, // Skip to: 13161 +/* 2654 */ MCD_OPC_CheckField, 0, 16, 14, 4, 41, 0, // Skip to: 13161 +/* 2661 */ MCD_OPC_Decode, 241, 6, 202, 1, // Opcode: AE_MULAFD32X16X2_FIR_HL +/* 2666 */ MCD_OPC_FilterValue, 1, 148, 0, 0, // Skip to: 2819 +/* 2671 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 2674 */ MCD_OPC_FilterValue, 14, 97, 0, 0, // Skip to: 2776 +/* 2679 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 2682 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2704 +/* 2687 */ MCD_OPC_CheckPredicate, 24, 229, 40, 0, // Skip to: 13161 +/* 2692 */ MCD_OPC_CheckField, 28, 4, 0, 222, 40, 0, // Skip to: 13161 +/* 2699 */ MCD_OPC_Decode, 242, 6, 202, 1, // Opcode: AE_MULAFD32X16X2_FIR_LH +/* 2704 */ MCD_OPC_FilterValue, 128, 128, 4, 17, 0, 0, // Skip to: 2728 +/* 2711 */ MCD_OPC_CheckPredicate, 24, 205, 40, 0, // Skip to: 13161 +/* 2716 */ MCD_OPC_CheckField, 28, 4, 0, 198, 40, 0, // Skip to: 13161 +/* 2723 */ MCD_OPC_Decode, 243, 6, 202, 1, // Opcode: AE_MULAFD32X16X2_FIR_LL +/* 2728 */ MCD_OPC_FilterValue, 128, 128, 8, 17, 0, 0, // Skip to: 2752 +/* 2735 */ MCD_OPC_CheckPredicate, 24, 181, 40, 0, // Skip to: 13161 +/* 2740 */ MCD_OPC_CheckField, 28, 4, 0, 174, 40, 0, // Skip to: 13161 +/* 2747 */ MCD_OPC_Decode, 209, 7, 210, 1, // Opcode: AE_MULFD24X2_FIR_H +/* 2752 */ MCD_OPC_FilterValue, 128, 128, 12, 162, 40, 0, // Skip to: 13161 +/* 2759 */ MCD_OPC_CheckPredicate, 24, 157, 40, 0, // Skip to: 13161 +/* 2764 */ MCD_OPC_CheckField, 28, 4, 0, 150, 40, 0, // Skip to: 13161 +/* 2771 */ MCD_OPC_Decode, 210, 7, 210, 1, // Opcode: AE_MULFD24X2_FIR_L +/* 2776 */ MCD_OPC_FilterValue, 15, 140, 40, 0, // Skip to: 13161 +/* 2781 */ MCD_OPC_CheckPredicate, 24, 135, 40, 0, // Skip to: 13161 +/* 2786 */ MCD_OPC_CheckField, 40, 16, 0, 128, 40, 0, // Skip to: 13161 +/* 2793 */ MCD_OPC_CheckField, 32, 4, 0, 121, 40, 0, // Skip to: 13161 +/* 2800 */ MCD_OPC_CheckField, 24, 4, 0, 114, 40, 0, // Skip to: 13161 +/* 2807 */ MCD_OPC_CheckField, 16, 4, 0, 107, 40, 0, // Skip to: 13161 +/* 2814 */ MCD_OPC_Decode, 219, 10, 211, 1, // Opcode: AE_SLAI64S +/* 2819 */ MCD_OPC_FilterValue, 2, 125, 0, 0, // Skip to: 2949 +/* 2824 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 2827 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2856 +/* 2832 */ MCD_OPC_CheckPredicate, 24, 84, 40, 0, // Skip to: 13161 +/* 2837 */ MCD_OPC_CheckField, 28, 4, 0, 77, 40, 0, // Skip to: 13161 +/* 2844 */ MCD_OPC_CheckField, 0, 16, 14, 70, 40, 0, // Skip to: 13161 +/* 2851 */ MCD_OPC_Decode, 211, 7, 210, 1, // Opcode: AE_MULFD32X16X2_FIR_HH +/* 2856 */ MCD_OPC_FilterValue, 128, 128, 4, 24, 0, 0, // Skip to: 2887 +/* 2863 */ MCD_OPC_CheckPredicate, 24, 53, 40, 0, // Skip to: 13161 +/* 2868 */ MCD_OPC_CheckField, 28, 4, 0, 46, 40, 0, // Skip to: 13161 +/* 2875 */ MCD_OPC_CheckField, 0, 16, 14, 39, 40, 0, // Skip to: 13161 +/* 2882 */ MCD_OPC_Decode, 212, 7, 210, 1, // Opcode: AE_MULFD32X16X2_FIR_HL +/* 2887 */ MCD_OPC_FilterValue, 128, 128, 8, 24, 0, 0, // Skip to: 2918 +/* 2894 */ MCD_OPC_CheckPredicate, 24, 22, 40, 0, // Skip to: 13161 +/* 2899 */ MCD_OPC_CheckField, 28, 4, 0, 15, 40, 0, // Skip to: 13161 +/* 2906 */ MCD_OPC_CheckField, 0, 16, 14, 8, 40, 0, // Skip to: 13161 +/* 2913 */ MCD_OPC_Decode, 213, 7, 210, 1, // Opcode: AE_MULFD32X16X2_FIR_LH +/* 2918 */ MCD_OPC_FilterValue, 128, 128, 12, 252, 39, 0, // Skip to: 13161 +/* 2925 */ MCD_OPC_CheckPredicate, 24, 247, 39, 0, // Skip to: 13161 +/* 2930 */ MCD_OPC_CheckField, 28, 4, 0, 240, 39, 0, // Skip to: 13161 +/* 2937 */ MCD_OPC_CheckField, 0, 16, 14, 233, 39, 0, // Skip to: 13161 +/* 2944 */ MCD_OPC_Decode, 214, 7, 210, 1, // Opcode: AE_MULFD32X16X2_FIR_LL +/* 2949 */ MCD_OPC_FilterValue, 3, 231, 4, 0, // Skip to: 4209 +/* 2954 */ MCD_OPC_ExtractField, 36, 22, // Inst{57-36} ... +/* 2957 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2986 +/* 2962 */ MCD_OPC_CheckPredicate, 24, 210, 39, 0, // Skip to: 13161 +/* 2967 */ MCD_OPC_CheckField, 28, 4, 0, 203, 39, 0, // Skip to: 13161 +/* 2974 */ MCD_OPC_CheckField, 0, 16, 14, 196, 39, 0, // Skip to: 13161 +/* 2981 */ MCD_OPC_Decode, 246, 5, 212, 1, // Opcode: AE_MUL16X4 +/* 2986 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3015 +/* 2991 */ MCD_OPC_CheckPredicate, 24, 181, 39, 0, // Skip to: 13161 +/* 2996 */ MCD_OPC_CheckField, 28, 4, 0, 174, 39, 0, // Skip to: 13161 +/* 3003 */ MCD_OPC_CheckField, 0, 16, 14, 167, 39, 0, // Skip to: 13161 +/* 3010 */ MCD_OPC_Decode, 206, 6, 213, 1, // Opcode: AE_MULAF16X4SS +/* 3015 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 3044 +/* 3020 */ MCD_OPC_CheckPredicate, 24, 152, 39, 0, // Skip to: 13161 +/* 3025 */ MCD_OPC_CheckField, 28, 4, 0, 145, 39, 0, // Skip to: 13161 +/* 3032 */ MCD_OPC_CheckField, 0, 16, 14, 138, 39, 0, // Skip to: 13161 +/* 3039 */ MCD_OPC_Decode, 242, 7, 213, 1, // Opcode: AE_MULS16X4 +/* 3044 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 3110 +/* 3049 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3052 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 3081 +/* 3057 */ MCD_OPC_CheckPredicate, 24, 115, 39, 0, // Skip to: 13161 +/* 3062 */ MCD_OPC_CheckField, 28, 4, 0, 108, 39, 0, // Skip to: 13161 +/* 3069 */ MCD_OPC_CheckField, 0, 16, 14, 101, 39, 0, // Skip to: 13161 +/* 3076 */ MCD_OPC_Decode, 198, 6, 204, 1, // Opcode: AE_MULAF16SS_11 +/* 3081 */ MCD_OPC_FilterValue, 15, 91, 39, 0, // Skip to: 13161 +/* 3086 */ MCD_OPC_CheckPredicate, 24, 86, 39, 0, // Skip to: 13161 +/* 3091 */ MCD_OPC_CheckField, 28, 4, 0, 79, 39, 0, // Skip to: 13161 +/* 3098 */ MCD_OPC_CheckField, 0, 16, 14, 72, 39, 0, // Skip to: 13161 +/* 3105 */ MCD_OPC_Decode, 200, 6, 204, 1, // Opcode: AE_MULAF16SS_21 +/* 3110 */ MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 3176 +/* 3115 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3118 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3147 +/* 3123 */ MCD_OPC_CheckPredicate, 24, 49, 39, 0, // Skip to: 13161 +/* 3128 */ MCD_OPC_CheckField, 28, 4, 0, 42, 39, 0, // Skip to: 13161 +/* 3135 */ MCD_OPC_CheckField, 0, 16, 14, 35, 39, 0, // Skip to: 13161 +/* 3142 */ MCD_OPC_Decode, 202, 6, 204, 1, // Opcode: AE_MULAF16SS_30 +/* 3147 */ MCD_OPC_FilterValue, 1, 25, 39, 0, // Skip to: 13161 +/* 3152 */ MCD_OPC_CheckPredicate, 24, 20, 39, 0, // Skip to: 13161 +/* 3157 */ MCD_OPC_CheckField, 28, 4, 0, 13, 39, 0, // Skip to: 13161 +/* 3164 */ MCD_OPC_CheckField, 0, 16, 14, 6, 39, 0, // Skip to: 13161 +/* 3171 */ MCD_OPC_Decode, 204, 6, 204, 1, // Opcode: AE_MULAF16SS_32 +/* 3176 */ MCD_OPC_FilterValue, 6, 119, 0, 0, // Skip to: 3300 +/* 3181 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3184 */ MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 3213 +/* 3189 */ MCD_OPC_CheckPredicate, 24, 239, 38, 0, // Skip to: 13161 +/* 3194 */ MCD_OPC_CheckField, 28, 4, 0, 232, 38, 0, // Skip to: 13161 +/* 3201 */ MCD_OPC_CheckField, 0, 16, 14, 225, 38, 0, // Skip to: 13161 +/* 3208 */ MCD_OPC_Decode, 168, 7, 205, 1, // Opcode: AE_MULF16SS_10 +/* 3213 */ MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 3242 +/* 3218 */ MCD_OPC_CheckPredicate, 24, 210, 38, 0, // Skip to: 13161 +/* 3223 */ MCD_OPC_CheckField, 28, 4, 0, 203, 38, 0, // Skip to: 13161 +/* 3230 */ MCD_OPC_CheckField, 0, 16, 14, 196, 38, 0, // Skip to: 13161 +/* 3237 */ MCD_OPC_Decode, 170, 7, 205, 1, // Opcode: AE_MULF16SS_20 +/* 3242 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 3271 +/* 3247 */ MCD_OPC_CheckPredicate, 24, 181, 38, 0, // Skip to: 13161 +/* 3252 */ MCD_OPC_CheckField, 28, 4, 0, 174, 38, 0, // Skip to: 13161 +/* 3259 */ MCD_OPC_CheckField, 0, 16, 14, 167, 38, 0, // Skip to: 13161 +/* 3266 */ MCD_OPC_Decode, 172, 7, 205, 1, // Opcode: AE_MULF16SS_22 +/* 3271 */ MCD_OPC_FilterValue, 15, 157, 38, 0, // Skip to: 13161 +/* 3276 */ MCD_OPC_CheckPredicate, 24, 152, 38, 0, // Skip to: 13161 +/* 3281 */ MCD_OPC_CheckField, 28, 4, 0, 145, 38, 0, // Skip to: 13161 +/* 3288 */ MCD_OPC_CheckField, 0, 16, 14, 138, 38, 0, // Skip to: 13161 +/* 3295 */ MCD_OPC_Decode, 174, 7, 205, 1, // Opcode: AE_MULF16SS_31 +/* 3300 */ MCD_OPC_FilterValue, 7, 61, 0, 0, // Skip to: 3366 +/* 3305 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3308 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3337 +/* 3313 */ MCD_OPC_CheckPredicate, 24, 115, 38, 0, // Skip to: 13161 +/* 3318 */ MCD_OPC_CheckField, 28, 4, 0, 108, 38, 0, // Skip to: 13161 +/* 3325 */ MCD_OPC_CheckField, 0, 16, 14, 101, 38, 0, // Skip to: 13161 +/* 3332 */ MCD_OPC_Decode, 176, 7, 205, 1, // Opcode: AE_MULF16SS_33 +/* 3337 */ MCD_OPC_FilterValue, 10, 91, 38, 0, // Skip to: 13161 +/* 3342 */ MCD_OPC_CheckPredicate, 24, 86, 38, 0, // Skip to: 13161 +/* 3347 */ MCD_OPC_CheckField, 28, 4, 0, 79, 38, 0, // Skip to: 13161 +/* 3354 */ MCD_OPC_CheckField, 0, 16, 14, 72, 38, 0, // Skip to: 13161 +/* 3361 */ MCD_OPC_Decode, 215, 7, 205, 1, // Opcode: AE_MULFP16X4RAS +/* 3366 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 3395 +/* 3371 */ MCD_OPC_CheckPredicate, 24, 57, 38, 0, // Skip to: 13161 +/* 3376 */ MCD_OPC_CheckField, 28, 4, 0, 50, 38, 0, // Skip to: 13161 +/* 3383 */ MCD_OPC_CheckField, 0, 16, 14, 43, 38, 0, // Skip to: 13161 +/* 3390 */ MCD_OPC_Decode, 140, 6, 213, 1, // Opcode: AE_MULA16X4 +/* 3395 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 3424 +/* 3400 */ MCD_OPC_CheckPredicate, 24, 28, 38, 0, // Skip to: 13161 +/* 3405 */ MCD_OPC_CheckField, 28, 4, 0, 21, 38, 0, // Skip to: 13161 +/* 3412 */ MCD_OPC_CheckField, 0, 16, 14, 14, 38, 0, // Skip to: 13161 +/* 3419 */ MCD_OPC_Decode, 177, 7, 212, 1, // Opcode: AE_MULF16X4SS +/* 3424 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 3453 +/* 3429 */ MCD_OPC_CheckPredicate, 24, 255, 37, 0, // Skip to: 13161 +/* 3434 */ MCD_OPC_CheckField, 28, 4, 0, 248, 37, 0, // Skip to: 13161 +/* 3441 */ MCD_OPC_CheckField, 0, 16, 14, 241, 37, 0, // Skip to: 13161 +/* 3448 */ MCD_OPC_Decode, 164, 8, 213, 1, // Opcode: AE_MULSF16X4SS +/* 3453 */ MCD_OPC_FilterValue, 12, 90, 0, 0, // Skip to: 3548 +/* 3458 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3461 */ MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 3490 +/* 3466 */ MCD_OPC_CheckPredicate, 24, 218, 37, 0, // Skip to: 13161 +/* 3471 */ MCD_OPC_CheckField, 28, 4, 0, 211, 37, 0, // Skip to: 13161 +/* 3478 */ MCD_OPC_CheckField, 0, 16, 14, 204, 37, 0, // Skip to: 13161 +/* 3485 */ MCD_OPC_Decode, 197, 6, 204, 1, // Opcode: AE_MULAF16SS_10 +/* 3490 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 3519 +/* 3495 */ MCD_OPC_CheckPredicate, 24, 189, 37, 0, // Skip to: 13161 +/* 3500 */ MCD_OPC_CheckField, 28, 4, 0, 182, 37, 0, // Skip to: 13161 +/* 3507 */ MCD_OPC_CheckField, 0, 16, 14, 175, 37, 0, // Skip to: 13161 +/* 3514 */ MCD_OPC_Decode, 199, 6, 204, 1, // Opcode: AE_MULAF16SS_20 +/* 3519 */ MCD_OPC_FilterValue, 15, 165, 37, 0, // Skip to: 13161 +/* 3524 */ MCD_OPC_CheckPredicate, 24, 160, 37, 0, // Skip to: 13161 +/* 3529 */ MCD_OPC_CheckField, 28, 4, 0, 153, 37, 0, // Skip to: 13161 +/* 3536 */ MCD_OPC_CheckField, 0, 16, 14, 146, 37, 0, // Skip to: 13161 +/* 3543 */ MCD_OPC_Decode, 201, 6, 204, 1, // Opcode: AE_MULAF16SS_22 +/* 3548 */ MCD_OPC_FilterValue, 13, 61, 0, 0, // Skip to: 3614 +/* 3553 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3556 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3585 +/* 3561 */ MCD_OPC_CheckPredicate, 24, 123, 37, 0, // Skip to: 13161 +/* 3566 */ MCD_OPC_CheckField, 28, 4, 0, 116, 37, 0, // Skip to: 13161 +/* 3573 */ MCD_OPC_CheckField, 0, 16, 14, 109, 37, 0, // Skip to: 13161 +/* 3580 */ MCD_OPC_Decode, 203, 6, 204, 1, // Opcode: AE_MULAF16SS_31 +/* 3585 */ MCD_OPC_FilterValue, 1, 99, 37, 0, // Skip to: 13161 +/* 3590 */ MCD_OPC_CheckPredicate, 24, 94, 37, 0, // Skip to: 13161 +/* 3595 */ MCD_OPC_CheckField, 28, 4, 0, 87, 37, 0, // Skip to: 13161 +/* 3602 */ MCD_OPC_CheckField, 0, 16, 14, 80, 37, 0, // Skip to: 13161 +/* 3609 */ MCD_OPC_Decode, 205, 6, 204, 1, // Opcode: AE_MULAF16SS_33 +/* 3614 */ MCD_OPC_FilterValue, 14, 119, 0, 0, // Skip to: 3738 +/* 3619 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3622 */ MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 3651 +/* 3627 */ MCD_OPC_CheckPredicate, 24, 57, 37, 0, // Skip to: 13161 +/* 3632 */ MCD_OPC_CheckField, 28, 4, 0, 50, 37, 0, // Skip to: 13161 +/* 3639 */ MCD_OPC_CheckField, 0, 16, 14, 43, 37, 0, // Skip to: 13161 +/* 3646 */ MCD_OPC_Decode, 169, 7, 205, 1, // Opcode: AE_MULF16SS_11 +/* 3651 */ MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 3680 +/* 3656 */ MCD_OPC_CheckPredicate, 24, 28, 37, 0, // Skip to: 13161 +/* 3661 */ MCD_OPC_CheckField, 28, 4, 0, 21, 37, 0, // Skip to: 13161 +/* 3668 */ MCD_OPC_CheckField, 0, 16, 14, 14, 37, 0, // Skip to: 13161 +/* 3675 */ MCD_OPC_Decode, 171, 7, 205, 1, // Opcode: AE_MULF16SS_21 +/* 3680 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 3709 +/* 3685 */ MCD_OPC_CheckPredicate, 24, 255, 36, 0, // Skip to: 13161 +/* 3690 */ MCD_OPC_CheckField, 28, 4, 0, 248, 36, 0, // Skip to: 13161 +/* 3697 */ MCD_OPC_CheckField, 0, 16, 14, 241, 36, 0, // Skip to: 13161 +/* 3704 */ MCD_OPC_Decode, 173, 7, 205, 1, // Opcode: AE_MULF16SS_30 +/* 3709 */ MCD_OPC_FilterValue, 15, 231, 36, 0, // Skip to: 13161 +/* 3714 */ MCD_OPC_CheckPredicate, 24, 226, 36, 0, // Skip to: 13161 +/* 3719 */ MCD_OPC_CheckField, 28, 4, 0, 219, 36, 0, // Skip to: 13161 +/* 3726 */ MCD_OPC_CheckField, 0, 16, 14, 212, 36, 0, // Skip to: 13161 +/* 3733 */ MCD_OPC_Decode, 175, 7, 205, 1, // Opcode: AE_MULF16SS_32 +/* 3738 */ MCD_OPC_FilterValue, 15, 31, 0, 0, // Skip to: 3774 +/* 3743 */ MCD_OPC_CheckPredicate, 24, 197, 36, 0, // Skip to: 13161 +/* 3748 */ MCD_OPC_CheckField, 28, 4, 0, 190, 36, 0, // Skip to: 13161 +/* 3755 */ MCD_OPC_CheckField, 20, 4, 10, 183, 36, 0, // Skip to: 13161 +/* 3762 */ MCD_OPC_CheckField, 0, 16, 14, 176, 36, 0, // Skip to: 13161 +/* 3769 */ MCD_OPC_Decode, 216, 7, 205, 1, // Opcode: AE_MULFP16X4S +/* 3774 */ MCD_OPC_FilterValue, 128, 128, 64, 61, 0, 0, // Skip to: 3842 +/* 3781 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3784 */ MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 3813 +/* 3789 */ MCD_OPC_CheckPredicate, 24, 151, 36, 0, // Skip to: 13161 +/* 3794 */ MCD_OPC_CheckField, 28, 4, 0, 144, 36, 0, // Skip to: 13161 +/* 3801 */ MCD_OPC_CheckField, 0, 16, 14, 137, 36, 0, // Skip to: 13161 +/* 3808 */ MCD_OPC_Decode, 143, 8, 204, 1, // Opcode: AE_MULSAD32X16_H1_L0 +/* 3813 */ MCD_OPC_FilterValue, 15, 127, 36, 0, // Skip to: 13161 +/* 3818 */ MCD_OPC_CheckPredicate, 24, 122, 36, 0, // Skip to: 13161 +/* 3823 */ MCD_OPC_CheckField, 28, 4, 0, 115, 36, 0, // Skip to: 13161 +/* 3830 */ MCD_OPC_CheckField, 0, 16, 14, 108, 36, 0, // Skip to: 13161 +/* 3837 */ MCD_OPC_Decode, 155, 8, 204, 1, // Opcode: AE_MULSF16SS_10 +/* 3842 */ MCD_OPC_FilterValue, 129, 128, 64, 119, 0, 0, // Skip to: 3968 +/* 3849 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 3852 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3881 +/* 3857 */ MCD_OPC_CheckPredicate, 24, 83, 36, 0, // Skip to: 13161 +/* 3862 */ MCD_OPC_CheckField, 28, 4, 0, 76, 36, 0, // Skip to: 13161 +/* 3869 */ MCD_OPC_CheckField, 0, 16, 14, 69, 36, 0, // Skip to: 13161 +/* 3876 */ MCD_OPC_Decode, 157, 8, 204, 1, // Opcode: AE_MULSF16SS_20 +/* 3881 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3910 +/* 3886 */ MCD_OPC_CheckPredicate, 24, 54, 36, 0, // Skip to: 13161 +/* 3891 */ MCD_OPC_CheckField, 28, 4, 0, 47, 36, 0, // Skip to: 13161 +/* 3898 */ MCD_OPC_CheckField, 0, 16, 14, 40, 36, 0, // Skip to: 13161 +/* 3905 */ MCD_OPC_Decode, 159, 8, 204, 1, // Opcode: AE_MULSF16SS_22 +/* 3910 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 3939 +/* 3915 */ MCD_OPC_CheckPredicate, 24, 25, 36, 0, // Skip to: 13161 +/* 3920 */ MCD_OPC_CheckField, 28, 4, 0, 18, 36, 0, // Skip to: 13161 +/* 3927 */ MCD_OPC_CheckField, 0, 16, 14, 11, 36, 0, // Skip to: 13161 +/* 3934 */ MCD_OPC_Decode, 161, 8, 204, 1, // Opcode: AE_MULSF16SS_31 +/* 3939 */ MCD_OPC_FilterValue, 3, 1, 36, 0, // Skip to: 13161 +/* 3944 */ MCD_OPC_CheckPredicate, 24, 252, 35, 0, // Skip to: 13161 +/* 3949 */ MCD_OPC_CheckField, 28, 4, 0, 245, 35, 0, // Skip to: 13161 +/* 3956 */ MCD_OPC_CheckField, 0, 16, 14, 238, 35, 0, // Skip to: 13161 +/* 3963 */ MCD_OPC_Decode, 163, 8, 204, 1, // Opcode: AE_MULSF16SS_33 +/* 3968 */ MCD_OPC_FilterValue, 131, 128, 64, 31, 0, 0, // Skip to: 4006 +/* 3975 */ MCD_OPC_CheckPredicate, 24, 221, 35, 0, // Skip to: 13161 +/* 3980 */ MCD_OPC_CheckField, 28, 4, 0, 214, 35, 0, // Skip to: 13161 +/* 3987 */ MCD_OPC_CheckField, 20, 4, 8, 207, 35, 0, // Skip to: 13161 +/* 3994 */ MCD_OPC_CheckField, 0, 16, 14, 200, 35, 0, // Skip to: 13161 +/* 4001 */ MCD_OPC_Decode, 167, 9, 205, 1, // Opcode: AE_MULZSAD32X16_H3_L2 +/* 4006 */ MCD_OPC_FilterValue, 136, 128, 64, 61, 0, 0, // Skip to: 4074 +/* 4013 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 4016 */ MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 4045 +/* 4021 */ MCD_OPC_CheckPredicate, 24, 175, 35, 0, // Skip to: 13161 +/* 4026 */ MCD_OPC_CheckField, 28, 4, 0, 168, 35, 0, // Skip to: 13161 +/* 4033 */ MCD_OPC_CheckField, 0, 16, 14, 161, 35, 0, // Skip to: 13161 +/* 4040 */ MCD_OPC_Decode, 145, 8, 204, 1, // Opcode: AE_MULSAD32X16_H3_L2 +/* 4045 */ MCD_OPC_FilterValue, 15, 151, 35, 0, // Skip to: 13161 +/* 4050 */ MCD_OPC_CheckPredicate, 24, 146, 35, 0, // Skip to: 13161 +/* 4055 */ MCD_OPC_CheckField, 28, 4, 0, 139, 35, 0, // Skip to: 13161 +/* 4062 */ MCD_OPC_CheckField, 0, 16, 14, 132, 35, 0, // Skip to: 13161 +/* 4069 */ MCD_OPC_Decode, 156, 8, 204, 1, // Opcode: AE_MULSF16SS_11 +/* 4074 */ MCD_OPC_FilterValue, 137, 128, 64, 90, 0, 0, // Skip to: 4171 +/* 4081 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 4084 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4113 +/* 4089 */ MCD_OPC_CheckPredicate, 24, 107, 35, 0, // Skip to: 13161 +/* 4094 */ MCD_OPC_CheckField, 28, 4, 0, 100, 35, 0, // Skip to: 13161 +/* 4101 */ MCD_OPC_CheckField, 0, 16, 14, 93, 35, 0, // Skip to: 13161 +/* 4108 */ MCD_OPC_Decode, 158, 8, 204, 1, // Opcode: AE_MULSF16SS_21 +/* 4113 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 4142 +/* 4118 */ MCD_OPC_CheckPredicate, 24, 78, 35, 0, // Skip to: 13161 +/* 4123 */ MCD_OPC_CheckField, 28, 4, 0, 71, 35, 0, // Skip to: 13161 +/* 4130 */ MCD_OPC_CheckField, 0, 16, 14, 64, 35, 0, // Skip to: 13161 +/* 4137 */ MCD_OPC_Decode, 160, 8, 204, 1, // Opcode: AE_MULSF16SS_30 +/* 4142 */ MCD_OPC_FilterValue, 2, 54, 35, 0, // Skip to: 13161 +/* 4147 */ MCD_OPC_CheckPredicate, 24, 49, 35, 0, // Skip to: 13161 +/* 4152 */ MCD_OPC_CheckField, 28, 4, 0, 42, 35, 0, // Skip to: 13161 +/* 4159 */ MCD_OPC_CheckField, 0, 16, 14, 35, 35, 0, // Skip to: 13161 +/* 4166 */ MCD_OPC_Decode, 162, 8, 204, 1, // Opcode: AE_MULSF16SS_32 +/* 4171 */ MCD_OPC_FilterValue, 139, 128, 64, 23, 35, 0, // Skip to: 13161 +/* 4178 */ MCD_OPC_CheckPredicate, 24, 18, 35, 0, // Skip to: 13161 +/* 4183 */ MCD_OPC_CheckField, 28, 4, 0, 11, 35, 0, // Skip to: 13161 +/* 4190 */ MCD_OPC_CheckField, 20, 4, 7, 4, 35, 0, // Skip to: 13161 +/* 4197 */ MCD_OPC_CheckField, 0, 16, 14, 253, 34, 0, // Skip to: 13161 +/* 4204 */ MCD_OPC_Decode, 165, 9, 205, 1, // Opcode: AE_MULZSAD32X16_H1_L0 +/* 4209 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 4252 +/* 4214 */ MCD_OPC_CheckPredicate, 24, 238, 34, 0, // Skip to: 13161 +/* 4219 */ MCD_OPC_CheckField, 40, 16, 0, 231, 34, 0, // Skip to: 13161 +/* 4226 */ MCD_OPC_CheckField, 32, 4, 0, 224, 34, 0, // Skip to: 13161 +/* 4233 */ MCD_OPC_CheckField, 24, 4, 0, 217, 34, 0, // Skip to: 13161 +/* 4240 */ MCD_OPC_CheckField, 0, 20, 15, 210, 34, 0, // Skip to: 13161 +/* 4247 */ MCD_OPC_Decode, 249, 10, 211, 1, // Opcode: AE_SRLI64 +/* 4252 */ MCD_OPC_FilterValue, 8, 89, 0, 0, // Skip to: 4346 +/* 4257 */ MCD_OPC_ExtractField, 57, 1, // Inst{57} ... +/* 4260 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 4303 +/* 4265 */ MCD_OPC_CheckPredicate, 24, 187, 34, 0, // Skip to: 13161 +/* 4270 */ MCD_OPC_CheckField, 40, 16, 0, 180, 34, 0, // Skip to: 13161 +/* 4277 */ MCD_OPC_CheckField, 32, 4, 0, 173, 34, 0, // Skip to: 13161 +/* 4284 */ MCD_OPC_CheckField, 24, 4, 0, 166, 34, 0, // Skip to: 13161 +/* 4291 */ MCD_OPC_CheckField, 0, 20, 15, 159, 34, 0, // Skip to: 13161 +/* 4298 */ MCD_OPC_Decode, 240, 10, 214, 1, // Opcode: AE_SRAI32R +/* 4303 */ MCD_OPC_FilterValue, 1, 149, 34, 0, // Skip to: 13161 +/* 4308 */ MCD_OPC_CheckPredicate, 24, 144, 34, 0, // Skip to: 13161 +/* 4313 */ MCD_OPC_CheckField, 40, 16, 0, 137, 34, 0, // Skip to: 13161 +/* 4320 */ MCD_OPC_CheckField, 32, 4, 0, 130, 34, 0, // Skip to: 13161 +/* 4327 */ MCD_OPC_CheckField, 24, 4, 0, 123, 34, 0, // Skip to: 13161 +/* 4334 */ MCD_OPC_CheckField, 0, 20, 15, 116, 34, 0, // Skip to: 13161 +/* 4341 */ MCD_OPC_Decode, 247, 10, 214, 1, // Opcode: AE_SRLI24 +/* 4346 */ MCD_OPC_FilterValue, 9, 79, 0, 0, // Skip to: 4430 +/* 4351 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 4354 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 4392 +/* 4361 */ MCD_OPC_CheckPredicate, 24, 91, 34, 0, // Skip to: 13161 +/* 4366 */ MCD_OPC_CheckField, 32, 4, 0, 84, 34, 0, // Skip to: 13161 +/* 4373 */ MCD_OPC_CheckField, 24, 4, 0, 77, 34, 0, // Skip to: 13161 +/* 4380 */ MCD_OPC_CheckField, 0, 20, 15, 70, 34, 0, // Skip to: 13161 +/* 4387 */ MCD_OPC_Decode, 249, 5, 215, 1, // Opcode: AE_MUL32X16_H0_S2 +/* 4392 */ MCD_OPC_FilterValue, 128, 128, 12, 58, 34, 0, // Skip to: 13161 +/* 4399 */ MCD_OPC_CheckPredicate, 24, 53, 34, 0, // Skip to: 13161 +/* 4404 */ MCD_OPC_CheckField, 32, 4, 0, 46, 34, 0, // Skip to: 13161 +/* 4411 */ MCD_OPC_CheckField, 24, 4, 0, 39, 34, 0, // Skip to: 13161 +/* 4418 */ MCD_OPC_CheckField, 0, 20, 15, 32, 34, 0, // Skip to: 13161 +/* 4425 */ MCD_OPC_Decode, 251, 5, 215, 1, // Opcode: AE_MUL32X16_H1_S2 +/* 4430 */ MCD_OPC_FilterValue, 10, 153, 0, 0, // Skip to: 4588 +/* 4435 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 4438 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4474 +/* 4443 */ MCD_OPC_CheckPredicate, 24, 9, 34, 0, // Skip to: 13161 +/* 4448 */ MCD_OPC_CheckField, 32, 4, 0, 2, 34, 0, // Skip to: 13161 +/* 4455 */ MCD_OPC_CheckField, 24, 4, 0, 251, 33, 0, // Skip to: 13161 +/* 4462 */ MCD_OPC_CheckField, 0, 20, 15, 244, 33, 0, // Skip to: 13161 +/* 4469 */ MCD_OPC_Decode, 253, 5, 215, 1, // Opcode: AE_MUL32X16_H2_S2 +/* 4474 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 4512 +/* 4481 */ MCD_OPC_CheckPredicate, 24, 227, 33, 0, // Skip to: 13161 +/* 4486 */ MCD_OPC_CheckField, 32, 4, 0, 220, 33, 0, // Skip to: 13161 +/* 4493 */ MCD_OPC_CheckField, 24, 4, 0, 213, 33, 0, // Skip to: 13161 +/* 4500 */ MCD_OPC_CheckField, 0, 20, 15, 206, 33, 0, // Skip to: 13161 +/* 4507 */ MCD_OPC_Decode, 255, 5, 215, 1, // Opcode: AE_MUL32X16_H3_S2 +/* 4512 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 4550 +/* 4519 */ MCD_OPC_CheckPredicate, 24, 189, 33, 0, // Skip to: 13161 +/* 4524 */ MCD_OPC_CheckField, 32, 4, 0, 182, 33, 0, // Skip to: 13161 +/* 4531 */ MCD_OPC_CheckField, 24, 4, 0, 175, 33, 0, // Skip to: 13161 +/* 4538 */ MCD_OPC_CheckField, 0, 20, 15, 168, 33, 0, // Skip to: 13161 +/* 4545 */ MCD_OPC_Decode, 129, 6, 215, 1, // Opcode: AE_MUL32X16_L0_S2 +/* 4550 */ MCD_OPC_FilterValue, 128, 128, 12, 156, 33, 0, // Skip to: 13161 +/* 4557 */ MCD_OPC_CheckPredicate, 24, 151, 33, 0, // Skip to: 13161 +/* 4562 */ MCD_OPC_CheckField, 32, 4, 0, 144, 33, 0, // Skip to: 13161 +/* 4569 */ MCD_OPC_CheckField, 24, 4, 0, 137, 33, 0, // Skip to: 13161 +/* 4576 */ MCD_OPC_CheckField, 0, 20, 15, 130, 33, 0, // Skip to: 13161 +/* 4583 */ MCD_OPC_Decode, 131, 6, 215, 1, // Opcode: AE_MUL32X16_L1_S2 +/* 4588 */ MCD_OPC_FilterValue, 11, 153, 0, 0, // Skip to: 4746 +/* 4593 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 4596 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4632 +/* 4601 */ MCD_OPC_CheckPredicate, 24, 107, 33, 0, // Skip to: 13161 +/* 4606 */ MCD_OPC_CheckField, 32, 4, 0, 100, 33, 0, // Skip to: 13161 +/* 4613 */ MCD_OPC_CheckField, 24, 4, 0, 93, 33, 0, // Skip to: 13161 +/* 4620 */ MCD_OPC_CheckField, 0, 20, 15, 86, 33, 0, // Skip to: 13161 +/* 4627 */ MCD_OPC_Decode, 133, 6, 215, 1, // Opcode: AE_MUL32X16_L2_S2 +/* 4632 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 4670 +/* 4639 */ MCD_OPC_CheckPredicate, 24, 69, 33, 0, // Skip to: 13161 +/* 4644 */ MCD_OPC_CheckField, 32, 4, 0, 62, 33, 0, // Skip to: 13161 +/* 4651 */ MCD_OPC_CheckField, 24, 4, 0, 55, 33, 0, // Skip to: 13161 +/* 4658 */ MCD_OPC_CheckField, 0, 20, 15, 48, 33, 0, // Skip to: 13161 +/* 4665 */ MCD_OPC_Decode, 135, 6, 215, 1, // Opcode: AE_MUL32X16_L3_S2 +/* 4670 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 4708 +/* 4677 */ MCD_OPC_CheckPredicate, 24, 31, 33, 0, // Skip to: 13161 +/* 4682 */ MCD_OPC_CheckField, 32, 4, 0, 24, 33, 0, // Skip to: 13161 +/* 4689 */ MCD_OPC_CheckField, 24, 4, 0, 17, 33, 0, // Skip to: 13161 +/* 4696 */ MCD_OPC_CheckField, 0, 20, 15, 10, 33, 0, // Skip to: 13161 +/* 4703 */ MCD_OPC_Decode, 139, 6, 215, 1, // Opcode: AE_MUL32_LL_S2 +/* 4708 */ MCD_OPC_FilterValue, 128, 128, 12, 254, 32, 0, // Skip to: 13161 +/* 4715 */ MCD_OPC_CheckPredicate, 24, 249, 32, 0, // Skip to: 13161 +/* 4720 */ MCD_OPC_CheckField, 32, 4, 0, 242, 32, 0, // Skip to: 13161 +/* 4727 */ MCD_OPC_CheckField, 24, 4, 0, 235, 32, 0, // Skip to: 13161 +/* 4734 */ MCD_OPC_CheckField, 0, 20, 15, 228, 32, 0, // Skip to: 13161 +/* 4741 */ MCD_OPC_Decode, 143, 6, 216, 1, // Opcode: AE_MULA32X16_H0_S2 +/* 4746 */ MCD_OPC_FilterValue, 12, 153, 0, 0, // Skip to: 4904 +/* 4751 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 4754 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4790 +/* 4759 */ MCD_OPC_CheckPredicate, 24, 205, 32, 0, // Skip to: 13161 +/* 4764 */ MCD_OPC_CheckField, 32, 4, 0, 198, 32, 0, // Skip to: 13161 +/* 4771 */ MCD_OPC_CheckField, 24, 4, 0, 191, 32, 0, // Skip to: 13161 +/* 4778 */ MCD_OPC_CheckField, 0, 20, 15, 184, 32, 0, // Skip to: 13161 +/* 4785 */ MCD_OPC_Decode, 145, 6, 216, 1, // Opcode: AE_MULA32X16_H1_S2 +/* 4790 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 4828 +/* 4797 */ MCD_OPC_CheckPredicate, 24, 167, 32, 0, // Skip to: 13161 +/* 4802 */ MCD_OPC_CheckField, 32, 4, 0, 160, 32, 0, // Skip to: 13161 +/* 4809 */ MCD_OPC_CheckField, 24, 4, 0, 153, 32, 0, // Skip to: 13161 +/* 4816 */ MCD_OPC_CheckField, 0, 20, 15, 146, 32, 0, // Skip to: 13161 +/* 4823 */ MCD_OPC_Decode, 147, 6, 216, 1, // Opcode: AE_MULA32X16_H2_S2 +/* 4828 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 4866 +/* 4835 */ MCD_OPC_CheckPredicate, 24, 129, 32, 0, // Skip to: 13161 +/* 4840 */ MCD_OPC_CheckField, 32, 4, 0, 122, 32, 0, // Skip to: 13161 +/* 4847 */ MCD_OPC_CheckField, 24, 4, 0, 115, 32, 0, // Skip to: 13161 +/* 4854 */ MCD_OPC_CheckField, 0, 20, 15, 108, 32, 0, // Skip to: 13161 +/* 4861 */ MCD_OPC_Decode, 149, 6, 216, 1, // Opcode: AE_MULA32X16_H3_S2 +/* 4866 */ MCD_OPC_FilterValue, 128, 128, 12, 96, 32, 0, // Skip to: 13161 +/* 4873 */ MCD_OPC_CheckPredicate, 24, 91, 32, 0, // Skip to: 13161 +/* 4878 */ MCD_OPC_CheckField, 32, 4, 0, 84, 32, 0, // Skip to: 13161 +/* 4885 */ MCD_OPC_CheckField, 24, 4, 0, 77, 32, 0, // Skip to: 13161 +/* 4892 */ MCD_OPC_CheckField, 0, 20, 15, 70, 32, 0, // Skip to: 13161 +/* 4899 */ MCD_OPC_Decode, 151, 6, 216, 1, // Opcode: AE_MULA32X16_L0_S2 +/* 4904 */ MCD_OPC_FilterValue, 13, 153, 0, 0, // Skip to: 5062 +/* 4909 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 4912 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4948 +/* 4917 */ MCD_OPC_CheckPredicate, 24, 47, 32, 0, // Skip to: 13161 +/* 4922 */ MCD_OPC_CheckField, 32, 4, 0, 40, 32, 0, // Skip to: 13161 +/* 4929 */ MCD_OPC_CheckField, 24, 4, 0, 33, 32, 0, // Skip to: 13161 +/* 4936 */ MCD_OPC_CheckField, 0, 20, 15, 26, 32, 0, // Skip to: 13161 +/* 4943 */ MCD_OPC_Decode, 153, 6, 216, 1, // Opcode: AE_MULA32X16_L1_S2 +/* 4948 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 4986 +/* 4955 */ MCD_OPC_CheckPredicate, 24, 9, 32, 0, // Skip to: 13161 +/* 4960 */ MCD_OPC_CheckField, 32, 4, 0, 2, 32, 0, // Skip to: 13161 +/* 4967 */ MCD_OPC_CheckField, 24, 4, 0, 251, 31, 0, // Skip to: 13161 +/* 4974 */ MCD_OPC_CheckField, 0, 20, 15, 244, 31, 0, // Skip to: 13161 +/* 4981 */ MCD_OPC_Decode, 155, 6, 216, 1, // Opcode: AE_MULA32X16_L2_S2 +/* 4986 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5024 +/* 4993 */ MCD_OPC_CheckPredicate, 24, 227, 31, 0, // Skip to: 13161 +/* 4998 */ MCD_OPC_CheckField, 32, 4, 0, 220, 31, 0, // Skip to: 13161 +/* 5005 */ MCD_OPC_CheckField, 24, 4, 0, 213, 31, 0, // Skip to: 13161 +/* 5012 */ MCD_OPC_CheckField, 0, 20, 15, 206, 31, 0, // Skip to: 13161 +/* 5019 */ MCD_OPC_Decode, 157, 6, 216, 1, // Opcode: AE_MULA32X16_L3_S2 +/* 5024 */ MCD_OPC_FilterValue, 128, 128, 12, 194, 31, 0, // Skip to: 13161 +/* 5031 */ MCD_OPC_CheckPredicate, 24, 189, 31, 0, // Skip to: 13161 +/* 5036 */ MCD_OPC_CheckField, 32, 4, 0, 182, 31, 0, // Skip to: 13161 +/* 5043 */ MCD_OPC_CheckField, 24, 4, 0, 175, 31, 0, // Skip to: 13161 +/* 5050 */ MCD_OPC_CheckField, 0, 20, 15, 168, 31, 0, // Skip to: 13161 +/* 5057 */ MCD_OPC_Decode, 161, 6, 216, 1, // Opcode: AE_MULA32_LL_S2 +/* 5062 */ MCD_OPC_FilterValue, 14, 153, 0, 0, // Skip to: 5220 +/* 5067 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 5070 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5106 +/* 5075 */ MCD_OPC_CheckPredicate, 24, 145, 31, 0, // Skip to: 13161 +/* 5080 */ MCD_OPC_CheckField, 32, 4, 0, 138, 31, 0, // Skip to: 13161 +/* 5087 */ MCD_OPC_CheckField, 24, 4, 0, 131, 31, 0, // Skip to: 13161 +/* 5094 */ MCD_OPC_CheckField, 0, 20, 15, 124, 31, 0, // Skip to: 13161 +/* 5101 */ MCD_OPC_Decode, 163, 6, 216, 1, // Opcode: AE_MULAAD24_HH_LL_S2 +/* 5106 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5144 +/* 5113 */ MCD_OPC_CheckPredicate, 24, 107, 31, 0, // Skip to: 13161 +/* 5118 */ MCD_OPC_CheckField, 32, 4, 0, 100, 31, 0, // Skip to: 13161 +/* 5125 */ MCD_OPC_CheckField, 24, 4, 0, 93, 31, 0, // Skip to: 13161 +/* 5132 */ MCD_OPC_CheckField, 0, 20, 15, 86, 31, 0, // Skip to: 13161 +/* 5139 */ MCD_OPC_Decode, 165, 6, 216, 1, // Opcode: AE_MULAAD24_HL_LH_S2 +/* 5144 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5182 +/* 5151 */ MCD_OPC_CheckPredicate, 24, 69, 31, 0, // Skip to: 13161 +/* 5156 */ MCD_OPC_CheckField, 32, 4, 0, 62, 31, 0, // Skip to: 13161 +/* 5163 */ MCD_OPC_CheckField, 24, 4, 0, 55, 31, 0, // Skip to: 13161 +/* 5170 */ MCD_OPC_CheckField, 0, 20, 15, 48, 31, 0, // Skip to: 13161 +/* 5177 */ MCD_OPC_Decode, 167, 6, 216, 1, // Opcode: AE_MULAAD32X16_H0_L1_S2 +/* 5182 */ MCD_OPC_FilterValue, 128, 128, 12, 36, 31, 0, // Skip to: 13161 +/* 5189 */ MCD_OPC_CheckPredicate, 24, 31, 31, 0, // Skip to: 13161 +/* 5194 */ MCD_OPC_CheckField, 32, 4, 0, 24, 31, 0, // Skip to: 13161 +/* 5201 */ MCD_OPC_CheckField, 24, 4, 0, 17, 31, 0, // Skip to: 13161 +/* 5208 */ MCD_OPC_CheckField, 0, 20, 15, 10, 31, 0, // Skip to: 13161 +/* 5215 */ MCD_OPC_Decode, 169, 6, 216, 1, // Opcode: AE_MULAAD32X16_H1_L0_S2 +/* 5220 */ MCD_OPC_FilterValue, 15, 153, 0, 0, // Skip to: 5378 +/* 5225 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 5228 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5264 +/* 5233 */ MCD_OPC_CheckPredicate, 24, 243, 30, 0, // Skip to: 13161 +/* 5238 */ MCD_OPC_CheckField, 32, 4, 0, 236, 30, 0, // Skip to: 13161 +/* 5245 */ MCD_OPC_CheckField, 24, 4, 0, 229, 30, 0, // Skip to: 13161 +/* 5252 */ MCD_OPC_CheckField, 0, 20, 15, 222, 30, 0, // Skip to: 13161 +/* 5259 */ MCD_OPC_Decode, 171, 6, 216, 1, // Opcode: AE_MULAAD32X16_H2_L3_S2 +/* 5264 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5302 +/* 5271 */ MCD_OPC_CheckPredicate, 24, 205, 30, 0, // Skip to: 13161 +/* 5276 */ MCD_OPC_CheckField, 32, 4, 0, 198, 30, 0, // Skip to: 13161 +/* 5283 */ MCD_OPC_CheckField, 24, 4, 0, 191, 30, 0, // Skip to: 13161 +/* 5290 */ MCD_OPC_CheckField, 0, 20, 15, 184, 30, 0, // Skip to: 13161 +/* 5297 */ MCD_OPC_Decode, 173, 6, 216, 1, // Opcode: AE_MULAAD32X16_H3_L2_S2 +/* 5302 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5340 +/* 5309 */ MCD_OPC_CheckPredicate, 24, 167, 30, 0, // Skip to: 13161 +/* 5314 */ MCD_OPC_CheckField, 32, 4, 0, 160, 30, 0, // Skip to: 13161 +/* 5321 */ MCD_OPC_CheckField, 24, 4, 0, 153, 30, 0, // Skip to: 13161 +/* 5328 */ MCD_OPC_CheckField, 0, 20, 15, 146, 30, 0, // Skip to: 13161 +/* 5335 */ MCD_OPC_Decode, 175, 6, 216, 1, // Opcode: AE_MULAAFD16SS_11_00_S2 +/* 5340 */ MCD_OPC_FilterValue, 128, 128, 12, 134, 30, 0, // Skip to: 13161 +/* 5347 */ MCD_OPC_CheckPredicate, 24, 129, 30, 0, // Skip to: 13161 +/* 5352 */ MCD_OPC_CheckField, 32, 4, 0, 122, 30, 0, // Skip to: 13161 +/* 5359 */ MCD_OPC_CheckField, 24, 4, 0, 115, 30, 0, // Skip to: 13161 +/* 5366 */ MCD_OPC_CheckField, 0, 20, 15, 108, 30, 0, // Skip to: 13161 +/* 5373 */ MCD_OPC_Decode, 177, 6, 216, 1, // Opcode: AE_MULAAFD16SS_13_02_S2 +/* 5378 */ MCD_OPC_FilterValue, 16, 153, 0, 0, // Skip to: 5536 +/* 5383 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 5386 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5422 +/* 5391 */ MCD_OPC_CheckPredicate, 24, 85, 30, 0, // Skip to: 13161 +/* 5396 */ MCD_OPC_CheckField, 32, 4, 0, 78, 30, 0, // Skip to: 13161 +/* 5403 */ MCD_OPC_CheckField, 24, 4, 0, 71, 30, 0, // Skip to: 13161 +/* 5410 */ MCD_OPC_CheckField, 0, 20, 15, 64, 30, 0, // Skip to: 13161 +/* 5417 */ MCD_OPC_Decode, 179, 6, 216, 1, // Opcode: AE_MULAAFD16SS_33_22_S2 +/* 5422 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5460 +/* 5429 */ MCD_OPC_CheckPredicate, 24, 47, 30, 0, // Skip to: 13161 +/* 5434 */ MCD_OPC_CheckField, 32, 4, 0, 40, 30, 0, // Skip to: 13161 +/* 5441 */ MCD_OPC_CheckField, 24, 4, 0, 33, 30, 0, // Skip to: 13161 +/* 5448 */ MCD_OPC_CheckField, 0, 20, 15, 26, 30, 0, // Skip to: 13161 +/* 5455 */ MCD_OPC_Decode, 181, 6, 216, 1, // Opcode: AE_MULAAFD24_HH_LL_S2 +/* 5460 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5498 +/* 5467 */ MCD_OPC_CheckPredicate, 24, 9, 30, 0, // Skip to: 13161 +/* 5472 */ MCD_OPC_CheckField, 32, 4, 0, 2, 30, 0, // Skip to: 13161 +/* 5479 */ MCD_OPC_CheckField, 24, 4, 0, 251, 29, 0, // Skip to: 13161 +/* 5486 */ MCD_OPC_CheckField, 0, 20, 15, 244, 29, 0, // Skip to: 13161 +/* 5493 */ MCD_OPC_Decode, 183, 6, 216, 1, // Opcode: AE_MULAAFD24_HL_LH_S2 +/* 5498 */ MCD_OPC_FilterValue, 128, 128, 12, 232, 29, 0, // Skip to: 13161 +/* 5505 */ MCD_OPC_CheckPredicate, 24, 227, 29, 0, // Skip to: 13161 +/* 5510 */ MCD_OPC_CheckField, 32, 4, 0, 220, 29, 0, // Skip to: 13161 +/* 5517 */ MCD_OPC_CheckField, 24, 4, 0, 213, 29, 0, // Skip to: 13161 +/* 5524 */ MCD_OPC_CheckField, 0, 20, 15, 206, 29, 0, // Skip to: 13161 +/* 5531 */ MCD_OPC_Decode, 185, 6, 216, 1, // Opcode: AE_MULAAFD32X16_H0_L1_S2 +/* 5536 */ MCD_OPC_FilterValue, 17, 153, 0, 0, // Skip to: 5694 +/* 5541 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 5544 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5580 +/* 5549 */ MCD_OPC_CheckPredicate, 24, 183, 29, 0, // Skip to: 13161 +/* 5554 */ MCD_OPC_CheckField, 32, 4, 0, 176, 29, 0, // Skip to: 13161 +/* 5561 */ MCD_OPC_CheckField, 24, 4, 0, 169, 29, 0, // Skip to: 13161 +/* 5568 */ MCD_OPC_CheckField, 0, 20, 15, 162, 29, 0, // Skip to: 13161 +/* 5575 */ MCD_OPC_Decode, 187, 6, 216, 1, // Opcode: AE_MULAAFD32X16_H1_L0_S2 +/* 5580 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5618 +/* 5587 */ MCD_OPC_CheckPredicate, 24, 145, 29, 0, // Skip to: 13161 +/* 5592 */ MCD_OPC_CheckField, 32, 4, 0, 138, 29, 0, // Skip to: 13161 +/* 5599 */ MCD_OPC_CheckField, 24, 4, 0, 131, 29, 0, // Skip to: 13161 +/* 5606 */ MCD_OPC_CheckField, 0, 20, 15, 124, 29, 0, // Skip to: 13161 +/* 5613 */ MCD_OPC_Decode, 189, 6, 216, 1, // Opcode: AE_MULAAFD32X16_H2_L3_S2 +/* 5618 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5656 +/* 5625 */ MCD_OPC_CheckPredicate, 24, 107, 29, 0, // Skip to: 13161 +/* 5630 */ MCD_OPC_CheckField, 32, 4, 0, 100, 29, 0, // Skip to: 13161 +/* 5637 */ MCD_OPC_CheckField, 24, 4, 0, 93, 29, 0, // Skip to: 13161 +/* 5644 */ MCD_OPC_CheckField, 0, 20, 15, 86, 29, 0, // Skip to: 13161 +/* 5651 */ MCD_OPC_Decode, 191, 6, 216, 1, // Opcode: AE_MULAAFD32X16_H3_L2_S2 +/* 5656 */ MCD_OPC_FilterValue, 128, 128, 12, 74, 29, 0, // Skip to: 13161 +/* 5663 */ MCD_OPC_CheckPredicate, 24, 69, 29, 0, // Skip to: 13161 +/* 5668 */ MCD_OPC_CheckField, 32, 4, 0, 62, 29, 0, // Skip to: 13161 +/* 5675 */ MCD_OPC_CheckField, 24, 4, 0, 55, 29, 0, // Skip to: 13161 +/* 5682 */ MCD_OPC_CheckField, 0, 20, 15, 48, 29, 0, // Skip to: 13161 +/* 5689 */ MCD_OPC_Decode, 196, 6, 216, 1, // Opcode: AE_MULAF16SS_00_S2 +/* 5694 */ MCD_OPC_FilterValue, 18, 153, 0, 0, // Skip to: 5852 +/* 5699 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 5702 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5738 +/* 5707 */ MCD_OPC_CheckPredicate, 24, 25, 29, 0, // Skip to: 13161 +/* 5712 */ MCD_OPC_CheckField, 32, 4, 0, 18, 29, 0, // Skip to: 13161 +/* 5719 */ MCD_OPC_CheckField, 24, 4, 0, 11, 29, 0, // Skip to: 13161 +/* 5726 */ MCD_OPC_CheckField, 0, 20, 15, 4, 29, 0, // Skip to: 13161 +/* 5733 */ MCD_OPC_Decode, 210, 6, 216, 1, // Opcode: AE_MULAF32R_LL_S2 +/* 5738 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5776 +/* 5745 */ MCD_OPC_CheckPredicate, 24, 243, 28, 0, // Skip to: 13161 +/* 5750 */ MCD_OPC_CheckField, 32, 4, 0, 236, 28, 0, // Skip to: 13161 +/* 5757 */ MCD_OPC_CheckField, 24, 4, 0, 229, 28, 0, // Skip to: 13161 +/* 5764 */ MCD_OPC_CheckField, 0, 20, 15, 222, 28, 0, // Skip to: 13161 +/* 5771 */ MCD_OPC_Decode, 214, 6, 216, 1, // Opcode: AE_MULAF32S_LL_S2 +/* 5776 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5814 +/* 5783 */ MCD_OPC_CheckPredicate, 24, 205, 28, 0, // Skip to: 13161 +/* 5788 */ MCD_OPC_CheckField, 32, 4, 0, 198, 28, 0, // Skip to: 13161 +/* 5795 */ MCD_OPC_CheckField, 24, 4, 0, 191, 28, 0, // Skip to: 13161 +/* 5802 */ MCD_OPC_CheckField, 0, 20, 15, 184, 28, 0, // Skip to: 13161 +/* 5809 */ MCD_OPC_Decode, 216, 6, 216, 1, // Opcode: AE_MULAF32X16_H0_S2 +/* 5814 */ MCD_OPC_FilterValue, 128, 128, 12, 172, 28, 0, // Skip to: 13161 +/* 5821 */ MCD_OPC_CheckPredicate, 24, 167, 28, 0, // Skip to: 13161 +/* 5826 */ MCD_OPC_CheckField, 32, 4, 0, 160, 28, 0, // Skip to: 13161 +/* 5833 */ MCD_OPC_CheckField, 24, 4, 0, 153, 28, 0, // Skip to: 13161 +/* 5840 */ MCD_OPC_CheckField, 0, 20, 15, 146, 28, 0, // Skip to: 13161 +/* 5847 */ MCD_OPC_Decode, 218, 6, 216, 1, // Opcode: AE_MULAF32X16_H1_S2 +/* 5852 */ MCD_OPC_FilterValue, 19, 153, 0, 0, // Skip to: 6010 +/* 5857 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 5860 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5896 +/* 5865 */ MCD_OPC_CheckPredicate, 24, 123, 28, 0, // Skip to: 13161 +/* 5870 */ MCD_OPC_CheckField, 32, 4, 0, 116, 28, 0, // Skip to: 13161 +/* 5877 */ MCD_OPC_CheckField, 24, 4, 0, 109, 28, 0, // Skip to: 13161 +/* 5884 */ MCD_OPC_CheckField, 0, 20, 15, 102, 28, 0, // Skip to: 13161 +/* 5891 */ MCD_OPC_Decode, 220, 6, 216, 1, // Opcode: AE_MULAF32X16_H2_S2 +/* 5896 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5934 +/* 5903 */ MCD_OPC_CheckPredicate, 24, 85, 28, 0, // Skip to: 13161 +/* 5908 */ MCD_OPC_CheckField, 32, 4, 0, 78, 28, 0, // Skip to: 13161 +/* 5915 */ MCD_OPC_CheckField, 24, 4, 0, 71, 28, 0, // Skip to: 13161 +/* 5922 */ MCD_OPC_CheckField, 0, 20, 15, 64, 28, 0, // Skip to: 13161 +/* 5929 */ MCD_OPC_Decode, 222, 6, 216, 1, // Opcode: AE_MULAF32X16_H3_S2 +/* 5934 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5972 +/* 5941 */ MCD_OPC_CheckPredicate, 24, 47, 28, 0, // Skip to: 13161 +/* 5946 */ MCD_OPC_CheckField, 32, 4, 0, 40, 28, 0, // Skip to: 13161 +/* 5953 */ MCD_OPC_CheckField, 24, 4, 0, 33, 28, 0, // Skip to: 13161 +/* 5960 */ MCD_OPC_CheckField, 0, 20, 15, 26, 28, 0, // Skip to: 13161 +/* 5967 */ MCD_OPC_Decode, 224, 6, 216, 1, // Opcode: AE_MULAF32X16_L0_S2 +/* 5972 */ MCD_OPC_FilterValue, 128, 128, 12, 14, 28, 0, // Skip to: 13161 +/* 5979 */ MCD_OPC_CheckPredicate, 24, 9, 28, 0, // Skip to: 13161 +/* 5984 */ MCD_OPC_CheckField, 32, 4, 0, 2, 28, 0, // Skip to: 13161 +/* 5991 */ MCD_OPC_CheckField, 24, 4, 0, 251, 27, 0, // Skip to: 13161 +/* 5998 */ MCD_OPC_CheckField, 0, 20, 15, 244, 27, 0, // Skip to: 13161 +/* 6005 */ MCD_OPC_Decode, 226, 6, 216, 1, // Opcode: AE_MULAF32X16_L1_S2 +/* 6010 */ MCD_OPC_FilterValue, 20, 153, 0, 0, // Skip to: 6168 +/* 6015 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 6018 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6054 +/* 6023 */ MCD_OPC_CheckPredicate, 24, 221, 27, 0, // Skip to: 13161 +/* 6028 */ MCD_OPC_CheckField, 32, 4, 0, 214, 27, 0, // Skip to: 13161 +/* 6035 */ MCD_OPC_CheckField, 24, 4, 0, 207, 27, 0, // Skip to: 13161 +/* 6042 */ MCD_OPC_CheckField, 0, 20, 15, 200, 27, 0, // Skip to: 13161 +/* 6049 */ MCD_OPC_Decode, 228, 6, 216, 1, // Opcode: AE_MULAF32X16_L2_S2 +/* 6054 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6092 +/* 6061 */ MCD_OPC_CheckPredicate, 24, 183, 27, 0, // Skip to: 13161 +/* 6066 */ MCD_OPC_CheckField, 32, 4, 0, 176, 27, 0, // Skip to: 13161 +/* 6073 */ MCD_OPC_CheckField, 24, 4, 0, 169, 27, 0, // Skip to: 13161 +/* 6080 */ MCD_OPC_CheckField, 0, 20, 15, 162, 27, 0, // Skip to: 13161 +/* 6087 */ MCD_OPC_Decode, 230, 6, 216, 1, // Opcode: AE_MULAF32X16_L3_S2 +/* 6092 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6130 +/* 6099 */ MCD_OPC_CheckPredicate, 24, 145, 27, 0, // Skip to: 13161 +/* 6104 */ MCD_OPC_CheckField, 32, 4, 0, 138, 27, 0, // Skip to: 13161 +/* 6111 */ MCD_OPC_CheckField, 24, 4, 0, 131, 27, 0, // Skip to: 13161 +/* 6118 */ MCD_OPC_CheckField, 0, 20, 15, 124, 27, 0, // Skip to: 13161 +/* 6125 */ MCD_OPC_Decode, 232, 6, 216, 1, // Opcode: AE_MULAF48Q32SP16S_L_S2 +/* 6130 */ MCD_OPC_FilterValue, 128, 128, 12, 112, 27, 0, // Skip to: 13161 +/* 6137 */ MCD_OPC_CheckPredicate, 24, 107, 27, 0, // Skip to: 13161 +/* 6142 */ MCD_OPC_CheckField, 32, 4, 0, 100, 27, 0, // Skip to: 13161 +/* 6149 */ MCD_OPC_CheckField, 24, 4, 0, 93, 27, 0, // Skip to: 13161 +/* 6156 */ MCD_OPC_CheckField, 0, 20, 15, 86, 27, 0, // Skip to: 13161 +/* 6163 */ MCD_OPC_Decode, 234, 6, 216, 1, // Opcode: AE_MULAF48Q32SP16U_L_S2 +/* 6168 */ MCD_OPC_FilterValue, 21, 153, 0, 0, // Skip to: 6326 +/* 6173 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 6176 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6212 +/* 6181 */ MCD_OPC_CheckPredicate, 24, 63, 27, 0, // Skip to: 13161 +/* 6186 */ MCD_OPC_CheckField, 32, 4, 0, 56, 27, 0, // Skip to: 13161 +/* 6193 */ MCD_OPC_CheckField, 24, 4, 0, 49, 27, 0, // Skip to: 13161 +/* 6200 */ MCD_OPC_CheckField, 0, 20, 15, 42, 27, 0, // Skip to: 13161 +/* 6207 */ MCD_OPC_Decode, 246, 6, 216, 1, // Opcode: AE_MULAFP24X2RA_S2 +/* 6212 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6250 +/* 6219 */ MCD_OPC_CheckPredicate, 24, 25, 27, 0, // Skip to: 13161 +/* 6224 */ MCD_OPC_CheckField, 32, 4, 0, 18, 27, 0, // Skip to: 13161 +/* 6231 */ MCD_OPC_CheckField, 24, 4, 0, 11, 27, 0, // Skip to: 13161 +/* 6238 */ MCD_OPC_CheckField, 0, 20, 15, 4, 27, 0, // Skip to: 13161 +/* 6245 */ MCD_OPC_Decode, 247, 6, 216, 1, // Opcode: AE_MULAFP24X2R_S2 +/* 6250 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6288 +/* 6257 */ MCD_OPC_CheckPredicate, 24, 243, 26, 0, // Skip to: 13161 +/* 6262 */ MCD_OPC_CheckField, 32, 4, 0, 236, 26, 0, // Skip to: 13161 +/* 6269 */ MCD_OPC_CheckField, 24, 4, 0, 229, 26, 0, // Skip to: 13161 +/* 6276 */ MCD_OPC_CheckField, 0, 20, 15, 222, 26, 0, // Skip to: 13161 +/* 6283 */ MCD_OPC_Decode, 249, 6, 216, 1, // Opcode: AE_MULAFP32X16X2RAS_H_S2 +/* 6288 */ MCD_OPC_FilterValue, 128, 128, 12, 210, 26, 0, // Skip to: 13161 +/* 6295 */ MCD_OPC_CheckPredicate, 24, 205, 26, 0, // Skip to: 13161 +/* 6300 */ MCD_OPC_CheckField, 32, 4, 0, 198, 26, 0, // Skip to: 13161 +/* 6307 */ MCD_OPC_CheckField, 24, 4, 0, 191, 26, 0, // Skip to: 13161 +/* 6314 */ MCD_OPC_CheckField, 0, 20, 15, 184, 26, 0, // Skip to: 13161 +/* 6321 */ MCD_OPC_Decode, 251, 6, 216, 1, // Opcode: AE_MULAFP32X16X2RAS_L_S2 +/* 6326 */ MCD_OPC_FilterValue, 22, 153, 0, 0, // Skip to: 6484 +/* 6331 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 6334 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6370 +/* 6339 */ MCD_OPC_CheckPredicate, 24, 161, 26, 0, // Skip to: 13161 +/* 6344 */ MCD_OPC_CheckField, 32, 4, 0, 154, 26, 0, // Skip to: 13161 +/* 6351 */ MCD_OPC_CheckField, 24, 4, 0, 147, 26, 0, // Skip to: 13161 +/* 6358 */ MCD_OPC_CheckField, 0, 20, 15, 140, 26, 0, // Skip to: 13161 +/* 6365 */ MCD_OPC_Decode, 253, 6, 216, 1, // Opcode: AE_MULAFP32X16X2RS_H_S2 +/* 6370 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6408 +/* 6377 */ MCD_OPC_CheckPredicate, 24, 123, 26, 0, // Skip to: 13161 +/* 6382 */ MCD_OPC_CheckField, 32, 4, 0, 116, 26, 0, // Skip to: 13161 +/* 6389 */ MCD_OPC_CheckField, 24, 4, 0, 109, 26, 0, // Skip to: 13161 +/* 6396 */ MCD_OPC_CheckField, 0, 20, 15, 102, 26, 0, // Skip to: 13161 +/* 6403 */ MCD_OPC_Decode, 255, 6, 216, 1, // Opcode: AE_MULAFP32X16X2RS_L_S2 +/* 6408 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6446 +/* 6415 */ MCD_OPC_CheckPredicate, 24, 85, 26, 0, // Skip to: 13161 +/* 6420 */ MCD_OPC_CheckField, 32, 4, 0, 78, 26, 0, // Skip to: 13161 +/* 6427 */ MCD_OPC_CheckField, 24, 4, 0, 71, 26, 0, // Skip to: 13161 +/* 6434 */ MCD_OPC_CheckField, 0, 20, 15, 64, 26, 0, // Skip to: 13161 +/* 6441 */ MCD_OPC_Decode, 130, 7, 216, 1, // Opcode: AE_MULAFQ32SP24S_H_S2 +/* 6446 */ MCD_OPC_FilterValue, 128, 128, 12, 52, 26, 0, // Skip to: 13161 +/* 6453 */ MCD_OPC_CheckPredicate, 24, 47, 26, 0, // Skip to: 13161 +/* 6458 */ MCD_OPC_CheckField, 32, 4, 0, 40, 26, 0, // Skip to: 13161 +/* 6465 */ MCD_OPC_CheckField, 24, 4, 0, 33, 26, 0, // Skip to: 13161 +/* 6472 */ MCD_OPC_CheckField, 0, 20, 15, 26, 26, 0, // Skip to: 13161 +/* 6479 */ MCD_OPC_Decode, 131, 7, 216, 1, // Opcode: AE_MULAFQ32SP24S_L_S2 +/* 6484 */ MCD_OPC_FilterValue, 23, 153, 0, 0, // Skip to: 6642 +/* 6489 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 6492 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6528 +/* 6497 */ MCD_OPC_CheckPredicate, 24, 3, 26, 0, // Skip to: 13161 +/* 6502 */ MCD_OPC_CheckField, 32, 4, 0, 252, 25, 0, // Skip to: 13161 +/* 6509 */ MCD_OPC_CheckField, 24, 4, 0, 245, 25, 0, // Skip to: 13161 +/* 6516 */ MCD_OPC_CheckField, 0, 20, 15, 238, 25, 0, // Skip to: 13161 +/* 6523 */ MCD_OPC_Decode, 133, 7, 216, 1, // Opcode: AE_MULAP24X2_S2 +/* 6528 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6566 +/* 6535 */ MCD_OPC_CheckPredicate, 24, 221, 25, 0, // Skip to: 13161 +/* 6540 */ MCD_OPC_CheckField, 32, 4, 0, 214, 25, 0, // Skip to: 13161 +/* 6547 */ MCD_OPC_CheckField, 24, 4, 0, 207, 25, 0, // Skip to: 13161 +/* 6554 */ MCD_OPC_CheckField, 0, 20, 15, 200, 25, 0, // Skip to: 13161 +/* 6561 */ MCD_OPC_Decode, 137, 7, 216, 1, // Opcode: AE_MULAQ32SP16S_L_S2 +/* 6566 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6604 +/* 6573 */ MCD_OPC_CheckPredicate, 24, 183, 25, 0, // Skip to: 13161 +/* 6578 */ MCD_OPC_CheckField, 32, 4, 0, 176, 25, 0, // Skip to: 13161 +/* 6585 */ MCD_OPC_CheckField, 24, 4, 0, 169, 25, 0, // Skip to: 13161 +/* 6592 */ MCD_OPC_CheckField, 0, 20, 15, 162, 25, 0, // Skip to: 13161 +/* 6599 */ MCD_OPC_Decode, 138, 7, 216, 1, // Opcode: AE_MULAQ32SP16U_L_S2 +/* 6604 */ MCD_OPC_FilterValue, 128, 128, 12, 150, 25, 0, // Skip to: 13161 +/* 6611 */ MCD_OPC_CheckPredicate, 24, 145, 25, 0, // Skip to: 13161 +/* 6616 */ MCD_OPC_CheckField, 32, 4, 0, 138, 25, 0, // Skip to: 13161 +/* 6623 */ MCD_OPC_CheckField, 24, 4, 0, 131, 25, 0, // Skip to: 13161 +/* 6630 */ MCD_OPC_CheckField, 0, 20, 15, 124, 25, 0, // Skip to: 13161 +/* 6637 */ MCD_OPC_Decode, 139, 7, 216, 1, // Opcode: AE_MULARFQ32SP24S_H_S2 +/* 6642 */ MCD_OPC_FilterValue, 24, 153, 0, 0, // Skip to: 6800 +/* 6647 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 6650 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6686 +/* 6655 */ MCD_OPC_CheckPredicate, 24, 101, 25, 0, // Skip to: 13161 +/* 6660 */ MCD_OPC_CheckField, 32, 4, 0, 94, 25, 0, // Skip to: 13161 +/* 6667 */ MCD_OPC_CheckField, 24, 4, 0, 87, 25, 0, // Skip to: 13161 +/* 6674 */ MCD_OPC_CheckField, 0, 20, 15, 80, 25, 0, // Skip to: 13161 +/* 6681 */ MCD_OPC_Decode, 140, 7, 216, 1, // Opcode: AE_MULARFQ32SP24S_L_S2 +/* 6686 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6724 +/* 6693 */ MCD_OPC_CheckPredicate, 24, 63, 25, 0, // Skip to: 13161 +/* 6698 */ MCD_OPC_CheckField, 32, 4, 0, 56, 25, 0, // Skip to: 13161 +/* 6705 */ MCD_OPC_CheckField, 24, 4, 0, 49, 25, 0, // Skip to: 13161 +/* 6712 */ MCD_OPC_CheckField, 0, 20, 15, 42, 25, 0, // Skip to: 13161 +/* 6719 */ MCD_OPC_Decode, 142, 7, 216, 1, // Opcode: AE_MULAS32F48P16S_HH_S2 +/* 6724 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6762 +/* 6731 */ MCD_OPC_CheckPredicate, 24, 25, 25, 0, // Skip to: 13161 +/* 6736 */ MCD_OPC_CheckField, 32, 4, 0, 18, 25, 0, // Skip to: 13161 +/* 6743 */ MCD_OPC_CheckField, 24, 4, 0, 11, 25, 0, // Skip to: 13161 +/* 6750 */ MCD_OPC_CheckField, 0, 20, 15, 4, 25, 0, // Skip to: 13161 +/* 6757 */ MCD_OPC_Decode, 144, 7, 216, 1, // Opcode: AE_MULAS32F48P16S_LH_S2 +/* 6762 */ MCD_OPC_FilterValue, 128, 128, 12, 248, 24, 0, // Skip to: 13161 +/* 6769 */ MCD_OPC_CheckPredicate, 24, 243, 24, 0, // Skip to: 13161 +/* 6774 */ MCD_OPC_CheckField, 32, 4, 0, 236, 24, 0, // Skip to: 13161 +/* 6781 */ MCD_OPC_CheckField, 24, 4, 0, 229, 24, 0, // Skip to: 13161 +/* 6788 */ MCD_OPC_CheckField, 0, 20, 15, 222, 24, 0, // Skip to: 13161 +/* 6795 */ MCD_OPC_Decode, 146, 7, 216, 1, // Opcode: AE_MULAS32F48P16S_LL_S2 +/* 6800 */ MCD_OPC_FilterValue, 25, 153, 0, 0, // Skip to: 6958 +/* 6805 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 6808 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6844 +/* 6813 */ MCD_OPC_CheckPredicate, 24, 199, 24, 0, // Skip to: 13161 +/* 6818 */ MCD_OPC_CheckField, 32, 4, 0, 192, 24, 0, // Skip to: 13161 +/* 6825 */ MCD_OPC_CheckField, 24, 4, 0, 185, 24, 0, // Skip to: 13161 +/* 6832 */ MCD_OPC_CheckField, 0, 20, 15, 178, 24, 0, // Skip to: 13161 +/* 6839 */ MCD_OPC_Decode, 148, 7, 216, 1, // Opcode: AE_MULASD24_HH_LL_S2 +/* 6844 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6882 +/* 6851 */ MCD_OPC_CheckPredicate, 24, 161, 24, 0, // Skip to: 13161 +/* 6856 */ MCD_OPC_CheckField, 32, 4, 0, 154, 24, 0, // Skip to: 13161 +/* 6863 */ MCD_OPC_CheckField, 24, 4, 0, 147, 24, 0, // Skip to: 13161 +/* 6870 */ MCD_OPC_CheckField, 0, 20, 15, 140, 24, 0, // Skip to: 13161 +/* 6877 */ MCD_OPC_Decode, 150, 7, 216, 1, // Opcode: AE_MULASD24_HL_LH_S2 +/* 6882 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6920 +/* 6889 */ MCD_OPC_CheckPredicate, 24, 123, 24, 0, // Skip to: 13161 +/* 6894 */ MCD_OPC_CheckField, 32, 4, 0, 116, 24, 0, // Skip to: 13161 +/* 6901 */ MCD_OPC_CheckField, 24, 4, 0, 109, 24, 0, // Skip to: 13161 +/* 6908 */ MCD_OPC_CheckField, 0, 20, 15, 102, 24, 0, // Skip to: 13161 +/* 6915 */ MCD_OPC_Decode, 152, 7, 216, 1, // Opcode: AE_MULASD32X16_H1_L0_S2 +/* 6920 */ MCD_OPC_FilterValue, 128, 128, 12, 90, 24, 0, // Skip to: 13161 +/* 6927 */ MCD_OPC_CheckPredicate, 24, 85, 24, 0, // Skip to: 13161 +/* 6932 */ MCD_OPC_CheckField, 32, 4, 0, 78, 24, 0, // Skip to: 13161 +/* 6939 */ MCD_OPC_CheckField, 24, 4, 0, 71, 24, 0, // Skip to: 13161 +/* 6946 */ MCD_OPC_CheckField, 0, 20, 15, 64, 24, 0, // Skip to: 13161 +/* 6953 */ MCD_OPC_Decode, 154, 7, 216, 1, // Opcode: AE_MULASD32X16_H3_L2_S2 +/* 6958 */ MCD_OPC_FilterValue, 26, 153, 0, 0, // Skip to: 7116 +/* 6963 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 6966 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7002 +/* 6971 */ MCD_OPC_CheckPredicate, 24, 41, 24, 0, // Skip to: 13161 +/* 6976 */ MCD_OPC_CheckField, 32, 4, 0, 34, 24, 0, // Skip to: 13161 +/* 6983 */ MCD_OPC_CheckField, 24, 4, 0, 27, 24, 0, // Skip to: 13161 +/* 6990 */ MCD_OPC_CheckField, 0, 20, 15, 20, 24, 0, // Skip to: 13161 +/* 6997 */ MCD_OPC_Decode, 156, 7, 216, 1, // Opcode: AE_MULASFD24_HH_LL_S2 +/* 7002 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7040 +/* 7009 */ MCD_OPC_CheckPredicate, 24, 3, 24, 0, // Skip to: 13161 +/* 7014 */ MCD_OPC_CheckField, 32, 4, 0, 252, 23, 0, // Skip to: 13161 +/* 7021 */ MCD_OPC_CheckField, 24, 4, 0, 245, 23, 0, // Skip to: 13161 +/* 7028 */ MCD_OPC_CheckField, 0, 20, 15, 238, 23, 0, // Skip to: 13161 +/* 7035 */ MCD_OPC_Decode, 158, 7, 216, 1, // Opcode: AE_MULASFD24_HL_LH_S2 +/* 7040 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7078 +/* 7047 */ MCD_OPC_CheckPredicate, 24, 221, 23, 0, // Skip to: 13161 +/* 7052 */ MCD_OPC_CheckField, 32, 4, 0, 214, 23, 0, // Skip to: 13161 +/* 7059 */ MCD_OPC_CheckField, 24, 4, 0, 207, 23, 0, // Skip to: 13161 +/* 7066 */ MCD_OPC_CheckField, 0, 20, 15, 200, 23, 0, // Skip to: 13161 +/* 7073 */ MCD_OPC_Decode, 160, 7, 216, 1, // Opcode: AE_MULASFD32X16_H1_L0_S2 +/* 7078 */ MCD_OPC_FilterValue, 128, 128, 12, 188, 23, 0, // Skip to: 13161 +/* 7085 */ MCD_OPC_CheckPredicate, 24, 183, 23, 0, // Skip to: 13161 +/* 7090 */ MCD_OPC_CheckField, 32, 4, 0, 176, 23, 0, // Skip to: 13161 +/* 7097 */ MCD_OPC_CheckField, 24, 4, 0, 169, 23, 0, // Skip to: 13161 +/* 7104 */ MCD_OPC_CheckField, 0, 20, 15, 162, 23, 0, // Skip to: 13161 +/* 7111 */ MCD_OPC_Decode, 162, 7, 216, 1, // Opcode: AE_MULASFD32X16_H3_L2_S2 +/* 7116 */ MCD_OPC_FilterValue, 27, 153, 0, 0, // Skip to: 7274 +/* 7121 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 7124 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7160 +/* 7129 */ MCD_OPC_CheckPredicate, 24, 139, 23, 0, // Skip to: 13161 +/* 7134 */ MCD_OPC_CheckField, 32, 4, 0, 132, 23, 0, // Skip to: 13161 +/* 7141 */ MCD_OPC_CheckField, 24, 4, 0, 125, 23, 0, // Skip to: 13161 +/* 7148 */ MCD_OPC_CheckField, 0, 20, 15, 118, 23, 0, // Skip to: 13161 +/* 7155 */ MCD_OPC_Decode, 167, 7, 215, 1, // Opcode: AE_MULF16SS_00_S2 +/* 7160 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7198 +/* 7167 */ MCD_OPC_CheckPredicate, 24, 101, 23, 0, // Skip to: 13161 +/* 7172 */ MCD_OPC_CheckField, 32, 4, 0, 94, 23, 0, // Skip to: 13161 +/* 7179 */ MCD_OPC_CheckField, 24, 4, 0, 87, 23, 0, // Skip to: 13161 +/* 7186 */ MCD_OPC_CheckField, 0, 20, 15, 80, 23, 0, // Skip to: 13161 +/* 7193 */ MCD_OPC_Decode, 181, 7, 215, 1, // Opcode: AE_MULF32R_LL_S2 +/* 7198 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7236 +/* 7205 */ MCD_OPC_CheckPredicate, 24, 63, 23, 0, // Skip to: 13161 +/* 7210 */ MCD_OPC_CheckField, 32, 4, 0, 56, 23, 0, // Skip to: 13161 +/* 7217 */ MCD_OPC_CheckField, 24, 4, 0, 49, 23, 0, // Skip to: 13161 +/* 7224 */ MCD_OPC_CheckField, 0, 20, 15, 42, 23, 0, // Skip to: 13161 +/* 7231 */ MCD_OPC_Decode, 185, 7, 215, 1, // Opcode: AE_MULF32S_LL_S2 +/* 7236 */ MCD_OPC_FilterValue, 128, 128, 12, 30, 23, 0, // Skip to: 13161 +/* 7243 */ MCD_OPC_CheckPredicate, 24, 25, 23, 0, // Skip to: 13161 +/* 7248 */ MCD_OPC_CheckField, 32, 4, 0, 18, 23, 0, // Skip to: 13161 +/* 7255 */ MCD_OPC_CheckField, 24, 4, 0, 11, 23, 0, // Skip to: 13161 +/* 7262 */ MCD_OPC_CheckField, 0, 20, 15, 4, 23, 0, // Skip to: 13161 +/* 7269 */ MCD_OPC_Decode, 187, 7, 215, 1, // Opcode: AE_MULF32X16_H0_S2 +/* 7274 */ MCD_OPC_FilterValue, 28, 153, 0, 0, // Skip to: 7432 +/* 7279 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 7282 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7318 +/* 7287 */ MCD_OPC_CheckPredicate, 24, 237, 22, 0, // Skip to: 13161 +/* 7292 */ MCD_OPC_CheckField, 32, 4, 0, 230, 22, 0, // Skip to: 13161 +/* 7299 */ MCD_OPC_CheckField, 24, 4, 0, 223, 22, 0, // Skip to: 13161 +/* 7306 */ MCD_OPC_CheckField, 0, 20, 15, 216, 22, 0, // Skip to: 13161 +/* 7313 */ MCD_OPC_Decode, 189, 7, 215, 1, // Opcode: AE_MULF32X16_H1_S2 +/* 7318 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7356 +/* 7325 */ MCD_OPC_CheckPredicate, 24, 199, 22, 0, // Skip to: 13161 +/* 7330 */ MCD_OPC_CheckField, 32, 4, 0, 192, 22, 0, // Skip to: 13161 +/* 7337 */ MCD_OPC_CheckField, 24, 4, 0, 185, 22, 0, // Skip to: 13161 +/* 7344 */ MCD_OPC_CheckField, 0, 20, 15, 178, 22, 0, // Skip to: 13161 +/* 7351 */ MCD_OPC_Decode, 191, 7, 215, 1, // Opcode: AE_MULF32X16_H2_S2 +/* 7356 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7394 +/* 7363 */ MCD_OPC_CheckPredicate, 24, 161, 22, 0, // Skip to: 13161 +/* 7368 */ MCD_OPC_CheckField, 32, 4, 0, 154, 22, 0, // Skip to: 13161 +/* 7375 */ MCD_OPC_CheckField, 24, 4, 0, 147, 22, 0, // Skip to: 13161 +/* 7382 */ MCD_OPC_CheckField, 0, 20, 15, 140, 22, 0, // Skip to: 13161 +/* 7389 */ MCD_OPC_Decode, 193, 7, 215, 1, // Opcode: AE_MULF32X16_H3_S2 +/* 7394 */ MCD_OPC_FilterValue, 128, 128, 12, 128, 22, 0, // Skip to: 13161 +/* 7401 */ MCD_OPC_CheckPredicate, 24, 123, 22, 0, // Skip to: 13161 +/* 7406 */ MCD_OPC_CheckField, 32, 4, 0, 116, 22, 0, // Skip to: 13161 +/* 7413 */ MCD_OPC_CheckField, 24, 4, 0, 109, 22, 0, // Skip to: 13161 +/* 7420 */ MCD_OPC_CheckField, 0, 20, 15, 102, 22, 0, // Skip to: 13161 +/* 7427 */ MCD_OPC_Decode, 195, 7, 215, 1, // Opcode: AE_MULF32X16_L0_S2 +/* 7432 */ MCD_OPC_FilterValue, 29, 153, 0, 0, // Skip to: 7590 +/* 7437 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 7440 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7476 +/* 7445 */ MCD_OPC_CheckPredicate, 24, 79, 22, 0, // Skip to: 13161 +/* 7450 */ MCD_OPC_CheckField, 32, 4, 0, 72, 22, 0, // Skip to: 13161 +/* 7457 */ MCD_OPC_CheckField, 24, 4, 0, 65, 22, 0, // Skip to: 13161 +/* 7464 */ MCD_OPC_CheckField, 0, 20, 15, 58, 22, 0, // Skip to: 13161 +/* 7471 */ MCD_OPC_Decode, 197, 7, 215, 1, // Opcode: AE_MULF32X16_L1_S2 +/* 7476 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7514 +/* 7483 */ MCD_OPC_CheckPredicate, 24, 41, 22, 0, // Skip to: 13161 +/* 7488 */ MCD_OPC_CheckField, 32, 4, 0, 34, 22, 0, // Skip to: 13161 +/* 7495 */ MCD_OPC_CheckField, 24, 4, 0, 27, 22, 0, // Skip to: 13161 +/* 7502 */ MCD_OPC_CheckField, 0, 20, 15, 20, 22, 0, // Skip to: 13161 +/* 7509 */ MCD_OPC_Decode, 199, 7, 215, 1, // Opcode: AE_MULF32X16_L2_S2 +/* 7514 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7552 +/* 7521 */ MCD_OPC_CheckPredicate, 24, 3, 22, 0, // Skip to: 13161 +/* 7526 */ MCD_OPC_CheckField, 32, 4, 0, 252, 21, 0, // Skip to: 13161 +/* 7533 */ MCD_OPC_CheckField, 24, 4, 0, 245, 21, 0, // Skip to: 13161 +/* 7540 */ MCD_OPC_CheckField, 0, 20, 15, 238, 21, 0, // Skip to: 13161 +/* 7547 */ MCD_OPC_Decode, 201, 7, 215, 1, // Opcode: AE_MULF32X16_L3_S2 +/* 7552 */ MCD_OPC_FilterValue, 128, 128, 12, 226, 21, 0, // Skip to: 13161 +/* 7559 */ MCD_OPC_CheckPredicate, 24, 221, 21, 0, // Skip to: 13161 +/* 7564 */ MCD_OPC_CheckField, 32, 4, 0, 214, 21, 0, // Skip to: 13161 +/* 7571 */ MCD_OPC_CheckField, 24, 4, 0, 207, 21, 0, // Skip to: 13161 +/* 7578 */ MCD_OPC_CheckField, 0, 20, 15, 200, 21, 0, // Skip to: 13161 +/* 7585 */ MCD_OPC_Decode, 203, 7, 215, 1, // Opcode: AE_MULF48Q32SP16S_L_S2 +/* 7590 */ MCD_OPC_FilterValue, 30, 153, 0, 0, // Skip to: 7748 +/* 7595 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 7598 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7634 +/* 7603 */ MCD_OPC_CheckPredicate, 24, 177, 21, 0, // Skip to: 13161 +/* 7608 */ MCD_OPC_CheckField, 32, 4, 0, 170, 21, 0, // Skip to: 13161 +/* 7615 */ MCD_OPC_CheckField, 24, 4, 0, 163, 21, 0, // Skip to: 13161 +/* 7622 */ MCD_OPC_CheckField, 0, 20, 15, 156, 21, 0, // Skip to: 13161 +/* 7629 */ MCD_OPC_Decode, 205, 7, 215, 1, // Opcode: AE_MULF48Q32SP16U_L_S2 +/* 7634 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7672 +/* 7641 */ MCD_OPC_CheckPredicate, 24, 139, 21, 0, // Skip to: 13161 +/* 7646 */ MCD_OPC_CheckField, 32, 4, 0, 132, 21, 0, // Skip to: 13161 +/* 7653 */ MCD_OPC_CheckField, 24, 4, 0, 125, 21, 0, // Skip to: 13161 +/* 7660 */ MCD_OPC_CheckField, 0, 20, 15, 118, 21, 0, // Skip to: 13161 +/* 7667 */ MCD_OPC_Decode, 219, 7, 215, 1, // Opcode: AE_MULFP24X2RA_S2 +/* 7672 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7710 +/* 7679 */ MCD_OPC_CheckPredicate, 24, 101, 21, 0, // Skip to: 13161 +/* 7684 */ MCD_OPC_CheckField, 32, 4, 0, 94, 21, 0, // Skip to: 13161 +/* 7691 */ MCD_OPC_CheckField, 24, 4, 0, 87, 21, 0, // Skip to: 13161 +/* 7698 */ MCD_OPC_CheckField, 0, 20, 15, 80, 21, 0, // Skip to: 13161 +/* 7705 */ MCD_OPC_Decode, 220, 7, 215, 1, // Opcode: AE_MULFP24X2R_S2 +/* 7710 */ MCD_OPC_FilterValue, 128, 128, 12, 68, 21, 0, // Skip to: 13161 +/* 7717 */ MCD_OPC_CheckPredicate, 24, 63, 21, 0, // Skip to: 13161 +/* 7722 */ MCD_OPC_CheckField, 32, 4, 0, 56, 21, 0, // Skip to: 13161 +/* 7729 */ MCD_OPC_CheckField, 24, 4, 0, 49, 21, 0, // Skip to: 13161 +/* 7736 */ MCD_OPC_CheckField, 0, 20, 15, 42, 21, 0, // Skip to: 13161 +/* 7743 */ MCD_OPC_Decode, 222, 7, 215, 1, // Opcode: AE_MULFP32X16X2RAS_H_S2 +/* 7748 */ MCD_OPC_FilterValue, 31, 153, 0, 0, // Skip to: 7906 +/* 7753 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 7756 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7792 +/* 7761 */ MCD_OPC_CheckPredicate, 24, 19, 21, 0, // Skip to: 13161 +/* 7766 */ MCD_OPC_CheckField, 32, 4, 0, 12, 21, 0, // Skip to: 13161 +/* 7773 */ MCD_OPC_CheckField, 24, 4, 0, 5, 21, 0, // Skip to: 13161 +/* 7780 */ MCD_OPC_CheckField, 0, 20, 15, 254, 20, 0, // Skip to: 13161 +/* 7787 */ MCD_OPC_Decode, 224, 7, 215, 1, // Opcode: AE_MULFP32X16X2RAS_L_S2 +/* 7792 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7830 +/* 7799 */ MCD_OPC_CheckPredicate, 24, 237, 20, 0, // Skip to: 13161 +/* 7804 */ MCD_OPC_CheckField, 32, 4, 0, 230, 20, 0, // Skip to: 13161 +/* 7811 */ MCD_OPC_CheckField, 24, 4, 0, 223, 20, 0, // Skip to: 13161 +/* 7818 */ MCD_OPC_CheckField, 0, 20, 15, 216, 20, 0, // Skip to: 13161 +/* 7825 */ MCD_OPC_Decode, 226, 7, 215, 1, // Opcode: AE_MULFP32X16X2RS_H_S2 +/* 7830 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7868 +/* 7837 */ MCD_OPC_CheckPredicate, 24, 199, 20, 0, // Skip to: 13161 +/* 7842 */ MCD_OPC_CheckField, 32, 4, 0, 192, 20, 0, // Skip to: 13161 +/* 7849 */ MCD_OPC_CheckField, 24, 4, 0, 185, 20, 0, // Skip to: 13161 +/* 7856 */ MCD_OPC_CheckField, 0, 20, 15, 178, 20, 0, // Skip to: 13161 +/* 7863 */ MCD_OPC_Decode, 228, 7, 215, 1, // Opcode: AE_MULFP32X16X2RS_L_S2 +/* 7868 */ MCD_OPC_FilterValue, 128, 128, 12, 166, 20, 0, // Skip to: 13161 +/* 7875 */ MCD_OPC_CheckPredicate, 24, 161, 20, 0, // Skip to: 13161 +/* 7880 */ MCD_OPC_CheckField, 32, 4, 0, 154, 20, 0, // Skip to: 13161 +/* 7887 */ MCD_OPC_CheckField, 24, 4, 0, 147, 20, 0, // Skip to: 13161 +/* 7894 */ MCD_OPC_CheckField, 0, 20, 15, 140, 20, 0, // Skip to: 13161 +/* 7901 */ MCD_OPC_Decode, 231, 7, 215, 1, // Opcode: AE_MULFQ32SP24S_H_S2 +/* 7906 */ MCD_OPC_FilterValue, 32, 153, 0, 0, // Skip to: 8064 +/* 7911 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 7914 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7950 +/* 7919 */ MCD_OPC_CheckPredicate, 24, 117, 20, 0, // Skip to: 13161 +/* 7924 */ MCD_OPC_CheckField, 32, 4, 0, 110, 20, 0, // Skip to: 13161 +/* 7931 */ MCD_OPC_CheckField, 24, 4, 0, 103, 20, 0, // Skip to: 13161 +/* 7938 */ MCD_OPC_CheckField, 0, 20, 15, 96, 20, 0, // Skip to: 13161 +/* 7945 */ MCD_OPC_Decode, 232, 7, 215, 1, // Opcode: AE_MULFQ32SP24S_L_S2 +/* 7950 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7988 +/* 7957 */ MCD_OPC_CheckPredicate, 24, 79, 20, 0, // Skip to: 13161 +/* 7962 */ MCD_OPC_CheckField, 32, 4, 0, 72, 20, 0, // Skip to: 13161 +/* 7969 */ MCD_OPC_CheckField, 24, 4, 0, 65, 20, 0, // Skip to: 13161 +/* 7976 */ MCD_OPC_CheckField, 0, 20, 15, 58, 20, 0, // Skip to: 13161 +/* 7983 */ MCD_OPC_Decode, 234, 7, 215, 1, // Opcode: AE_MULP24X2_S2 +/* 7988 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8026 +/* 7995 */ MCD_OPC_CheckPredicate, 24, 41, 20, 0, // Skip to: 13161 +/* 8000 */ MCD_OPC_CheckField, 32, 4, 0, 34, 20, 0, // Skip to: 13161 +/* 8007 */ MCD_OPC_CheckField, 24, 4, 0, 27, 20, 0, // Skip to: 13161 +/* 8014 */ MCD_OPC_CheckField, 0, 20, 15, 20, 20, 0, // Skip to: 13161 +/* 8021 */ MCD_OPC_Decode, 238, 7, 215, 1, // Opcode: AE_MULQ32SP16S_L_S2 +/* 8026 */ MCD_OPC_FilterValue, 128, 128, 12, 8, 20, 0, // Skip to: 13161 +/* 8033 */ MCD_OPC_CheckPredicate, 24, 3, 20, 0, // Skip to: 13161 +/* 8038 */ MCD_OPC_CheckField, 32, 4, 0, 252, 19, 0, // Skip to: 13161 +/* 8045 */ MCD_OPC_CheckField, 24, 4, 0, 245, 19, 0, // Skip to: 13161 +/* 8052 */ MCD_OPC_CheckField, 0, 20, 15, 238, 19, 0, // Skip to: 13161 +/* 8059 */ MCD_OPC_Decode, 239, 7, 215, 1, // Opcode: AE_MULQ32SP16U_L_S2 +/* 8064 */ MCD_OPC_FilterValue, 33, 153, 0, 0, // Skip to: 8222 +/* 8069 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 8072 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8108 +/* 8077 */ MCD_OPC_CheckPredicate, 24, 215, 19, 0, // Skip to: 13161 +/* 8082 */ MCD_OPC_CheckField, 32, 4, 0, 208, 19, 0, // Skip to: 13161 +/* 8089 */ MCD_OPC_CheckField, 24, 4, 0, 201, 19, 0, // Skip to: 13161 +/* 8096 */ MCD_OPC_CheckField, 0, 20, 15, 194, 19, 0, // Skip to: 13161 +/* 8103 */ MCD_OPC_Decode, 240, 7, 215, 1, // Opcode: AE_MULRFQ32SP24S_H_S2 +/* 8108 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8146 +/* 8115 */ MCD_OPC_CheckPredicate, 24, 177, 19, 0, // Skip to: 13161 +/* 8120 */ MCD_OPC_CheckField, 32, 4, 0, 170, 19, 0, // Skip to: 13161 +/* 8127 */ MCD_OPC_CheckField, 24, 4, 0, 163, 19, 0, // Skip to: 13161 +/* 8134 */ MCD_OPC_CheckField, 0, 20, 15, 156, 19, 0, // Skip to: 13161 +/* 8141 */ MCD_OPC_Decode, 241, 7, 215, 1, // Opcode: AE_MULRFQ32SP24S_L_S2 +/* 8146 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8184 +/* 8153 */ MCD_OPC_CheckPredicate, 24, 139, 19, 0, // Skip to: 13161 +/* 8158 */ MCD_OPC_CheckField, 32, 4, 0, 132, 19, 0, // Skip to: 13161 +/* 8165 */ MCD_OPC_CheckField, 24, 4, 0, 125, 19, 0, // Skip to: 13161 +/* 8172 */ MCD_OPC_CheckField, 0, 20, 15, 118, 19, 0, // Skip to: 13161 +/* 8179 */ MCD_OPC_Decode, 244, 7, 215, 1, // Opcode: AE_MULS32F48P16S_HH_S2 +/* 8184 */ MCD_OPC_FilterValue, 128, 128, 12, 106, 19, 0, // Skip to: 13161 +/* 8191 */ MCD_OPC_CheckPredicate, 24, 101, 19, 0, // Skip to: 13161 +/* 8196 */ MCD_OPC_CheckField, 32, 4, 0, 94, 19, 0, // Skip to: 13161 +/* 8203 */ MCD_OPC_CheckField, 24, 4, 0, 87, 19, 0, // Skip to: 13161 +/* 8210 */ MCD_OPC_CheckField, 0, 20, 15, 80, 19, 0, // Skip to: 13161 +/* 8217 */ MCD_OPC_Decode, 246, 7, 215, 1, // Opcode: AE_MULS32F48P16S_LH_S2 +/* 8222 */ MCD_OPC_FilterValue, 34, 153, 0, 0, // Skip to: 8380 +/* 8227 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 8230 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8266 +/* 8235 */ MCD_OPC_CheckPredicate, 24, 57, 19, 0, // Skip to: 13161 +/* 8240 */ MCD_OPC_CheckField, 32, 4, 0, 50, 19, 0, // Skip to: 13161 +/* 8247 */ MCD_OPC_CheckField, 24, 4, 0, 43, 19, 0, // Skip to: 13161 +/* 8254 */ MCD_OPC_CheckField, 0, 20, 15, 36, 19, 0, // Skip to: 13161 +/* 8261 */ MCD_OPC_Decode, 248, 7, 215, 1, // Opcode: AE_MULS32F48P16S_LL_S2 +/* 8266 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8304 +/* 8273 */ MCD_OPC_CheckPredicate, 24, 19, 19, 0, // Skip to: 13161 +/* 8278 */ MCD_OPC_CheckField, 32, 4, 0, 12, 19, 0, // Skip to: 13161 +/* 8285 */ MCD_OPC_CheckField, 24, 4, 0, 5, 19, 0, // Skip to: 13161 +/* 8292 */ MCD_OPC_CheckField, 0, 20, 15, 254, 18, 0, // Skip to: 13161 +/* 8299 */ MCD_OPC_Decode, 251, 7, 216, 1, // Opcode: AE_MULS32X16_H0_S2 +/* 8304 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8342 +/* 8311 */ MCD_OPC_CheckPredicate, 24, 237, 18, 0, // Skip to: 13161 +/* 8316 */ MCD_OPC_CheckField, 32, 4, 0, 230, 18, 0, // Skip to: 13161 +/* 8323 */ MCD_OPC_CheckField, 24, 4, 0, 223, 18, 0, // Skip to: 13161 +/* 8330 */ MCD_OPC_CheckField, 0, 20, 15, 216, 18, 0, // Skip to: 13161 +/* 8337 */ MCD_OPC_Decode, 253, 7, 216, 1, // Opcode: AE_MULS32X16_H1_S2 +/* 8342 */ MCD_OPC_FilterValue, 128, 128, 12, 204, 18, 0, // Skip to: 13161 +/* 8349 */ MCD_OPC_CheckPredicate, 24, 199, 18, 0, // Skip to: 13161 +/* 8354 */ MCD_OPC_CheckField, 32, 4, 0, 192, 18, 0, // Skip to: 13161 +/* 8361 */ MCD_OPC_CheckField, 24, 4, 0, 185, 18, 0, // Skip to: 13161 +/* 8368 */ MCD_OPC_CheckField, 0, 20, 15, 178, 18, 0, // Skip to: 13161 +/* 8375 */ MCD_OPC_Decode, 255, 7, 216, 1, // Opcode: AE_MULS32X16_H2_S2 +/* 8380 */ MCD_OPC_FilterValue, 35, 153, 0, 0, // Skip to: 8538 +/* 8385 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 8388 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8424 +/* 8393 */ MCD_OPC_CheckPredicate, 24, 155, 18, 0, // Skip to: 13161 +/* 8398 */ MCD_OPC_CheckField, 32, 4, 0, 148, 18, 0, // Skip to: 13161 +/* 8405 */ MCD_OPC_CheckField, 24, 4, 0, 141, 18, 0, // Skip to: 13161 +/* 8412 */ MCD_OPC_CheckField, 0, 20, 15, 134, 18, 0, // Skip to: 13161 +/* 8419 */ MCD_OPC_Decode, 129, 8, 216, 1, // Opcode: AE_MULS32X16_H3_S2 +/* 8424 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8462 +/* 8431 */ MCD_OPC_CheckPredicate, 24, 117, 18, 0, // Skip to: 13161 +/* 8436 */ MCD_OPC_CheckField, 32, 4, 0, 110, 18, 0, // Skip to: 13161 +/* 8443 */ MCD_OPC_CheckField, 24, 4, 0, 103, 18, 0, // Skip to: 13161 +/* 8450 */ MCD_OPC_CheckField, 0, 20, 15, 96, 18, 0, // Skip to: 13161 +/* 8457 */ MCD_OPC_Decode, 131, 8, 216, 1, // Opcode: AE_MULS32X16_L0_S2 +/* 8462 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8500 +/* 8469 */ MCD_OPC_CheckPredicate, 24, 79, 18, 0, // Skip to: 13161 +/* 8474 */ MCD_OPC_CheckField, 32, 4, 0, 72, 18, 0, // Skip to: 13161 +/* 8481 */ MCD_OPC_CheckField, 24, 4, 0, 65, 18, 0, // Skip to: 13161 +/* 8488 */ MCD_OPC_CheckField, 0, 20, 15, 58, 18, 0, // Skip to: 13161 +/* 8495 */ MCD_OPC_Decode, 133, 8, 216, 1, // Opcode: AE_MULS32X16_L1_S2 +/* 8500 */ MCD_OPC_FilterValue, 128, 128, 12, 46, 18, 0, // Skip to: 13161 +/* 8507 */ MCD_OPC_CheckPredicate, 24, 41, 18, 0, // Skip to: 13161 +/* 8512 */ MCD_OPC_CheckField, 32, 4, 0, 34, 18, 0, // Skip to: 13161 +/* 8519 */ MCD_OPC_CheckField, 24, 4, 0, 27, 18, 0, // Skip to: 13161 +/* 8526 */ MCD_OPC_CheckField, 0, 20, 15, 20, 18, 0, // Skip to: 13161 +/* 8533 */ MCD_OPC_Decode, 135, 8, 216, 1, // Opcode: AE_MULS32X16_L2_S2 +/* 8538 */ MCD_OPC_FilterValue, 36, 153, 0, 0, // Skip to: 8696 +/* 8543 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 8546 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8582 +/* 8551 */ MCD_OPC_CheckPredicate, 24, 253, 17, 0, // Skip to: 13161 +/* 8556 */ MCD_OPC_CheckField, 32, 4, 0, 246, 17, 0, // Skip to: 13161 +/* 8563 */ MCD_OPC_CheckField, 24, 4, 0, 239, 17, 0, // Skip to: 13161 +/* 8570 */ MCD_OPC_CheckField, 0, 20, 15, 232, 17, 0, // Skip to: 13161 +/* 8577 */ MCD_OPC_Decode, 137, 8, 216, 1, // Opcode: AE_MULS32X16_L3_S2 +/* 8582 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8620 +/* 8589 */ MCD_OPC_CheckPredicate, 24, 215, 17, 0, // Skip to: 13161 +/* 8594 */ MCD_OPC_CheckField, 32, 4, 0, 208, 17, 0, // Skip to: 13161 +/* 8601 */ MCD_OPC_CheckField, 24, 4, 0, 201, 17, 0, // Skip to: 13161 +/* 8608 */ MCD_OPC_CheckField, 0, 20, 15, 194, 17, 0, // Skip to: 13161 +/* 8615 */ MCD_OPC_Decode, 142, 8, 216, 1, // Opcode: AE_MULSAD24_HH_LL_S2 +/* 8620 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8658 +/* 8627 */ MCD_OPC_CheckPredicate, 24, 177, 17, 0, // Skip to: 13161 +/* 8632 */ MCD_OPC_CheckField, 32, 4, 0, 170, 17, 0, // Skip to: 13161 +/* 8639 */ MCD_OPC_CheckField, 24, 4, 0, 163, 17, 0, // Skip to: 13161 +/* 8646 */ MCD_OPC_CheckField, 0, 20, 15, 156, 17, 0, // Skip to: 13161 +/* 8653 */ MCD_OPC_Decode, 144, 8, 216, 1, // Opcode: AE_MULSAD32X16_H1_L0_S2 +/* 8658 */ MCD_OPC_FilterValue, 128, 128, 12, 144, 17, 0, // Skip to: 13161 +/* 8665 */ MCD_OPC_CheckPredicate, 24, 139, 17, 0, // Skip to: 13161 +/* 8670 */ MCD_OPC_CheckField, 32, 4, 0, 132, 17, 0, // Skip to: 13161 +/* 8677 */ MCD_OPC_CheckField, 24, 4, 0, 125, 17, 0, // Skip to: 13161 +/* 8684 */ MCD_OPC_CheckField, 0, 20, 15, 118, 17, 0, // Skip to: 13161 +/* 8691 */ MCD_OPC_Decode, 146, 8, 216, 1, // Opcode: AE_MULSAD32X16_H3_L2_S2 +/* 8696 */ MCD_OPC_FilterValue, 37, 153, 0, 0, // Skip to: 8854 +/* 8701 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 8704 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8740 +/* 8709 */ MCD_OPC_CheckPredicate, 24, 95, 17, 0, // Skip to: 13161 +/* 8714 */ MCD_OPC_CheckField, 32, 4, 0, 88, 17, 0, // Skip to: 13161 +/* 8721 */ MCD_OPC_CheckField, 24, 4, 0, 81, 17, 0, // Skip to: 13161 +/* 8728 */ MCD_OPC_CheckField, 0, 20, 15, 74, 17, 0, // Skip to: 13161 +/* 8735 */ MCD_OPC_Decode, 148, 8, 216, 1, // Opcode: AE_MULSAFD24_HH_LL_S2 +/* 8740 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8778 +/* 8747 */ MCD_OPC_CheckPredicate, 24, 57, 17, 0, // Skip to: 13161 +/* 8752 */ MCD_OPC_CheckField, 32, 4, 0, 50, 17, 0, // Skip to: 13161 +/* 8759 */ MCD_OPC_CheckField, 24, 4, 0, 43, 17, 0, // Skip to: 13161 +/* 8766 */ MCD_OPC_CheckField, 0, 20, 15, 36, 17, 0, // Skip to: 13161 +/* 8773 */ MCD_OPC_Decode, 150, 8, 216, 1, // Opcode: AE_MULSAFD32X16_H1_L0_S2 +/* 8778 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8816 +/* 8785 */ MCD_OPC_CheckPredicate, 24, 19, 17, 0, // Skip to: 13161 +/* 8790 */ MCD_OPC_CheckField, 32, 4, 0, 12, 17, 0, // Skip to: 13161 +/* 8797 */ MCD_OPC_CheckField, 24, 4, 0, 5, 17, 0, // Skip to: 13161 +/* 8804 */ MCD_OPC_CheckField, 0, 20, 15, 254, 16, 0, // Skip to: 13161 +/* 8811 */ MCD_OPC_Decode, 152, 8, 216, 1, // Opcode: AE_MULSAFD32X16_H3_L2_S2 +/* 8816 */ MCD_OPC_FilterValue, 128, 128, 12, 242, 16, 0, // Skip to: 13161 +/* 8823 */ MCD_OPC_CheckPredicate, 24, 237, 16, 0, // Skip to: 13161 +/* 8828 */ MCD_OPC_CheckField, 32, 4, 0, 230, 16, 0, // Skip to: 13161 +/* 8835 */ MCD_OPC_CheckField, 24, 4, 0, 223, 16, 0, // Skip to: 13161 +/* 8842 */ MCD_OPC_CheckField, 0, 20, 15, 216, 16, 0, // Skip to: 13161 +/* 8849 */ MCD_OPC_Decode, 154, 8, 216, 1, // Opcode: AE_MULSF16SS_00_S2 +/* 8854 */ MCD_OPC_FilterValue, 38, 153, 0, 0, // Skip to: 9012 +/* 8859 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 8862 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8898 +/* 8867 */ MCD_OPC_CheckPredicate, 24, 193, 16, 0, // Skip to: 13161 +/* 8872 */ MCD_OPC_CheckField, 32, 4, 0, 186, 16, 0, // Skip to: 13161 +/* 8879 */ MCD_OPC_CheckField, 24, 4, 0, 179, 16, 0, // Skip to: 13161 +/* 8886 */ MCD_OPC_CheckField, 0, 20, 15, 172, 16, 0, // Skip to: 13161 +/* 8893 */ MCD_OPC_Decode, 168, 8, 216, 1, // Opcode: AE_MULSF32R_LL_S2 +/* 8898 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8936 +/* 8905 */ MCD_OPC_CheckPredicate, 24, 155, 16, 0, // Skip to: 13161 +/* 8910 */ MCD_OPC_CheckField, 32, 4, 0, 148, 16, 0, // Skip to: 13161 +/* 8917 */ MCD_OPC_CheckField, 24, 4, 0, 141, 16, 0, // Skip to: 13161 +/* 8924 */ MCD_OPC_CheckField, 0, 20, 15, 134, 16, 0, // Skip to: 13161 +/* 8931 */ MCD_OPC_Decode, 173, 8, 216, 1, // Opcode: AE_MULSF32X16_H0_S2 +/* 8936 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8974 +/* 8943 */ MCD_OPC_CheckPredicate, 24, 117, 16, 0, // Skip to: 13161 +/* 8948 */ MCD_OPC_CheckField, 32, 4, 0, 110, 16, 0, // Skip to: 13161 +/* 8955 */ MCD_OPC_CheckField, 24, 4, 0, 103, 16, 0, // Skip to: 13161 +/* 8962 */ MCD_OPC_CheckField, 0, 20, 15, 96, 16, 0, // Skip to: 13161 +/* 8969 */ MCD_OPC_Decode, 175, 8, 216, 1, // Opcode: AE_MULSF32X16_H1_S2 +/* 8974 */ MCD_OPC_FilterValue, 128, 128, 12, 84, 16, 0, // Skip to: 13161 +/* 8981 */ MCD_OPC_CheckPredicate, 24, 79, 16, 0, // Skip to: 13161 +/* 8986 */ MCD_OPC_CheckField, 32, 4, 0, 72, 16, 0, // Skip to: 13161 +/* 8993 */ MCD_OPC_CheckField, 24, 4, 0, 65, 16, 0, // Skip to: 13161 +/* 9000 */ MCD_OPC_CheckField, 0, 20, 15, 58, 16, 0, // Skip to: 13161 +/* 9007 */ MCD_OPC_Decode, 177, 8, 216, 1, // Opcode: AE_MULSF32X16_H2_S2 +/* 9012 */ MCD_OPC_FilterValue, 39, 213, 0, 0, // Skip to: 9230 +/* 9017 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 9020 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 9086 +/* 9025 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 9028 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9057 +/* 9033 */ MCD_OPC_CheckPredicate, 24, 27, 16, 0, // Skip to: 13161 +/* 9038 */ MCD_OPC_CheckField, 32, 4, 0, 20, 16, 0, // Skip to: 13161 +/* 9045 */ MCD_OPC_CheckField, 24, 4, 0, 13, 16, 0, // Skip to: 13161 +/* 9052 */ MCD_OPC_Decode, 211, 9, 215, 1, // Opcode: AE_ROUND16X4F32SSYM +/* 9057 */ MCD_OPC_FilterValue, 15, 3, 16, 0, // Skip to: 13161 +/* 9062 */ MCD_OPC_CheckPredicate, 24, 254, 15, 0, // Skip to: 13161 +/* 9067 */ MCD_OPC_CheckField, 32, 4, 0, 247, 15, 0, // Skip to: 13161 +/* 9074 */ MCD_OPC_CheckField, 24, 4, 0, 240, 15, 0, // Skip to: 13161 +/* 9081 */ MCD_OPC_Decode, 179, 8, 216, 1, // Opcode: AE_MULSF32X16_H3_S2 +/* 9086 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 9124 +/* 9093 */ MCD_OPC_CheckPredicate, 24, 223, 15, 0, // Skip to: 13161 +/* 9098 */ MCD_OPC_CheckField, 32, 4, 0, 216, 15, 0, // Skip to: 13161 +/* 9105 */ MCD_OPC_CheckField, 24, 4, 0, 209, 15, 0, // Skip to: 13161 +/* 9112 */ MCD_OPC_CheckField, 0, 20, 15, 202, 15, 0, // Skip to: 13161 +/* 9119 */ MCD_OPC_Decode, 181, 8, 216, 1, // Opcode: AE_MULSF32X16_L0_S2 +/* 9124 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 9162 +/* 9131 */ MCD_OPC_CheckPredicate, 24, 185, 15, 0, // Skip to: 13161 +/* 9136 */ MCD_OPC_CheckField, 32, 4, 0, 178, 15, 0, // Skip to: 13161 +/* 9143 */ MCD_OPC_CheckField, 24, 4, 0, 171, 15, 0, // Skip to: 13161 +/* 9150 */ MCD_OPC_CheckField, 0, 20, 15, 164, 15, 0, // Skip to: 13161 +/* 9157 */ MCD_OPC_Decode, 183, 8, 216, 1, // Opcode: AE_MULSF32X16_L1_S2 +/* 9162 */ MCD_OPC_FilterValue, 128, 128, 12, 152, 15, 0, // Skip to: 13161 +/* 9169 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 9172 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9201 +/* 9177 */ MCD_OPC_CheckPredicate, 24, 139, 15, 0, // Skip to: 13161 +/* 9182 */ MCD_OPC_CheckField, 32, 4, 0, 132, 15, 0, // Skip to: 13161 +/* 9189 */ MCD_OPC_CheckField, 24, 4, 0, 125, 15, 0, // Skip to: 13161 +/* 9196 */ MCD_OPC_Decode, 214, 9, 217, 1, // Opcode: AE_ROUND32X2F48SASYM +/* 9201 */ MCD_OPC_FilterValue, 15, 115, 15, 0, // Skip to: 13161 +/* 9206 */ MCD_OPC_CheckPredicate, 24, 110, 15, 0, // Skip to: 13161 +/* 9211 */ MCD_OPC_CheckField, 32, 4, 0, 103, 15, 0, // Skip to: 13161 +/* 9218 */ MCD_OPC_CheckField, 24, 4, 0, 96, 15, 0, // Skip to: 13161 +/* 9225 */ MCD_OPC_Decode, 185, 8, 216, 1, // Opcode: AE_MULSF32X16_L2_S2 +/* 9230 */ MCD_OPC_FilterValue, 40, 213, 0, 0, // Skip to: 9448 +/* 9235 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 9238 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 9304 +/* 9243 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 9246 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9275 +/* 9251 */ MCD_OPC_CheckPredicate, 24, 65, 15, 0, // Skip to: 13161 +/* 9256 */ MCD_OPC_CheckField, 32, 4, 0, 58, 15, 0, // Skip to: 13161 +/* 9263 */ MCD_OPC_CheckField, 24, 4, 0, 51, 15, 0, // Skip to: 13161 +/* 9270 */ MCD_OPC_Decode, 215, 9, 217, 1, // Opcode: AE_ROUND32X2F48SSYM +/* 9275 */ MCD_OPC_FilterValue, 15, 41, 15, 0, // Skip to: 13161 +/* 9280 */ MCD_OPC_CheckPredicate, 24, 36, 15, 0, // Skip to: 13161 +/* 9285 */ MCD_OPC_CheckField, 32, 4, 0, 29, 15, 0, // Skip to: 13161 +/* 9292 */ MCD_OPC_CheckField, 24, 4, 0, 22, 15, 0, // Skip to: 13161 +/* 9299 */ MCD_OPC_Decode, 187, 8, 216, 1, // Opcode: AE_MULSF32X16_L3_S2 +/* 9304 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 9342 +/* 9311 */ MCD_OPC_CheckPredicate, 24, 5, 15, 0, // Skip to: 13161 +/* 9316 */ MCD_OPC_CheckField, 32, 4, 0, 254, 14, 0, // Skip to: 13161 +/* 9323 */ MCD_OPC_CheckField, 24, 4, 0, 247, 14, 0, // Skip to: 13161 +/* 9330 */ MCD_OPC_CheckField, 0, 20, 15, 240, 14, 0, // Skip to: 13161 +/* 9337 */ MCD_OPC_Decode, 189, 8, 216, 1, // Opcode: AE_MULSF48Q32SP16S_L_S2 +/* 9342 */ MCD_OPC_FilterValue, 128, 128, 8, 61, 0, 0, // Skip to: 9410 +/* 9349 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 9352 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9381 +/* 9357 */ MCD_OPC_CheckPredicate, 24, 215, 14, 0, // Skip to: 13161 +/* 9362 */ MCD_OPC_CheckField, 32, 4, 0, 208, 14, 0, // Skip to: 13161 +/* 9369 */ MCD_OPC_CheckField, 24, 4, 0, 201, 14, 0, // Skip to: 13161 +/* 9376 */ MCD_OPC_Decode, 217, 9, 217, 1, // Opcode: AE_ROUND32X2F64SSYM +/* 9381 */ MCD_OPC_FilterValue, 15, 191, 14, 0, // Skip to: 13161 +/* 9386 */ MCD_OPC_CheckPredicate, 24, 186, 14, 0, // Skip to: 13161 +/* 9391 */ MCD_OPC_CheckField, 32, 4, 0, 179, 14, 0, // Skip to: 13161 +/* 9398 */ MCD_OPC_CheckField, 24, 4, 0, 172, 14, 0, // Skip to: 13161 +/* 9405 */ MCD_OPC_Decode, 191, 8, 216, 1, // Opcode: AE_MULSF48Q32SP16U_L_S2 +/* 9410 */ MCD_OPC_FilterValue, 128, 128, 12, 160, 14, 0, // Skip to: 13161 +/* 9417 */ MCD_OPC_CheckPredicate, 24, 155, 14, 0, // Skip to: 13161 +/* 9422 */ MCD_OPC_CheckField, 32, 4, 0, 148, 14, 0, // Skip to: 13161 +/* 9429 */ MCD_OPC_CheckField, 24, 4, 0, 141, 14, 0, // Skip to: 13161 +/* 9436 */ MCD_OPC_CheckField, 0, 20, 15, 134, 14, 0, // Skip to: 13161 +/* 9443 */ MCD_OPC_Decode, 194, 8, 216, 1, // Opcode: AE_MULSFP24X2RA_S2 +/* 9448 */ MCD_OPC_FilterValue, 41, 213, 0, 0, // Skip to: 9666 +/* 9453 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 9456 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 9522 +/* 9461 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 9464 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9493 +/* 9469 */ MCD_OPC_CheckPredicate, 24, 103, 14, 0, // Skip to: 13161 +/* 9474 */ MCD_OPC_CheckField, 32, 4, 0, 96, 14, 0, // Skip to: 13161 +/* 9481 */ MCD_OPC_CheckField, 24, 4, 0, 89, 14, 0, // Skip to: 13161 +/* 9488 */ MCD_OPC_Decode, 221, 9, 217, 1, // Opcode: AE_ROUNDSP16Q48X2SYM +/* 9493 */ MCD_OPC_FilterValue, 15, 79, 14, 0, // Skip to: 13161 +/* 9498 */ MCD_OPC_CheckPredicate, 24, 74, 14, 0, // Skip to: 13161 +/* 9503 */ MCD_OPC_CheckField, 32, 4, 0, 67, 14, 0, // Skip to: 13161 +/* 9510 */ MCD_OPC_CheckField, 24, 4, 0, 60, 14, 0, // Skip to: 13161 +/* 9517 */ MCD_OPC_Decode, 195, 8, 216, 1, // Opcode: AE_MULSFP24X2R_S2 +/* 9522 */ MCD_OPC_FilterValue, 128, 128, 4, 61, 0, 0, // Skip to: 9590 +/* 9529 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 9532 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9561 +/* 9537 */ MCD_OPC_CheckPredicate, 24, 35, 14, 0, // Skip to: 13161 +/* 9542 */ MCD_OPC_CheckField, 32, 4, 0, 28, 14, 0, // Skip to: 13161 +/* 9549 */ MCD_OPC_CheckField, 24, 4, 0, 21, 14, 0, // Skip to: 13161 +/* 9556 */ MCD_OPC_Decode, 187, 10, 217, 1, // Opcode: AE_SAT16X4 +/* 9561 */ MCD_OPC_FilterValue, 15, 11, 14, 0, // Skip to: 13161 +/* 9566 */ MCD_OPC_CheckPredicate, 24, 6, 14, 0, // Skip to: 13161 +/* 9571 */ MCD_OPC_CheckField, 32, 4, 0, 255, 13, 0, // Skip to: 13161 +/* 9578 */ MCD_OPC_CheckField, 24, 4, 0, 248, 13, 0, // Skip to: 13161 +/* 9585 */ MCD_OPC_Decode, 197, 8, 216, 1, // Opcode: AE_MULSFP32X16X2RAS_H_S2 +/* 9590 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 9628 +/* 9597 */ MCD_OPC_CheckPredicate, 24, 231, 13, 0, // Skip to: 13161 +/* 9602 */ MCD_OPC_CheckField, 32, 4, 0, 224, 13, 0, // Skip to: 13161 +/* 9609 */ MCD_OPC_CheckField, 24, 4, 0, 217, 13, 0, // Skip to: 13161 +/* 9616 */ MCD_OPC_CheckField, 0, 20, 15, 210, 13, 0, // Skip to: 13161 +/* 9623 */ MCD_OPC_Decode, 199, 8, 216, 1, // Opcode: AE_MULSFP32X16X2RAS_L_S2 +/* 9628 */ MCD_OPC_FilterValue, 128, 128, 12, 198, 13, 0, // Skip to: 13161 +/* 9635 */ MCD_OPC_CheckPredicate, 24, 193, 13, 0, // Skip to: 13161 +/* 9640 */ MCD_OPC_CheckField, 32, 4, 0, 186, 13, 0, // Skip to: 13161 +/* 9647 */ MCD_OPC_CheckField, 24, 4, 0, 179, 13, 0, // Skip to: 13161 +/* 9654 */ MCD_OPC_CheckField, 0, 20, 15, 172, 13, 0, // Skip to: 13161 +/* 9661 */ MCD_OPC_Decode, 201, 8, 216, 1, // Opcode: AE_MULSFP32X16X2RS_H_S2 +/* 9666 */ MCD_OPC_FilterValue, 42, 153, 0, 0, // Skip to: 9824 +/* 9671 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 9674 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9710 +/* 9679 */ MCD_OPC_CheckPredicate, 24, 149, 13, 0, // Skip to: 13161 +/* 9684 */ MCD_OPC_CheckField, 32, 4, 0, 142, 13, 0, // Skip to: 13161 +/* 9691 */ MCD_OPC_CheckField, 24, 4, 0, 135, 13, 0, // Skip to: 13161 +/* 9698 */ MCD_OPC_CheckField, 0, 20, 15, 128, 13, 0, // Skip to: 13161 +/* 9705 */ MCD_OPC_Decode, 203, 8, 216, 1, // Opcode: AE_MULSFP32X16X2RS_L_S2 +/* 9710 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 9748 +/* 9717 */ MCD_OPC_CheckPredicate, 24, 111, 13, 0, // Skip to: 13161 +/* 9722 */ MCD_OPC_CheckField, 32, 4, 0, 104, 13, 0, // Skip to: 13161 +/* 9729 */ MCD_OPC_CheckField, 24, 4, 0, 97, 13, 0, // Skip to: 13161 +/* 9736 */ MCD_OPC_CheckField, 0, 20, 15, 90, 13, 0, // Skip to: 13161 +/* 9743 */ MCD_OPC_Decode, 206, 8, 216, 1, // Opcode: AE_MULSFQ32SP24S_H_S2 +/* 9748 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 9786 +/* 9755 */ MCD_OPC_CheckPredicate, 24, 73, 13, 0, // Skip to: 13161 +/* 9760 */ MCD_OPC_CheckField, 32, 4, 0, 66, 13, 0, // Skip to: 13161 +/* 9767 */ MCD_OPC_CheckField, 24, 4, 0, 59, 13, 0, // Skip to: 13161 +/* 9774 */ MCD_OPC_CheckField, 0, 20, 15, 52, 13, 0, // Skip to: 13161 +/* 9781 */ MCD_OPC_Decode, 207, 8, 216, 1, // Opcode: AE_MULSFQ32SP24S_L_S2 +/* 9786 */ MCD_OPC_FilterValue, 128, 128, 12, 40, 13, 0, // Skip to: 13161 +/* 9793 */ MCD_OPC_CheckPredicate, 24, 35, 13, 0, // Skip to: 13161 +/* 9798 */ MCD_OPC_CheckField, 32, 4, 0, 28, 13, 0, // Skip to: 13161 +/* 9805 */ MCD_OPC_CheckField, 24, 4, 0, 21, 13, 0, // Skip to: 13161 +/* 9812 */ MCD_OPC_CheckField, 0, 20, 15, 14, 13, 0, // Skip to: 13161 +/* 9819 */ MCD_OPC_Decode, 209, 8, 216, 1, // Opcode: AE_MULSP24X2_S2 +/* 9824 */ MCD_OPC_FilterValue, 43, 153, 0, 0, // Skip to: 9982 +/* 9829 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 9832 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9868 +/* 9837 */ MCD_OPC_CheckPredicate, 24, 247, 12, 0, // Skip to: 13161 +/* 9842 */ MCD_OPC_CheckField, 32, 4, 0, 240, 12, 0, // Skip to: 13161 +/* 9849 */ MCD_OPC_CheckField, 24, 4, 0, 233, 12, 0, // Skip to: 13161 +/* 9856 */ MCD_OPC_CheckField, 0, 20, 15, 226, 12, 0, // Skip to: 13161 +/* 9863 */ MCD_OPC_Decode, 213, 8, 216, 1, // Opcode: AE_MULSQ32SP16S_L_S2 +/* 9868 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 9906 +/* 9875 */ MCD_OPC_CheckPredicate, 24, 209, 12, 0, // Skip to: 13161 +/* 9880 */ MCD_OPC_CheckField, 32, 4, 0, 202, 12, 0, // Skip to: 13161 +/* 9887 */ MCD_OPC_CheckField, 24, 4, 0, 195, 12, 0, // Skip to: 13161 +/* 9894 */ MCD_OPC_CheckField, 0, 20, 15, 188, 12, 0, // Skip to: 13161 +/* 9901 */ MCD_OPC_Decode, 214, 8, 216, 1, // Opcode: AE_MULSQ32SP16U_L_S2 +/* 9906 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 9944 +/* 9913 */ MCD_OPC_CheckPredicate, 24, 171, 12, 0, // Skip to: 13161 +/* 9918 */ MCD_OPC_CheckField, 32, 4, 0, 164, 12, 0, // Skip to: 13161 +/* 9925 */ MCD_OPC_CheckField, 24, 4, 0, 157, 12, 0, // Skip to: 13161 +/* 9932 */ MCD_OPC_CheckField, 0, 20, 15, 150, 12, 0, // Skip to: 13161 +/* 9939 */ MCD_OPC_Decode, 215, 8, 216, 1, // Opcode: AE_MULSRFQ32SP24S_H_S2 +/* 9944 */ MCD_OPC_FilterValue, 128, 128, 12, 138, 12, 0, // Skip to: 13161 +/* 9951 */ MCD_OPC_CheckPredicate, 24, 133, 12, 0, // Skip to: 13161 +/* 9956 */ MCD_OPC_CheckField, 32, 4, 0, 126, 12, 0, // Skip to: 13161 +/* 9963 */ MCD_OPC_CheckField, 24, 4, 0, 119, 12, 0, // Skip to: 13161 +/* 9970 */ MCD_OPC_CheckField, 0, 20, 15, 112, 12, 0, // Skip to: 13161 +/* 9977 */ MCD_OPC_Decode, 216, 8, 216, 1, // Opcode: AE_MULSRFQ32SP24S_L_S2 +/* 9982 */ MCD_OPC_FilterValue, 44, 183, 0, 0, // Skip to: 10170 +/* 9987 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 9990 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10056 +/* 9995 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 9998 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10027 +/* 10003 */ MCD_OPC_CheckPredicate, 24, 81, 12, 0, // Skip to: 13161 +/* 10008 */ MCD_OPC_CheckField, 32, 4, 0, 74, 12, 0, // Skip to: 13161 +/* 10015 */ MCD_OPC_CheckField, 24, 4, 0, 67, 12, 0, // Skip to: 13161 +/* 10022 */ MCD_OPC_Decode, 248, 4, 218, 1, // Opcode: AE_EQ64 +/* 10027 */ MCD_OPC_FilterValue, 15, 57, 12, 0, // Skip to: 13161 +/* 10032 */ MCD_OPC_CheckPredicate, 24, 52, 12, 0, // Skip to: 13161 +/* 10037 */ MCD_OPC_CheckField, 32, 4, 0, 45, 12, 0, // Skip to: 13161 +/* 10044 */ MCD_OPC_CheckField, 24, 4, 0, 38, 12, 0, // Skip to: 13161 +/* 10051 */ MCD_OPC_Decode, 218, 8, 216, 1, // Opcode: AE_MULSS32F48P16S_HH_S2 +/* 10056 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 10094 +/* 10063 */ MCD_OPC_CheckPredicate, 24, 21, 12, 0, // Skip to: 13161 +/* 10068 */ MCD_OPC_CheckField, 32, 4, 0, 14, 12, 0, // Skip to: 13161 +/* 10075 */ MCD_OPC_CheckField, 24, 4, 0, 7, 12, 0, // Skip to: 13161 +/* 10082 */ MCD_OPC_CheckField, 0, 20, 15, 0, 12, 0, // Skip to: 13161 +/* 10089 */ MCD_OPC_Decode, 220, 8, 216, 1, // Opcode: AE_MULSS32F48P16S_LH_S2 +/* 10094 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 10132 +/* 10101 */ MCD_OPC_CheckPredicate, 24, 239, 11, 0, // Skip to: 13161 +/* 10106 */ MCD_OPC_CheckField, 32, 4, 0, 232, 11, 0, // Skip to: 13161 +/* 10113 */ MCD_OPC_CheckField, 24, 4, 0, 225, 11, 0, // Skip to: 13161 +/* 10120 */ MCD_OPC_CheckField, 0, 20, 15, 218, 11, 0, // Skip to: 13161 +/* 10127 */ MCD_OPC_Decode, 222, 8, 216, 1, // Opcode: AE_MULSS32F48P16S_LL_S2 +/* 10132 */ MCD_OPC_FilterValue, 128, 128, 12, 206, 11, 0, // Skip to: 13161 +/* 10139 */ MCD_OPC_CheckPredicate, 24, 201, 11, 0, // Skip to: 13161 +/* 10144 */ MCD_OPC_CheckField, 32, 4, 0, 194, 11, 0, // Skip to: 13161 +/* 10151 */ MCD_OPC_CheckField, 24, 4, 0, 187, 11, 0, // Skip to: 13161 +/* 10158 */ MCD_OPC_CheckField, 0, 20, 15, 180, 11, 0, // Skip to: 13161 +/* 10165 */ MCD_OPC_Decode, 224, 8, 216, 1, // Opcode: AE_MULSSD24_HH_LL_S2 +/* 10170 */ MCD_OPC_FilterValue, 45, 243, 0, 0, // Skip to: 10418 +/* 10175 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 10178 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10244 +/* 10183 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10186 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10215 +/* 10191 */ MCD_OPC_CheckPredicate, 24, 149, 11, 0, // Skip to: 13161 +/* 10196 */ MCD_OPC_CheckField, 32, 4, 0, 142, 11, 0, // Skip to: 13161 +/* 10203 */ MCD_OPC_CheckField, 24, 4, 0, 135, 11, 0, // Skip to: 13161 +/* 10210 */ MCD_OPC_Decode, 220, 5, 215, 1, // Opcode: AE_MAX64 +/* 10215 */ MCD_OPC_FilterValue, 15, 125, 11, 0, // Skip to: 13161 +/* 10220 */ MCD_OPC_CheckPredicate, 24, 120, 11, 0, // Skip to: 13161 +/* 10225 */ MCD_OPC_CheckField, 32, 4, 0, 113, 11, 0, // Skip to: 13161 +/* 10232 */ MCD_OPC_CheckField, 24, 4, 0, 106, 11, 0, // Skip to: 13161 +/* 10239 */ MCD_OPC_Decode, 226, 8, 216, 1, // Opcode: AE_MULSSD24_HL_LH_S2 +/* 10244 */ MCD_OPC_FilterValue, 128, 128, 4, 61, 0, 0, // Skip to: 10312 +/* 10251 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10254 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10283 +/* 10259 */ MCD_OPC_CheckPredicate, 24, 81, 11, 0, // Skip to: 13161 +/* 10264 */ MCD_OPC_CheckField, 32, 4, 0, 74, 11, 0, // Skip to: 13161 +/* 10271 */ MCD_OPC_CheckField, 24, 4, 0, 67, 11, 0, // Skip to: 13161 +/* 10278 */ MCD_OPC_Decode, 221, 5, 215, 1, // Opcode: AE_MAXABS32S +/* 10283 */ MCD_OPC_FilterValue, 15, 57, 11, 0, // Skip to: 13161 +/* 10288 */ MCD_OPC_CheckPredicate, 24, 52, 11, 0, // Skip to: 13161 +/* 10293 */ MCD_OPC_CheckField, 32, 4, 0, 45, 11, 0, // Skip to: 13161 +/* 10300 */ MCD_OPC_CheckField, 24, 4, 0, 38, 11, 0, // Skip to: 13161 +/* 10307 */ MCD_OPC_Decode, 228, 8, 216, 1, // Opcode: AE_MULSSD32X16_H1_L0_S2 +/* 10312 */ MCD_OPC_FilterValue, 128, 128, 8, 61, 0, 0, // Skip to: 10380 +/* 10319 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10322 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10351 +/* 10327 */ MCD_OPC_CheckPredicate, 24, 13, 11, 0, // Skip to: 13161 +/* 10332 */ MCD_OPC_CheckField, 32, 4, 0, 6, 11, 0, // Skip to: 13161 +/* 10339 */ MCD_OPC_CheckField, 24, 4, 0, 255, 10, 0, // Skip to: 13161 +/* 10346 */ MCD_OPC_Decode, 222, 5, 215, 1, // Opcode: AE_MAXABS64S +/* 10351 */ MCD_OPC_FilterValue, 15, 245, 10, 0, // Skip to: 13161 +/* 10356 */ MCD_OPC_CheckPredicate, 24, 240, 10, 0, // Skip to: 13161 +/* 10361 */ MCD_OPC_CheckField, 32, 4, 0, 233, 10, 0, // Skip to: 13161 +/* 10368 */ MCD_OPC_CheckField, 24, 4, 0, 226, 10, 0, // Skip to: 13161 +/* 10375 */ MCD_OPC_Decode, 230, 8, 216, 1, // Opcode: AE_MULSSD32X16_H3_L2_S2 +/* 10380 */ MCD_OPC_FilterValue, 128, 128, 12, 214, 10, 0, // Skip to: 13161 +/* 10387 */ MCD_OPC_CheckPredicate, 24, 209, 10, 0, // Skip to: 13161 +/* 10392 */ MCD_OPC_CheckField, 32, 4, 0, 202, 10, 0, // Skip to: 13161 +/* 10399 */ MCD_OPC_CheckField, 24, 4, 0, 195, 10, 0, // Skip to: 13161 +/* 10406 */ MCD_OPC_CheckField, 0, 20, 15, 188, 10, 0, // Skip to: 13161 +/* 10413 */ MCD_OPC_Decode, 232, 8, 216, 1, // Opcode: AE_MULSSFD16SS_11_00_S2 +/* 10418 */ MCD_OPC_FilterValue, 46, 243, 0, 0, // Skip to: 10666 +/* 10423 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 10426 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10492 +/* 10431 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10434 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10463 +/* 10439 */ MCD_OPC_CheckPredicate, 24, 157, 10, 0, // Skip to: 13161 +/* 10444 */ MCD_OPC_CheckField, 32, 4, 0, 150, 10, 0, // Skip to: 13161 +/* 10451 */ MCD_OPC_CheckField, 24, 4, 0, 143, 10, 0, // Skip to: 13161 +/* 10458 */ MCD_OPC_Decode, 224, 5, 215, 1, // Opcode: AE_MIN64 +/* 10463 */ MCD_OPC_FilterValue, 15, 133, 10, 0, // Skip to: 13161 +/* 10468 */ MCD_OPC_CheckPredicate, 24, 128, 10, 0, // Skip to: 13161 +/* 10473 */ MCD_OPC_CheckField, 32, 4, 0, 121, 10, 0, // Skip to: 13161 +/* 10480 */ MCD_OPC_CheckField, 24, 4, 0, 114, 10, 0, // Skip to: 13161 +/* 10487 */ MCD_OPC_Decode, 234, 8, 216, 1, // Opcode: AE_MULSSFD16SS_13_02_S2 +/* 10492 */ MCD_OPC_FilterValue, 128, 128, 4, 61, 0, 0, // Skip to: 10560 +/* 10499 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10502 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10531 +/* 10507 */ MCD_OPC_CheckPredicate, 24, 89, 10, 0, // Skip to: 13161 +/* 10512 */ MCD_OPC_CheckField, 32, 4, 0, 82, 10, 0, // Skip to: 13161 +/* 10519 */ MCD_OPC_CheckField, 24, 4, 0, 75, 10, 0, // Skip to: 13161 +/* 10526 */ MCD_OPC_Decode, 225, 5, 215, 1, // Opcode: AE_MINABS32S +/* 10531 */ MCD_OPC_FilterValue, 15, 65, 10, 0, // Skip to: 13161 +/* 10536 */ MCD_OPC_CheckPredicate, 24, 60, 10, 0, // Skip to: 13161 +/* 10541 */ MCD_OPC_CheckField, 32, 4, 0, 53, 10, 0, // Skip to: 13161 +/* 10548 */ MCD_OPC_CheckField, 24, 4, 0, 46, 10, 0, // Skip to: 13161 +/* 10555 */ MCD_OPC_Decode, 236, 8, 216, 1, // Opcode: AE_MULSSFD16SS_33_22_S2 +/* 10560 */ MCD_OPC_FilterValue, 128, 128, 8, 61, 0, 0, // Skip to: 10628 +/* 10567 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10570 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10599 +/* 10575 */ MCD_OPC_CheckPredicate, 24, 21, 10, 0, // Skip to: 13161 +/* 10580 */ MCD_OPC_CheckField, 32, 4, 0, 14, 10, 0, // Skip to: 13161 +/* 10587 */ MCD_OPC_CheckField, 24, 4, 0, 7, 10, 0, // Skip to: 13161 +/* 10594 */ MCD_OPC_Decode, 226, 5, 215, 1, // Opcode: AE_MINABS64S +/* 10599 */ MCD_OPC_FilterValue, 15, 253, 9, 0, // Skip to: 13161 +/* 10604 */ MCD_OPC_CheckPredicate, 24, 248, 9, 0, // Skip to: 13161 +/* 10609 */ MCD_OPC_CheckField, 32, 4, 0, 241, 9, 0, // Skip to: 13161 +/* 10616 */ MCD_OPC_CheckField, 24, 4, 0, 234, 9, 0, // Skip to: 13161 +/* 10623 */ MCD_OPC_Decode, 238, 8, 216, 1, // Opcode: AE_MULSSFD24_HH_LL_S2 +/* 10628 */ MCD_OPC_FilterValue, 128, 128, 12, 222, 9, 0, // Skip to: 13161 +/* 10635 */ MCD_OPC_CheckPredicate, 24, 217, 9, 0, // Skip to: 13161 +/* 10640 */ MCD_OPC_CheckField, 32, 4, 0, 210, 9, 0, // Skip to: 13161 +/* 10647 */ MCD_OPC_CheckField, 24, 4, 0, 203, 9, 0, // Skip to: 13161 +/* 10654 */ MCD_OPC_CheckField, 0, 20, 15, 196, 9, 0, // Skip to: 13161 +/* 10661 */ MCD_OPC_Decode, 240, 8, 216, 1, // Opcode: AE_MULSSFD24_HL_LH_S2 +/* 10666 */ MCD_OPC_FilterValue, 47, 183, 0, 0, // Skip to: 10854 +/* 10671 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 10674 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10740 +/* 10679 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10682 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10711 +/* 10687 */ MCD_OPC_CheckPredicate, 24, 165, 9, 0, // Skip to: 13161 +/* 10692 */ MCD_OPC_CheckField, 32, 4, 0, 158, 9, 0, // Skip to: 13161 +/* 10699 */ MCD_OPC_CheckField, 24, 4, 0, 151, 9, 0, // Skip to: 13161 +/* 10706 */ MCD_OPC_Decode, 197, 9, 215, 1, // Opcode: AE_NAND +/* 10711 */ MCD_OPC_FilterValue, 15, 141, 9, 0, // Skip to: 13161 +/* 10716 */ MCD_OPC_CheckPredicate, 24, 136, 9, 0, // Skip to: 13161 +/* 10721 */ MCD_OPC_CheckField, 32, 4, 0, 129, 9, 0, // Skip to: 13161 +/* 10728 */ MCD_OPC_CheckField, 24, 4, 0, 122, 9, 0, // Skip to: 13161 +/* 10735 */ MCD_OPC_Decode, 242, 8, 216, 1, // Opcode: AE_MULSSFD32X16_H1_L0_S2 +/* 10740 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 10778 +/* 10747 */ MCD_OPC_CheckPredicate, 24, 105, 9, 0, // Skip to: 13161 +/* 10752 */ MCD_OPC_CheckField, 32, 4, 0, 98, 9, 0, // Skip to: 13161 +/* 10759 */ MCD_OPC_CheckField, 24, 4, 0, 91, 9, 0, // Skip to: 13161 +/* 10766 */ MCD_OPC_CheckField, 0, 20, 15, 84, 9, 0, // Skip to: 13161 +/* 10773 */ MCD_OPC_Decode, 244, 8, 216, 1, // Opcode: AE_MULSSFD32X16_H3_L2_S2 +/* 10778 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 10816 +/* 10785 */ MCD_OPC_CheckPredicate, 24, 67, 9, 0, // Skip to: 13161 +/* 10790 */ MCD_OPC_CheckField, 32, 4, 0, 60, 9, 0, // Skip to: 13161 +/* 10797 */ MCD_OPC_CheckField, 24, 4, 0, 53, 9, 0, // Skip to: 13161 +/* 10804 */ MCD_OPC_CheckField, 0, 20, 15, 46, 9, 0, // Skip to: 13161 +/* 10811 */ MCD_OPC_Decode, 246, 8, 215, 1, // Opcode: AE_MULZAAD24_HH_LL_S2 +/* 10816 */ MCD_OPC_FilterValue, 128, 128, 12, 34, 9, 0, // Skip to: 13161 +/* 10823 */ MCD_OPC_CheckPredicate, 24, 29, 9, 0, // Skip to: 13161 +/* 10828 */ MCD_OPC_CheckField, 32, 4, 0, 22, 9, 0, // Skip to: 13161 +/* 10835 */ MCD_OPC_CheckField, 24, 4, 0, 15, 9, 0, // Skip to: 13161 +/* 10842 */ MCD_OPC_CheckField, 0, 20, 15, 8, 9, 0, // Skip to: 13161 +/* 10849 */ MCD_OPC_Decode, 248, 8, 215, 1, // Opcode: AE_MULZAAD24_HL_LH_S2 +/* 10854 */ MCD_OPC_FilterValue, 48, 31, 1, 0, // Skip to: 11146 +/* 10859 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 10862 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10928 +/* 10867 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10870 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10899 +/* 10875 */ MCD_OPC_CheckPredicate, 24, 233, 8, 0, // Skip to: 13161 +/* 10880 */ MCD_OPC_CheckField, 32, 4, 0, 226, 8, 0, // Skip to: 13161 +/* 10887 */ MCD_OPC_CheckField, 24, 4, 0, 219, 8, 0, // Skip to: 13161 +/* 10894 */ MCD_OPC_Decode, 241, 5, 219, 1, // Opcode: AE_MOVF64 +/* 10899 */ MCD_OPC_FilterValue, 15, 209, 8, 0, // Skip to: 13161 +/* 10904 */ MCD_OPC_CheckPredicate, 24, 204, 8, 0, // Skip to: 13161 +/* 10909 */ MCD_OPC_CheckField, 32, 4, 0, 197, 8, 0, // Skip to: 13161 +/* 10916 */ MCD_OPC_CheckField, 24, 4, 0, 190, 8, 0, // Skip to: 13161 +/* 10923 */ MCD_OPC_Decode, 250, 8, 215, 1, // Opcode: AE_MULZAAD32X16_H0_L1_S2 +/* 10928 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 10966 +/* 10935 */ MCD_OPC_CheckPredicate, 24, 173, 8, 0, // Skip to: 13161 +/* 10940 */ MCD_OPC_CheckField, 32, 4, 0, 166, 8, 0, // Skip to: 13161 +/* 10947 */ MCD_OPC_CheckField, 24, 4, 0, 159, 8, 0, // Skip to: 13161 +/* 10954 */ MCD_OPC_CheckField, 0, 20, 15, 152, 8, 0, // Skip to: 13161 +/* 10961 */ MCD_OPC_Decode, 252, 8, 215, 1, // Opcode: AE_MULZAAD32X16_H1_L0_S2 +/* 10966 */ MCD_OPC_FilterValue, 128, 128, 8, 68, 0, 0, // Skip to: 11041 +/* 10973 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 10976 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 11012 +/* 10981 */ MCD_OPC_CheckPredicate, 24, 127, 8, 0, // Skip to: 13161 +/* 10986 */ MCD_OPC_CheckField, 32, 4, 0, 120, 8, 0, // Skip to: 13161 +/* 10993 */ MCD_OPC_CheckField, 24, 4, 0, 113, 8, 0, // Skip to: 13161 +/* 11000 */ MCD_OPC_CheckField, 20, 1, 1, 106, 8, 0, // Skip to: 13161 +/* 11007 */ MCD_OPC_Decode, 214, 5, 220, 1, // Opcode: AE_LE32 +/* 11012 */ MCD_OPC_FilterValue, 15, 96, 8, 0, // Skip to: 13161 +/* 11017 */ MCD_OPC_CheckPredicate, 24, 91, 8, 0, // Skip to: 13161 +/* 11022 */ MCD_OPC_CheckField, 32, 4, 0, 84, 8, 0, // Skip to: 13161 +/* 11029 */ MCD_OPC_CheckField, 24, 4, 0, 77, 8, 0, // Skip to: 13161 +/* 11036 */ MCD_OPC_Decode, 254, 8, 215, 1, // Opcode: AE_MULZAAD32X16_H2_L3_S2 +/* 11041 */ MCD_OPC_FilterValue, 128, 128, 12, 65, 8, 0, // Skip to: 13161 +/* 11048 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 11051 */ MCD_OPC_FilterValue, 14, 61, 0, 0, // Skip to: 11117 +/* 11056 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11059 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 11088 +/* 11064 */ MCD_OPC_CheckPredicate, 24, 44, 8, 0, // Skip to: 13161 +/* 11069 */ MCD_OPC_CheckField, 32, 4, 0, 37, 8, 0, // Skip to: 13161 +/* 11076 */ MCD_OPC_CheckField, 24, 4, 0, 30, 8, 0, // Skip to: 13161 +/* 11083 */ MCD_OPC_Decode, 246, 4, 221, 1, // Opcode: AE_EQ16 +/* 11088 */ MCD_OPC_FilterValue, 3, 20, 8, 0, // Skip to: 13161 +/* 11093 */ MCD_OPC_CheckPredicate, 24, 15, 8, 0, // Skip to: 13161 +/* 11098 */ MCD_OPC_CheckField, 32, 4, 0, 8, 8, 0, // Skip to: 13161 +/* 11105 */ MCD_OPC_CheckField, 24, 4, 0, 1, 8, 0, // Skip to: 13161 +/* 11112 */ MCD_OPC_Decode, 213, 5, 221, 1, // Opcode: AE_LE16 +/* 11117 */ MCD_OPC_FilterValue, 15, 247, 7, 0, // Skip to: 13161 +/* 11122 */ MCD_OPC_CheckPredicate, 24, 242, 7, 0, // Skip to: 13161 +/* 11127 */ MCD_OPC_CheckField, 32, 4, 0, 235, 7, 0, // Skip to: 13161 +/* 11134 */ MCD_OPC_CheckField, 24, 4, 0, 228, 7, 0, // Skip to: 13161 +/* 11141 */ MCD_OPC_Decode, 128, 9, 215, 1, // Opcode: AE_MULZAAD32X16_H3_L2_S2 +/* 11146 */ MCD_OPC_FilterValue, 49, 27, 1, 0, // Skip to: 11434 +/* 11151 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 11154 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11190 +/* 11159 */ MCD_OPC_CheckPredicate, 24, 205, 7, 0, // Skip to: 13161 +/* 11164 */ MCD_OPC_CheckField, 32, 4, 0, 198, 7, 0, // Skip to: 13161 +/* 11171 */ MCD_OPC_CheckField, 24, 4, 0, 191, 7, 0, // Skip to: 13161 +/* 11178 */ MCD_OPC_CheckField, 0, 20, 15, 184, 7, 0, // Skip to: 13161 +/* 11185 */ MCD_OPC_Decode, 130, 9, 215, 1, // Opcode: AE_MULZAAFD16SS_11_00_S2 +/* 11190 */ MCD_OPC_FilterValue, 128, 128, 4, 84, 0, 0, // Skip to: 11281 +/* 11197 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 11200 */ MCD_OPC_FilterValue, 14, 47, 0, 0, // Skip to: 11252 +/* 11205 */ MCD_OPC_ExtractField, 24, 6, // Inst{29-24} ... +/* 11208 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11230 +/* 11213 */ MCD_OPC_CheckPredicate, 24, 151, 7, 0, // Skip to: 13161 +/* 11218 */ MCD_OPC_CheckField, 32, 4, 0, 144, 7, 0, // Skip to: 13161 +/* 11225 */ MCD_OPC_Decode, 239, 5, 222, 1, // Opcode: AE_MOVF16X4 +/* 11230 */ MCD_OPC_FilterValue, 16, 134, 7, 0, // Skip to: 13161 +/* 11235 */ MCD_OPC_CheckPredicate, 24, 129, 7, 0, // Skip to: 13161 +/* 11240 */ MCD_OPC_CheckField, 32, 4, 0, 122, 7, 0, // Skip to: 13161 +/* 11247 */ MCD_OPC_Decode, 243, 5, 222, 1, // Opcode: AE_MOVT16X4 +/* 11252 */ MCD_OPC_FilterValue, 15, 112, 7, 0, // Skip to: 13161 +/* 11257 */ MCD_OPC_CheckPredicate, 24, 107, 7, 0, // Skip to: 13161 +/* 11262 */ MCD_OPC_CheckField, 32, 4, 0, 100, 7, 0, // Skip to: 13161 +/* 11269 */ MCD_OPC_CheckField, 24, 4, 0, 93, 7, 0, // Skip to: 13161 +/* 11276 */ MCD_OPC_Decode, 132, 9, 215, 1, // Opcode: AE_MULZAAFD16SS_13_02_S2 +/* 11281 */ MCD_OPC_FilterValue, 128, 128, 8, 68, 0, 0, // Skip to: 11356 +/* 11288 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 11291 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 11327 +/* 11296 */ MCD_OPC_CheckPredicate, 24, 68, 7, 0, // Skip to: 13161 +/* 11301 */ MCD_OPC_CheckField, 32, 4, 0, 61, 7, 0, // Skip to: 13161 +/* 11308 */ MCD_OPC_CheckField, 24, 4, 0, 54, 7, 0, // Skip to: 13161 +/* 11315 */ MCD_OPC_CheckField, 20, 2, 0, 47, 7, 0, // Skip to: 13161 +/* 11322 */ MCD_OPC_Decode, 216, 5, 221, 1, // Opcode: AE_LT16 +/* 11327 */ MCD_OPC_FilterValue, 15, 37, 7, 0, // Skip to: 13161 +/* 11332 */ MCD_OPC_CheckPredicate, 24, 32, 7, 0, // Skip to: 13161 +/* 11337 */ MCD_OPC_CheckField, 32, 4, 0, 25, 7, 0, // Skip to: 13161 +/* 11344 */ MCD_OPC_CheckField, 24, 4, 0, 18, 7, 0, // Skip to: 13161 +/* 11351 */ MCD_OPC_Decode, 134, 9, 215, 1, // Opcode: AE_MULZAAFD16SS_33_22_S2 +/* 11356 */ MCD_OPC_FilterValue, 128, 128, 12, 6, 7, 0, // Skip to: 13161 +/* 11363 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 11366 */ MCD_OPC_FilterValue, 14, 34, 0, 0, // Skip to: 11405 +/* 11371 */ MCD_OPC_ExtractField, 24, 12, // Inst{35-24} ... +/* 11374 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 11389 +/* 11379 */ MCD_OPC_CheckPredicate, 24, 241, 6, 0, // Skip to: 13161 +/* 11384 */ MCD_OPC_Decode, 244, 4, 223, 1, // Opcode: AE_DIV64D32_H +/* 11389 */ MCD_OPC_FilterValue, 224, 1, 230, 6, 0, // Skip to: 13161 +/* 11395 */ MCD_OPC_CheckPredicate, 24, 225, 6, 0, // Skip to: 13161 +/* 11400 */ MCD_OPC_Decode, 188, 10, 224, 1, // Opcode: AE_SAT24S +/* 11405 */ MCD_OPC_FilterValue, 15, 215, 6, 0, // Skip to: 13161 +/* 11410 */ MCD_OPC_CheckPredicate, 24, 210, 6, 0, // Skip to: 13161 +/* 11415 */ MCD_OPC_CheckField, 32, 4, 0, 203, 6, 0, // Skip to: 13161 +/* 11422 */ MCD_OPC_CheckField, 24, 4, 0, 196, 6, 0, // Skip to: 13161 +/* 11429 */ MCD_OPC_Decode, 136, 9, 215, 1, // Opcode: AE_MULZAAFD24_HH_LL_S2 +/* 11434 */ MCD_OPC_FilterValue, 50, 11, 1, 0, // Skip to: 11706 +/* 11439 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 11442 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 11517 +/* 11447 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 11450 */ MCD_OPC_FilterValue, 14, 33, 0, 0, // Skip to: 11488 +/* 11455 */ MCD_OPC_ExtractField, 24, 12, // Inst{35-24} ... +/* 11458 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11473 +/* 11463 */ MCD_OPC_CheckPredicate, 24, 157, 6, 0, // Skip to: 13161 +/* 11468 */ MCD_OPC_Decode, 190, 10, 224, 1, // Opcode: AE_SATQ56S +/* 11473 */ MCD_OPC_FilterValue, 16, 147, 6, 0, // Skip to: 13161 +/* 11478 */ MCD_OPC_CheckPredicate, 24, 142, 6, 0, // Skip to: 13161 +/* 11483 */ MCD_OPC_Decode, 232, 4, 224, 1, // Opcode: AE_CVT64F32_H +/* 11488 */ MCD_OPC_FilterValue, 15, 132, 6, 0, // Skip to: 13161 +/* 11493 */ MCD_OPC_CheckPredicate, 24, 127, 6, 0, // Skip to: 13161 +/* 11498 */ MCD_OPC_CheckField, 32, 4, 0, 120, 6, 0, // Skip to: 13161 +/* 11505 */ MCD_OPC_CheckField, 24, 4, 0, 113, 6, 0, // Skip to: 13161 +/* 11512 */ MCD_OPC_Decode, 138, 9, 215, 1, // Opcode: AE_MULZAAFD24_HL_LH_S2 +/* 11517 */ MCD_OPC_FilterValue, 128, 128, 4, 106, 0, 0, // Skip to: 11630 +/* 11524 */ MCD_OPC_ExtractField, 0, 20, // Inst{19-0} ... +/* 11527 */ MCD_OPC_FilterValue, 14, 69, 0, 0, // Skip to: 11601 +/* 11532 */ MCD_OPC_ExtractField, 32, 8, // Inst{39-32} ... +/* 11535 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11557 +/* 11540 */ MCD_OPC_CheckPredicate, 24, 80, 6, 0, // Skip to: 13161 +/* 11545 */ MCD_OPC_CheckField, 24, 4, 0, 73, 6, 0, // Skip to: 13161 +/* 11552 */ MCD_OPC_Decode, 218, 9, 225, 1, // Opcode: AE_ROUNDSP16F24ASYM +/* 11557 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 11579 +/* 11562 */ MCD_OPC_CheckPredicate, 24, 58, 6, 0, // Skip to: 13161 +/* 11567 */ MCD_OPC_CheckField, 24, 4, 0, 51, 6, 0, // Skip to: 13161 +/* 11574 */ MCD_OPC_Decode, 219, 9, 225, 1, // Opcode: AE_ROUNDSP16F24SYM +/* 11579 */ MCD_OPC_FilterValue, 112, 41, 6, 0, // Skip to: 13161 +/* 11584 */ MCD_OPC_CheckPredicate, 24, 36, 6, 0, // Skip to: 13161 +/* 11589 */ MCD_OPC_CheckField, 24, 4, 0, 29, 6, 0, // Skip to: 13161 +/* 11596 */ MCD_OPC_Decode, 206, 10, 225, 1, // Opcode: AE_SHORTSWAP +/* 11601 */ MCD_OPC_FilterValue, 15, 19, 6, 0, // Skip to: 13161 +/* 11606 */ MCD_OPC_CheckPredicate, 24, 14, 6, 0, // Skip to: 13161 +/* 11611 */ MCD_OPC_CheckField, 32, 4, 0, 7, 6, 0, // Skip to: 13161 +/* 11618 */ MCD_OPC_CheckField, 24, 4, 0, 0, 6, 0, // Skip to: 13161 +/* 11625 */ MCD_OPC_Decode, 140, 9, 215, 1, // Opcode: AE_MULZAAFD32X16_H0_L1_S2 +/* 11630 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 11668 +/* 11637 */ MCD_OPC_CheckPredicate, 24, 239, 5, 0, // Skip to: 13161 +/* 11642 */ MCD_OPC_CheckField, 32, 4, 0, 232, 5, 0, // Skip to: 13161 +/* 11649 */ MCD_OPC_CheckField, 24, 4, 0, 225, 5, 0, // Skip to: 13161 +/* 11656 */ MCD_OPC_CheckField, 0, 20, 15, 218, 5, 0, // Skip to: 13161 +/* 11663 */ MCD_OPC_Decode, 142, 9, 215, 1, // Opcode: AE_MULZAAFD32X16_H1_L0_S2 +/* 11668 */ MCD_OPC_FilterValue, 128, 128, 12, 206, 5, 0, // Skip to: 13161 +/* 11675 */ MCD_OPC_CheckPredicate, 24, 201, 5, 0, // Skip to: 13161 +/* 11680 */ MCD_OPC_CheckField, 32, 4, 0, 194, 5, 0, // Skip to: 13161 +/* 11687 */ MCD_OPC_CheckField, 24, 4, 0, 187, 5, 0, // Skip to: 13161 +/* 11694 */ MCD_OPC_CheckField, 0, 20, 15, 180, 5, 0, // Skip to: 13161 +/* 11701 */ MCD_OPC_Decode, 144, 9, 215, 1, // Opcode: AE_MULZAAFD32X16_H2_L3_S2 +/* 11706 */ MCD_OPC_FilterValue, 51, 153, 0, 0, // Skip to: 11864 +/* 11711 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 11714 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11750 +/* 11719 */ MCD_OPC_CheckPredicate, 24, 157, 5, 0, // Skip to: 13161 +/* 11724 */ MCD_OPC_CheckField, 32, 4, 0, 150, 5, 0, // Skip to: 13161 +/* 11731 */ MCD_OPC_CheckField, 24, 4, 0, 143, 5, 0, // Skip to: 13161 +/* 11738 */ MCD_OPC_CheckField, 0, 20, 15, 136, 5, 0, // Skip to: 13161 +/* 11745 */ MCD_OPC_Decode, 146, 9, 215, 1, // Opcode: AE_MULZAAFD32X16_H3_L2_S2 +/* 11750 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 11788 +/* 11757 */ MCD_OPC_CheckPredicate, 24, 119, 5, 0, // Skip to: 13161 +/* 11762 */ MCD_OPC_CheckField, 32, 4, 0, 112, 5, 0, // Skip to: 13161 +/* 11769 */ MCD_OPC_CheckField, 24, 4, 0, 105, 5, 0, // Skip to: 13161 +/* 11776 */ MCD_OPC_CheckField, 0, 20, 15, 98, 5, 0, // Skip to: 13161 +/* 11783 */ MCD_OPC_Decode, 148, 9, 215, 1, // Opcode: AE_MULZASD24_HH_LL_S2 +/* 11788 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 11826 +/* 11795 */ MCD_OPC_CheckPredicate, 24, 81, 5, 0, // Skip to: 13161 +/* 11800 */ MCD_OPC_CheckField, 32, 4, 0, 74, 5, 0, // Skip to: 13161 +/* 11807 */ MCD_OPC_CheckField, 24, 4, 0, 67, 5, 0, // Skip to: 13161 +/* 11814 */ MCD_OPC_CheckField, 0, 20, 15, 60, 5, 0, // Skip to: 13161 +/* 11821 */ MCD_OPC_Decode, 150, 9, 215, 1, // Opcode: AE_MULZASD24_HL_LH_S2 +/* 11826 */ MCD_OPC_FilterValue, 128, 128, 12, 48, 5, 0, // Skip to: 13161 +/* 11833 */ MCD_OPC_CheckPredicate, 24, 43, 5, 0, // Skip to: 13161 +/* 11838 */ MCD_OPC_CheckField, 32, 4, 0, 36, 5, 0, // Skip to: 13161 +/* 11845 */ MCD_OPC_CheckField, 24, 4, 0, 29, 5, 0, // Skip to: 13161 +/* 11852 */ MCD_OPC_CheckField, 0, 20, 15, 22, 5, 0, // Skip to: 13161 +/* 11859 */ MCD_OPC_Decode, 152, 9, 215, 1, // Opcode: AE_MULZASD32X16_H1_L0_S2 +/* 11864 */ MCD_OPC_FilterValue, 52, 153, 0, 0, // Skip to: 12022 +/* 11869 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 11872 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11908 +/* 11877 */ MCD_OPC_CheckPredicate, 24, 255, 4, 0, // Skip to: 13161 +/* 11882 */ MCD_OPC_CheckField, 32, 4, 0, 248, 4, 0, // Skip to: 13161 +/* 11889 */ MCD_OPC_CheckField, 24, 4, 0, 241, 4, 0, // Skip to: 13161 +/* 11896 */ MCD_OPC_CheckField, 0, 20, 15, 234, 4, 0, // Skip to: 13161 +/* 11903 */ MCD_OPC_Decode, 154, 9, 215, 1, // Opcode: AE_MULZASD32X16_H3_L2_S2 +/* 11908 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 11946 +/* 11915 */ MCD_OPC_CheckPredicate, 24, 217, 4, 0, // Skip to: 13161 +/* 11920 */ MCD_OPC_CheckField, 32, 4, 0, 210, 4, 0, // Skip to: 13161 +/* 11927 */ MCD_OPC_CheckField, 24, 4, 0, 203, 4, 0, // Skip to: 13161 +/* 11934 */ MCD_OPC_CheckField, 0, 20, 15, 196, 4, 0, // Skip to: 13161 +/* 11941 */ MCD_OPC_Decode, 156, 9, 215, 1, // Opcode: AE_MULZASFD24_HH_LL_S2 +/* 11946 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 11984 +/* 11953 */ MCD_OPC_CheckPredicate, 24, 179, 4, 0, // Skip to: 13161 +/* 11958 */ MCD_OPC_CheckField, 32, 4, 0, 172, 4, 0, // Skip to: 13161 +/* 11965 */ MCD_OPC_CheckField, 24, 4, 0, 165, 4, 0, // Skip to: 13161 +/* 11972 */ MCD_OPC_CheckField, 0, 20, 15, 158, 4, 0, // Skip to: 13161 +/* 11979 */ MCD_OPC_Decode, 158, 9, 215, 1, // Opcode: AE_MULZASFD24_HL_LH_S2 +/* 11984 */ MCD_OPC_FilterValue, 128, 128, 12, 146, 4, 0, // Skip to: 13161 +/* 11991 */ MCD_OPC_CheckPredicate, 24, 141, 4, 0, // Skip to: 13161 +/* 11996 */ MCD_OPC_CheckField, 32, 4, 0, 134, 4, 0, // Skip to: 13161 +/* 12003 */ MCD_OPC_CheckField, 24, 4, 0, 127, 4, 0, // Skip to: 13161 +/* 12010 */ MCD_OPC_CheckField, 0, 20, 15, 120, 4, 0, // Skip to: 13161 +/* 12017 */ MCD_OPC_Decode, 160, 9, 215, 1, // Opcode: AE_MULZASFD32X16_H1_L0_S2 +/* 12022 */ MCD_OPC_FilterValue, 53, 153, 0, 0, // Skip to: 12180 +/* 12027 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 12030 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12066 +/* 12035 */ MCD_OPC_CheckPredicate, 24, 97, 4, 0, // Skip to: 13161 +/* 12040 */ MCD_OPC_CheckField, 32, 4, 0, 90, 4, 0, // Skip to: 13161 +/* 12047 */ MCD_OPC_CheckField, 24, 4, 0, 83, 4, 0, // Skip to: 13161 +/* 12054 */ MCD_OPC_CheckField, 0, 20, 15, 76, 4, 0, // Skip to: 13161 +/* 12061 */ MCD_OPC_Decode, 162, 9, 215, 1, // Opcode: AE_MULZASFD32X16_H3_L2_S2 +/* 12066 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12104 +/* 12073 */ MCD_OPC_CheckPredicate, 24, 59, 4, 0, // Skip to: 13161 +/* 12078 */ MCD_OPC_CheckField, 32, 4, 0, 52, 4, 0, // Skip to: 13161 +/* 12085 */ MCD_OPC_CheckField, 24, 4, 0, 45, 4, 0, // Skip to: 13161 +/* 12092 */ MCD_OPC_CheckField, 0, 20, 15, 38, 4, 0, // Skip to: 13161 +/* 12099 */ MCD_OPC_Decode, 164, 9, 215, 1, // Opcode: AE_MULZSAD24_HH_LL_S2 +/* 12104 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12142 +/* 12111 */ MCD_OPC_CheckPredicate, 24, 21, 4, 0, // Skip to: 13161 +/* 12116 */ MCD_OPC_CheckField, 32, 4, 0, 14, 4, 0, // Skip to: 13161 +/* 12123 */ MCD_OPC_CheckField, 24, 4, 0, 7, 4, 0, // Skip to: 13161 +/* 12130 */ MCD_OPC_CheckField, 0, 20, 15, 0, 4, 0, // Skip to: 13161 +/* 12137 */ MCD_OPC_Decode, 166, 9, 215, 1, // Opcode: AE_MULZSAD32X16_H1_L0_S2 +/* 12142 */ MCD_OPC_FilterValue, 128, 128, 12, 244, 3, 0, // Skip to: 13161 +/* 12149 */ MCD_OPC_CheckPredicate, 24, 239, 3, 0, // Skip to: 13161 +/* 12154 */ MCD_OPC_CheckField, 32, 4, 0, 232, 3, 0, // Skip to: 13161 +/* 12161 */ MCD_OPC_CheckField, 24, 4, 0, 225, 3, 0, // Skip to: 13161 +/* 12168 */ MCD_OPC_CheckField, 0, 20, 15, 218, 3, 0, // Skip to: 13161 +/* 12175 */ MCD_OPC_Decode, 168, 9, 215, 1, // Opcode: AE_MULZSAD32X16_H3_L2_S2 +/* 12180 */ MCD_OPC_FilterValue, 54, 153, 0, 0, // Skip to: 12338 +/* 12185 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 12188 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12224 +/* 12193 */ MCD_OPC_CheckPredicate, 24, 195, 3, 0, // Skip to: 13161 +/* 12198 */ MCD_OPC_CheckField, 32, 4, 0, 188, 3, 0, // Skip to: 13161 +/* 12205 */ MCD_OPC_CheckField, 24, 4, 0, 181, 3, 0, // Skip to: 13161 +/* 12212 */ MCD_OPC_CheckField, 0, 20, 15, 174, 3, 0, // Skip to: 13161 +/* 12219 */ MCD_OPC_Decode, 170, 9, 215, 1, // Opcode: AE_MULZSAFD24_HH_LL_S2 +/* 12224 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12262 +/* 12231 */ MCD_OPC_CheckPredicate, 24, 157, 3, 0, // Skip to: 13161 +/* 12236 */ MCD_OPC_CheckField, 32, 4, 0, 150, 3, 0, // Skip to: 13161 +/* 12243 */ MCD_OPC_CheckField, 24, 4, 0, 143, 3, 0, // Skip to: 13161 +/* 12250 */ MCD_OPC_CheckField, 0, 20, 15, 136, 3, 0, // Skip to: 13161 +/* 12257 */ MCD_OPC_Decode, 172, 9, 215, 1, // Opcode: AE_MULZSAFD32X16_H1_L0_S2 +/* 12262 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12300 +/* 12269 */ MCD_OPC_CheckPredicate, 24, 119, 3, 0, // Skip to: 13161 +/* 12274 */ MCD_OPC_CheckField, 32, 4, 0, 112, 3, 0, // Skip to: 13161 +/* 12281 */ MCD_OPC_CheckField, 24, 4, 0, 105, 3, 0, // Skip to: 13161 +/* 12288 */ MCD_OPC_CheckField, 0, 20, 15, 98, 3, 0, // Skip to: 13161 +/* 12295 */ MCD_OPC_Decode, 174, 9, 215, 1, // Opcode: AE_MULZSAFD32X16_H3_L2_S2 +/* 12300 */ MCD_OPC_FilterValue, 128, 128, 12, 86, 3, 0, // Skip to: 13161 +/* 12307 */ MCD_OPC_CheckPredicate, 24, 81, 3, 0, // Skip to: 13161 +/* 12312 */ MCD_OPC_CheckField, 32, 4, 0, 74, 3, 0, // Skip to: 13161 +/* 12319 */ MCD_OPC_CheckField, 24, 4, 0, 67, 3, 0, // Skip to: 13161 +/* 12326 */ MCD_OPC_CheckField, 0, 20, 15, 60, 3, 0, // Skip to: 13161 +/* 12333 */ MCD_OPC_Decode, 176, 9, 215, 1, // Opcode: AE_MULZSSD24_HH_LL_S2 +/* 12338 */ MCD_OPC_FilterValue, 55, 153, 0, 0, // Skip to: 12496 +/* 12343 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 12346 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12382 +/* 12351 */ MCD_OPC_CheckPredicate, 24, 37, 3, 0, // Skip to: 13161 +/* 12356 */ MCD_OPC_CheckField, 32, 4, 0, 30, 3, 0, // Skip to: 13161 +/* 12363 */ MCD_OPC_CheckField, 24, 4, 0, 23, 3, 0, // Skip to: 13161 +/* 12370 */ MCD_OPC_CheckField, 0, 20, 15, 16, 3, 0, // Skip to: 13161 +/* 12377 */ MCD_OPC_Decode, 178, 9, 215, 1, // Opcode: AE_MULZSSD24_HL_LH_S2 +/* 12382 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12420 +/* 12389 */ MCD_OPC_CheckPredicate, 24, 255, 2, 0, // Skip to: 13161 +/* 12394 */ MCD_OPC_CheckField, 32, 4, 0, 248, 2, 0, // Skip to: 13161 +/* 12401 */ MCD_OPC_CheckField, 24, 4, 0, 241, 2, 0, // Skip to: 13161 +/* 12408 */ MCD_OPC_CheckField, 0, 20, 15, 234, 2, 0, // Skip to: 13161 +/* 12415 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: AE_MULZSSD32X16_H1_L0_S2 +/* 12420 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12458 +/* 12427 */ MCD_OPC_CheckPredicate, 24, 217, 2, 0, // Skip to: 13161 +/* 12432 */ MCD_OPC_CheckField, 32, 4, 0, 210, 2, 0, // Skip to: 13161 +/* 12439 */ MCD_OPC_CheckField, 24, 4, 0, 203, 2, 0, // Skip to: 13161 +/* 12446 */ MCD_OPC_CheckField, 0, 20, 15, 196, 2, 0, // Skip to: 13161 +/* 12453 */ MCD_OPC_Decode, 182, 9, 215, 1, // Opcode: AE_MULZSSD32X16_H3_L2_S2 +/* 12458 */ MCD_OPC_FilterValue, 128, 128, 12, 184, 2, 0, // Skip to: 13161 +/* 12465 */ MCD_OPC_CheckPredicate, 24, 179, 2, 0, // Skip to: 13161 +/* 12470 */ MCD_OPC_CheckField, 32, 4, 0, 172, 2, 0, // Skip to: 13161 +/* 12477 */ MCD_OPC_CheckField, 24, 4, 0, 165, 2, 0, // Skip to: 13161 +/* 12484 */ MCD_OPC_CheckField, 0, 20, 15, 158, 2, 0, // Skip to: 13161 +/* 12491 */ MCD_OPC_Decode, 184, 9, 215, 1, // Opcode: AE_MULZSSFD16SS_11_00_S2 +/* 12496 */ MCD_OPC_FilterValue, 56, 153, 0, 0, // Skip to: 12654 +/* 12501 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 12504 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12540 +/* 12509 */ MCD_OPC_CheckPredicate, 24, 135, 2, 0, // Skip to: 13161 +/* 12514 */ MCD_OPC_CheckField, 32, 4, 0, 128, 2, 0, // Skip to: 13161 +/* 12521 */ MCD_OPC_CheckField, 24, 4, 0, 121, 2, 0, // Skip to: 13161 +/* 12528 */ MCD_OPC_CheckField, 0, 20, 15, 114, 2, 0, // Skip to: 13161 +/* 12535 */ MCD_OPC_Decode, 186, 9, 215, 1, // Opcode: AE_MULZSSFD16SS_13_02_S2 +/* 12540 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12578 +/* 12547 */ MCD_OPC_CheckPredicate, 24, 97, 2, 0, // Skip to: 13161 +/* 12552 */ MCD_OPC_CheckField, 32, 4, 0, 90, 2, 0, // Skip to: 13161 +/* 12559 */ MCD_OPC_CheckField, 24, 4, 0, 83, 2, 0, // Skip to: 13161 +/* 12566 */ MCD_OPC_CheckField, 0, 20, 15, 76, 2, 0, // Skip to: 13161 +/* 12573 */ MCD_OPC_Decode, 188, 9, 215, 1, // Opcode: AE_MULZSSFD16SS_33_22_S2 +/* 12578 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12616 +/* 12585 */ MCD_OPC_CheckPredicate, 24, 59, 2, 0, // Skip to: 13161 +/* 12590 */ MCD_OPC_CheckField, 32, 4, 0, 52, 2, 0, // Skip to: 13161 +/* 12597 */ MCD_OPC_CheckField, 24, 4, 0, 45, 2, 0, // Skip to: 13161 +/* 12604 */ MCD_OPC_CheckField, 0, 20, 15, 38, 2, 0, // Skip to: 13161 +/* 12611 */ MCD_OPC_Decode, 190, 9, 215, 1, // Opcode: AE_MULZSSFD24_HH_LL_S2 +/* 12616 */ MCD_OPC_FilterValue, 128, 128, 12, 26, 2, 0, // Skip to: 13161 +/* 12623 */ MCD_OPC_CheckPredicate, 24, 21, 2, 0, // Skip to: 13161 +/* 12628 */ MCD_OPC_CheckField, 32, 4, 0, 14, 2, 0, // Skip to: 13161 +/* 12635 */ MCD_OPC_CheckField, 24, 4, 0, 7, 2, 0, // Skip to: 13161 +/* 12642 */ MCD_OPC_CheckField, 0, 20, 15, 0, 2, 0, // Skip to: 13161 +/* 12649 */ MCD_OPC_Decode, 192, 9, 215, 1, // Opcode: AE_MULZSSFD24_HL_LH_S2 +/* 12654 */ MCD_OPC_FilterValue, 57, 153, 0, 0, // Skip to: 12812 +/* 12659 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 12662 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12698 +/* 12667 */ MCD_OPC_CheckPredicate, 24, 233, 1, 0, // Skip to: 13161 +/* 12672 */ MCD_OPC_CheckField, 32, 4, 0, 226, 1, 0, // Skip to: 13161 +/* 12679 */ MCD_OPC_CheckField, 24, 4, 0, 219, 1, 0, // Skip to: 13161 +/* 12686 */ MCD_OPC_CheckField, 0, 20, 15, 212, 1, 0, // Skip to: 13161 +/* 12693 */ MCD_OPC_Decode, 194, 9, 215, 1, // Opcode: AE_MULZSSFD32X16_H1_L0_S2 +/* 12698 */ MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12736 +/* 12705 */ MCD_OPC_CheckPredicate, 24, 195, 1, 0, // Skip to: 13161 +/* 12710 */ MCD_OPC_CheckField, 32, 4, 0, 188, 1, 0, // Skip to: 13161 +/* 12717 */ MCD_OPC_CheckField, 24, 4, 0, 181, 1, 0, // Skip to: 13161 +/* 12724 */ MCD_OPC_CheckField, 0, 20, 15, 174, 1, 0, // Skip to: 13161 +/* 12731 */ MCD_OPC_Decode, 196, 9, 215, 1, // Opcode: AE_MULZSSFD32X16_H3_L2_S2 +/* 12736 */ MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12774 +/* 12743 */ MCD_OPC_CheckPredicate, 24, 157, 1, 0, // Skip to: 13161 +/* 12748 */ MCD_OPC_CheckField, 32, 4, 0, 150, 1, 0, // Skip to: 13161 +/* 12755 */ MCD_OPC_CheckField, 24, 4, 0, 143, 1, 0, // Skip to: 13161 +/* 12762 */ MCD_OPC_CheckField, 0, 20, 15, 136, 1, 0, // Skip to: 13161 +/* 12769 */ MCD_OPC_Decode, 213, 10, 226, 1, // Opcode: AE_SLAI16S +/* 12774 */ MCD_OPC_FilterValue, 128, 128, 12, 124, 1, 0, // Skip to: 13161 +/* 12781 */ MCD_OPC_CheckPredicate, 24, 119, 1, 0, // Skip to: 13161 +/* 12786 */ MCD_OPC_CheckField, 32, 4, 0, 112, 1, 0, // Skip to: 13161 +/* 12793 */ MCD_OPC_CheckField, 24, 4, 0, 105, 1, 0, // Skip to: 13161 +/* 12800 */ MCD_OPC_CheckField, 0, 20, 15, 98, 1, 0, // Skip to: 13161 +/* 12807 */ MCD_OPC_Decode, 236, 10, 226, 1, // Opcode: AE_SRAI16 +/* 12812 */ MCD_OPC_FilterValue, 58, 88, 1, 0, // Skip to: 13161 +/* 12817 */ MCD_OPC_ExtractField, 40, 18, // Inst{57-40} ... +/* 12820 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12856 +/* 12825 */ MCD_OPC_CheckPredicate, 24, 75, 1, 0, // Skip to: 13161 +/* 12830 */ MCD_OPC_CheckField, 32, 4, 0, 68, 1, 0, // Skip to: 13161 +/* 12837 */ MCD_OPC_CheckField, 24, 4, 0, 61, 1, 0, // Skip to: 13161 +/* 12844 */ MCD_OPC_CheckField, 0, 20, 15, 54, 1, 0, // Skip to: 13161 +/* 12851 */ MCD_OPC_Decode, 237, 10, 226, 1, // Opcode: AE_SRAI16R +/* 12856 */ MCD_OPC_FilterValue, 128, 128, 8, 42, 1, 0, // Skip to: 13161 +/* 12863 */ MCD_OPC_ExtractField, 32, 8, // Inst{39-32} ... +/* 12866 */ MCD_OPC_FilterValue, 16, 24, 0, 0, // Skip to: 12895 +/* 12871 */ MCD_OPC_CheckPredicate, 24, 29, 1, 0, // Skip to: 13161 +/* 12876 */ MCD_OPC_CheckField, 24, 4, 0, 22, 1, 0, // Skip to: 13161 +/* 12883 */ MCD_OPC_CheckField, 0, 20, 15, 15, 1, 0, // Skip to: 13161 +/* 12890 */ MCD_OPC_Decode, 222, 10, 225, 1, // Opcode: AE_SLAS24S +/* 12895 */ MCD_OPC_FilterValue, 32, 24, 0, 0, // Skip to: 12924 +/* 12900 */ MCD_OPC_CheckPredicate, 24, 0, 1, 0, // Skip to: 13161 +/* 12905 */ MCD_OPC_CheckField, 24, 4, 0, 249, 0, 0, // Skip to: 13161 +/* 12912 */ MCD_OPC_CheckField, 0, 20, 15, 242, 0, 0, // Skip to: 13161 +/* 12919 */ MCD_OPC_Decode, 223, 10, 225, 1, // Opcode: AE_SLAS32 +/* 12924 */ MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 12953 +/* 12929 */ MCD_OPC_CheckPredicate, 24, 227, 0, 0, // Skip to: 13161 +/* 12934 */ MCD_OPC_CheckField, 24, 4, 0, 220, 0, 0, // Skip to: 13161 +/* 12941 */ MCD_OPC_CheckField, 0, 20, 15, 213, 0, 0, // Skip to: 13161 +/* 12948 */ MCD_OPC_Decode, 224, 10, 225, 1, // Opcode: AE_SLAS32S +/* 12953 */ MCD_OPC_FilterValue, 64, 24, 0, 0, // Skip to: 12982 +/* 12958 */ MCD_OPC_CheckPredicate, 24, 198, 0, 0, // Skip to: 13161 +/* 12963 */ MCD_OPC_CheckField, 24, 4, 0, 191, 0, 0, // Skip to: 13161 +/* 12970 */ MCD_OPC_CheckField, 0, 20, 15, 184, 0, 0, // Skip to: 13161 +/* 12977 */ MCD_OPC_Decode, 225, 10, 225, 1, // Opcode: AE_SLAS64 +/* 12982 */ MCD_OPC_FilterValue, 112, 24, 0, 0, // Skip to: 13011 +/* 12987 */ MCD_OPC_CheckPredicate, 24, 169, 0, 0, // Skip to: 13161 +/* 12992 */ MCD_OPC_CheckField, 24, 4, 0, 162, 0, 0, // Skip to: 13161 +/* 12999 */ MCD_OPC_CheckField, 0, 20, 15, 155, 0, 0, // Skip to: 13161 +/* 13006 */ MCD_OPC_Decode, 228, 10, 225, 1, // Opcode: AE_SLASSQ56S +/* 13011 */ MCD_OPC_FilterValue, 144, 1, 24, 0, 0, // Skip to: 13041 +/* 13017 */ MCD_OPC_CheckPredicate, 24, 139, 0, 0, // Skip to: 13161 +/* 13022 */ MCD_OPC_CheckField, 24, 4, 0, 132, 0, 0, // Skip to: 13161 +/* 13029 */ MCD_OPC_CheckField, 0, 20, 15, 125, 0, 0, // Skip to: 13161 +/* 13036 */ MCD_OPC_Decode, 243, 10, 225, 1, // Opcode: AE_SRAS32 +/* 13041 */ MCD_OPC_FilterValue, 160, 1, 24, 0, 0, // Skip to: 13071 +/* 13047 */ MCD_OPC_CheckPredicate, 24, 109, 0, 0, // Skip to: 13161 +/* 13052 */ MCD_OPC_CheckField, 24, 4, 0, 102, 0, 0, // Skip to: 13161 +/* 13059 */ MCD_OPC_CheckField, 0, 20, 15, 95, 0, 0, // Skip to: 13161 +/* 13066 */ MCD_OPC_Decode, 244, 10, 225, 1, // Opcode: AE_SRAS64 +/* 13071 */ MCD_OPC_FilterValue, 192, 1, 24, 0, 0, // Skip to: 13101 +/* 13077 */ MCD_OPC_CheckPredicate, 24, 79, 0, 0, // Skip to: 13161 +/* 13082 */ MCD_OPC_CheckField, 24, 4, 0, 72, 0, 0, // Skip to: 13161 +/* 13089 */ MCD_OPC_CheckField, 0, 20, 15, 65, 0, 0, // Skip to: 13161 +/* 13096 */ MCD_OPC_Decode, 250, 10, 225, 1, // Opcode: AE_SRLS24 +/* 13101 */ MCD_OPC_FilterValue, 208, 1, 24, 0, 0, // Skip to: 13131 +/* 13107 */ MCD_OPC_CheckPredicate, 24, 49, 0, 0, // Skip to: 13161 +/* 13112 */ MCD_OPC_CheckField, 24, 4, 0, 42, 0, 0, // Skip to: 13161 +/* 13119 */ MCD_OPC_CheckField, 0, 20, 15, 35, 0, 0, // Skip to: 13161 +/* 13126 */ MCD_OPC_Decode, 251, 10, 225, 1, // Opcode: AE_SRLS32 +/* 13131 */ MCD_OPC_FilterValue, 224, 1, 24, 0, 0, // Skip to: 13161 +/* 13137 */ MCD_OPC_CheckPredicate, 24, 19, 0, 0, // Skip to: 13161 +/* 13142 */ MCD_OPC_CheckField, 24, 4, 0, 12, 0, 0, // Skip to: 13161 +/* 13149 */ MCD_OPC_CheckField, 0, 20, 15, 5, 0, 0, // Skip to: 13161 +/* 13156 */ MCD_OPC_Decode, 252, 10, 225, 1, // Opcode: AE_SRLS64 +/* 13161 */ MCD_OPC_Fail, 0 }; static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) { - llvm_unreachable("Invalid index!"); - return true; + switch (Idx) { + default: CS_ASSERT_RET_VAL(0 && "Invalid index!", false); + case 0: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDensity)); + case 1: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDensity) && Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDebug)); + case 2: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureWindowed) && Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDensity)); + case 3: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureWindowed)); + case 4: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureException)); + case 5: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureInterrupt)); + case 6: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDebug)); + case 7: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureBoolean)); + case 8: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureRegionProtection)); + case 9: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureNSA)); + case 10: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMul16)); + case 11: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureSEXT)); + case 12: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureCLAMPS)); + case 13: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMINMAX)); + case 14: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMul32)); + case 15: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMul32High)); + case 16: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDiv32)); + case 17: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureESP32S2Ops)); + case 18: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureSingleFloat)); + case 19: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureBoolean) && Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureSingleFloat)); + case 20: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureS32C1I)); + case 21: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMAC16)); + case 22: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureESP32S3Ops)); + case 23: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureLoop)); + case 24: + return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureHIFI3)); + } } #define DecodeToMCInst(fname, fieldname, InsnType) \ @@ -308,202 +7100,2358 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M *DecodeComplete = true; \ InsnType tmp; \ switch (Idx) { \ - default: /* llvm_unreachable("Invalid index!"); */ \ + default: CS_ASSERT_RET_VAL(0 && "Invalid index!", MCDisassembler_Fail); \ case 0: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 8); \ + if (!Check(&S, decodeMem32nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 1: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeImm1n_15Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 3: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 3) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (!Check(&S, decodeImm32n_95Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 6: \ + return S; \ + case 7: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 11: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 4; \ + if (!Check(&S, decodeShimm1_31Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 12: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 4; \ + if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 13: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeImm8n_7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 15: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 16: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 8); \ + if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 8); \ + if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 8); \ + if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 8, 8); \ + if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 8); \ + if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 26: \ + tmp = fieldname(insn, 8, 8); \ + if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 27: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 16, 1) << 4; \ + if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 4, 8); \ + if (!Check(&S, decodeSelect_256Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4) << 2; \ + if (!Check(&S, decodeImm64n_4nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 34: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 37: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 41: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 42: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 45: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 46: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 16); \ + if (!Check(&S, decodeL32ROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 47: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 16, 8) << 4; \ + if (!Check(&S, decodeMem8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 48: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 16, 8) << 4; \ + if (!Check(&S, decodeMem16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 49: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 16, 8) << 4; \ + if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 50: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + tmp |= fieldname(insn, 16, 8) << 0; \ + if (!Check(&S, decodeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 51: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + if (!Check(&S, decodeImm8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 52: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8) << 8; \ + if (!Check(&S, decodeImm8_sh8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 53: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 16, 8) << 4; \ + if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 16, 8) << 4; \ + if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 55: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8) << 2; \ + if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8) << 2; \ + if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 57: \ + tmp = fieldname(insn, 12, 2); \ + if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 1); \ + if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 1); \ + if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 58: \ + tmp = fieldname(insn, 14, 1); \ + if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 1); \ + if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 59: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 1); \ + if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 60: \ + tmp = fieldname(insn, 12, 2); \ + if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 1); \ + if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 61: \ + tmp = fieldname(insn, 12, 2); \ + if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 1); \ + if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 14, 1); \ + if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 12, 2); \ + if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 64: \ + tmp = fieldname(insn, 6, 18); \ + if (!Check(&S, decodeCallOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 65: \ + tmp = fieldname(insn, 6, 18); \ + if (!Check(&S, decodeJumpOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 12); \ + if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeB4constOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 12) << 3; \ + if (!Check(&S, decodeEntry_Imm12OpValue(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + if (!Check(&S, decodeLoopOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeB4constuOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 72: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 73: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 4) << 0; \ + tmp |= fieldname(insn, 12, 1) << 4; \ + if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 7) << 0; \ + tmp |= fieldname(insn, 22, 1) << 7; \ + if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 76: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 7) << 0; \ + tmp |= fieldname(insn, 22, 1) << 7; \ + if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 77: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 7) << 0; \ + tmp |= fieldname(insn, 22, 1) << 7; \ + if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 78: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 7) << 0; \ + tmp |= fieldname(insn, 22, 1) << 7; \ + if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 79: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 7) << 0; \ + tmp |= fieldname(insn, 22, 1) << 7; \ + if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 7) << 0; \ + tmp |= fieldname(insn, 22, 1) << 7; \ + if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 82: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 7); \ + if (!Check(&S, decodeOffset_128_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 83: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 7); \ + if (!Check(&S, decodeOffset_128_1Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 84: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 85: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 86: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 87: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + tmp |= fieldname(insn, 20, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 14, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 88: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 7) << 0; \ + tmp |= fieldname(insn, 22, 1) << 7; \ + if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 89: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 14, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 90: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 7) << 0; \ + tmp |= fieldname(insn, 22, 1) << 7; \ + if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 91: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 14, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 92: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 6, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + tmp |= fieldname(insn, 10, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 1); \ + if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 93: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 94: \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 96: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 97: \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 98: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 99: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 100: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 101: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 102: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 6, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + tmp |= fieldname(insn, 10, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 103: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 2); \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 104: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 1); \ + if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 105: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 106: \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 107: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 2); \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 108: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 1); \ + if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 109: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 110: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 6, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 111: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 112: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 1); \ + if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 113: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 14, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 114: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 14, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 115: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 14, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + tmp |= fieldname(insn, 20, 2) << 2; \ + if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 116: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 14, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 117: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 15, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + tmp |= fieldname(insn, 10, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 118: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 26, 2) << 4; \ + if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 119: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 3) << 1; \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 16, 3) << 1; \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 120: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 3) << 1; \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 16, 3) << 1; \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 121: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 3) << 1; \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 16, 3) << 1; \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 122: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 3) << 1; \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 16, 3) << 1; \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 123: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 26, 1); \ + if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 124: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 1) << 1; \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 25, 2); \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 125: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 126: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 19, 1) << 1; \ + tmp |= fieldname(insn, 24, 1) << 2; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 25, 1); \ + if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 127: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 128: \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 2) << 0; \ + tmp |= fieldname(insn, 12, 2) << 3; \ + tmp |= fieldname(insn, 19, 1) << 5; \ + tmp |= fieldname(insn, 23, 1) << 2; \ + tmp |= fieldname(insn, 24, 2) << 6; \ + if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 129: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 1; \ + tmp |= fieldname(insn, 8, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + tmp |= fieldname(insn, 24, 2) << 6; \ + if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 130: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 1; \ + tmp |= fieldname(insn, 8, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + tmp |= fieldname(insn, 24, 2) << 6; \ + if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 131: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 132: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 2); \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 133: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 134: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 3) << 1; \ + tmp |= fieldname(insn, 20, 1) << 0; \ + if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 135: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 136: \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 1) << 1; \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 137: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 2); \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 138: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 139: \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 1) << 1; \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 140: \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 141: \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 3); \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 142: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 26, 2) << 4; \ + if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 143: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 1) << 0; \ + tmp |= fieldname(insn, 24, 2) << 1; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 2; \ + tmp |= fieldname(insn, 14, 2) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 2) << 1; \ + tmp |= fieldname(insn, 23, 1) << 0; \ + if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 144: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 145: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 146: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 147: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 148: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 149: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 150: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 151: \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 152: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 153: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 154: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 155: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 156: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 157: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 158: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 159: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 160: \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 161: \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 162: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 163: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 164: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 3); \ + if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 165: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 166: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 2: \ + case 167: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 8, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 168: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 169: \ tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 3: \ + case 170: \ tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 171: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 172: \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0x0; \ - tmp |= fieldname(insn, 4, 4) << 0; \ - tmp |= fieldname(insn, 20, 1) << 4; \ - if (!Check(&S, decodeShimm1_31Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 4: \ + case 173: \ tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0x0; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - tmp |= fieldname(insn, 20, 1) << 4; \ - if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 5: \ - tmp = 0x0; \ - tmp |= fieldname(insn, 4, 1) << 4; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + case 174: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 6: \ + case 175: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 176: \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 7: \ - tmp = fieldname(insn, 12, 4); \ + case 177: \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 4, 4); \ + return S; \ + case 178: \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 8: \ - tmp = fieldname(insn, 4, 4); \ + case 179: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 8); \ - if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 8); \ - if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 9: \ - tmp = fieldname(insn, 12, 4); \ + case 180: \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 10: \ tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 181: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 8); \ - if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 11: \ - tmp = fieldname(insn, 8, 8); \ - if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + case 182: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 16, 2) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 12: \ + case 183: \ tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0x0; \ tmp |= fieldname(insn, 8, 4) << 0; \ tmp |= fieldname(insn, 16, 1) << 4; \ if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 4); \ - if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 13: \ + case 184: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 16); \ - if (!Check(&S, decodeL32ROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 14: \ - tmp = fieldname(insn, 4, 4); \ + case 185: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0x0; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - tmp |= fieldname(insn, 16, 8) << 4; \ - if (!Check(&S, decodeMem8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 15: \ tmp = fieldname(insn, 4, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0x0; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - tmp |= fieldname(insn, 16, 8) << 4; \ - if (!Check(&S, decodeMem16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 16: \ - tmp = fieldname(insn, 4, 4); \ + case 186: \ + tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0x0; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - tmp |= fieldname(insn, 16, 8) << 4; \ - if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 17: \ + case 187: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0x0; \ - tmp |= fieldname(insn, 8, 4) << 8; \ - tmp |= fieldname(insn, 16, 8) << 0; \ - if (!Check(&S, decodeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 18: \ tmp = fieldname(insn, 4, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 8); \ - if (!Check(&S, decodeImm8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 19: \ + case 188: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 8) << 8; \ - if (!Check(&S, decodeImm8_sh8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 20: \ - tmp = fieldname(insn, 6, 18); \ - if (!Check(&S, decodeCallOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + case 189: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 21: \ - tmp = fieldname(insn, 6, 18); \ - if (!Check(&S, decodeJumpOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + case 190: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 22: \ + case 191: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 192: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 193: \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 12); \ - if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 23: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 194: \ tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, decodeB4constOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 8); \ - if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 24: \ + case 195: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, decodeB4constuOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 8); \ - if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 25: \ + case 196: \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 197: \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 198: \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 28, 2) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 199: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 200: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 8); \ - if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 26: \ + case 201: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 202: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 203: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 48, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 204: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 205: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 206: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 207: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 208: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 209: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 210: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 211: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0x0; \ - tmp |= fieldname(insn, 4, 4) << 0; \ - tmp |= fieldname(insn, 12, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + tmp |= fieldname(insn, 56, 2) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 212: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 213: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 214: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + tmp |= fieldname(insn, 56, 1) << 4; \ if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 8); \ - if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 215: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 216: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 217: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 218: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 219: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 220: \ + tmp = fieldname(insn, 21, 3); \ + if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 221: \ + tmp = fieldname(insn, 22, 2); \ + if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 222: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 2); \ + if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 223: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 224: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 225: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 226: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ } \ } @@ -603,6 +9551,9 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ /* Decoding complete. */ \ return S; \ } else { \ + /* LLVM uses a MCInst on the stack, but for our use case, */ \ + /* it is enough for now to reset the op counter. */ \ + MCInst_clear(MI); \ /* If the decoding was incomplete, skip. */ \ Ptr += NumToSkip; \ /* Reset decode status. This also drops a SoftFail status that could be */ \ @@ -631,3 +9582,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ /* Bogisity detected in disassembler state machine! */ \ } +FieldFromInstruction(fieldFromInstruction_3, uint64_t) +DecodeToMCInst(decodeToMCInst_3, fieldFromInstruction_3, uint64_t) +DecodeInstruction(decodeInstruction_3, fieldFromInstruction_3, decodeToMCInst_3, uint64_t) + diff --git a/arch/Xtensa/XtensaGenInstrInfo.inc b/arch/Xtensa/XtensaGenInstrInfo.inc index d9438d6357..3af7cdcd31 100644 --- a/arch/Xtensa/XtensaGenInstrInfo.inc +++ b/arch/Xtensa/XtensaGenInstrInfo.inc @@ -286,95 +286,1736 @@ Xtensa_G_VECREDUCE_UMIN = 268, Xtensa_G_SBFX = 269, Xtensa_G_UBFX = 270, - Xtensa_ABS = 271, - Xtensa_ADD = 272, - Xtensa_ADDI = 273, - Xtensa_ADDMI = 274, - Xtensa_ADDX2 = 275, - Xtensa_ADDX4 = 276, - Xtensa_ADDX8 = 277, - Xtensa_AND = 278, - Xtensa_BALL = 279, - Xtensa_BANY = 280, - Xtensa_BBC = 281, - Xtensa_BBCI = 282, - Xtensa_BBS = 283, - Xtensa_BBSI = 284, - Xtensa_BEQ = 285, - Xtensa_BEQI = 286, - Xtensa_BEQZ = 287, - Xtensa_BGE = 288, - Xtensa_BGEI = 289, - Xtensa_BGEU = 290, - Xtensa_BGEUI = 291, - Xtensa_BGEZ = 292, - Xtensa_BLT = 293, - Xtensa_BLTI = 294, - Xtensa_BLTU = 295, - Xtensa_BLTUI = 296, - Xtensa_BLTZ = 297, - Xtensa_BNALL = 298, - Xtensa_BNE = 299, - Xtensa_BNEI = 300, - Xtensa_BNEZ = 301, - Xtensa_BNONE = 302, - Xtensa_CALL0 = 303, - Xtensa_CALLX0 = 304, - Xtensa_DSYNC = 305, - Xtensa_ESYNC = 306, - Xtensa_EXTUI = 307, - Xtensa_EXTW = 308, - Xtensa_ISYNC = 309, - Xtensa_J = 310, - Xtensa_JX = 311, - Xtensa_L16SI = 312, - Xtensa_L16UI = 313, - Xtensa_L32I = 314, - Xtensa_L32R = 315, - Xtensa_L8UI = 316, - Xtensa_MEMW = 317, - Xtensa_MOVEQZ = 318, - Xtensa_MOVGEZ = 319, - Xtensa_MOVI = 320, - Xtensa_MOVLTZ = 321, - Xtensa_MOVNEZ = 322, - Xtensa_NEG = 323, - Xtensa_NOP = 324, - Xtensa_OR = 325, - Xtensa_RET = 326, - Xtensa_RSR = 327, - Xtensa_RSYNC = 328, - Xtensa_S16I = 329, - Xtensa_S32I = 330, - Xtensa_S8I = 331, - Xtensa_SLL = 332, - Xtensa_SLLI = 333, - Xtensa_SRA = 334, - Xtensa_SRAI = 335, - Xtensa_SRC = 336, - Xtensa_SRL = 337, - Xtensa_SRLI = 338, - Xtensa_SSA8L = 339, - Xtensa_SSAI = 340, - Xtensa_SSL = 341, - Xtensa_SSR = 342, - Xtensa_SUB = 343, - Xtensa_SUBX2 = 344, - Xtensa_SUBX4 = 345, - Xtensa_SUBX8 = 346, - Xtensa_WSR = 347, - Xtensa_XOR = 348, - Xtensa_XSR = 349, - INSTRUCTION_LIST_END = 350 + Xtensa_ADJCALLSTACKDOWN = 271, + Xtensa_ADJCALLSTACKUP = 272, + Xtensa_ATOMIC_CMP_SWAP_16_P = 273, + Xtensa_ATOMIC_CMP_SWAP_32_P = 274, + Xtensa_ATOMIC_CMP_SWAP_8_P = 275, + Xtensa_ATOMIC_LOAD_ADD_16_P = 276, + Xtensa_ATOMIC_LOAD_ADD_32_P = 277, + Xtensa_ATOMIC_LOAD_ADD_8_P = 278, + Xtensa_ATOMIC_LOAD_AND_16_P = 279, + Xtensa_ATOMIC_LOAD_AND_32_P = 280, + Xtensa_ATOMIC_LOAD_AND_8_P = 281, + Xtensa_ATOMIC_LOAD_MAX_16_P = 282, + Xtensa_ATOMIC_LOAD_MAX_32_P = 283, + Xtensa_ATOMIC_LOAD_MAX_8_P = 284, + Xtensa_ATOMIC_LOAD_MIN_16_P = 285, + Xtensa_ATOMIC_LOAD_MIN_32_P = 286, + Xtensa_ATOMIC_LOAD_MIN_8_P = 287, + Xtensa_ATOMIC_LOAD_NAND_16_P = 288, + Xtensa_ATOMIC_LOAD_NAND_32_P = 289, + Xtensa_ATOMIC_LOAD_NAND_8_P = 290, + Xtensa_ATOMIC_LOAD_OR_16_P = 291, + Xtensa_ATOMIC_LOAD_OR_32_P = 292, + Xtensa_ATOMIC_LOAD_OR_8_P = 293, + Xtensa_ATOMIC_LOAD_SUB_16_P = 294, + Xtensa_ATOMIC_LOAD_SUB_32_P = 295, + Xtensa_ATOMIC_LOAD_SUB_8_P = 296, + Xtensa_ATOMIC_LOAD_UMAX_16_P = 297, + Xtensa_ATOMIC_LOAD_UMAX_32_P = 298, + Xtensa_ATOMIC_LOAD_UMAX_8_P = 299, + Xtensa_ATOMIC_LOAD_UMIN_16_P = 300, + Xtensa_ATOMIC_LOAD_UMIN_32_P = 301, + Xtensa_ATOMIC_LOAD_UMIN_8_P = 302, + Xtensa_ATOMIC_LOAD_XOR_16_P = 303, + Xtensa_ATOMIC_LOAD_XOR_32_P = 304, + Xtensa_ATOMIC_LOAD_XOR_8_P = 305, + Xtensa_ATOMIC_SWAP_16_P = 306, + Xtensa_ATOMIC_SWAP_32_P = 307, + Xtensa_ATOMIC_SWAP_8_P = 308, + Xtensa_BRCC_FP = 309, + Xtensa_BR_JT = 310, + Xtensa_CONSTPOOL_ENTRY = 311, + Xtensa_EE_ANDQ_P = 312, + Xtensa_EE_BITREV_P = 313, + Xtensa_EE_CMUL_S16_LD_INCP_P = 314, + Xtensa_EE_CMUL_S16_P = 315, + Xtensa_EE_CMUL_S16_ST_INCP_P = 316, + Xtensa_EE_FFT_AMS_S16_LD_INCP_P = 317, + Xtensa_EE_FFT_AMS_S16_LD_INCP_UAUP_P = 318, + Xtensa_EE_FFT_AMS_S16_LD_R32_DECP_P = 319, + Xtensa_EE_FFT_AMS_S16_ST_INCP_P = 320, + Xtensa_EE_FFT_CMUL_S16_LD_XP_P = 321, + Xtensa_EE_FFT_CMUL_S16_ST_XP_P = 322, + Xtensa_EE_FFT_R2BF_S16_P = 323, + Xtensa_EE_FFT_R2BF_S16_ST_INCP_P = 324, + Xtensa_EE_FFT_VST_R32_DECP_P = 325, + Xtensa_EE_LDF_128_IP_P = 326, + Xtensa_EE_LDF_128_XP_P = 327, + Xtensa_EE_LDF_64_IP_P = 328, + Xtensa_EE_LDF_64_XP_P = 329, + Xtensa_EE_LDQA_S16_128_IP_P = 330, + Xtensa_EE_LDQA_S16_128_XP_P = 331, + Xtensa_EE_LDQA_S8_128_IP_P = 332, + Xtensa_EE_LDQA_S8_128_XP_P = 333, + Xtensa_EE_LDQA_U16_128_IP_P = 334, + Xtensa_EE_LDQA_U16_128_XP_P = 335, + Xtensa_EE_LDQA_U8_128_IP_P = 336, + Xtensa_EE_LDQA_U8_128_XP_P = 337, + Xtensa_EE_LDXQ_32_P = 338, + Xtensa_EE_LD_128_USAR_IP_P = 339, + Xtensa_EE_LD_128_USAR_XP_P = 340, + Xtensa_EE_LD_ACCX_IP_P = 341, + Xtensa_EE_LD_QACC_H_H_32_IP_P = 342, + Xtensa_EE_LD_QACC_H_L_128_IP_P = 343, + Xtensa_EE_LD_QACC_L_H_32_IP_P = 344, + Xtensa_EE_LD_QACC_L_L_128_IP_P = 345, + Xtensa_EE_LD_UA_STATE_IP_P = 346, + Xtensa_EE_MOVI_32_A_P = 347, + Xtensa_EE_MOVI_32_Q_P = 348, + Xtensa_EE_MOV_S16_QACC_P = 349, + Xtensa_EE_MOV_S8_QACC_P = 350, + Xtensa_EE_MOV_U16_QACC_P = 351, + Xtensa_EE_MOV_U8_QACC_P = 352, + Xtensa_EE_NOTQ_P = 353, + Xtensa_EE_ORQ_P = 354, + Xtensa_EE_SLCI_2Q_P = 355, + Xtensa_EE_SLCXXP_2Q_P = 356, + Xtensa_EE_SRCI_2Q_P = 357, + Xtensa_EE_SRCMB_S16_QACC_P = 358, + Xtensa_EE_SRCMB_S8_QACC_P = 359, + Xtensa_EE_SRCQ_128_ST_INCP_P = 360, + Xtensa_EE_SRCXXP_2Q_P = 361, + Xtensa_EE_SRC_Q_LD_IP_P = 362, + Xtensa_EE_SRC_Q_LD_XP_P = 363, + Xtensa_EE_SRC_Q_P = 364, + Xtensa_EE_SRC_Q_QUP_P = 365, + Xtensa_EE_SRS_ACCX_P = 366, + Xtensa_EE_STF_128_IP_P = 367, + Xtensa_EE_STF_128_XP_P = 368, + Xtensa_EE_STF_64_IP_P = 369, + Xtensa_EE_STF_64_XP_P = 370, + Xtensa_EE_STXQ_32_P = 371, + Xtensa_EE_ST_ACCX_IP_P = 372, + Xtensa_EE_ST_QACC_H_H_32_IP_P = 373, + Xtensa_EE_ST_QACC_H_L_128_IP_P = 374, + Xtensa_EE_ST_QACC_L_H_32_IP_P = 375, + Xtensa_EE_ST_QACC_L_L_128_IP_P = 376, + Xtensa_EE_ST_UA_STATE_IP_P = 377, + Xtensa_EE_VADDS_S16_LD_INCP_P = 378, + Xtensa_EE_VADDS_S16_P = 379, + Xtensa_EE_VADDS_S16_ST_INCP_P = 380, + Xtensa_EE_VADDS_S32_LD_INCP_P = 381, + Xtensa_EE_VADDS_S32_P = 382, + Xtensa_EE_VADDS_S32_ST_INCP_P = 383, + Xtensa_EE_VADDS_S8_LD_INCP_P = 384, + Xtensa_EE_VADDS_S8_P = 385, + Xtensa_EE_VADDS_S8_ST_INCP_P = 386, + Xtensa_EE_VCMP_EQ_S16_P = 387, + Xtensa_EE_VCMP_EQ_S32_P = 388, + Xtensa_EE_VCMP_EQ_S8_P = 389, + Xtensa_EE_VCMP_GT_S16_P = 390, + Xtensa_EE_VCMP_GT_S32_P = 391, + Xtensa_EE_VCMP_GT_S8_P = 392, + Xtensa_EE_VCMP_LT_S16_P = 393, + Xtensa_EE_VCMP_LT_S32_P = 394, + Xtensa_EE_VCMP_LT_S8_P = 395, + Xtensa_EE_VLDBC_16_IP_P = 396, + Xtensa_EE_VLDBC_16_P = 397, + Xtensa_EE_VLDBC_16_XP_P = 398, + Xtensa_EE_VLDBC_32_IP_P = 399, + Xtensa_EE_VLDBC_32_P = 400, + Xtensa_EE_VLDBC_32_XP_P = 401, + Xtensa_EE_VLDBC_8_IP_P = 402, + Xtensa_EE_VLDBC_8_P = 403, + Xtensa_EE_VLDBC_8_XP_P = 404, + Xtensa_EE_VLDHBC_16_INCP_P = 405, + Xtensa_EE_VLD_128_IP_P = 406, + Xtensa_EE_VLD_128_XP_P = 407, + Xtensa_EE_VLD_H_64_IP_P = 408, + Xtensa_EE_VLD_H_64_XP_P = 409, + Xtensa_EE_VLD_L_64_IP_P = 410, + Xtensa_EE_VLD_L_64_XP_P = 411, + Xtensa_EE_VMAX_S16_LD_INCP_P = 412, + Xtensa_EE_VMAX_S16_P = 413, + Xtensa_EE_VMAX_S16_ST_INCP_P = 414, + Xtensa_EE_VMAX_S32_LD_INCP_P = 415, + Xtensa_EE_VMAX_S32_P = 416, + Xtensa_EE_VMAX_S32_ST_INCP_P = 417, + Xtensa_EE_VMAX_S8_LD_INCP_P = 418, + Xtensa_EE_VMAX_S8_P = 419, + Xtensa_EE_VMAX_S8_ST_INCP_P = 420, + Xtensa_EE_VMIN_S16_LD_INCP_P = 421, + Xtensa_EE_VMIN_S16_P = 422, + Xtensa_EE_VMIN_S16_ST_INCP_P = 423, + Xtensa_EE_VMIN_S32_LD_INCP_P = 424, + Xtensa_EE_VMIN_S32_P = 425, + Xtensa_EE_VMIN_S32_ST_INCP_P = 426, + Xtensa_EE_VMIN_S8_LD_INCP_P = 427, + Xtensa_EE_VMIN_S8_P = 428, + Xtensa_EE_VMIN_S8_ST_INCP_P = 429, + Xtensa_EE_VMULAS_S16_ACCX_LD_IP_P = 430, + Xtensa_EE_VMULAS_S16_ACCX_LD_IP_QUP_P = 431, + Xtensa_EE_VMULAS_S16_ACCX_LD_XP_P = 432, + Xtensa_EE_VMULAS_S16_ACCX_LD_XP_QUP_P = 433, + Xtensa_EE_VMULAS_S16_ACCX_P = 434, + Xtensa_EE_VMULAS_S16_QACC_LDBC_INCP_P = 435, + Xtensa_EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P = 436, + Xtensa_EE_VMULAS_S16_QACC_LD_IP_P = 437, + Xtensa_EE_VMULAS_S16_QACC_LD_IP_QUP_P = 438, + Xtensa_EE_VMULAS_S16_QACC_LD_XP_P = 439, + Xtensa_EE_VMULAS_S16_QACC_LD_XP_QUP_P = 440, + Xtensa_EE_VMULAS_S16_QACC_P = 441, + Xtensa_EE_VMULAS_S8_ACCX_LD_IP_P = 442, + Xtensa_EE_VMULAS_S8_ACCX_LD_IP_QUP_P = 443, + Xtensa_EE_VMULAS_S8_ACCX_LD_XP_P = 444, + Xtensa_EE_VMULAS_S8_ACCX_LD_XP_QUP_P = 445, + Xtensa_EE_VMULAS_S8_ACCX_P = 446, + Xtensa_EE_VMULAS_S8_QACC_LDBC_INCP_P = 447, + Xtensa_EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P = 448, + Xtensa_EE_VMULAS_S8_QACC_LD_IP_P = 449, + Xtensa_EE_VMULAS_S8_QACC_LD_IP_QUP_P = 450, + Xtensa_EE_VMULAS_S8_QACC_LD_XP_P = 451, + Xtensa_EE_VMULAS_S8_QACC_LD_XP_QUP_P = 452, + Xtensa_EE_VMULAS_S8_QACC_P = 453, + Xtensa_EE_VMULAS_U16_ACCX_LD_IP_P = 454, + Xtensa_EE_VMULAS_U16_ACCX_LD_IP_QUP_P = 455, + Xtensa_EE_VMULAS_U16_ACCX_LD_XP_P = 456, + Xtensa_EE_VMULAS_U16_ACCX_LD_XP_QUP_P = 457, + Xtensa_EE_VMULAS_U16_ACCX_P = 458, + Xtensa_EE_VMULAS_U16_QACC_LDBC_INCP_P = 459, + Xtensa_EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P = 460, + Xtensa_EE_VMULAS_U16_QACC_LD_IP_P = 461, + Xtensa_EE_VMULAS_U16_QACC_LD_IP_QUP_P = 462, + Xtensa_EE_VMULAS_U16_QACC_LD_XP_P = 463, + Xtensa_EE_VMULAS_U16_QACC_LD_XP_QUP_P = 464, + Xtensa_EE_VMULAS_U16_QACC_P = 465, + Xtensa_EE_VMULAS_U8_ACCX_LD_IP_P = 466, + Xtensa_EE_VMULAS_U8_ACCX_LD_IP_QUP_P = 467, + Xtensa_EE_VMULAS_U8_ACCX_LD_XP_P = 468, + Xtensa_EE_VMULAS_U8_ACCX_LD_XP_QUP_P = 469, + Xtensa_EE_VMULAS_U8_ACCX_P = 470, + Xtensa_EE_VMULAS_U8_QACC_LDBC_INCP_P = 471, + Xtensa_EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P = 472, + Xtensa_EE_VMULAS_U8_QACC_LD_IP_P = 473, + Xtensa_EE_VMULAS_U8_QACC_LD_IP_QUP_P = 474, + Xtensa_EE_VMULAS_U8_QACC_LD_XP_P = 475, + Xtensa_EE_VMULAS_U8_QACC_LD_XP_QUP_P = 476, + Xtensa_EE_VMULAS_U8_QACC_P = 477, + Xtensa_EE_VMUL_S16_LD_INCP_P = 478, + Xtensa_EE_VMUL_S16_P = 479, + Xtensa_EE_VMUL_S16_ST_INCP_P = 480, + Xtensa_EE_VMUL_S8_LD_INCP_P = 481, + Xtensa_EE_VMUL_S8_P = 482, + Xtensa_EE_VMUL_S8_ST_INCP_P = 483, + Xtensa_EE_VMUL_U16_LD_INCP_P = 484, + Xtensa_EE_VMUL_U16_P = 485, + Xtensa_EE_VMUL_U16_ST_INCP_P = 486, + Xtensa_EE_VMUL_U8_LD_INCP_P = 487, + Xtensa_EE_VMUL_U8_P = 488, + Xtensa_EE_VMUL_U8_ST_INCP_P = 489, + Xtensa_EE_VPRELU_S16_P = 490, + Xtensa_EE_VPRELU_S8_P = 491, + Xtensa_EE_VRELU_S16_P = 492, + Xtensa_EE_VRELU_S8_P = 493, + Xtensa_EE_VSL_32_P = 494, + Xtensa_EE_VSMULAS_S16_QACC_LD_INCP_P = 495, + Xtensa_EE_VSMULAS_S16_QACC_P = 496, + Xtensa_EE_VSMULAS_S8_QACC_LD_INCP_P = 497, + Xtensa_EE_VSMULAS_S8_QACC_P = 498, + Xtensa_EE_VSR_32_P = 499, + Xtensa_EE_VST_128_IP_P = 500, + Xtensa_EE_VST_128_XP_P = 501, + Xtensa_EE_VST_H_64_IP_P = 502, + Xtensa_EE_VST_H_64_XP_P = 503, + Xtensa_EE_VST_L_64_IP_P = 504, + Xtensa_EE_VST_L_64_XP_P = 505, + Xtensa_EE_VSUBS_S16_LD_INCP_P = 506, + Xtensa_EE_VSUBS_S16_P = 507, + Xtensa_EE_VSUBS_S16_ST_INCP_P = 508, + Xtensa_EE_VSUBS_S32_LD_INCP_P = 509, + Xtensa_EE_VSUBS_S32_P = 510, + Xtensa_EE_VSUBS_S32_ST_INCP_P = 511, + Xtensa_EE_VSUBS_S8_LD_INCP_P = 512, + Xtensa_EE_VSUBS_S8_P = 513, + Xtensa_EE_VSUBS_S8_ST_INCP_P = 514, + Xtensa_EE_VUNZIP_16_P = 515, + Xtensa_EE_VUNZIP_32_P = 516, + Xtensa_EE_VUNZIP_8_P = 517, + Xtensa_EE_VZIP_16_P = 518, + Xtensa_EE_VZIP_32_P = 519, + Xtensa_EE_VZIP_8_P = 520, + Xtensa_EE_XORQ_P = 521, + Xtensa_EE_ZERO_ACCX_P = 522, + Xtensa_EE_ZERO_QACC_P = 523, + Xtensa_EE_ZERO_Q_P = 524, + Xtensa_EXTUI_BR2_P = 525, + Xtensa_EXTUI_BR4_P = 526, + Xtensa_EXTUI_BR_P = 527, + Xtensa_L8I_P = 528, + Xtensa_LDDEC_P = 529, + Xtensa_LDINC_P = 530, + Xtensa_LOOPBR = 531, + Xtensa_LOOPDEC = 532, + Xtensa_LOOPEND = 533, + Xtensa_LOOPINIT = 534, + Xtensa_LOOPSTART = 535, + Xtensa_MOVBA2_P = 536, + Xtensa_MOVBA2_P2 = 537, + Xtensa_MOVBA4_P = 538, + Xtensa_MOVBA4_P2 = 539, + Xtensa_MOVBA_P = 540, + Xtensa_MOVBA_P2 = 541, + Xtensa_MULA_DA_HH_LDDEC_P = 542, + Xtensa_MULA_DA_HH_LDINC_P = 543, + Xtensa_MULA_DA_HL_LDDEC_P = 544, + Xtensa_MULA_DA_HL_LDINC_P = 545, + Xtensa_MULA_DA_LH_LDDEC_P = 546, + Xtensa_MULA_DA_LH_LDINC_P = 547, + Xtensa_MULA_DA_LL_LDDEC_P = 548, + Xtensa_MULA_DA_LL_LDINC_P = 549, + Xtensa_MULA_DD_HH_LDDEC_P = 550, + Xtensa_MULA_DD_HH_LDINC_P = 551, + Xtensa_MULA_DD_HL_LDDEC_P = 552, + Xtensa_MULA_DD_HL_LDINC_P = 553, + Xtensa_MULA_DD_LH_LDDEC_P = 554, + Xtensa_MULA_DD_LH_LDINC_P = 555, + Xtensa_MULA_DD_LL_LDDEC_P = 556, + Xtensa_MULA_DD_LL_LDINC_P = 557, + Xtensa_RESTORE_BOOL = 558, + Xtensa_SELECT = 559, + Xtensa_SELECT_CC_FP_FP = 560, + Xtensa_SELECT_CC_FP_INT = 561, + Xtensa_SELECT_CC_INT_FP = 562, + Xtensa_SLLI_BR_P = 563, + Xtensa_SLL_P = 564, + Xtensa_SPILL_BOOL = 565, + Xtensa_SRA_P = 566, + Xtensa_SRL_P = 567, + Xtensa_WSR_ACCHI_P = 568, + Xtensa_WSR_ACCLO_P = 569, + Xtensa_WSR_M0_P = 570, + Xtensa_WSR_M1_P = 571, + Xtensa_WSR_M2_P = 572, + Xtensa_WSR_M3_P = 573, + Xtensa_XSR_ACCHI_P = 574, + Xtensa_XSR_ACCLO_P = 575, + Xtensa_XSR_M0_P = 576, + Xtensa_XSR_M1_P = 577, + Xtensa_XSR_M2_P = 578, + Xtensa_XSR_M3_P = 579, + Xtensa_mv_QR_P = 580, + Xtensa_ABS = 581, + Xtensa_ABS_S = 582, + Xtensa_ADD = 583, + Xtensa_ADDEXPM_S = 584, + Xtensa_ADDEXP_S = 585, + Xtensa_ADDI = 586, + Xtensa_ADDI_N = 587, + Xtensa_ADDMI = 588, + Xtensa_ADDX2 = 589, + Xtensa_ADDX4 = 590, + Xtensa_ADDX8 = 591, + Xtensa_ADD_N = 592, + Xtensa_ADD_S = 593, + Xtensa_AE_ABS16S = 594, + Xtensa_AE_ABS24S = 595, + Xtensa_AE_ABS32 = 596, + Xtensa_AE_ABS32S = 597, + Xtensa_AE_ABS64 = 598, + Xtensa_AE_ABS64S = 599, + Xtensa_AE_ADD16 = 600, + Xtensa_AE_ADD16S = 601, + Xtensa_AE_ADD24S = 602, + Xtensa_AE_ADD32 = 603, + Xtensa_AE_ADD32S = 604, + Xtensa_AE_ADD32_HL_LH = 605, + Xtensa_AE_ADD64 = 606, + Xtensa_AE_ADD64S = 607, + Xtensa_AE_ADDBRBA32 = 608, + Xtensa_AE_ADDSUB32 = 609, + Xtensa_AE_ADDSUB32S = 610, + Xtensa_AE_AND = 611, + Xtensa_AE_CVT32X2F16_10 = 612, + Xtensa_AE_CVT32X2F16_32 = 613, + Xtensa_AE_CVT48A32 = 614, + Xtensa_AE_CVT64A32 = 615, + Xtensa_AE_CVT64F32_H = 616, + Xtensa_AE_CVTA32F24S_H = 617, + Xtensa_AE_CVTA32F24S_L = 618, + Xtensa_AE_CVTQ56A32S = 619, + Xtensa_AE_CVTQ56P32S_H = 620, + Xtensa_AE_CVTQ56P32S_L = 621, + Xtensa_AE_DB = 622, + Xtensa_AE_DBI = 623, + Xtensa_AE_DBI_IC = 624, + Xtensa_AE_DBI_IP = 625, + Xtensa_AE_DB_IC = 626, + Xtensa_AE_DB_IP = 627, + Xtensa_AE_DIV64D32_H = 628, + Xtensa_AE_DIV64D32_L = 629, + Xtensa_AE_EQ16 = 630, + Xtensa_AE_EQ32 = 631, + Xtensa_AE_EQ64 = 632, + Xtensa_AE_L16M_I = 633, + Xtensa_AE_L16M_IU = 634, + Xtensa_AE_L16M_X = 635, + Xtensa_AE_L16M_XC = 636, + Xtensa_AE_L16M_XU = 637, + Xtensa_AE_L16X2M_I = 638, + Xtensa_AE_L16X2M_IU = 639, + Xtensa_AE_L16X2M_X = 640, + Xtensa_AE_L16X2M_XC = 641, + Xtensa_AE_L16X2M_XU = 642, + Xtensa_AE_L16X4_I = 643, + Xtensa_AE_L16X4_IP = 644, + Xtensa_AE_L16X4_RIC = 645, + Xtensa_AE_L16X4_RIP = 646, + Xtensa_AE_L16X4_X = 647, + Xtensa_AE_L16X4_XC = 648, + Xtensa_AE_L16X4_XP = 649, + Xtensa_AE_L16_I = 650, + Xtensa_AE_L16_IP = 651, + Xtensa_AE_L16_X = 652, + Xtensa_AE_L16_XC = 653, + Xtensa_AE_L16_XP = 654, + Xtensa_AE_L32F24_I = 655, + Xtensa_AE_L32F24_IP = 656, + Xtensa_AE_L32F24_X = 657, + Xtensa_AE_L32F24_XC = 658, + Xtensa_AE_L32F24_XP = 659, + Xtensa_AE_L32M_I = 660, + Xtensa_AE_L32M_IU = 661, + Xtensa_AE_L32M_X = 662, + Xtensa_AE_L32M_XC = 663, + Xtensa_AE_L32M_XU = 664, + Xtensa_AE_L32X2F24_I = 665, + Xtensa_AE_L32X2F24_IP = 666, + Xtensa_AE_L32X2F24_RIC = 667, + Xtensa_AE_L32X2F24_RIP = 668, + Xtensa_AE_L32X2F24_X = 669, + Xtensa_AE_L32X2F24_XC = 670, + Xtensa_AE_L32X2F24_XP = 671, + Xtensa_AE_L32X2_I = 672, + Xtensa_AE_L32X2_IP = 673, + Xtensa_AE_L32X2_RIC = 674, + Xtensa_AE_L32X2_RIP = 675, + Xtensa_AE_L32X2_X = 676, + Xtensa_AE_L32X2_XC = 677, + Xtensa_AE_L32X2_XP = 678, + Xtensa_AE_L32_I = 679, + Xtensa_AE_L32_IP = 680, + Xtensa_AE_L32_X = 681, + Xtensa_AE_L32_XC = 682, + Xtensa_AE_L32_XP = 683, + Xtensa_AE_L64_I = 684, + Xtensa_AE_L64_IP = 685, + Xtensa_AE_L64_X = 686, + Xtensa_AE_L64_XC = 687, + Xtensa_AE_L64_XP = 688, + Xtensa_AE_LA16X4NEG_PC = 689, + Xtensa_AE_LA16X4POS_PC = 690, + Xtensa_AE_LA16X4_IC = 691, + Xtensa_AE_LA16X4_IP = 692, + Xtensa_AE_LA16X4_RIC = 693, + Xtensa_AE_LA16X4_RIP = 694, + Xtensa_AE_LA24NEG_PC = 695, + Xtensa_AE_LA24POS_PC = 696, + Xtensa_AE_LA24X2NEG_PC = 697, + Xtensa_AE_LA24X2POS_PC = 698, + Xtensa_AE_LA24X2_IC = 699, + Xtensa_AE_LA24X2_IP = 700, + Xtensa_AE_LA24X2_RIC = 701, + Xtensa_AE_LA24X2_RIP = 702, + Xtensa_AE_LA24_IC = 703, + Xtensa_AE_LA24_IP = 704, + Xtensa_AE_LA24_RIC = 705, + Xtensa_AE_LA24_RIP = 706, + Xtensa_AE_LA32X2F24_IC = 707, + Xtensa_AE_LA32X2F24_IP = 708, + Xtensa_AE_LA32X2F24_RIC = 709, + Xtensa_AE_LA32X2F24_RIP = 710, + Xtensa_AE_LA32X2NEG_PC = 711, + Xtensa_AE_LA32X2POS_PC = 712, + Xtensa_AE_LA32X2_IC = 713, + Xtensa_AE_LA32X2_IP = 714, + Xtensa_AE_LA32X2_RIC = 715, + Xtensa_AE_LA32X2_RIP = 716, + Xtensa_AE_LA64_PP = 717, + Xtensa_AE_LALIGN64_I = 718, + Xtensa_AE_LB = 719, + Xtensa_AE_LBI = 720, + Xtensa_AE_LBK = 721, + Xtensa_AE_LBKI = 722, + Xtensa_AE_LBS = 723, + Xtensa_AE_LBSI = 724, + Xtensa_AE_LE16 = 725, + Xtensa_AE_LE32 = 726, + Xtensa_AE_LE64 = 727, + Xtensa_AE_LT16 = 728, + Xtensa_AE_LT32 = 729, + Xtensa_AE_LT64 = 730, + Xtensa_AE_MAX32 = 731, + Xtensa_AE_MAX64 = 732, + Xtensa_AE_MAXABS32S = 733, + Xtensa_AE_MAXABS64S = 734, + Xtensa_AE_MIN32 = 735, + Xtensa_AE_MIN64 = 736, + Xtensa_AE_MINABS32S = 737, + Xtensa_AE_MINABS64S = 738, + Xtensa_AE_MOV = 739, + Xtensa_AE_MOVAD16_0 = 740, + Xtensa_AE_MOVAD16_1 = 741, + Xtensa_AE_MOVAD16_2 = 742, + Xtensa_AE_MOVAD16_3 = 743, + Xtensa_AE_MOVAD32_H = 744, + Xtensa_AE_MOVAD32_L = 745, + Xtensa_AE_MOVALIGN = 746, + Xtensa_AE_MOVDA16 = 747, + Xtensa_AE_MOVDA16X2 = 748, + Xtensa_AE_MOVDA32 = 749, + Xtensa_AE_MOVDA32X2 = 750, + Xtensa_AE_MOVF16X4 = 751, + Xtensa_AE_MOVF32X2 = 752, + Xtensa_AE_MOVF64 = 753, + Xtensa_AE_MOVI = 754, + Xtensa_AE_MOVT16X4 = 755, + Xtensa_AE_MOVT32X2 = 756, + Xtensa_AE_MOVT64 = 757, + Xtensa_AE_MUL16X4 = 758, + Xtensa_AE_MUL32U_LL = 759, + Xtensa_AE_MUL32X16_H0 = 760, + Xtensa_AE_MUL32X16_H0_S2 = 761, + Xtensa_AE_MUL32X16_H1 = 762, + Xtensa_AE_MUL32X16_H1_S2 = 763, + Xtensa_AE_MUL32X16_H2 = 764, + Xtensa_AE_MUL32X16_H2_S2 = 765, + Xtensa_AE_MUL32X16_H3 = 766, + Xtensa_AE_MUL32X16_H3_S2 = 767, + Xtensa_AE_MUL32X16_L0 = 768, + Xtensa_AE_MUL32X16_L0_S2 = 769, + Xtensa_AE_MUL32X16_L1 = 770, + Xtensa_AE_MUL32X16_L1_S2 = 771, + Xtensa_AE_MUL32X16_L2 = 772, + Xtensa_AE_MUL32X16_L2_S2 = 773, + Xtensa_AE_MUL32X16_L3 = 774, + Xtensa_AE_MUL32X16_L3_S2 = 775, + Xtensa_AE_MUL32_HH = 776, + Xtensa_AE_MUL32_LH = 777, + Xtensa_AE_MUL32_LL = 778, + Xtensa_AE_MUL32_LL_S2 = 779, + Xtensa_AE_MULA16X4 = 780, + Xtensa_AE_MULA32U_LL = 781, + Xtensa_AE_MULA32X16_H0 = 782, + Xtensa_AE_MULA32X16_H0_S2 = 783, + Xtensa_AE_MULA32X16_H1 = 784, + Xtensa_AE_MULA32X16_H1_S2 = 785, + Xtensa_AE_MULA32X16_H2 = 786, + Xtensa_AE_MULA32X16_H2_S2 = 787, + Xtensa_AE_MULA32X16_H3 = 788, + Xtensa_AE_MULA32X16_H3_S2 = 789, + Xtensa_AE_MULA32X16_L0 = 790, + Xtensa_AE_MULA32X16_L0_S2 = 791, + Xtensa_AE_MULA32X16_L1 = 792, + Xtensa_AE_MULA32X16_L1_S2 = 793, + Xtensa_AE_MULA32X16_L2 = 794, + Xtensa_AE_MULA32X16_L2_S2 = 795, + Xtensa_AE_MULA32X16_L3 = 796, + Xtensa_AE_MULA32X16_L3_S2 = 797, + Xtensa_AE_MULA32_HH = 798, + Xtensa_AE_MULA32_LH = 799, + Xtensa_AE_MULA32_LL = 800, + Xtensa_AE_MULA32_LL_S2 = 801, + Xtensa_AE_MULAAD24_HH_LL = 802, + Xtensa_AE_MULAAD24_HH_LL_S2 = 803, + Xtensa_AE_MULAAD24_HL_LH = 804, + Xtensa_AE_MULAAD24_HL_LH_S2 = 805, + Xtensa_AE_MULAAD32X16_H0_L1 = 806, + Xtensa_AE_MULAAD32X16_H0_L1_S2 = 807, + Xtensa_AE_MULAAD32X16_H1_L0 = 808, + Xtensa_AE_MULAAD32X16_H1_L0_S2 = 809, + Xtensa_AE_MULAAD32X16_H2_L3 = 810, + Xtensa_AE_MULAAD32X16_H2_L3_S2 = 811, + Xtensa_AE_MULAAD32X16_H3_L2 = 812, + Xtensa_AE_MULAAD32X16_H3_L2_S2 = 813, + Xtensa_AE_MULAAFD16SS_11_00 = 814, + Xtensa_AE_MULAAFD16SS_11_00_S2 = 815, + Xtensa_AE_MULAAFD16SS_13_02 = 816, + Xtensa_AE_MULAAFD16SS_13_02_S2 = 817, + Xtensa_AE_MULAAFD16SS_33_22 = 818, + Xtensa_AE_MULAAFD16SS_33_22_S2 = 819, + Xtensa_AE_MULAAFD24_HH_LL = 820, + Xtensa_AE_MULAAFD24_HH_LL_S2 = 821, + Xtensa_AE_MULAAFD24_HL_LH = 822, + Xtensa_AE_MULAAFD24_HL_LH_S2 = 823, + Xtensa_AE_MULAAFD32X16_H0_L1 = 824, + Xtensa_AE_MULAAFD32X16_H0_L1_S2 = 825, + Xtensa_AE_MULAAFD32X16_H1_L0 = 826, + Xtensa_AE_MULAAFD32X16_H1_L0_S2 = 827, + Xtensa_AE_MULAAFD32X16_H2_L3 = 828, + Xtensa_AE_MULAAFD32X16_H2_L3_S2 = 829, + Xtensa_AE_MULAAFD32X16_H3_L2 = 830, + Xtensa_AE_MULAAFD32X16_H3_L2_S2 = 831, + Xtensa_AE_MULAC24 = 832, + Xtensa_AE_MULAC32X16_H = 833, + Xtensa_AE_MULAC32X16_L = 834, + Xtensa_AE_MULAF16SS_00 = 835, + Xtensa_AE_MULAF16SS_00_S2 = 836, + Xtensa_AE_MULAF16SS_10 = 837, + Xtensa_AE_MULAF16SS_11 = 838, + Xtensa_AE_MULAF16SS_20 = 839, + Xtensa_AE_MULAF16SS_21 = 840, + Xtensa_AE_MULAF16SS_22 = 841, + Xtensa_AE_MULAF16SS_30 = 842, + Xtensa_AE_MULAF16SS_31 = 843, + Xtensa_AE_MULAF16SS_32 = 844, + Xtensa_AE_MULAF16SS_33 = 845, + Xtensa_AE_MULAF16X4SS = 846, + Xtensa_AE_MULAF32R_HH = 847, + Xtensa_AE_MULAF32R_LH = 848, + Xtensa_AE_MULAF32R_LL = 849, + Xtensa_AE_MULAF32R_LL_S2 = 850, + Xtensa_AE_MULAF32S_HH = 851, + Xtensa_AE_MULAF32S_LH = 852, + Xtensa_AE_MULAF32S_LL = 853, + Xtensa_AE_MULAF32S_LL_S2 = 854, + Xtensa_AE_MULAF32X16_H0 = 855, + Xtensa_AE_MULAF32X16_H0_S2 = 856, + Xtensa_AE_MULAF32X16_H1 = 857, + Xtensa_AE_MULAF32X16_H1_S2 = 858, + Xtensa_AE_MULAF32X16_H2 = 859, + Xtensa_AE_MULAF32X16_H2_S2 = 860, + Xtensa_AE_MULAF32X16_H3 = 861, + Xtensa_AE_MULAF32X16_H3_S2 = 862, + Xtensa_AE_MULAF32X16_L0 = 863, + Xtensa_AE_MULAF32X16_L0_S2 = 864, + Xtensa_AE_MULAF32X16_L1 = 865, + Xtensa_AE_MULAF32X16_L1_S2 = 866, + Xtensa_AE_MULAF32X16_L2 = 867, + Xtensa_AE_MULAF32X16_L2_S2 = 868, + Xtensa_AE_MULAF32X16_L3 = 869, + Xtensa_AE_MULAF32X16_L3_S2 = 870, + Xtensa_AE_MULAF48Q32SP16S_L = 871, + Xtensa_AE_MULAF48Q32SP16S_L_S2 = 872, + Xtensa_AE_MULAF48Q32SP16U_L = 873, + Xtensa_AE_MULAF48Q32SP16U_L_S2 = 874, + Xtensa_AE_MULAFC24RA = 875, + Xtensa_AE_MULAFC32X16RAS_H = 876, + Xtensa_AE_MULAFC32X16RAS_L = 877, + Xtensa_AE_MULAFD24X2_FIR_H = 878, + Xtensa_AE_MULAFD24X2_FIR_L = 879, + Xtensa_AE_MULAFD32X16X2_FIR_HH = 880, + Xtensa_AE_MULAFD32X16X2_FIR_HL = 881, + Xtensa_AE_MULAFD32X16X2_FIR_LH = 882, + Xtensa_AE_MULAFD32X16X2_FIR_LL = 883, + Xtensa_AE_MULAFP24X2R = 884, + Xtensa_AE_MULAFP24X2RA = 885, + Xtensa_AE_MULAFP24X2RA_S2 = 886, + Xtensa_AE_MULAFP24X2R_S2 = 887, + Xtensa_AE_MULAFP32X16X2RAS_H = 888, + Xtensa_AE_MULAFP32X16X2RAS_H_S2 = 889, + Xtensa_AE_MULAFP32X16X2RAS_L = 890, + Xtensa_AE_MULAFP32X16X2RAS_L_S2 = 891, + Xtensa_AE_MULAFP32X16X2RS_H = 892, + Xtensa_AE_MULAFP32X16X2RS_H_S2 = 893, + Xtensa_AE_MULAFP32X16X2RS_L = 894, + Xtensa_AE_MULAFP32X16X2RS_L_S2 = 895, + Xtensa_AE_MULAFP32X2RAS = 896, + Xtensa_AE_MULAFP32X2RS = 897, + Xtensa_AE_MULAFQ32SP24S_H_S2 = 898, + Xtensa_AE_MULAFQ32SP24S_L_S2 = 899, + Xtensa_AE_MULAP24X2 = 900, + Xtensa_AE_MULAP24X2_S2 = 901, + Xtensa_AE_MULAP32X16X2_H = 902, + Xtensa_AE_MULAP32X16X2_L = 903, + Xtensa_AE_MULAP32X2 = 904, + Xtensa_AE_MULAQ32SP16S_L_S2 = 905, + Xtensa_AE_MULAQ32SP16U_L_S2 = 906, + Xtensa_AE_MULARFQ32SP24S_H_S2 = 907, + Xtensa_AE_MULARFQ32SP24S_L_S2 = 908, + Xtensa_AE_MULAS32F48P16S_HH = 909, + Xtensa_AE_MULAS32F48P16S_HH_S2 = 910, + Xtensa_AE_MULAS32F48P16S_LH = 911, + Xtensa_AE_MULAS32F48P16S_LH_S2 = 912, + Xtensa_AE_MULAS32F48P16S_LL = 913, + Xtensa_AE_MULAS32F48P16S_LL_S2 = 914, + Xtensa_AE_MULASD24_HH_LL = 915, + Xtensa_AE_MULASD24_HH_LL_S2 = 916, + Xtensa_AE_MULASD24_HL_LH = 917, + Xtensa_AE_MULASD24_HL_LH_S2 = 918, + Xtensa_AE_MULASD32X16_H1_L0 = 919, + Xtensa_AE_MULASD32X16_H1_L0_S2 = 920, + Xtensa_AE_MULASD32X16_H3_L2 = 921, + Xtensa_AE_MULASD32X16_H3_L2_S2 = 922, + Xtensa_AE_MULASFD24_HH_LL = 923, + Xtensa_AE_MULASFD24_HH_LL_S2 = 924, + Xtensa_AE_MULASFD24_HL_LH = 925, + Xtensa_AE_MULASFD24_HL_LH_S2 = 926, + Xtensa_AE_MULASFD32X16_H1_L0 = 927, + Xtensa_AE_MULASFD32X16_H1_L0_S2 = 928, + Xtensa_AE_MULASFD32X16_H3_L2 = 929, + Xtensa_AE_MULASFD32X16_H3_L2_S2 = 930, + Xtensa_AE_MULC24 = 931, + Xtensa_AE_MULC32X16_H = 932, + Xtensa_AE_MULC32X16_L = 933, + Xtensa_AE_MULF16SS_00 = 934, + Xtensa_AE_MULF16SS_00_S2 = 935, + Xtensa_AE_MULF16SS_10 = 936, + Xtensa_AE_MULF16SS_11 = 937, + Xtensa_AE_MULF16SS_20 = 938, + Xtensa_AE_MULF16SS_21 = 939, + Xtensa_AE_MULF16SS_22 = 940, + Xtensa_AE_MULF16SS_30 = 941, + Xtensa_AE_MULF16SS_31 = 942, + Xtensa_AE_MULF16SS_32 = 943, + Xtensa_AE_MULF16SS_33 = 944, + Xtensa_AE_MULF16X4SS = 945, + Xtensa_AE_MULF32R_HH = 946, + Xtensa_AE_MULF32R_LH = 947, + Xtensa_AE_MULF32R_LL = 948, + Xtensa_AE_MULF32R_LL_S2 = 949, + Xtensa_AE_MULF32S_HH = 950, + Xtensa_AE_MULF32S_LH = 951, + Xtensa_AE_MULF32S_LL = 952, + Xtensa_AE_MULF32S_LL_S2 = 953, + Xtensa_AE_MULF32X16_H0 = 954, + Xtensa_AE_MULF32X16_H0_S2 = 955, + Xtensa_AE_MULF32X16_H1 = 956, + Xtensa_AE_MULF32X16_H1_S2 = 957, + Xtensa_AE_MULF32X16_H2 = 958, + Xtensa_AE_MULF32X16_H2_S2 = 959, + Xtensa_AE_MULF32X16_H3 = 960, + Xtensa_AE_MULF32X16_H3_S2 = 961, + Xtensa_AE_MULF32X16_L0 = 962, + Xtensa_AE_MULF32X16_L0_S2 = 963, + Xtensa_AE_MULF32X16_L1 = 964, + Xtensa_AE_MULF32X16_L1_S2 = 965, + Xtensa_AE_MULF32X16_L2 = 966, + Xtensa_AE_MULF32X16_L2_S2 = 967, + Xtensa_AE_MULF32X16_L3 = 968, + Xtensa_AE_MULF32X16_L3_S2 = 969, + Xtensa_AE_MULF48Q32SP16S_L = 970, + Xtensa_AE_MULF48Q32SP16S_L_S2 = 971, + Xtensa_AE_MULF48Q32SP16U_L = 972, + Xtensa_AE_MULF48Q32SP16U_L_S2 = 973, + Xtensa_AE_MULFC24RA = 974, + Xtensa_AE_MULFC32X16RAS_H = 975, + Xtensa_AE_MULFC32X16RAS_L = 976, + Xtensa_AE_MULFD24X2_FIR_H = 977, + Xtensa_AE_MULFD24X2_FIR_L = 978, + Xtensa_AE_MULFD32X16X2_FIR_HH = 979, + Xtensa_AE_MULFD32X16X2_FIR_HL = 980, + Xtensa_AE_MULFD32X16X2_FIR_LH = 981, + Xtensa_AE_MULFD32X16X2_FIR_LL = 982, + Xtensa_AE_MULFP16X4RAS = 983, + Xtensa_AE_MULFP16X4S = 984, + Xtensa_AE_MULFP24X2R = 985, + Xtensa_AE_MULFP24X2RA = 986, + Xtensa_AE_MULFP24X2RA_S2 = 987, + Xtensa_AE_MULFP24X2R_S2 = 988, + Xtensa_AE_MULFP32X16X2RAS_H = 989, + Xtensa_AE_MULFP32X16X2RAS_H_S2 = 990, + Xtensa_AE_MULFP32X16X2RAS_L = 991, + Xtensa_AE_MULFP32X16X2RAS_L_S2 = 992, + Xtensa_AE_MULFP32X16X2RS_H = 993, + Xtensa_AE_MULFP32X16X2RS_H_S2 = 994, + Xtensa_AE_MULFP32X16X2RS_L = 995, + Xtensa_AE_MULFP32X16X2RS_L_S2 = 996, + Xtensa_AE_MULFP32X2RAS = 997, + Xtensa_AE_MULFP32X2RS = 998, + Xtensa_AE_MULFQ32SP24S_H_S2 = 999, + Xtensa_AE_MULFQ32SP24S_L_S2 = 1000, + Xtensa_AE_MULP24X2 = 1001, + Xtensa_AE_MULP24X2_S2 = 1002, + Xtensa_AE_MULP32X16X2_H = 1003, + Xtensa_AE_MULP32X16X2_L = 1004, + Xtensa_AE_MULP32X2 = 1005, + Xtensa_AE_MULQ32SP16S_L_S2 = 1006, + Xtensa_AE_MULQ32SP16U_L_S2 = 1007, + Xtensa_AE_MULRFQ32SP24S_H_S2 = 1008, + Xtensa_AE_MULRFQ32SP24S_L_S2 = 1009, + Xtensa_AE_MULS16X4 = 1010, + Xtensa_AE_MULS32F48P16S_HH = 1011, + Xtensa_AE_MULS32F48P16S_HH_S2 = 1012, + Xtensa_AE_MULS32F48P16S_LH = 1013, + Xtensa_AE_MULS32F48P16S_LH_S2 = 1014, + Xtensa_AE_MULS32F48P16S_LL = 1015, + Xtensa_AE_MULS32F48P16S_LL_S2 = 1016, + Xtensa_AE_MULS32U_LL = 1017, + Xtensa_AE_MULS32X16_H0 = 1018, + Xtensa_AE_MULS32X16_H0_S2 = 1019, + Xtensa_AE_MULS32X16_H1 = 1020, + Xtensa_AE_MULS32X16_H1_S2 = 1021, + Xtensa_AE_MULS32X16_H2 = 1022, + Xtensa_AE_MULS32X16_H2_S2 = 1023, + Xtensa_AE_MULS32X16_H3 = 1024, + Xtensa_AE_MULS32X16_H3_S2 = 1025, + Xtensa_AE_MULS32X16_L0 = 1026, + Xtensa_AE_MULS32X16_L0_S2 = 1027, + Xtensa_AE_MULS32X16_L1 = 1028, + Xtensa_AE_MULS32X16_L1_S2 = 1029, + Xtensa_AE_MULS32X16_L2 = 1030, + Xtensa_AE_MULS32X16_L2_S2 = 1031, + Xtensa_AE_MULS32X16_L3 = 1032, + Xtensa_AE_MULS32X16_L3_S2 = 1033, + Xtensa_AE_MULS32_HH = 1034, + Xtensa_AE_MULS32_LH = 1035, + Xtensa_AE_MULS32_LL = 1036, + Xtensa_AE_MULSAD24_HH_LL = 1037, + Xtensa_AE_MULSAD24_HH_LL_S2 = 1038, + Xtensa_AE_MULSAD32X16_H1_L0 = 1039, + Xtensa_AE_MULSAD32X16_H1_L0_S2 = 1040, + Xtensa_AE_MULSAD32X16_H3_L2 = 1041, + Xtensa_AE_MULSAD32X16_H3_L2_S2 = 1042, + Xtensa_AE_MULSAFD24_HH_LL = 1043, + Xtensa_AE_MULSAFD24_HH_LL_S2 = 1044, + Xtensa_AE_MULSAFD32X16_H1_L0 = 1045, + Xtensa_AE_MULSAFD32X16_H1_L0_S2 = 1046, + Xtensa_AE_MULSAFD32X16_H3_L2 = 1047, + Xtensa_AE_MULSAFD32X16_H3_L2_S2 = 1048, + Xtensa_AE_MULSF16SS_00 = 1049, + Xtensa_AE_MULSF16SS_00_S2 = 1050, + Xtensa_AE_MULSF16SS_10 = 1051, + Xtensa_AE_MULSF16SS_11 = 1052, + Xtensa_AE_MULSF16SS_20 = 1053, + Xtensa_AE_MULSF16SS_21 = 1054, + Xtensa_AE_MULSF16SS_22 = 1055, + Xtensa_AE_MULSF16SS_30 = 1056, + Xtensa_AE_MULSF16SS_31 = 1057, + Xtensa_AE_MULSF16SS_32 = 1058, + Xtensa_AE_MULSF16SS_33 = 1059, + Xtensa_AE_MULSF16X4SS = 1060, + Xtensa_AE_MULSF32R_HH = 1061, + Xtensa_AE_MULSF32R_LH = 1062, + Xtensa_AE_MULSF32R_LL = 1063, + Xtensa_AE_MULSF32R_LL_S2 = 1064, + Xtensa_AE_MULSF32S_HH = 1065, + Xtensa_AE_MULSF32S_LH = 1066, + Xtensa_AE_MULSF32S_LL = 1067, + Xtensa_AE_MULSF32X16_H0 = 1068, + Xtensa_AE_MULSF32X16_H0_S2 = 1069, + Xtensa_AE_MULSF32X16_H1 = 1070, + Xtensa_AE_MULSF32X16_H1_S2 = 1071, + Xtensa_AE_MULSF32X16_H2 = 1072, + Xtensa_AE_MULSF32X16_H2_S2 = 1073, + Xtensa_AE_MULSF32X16_H3 = 1074, + Xtensa_AE_MULSF32X16_H3_S2 = 1075, + Xtensa_AE_MULSF32X16_L0 = 1076, + Xtensa_AE_MULSF32X16_L0_S2 = 1077, + Xtensa_AE_MULSF32X16_L1 = 1078, + Xtensa_AE_MULSF32X16_L1_S2 = 1079, + Xtensa_AE_MULSF32X16_L2 = 1080, + Xtensa_AE_MULSF32X16_L2_S2 = 1081, + Xtensa_AE_MULSF32X16_L3 = 1082, + Xtensa_AE_MULSF32X16_L3_S2 = 1083, + Xtensa_AE_MULSF48Q32SP16S_L = 1084, + Xtensa_AE_MULSF48Q32SP16S_L_S2 = 1085, + Xtensa_AE_MULSF48Q32SP16U_L = 1086, + Xtensa_AE_MULSF48Q32SP16U_L_S2 = 1087, + Xtensa_AE_MULSFP24X2R = 1088, + Xtensa_AE_MULSFP24X2RA = 1089, + Xtensa_AE_MULSFP24X2RA_S2 = 1090, + Xtensa_AE_MULSFP24X2R_S2 = 1091, + Xtensa_AE_MULSFP32X16X2RAS_H = 1092, + Xtensa_AE_MULSFP32X16X2RAS_H_S2 = 1093, + Xtensa_AE_MULSFP32X16X2RAS_L = 1094, + Xtensa_AE_MULSFP32X16X2RAS_L_S2 = 1095, + Xtensa_AE_MULSFP32X16X2RS_H = 1096, + Xtensa_AE_MULSFP32X16X2RS_H_S2 = 1097, + Xtensa_AE_MULSFP32X16X2RS_L = 1098, + Xtensa_AE_MULSFP32X16X2RS_L_S2 = 1099, + Xtensa_AE_MULSFP32X2RAS = 1100, + Xtensa_AE_MULSFP32X2RS = 1101, + Xtensa_AE_MULSFQ32SP24S_H_S2 = 1102, + Xtensa_AE_MULSFQ32SP24S_L_S2 = 1103, + Xtensa_AE_MULSP24X2 = 1104, + Xtensa_AE_MULSP24X2_S2 = 1105, + Xtensa_AE_MULSP32X16X2_H = 1106, + Xtensa_AE_MULSP32X16X2_L = 1107, + Xtensa_AE_MULSP32X2 = 1108, + Xtensa_AE_MULSQ32SP16S_L_S2 = 1109, + Xtensa_AE_MULSQ32SP16U_L_S2 = 1110, + Xtensa_AE_MULSRFQ32SP24S_H_S2 = 1111, + Xtensa_AE_MULSRFQ32SP24S_L_S2 = 1112, + Xtensa_AE_MULSS32F48P16S_HH = 1113, + Xtensa_AE_MULSS32F48P16S_HH_S2 = 1114, + Xtensa_AE_MULSS32F48P16S_LH = 1115, + Xtensa_AE_MULSS32F48P16S_LH_S2 = 1116, + Xtensa_AE_MULSS32F48P16S_LL = 1117, + Xtensa_AE_MULSS32F48P16S_LL_S2 = 1118, + Xtensa_AE_MULSSD24_HH_LL = 1119, + Xtensa_AE_MULSSD24_HH_LL_S2 = 1120, + Xtensa_AE_MULSSD24_HL_LH = 1121, + Xtensa_AE_MULSSD24_HL_LH_S2 = 1122, + Xtensa_AE_MULSSD32X16_H1_L0 = 1123, + Xtensa_AE_MULSSD32X16_H1_L0_S2 = 1124, + Xtensa_AE_MULSSD32X16_H3_L2 = 1125, + Xtensa_AE_MULSSD32X16_H3_L2_S2 = 1126, + Xtensa_AE_MULSSFD16SS_11_00 = 1127, + Xtensa_AE_MULSSFD16SS_11_00_S2 = 1128, + Xtensa_AE_MULSSFD16SS_13_02 = 1129, + Xtensa_AE_MULSSFD16SS_13_02_S2 = 1130, + Xtensa_AE_MULSSFD16SS_33_22 = 1131, + Xtensa_AE_MULSSFD16SS_33_22_S2 = 1132, + Xtensa_AE_MULSSFD24_HH_LL = 1133, + Xtensa_AE_MULSSFD24_HH_LL_S2 = 1134, + Xtensa_AE_MULSSFD24_HL_LH = 1135, + Xtensa_AE_MULSSFD24_HL_LH_S2 = 1136, + Xtensa_AE_MULSSFD32X16_H1_L0 = 1137, + Xtensa_AE_MULSSFD32X16_H1_L0_S2 = 1138, + Xtensa_AE_MULSSFD32X16_H3_L2 = 1139, + Xtensa_AE_MULSSFD32X16_H3_L2_S2 = 1140, + Xtensa_AE_MULZAAD24_HH_LL = 1141, + Xtensa_AE_MULZAAD24_HH_LL_S2 = 1142, + Xtensa_AE_MULZAAD24_HL_LH = 1143, + Xtensa_AE_MULZAAD24_HL_LH_S2 = 1144, + Xtensa_AE_MULZAAD32X16_H0_L1 = 1145, + Xtensa_AE_MULZAAD32X16_H0_L1_S2 = 1146, + Xtensa_AE_MULZAAD32X16_H1_L0 = 1147, + Xtensa_AE_MULZAAD32X16_H1_L0_S2 = 1148, + Xtensa_AE_MULZAAD32X16_H2_L3 = 1149, + Xtensa_AE_MULZAAD32X16_H2_L3_S2 = 1150, + Xtensa_AE_MULZAAD32X16_H3_L2 = 1151, + Xtensa_AE_MULZAAD32X16_H3_L2_S2 = 1152, + Xtensa_AE_MULZAAFD16SS_11_00 = 1153, + Xtensa_AE_MULZAAFD16SS_11_00_S2 = 1154, + Xtensa_AE_MULZAAFD16SS_13_02 = 1155, + Xtensa_AE_MULZAAFD16SS_13_02_S2 = 1156, + Xtensa_AE_MULZAAFD16SS_33_22 = 1157, + Xtensa_AE_MULZAAFD16SS_33_22_S2 = 1158, + Xtensa_AE_MULZAAFD24_HH_LL = 1159, + Xtensa_AE_MULZAAFD24_HH_LL_S2 = 1160, + Xtensa_AE_MULZAAFD24_HL_LH = 1161, + Xtensa_AE_MULZAAFD24_HL_LH_S2 = 1162, + Xtensa_AE_MULZAAFD32X16_H0_L1 = 1163, + Xtensa_AE_MULZAAFD32X16_H0_L1_S2 = 1164, + Xtensa_AE_MULZAAFD32X16_H1_L0 = 1165, + Xtensa_AE_MULZAAFD32X16_H1_L0_S2 = 1166, + Xtensa_AE_MULZAAFD32X16_H2_L3 = 1167, + Xtensa_AE_MULZAAFD32X16_H2_L3_S2 = 1168, + Xtensa_AE_MULZAAFD32X16_H3_L2 = 1169, + Xtensa_AE_MULZAAFD32X16_H3_L2_S2 = 1170, + Xtensa_AE_MULZASD24_HH_LL = 1171, + Xtensa_AE_MULZASD24_HH_LL_S2 = 1172, + Xtensa_AE_MULZASD24_HL_LH = 1173, + Xtensa_AE_MULZASD24_HL_LH_S2 = 1174, + Xtensa_AE_MULZASD32X16_H1_L0 = 1175, + Xtensa_AE_MULZASD32X16_H1_L0_S2 = 1176, + Xtensa_AE_MULZASD32X16_H3_L2 = 1177, + Xtensa_AE_MULZASD32X16_H3_L2_S2 = 1178, + Xtensa_AE_MULZASFD24_HH_LL = 1179, + Xtensa_AE_MULZASFD24_HH_LL_S2 = 1180, + Xtensa_AE_MULZASFD24_HL_LH = 1181, + Xtensa_AE_MULZASFD24_HL_LH_S2 = 1182, + Xtensa_AE_MULZASFD32X16_H1_L0 = 1183, + Xtensa_AE_MULZASFD32X16_H1_L0_S2 = 1184, + Xtensa_AE_MULZASFD32X16_H3_L2 = 1185, + Xtensa_AE_MULZASFD32X16_H3_L2_S2 = 1186, + Xtensa_AE_MULZSAD24_HH_LL = 1187, + Xtensa_AE_MULZSAD24_HH_LL_S2 = 1188, + Xtensa_AE_MULZSAD32X16_H1_L0 = 1189, + Xtensa_AE_MULZSAD32X16_H1_L0_S2 = 1190, + Xtensa_AE_MULZSAD32X16_H3_L2 = 1191, + Xtensa_AE_MULZSAD32X16_H3_L2_S2 = 1192, + Xtensa_AE_MULZSAFD24_HH_LL = 1193, + Xtensa_AE_MULZSAFD24_HH_LL_S2 = 1194, + Xtensa_AE_MULZSAFD32X16_H1_L0 = 1195, + Xtensa_AE_MULZSAFD32X16_H1_L0_S2 = 1196, + Xtensa_AE_MULZSAFD32X16_H3_L2 = 1197, + Xtensa_AE_MULZSAFD32X16_H3_L2_S2 = 1198, + Xtensa_AE_MULZSSD24_HH_LL = 1199, + Xtensa_AE_MULZSSD24_HH_LL_S2 = 1200, + Xtensa_AE_MULZSSD24_HL_LH = 1201, + Xtensa_AE_MULZSSD24_HL_LH_S2 = 1202, + Xtensa_AE_MULZSSD32X16_H1_L0 = 1203, + Xtensa_AE_MULZSSD32X16_H1_L0_S2 = 1204, + Xtensa_AE_MULZSSD32X16_H3_L2 = 1205, + Xtensa_AE_MULZSSD32X16_H3_L2_S2 = 1206, + Xtensa_AE_MULZSSFD16SS_11_00 = 1207, + Xtensa_AE_MULZSSFD16SS_11_00_S2 = 1208, + Xtensa_AE_MULZSSFD16SS_13_02 = 1209, + Xtensa_AE_MULZSSFD16SS_13_02_S2 = 1210, + Xtensa_AE_MULZSSFD16SS_33_22 = 1211, + Xtensa_AE_MULZSSFD16SS_33_22_S2 = 1212, + Xtensa_AE_MULZSSFD24_HH_LL = 1213, + Xtensa_AE_MULZSSFD24_HH_LL_S2 = 1214, + Xtensa_AE_MULZSSFD24_HL_LH = 1215, + Xtensa_AE_MULZSSFD24_HL_LH_S2 = 1216, + Xtensa_AE_MULZSSFD32X16_H1_L0 = 1217, + Xtensa_AE_MULZSSFD32X16_H1_L0_S2 = 1218, + Xtensa_AE_MULZSSFD32X16_H3_L2 = 1219, + Xtensa_AE_MULZSSFD32X16_H3_L2_S2 = 1220, + Xtensa_AE_NAND = 1221, + Xtensa_AE_NEG16S = 1222, + Xtensa_AE_NEG24S = 1223, + Xtensa_AE_NEG32 = 1224, + Xtensa_AE_NEG32S = 1225, + Xtensa_AE_NEG64 = 1226, + Xtensa_AE_NEG64S = 1227, + Xtensa_AE_NSA64 = 1228, + Xtensa_AE_NSAZ16_0 = 1229, + Xtensa_AE_NSAZ32_L = 1230, + Xtensa_AE_OR = 1231, + Xtensa_AE_PKSR24 = 1232, + Xtensa_AE_PKSR32 = 1233, + Xtensa_AE_ROUND16X4F32SASYM = 1234, + Xtensa_AE_ROUND16X4F32SSYM = 1235, + Xtensa_AE_ROUND24X2F48SASYM = 1236, + Xtensa_AE_ROUND24X2F48SSYM = 1237, + Xtensa_AE_ROUND32X2F48SASYM = 1238, + Xtensa_AE_ROUND32X2F48SSYM = 1239, + Xtensa_AE_ROUND32X2F64SASYM = 1240, + Xtensa_AE_ROUND32X2F64SSYM = 1241, + Xtensa_AE_ROUNDSP16F24ASYM = 1242, + Xtensa_AE_ROUNDSP16F24SYM = 1243, + Xtensa_AE_ROUNDSP16Q48X2ASYM = 1244, + Xtensa_AE_ROUNDSP16Q48X2SYM = 1245, + Xtensa_AE_ROUNDSQ32F48ASYM = 1246, + Xtensa_AE_ROUNDSQ32F48SYM = 1247, + Xtensa_AE_S16M_L_I = 1248, + Xtensa_AE_S16M_L_IU = 1249, + Xtensa_AE_S16M_L_X = 1250, + Xtensa_AE_S16M_L_XC = 1251, + Xtensa_AE_S16M_L_XU = 1252, + Xtensa_AE_S16X2M_I = 1253, + Xtensa_AE_S16X2M_IU = 1254, + Xtensa_AE_S16X2M_X = 1255, + Xtensa_AE_S16X2M_XC = 1256, + Xtensa_AE_S16X2M_XU = 1257, + Xtensa_AE_S16X4_I = 1258, + Xtensa_AE_S16X4_IP = 1259, + Xtensa_AE_S16X4_RIC = 1260, + Xtensa_AE_S16X4_RIP = 1261, + Xtensa_AE_S16X4_X = 1262, + Xtensa_AE_S16X4_XC = 1263, + Xtensa_AE_S16X4_XP = 1264, + Xtensa_AE_S16_0_I = 1265, + Xtensa_AE_S16_0_IP = 1266, + Xtensa_AE_S16_0_X = 1267, + Xtensa_AE_S16_0_XC = 1268, + Xtensa_AE_S16_0_XP = 1269, + Xtensa_AE_S24RA64S_I = 1270, + Xtensa_AE_S24RA64S_IP = 1271, + Xtensa_AE_S24RA64S_X = 1272, + Xtensa_AE_S24RA64S_XC = 1273, + Xtensa_AE_S24RA64S_XP = 1274, + Xtensa_AE_S24X2RA64S_IP = 1275, + Xtensa_AE_S32F24_L_I = 1276, + Xtensa_AE_S32F24_L_IP = 1277, + Xtensa_AE_S32F24_L_X = 1278, + Xtensa_AE_S32F24_L_XC = 1279, + Xtensa_AE_S32F24_L_XP = 1280, + Xtensa_AE_S32M_I = 1281, + Xtensa_AE_S32M_IU = 1282, + Xtensa_AE_S32M_X = 1283, + Xtensa_AE_S32M_XC = 1284, + Xtensa_AE_S32M_XU = 1285, + Xtensa_AE_S32RA64S_I = 1286, + Xtensa_AE_S32RA64S_IP = 1287, + Xtensa_AE_S32RA64S_X = 1288, + Xtensa_AE_S32RA64S_XC = 1289, + Xtensa_AE_S32RA64S_XP = 1290, + Xtensa_AE_S32X2F24_I = 1291, + Xtensa_AE_S32X2F24_IP = 1292, + Xtensa_AE_S32X2F24_RIC = 1293, + Xtensa_AE_S32X2F24_RIP = 1294, + Xtensa_AE_S32X2F24_X = 1295, + Xtensa_AE_S32X2F24_XC = 1296, + Xtensa_AE_S32X2F24_XP = 1297, + Xtensa_AE_S32X2RA64S_IP = 1298, + Xtensa_AE_S32X2_I = 1299, + Xtensa_AE_S32X2_IP = 1300, + Xtensa_AE_S32X2_RIC = 1301, + Xtensa_AE_S32X2_RIP = 1302, + Xtensa_AE_S32X2_X = 1303, + Xtensa_AE_S32X2_XC = 1304, + Xtensa_AE_S32X2_XP = 1305, + Xtensa_AE_S32_L_I = 1306, + Xtensa_AE_S32_L_IP = 1307, + Xtensa_AE_S32_L_X = 1308, + Xtensa_AE_S32_L_XC = 1309, + Xtensa_AE_S32_L_XP = 1310, + Xtensa_AE_S64_I = 1311, + Xtensa_AE_S64_IP = 1312, + Xtensa_AE_S64_X = 1313, + Xtensa_AE_S64_XC = 1314, + Xtensa_AE_S64_XP = 1315, + Xtensa_AE_SA16X4_IC = 1316, + Xtensa_AE_SA16X4_IP = 1317, + Xtensa_AE_SA16X4_RIC = 1318, + Xtensa_AE_SA16X4_RIP = 1319, + Xtensa_AE_SA24X2_IC = 1320, + Xtensa_AE_SA24X2_IP = 1321, + Xtensa_AE_SA24X2_RIC = 1322, + Xtensa_AE_SA24X2_RIP = 1323, + Xtensa_AE_SA24_L_IC = 1324, + Xtensa_AE_SA24_L_IP = 1325, + Xtensa_AE_SA24_L_RIC = 1326, + Xtensa_AE_SA24_L_RIP = 1327, + Xtensa_AE_SA32X2F24_IC = 1328, + Xtensa_AE_SA32X2F24_IP = 1329, + Xtensa_AE_SA32X2F24_RIC = 1330, + Xtensa_AE_SA32X2F24_RIP = 1331, + Xtensa_AE_SA32X2_IC = 1332, + Xtensa_AE_SA32X2_IP = 1333, + Xtensa_AE_SA32X2_RIC = 1334, + Xtensa_AE_SA32X2_RIP = 1335, + Xtensa_AE_SA64NEG_FP = 1336, + Xtensa_AE_SA64POS_FP = 1337, + Xtensa_AE_SALIGN64_I = 1338, + Xtensa_AE_SAT16X4 = 1339, + Xtensa_AE_SAT24S = 1340, + Xtensa_AE_SAT48S = 1341, + Xtensa_AE_SATQ56S = 1342, + Xtensa_AE_SB = 1343, + Xtensa_AE_SBF = 1344, + Xtensa_AE_SBF_IC = 1345, + Xtensa_AE_SBF_IP = 1346, + Xtensa_AE_SBI = 1347, + Xtensa_AE_SBI_IC = 1348, + Xtensa_AE_SBI_IP = 1349, + Xtensa_AE_SB_IC = 1350, + Xtensa_AE_SB_IP = 1351, + Xtensa_AE_SEL16I = 1352, + Xtensa_AE_SEL16I_N = 1353, + Xtensa_AE_SEXT32 = 1354, + Xtensa_AE_SEXT32X2D16_10 = 1355, + Xtensa_AE_SEXT32X2D16_32 = 1356, + Xtensa_AE_SHA32 = 1357, + Xtensa_AE_SHORTSWAP = 1358, + Xtensa_AE_SLAA16S = 1359, + Xtensa_AE_SLAA32 = 1360, + Xtensa_AE_SLAA32S = 1361, + Xtensa_AE_SLAA64 = 1362, + Xtensa_AE_SLAA64S = 1363, + Xtensa_AE_SLAAQ56 = 1364, + Xtensa_AE_SLAI16S = 1365, + Xtensa_AE_SLAI24 = 1366, + Xtensa_AE_SLAI24S = 1367, + Xtensa_AE_SLAI32 = 1368, + Xtensa_AE_SLAI32S = 1369, + Xtensa_AE_SLAI64 = 1370, + Xtensa_AE_SLAI64S = 1371, + Xtensa_AE_SLAISQ56S = 1372, + Xtensa_AE_SLAS24 = 1373, + Xtensa_AE_SLAS24S = 1374, + Xtensa_AE_SLAS32 = 1375, + Xtensa_AE_SLAS32S = 1376, + Xtensa_AE_SLAS64 = 1377, + Xtensa_AE_SLAS64S = 1378, + Xtensa_AE_SLASQ56 = 1379, + Xtensa_AE_SLASSQ56S = 1380, + Xtensa_AE_SRA64_32 = 1381, + Xtensa_AE_SRAA16RS = 1382, + Xtensa_AE_SRAA16S = 1383, + Xtensa_AE_SRAA32 = 1384, + Xtensa_AE_SRAA32RS = 1385, + Xtensa_AE_SRAA32S = 1386, + Xtensa_AE_SRAA64 = 1387, + Xtensa_AE_SRAI16 = 1388, + Xtensa_AE_SRAI16R = 1389, + Xtensa_AE_SRAI24 = 1390, + Xtensa_AE_SRAI32 = 1391, + Xtensa_AE_SRAI32R = 1392, + Xtensa_AE_SRAI64 = 1393, + Xtensa_AE_SRAS24 = 1394, + Xtensa_AE_SRAS32 = 1395, + Xtensa_AE_SRAS64 = 1396, + Xtensa_AE_SRLA32 = 1397, + Xtensa_AE_SRLA64 = 1398, + Xtensa_AE_SRLI24 = 1399, + Xtensa_AE_SRLI32 = 1400, + Xtensa_AE_SRLI64 = 1401, + Xtensa_AE_SRLS24 = 1402, + Xtensa_AE_SRLS32 = 1403, + Xtensa_AE_SRLS64 = 1404, + Xtensa_AE_SUB16 = 1405, + Xtensa_AE_SUB16S = 1406, + Xtensa_AE_SUB24S = 1407, + Xtensa_AE_SUB32 = 1408, + Xtensa_AE_SUB32S = 1409, + Xtensa_AE_SUB64 = 1410, + Xtensa_AE_SUB64S = 1411, + Xtensa_AE_SUBADD32 = 1412, + Xtensa_AE_SUBADD32S = 1413, + Xtensa_AE_TRUNCA32F64S_L = 1414, + Xtensa_AE_TRUNCA32X2F64S = 1415, + Xtensa_AE_TRUNCI32F64S_L = 1416, + Xtensa_AE_TRUNCI32X2F64S = 1417, + Xtensa_AE_VLDL16C = 1418, + Xtensa_AE_VLDL16C_IC = 1419, + Xtensa_AE_VLDL16C_IP = 1420, + Xtensa_AE_VLDL16T = 1421, + Xtensa_AE_VLDL32T = 1422, + Xtensa_AE_VLDSHT = 1423, + Xtensa_AE_VLEL16T = 1424, + Xtensa_AE_VLEL32T = 1425, + Xtensa_AE_VLES16C = 1426, + Xtensa_AE_VLES16C_IC = 1427, + Xtensa_AE_VLES16C_IP = 1428, + Xtensa_AE_XOR = 1429, + Xtensa_AE_ZALIGN64 = 1430, + Xtensa_ALL4 = 1431, + Xtensa_ALL8 = 1432, + Xtensa_AND = 1433, + Xtensa_ANDB = 1434, + Xtensa_ANDBC = 1435, + Xtensa_ANY4 = 1436, + Xtensa_ANY8 = 1437, + Xtensa_BALL = 1438, + Xtensa_BANY = 1439, + Xtensa_BBC = 1440, + Xtensa_BBCI = 1441, + Xtensa_BBS = 1442, + Xtensa_BBSI = 1443, + Xtensa_BEQ = 1444, + Xtensa_BEQI = 1445, + Xtensa_BEQZ = 1446, + Xtensa_BF = 1447, + Xtensa_BGE = 1448, + Xtensa_BGEI = 1449, + Xtensa_BGEU = 1450, + Xtensa_BGEUI = 1451, + Xtensa_BGEZ = 1452, + Xtensa_BLT = 1453, + Xtensa_BLTI = 1454, + Xtensa_BLTU = 1455, + Xtensa_BLTUI = 1456, + Xtensa_BLTZ = 1457, + Xtensa_BNALL = 1458, + Xtensa_BNE = 1459, + Xtensa_BNEI = 1460, + Xtensa_BNEZ = 1461, + Xtensa_BNONE = 1462, + Xtensa_BREAK = 1463, + Xtensa_BREAK_N = 1464, + Xtensa_BT = 1465, + Xtensa_CALL0 = 1466, + Xtensa_CALL12 = 1467, + Xtensa_CALL4 = 1468, + Xtensa_CALL8 = 1469, + Xtensa_CALLX0 = 1470, + Xtensa_CALLX12 = 1471, + Xtensa_CALLX4 = 1472, + Xtensa_CALLX8 = 1473, + Xtensa_CEIL_S = 1474, + Xtensa_CLAMPS = 1475, + Xtensa_CLR_BIT_GPIO_OUT = 1476, + Xtensa_CONST_S = 1477, + Xtensa_DIV0_S = 1478, + Xtensa_DIVN_S = 1479, + Xtensa_DSYNC = 1480, + Xtensa_EE_ANDQ = 1481, + Xtensa_EE_BITREV = 1482, + Xtensa_EE_CLR_BIT_GPIO_OUT = 1483, + Xtensa_EE_CMUL_S16 = 1484, + Xtensa_EE_CMUL_S16_LD_INCP = 1485, + Xtensa_EE_CMUL_S16_ST_INCP = 1486, + Xtensa_EE_FFT_AMS_S16_LD_INCP = 1487, + Xtensa_EE_FFT_AMS_S16_LD_INCP_UAUP = 1488, + Xtensa_EE_FFT_AMS_S16_LD_R32_DECP = 1489, + Xtensa_EE_FFT_AMS_S16_ST_INCP = 1490, + Xtensa_EE_FFT_CMUL_S16_LD_XP = 1491, + Xtensa_EE_FFT_CMUL_S16_ST_XP = 1492, + Xtensa_EE_FFT_R2BF_S16 = 1493, + Xtensa_EE_FFT_R2BF_S16_ST_INCP = 1494, + Xtensa_EE_FFT_VST_R32_DECP = 1495, + Xtensa_EE_GET_GPIO_IN = 1496, + Xtensa_EE_LDF_128_IP = 1497, + Xtensa_EE_LDF_128_XP = 1498, + Xtensa_EE_LDF_64_IP = 1499, + Xtensa_EE_LDF_64_XP = 1500, + Xtensa_EE_LDQA_S16_128_IP = 1501, + Xtensa_EE_LDQA_S16_128_XP = 1502, + Xtensa_EE_LDQA_S8_128_IP = 1503, + Xtensa_EE_LDQA_S8_128_XP = 1504, + Xtensa_EE_LDQA_U16_128_IP = 1505, + Xtensa_EE_LDQA_U16_128_XP = 1506, + Xtensa_EE_LDQA_U8_128_IP = 1507, + Xtensa_EE_LDQA_U8_128_XP = 1508, + Xtensa_EE_LDXQ_32 = 1509, + Xtensa_EE_LD_128_USAR_IP = 1510, + Xtensa_EE_LD_128_USAR_XP = 1511, + Xtensa_EE_LD_ACCX_IP = 1512, + Xtensa_EE_LD_QACC_H_H_32_IP = 1513, + Xtensa_EE_LD_QACC_H_L_128_IP = 1514, + Xtensa_EE_LD_QACC_L_H_32_IP = 1515, + Xtensa_EE_LD_QACC_L_L_128_IP = 1516, + Xtensa_EE_LD_UA_STATE_IP = 1517, + Xtensa_EE_MOVI_32_A = 1518, + Xtensa_EE_MOVI_32_Q = 1519, + Xtensa_EE_MOV_S16_QACC = 1520, + Xtensa_EE_MOV_S8_QACC = 1521, + Xtensa_EE_MOV_U16_QACC = 1522, + Xtensa_EE_MOV_U8_QACC = 1523, + Xtensa_EE_NOTQ = 1524, + Xtensa_EE_ORQ = 1525, + Xtensa_EE_SET_BIT_GPIO_OUT = 1526, + Xtensa_EE_SLCI_2Q = 1527, + Xtensa_EE_SLCXXP_2Q = 1528, + Xtensa_EE_SRCI_2Q = 1529, + Xtensa_EE_SRCMB_S16_QACC = 1530, + Xtensa_EE_SRCMB_S8_QACC = 1531, + Xtensa_EE_SRCQ_128_ST_INCP = 1532, + Xtensa_EE_SRCXXP_2Q = 1533, + Xtensa_EE_SRC_Q = 1534, + Xtensa_EE_SRC_Q_LD_IP = 1535, + Xtensa_EE_SRC_Q_LD_XP = 1536, + Xtensa_EE_SRC_Q_QUP = 1537, + Xtensa_EE_SRS_ACCX = 1538, + Xtensa_EE_STF_128_IP = 1539, + Xtensa_EE_STF_128_XP = 1540, + Xtensa_EE_STF_64_IP = 1541, + Xtensa_EE_STF_64_XP = 1542, + Xtensa_EE_STXQ_32 = 1543, + Xtensa_EE_ST_ACCX_IP = 1544, + Xtensa_EE_ST_QACC_H_H_32_IP = 1545, + Xtensa_EE_ST_QACC_H_L_128_IP = 1546, + Xtensa_EE_ST_QACC_L_H_32_IP = 1547, + Xtensa_EE_ST_QACC_L_L_128_IP = 1548, + Xtensa_EE_ST_UA_STATE_IP = 1549, + Xtensa_EE_VADDS_S16 = 1550, + Xtensa_EE_VADDS_S16_LD_INCP = 1551, + Xtensa_EE_VADDS_S16_ST_INCP = 1552, + Xtensa_EE_VADDS_S32 = 1553, + Xtensa_EE_VADDS_S32_LD_INCP = 1554, + Xtensa_EE_VADDS_S32_ST_INCP = 1555, + Xtensa_EE_VADDS_S8 = 1556, + Xtensa_EE_VADDS_S8_LD_INCP = 1557, + Xtensa_EE_VADDS_S8_ST_INCP = 1558, + Xtensa_EE_VCMP_EQ_S16 = 1559, + Xtensa_EE_VCMP_EQ_S32 = 1560, + Xtensa_EE_VCMP_EQ_S8 = 1561, + Xtensa_EE_VCMP_GT_S16 = 1562, + Xtensa_EE_VCMP_GT_S32 = 1563, + Xtensa_EE_VCMP_GT_S8 = 1564, + Xtensa_EE_VCMP_LT_S16 = 1565, + Xtensa_EE_VCMP_LT_S32 = 1566, + Xtensa_EE_VCMP_LT_S8 = 1567, + Xtensa_EE_VLDBC_16 = 1568, + Xtensa_EE_VLDBC_16_IP = 1569, + Xtensa_EE_VLDBC_16_XP = 1570, + Xtensa_EE_VLDBC_32 = 1571, + Xtensa_EE_VLDBC_32_IP = 1572, + Xtensa_EE_VLDBC_32_XP = 1573, + Xtensa_EE_VLDBC_8 = 1574, + Xtensa_EE_VLDBC_8_IP = 1575, + Xtensa_EE_VLDBC_8_XP = 1576, + Xtensa_EE_VLDHBC_16_INCP = 1577, + Xtensa_EE_VLD_128_IP = 1578, + Xtensa_EE_VLD_128_XP = 1579, + Xtensa_EE_VLD_H_64_IP = 1580, + Xtensa_EE_VLD_H_64_XP = 1581, + Xtensa_EE_VLD_L_64_IP = 1582, + Xtensa_EE_VLD_L_64_XP = 1583, + Xtensa_EE_VMAX_S16 = 1584, + Xtensa_EE_VMAX_S16_LD_INCP = 1585, + Xtensa_EE_VMAX_S16_ST_INCP = 1586, + Xtensa_EE_VMAX_S32 = 1587, + Xtensa_EE_VMAX_S32_LD_INCP = 1588, + Xtensa_EE_VMAX_S32_ST_INCP = 1589, + Xtensa_EE_VMAX_S8 = 1590, + Xtensa_EE_VMAX_S8_LD_INCP = 1591, + Xtensa_EE_VMAX_S8_ST_INCP = 1592, + Xtensa_EE_VMIN_S16 = 1593, + Xtensa_EE_VMIN_S16_LD_INCP = 1594, + Xtensa_EE_VMIN_S16_ST_INCP = 1595, + Xtensa_EE_VMIN_S32 = 1596, + Xtensa_EE_VMIN_S32_LD_INCP = 1597, + Xtensa_EE_VMIN_S32_ST_INCP = 1598, + Xtensa_EE_VMIN_S8 = 1599, + Xtensa_EE_VMIN_S8_LD_INCP = 1600, + Xtensa_EE_VMIN_S8_ST_INCP = 1601, + Xtensa_EE_VMULAS_S16_ACCX = 1602, + Xtensa_EE_VMULAS_S16_ACCX_LD_IP = 1603, + Xtensa_EE_VMULAS_S16_ACCX_LD_IP_QUP = 1604, + Xtensa_EE_VMULAS_S16_ACCX_LD_XP = 1605, + Xtensa_EE_VMULAS_S16_ACCX_LD_XP_QUP = 1606, + Xtensa_EE_VMULAS_S16_QACC = 1607, + Xtensa_EE_VMULAS_S16_QACC_LDBC_INCP = 1608, + Xtensa_EE_VMULAS_S16_QACC_LDBC_INCP_QUP = 1609, + Xtensa_EE_VMULAS_S16_QACC_LD_IP = 1610, + Xtensa_EE_VMULAS_S16_QACC_LD_IP_QUP = 1611, + Xtensa_EE_VMULAS_S16_QACC_LD_XP = 1612, + Xtensa_EE_VMULAS_S16_QACC_LD_XP_QUP = 1613, + Xtensa_EE_VMULAS_S8_ACCX = 1614, + Xtensa_EE_VMULAS_S8_ACCX_LD_IP = 1615, + Xtensa_EE_VMULAS_S8_ACCX_LD_IP_QUP = 1616, + Xtensa_EE_VMULAS_S8_ACCX_LD_XP = 1617, + Xtensa_EE_VMULAS_S8_ACCX_LD_XP_QUP = 1618, + Xtensa_EE_VMULAS_S8_QACC = 1619, + Xtensa_EE_VMULAS_S8_QACC_LDBC_INCP = 1620, + Xtensa_EE_VMULAS_S8_QACC_LDBC_INCP_QUP = 1621, + Xtensa_EE_VMULAS_S8_QACC_LD_IP = 1622, + Xtensa_EE_VMULAS_S8_QACC_LD_IP_QUP = 1623, + Xtensa_EE_VMULAS_S8_QACC_LD_XP = 1624, + Xtensa_EE_VMULAS_S8_QACC_LD_XP_QUP = 1625, + Xtensa_EE_VMULAS_U16_ACCX = 1626, + Xtensa_EE_VMULAS_U16_ACCX_LD_IP = 1627, + Xtensa_EE_VMULAS_U16_ACCX_LD_IP_QUP = 1628, + Xtensa_EE_VMULAS_U16_ACCX_LD_XP = 1629, + Xtensa_EE_VMULAS_U16_ACCX_LD_XP_QUP = 1630, + Xtensa_EE_VMULAS_U16_QACC = 1631, + Xtensa_EE_VMULAS_U16_QACC_LDBC_INCP = 1632, + Xtensa_EE_VMULAS_U16_QACC_LDBC_INCP_QUP = 1633, + Xtensa_EE_VMULAS_U16_QACC_LD_IP = 1634, + Xtensa_EE_VMULAS_U16_QACC_LD_IP_QUP = 1635, + Xtensa_EE_VMULAS_U16_QACC_LD_XP = 1636, + Xtensa_EE_VMULAS_U16_QACC_LD_XP_QUP = 1637, + Xtensa_EE_VMULAS_U8_ACCX = 1638, + Xtensa_EE_VMULAS_U8_ACCX_LD_IP = 1639, + Xtensa_EE_VMULAS_U8_ACCX_LD_IP_QUP = 1640, + Xtensa_EE_VMULAS_U8_ACCX_LD_XP = 1641, + Xtensa_EE_VMULAS_U8_ACCX_LD_XP_QUP = 1642, + Xtensa_EE_VMULAS_U8_QACC = 1643, + Xtensa_EE_VMULAS_U8_QACC_LDBC_INCP = 1644, + Xtensa_EE_VMULAS_U8_QACC_LDBC_INCP_QUP = 1645, + Xtensa_EE_VMULAS_U8_QACC_LD_IP = 1646, + Xtensa_EE_VMULAS_U8_QACC_LD_IP_QUP = 1647, + Xtensa_EE_VMULAS_U8_QACC_LD_XP = 1648, + Xtensa_EE_VMULAS_U8_QACC_LD_XP_QUP = 1649, + Xtensa_EE_VMUL_S16 = 1650, + Xtensa_EE_VMUL_S16_LD_INCP = 1651, + Xtensa_EE_VMUL_S16_ST_INCP = 1652, + Xtensa_EE_VMUL_S8 = 1653, + Xtensa_EE_VMUL_S8_LD_INCP = 1654, + Xtensa_EE_VMUL_S8_ST_INCP = 1655, + Xtensa_EE_VMUL_U16 = 1656, + Xtensa_EE_VMUL_U16_LD_INCP = 1657, + Xtensa_EE_VMUL_U16_ST_INCP = 1658, + Xtensa_EE_VMUL_U8 = 1659, + Xtensa_EE_VMUL_U8_LD_INCP = 1660, + Xtensa_EE_VMUL_U8_ST_INCP = 1661, + Xtensa_EE_VPRELU_S16 = 1662, + Xtensa_EE_VPRELU_S8 = 1663, + Xtensa_EE_VRELU_S16 = 1664, + Xtensa_EE_VRELU_S8 = 1665, + Xtensa_EE_VSL_32 = 1666, + Xtensa_EE_VSMULAS_S16_QACC = 1667, + Xtensa_EE_VSMULAS_S16_QACC_LD_INCP = 1668, + Xtensa_EE_VSMULAS_S8_QACC = 1669, + Xtensa_EE_VSMULAS_S8_QACC_LD_INCP = 1670, + Xtensa_EE_VSR_32 = 1671, + Xtensa_EE_VST_128_IP = 1672, + Xtensa_EE_VST_128_XP = 1673, + Xtensa_EE_VST_H_64_IP = 1674, + Xtensa_EE_VST_H_64_XP = 1675, + Xtensa_EE_VST_L_64_IP = 1676, + Xtensa_EE_VST_L_64_XP = 1677, + Xtensa_EE_VSUBS_S16 = 1678, + Xtensa_EE_VSUBS_S16_LD_INCP = 1679, + Xtensa_EE_VSUBS_S16_ST_INCP = 1680, + Xtensa_EE_VSUBS_S32 = 1681, + Xtensa_EE_VSUBS_S32_LD_INCP = 1682, + Xtensa_EE_VSUBS_S32_ST_INCP = 1683, + Xtensa_EE_VSUBS_S8 = 1684, + Xtensa_EE_VSUBS_S8_LD_INCP = 1685, + Xtensa_EE_VSUBS_S8_ST_INCP = 1686, + Xtensa_EE_VUNZIP_16 = 1687, + Xtensa_EE_VUNZIP_32 = 1688, + Xtensa_EE_VUNZIP_8 = 1689, + Xtensa_EE_VZIP_16 = 1690, + Xtensa_EE_VZIP_32 = 1691, + Xtensa_EE_VZIP_8 = 1692, + Xtensa_EE_WR_MASK_GPIO_OUT = 1693, + Xtensa_EE_XORQ = 1694, + Xtensa_EE_ZERO_ACCX = 1695, + Xtensa_EE_ZERO_Q = 1696, + Xtensa_EE_ZERO_QACC = 1697, + Xtensa_ENTRY = 1698, + Xtensa_ESYNC = 1699, + Xtensa_EXCW = 1700, + Xtensa_EXTUI = 1701, + Xtensa_EXTW = 1702, + Xtensa_FLOAT_S = 1703, + Xtensa_FLOOR_S = 1704, + Xtensa_GET_GPIO_IN = 1705, + Xtensa_ILL = 1706, + Xtensa_ILL_N = 1707, + Xtensa_ISYNC = 1708, + Xtensa_J = 1709, + Xtensa_JX = 1710, + Xtensa_L16SI = 1711, + Xtensa_L16UI = 1712, + Xtensa_L32E = 1713, + Xtensa_L32I = 1714, + Xtensa_L32I_N = 1715, + Xtensa_L32R = 1716, + Xtensa_L8UI = 1717, + Xtensa_LDDEC = 1718, + Xtensa_LDINC = 1719, + Xtensa_LEA_ADD = 1720, + Xtensa_LOOP = 1721, + Xtensa_LOOPGTZ = 1722, + Xtensa_LOOPNEZ = 1723, + Xtensa_LSI = 1724, + Xtensa_LSIP = 1725, + Xtensa_LSX = 1726, + Xtensa_LSXP = 1727, + Xtensa_MADDN_S = 1728, + Xtensa_MADD_S = 1729, + Xtensa_MAX = 1730, + Xtensa_MAXU = 1731, + Xtensa_MEMW = 1732, + Xtensa_MIN = 1733, + Xtensa_MINU = 1734, + Xtensa_MKDADJ_S = 1735, + Xtensa_MKSADJ_S = 1736, + Xtensa_MOVEQZ = 1737, + Xtensa_MOVEQZ_S = 1738, + Xtensa_MOVF = 1739, + Xtensa_MOVF_S = 1740, + Xtensa_MOVGEZ = 1741, + Xtensa_MOVGEZ_S = 1742, + Xtensa_MOVI = 1743, + Xtensa_MOVI_N = 1744, + Xtensa_MOVLTZ = 1745, + Xtensa_MOVLTZ_S = 1746, + Xtensa_MOVNEZ = 1747, + Xtensa_MOVNEZ_S = 1748, + Xtensa_MOVSP = 1749, + Xtensa_MOVT = 1750, + Xtensa_MOVT_S = 1751, + Xtensa_MOV_N = 1752, + Xtensa_MOV_S = 1753, + Xtensa_MSUB_S = 1754, + Xtensa_MUL16S = 1755, + Xtensa_MUL16U = 1756, + Xtensa_MULA_AA_HH = 1757, + Xtensa_MULA_AA_HL = 1758, + Xtensa_MULA_AA_LH = 1759, + Xtensa_MULA_AA_LL = 1760, + Xtensa_MULA_AD_HH = 1761, + Xtensa_MULA_AD_HL = 1762, + Xtensa_MULA_AD_LH = 1763, + Xtensa_MULA_AD_LL = 1764, + Xtensa_MULA_DA_HH = 1765, + Xtensa_MULA_DA_HH_LDDEC = 1766, + Xtensa_MULA_DA_HH_LDINC = 1767, + Xtensa_MULA_DA_HL = 1768, + Xtensa_MULA_DA_HL_LDDEC = 1769, + Xtensa_MULA_DA_HL_LDINC = 1770, + Xtensa_MULA_DA_LH = 1771, + Xtensa_MULA_DA_LH_LDDEC = 1772, + Xtensa_MULA_DA_LH_LDINC = 1773, + Xtensa_MULA_DA_LL = 1774, + Xtensa_MULA_DA_LL_LDDEC = 1775, + Xtensa_MULA_DA_LL_LDINC = 1776, + Xtensa_MULA_DD_HH = 1777, + Xtensa_MULA_DD_HH_LDDEC = 1778, + Xtensa_MULA_DD_HH_LDINC = 1779, + Xtensa_MULA_DD_HL = 1780, + Xtensa_MULA_DD_HL_LDDEC = 1781, + Xtensa_MULA_DD_HL_LDINC = 1782, + Xtensa_MULA_DD_LH = 1783, + Xtensa_MULA_DD_LH_LDDEC = 1784, + Xtensa_MULA_DD_LH_LDINC = 1785, + Xtensa_MULA_DD_LL = 1786, + Xtensa_MULA_DD_LL_LDDEC = 1787, + Xtensa_MULA_DD_LL_LDINC = 1788, + Xtensa_MULL = 1789, + Xtensa_MULSH = 1790, + Xtensa_MULS_AA_HH = 1791, + Xtensa_MULS_AA_HL = 1792, + Xtensa_MULS_AA_LH = 1793, + Xtensa_MULS_AA_LL = 1794, + Xtensa_MULS_AD_HH = 1795, + Xtensa_MULS_AD_HL = 1796, + Xtensa_MULS_AD_LH = 1797, + Xtensa_MULS_AD_LL = 1798, + Xtensa_MULS_DA_HH = 1799, + Xtensa_MULS_DA_HL = 1800, + Xtensa_MULS_DA_LH = 1801, + Xtensa_MULS_DA_LL = 1802, + Xtensa_MULS_DD_HH = 1803, + Xtensa_MULS_DD_HL = 1804, + Xtensa_MULS_DD_LH = 1805, + Xtensa_MULS_DD_LL = 1806, + Xtensa_MULUH = 1807, + Xtensa_MUL_AA_HH = 1808, + Xtensa_MUL_AA_HL = 1809, + Xtensa_MUL_AA_LH = 1810, + Xtensa_MUL_AA_LL = 1811, + Xtensa_MUL_AD_HH = 1812, + Xtensa_MUL_AD_HL = 1813, + Xtensa_MUL_AD_LH = 1814, + Xtensa_MUL_AD_LL = 1815, + Xtensa_MUL_DA_HH = 1816, + Xtensa_MUL_DA_HL = 1817, + Xtensa_MUL_DA_LH = 1818, + Xtensa_MUL_DA_LL = 1819, + Xtensa_MUL_DD_HH = 1820, + Xtensa_MUL_DD_HL = 1821, + Xtensa_MUL_DD_LH = 1822, + Xtensa_MUL_DD_LL = 1823, + Xtensa_MUL_S = 1824, + Xtensa_NEG = 1825, + Xtensa_NEG_S = 1826, + Xtensa_NEXP01_S = 1827, + Xtensa_NOP = 1828, + Xtensa_NSA = 1829, + Xtensa_NSAU = 1830, + Xtensa_OEQ_S = 1831, + Xtensa_OLE_S = 1832, + Xtensa_OLT_S = 1833, + Xtensa_OR = 1834, + Xtensa_ORB = 1835, + Xtensa_ORBC = 1836, + Xtensa_QUOS = 1837, + Xtensa_QUOU = 1838, + Xtensa_RECIP0_S = 1839, + Xtensa_REMS = 1840, + Xtensa_REMU = 1841, + Xtensa_RER = 1842, + Xtensa_RET = 1843, + Xtensa_RETW = 1844, + Xtensa_RETW_N = 1845, + Xtensa_RET_N = 1846, + Xtensa_RFDE = 1847, + Xtensa_RFE = 1848, + Xtensa_RFI = 1849, + Xtensa_RFR = 1850, + Xtensa_RFWO = 1851, + Xtensa_RFWU = 1852, + Xtensa_ROTW = 1853, + Xtensa_ROUND_S = 1854, + Xtensa_RSIL = 1855, + Xtensa_RSQRT0_S = 1856, + Xtensa_RSR = 1857, + Xtensa_RSYNC = 1858, + Xtensa_RUR = 1859, + Xtensa_RUR_ACCX_0 = 1860, + Xtensa_RUR_ACCX_1 = 1861, + Xtensa_RUR_AE_BITHEAD = 1862, + Xtensa_RUR_AE_BITPTR = 1863, + Xtensa_RUR_AE_BITSUSED = 1864, + Xtensa_RUR_AE_CBEGIN0 = 1865, + Xtensa_RUR_AE_CEND0 = 1866, + Xtensa_RUR_AE_CWRAP = 1867, + Xtensa_RUR_AE_CW_SD_NO = 1868, + Xtensa_RUR_AE_FIRST_TS = 1869, + Xtensa_RUR_AE_NEXTOFFSET = 1870, + Xtensa_RUR_AE_OVERFLOW = 1871, + Xtensa_RUR_AE_OVF_SAR = 1872, + Xtensa_RUR_AE_SAR = 1873, + Xtensa_RUR_AE_SEARCHDONE = 1874, + Xtensa_RUR_AE_TABLESIZE = 1875, + Xtensa_RUR_AE_TS_FTS_BU_BP = 1876, + Xtensa_RUR_FFT_BIT_WIDTH = 1877, + Xtensa_RUR_GPIO_OUT = 1878, + Xtensa_RUR_QACC_H_0 = 1879, + Xtensa_RUR_QACC_H_1 = 1880, + Xtensa_RUR_QACC_H_2 = 1881, + Xtensa_RUR_QACC_H_3 = 1882, + Xtensa_RUR_QACC_H_4 = 1883, + Xtensa_RUR_QACC_L_0 = 1884, + Xtensa_RUR_QACC_L_1 = 1885, + Xtensa_RUR_QACC_L_2 = 1886, + Xtensa_RUR_QACC_L_3 = 1887, + Xtensa_RUR_QACC_L_4 = 1888, + Xtensa_RUR_SAR_BYTE = 1889, + Xtensa_RUR_UA_STATE_0 = 1890, + Xtensa_RUR_UA_STATE_1 = 1891, + Xtensa_RUR_UA_STATE_2 = 1892, + Xtensa_RUR_UA_STATE_3 = 1893, + Xtensa_S16I = 1894, + Xtensa_S32C1I = 1895, + Xtensa_S32E = 1896, + Xtensa_S32I = 1897, + Xtensa_S32I_N = 1898, + Xtensa_S8I = 1899, + Xtensa_SET_BIT_GPIO_OUT = 1900, + Xtensa_SEXT = 1901, + Xtensa_SIMCALL = 1902, + Xtensa_SLL = 1903, + Xtensa_SLLI = 1904, + Xtensa_SQRT0_S = 1905, + Xtensa_SRA = 1906, + Xtensa_SRAI = 1907, + Xtensa_SRC = 1908, + Xtensa_SRL = 1909, + Xtensa_SRLI = 1910, + Xtensa_SSA8L = 1911, + Xtensa_SSAI = 1912, + Xtensa_SSI = 1913, + Xtensa_SSIP = 1914, + Xtensa_SSL = 1915, + Xtensa_SSR = 1916, + Xtensa_SSX = 1917, + Xtensa_SSXP = 1918, + Xtensa_SUB = 1919, + Xtensa_SUBX2 = 1920, + Xtensa_SUBX4 = 1921, + Xtensa_SUBX8 = 1922, + Xtensa_SUB_S = 1923, + Xtensa_SYSCALL = 1924, + Xtensa_TRUNC_S = 1925, + Xtensa_UEQ_S = 1926, + Xtensa_UFLOAT_S = 1927, + Xtensa_ULE_S = 1928, + Xtensa_ULT_S = 1929, + Xtensa_UMUL_AA_HH = 1930, + Xtensa_UMUL_AA_HL = 1931, + Xtensa_UMUL_AA_LH = 1932, + Xtensa_UMUL_AA_LL = 1933, + Xtensa_UN_S = 1934, + Xtensa_UTRUNC_S = 1935, + Xtensa_WAITI = 1936, + Xtensa_WDTLB = 1937, + Xtensa_WER = 1938, + Xtensa_WFR = 1939, + Xtensa_WITLB = 1940, + Xtensa_WR_MASK_GPIO_OUT = 1941, + Xtensa_WSR = 1942, + Xtensa_WUR = 1943, + Xtensa_WUR_ACCX_0 = 1944, + Xtensa_WUR_ACCX_1 = 1945, + Xtensa_WUR_AE_BITHEAD = 1946, + Xtensa_WUR_AE_BITPTR = 1947, + Xtensa_WUR_AE_BITSUSED = 1948, + Xtensa_WUR_AE_CBEGIN0 = 1949, + Xtensa_WUR_AE_CEND0 = 1950, + Xtensa_WUR_AE_CWRAP = 1951, + Xtensa_WUR_AE_CW_SD_NO = 1952, + Xtensa_WUR_AE_FIRST_TS = 1953, + Xtensa_WUR_AE_NEXTOFFSET = 1954, + Xtensa_WUR_AE_OVERFLOW = 1955, + Xtensa_WUR_AE_OVF_SAR = 1956, + Xtensa_WUR_AE_SAR = 1957, + Xtensa_WUR_AE_SEARCHDONE = 1958, + Xtensa_WUR_AE_TABLESIZE = 1959, + Xtensa_WUR_AE_TS_FTS_BU_BP = 1960, + Xtensa_WUR_FCR = 1961, + Xtensa_WUR_FFT_BIT_WIDTH = 1962, + Xtensa_WUR_FSR = 1963, + Xtensa_WUR_GPIO_OUT = 1964, + Xtensa_WUR_QACC_H_0 = 1965, + Xtensa_WUR_QACC_H_1 = 1966, + Xtensa_WUR_QACC_H_2 = 1967, + Xtensa_WUR_QACC_H_3 = 1968, + Xtensa_WUR_QACC_H_4 = 1969, + Xtensa_WUR_QACC_L_0 = 1970, + Xtensa_WUR_QACC_L_1 = 1971, + Xtensa_WUR_QACC_L_2 = 1972, + Xtensa_WUR_QACC_L_3 = 1973, + Xtensa_WUR_QACC_L_4 = 1974, + Xtensa_WUR_SAR_BYTE = 1975, + Xtensa_WUR_UA_STATE_0 = 1976, + Xtensa_WUR_UA_STATE_1 = 1977, + Xtensa_WUR_UA_STATE_2 = 1978, + Xtensa_WUR_UA_STATE_3 = 1979, + Xtensa_XOR = 1980, + Xtensa_XORB = 1981, + Xtensa_XSR = 1982, + Xtensa__L32I = 1983, + Xtensa__L32I_N = 1984, + Xtensa__MOVI = 1985, + Xtensa__S32I = 1986, + Xtensa__S32I_N = 1987, + Xtensa__SLLI = 1988, + Xtensa__SRLI = 1989, + Xtensa_mv_QR = 1990, + INSTRUCTION_LIST_END = 1991 }; #endif // GET_INSTRINFO_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) typedef struct XtensaInstrTable { - MCInstrDesc Insts[350]; - MCOperandInfo OperandInfo[169]; - MCPhysReg ImplicitOps[2]; + MCInstrDesc Insts[1991]; + MCOperandInfo OperandInfo[885]; + MCPhysReg ImplicitOps[19]; } XtensaInstrTable; #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) @@ -386,85 +2027,1726 @@ static const unsigned XtensaImpOpBase = sizeof(MCOperandInfo) / (sizeof(MCPhysRe static const XtensaInstrTable XtensaDescs = { { - { 4, &XtensaDescs.OperandInfo[165] }, // Inst #349 = XSR - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #348 = XOR - { 2, &XtensaDescs.OperandInfo[163] }, // Inst #347 = WSR - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #346 = SUBX8 - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #345 = SUBX4 - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #344 = SUBX2 - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #343 = SUB - { 1, &XtensaDescs.OperandInfo[153] }, // Inst #342 = SSR - { 1, &XtensaDescs.OperandInfo[153] }, // Inst #341 = SSL - { 1, &XtensaDescs.OperandInfo[0] }, // Inst #340 = SSAI - { 1, &XtensaDescs.OperandInfo[153] }, // Inst #339 = SSA8L - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #338 = SRLI - { 2, &XtensaDescs.OperandInfo[140] }, // Inst #337 = SRL - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #336 = SRC - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #335 = SRAI - { 2, &XtensaDescs.OperandInfo[140] }, // Inst #334 = SRA - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #333 = SLLI - { 2, &XtensaDescs.OperandInfo[140] }, // Inst #332 = SLL - { 3, &XtensaDescs.OperandInfo[158] }, // Inst #331 = S8I - { 3, &XtensaDescs.OperandInfo[158] }, // Inst #330 = S32I - { 3, &XtensaDescs.OperandInfo[158] }, // Inst #329 = S16I - { 0, &XtensaDescs.OperandInfo[1] }, // Inst #328 = RSYNC - { 2, &XtensaDescs.OperandInfo[161] }, // Inst #327 = RSR - { 0, &XtensaDescs.OperandInfo[1] }, // Inst #326 = RET - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #325 = OR - { 0, &XtensaDescs.OperandInfo[1] }, // Inst #324 = NOP - { 2, &XtensaDescs.OperandInfo[140] }, // Inst #323 = NEG - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #322 = MOVNEZ - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #321 = MOVLTZ - { 2, &XtensaDescs.OperandInfo[151] }, // Inst #320 = MOVI - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #319 = MOVGEZ - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #318 = MOVEQZ - { 0, &XtensaDescs.OperandInfo[1] }, // Inst #317 = MEMW - { 3, &XtensaDescs.OperandInfo[158] }, // Inst #316 = L8UI - { 2, &XtensaDescs.OperandInfo[151] }, // Inst #315 = L32R - { 3, &XtensaDescs.OperandInfo[158] }, // Inst #314 = L32I - { 3, &XtensaDescs.OperandInfo[158] }, // Inst #313 = L16UI - { 3, &XtensaDescs.OperandInfo[158] }, // Inst #312 = L16SI - { 1, &XtensaDescs.OperandInfo[153] }, // Inst #311 = JX - { 1, &XtensaDescs.OperandInfo[0] }, // Inst #310 = J - { 0, &XtensaDescs.OperandInfo[1] }, // Inst #309 = ISYNC - { 0, &XtensaDescs.OperandInfo[1] }, // Inst #308 = EXTW - { 4, &XtensaDescs.OperandInfo[154] }, // Inst #307 = EXTUI - { 0, &XtensaDescs.OperandInfo[1] }, // Inst #306 = ESYNC - { 0, &XtensaDescs.OperandInfo[1] }, // Inst #305 = DSYNC - { 1, &XtensaDescs.OperandInfo[153] }, // Inst #304 = CALLX0 - { 1, &XtensaDescs.OperandInfo[0] }, // Inst #303 = CALL0 - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #302 = BNONE - { 2, &XtensaDescs.OperandInfo[151] }, // Inst #301 = BNEZ - { 3, &XtensaDescs.OperandInfo[148] }, // Inst #300 = BNEI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #299 = BNE - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #298 = BNALL - { 2, &XtensaDescs.OperandInfo[151] }, // Inst #297 = BLTZ - { 3, &XtensaDescs.OperandInfo[148] }, // Inst #296 = BLTUI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #295 = BLTU - { 3, &XtensaDescs.OperandInfo[148] }, // Inst #294 = BLTI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #293 = BLT - { 2, &XtensaDescs.OperandInfo[151] }, // Inst #292 = BGEZ - { 3, &XtensaDescs.OperandInfo[148] }, // Inst #291 = BGEUI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #290 = BGEU - { 3, &XtensaDescs.OperandInfo[148] }, // Inst #289 = BGEI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #288 = BGE - { 2, &XtensaDescs.OperandInfo[151] }, // Inst #287 = BEQZ - { 3, &XtensaDescs.OperandInfo[148] }, // Inst #286 = BEQI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #285 = BEQ - { 3, &XtensaDescs.OperandInfo[148] }, // Inst #284 = BBSI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #283 = BBS - { 3, &XtensaDescs.OperandInfo[148] }, // Inst #282 = BBCI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #281 = BBC - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #280 = BANY - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #279 = BALL - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #278 = AND - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #277 = ADDX8 - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #276 = ADDX4 - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #275 = ADDX2 - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #274 = ADDMI - { 3, &XtensaDescs.OperandInfo[145] }, // Inst #273 = ADDI - { 3, &XtensaDescs.OperandInfo[142] }, // Inst #272 = ADD - { 2, &XtensaDescs.OperandInfo[140] }, // Inst #271 = ABS + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1990 = mv_QR + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1989 = _SRLI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1988 = _SLLI + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1987 = _S32I_N + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1986 = _S32I + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1985 = _MOVI + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1984 = _L32I_N + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1983 = _L32I + { 4, &XtensaDescs.OperandInfo[881] }, // Inst #1982 = XSR + { 3, &XtensaDescs.OperandInfo[505] }, // Inst #1981 = XORB + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1980 = XOR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1979 = WUR_UA_STATE_3 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1978 = WUR_UA_STATE_2 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1977 = WUR_UA_STATE_1 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1976 = WUR_UA_STATE_0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1975 = WUR_SAR_BYTE + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1974 = WUR_QACC_L_4 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1973 = WUR_QACC_L_3 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1972 = WUR_QACC_L_2 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1971 = WUR_QACC_L_1 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1970 = WUR_QACC_L_0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1969 = WUR_QACC_H_4 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1968 = WUR_QACC_H_3 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1967 = WUR_QACC_H_2 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1966 = WUR_QACC_H_1 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1965 = WUR_QACC_H_0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1964 = WUR_GPIO_OUT + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1963 = WUR_FSR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1962 = WUR_FFT_BIT_WIDTH + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1961 = WUR_FCR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1960 = WUR_AE_TS_FTS_BU_BP + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1959 = WUR_AE_TABLESIZE + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1958 = WUR_AE_SEARCHDONE + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1957 = WUR_AE_SAR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1956 = WUR_AE_OVF_SAR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1955 = WUR_AE_OVERFLOW + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1954 = WUR_AE_NEXTOFFSET + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1953 = WUR_AE_FIRST_TS + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1952 = WUR_AE_CW_SD_NO + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1951 = WUR_AE_CWRAP + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1950 = WUR_AE_CEND0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1949 = WUR_AE_CBEGIN0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1948 = WUR_AE_BITSUSED + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1947 = WUR_AE_BITPTR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1946 = WUR_AE_BITHEAD + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1945 = WUR_ACCX_1 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1944 = WUR_ACCX_0 + { 2, &XtensaDescs.OperandInfo[879] }, // Inst #1943 = WUR + { 2, &XtensaDescs.OperandInfo[877] }, // Inst #1942 = WSR + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1941 = WR_MASK_GPIO_OUT + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1940 = WITLB + { 2, &XtensaDescs.OperandInfo[875] }, // Inst #1939 = WFR + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1938 = WER + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1937 = WDTLB + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1936 = WAITI + { 3, &XtensaDescs.OperandInfo[513] }, // Inst #1935 = UTRUNC_S + { 3, &XtensaDescs.OperandInfo[854] }, // Inst #1934 = UN_S + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1933 = UMUL_AA_LL + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1932 = UMUL_AA_LH + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1931 = UMUL_AA_HL + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1930 = UMUL_AA_HH + { 3, &XtensaDescs.OperandInfo[854] }, // Inst #1929 = ULT_S + { 3, &XtensaDescs.OperandInfo[854] }, // Inst #1928 = ULE_S + { 3, &XtensaDescs.OperandInfo[797] }, // Inst #1927 = UFLOAT_S + { 3, &XtensaDescs.OperandInfo[854] }, // Inst #1926 = UEQ_S + { 3, &XtensaDescs.OperandInfo[513] }, // Inst #1925 = TRUNC_S + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1924 = SYSCALL + { 3, &XtensaDescs.OperandInfo[346] }, // Inst #1923 = SUB_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1922 = SUBX8 + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1921 = SUBX4 + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1920 = SUBX2 + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1919 = SUB + { 4, &XtensaDescs.OperandInfo[871] }, // Inst #1918 = SSXP + { 3, &XtensaDescs.OperandInfo[810] }, // Inst #1917 = SSX + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1916 = SSR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1915 = SSL + { 4, &XtensaDescs.OperandInfo[867] }, // Inst #1914 = SSIP + { 3, &XtensaDescs.OperandInfo[803] }, // Inst #1913 = SSI + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1912 = SSAI + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1911 = SSA8L + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1910 = SRLI + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1909 = SRL + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1908 = SRC + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1907 = SRAI + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1906 = SRA + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #1905 = SQRT0_S + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1904 = SLLI + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1903 = SLL + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1902 = SIMCALL + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1901 = SEXT + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1900 = SET_BIT_GPIO_OUT + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1899 = S8I + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1898 = S32I_N + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1897 = S32I + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1896 = S32E + { 4, &XtensaDescs.OperandInfo[863] }, // Inst #1895 = S32C1I + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1894 = S16I + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1893 = RUR_UA_STATE_3 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1892 = RUR_UA_STATE_2 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1891 = RUR_UA_STATE_1 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1890 = RUR_UA_STATE_0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1889 = RUR_SAR_BYTE + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1888 = RUR_QACC_L_4 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1887 = RUR_QACC_L_3 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1886 = RUR_QACC_L_2 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1885 = RUR_QACC_L_1 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1884 = RUR_QACC_L_0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1883 = RUR_QACC_H_4 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1882 = RUR_QACC_H_3 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1881 = RUR_QACC_H_2 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1880 = RUR_QACC_H_1 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1879 = RUR_QACC_H_0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1878 = RUR_GPIO_OUT + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1877 = RUR_FFT_BIT_WIDTH + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1876 = RUR_AE_TS_FTS_BU_BP + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1875 = RUR_AE_TABLESIZE + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1874 = RUR_AE_SEARCHDONE + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1873 = RUR_AE_SAR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1872 = RUR_AE_OVF_SAR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1871 = RUR_AE_OVERFLOW + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1870 = RUR_AE_NEXTOFFSET + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1869 = RUR_AE_FIRST_TS + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1868 = RUR_AE_CW_SD_NO + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1867 = RUR_AE_CWRAP + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1866 = RUR_AE_CEND0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1865 = RUR_AE_CBEGIN0 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1864 = RUR_AE_BITSUSED + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1863 = RUR_AE_BITPTR + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1862 = RUR_AE_BITHEAD + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1861 = RUR_ACCX_1 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1860 = RUR_ACCX_0 + { 2, &XtensaDescs.OperandInfo[861] }, // Inst #1859 = RUR + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1858 = RSYNC + { 2, &XtensaDescs.OperandInfo[859] }, // Inst #1857 = RSR + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #1856 = RSQRT0_S + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1855 = RSIL + { 3, &XtensaDescs.OperandInfo[513] }, // Inst #1854 = ROUND_S + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1853 = ROTW + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1852 = RFWU + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1851 = RFWO + { 2, &XtensaDescs.OperandInfo[857] }, // Inst #1850 = RFR + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1849 = RFI + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1848 = RFE + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1847 = RFDE + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1846 = RET_N + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1845 = RETW_N + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1844 = RETW + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1843 = RET + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1842 = RER + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1841 = REMU + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1840 = REMS + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #1839 = RECIP0_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1838 = QUOU + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1837 = QUOS + { 3, &XtensaDescs.OperandInfo[505] }, // Inst #1836 = ORBC + { 3, &XtensaDescs.OperandInfo[505] }, // Inst #1835 = ORB + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1834 = OR + { 3, &XtensaDescs.OperandInfo[854] }, // Inst #1833 = OLT_S + { 3, &XtensaDescs.OperandInfo[854] }, // Inst #1832 = OLE_S + { 3, &XtensaDescs.OperandInfo[854] }, // Inst #1831 = OEQ_S + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1830 = NSAU + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1829 = NSA + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1828 = NOP + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #1827 = NEXP01_S + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #1826 = NEG_S + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1825 = NEG + { 3, &XtensaDescs.OperandInfo[346] }, // Inst #1824 = MUL_S + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1823 = MUL_DD_LL + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1822 = MUL_DD_LH + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1821 = MUL_DD_HL + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1820 = MUL_DD_HH + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1819 = MUL_DA_LL + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1818 = MUL_DA_LH + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1817 = MUL_DA_HL + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1816 = MUL_DA_HH + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1815 = MUL_AD_LL + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1814 = MUL_AD_LH + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1813 = MUL_AD_HL + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1812 = MUL_AD_HH + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1811 = MUL_AA_LL + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1810 = MUL_AA_LH + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1809 = MUL_AA_HL + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1808 = MUL_AA_HH + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1807 = MULUH + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1806 = MULS_DD_LL + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1805 = MULS_DD_LH + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1804 = MULS_DD_HL + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1803 = MULS_DD_HH + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1802 = MULS_DA_LL + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1801 = MULS_DA_LH + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1800 = MULS_DA_HL + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1799 = MULS_DA_HH + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1798 = MULS_AD_LL + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1797 = MULS_AD_LH + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1796 = MULS_AD_HL + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1795 = MULS_AD_HH + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1794 = MULS_AA_LL + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1793 = MULS_AA_LH + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1792 = MULS_AA_HL + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1791 = MULS_AA_HH + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1790 = MULSH + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1789 = MULL + { 5, &XtensaDescs.OperandInfo[849] }, // Inst #1788 = MULA_DD_LL_LDINC + { 5, &XtensaDescs.OperandInfo[849] }, // Inst #1787 = MULA_DD_LL_LDDEC + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1786 = MULA_DD_LL + { 5, &XtensaDescs.OperandInfo[849] }, // Inst #1785 = MULA_DD_LH_LDINC + { 5, &XtensaDescs.OperandInfo[849] }, // Inst #1784 = MULA_DD_LH_LDDEC + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1783 = MULA_DD_LH + { 5, &XtensaDescs.OperandInfo[849] }, // Inst #1782 = MULA_DD_HL_LDINC + { 5, &XtensaDescs.OperandInfo[849] }, // Inst #1781 = MULA_DD_HL_LDDEC + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1780 = MULA_DD_HL + { 5, &XtensaDescs.OperandInfo[849] }, // Inst #1779 = MULA_DD_HH_LDINC + { 5, &XtensaDescs.OperandInfo[849] }, // Inst #1778 = MULA_DD_HH_LDDEC + { 2, &XtensaDescs.OperandInfo[847] }, // Inst #1777 = MULA_DD_HH + { 5, &XtensaDescs.OperandInfo[842] }, // Inst #1776 = MULA_DA_LL_LDINC + { 5, &XtensaDescs.OperandInfo[837] }, // Inst #1775 = MULA_DA_LL_LDDEC + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1774 = MULA_DA_LL + { 5, &XtensaDescs.OperandInfo[842] }, // Inst #1773 = MULA_DA_LH_LDINC + { 5, &XtensaDescs.OperandInfo[837] }, // Inst #1772 = MULA_DA_LH_LDDEC + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1771 = MULA_DA_LH + { 5, &XtensaDescs.OperandInfo[842] }, // Inst #1770 = MULA_DA_HL_LDINC + { 5, &XtensaDescs.OperandInfo[837] }, // Inst #1769 = MULA_DA_HL_LDDEC + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1768 = MULA_DA_HL + { 5, &XtensaDescs.OperandInfo[842] }, // Inst #1767 = MULA_DA_HH_LDINC + { 5, &XtensaDescs.OperandInfo[837] }, // Inst #1766 = MULA_DA_HH_LDDEC + { 2, &XtensaDescs.OperandInfo[835] }, // Inst #1765 = MULA_DA_HH + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1764 = MULA_AD_LL + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1763 = MULA_AD_LH + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1762 = MULA_AD_HL + { 2, &XtensaDescs.OperandInfo[833] }, // Inst #1761 = MULA_AD_HH + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1760 = MULA_AA_LL + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1759 = MULA_AA_LH + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1758 = MULA_AA_HL + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1757 = MULA_AA_HH + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1756 = MUL16U + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1755 = MUL16S + { 4, &XtensaDescs.OperandInfo[817] }, // Inst #1754 = MSUB_S + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #1753 = MOV_S + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1752 = MOV_N + { 4, &XtensaDescs.OperandInfo[829] }, // Inst #1751 = MOVT_S + { 4, &XtensaDescs.OperandInfo[825] }, // Inst #1750 = MOVT + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1749 = MOVSP + { 4, &XtensaDescs.OperandInfo[821] }, // Inst #1748 = MOVNEZ_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1747 = MOVNEZ + { 4, &XtensaDescs.OperandInfo[821] }, // Inst #1746 = MOVLTZ_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1745 = MOVLTZ + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1744 = MOVI_N + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1743 = MOVI + { 4, &XtensaDescs.OperandInfo[821] }, // Inst #1742 = MOVGEZ_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1741 = MOVGEZ + { 4, &XtensaDescs.OperandInfo[829] }, // Inst #1740 = MOVF_S + { 4, &XtensaDescs.OperandInfo[825] }, // Inst #1739 = MOVF + { 4, &XtensaDescs.OperandInfo[821] }, // Inst #1738 = MOVEQZ_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1737 = MOVEQZ + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #1736 = MKSADJ_S + { 3, &XtensaDescs.OperandInfo[343] }, // Inst #1735 = MKDADJ_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1734 = MINU + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1733 = MIN + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1732 = MEMW + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1731 = MAXU + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1730 = MAX + { 4, &XtensaDescs.OperandInfo[817] }, // Inst #1729 = MADD_S + { 4, &XtensaDescs.OperandInfo[817] }, // Inst #1728 = MADDN_S + { 4, &XtensaDescs.OperandInfo[813] }, // Inst #1727 = LSXP + { 3, &XtensaDescs.OperandInfo[810] }, // Inst #1726 = LSX + { 4, &XtensaDescs.OperandInfo[806] }, // Inst #1725 = LSIP + { 3, &XtensaDescs.OperandInfo[803] }, // Inst #1724 = LSI + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1723 = LOOPNEZ + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1722 = LOOPGTZ + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1721 = LOOP + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1720 = LEA_ADD + { 3, &XtensaDescs.OperandInfo[800] }, // Inst #1719 = LDINC + { 3, &XtensaDescs.OperandInfo[800] }, // Inst #1718 = LDDEC + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1717 = L8UI + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1716 = L32R + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1715 = L32I_N + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1714 = L32I + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1713 = L32E + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1712 = L16UI + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #1711 = L16SI + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1710 = JX + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1709 = J + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1708 = ISYNC + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1707 = ILL_N + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1706 = ILL + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1705 = GET_GPIO_IN + { 3, &XtensaDescs.OperandInfo[513] }, // Inst #1704 = FLOOR_S + { 3, &XtensaDescs.OperandInfo[797] }, // Inst #1703 = FLOAT_S + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1702 = EXTW + { 4, &XtensaDescs.OperandInfo[793] }, // Inst #1701 = EXTUI + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1700 = EXCW + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1699 = ESYNC + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1698 = ENTRY + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1697 = EE_ZERO_QACC + { 1, &XtensaDescs.OperandInfo[646] }, // Inst #1696 = EE_ZERO_Q + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1695 = EE_ZERO_ACCX + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1694 = EE_XORQ + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1693 = EE_WR_MASK_GPIO_OUT + { 4, &XtensaDescs.OperandInfo[789] }, // Inst #1692 = EE_VZIP_8 + { 4, &XtensaDescs.OperandInfo[789] }, // Inst #1691 = EE_VZIP_32 + { 4, &XtensaDescs.OperandInfo[789] }, // Inst #1690 = EE_VZIP_16 + { 4, &XtensaDescs.OperandInfo[789] }, // Inst #1689 = EE_VUNZIP_8 + { 4, &XtensaDescs.OperandInfo[789] }, // Inst #1688 = EE_VUNZIP_32 + { 4, &XtensaDescs.OperandInfo[789] }, // Inst #1687 = EE_VUNZIP_16 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1686 = EE_VSUBS_S8_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1685 = EE_VSUBS_S8_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1684 = EE_VSUBS_S8 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1683 = EE_VSUBS_S32_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1682 = EE_VSUBS_S32_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1681 = EE_VSUBS_S32 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1680 = EE_VSUBS_S16_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1679 = EE_VSUBS_S16_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1678 = EE_VSUBS_S16 + { 4, &XtensaDescs.OperandInfo[785] }, // Inst #1677 = EE_VST_L_64_XP + { 4, &XtensaDescs.OperandInfo[593] }, // Inst #1676 = EE_VST_L_64_IP + { 4, &XtensaDescs.OperandInfo[785] }, // Inst #1675 = EE_VST_H_64_XP + { 4, &XtensaDescs.OperandInfo[593] }, // Inst #1674 = EE_VST_H_64_IP + { 4, &XtensaDescs.OperandInfo[785] }, // Inst #1673 = EE_VST_128_XP + { 4, &XtensaDescs.OperandInfo[593] }, // Inst #1672 = EE_VST_128_IP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1671 = EE_VSR_32 + { 6, &XtensaDescs.OperandInfo[779] }, // Inst #1670 = EE_VSMULAS_S8_QACC_LD_INCP + { 3, &XtensaDescs.OperandInfo[776] }, // Inst #1669 = EE_VSMULAS_S8_QACC + { 6, &XtensaDescs.OperandInfo[779] }, // Inst #1668 = EE_VSMULAS_S16_QACC_LD_INCP + { 3, &XtensaDescs.OperandInfo[776] }, // Inst #1667 = EE_VSMULAS_S16_QACC + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1666 = EE_VSL_32 + { 4, &XtensaDescs.OperandInfo[772] }, // Inst #1665 = EE_VRELU_S8 + { 4, &XtensaDescs.OperandInfo[772] }, // Inst #1664 = EE_VRELU_S16 + { 4, &XtensaDescs.OperandInfo[768] }, // Inst #1663 = EE_VPRELU_S8 + { 4, &XtensaDescs.OperandInfo[768] }, // Inst #1662 = EE_VPRELU_S16 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1661 = EE_VMUL_U8_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1660 = EE_VMUL_U8_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1659 = EE_VMUL_U8 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1658 = EE_VMUL_U16_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1657 = EE_VMUL_U16_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1656 = EE_VMUL_U16 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1655 = EE_VMUL_S8_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1654 = EE_VMUL_S8_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1653 = EE_VMUL_S8 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1652 = EE_VMUL_S16_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1651 = EE_VMUL_S16_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1650 = EE_VMUL_S16 + { 9, &XtensaDescs.OperandInfo[746] }, // Inst #1649 = EE_VMULAS_U8_QACC_LD_XP_QUP + { 6, &XtensaDescs.OperandInfo[740] }, // Inst #1648 = EE_VMULAS_U8_QACC_LD_XP + { 9, &XtensaDescs.OperandInfo[731] }, // Inst #1647 = EE_VMULAS_U8_QACC_LD_IP_QUP + { 6, &XtensaDescs.OperandInfo[725] }, // Inst #1646 = EE_VMULAS_U8_QACC_LD_IP + { 8, &XtensaDescs.OperandInfo[760] }, // Inst #1645 = EE_VMULAS_U8_QACC_LDBC_INCP_QUP + { 5, &XtensaDescs.OperandInfo[755] }, // Inst #1644 = EE_VMULAS_U8_QACC_LDBC_INCP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1643 = EE_VMULAS_U8_QACC + { 9, &XtensaDescs.OperandInfo[746] }, // Inst #1642 = EE_VMULAS_U8_ACCX_LD_XP_QUP + { 6, &XtensaDescs.OperandInfo[740] }, // Inst #1641 = EE_VMULAS_U8_ACCX_LD_XP + { 9, &XtensaDescs.OperandInfo[731] }, // Inst #1640 = EE_VMULAS_U8_ACCX_LD_IP_QUP + { 6, &XtensaDescs.OperandInfo[725] }, // Inst #1639 = EE_VMULAS_U8_ACCX_LD_IP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1638 = EE_VMULAS_U8_ACCX + { 9, &XtensaDescs.OperandInfo[746] }, // Inst #1637 = EE_VMULAS_U16_QACC_LD_XP_QUP + { 6, &XtensaDescs.OperandInfo[740] }, // Inst #1636 = EE_VMULAS_U16_QACC_LD_XP + { 9, &XtensaDescs.OperandInfo[731] }, // Inst #1635 = EE_VMULAS_U16_QACC_LD_IP_QUP + { 6, &XtensaDescs.OperandInfo[725] }, // Inst #1634 = EE_VMULAS_U16_QACC_LD_IP + { 8, &XtensaDescs.OperandInfo[760] }, // Inst #1633 = EE_VMULAS_U16_QACC_LDBC_INCP_QUP + { 5, &XtensaDescs.OperandInfo[755] }, // Inst #1632 = EE_VMULAS_U16_QACC_LDBC_INCP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1631 = EE_VMULAS_U16_QACC + { 9, &XtensaDescs.OperandInfo[746] }, // Inst #1630 = EE_VMULAS_U16_ACCX_LD_XP_QUP + { 6, &XtensaDescs.OperandInfo[740] }, // Inst #1629 = EE_VMULAS_U16_ACCX_LD_XP + { 9, &XtensaDescs.OperandInfo[731] }, // Inst #1628 = EE_VMULAS_U16_ACCX_LD_IP_QUP + { 6, &XtensaDescs.OperandInfo[725] }, // Inst #1627 = EE_VMULAS_U16_ACCX_LD_IP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1626 = EE_VMULAS_U16_ACCX + { 9, &XtensaDescs.OperandInfo[746] }, // Inst #1625 = EE_VMULAS_S8_QACC_LD_XP_QUP + { 6, &XtensaDescs.OperandInfo[740] }, // Inst #1624 = EE_VMULAS_S8_QACC_LD_XP + { 9, &XtensaDescs.OperandInfo[731] }, // Inst #1623 = EE_VMULAS_S8_QACC_LD_IP_QUP + { 6, &XtensaDescs.OperandInfo[725] }, // Inst #1622 = EE_VMULAS_S8_QACC_LD_IP + { 8, &XtensaDescs.OperandInfo[760] }, // Inst #1621 = EE_VMULAS_S8_QACC_LDBC_INCP_QUP + { 5, &XtensaDescs.OperandInfo[755] }, // Inst #1620 = EE_VMULAS_S8_QACC_LDBC_INCP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1619 = EE_VMULAS_S8_QACC + { 9, &XtensaDescs.OperandInfo[746] }, // Inst #1618 = EE_VMULAS_S8_ACCX_LD_XP_QUP + { 6, &XtensaDescs.OperandInfo[740] }, // Inst #1617 = EE_VMULAS_S8_ACCX_LD_XP + { 9, &XtensaDescs.OperandInfo[731] }, // Inst #1616 = EE_VMULAS_S8_ACCX_LD_IP_QUP + { 6, &XtensaDescs.OperandInfo[725] }, // Inst #1615 = EE_VMULAS_S8_ACCX_LD_IP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1614 = EE_VMULAS_S8_ACCX + { 9, &XtensaDescs.OperandInfo[746] }, // Inst #1613 = EE_VMULAS_S16_QACC_LD_XP_QUP + { 6, &XtensaDescs.OperandInfo[740] }, // Inst #1612 = EE_VMULAS_S16_QACC_LD_XP + { 9, &XtensaDescs.OperandInfo[731] }, // Inst #1611 = EE_VMULAS_S16_QACC_LD_IP_QUP + { 6, &XtensaDescs.OperandInfo[725] }, // Inst #1610 = EE_VMULAS_S16_QACC_LD_IP + { 8, &XtensaDescs.OperandInfo[760] }, // Inst #1609 = EE_VMULAS_S16_QACC_LDBC_INCP_QUP + { 5, &XtensaDescs.OperandInfo[755] }, // Inst #1608 = EE_VMULAS_S16_QACC_LDBC_INCP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1607 = EE_VMULAS_S16_QACC + { 9, &XtensaDescs.OperandInfo[746] }, // Inst #1606 = EE_VMULAS_S16_ACCX_LD_XP_QUP + { 6, &XtensaDescs.OperandInfo[740] }, // Inst #1605 = EE_VMULAS_S16_ACCX_LD_XP + { 9, &XtensaDescs.OperandInfo[731] }, // Inst #1604 = EE_VMULAS_S16_ACCX_LD_IP_QUP + { 6, &XtensaDescs.OperandInfo[725] }, // Inst #1603 = EE_VMULAS_S16_ACCX_LD_IP + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1602 = EE_VMULAS_S16_ACCX + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1601 = EE_VMIN_S8_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1600 = EE_VMIN_S8_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1599 = EE_VMIN_S8 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1598 = EE_VMIN_S32_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1597 = EE_VMIN_S32_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1596 = EE_VMIN_S32 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1595 = EE_VMIN_S16_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1594 = EE_VMIN_S16_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1593 = EE_VMIN_S16 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1592 = EE_VMAX_S8_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1591 = EE_VMAX_S8_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1590 = EE_VMAX_S8 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1589 = EE_VMAX_S32_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1588 = EE_VMAX_S32_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1587 = EE_VMAX_S32 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1586 = EE_VMAX_S16_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1585 = EE_VMAX_S16_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1584 = EE_VMAX_S16 + { 4, &XtensaDescs.OperandInfo[636] }, // Inst #1583 = EE_VLD_L_64_XP + { 4, &XtensaDescs.OperandInfo[632] }, // Inst #1582 = EE_VLD_L_64_IP + { 4, &XtensaDescs.OperandInfo[636] }, // Inst #1581 = EE_VLD_H_64_XP + { 4, &XtensaDescs.OperandInfo[632] }, // Inst #1580 = EE_VLD_H_64_IP + { 4, &XtensaDescs.OperandInfo[636] }, // Inst #1579 = EE_VLD_128_XP + { 4, &XtensaDescs.OperandInfo[632] }, // Inst #1578 = EE_VLD_128_IP + { 4, &XtensaDescs.OperandInfo[721] }, // Inst #1577 = EE_VLDHBC_16_INCP + { 4, &XtensaDescs.OperandInfo[636] }, // Inst #1576 = EE_VLDBC_8_XP + { 4, &XtensaDescs.OperandInfo[632] }, // Inst #1575 = EE_VLDBC_8_IP + { 2, &XtensaDescs.OperandInfo[719] }, // Inst #1574 = EE_VLDBC_8 + { 4, &XtensaDescs.OperandInfo[636] }, // Inst #1573 = EE_VLDBC_32_XP + { 4, &XtensaDescs.OperandInfo[632] }, // Inst #1572 = EE_VLDBC_32_IP + { 2, &XtensaDescs.OperandInfo[719] }, // Inst #1571 = EE_VLDBC_32 + { 4, &XtensaDescs.OperandInfo[636] }, // Inst #1570 = EE_VLDBC_16_XP + { 4, &XtensaDescs.OperandInfo[632] }, // Inst #1569 = EE_VLDBC_16_IP + { 2, &XtensaDescs.OperandInfo[719] }, // Inst #1568 = EE_VLDBC_16 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1567 = EE_VCMP_LT_S8 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1566 = EE_VCMP_LT_S32 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1565 = EE_VCMP_LT_S16 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1564 = EE_VCMP_GT_S8 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1563 = EE_VCMP_GT_S32 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1562 = EE_VCMP_GT_S16 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1561 = EE_VCMP_EQ_S8 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1560 = EE_VCMP_EQ_S32 + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1559 = EE_VCMP_EQ_S16 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1558 = EE_VADDS_S8_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1557 = EE_VADDS_S8_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1556 = EE_VADDS_S8 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1555 = EE_VADDS_S32_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1554 = EE_VADDS_S32_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1553 = EE_VADDS_S32 + { 6, &XtensaDescs.OperandInfo[713] }, // Inst #1552 = EE_VADDS_S16_ST_INCP + { 6, &XtensaDescs.OperandInfo[707] }, // Inst #1551 = EE_VADDS_S16_LD_INCP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1550 = EE_VADDS_S16 + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1549 = EE_ST_UA_STATE_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1548 = EE_ST_QACC_L_L_128_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1547 = EE_ST_QACC_L_H_32_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1546 = EE_ST_QACC_H_L_128_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1545 = EE_ST_QACC_H_H_32_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1544 = EE_ST_ACCX_IP + { 5, &XtensaDescs.OperandInfo[627] }, // Inst #1543 = EE_STXQ_32 + { 5, &XtensaDescs.OperandInfo[702] }, // Inst #1542 = EE_STF_64_XP + { 5, &XtensaDescs.OperandInfo[697] }, // Inst #1541 = EE_STF_64_IP + { 7, &XtensaDescs.OperandInfo[690] }, // Inst #1540 = EE_STF_128_XP + { 7, &XtensaDescs.OperandInfo[683] }, // Inst #1539 = EE_STF_128_IP + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1538 = EE_SRS_ACCX + { 4, &XtensaDescs.OperandInfo[679] }, // Inst #1537 = EE_SRC_Q_QUP + { 7, &XtensaDescs.OperandInfo[672] }, // Inst #1536 = EE_SRC_Q_LD_XP + { 7, &XtensaDescs.OperandInfo[665] }, // Inst #1535 = EE_SRC_Q_LD_IP + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1534 = EE_SRC_Q + { 7, &XtensaDescs.OperandInfo[654] }, // Inst #1533 = EE_SRCXXP_2Q + { 4, &XtensaDescs.OperandInfo[661] }, // Inst #1532 = EE_SRCQ_128_ST_INCP + { 3, &XtensaDescs.OperandInfo[643] }, // Inst #1531 = EE_SRCMB_S8_QACC + { 3, &XtensaDescs.OperandInfo[643] }, // Inst #1530 = EE_SRCMB_S16_QACC + { 5, &XtensaDescs.OperandInfo[649] }, // Inst #1529 = EE_SRCI_2Q + { 7, &XtensaDescs.OperandInfo[654] }, // Inst #1528 = EE_SLCXXP_2Q + { 5, &XtensaDescs.OperandInfo[649] }, // Inst #1527 = EE_SLCI_2Q + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1526 = EE_SET_BIT_GPIO_OUT + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1525 = EE_ORQ + { 2, &XtensaDescs.OperandInfo[647] }, // Inst #1524 = EE_NOTQ + { 1, &XtensaDescs.OperandInfo[646] }, // Inst #1523 = EE_MOV_U8_QACC + { 1, &XtensaDescs.OperandInfo[646] }, // Inst #1522 = EE_MOV_U16_QACC + { 1, &XtensaDescs.OperandInfo[646] }, // Inst #1521 = EE_MOV_S8_QACC + { 1, &XtensaDescs.OperandInfo[646] }, // Inst #1520 = EE_MOV_S16_QACC + { 3, &XtensaDescs.OperandInfo[643] }, // Inst #1519 = EE_MOVI_32_Q + { 3, &XtensaDescs.OperandInfo[640] }, // Inst #1518 = EE_MOVI_32_A + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1517 = EE_LD_UA_STATE_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1516 = EE_LD_QACC_L_L_128_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1515 = EE_LD_QACC_L_H_32_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1514 = EE_LD_QACC_H_L_128_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1513 = EE_LD_QACC_H_H_32_IP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1512 = EE_LD_ACCX_IP + { 4, &XtensaDescs.OperandInfo[636] }, // Inst #1511 = EE_LD_128_USAR_XP + { 4, &XtensaDescs.OperandInfo[632] }, // Inst #1510 = EE_LD_128_USAR_IP + { 5, &XtensaDescs.OperandInfo[627] }, // Inst #1509 = EE_LDXQ_32 + { 3, &XtensaDescs.OperandInfo[624] }, // Inst #1508 = EE_LDQA_U8_128_XP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1507 = EE_LDQA_U8_128_IP + { 3, &XtensaDescs.OperandInfo[624] }, // Inst #1506 = EE_LDQA_U16_128_XP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1505 = EE_LDQA_U16_128_IP + { 3, &XtensaDescs.OperandInfo[624] }, // Inst #1504 = EE_LDQA_S8_128_XP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1503 = EE_LDQA_S8_128_IP + { 3, &XtensaDescs.OperandInfo[624] }, // Inst #1502 = EE_LDQA_S16_128_XP + { 3, &XtensaDescs.OperandInfo[621] }, // Inst #1501 = EE_LDQA_S16_128_IP + { 5, &XtensaDescs.OperandInfo[616] }, // Inst #1500 = EE_LDF_64_XP + { 5, &XtensaDescs.OperandInfo[611] }, // Inst #1499 = EE_LDF_64_IP + { 7, &XtensaDescs.OperandInfo[604] }, // Inst #1498 = EE_LDF_128_XP + { 7, &XtensaDescs.OperandInfo[597] }, // Inst #1497 = EE_LDF_128_IP + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1496 = EE_GET_GPIO_IN + { 4, &XtensaDescs.OperandInfo[593] }, // Inst #1495 = EE_FFT_VST_R32_DECP + { 6, &XtensaDescs.OperandInfo[587] }, // Inst #1494 = EE_FFT_R2BF_S16_ST_INCP + { 5, &XtensaDescs.OperandInfo[582] }, // Inst #1493 = EE_FFT_R2BF_S16 + { 9, &XtensaDescs.OperandInfo[573] }, // Inst #1492 = EE_FFT_CMUL_S16_ST_XP + { 8, &XtensaDescs.OperandInfo[565] }, // Inst #1491 = EE_FFT_CMUL_S16_LD_XP + { 10, &XtensaDescs.OperandInfo[555] }, // Inst #1490 = EE_FFT_AMS_S16_ST_INCP + { 9, &XtensaDescs.OperandInfo[546] }, // Inst #1489 = EE_FFT_AMS_S16_LD_R32_DECP + { 9, &XtensaDescs.OperandInfo[546] }, // Inst #1488 = EE_FFT_AMS_S16_LD_INCP_UAUP + { 9, &XtensaDescs.OperandInfo[546] }, // Inst #1487 = EE_FFT_AMS_S16_LD_INCP + { 7, &XtensaDescs.OperandInfo[539] }, // Inst #1486 = EE_CMUL_S16_ST_INCP + { 7, &XtensaDescs.OperandInfo[532] }, // Inst #1485 = EE_CMUL_S16_LD_INCP + { 4, &XtensaDescs.OperandInfo[528] }, // Inst #1484 = EE_CMUL_S16 + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1483 = EE_CLR_BIT_GPIO_OUT + { 3, &XtensaDescs.OperandInfo[525] }, // Inst #1482 = EE_BITREV + { 3, &XtensaDescs.OperandInfo[522] }, // Inst #1481 = EE_ANDQ + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #1480 = DSYNC + { 4, &XtensaDescs.OperandInfo[518] }, // Inst #1479 = DIVN_S + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #1478 = DIV0_S + { 2, &XtensaDescs.OperandInfo[516] }, // Inst #1477 = CONST_S + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1476 = CLR_BIT_GPIO_OUT + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1475 = CLAMPS + { 3, &XtensaDescs.OperandInfo[513] }, // Inst #1474 = CEIL_S + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1473 = CALLX8 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1472 = CALLX4 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1471 = CALLX12 + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1470 = CALLX0 + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1469 = CALL8 + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1468 = CALL4 + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1467 = CALL12 + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1466 = CALL0 + { 2, &XtensaDescs.OperandInfo[511] }, // Inst #1465 = BT + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #1464 = BREAK_N + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #1463 = BREAK + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1462 = BNONE + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1461 = BNEZ + { 3, &XtensaDescs.OperandInfo[508] }, // Inst #1460 = BNEI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1459 = BNE + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1458 = BNALL + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1457 = BLTZ + { 3, &XtensaDescs.OperandInfo[508] }, // Inst #1456 = BLTUI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1455 = BLTU + { 3, &XtensaDescs.OperandInfo[508] }, // Inst #1454 = BLTI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1453 = BLT + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1452 = BGEZ + { 3, &XtensaDescs.OperandInfo[508] }, // Inst #1451 = BGEUI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1450 = BGEU + { 3, &XtensaDescs.OperandInfo[508] }, // Inst #1449 = BGEI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1448 = BGE + { 2, &XtensaDescs.OperandInfo[511] }, // Inst #1447 = BF + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #1446 = BEQZ + { 3, &XtensaDescs.OperandInfo[508] }, // Inst #1445 = BEQI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1444 = BEQ + { 3, &XtensaDescs.OperandInfo[508] }, // Inst #1443 = BBSI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1442 = BBS + { 3, &XtensaDescs.OperandInfo[508] }, // Inst #1441 = BBCI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1440 = BBC + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1439 = BANY + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #1438 = BALL + { 2, &XtensaDescs.OperandInfo[503] }, // Inst #1437 = ANY8 + { 2, &XtensaDescs.OperandInfo[503] }, // Inst #1436 = ANY4 + { 3, &XtensaDescs.OperandInfo[505] }, // Inst #1435 = ANDBC + { 3, &XtensaDescs.OperandInfo[505] }, // Inst #1434 = ANDB + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #1433 = AND + { 2, &XtensaDescs.OperandInfo[503] }, // Inst #1432 = ALL8 + { 2, &XtensaDescs.OperandInfo[503] }, // Inst #1431 = ALL4 + { 1, &XtensaDescs.OperandInfo[502] }, // Inst #1430 = AE_ZALIGN64 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1429 = AE_XOR + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1428 = AE_VLES16C_IP + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1427 = AE_VLES16C_IC + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1426 = AE_VLES16C + { 4, &XtensaDescs.OperandInfo[498] }, // Inst #1425 = AE_VLEL32T + { 4, &XtensaDescs.OperandInfo[498] }, // Inst #1424 = AE_VLEL16T + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #1423 = AE_VLDSHT + { 3, &XtensaDescs.OperandInfo[495] }, // Inst #1422 = AE_VLDL32T + { 3, &XtensaDescs.OperandInfo[495] }, // Inst #1421 = AE_VLDL16T + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1420 = AE_VLDL16C_IP + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1419 = AE_VLDL16C_IC + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1418 = AE_VLDL16C + { 4, &XtensaDescs.OperandInfo[481] }, // Inst #1417 = AE_TRUNCI32X2F64S + { 4, &XtensaDescs.OperandInfo[481] }, // Inst #1416 = AE_TRUNCI32F64S_L + { 4, &XtensaDescs.OperandInfo[491] }, // Inst #1415 = AE_TRUNCA32X2F64S + { 4, &XtensaDescs.OperandInfo[491] }, // Inst #1414 = AE_TRUNCA32F64S_L + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1413 = AE_SUBADD32S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1412 = AE_SUBADD32 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1411 = AE_SUB64S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1410 = AE_SUB64 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1409 = AE_SUB32S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1408 = AE_SUB32 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1407 = AE_SUB24S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1406 = AE_SUB16S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1405 = AE_SUB16 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1404 = AE_SRLS64 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1403 = AE_SRLS32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1402 = AE_SRLS24 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1401 = AE_SRLI64 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1400 = AE_SRLI32 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1399 = AE_SRLI24 + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1398 = AE_SRLA64 + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1397 = AE_SRLA32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1396 = AE_SRAS64 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1395 = AE_SRAS32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1394 = AE_SRAS24 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1393 = AE_SRAI64 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1392 = AE_SRAI32R + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1391 = AE_SRAI32 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1390 = AE_SRAI24 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1389 = AE_SRAI16R + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1388 = AE_SRAI16 + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1387 = AE_SRAA64 + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1386 = AE_SRAA32S + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1385 = AE_SRAA32RS + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1384 = AE_SRAA32 + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1383 = AE_SRAA16S + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1382 = AE_SRAA16RS + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1381 = AE_SRA64_32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1380 = AE_SLASSQ56S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1379 = AE_SLASQ56 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1378 = AE_SLAS64S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1377 = AE_SLAS64 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1376 = AE_SLAS32S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1375 = AE_SLAS32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1374 = AE_SLAS24S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1373 = AE_SLAS24 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1372 = AE_SLAISQ56S + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1371 = AE_SLAI64S + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1370 = AE_SLAI64 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1369 = AE_SLAI32S + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1368 = AE_SLAI32 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1367 = AE_SLAI24S + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1366 = AE_SLAI24 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1365 = AE_SLAI16S + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1364 = AE_SLAAQ56 + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1363 = AE_SLAA64S + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1362 = AE_SLAA64 + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1361 = AE_SLAA32S + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1360 = AE_SLAA32 + { 3, &XtensaDescs.OperandInfo[488] }, // Inst #1359 = AE_SLAA16S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1358 = AE_SHORTSWAP + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #1357 = AE_SHA32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1356 = AE_SEXT32X2D16_32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1355 = AE_SEXT32X2D16_10 + { 3, &XtensaDescs.OperandInfo[485] }, // Inst #1354 = AE_SEXT32 + { 4, &XtensaDescs.OperandInfo[481] }, // Inst #1353 = AE_SEL16I_N + { 4, &XtensaDescs.OperandInfo[481] }, // Inst #1352 = AE_SEL16I + { 3, &XtensaDescs.OperandInfo[358] }, // Inst #1351 = AE_SB_IP + { 3, &XtensaDescs.OperandInfo[358] }, // Inst #1350 = AE_SB_IC + { 4, &XtensaDescs.OperandInfo[477] }, // Inst #1349 = AE_SBI_IP + { 4, &XtensaDescs.OperandInfo[477] }, // Inst #1348 = AE_SBI_IC + { 4, &XtensaDescs.OperandInfo[477] }, // Inst #1347 = AE_SBI + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1346 = AE_SBF_IP + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1345 = AE_SBF_IC + { 2, &XtensaDescs.OperandInfo[475] }, // Inst #1344 = AE_SBF + { 3, &XtensaDescs.OperandInfo[358] }, // Inst #1343 = AE_SB + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1342 = AE_SATQ56S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1341 = AE_SAT48S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1340 = AE_SAT24S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1339 = AE_SAT16X4 + { 3, &XtensaDescs.OperandInfo[403] }, // Inst #1338 = AE_SALIGN64_I + { 3, &XtensaDescs.OperandInfo[472] }, // Inst #1337 = AE_SA64POS_FP + { 3, &XtensaDescs.OperandInfo[472] }, // Inst #1336 = AE_SA64NEG_FP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1335 = AE_SA32X2_RIP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1334 = AE_SA32X2_RIC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1333 = AE_SA32X2_IP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1332 = AE_SA32X2_IC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1331 = AE_SA32X2F24_RIP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1330 = AE_SA32X2F24_RIC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1329 = AE_SA32X2F24_IP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1328 = AE_SA32X2F24_IC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1327 = AE_SA24_L_RIP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1326 = AE_SA24_L_RIC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1325 = AE_SA24_L_IP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1324 = AE_SA24_L_IC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1323 = AE_SA24X2_RIP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1322 = AE_SA24X2_RIC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1321 = AE_SA24X2_IP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1320 = AE_SA24X2_IC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1319 = AE_SA16X4_RIP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1318 = AE_SA16X4_RIC + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1317 = AE_SA16X4_IP + { 5, &XtensaDescs.OperandInfo[467] }, // Inst #1316 = AE_SA16X4_IC + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1315 = AE_S64_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1314 = AE_S64_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1313 = AE_S64_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1312 = AE_S64_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1311 = AE_S64_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1310 = AE_S32_L_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1309 = AE_S32_L_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1308 = AE_S32_L_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1307 = AE_S32_L_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1306 = AE_S32_L_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1305 = AE_S32X2_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1304 = AE_S32X2_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1303 = AE_S32X2_X + { 3, &XtensaDescs.OperandInfo[460] }, // Inst #1302 = AE_S32X2_RIP + { 3, &XtensaDescs.OperandInfo[460] }, // Inst #1301 = AE_S32X2_RIC + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1300 = AE_S32X2_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1299 = AE_S32X2_I + { 4, &XtensaDescs.OperandInfo[463] }, // Inst #1298 = AE_S32X2RA64S_IP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1297 = AE_S32X2F24_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1296 = AE_S32X2F24_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1295 = AE_S32X2F24_X + { 3, &XtensaDescs.OperandInfo[460] }, // Inst #1294 = AE_S32X2F24_RIP + { 3, &XtensaDescs.OperandInfo[460] }, // Inst #1293 = AE_S32X2F24_RIC + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1292 = AE_S32X2F24_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1291 = AE_S32X2F24_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1290 = AE_S32RA64S_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1289 = AE_S32RA64S_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1288 = AE_S32RA64S_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1287 = AE_S32RA64S_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1286 = AE_S32RA64S_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1285 = AE_S32M_XU + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1284 = AE_S32M_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1283 = AE_S32M_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1282 = AE_S32M_IU + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1281 = AE_S32M_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1280 = AE_S32F24_L_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1279 = AE_S32F24_L_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1278 = AE_S32F24_L_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1277 = AE_S32F24_L_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1276 = AE_S32F24_L_I + { 4, &XtensaDescs.OperandInfo[463] }, // Inst #1275 = AE_S24X2RA64S_IP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1274 = AE_S24RA64S_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1273 = AE_S24RA64S_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1272 = AE_S24RA64S_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1271 = AE_S24RA64S_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1270 = AE_S24RA64S_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1269 = AE_S16_0_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1268 = AE_S16_0_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1267 = AE_S16_0_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1266 = AE_S16_0_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1265 = AE_S16_0_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1264 = AE_S16X4_XP + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1263 = AE_S16X4_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1262 = AE_S16X4_X + { 3, &XtensaDescs.OperandInfo[460] }, // Inst #1261 = AE_S16X4_RIP + { 3, &XtensaDescs.OperandInfo[460] }, // Inst #1260 = AE_S16X4_RIC + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1259 = AE_S16X4_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1258 = AE_S16X4_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1257 = AE_S16X2M_XU + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1256 = AE_S16X2M_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1255 = AE_S16X2M_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1254 = AE_S16X2M_IU + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1253 = AE_S16X2M_I + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1252 = AE_S16M_L_XU + { 4, &XtensaDescs.OperandInfo[456] }, // Inst #1251 = AE_S16M_L_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #1250 = AE_S16M_L_X + { 4, &XtensaDescs.OperandInfo[452] }, // Inst #1249 = AE_S16M_L_IU + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #1248 = AE_S16M_L_I + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1247 = AE_ROUNDSQ32F48SYM + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1246 = AE_ROUNDSQ32F48ASYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1245 = AE_ROUNDSP16Q48X2SYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1244 = AE_ROUNDSP16Q48X2ASYM + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1243 = AE_ROUNDSP16F24SYM + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1242 = AE_ROUNDSP16F24ASYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1241 = AE_ROUND32X2F64SSYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1240 = AE_ROUND32X2F64SASYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1239 = AE_ROUND32X2F48SSYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1238 = AE_ROUND32X2F48SASYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1237 = AE_ROUND24X2F48SSYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1236 = AE_ROUND24X2F48SASYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1235 = AE_ROUND16X4F32SSYM + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1234 = AE_ROUND16X4F32SASYM + { 4, &XtensaDescs.OperandInfo[448] }, // Inst #1233 = AE_PKSR32 + { 4, &XtensaDescs.OperandInfo[448] }, // Inst #1232 = AE_PKSR24 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1231 = AE_OR + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #1230 = AE_NSAZ32_L + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #1229 = AE_NSAZ16_0 + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #1228 = AE_NSA64 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1227 = AE_NEG64S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1226 = AE_NEG64 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1225 = AE_NEG32S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1224 = AE_NEG32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1223 = AE_NEG24S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #1222 = AE_NEG16S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1221 = AE_NAND + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1220 = AE_MULZSSFD32X16_H3_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1219 = AE_MULZSSFD32X16_H3_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1218 = AE_MULZSSFD32X16_H1_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1217 = AE_MULZSSFD32X16_H1_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1216 = AE_MULZSSFD24_HL_LH_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1215 = AE_MULZSSFD24_HL_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1214 = AE_MULZSSFD24_HH_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1213 = AE_MULZSSFD24_HH_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1212 = AE_MULZSSFD16SS_33_22_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1211 = AE_MULZSSFD16SS_33_22 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1210 = AE_MULZSSFD16SS_13_02_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1209 = AE_MULZSSFD16SS_13_02 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1208 = AE_MULZSSFD16SS_11_00_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1207 = AE_MULZSSFD16SS_11_00 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1206 = AE_MULZSSD32X16_H3_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1205 = AE_MULZSSD32X16_H3_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1204 = AE_MULZSSD32X16_H1_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1203 = AE_MULZSSD32X16_H1_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1202 = AE_MULZSSD24_HL_LH_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1201 = AE_MULZSSD24_HL_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1200 = AE_MULZSSD24_HH_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1199 = AE_MULZSSD24_HH_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1198 = AE_MULZSAFD32X16_H3_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1197 = AE_MULZSAFD32X16_H3_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1196 = AE_MULZSAFD32X16_H1_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1195 = AE_MULZSAFD32X16_H1_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1194 = AE_MULZSAFD24_HH_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1193 = AE_MULZSAFD24_HH_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1192 = AE_MULZSAD32X16_H3_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1191 = AE_MULZSAD32X16_H3_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1190 = AE_MULZSAD32X16_H1_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1189 = AE_MULZSAD32X16_H1_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1188 = AE_MULZSAD24_HH_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1187 = AE_MULZSAD24_HH_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1186 = AE_MULZASFD32X16_H3_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1185 = AE_MULZASFD32X16_H3_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1184 = AE_MULZASFD32X16_H1_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1183 = AE_MULZASFD32X16_H1_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1182 = AE_MULZASFD24_HL_LH_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1181 = AE_MULZASFD24_HL_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1180 = AE_MULZASFD24_HH_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1179 = AE_MULZASFD24_HH_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1178 = AE_MULZASD32X16_H3_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1177 = AE_MULZASD32X16_H3_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1176 = AE_MULZASD32X16_H1_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1175 = AE_MULZASD32X16_H1_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1174 = AE_MULZASD24_HL_LH_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1173 = AE_MULZASD24_HL_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1172 = AE_MULZASD24_HH_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1171 = AE_MULZASD24_HH_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1170 = AE_MULZAAFD32X16_H3_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1169 = AE_MULZAAFD32X16_H3_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1168 = AE_MULZAAFD32X16_H2_L3_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1167 = AE_MULZAAFD32X16_H2_L3 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1166 = AE_MULZAAFD32X16_H1_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1165 = AE_MULZAAFD32X16_H1_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1164 = AE_MULZAAFD32X16_H0_L1_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1163 = AE_MULZAAFD32X16_H0_L1 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1162 = AE_MULZAAFD24_HL_LH_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1161 = AE_MULZAAFD24_HL_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1160 = AE_MULZAAFD24_HH_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1159 = AE_MULZAAFD24_HH_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1158 = AE_MULZAAFD16SS_33_22_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1157 = AE_MULZAAFD16SS_33_22 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1156 = AE_MULZAAFD16SS_13_02_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1155 = AE_MULZAAFD16SS_13_02 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1154 = AE_MULZAAFD16SS_11_00_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1153 = AE_MULZAAFD16SS_11_00 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1152 = AE_MULZAAD32X16_H3_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1151 = AE_MULZAAD32X16_H3_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1150 = AE_MULZAAD32X16_H2_L3_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1149 = AE_MULZAAD32X16_H2_L3 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1148 = AE_MULZAAD32X16_H1_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1147 = AE_MULZAAD32X16_H1_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1146 = AE_MULZAAD32X16_H0_L1_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1145 = AE_MULZAAD32X16_H0_L1 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1144 = AE_MULZAAD24_HL_LH_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1143 = AE_MULZAAD24_HL_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1142 = AE_MULZAAD24_HH_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1141 = AE_MULZAAD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1140 = AE_MULSSFD32X16_H3_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1139 = AE_MULSSFD32X16_H3_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1138 = AE_MULSSFD32X16_H1_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1137 = AE_MULSSFD32X16_H1_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1136 = AE_MULSSFD24_HL_LH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1135 = AE_MULSSFD24_HL_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1134 = AE_MULSSFD24_HH_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1133 = AE_MULSSFD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1132 = AE_MULSSFD16SS_33_22_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1131 = AE_MULSSFD16SS_33_22 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1130 = AE_MULSSFD16SS_13_02_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1129 = AE_MULSSFD16SS_13_02 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1128 = AE_MULSSFD16SS_11_00_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1127 = AE_MULSSFD16SS_11_00 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1126 = AE_MULSSD32X16_H3_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1125 = AE_MULSSD32X16_H3_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1124 = AE_MULSSD32X16_H1_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1123 = AE_MULSSD32X16_H1_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1122 = AE_MULSSD24_HL_LH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1121 = AE_MULSSD24_HL_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1120 = AE_MULSSD24_HH_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1119 = AE_MULSSD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1118 = AE_MULSS32F48P16S_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1117 = AE_MULSS32F48P16S_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1116 = AE_MULSS32F48P16S_LH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1115 = AE_MULSS32F48P16S_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1114 = AE_MULSS32F48P16S_HH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1113 = AE_MULSS32F48P16S_HH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1112 = AE_MULSRFQ32SP24S_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1111 = AE_MULSRFQ32SP24S_H_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1110 = AE_MULSQ32SP16U_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1109 = AE_MULSQ32SP16S_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1108 = AE_MULSP32X2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1107 = AE_MULSP32X16X2_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1106 = AE_MULSP32X16X2_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1105 = AE_MULSP24X2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1104 = AE_MULSP24X2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1103 = AE_MULSFQ32SP24S_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1102 = AE_MULSFQ32SP24S_H_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1101 = AE_MULSFP32X2RS + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1100 = AE_MULSFP32X2RAS + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1099 = AE_MULSFP32X16X2RS_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1098 = AE_MULSFP32X16X2RS_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1097 = AE_MULSFP32X16X2RS_H_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1096 = AE_MULSFP32X16X2RS_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1095 = AE_MULSFP32X16X2RAS_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1094 = AE_MULSFP32X16X2RAS_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1093 = AE_MULSFP32X16X2RAS_H_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1092 = AE_MULSFP32X16X2RAS_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1091 = AE_MULSFP24X2R_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1090 = AE_MULSFP24X2RA_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1089 = AE_MULSFP24X2RA + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1088 = AE_MULSFP24X2R + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1087 = AE_MULSF48Q32SP16U_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1086 = AE_MULSF48Q32SP16U_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1085 = AE_MULSF48Q32SP16S_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1084 = AE_MULSF48Q32SP16S_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1083 = AE_MULSF32X16_L3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1082 = AE_MULSF32X16_L3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1081 = AE_MULSF32X16_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1080 = AE_MULSF32X16_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1079 = AE_MULSF32X16_L1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1078 = AE_MULSF32X16_L1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1077 = AE_MULSF32X16_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1076 = AE_MULSF32X16_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1075 = AE_MULSF32X16_H3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1074 = AE_MULSF32X16_H3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1073 = AE_MULSF32X16_H2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1072 = AE_MULSF32X16_H2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1071 = AE_MULSF32X16_H1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1070 = AE_MULSF32X16_H1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1069 = AE_MULSF32X16_H0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1068 = AE_MULSF32X16_H0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1067 = AE_MULSF32S_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1066 = AE_MULSF32S_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1065 = AE_MULSF32S_HH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1064 = AE_MULSF32R_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1063 = AE_MULSF32R_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1062 = AE_MULSF32R_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1061 = AE_MULSF32R_HH + { 6, &XtensaDescs.OperandInfo[426] }, // Inst #1060 = AE_MULSF16X4SS + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1059 = AE_MULSF16SS_33 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1058 = AE_MULSF16SS_32 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1057 = AE_MULSF16SS_31 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1056 = AE_MULSF16SS_30 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1055 = AE_MULSF16SS_22 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1054 = AE_MULSF16SS_21 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1053 = AE_MULSF16SS_20 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1052 = AE_MULSF16SS_11 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1051 = AE_MULSF16SS_10 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1050 = AE_MULSF16SS_00_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1049 = AE_MULSF16SS_00 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1048 = AE_MULSAFD32X16_H3_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1047 = AE_MULSAFD32X16_H3_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1046 = AE_MULSAFD32X16_H1_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1045 = AE_MULSAFD32X16_H1_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1044 = AE_MULSAFD24_HH_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1043 = AE_MULSAFD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1042 = AE_MULSAD32X16_H3_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1041 = AE_MULSAD32X16_H3_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1040 = AE_MULSAD32X16_H1_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1039 = AE_MULSAD32X16_H1_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1038 = AE_MULSAD24_HH_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1037 = AE_MULSAD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1036 = AE_MULS32_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1035 = AE_MULS32_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1034 = AE_MULS32_HH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1033 = AE_MULS32X16_L3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1032 = AE_MULS32X16_L3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1031 = AE_MULS32X16_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1030 = AE_MULS32X16_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1029 = AE_MULS32X16_L1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1028 = AE_MULS32X16_L1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1027 = AE_MULS32X16_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1026 = AE_MULS32X16_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1025 = AE_MULS32X16_H3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1024 = AE_MULS32X16_H3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1023 = AE_MULS32X16_H2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1022 = AE_MULS32X16_H2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1021 = AE_MULS32X16_H1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1020 = AE_MULS32X16_H1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1019 = AE_MULS32X16_H0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1018 = AE_MULS32X16_H0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #1017 = AE_MULS32U_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1016 = AE_MULS32F48P16S_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1015 = AE_MULS32F48P16S_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1014 = AE_MULS32F48P16S_LH_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1013 = AE_MULS32F48P16S_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1012 = AE_MULS32F48P16S_HH_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1011 = AE_MULS32F48P16S_HH + { 6, &XtensaDescs.OperandInfo[426] }, // Inst #1010 = AE_MULS16X4 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1009 = AE_MULRFQ32SP24S_L_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1008 = AE_MULRFQ32SP24S_H_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1007 = AE_MULQ32SP16U_L_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1006 = AE_MULQ32SP16S_L_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1005 = AE_MULP32X2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1004 = AE_MULP32X16X2_L + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1003 = AE_MULP32X16X2_H + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1002 = AE_MULP24X2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1001 = AE_MULP24X2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #1000 = AE_MULFQ32SP24S_L_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #999 = AE_MULFQ32SP24S_H_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #998 = AE_MULFP32X2RS + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #997 = AE_MULFP32X2RAS + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #996 = AE_MULFP32X16X2RS_L_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #995 = AE_MULFP32X16X2RS_L + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #994 = AE_MULFP32X16X2RS_H_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #993 = AE_MULFP32X16X2RS_H + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #992 = AE_MULFP32X16X2RAS_L_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #991 = AE_MULFP32X16X2RAS_L + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #990 = AE_MULFP32X16X2RAS_H_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #989 = AE_MULFP32X16X2RAS_H + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #988 = AE_MULFP24X2R_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #987 = AE_MULFP24X2RA_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #986 = AE_MULFP24X2RA + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #985 = AE_MULFP24X2R + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #984 = AE_MULFP16X4S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #983 = AE_MULFP16X4RAS + { 5, &XtensaDescs.OperandInfo[443] }, // Inst #982 = AE_MULFD32X16X2_FIR_LL + { 5, &XtensaDescs.OperandInfo[443] }, // Inst #981 = AE_MULFD32X16X2_FIR_LH + { 5, &XtensaDescs.OperandInfo[443] }, // Inst #980 = AE_MULFD32X16X2_FIR_HL + { 5, &XtensaDescs.OperandInfo[443] }, // Inst #979 = AE_MULFD32X16X2_FIR_HH + { 5, &XtensaDescs.OperandInfo[443] }, // Inst #978 = AE_MULFD24X2_FIR_L + { 5, &XtensaDescs.OperandInfo[443] }, // Inst #977 = AE_MULFD24X2_FIR_H + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #976 = AE_MULFC32X16RAS_L + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #975 = AE_MULFC32X16RAS_H + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #974 = AE_MULFC24RA + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #973 = AE_MULF48Q32SP16U_L_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #972 = AE_MULF48Q32SP16U_L + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #971 = AE_MULF48Q32SP16S_L_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #970 = AE_MULF48Q32SP16S_L + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #969 = AE_MULF32X16_L3_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #968 = AE_MULF32X16_L3 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #967 = AE_MULF32X16_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #966 = AE_MULF32X16_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #965 = AE_MULF32X16_L1_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #964 = AE_MULF32X16_L1 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #963 = AE_MULF32X16_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #962 = AE_MULF32X16_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #961 = AE_MULF32X16_H3_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #960 = AE_MULF32X16_H3 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #959 = AE_MULF32X16_H2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #958 = AE_MULF32X16_H2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #957 = AE_MULF32X16_H1_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #956 = AE_MULF32X16_H1 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #955 = AE_MULF32X16_H0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #954 = AE_MULF32X16_H0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #953 = AE_MULF32S_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #952 = AE_MULF32S_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #951 = AE_MULF32S_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #950 = AE_MULF32S_HH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #949 = AE_MULF32R_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #948 = AE_MULF32R_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #947 = AE_MULF32R_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #946 = AE_MULF32R_HH + { 4, &XtensaDescs.OperandInfo[422] }, // Inst #945 = AE_MULF16X4SS + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #944 = AE_MULF16SS_33 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #943 = AE_MULF16SS_32 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #942 = AE_MULF16SS_31 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #941 = AE_MULF16SS_30 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #940 = AE_MULF16SS_22 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #939 = AE_MULF16SS_21 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #938 = AE_MULF16SS_20 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #937 = AE_MULF16SS_11 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #936 = AE_MULF16SS_10 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #935 = AE_MULF16SS_00_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #934 = AE_MULF16SS_00 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #933 = AE_MULC32X16_L + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #932 = AE_MULC32X16_H + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #931 = AE_MULC24 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #930 = AE_MULASFD32X16_H3_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #929 = AE_MULASFD32X16_H3_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #928 = AE_MULASFD32X16_H1_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #927 = AE_MULASFD32X16_H1_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #926 = AE_MULASFD24_HL_LH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #925 = AE_MULASFD24_HL_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #924 = AE_MULASFD24_HH_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #923 = AE_MULASFD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #922 = AE_MULASD32X16_H3_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #921 = AE_MULASD32X16_H3_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #920 = AE_MULASD32X16_H1_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #919 = AE_MULASD32X16_H1_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #918 = AE_MULASD24_HL_LH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #917 = AE_MULASD24_HL_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #916 = AE_MULASD24_HH_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #915 = AE_MULASD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #914 = AE_MULAS32F48P16S_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #913 = AE_MULAS32F48P16S_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #912 = AE_MULAS32F48P16S_LH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #911 = AE_MULAS32F48P16S_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #910 = AE_MULAS32F48P16S_HH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #909 = AE_MULAS32F48P16S_HH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #908 = AE_MULARFQ32SP24S_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #907 = AE_MULARFQ32SP24S_H_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #906 = AE_MULAQ32SP16U_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #905 = AE_MULAQ32SP16S_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #904 = AE_MULAP32X2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #903 = AE_MULAP32X16X2_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #902 = AE_MULAP32X16X2_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #901 = AE_MULAP24X2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #900 = AE_MULAP24X2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #899 = AE_MULAFQ32SP24S_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #898 = AE_MULAFQ32SP24S_H_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #897 = AE_MULAFP32X2RS + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #896 = AE_MULAFP32X2RAS + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #895 = AE_MULAFP32X16X2RS_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #894 = AE_MULAFP32X16X2RS_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #893 = AE_MULAFP32X16X2RS_H_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #892 = AE_MULAFP32X16X2RS_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #891 = AE_MULAFP32X16X2RAS_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #890 = AE_MULAFP32X16X2RAS_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #889 = AE_MULAFP32X16X2RAS_H_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #888 = AE_MULAFP32X16X2RAS_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #887 = AE_MULAFP24X2R_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #886 = AE_MULAFP24X2RA_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #885 = AE_MULAFP24X2RA + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #884 = AE_MULAFP24X2R + { 7, &XtensaDescs.OperandInfo[436] }, // Inst #883 = AE_MULAFD32X16X2_FIR_LL + { 7, &XtensaDescs.OperandInfo[436] }, // Inst #882 = AE_MULAFD32X16X2_FIR_LH + { 7, &XtensaDescs.OperandInfo[436] }, // Inst #881 = AE_MULAFD32X16X2_FIR_HL + { 7, &XtensaDescs.OperandInfo[436] }, // Inst #880 = AE_MULAFD32X16X2_FIR_HH + { 7, &XtensaDescs.OperandInfo[436] }, // Inst #879 = AE_MULAFD24X2_FIR_L + { 7, &XtensaDescs.OperandInfo[436] }, // Inst #878 = AE_MULAFD24X2_FIR_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #877 = AE_MULAFC32X16RAS_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #876 = AE_MULAFC32X16RAS_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #875 = AE_MULAFC24RA + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #874 = AE_MULAF48Q32SP16U_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #873 = AE_MULAF48Q32SP16U_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #872 = AE_MULAF48Q32SP16S_L_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #871 = AE_MULAF48Q32SP16S_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #870 = AE_MULAF32X16_L3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #869 = AE_MULAF32X16_L3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #868 = AE_MULAF32X16_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #867 = AE_MULAF32X16_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #866 = AE_MULAF32X16_L1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #865 = AE_MULAF32X16_L1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #864 = AE_MULAF32X16_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #863 = AE_MULAF32X16_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #862 = AE_MULAF32X16_H3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #861 = AE_MULAF32X16_H3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #860 = AE_MULAF32X16_H2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #859 = AE_MULAF32X16_H2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #858 = AE_MULAF32X16_H1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #857 = AE_MULAF32X16_H1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #856 = AE_MULAF32X16_H0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #855 = AE_MULAF32X16_H0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #854 = AE_MULAF32S_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #853 = AE_MULAF32S_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #852 = AE_MULAF32S_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #851 = AE_MULAF32S_HH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #850 = AE_MULAF32R_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #849 = AE_MULAF32R_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #848 = AE_MULAF32R_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #847 = AE_MULAF32R_HH + { 6, &XtensaDescs.OperandInfo[426] }, // Inst #846 = AE_MULAF16X4SS + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #845 = AE_MULAF16SS_33 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #844 = AE_MULAF16SS_32 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #843 = AE_MULAF16SS_31 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #842 = AE_MULAF16SS_30 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #841 = AE_MULAF16SS_22 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #840 = AE_MULAF16SS_21 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #839 = AE_MULAF16SS_20 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #838 = AE_MULAF16SS_11 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #837 = AE_MULAF16SS_10 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #836 = AE_MULAF16SS_00_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #835 = AE_MULAF16SS_00 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #834 = AE_MULAC32X16_L + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #833 = AE_MULAC32X16_H + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #832 = AE_MULAC24 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #831 = AE_MULAAFD32X16_H3_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #830 = AE_MULAAFD32X16_H3_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #829 = AE_MULAAFD32X16_H2_L3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #828 = AE_MULAAFD32X16_H2_L3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #827 = AE_MULAAFD32X16_H1_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #826 = AE_MULAAFD32X16_H1_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #825 = AE_MULAAFD32X16_H0_L1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #824 = AE_MULAAFD32X16_H0_L1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #823 = AE_MULAAFD24_HL_LH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #822 = AE_MULAAFD24_HL_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #821 = AE_MULAAFD24_HH_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #820 = AE_MULAAFD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #819 = AE_MULAAFD16SS_33_22_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #818 = AE_MULAAFD16SS_33_22 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #817 = AE_MULAAFD16SS_13_02_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #816 = AE_MULAAFD16SS_13_02 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #815 = AE_MULAAFD16SS_11_00_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #814 = AE_MULAAFD16SS_11_00 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #813 = AE_MULAAD32X16_H3_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #812 = AE_MULAAD32X16_H3_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #811 = AE_MULAAD32X16_H2_L3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #810 = AE_MULAAD32X16_H2_L3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #809 = AE_MULAAD32X16_H1_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #808 = AE_MULAAD32X16_H1_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #807 = AE_MULAAD32X16_H0_L1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #806 = AE_MULAAD32X16_H0_L1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #805 = AE_MULAAD24_HL_LH_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #804 = AE_MULAAD24_HL_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #803 = AE_MULAAD24_HH_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #802 = AE_MULAAD24_HH_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #801 = AE_MULA32_LL_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #800 = AE_MULA32_LL + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #799 = AE_MULA32_LH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #798 = AE_MULA32_HH + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #797 = AE_MULA32X16_L3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #796 = AE_MULA32X16_L3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #795 = AE_MULA32X16_L2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #794 = AE_MULA32X16_L2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #793 = AE_MULA32X16_L1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #792 = AE_MULA32X16_L1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #791 = AE_MULA32X16_L0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #790 = AE_MULA32X16_L0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #789 = AE_MULA32X16_H3_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #788 = AE_MULA32X16_H3 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #787 = AE_MULA32X16_H2_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #786 = AE_MULA32X16_H2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #785 = AE_MULA32X16_H1_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #784 = AE_MULA32X16_H1 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #783 = AE_MULA32X16_H0_S2 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #782 = AE_MULA32X16_H0 + { 4, &XtensaDescs.OperandInfo[432] }, // Inst #781 = AE_MULA32U_LL + { 6, &XtensaDescs.OperandInfo[426] }, // Inst #780 = AE_MULA16X4 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #779 = AE_MUL32_LL_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #778 = AE_MUL32_LL + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #777 = AE_MUL32_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #776 = AE_MUL32_HH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #775 = AE_MUL32X16_L3_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #774 = AE_MUL32X16_L3 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #773 = AE_MUL32X16_L2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #772 = AE_MUL32X16_L2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #771 = AE_MUL32X16_L1_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #770 = AE_MUL32X16_L1 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #769 = AE_MUL32X16_L0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #768 = AE_MUL32X16_L0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #767 = AE_MUL32X16_H3_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #766 = AE_MUL32X16_H3 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #765 = AE_MUL32X16_H2_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #764 = AE_MUL32X16_H2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #763 = AE_MUL32X16_H1_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #762 = AE_MUL32X16_H1 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #761 = AE_MUL32X16_H0_S2 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #760 = AE_MUL32X16_H0 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #759 = AE_MUL32U_LL + { 4, &XtensaDescs.OperandInfo[422] }, // Inst #758 = AE_MUL16X4 + { 4, &XtensaDescs.OperandInfo[416] }, // Inst #757 = AE_MOVT64 + { 4, &XtensaDescs.OperandInfo[412] }, // Inst #756 = AE_MOVT32X2 + { 4, &XtensaDescs.OperandInfo[408] }, // Inst #755 = AE_MOVT16X4 + { 2, &XtensaDescs.OperandInfo[420] }, // Inst #754 = AE_MOVI + { 4, &XtensaDescs.OperandInfo[416] }, // Inst #753 = AE_MOVF64 + { 4, &XtensaDescs.OperandInfo[412] }, // Inst #752 = AE_MOVF32X2 + { 4, &XtensaDescs.OperandInfo[408] }, // Inst #751 = AE_MOVF16X4 + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #750 = AE_MOVDA32X2 + { 2, &XtensaDescs.OperandInfo[354] }, // Inst #749 = AE_MOVDA32 + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #748 = AE_MOVDA16X2 + { 2, &XtensaDescs.OperandInfo[354] }, // Inst #747 = AE_MOVDA16 + { 2, &XtensaDescs.OperandInfo[406] }, // Inst #746 = AE_MOVALIGN + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #745 = AE_MOVAD32_L + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #744 = AE_MOVAD32_H + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #743 = AE_MOVAD16_3 + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #742 = AE_MOVAD16_2 + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #741 = AE_MOVAD16_1 + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #740 = AE_MOVAD16_0 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #739 = AE_MOV + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #738 = AE_MINABS64S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #737 = AE_MINABS32S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #736 = AE_MIN64 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #735 = AE_MIN32 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #734 = AE_MAXABS64S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #733 = AE_MAXABS32S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #732 = AE_MAX64 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #731 = AE_MAX32 + { 3, &XtensaDescs.OperandInfo[373] }, // Inst #730 = AE_LT64 + { 3, &XtensaDescs.OperandInfo[370] }, // Inst #729 = AE_LT32 + { 3, &XtensaDescs.OperandInfo[367] }, // Inst #728 = AE_LT16 + { 3, &XtensaDescs.OperandInfo[373] }, // Inst #727 = AE_LE64 + { 3, &XtensaDescs.OperandInfo[370] }, // Inst #726 = AE_LE32 + { 3, &XtensaDescs.OperandInfo[367] }, // Inst #725 = AE_LE16 + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #724 = AE_LBSI + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #723 = AE_LBS + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #722 = AE_LBKI + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #721 = AE_LBK + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #720 = AE_LBI + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #719 = AE_LB + { 3, &XtensaDescs.OperandInfo[403] }, // Inst #718 = AE_LALIGN64_I + { 2, &XtensaDescs.OperandInfo[401] }, // Inst #717 = AE_LA64_PP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #716 = AE_LA32X2_RIP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #715 = AE_LA32X2_RIC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #714 = AE_LA32X2_IP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #713 = AE_LA32X2_IC + { 3, &XtensaDescs.OperandInfo[393] }, // Inst #712 = AE_LA32X2POS_PC + { 3, &XtensaDescs.OperandInfo[393] }, // Inst #711 = AE_LA32X2NEG_PC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #710 = AE_LA32X2F24_RIP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #709 = AE_LA32X2F24_RIC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #708 = AE_LA32X2F24_IP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #707 = AE_LA32X2F24_IC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #706 = AE_LA24_RIP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #705 = AE_LA24_RIC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #704 = AE_LA24_IP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #703 = AE_LA24_IC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #702 = AE_LA24X2_RIP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #701 = AE_LA24X2_RIC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #700 = AE_LA24X2_IP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #699 = AE_LA24X2_IC + { 3, &XtensaDescs.OperandInfo[393] }, // Inst #698 = AE_LA24X2POS_PC + { 3, &XtensaDescs.OperandInfo[393] }, // Inst #697 = AE_LA24X2NEG_PC + { 3, &XtensaDescs.OperandInfo[393] }, // Inst #696 = AE_LA24POS_PC + { 3, &XtensaDescs.OperandInfo[393] }, // Inst #695 = AE_LA24NEG_PC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #694 = AE_LA16X4_RIP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #693 = AE_LA16X4_RIC + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #692 = AE_LA16X4_IP + { 5, &XtensaDescs.OperandInfo[396] }, // Inst #691 = AE_LA16X4_IC + { 3, &XtensaDescs.OperandInfo[393] }, // Inst #690 = AE_LA16X4POS_PC + { 3, &XtensaDescs.OperandInfo[393] }, // Inst #689 = AE_LA16X4NEG_PC + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #688 = AE_L64_XP + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #687 = AE_L64_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #686 = AE_L64_X + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #685 = AE_L64_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #684 = AE_L64_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #683 = AE_L32_XP + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #682 = AE_L32_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #681 = AE_L32_X + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #680 = AE_L32_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #679 = AE_L32_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #678 = AE_L32X2_XP + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #677 = AE_L32X2_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #676 = AE_L32X2_X + { 3, &XtensaDescs.OperandInfo[390] }, // Inst #675 = AE_L32X2_RIP + { 3, &XtensaDescs.OperandInfo[390] }, // Inst #674 = AE_L32X2_RIC + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #673 = AE_L32X2_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #672 = AE_L32X2_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #671 = AE_L32X2F24_XP + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #670 = AE_L32X2F24_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #669 = AE_L32X2F24_X + { 3, &XtensaDescs.OperandInfo[390] }, // Inst #668 = AE_L32X2F24_RIP + { 3, &XtensaDescs.OperandInfo[390] }, // Inst #667 = AE_L32X2F24_RIC + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #666 = AE_L32X2F24_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #665 = AE_L32X2F24_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #664 = AE_L32M_XU + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #663 = AE_L32M_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #662 = AE_L32M_X + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #661 = AE_L32M_IU + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #660 = AE_L32M_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #659 = AE_L32F24_XP + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #658 = AE_L32F24_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #657 = AE_L32F24_X + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #656 = AE_L32F24_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #655 = AE_L32F24_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #654 = AE_L16_XP + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #653 = AE_L16_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #652 = AE_L16_X + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #651 = AE_L16_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #650 = AE_L16_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #649 = AE_L16X4_XP + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #648 = AE_L16X4_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #647 = AE_L16X4_X + { 3, &XtensaDescs.OperandInfo[390] }, // Inst #646 = AE_L16X4_RIP + { 3, &XtensaDescs.OperandInfo[390] }, // Inst #645 = AE_L16X4_RIC + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #644 = AE_L16X4_IP + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #643 = AE_L16X4_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #642 = AE_L16X2M_XU + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #641 = AE_L16X2M_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #640 = AE_L16X2M_X + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #639 = AE_L16X2M_IU + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #638 = AE_L16X2M_I + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #637 = AE_L16M_XU + { 4, &XtensaDescs.OperandInfo[386] }, // Inst #636 = AE_L16M_XC + { 3, &XtensaDescs.OperandInfo[383] }, // Inst #635 = AE_L16M_X + { 4, &XtensaDescs.OperandInfo[379] }, // Inst #634 = AE_L16M_IU + { 3, &XtensaDescs.OperandInfo[376] }, // Inst #633 = AE_L16M_I + { 3, &XtensaDescs.OperandInfo[373] }, // Inst #632 = AE_EQ64 + { 3, &XtensaDescs.OperandInfo[370] }, // Inst #631 = AE_EQ32 + { 3, &XtensaDescs.OperandInfo[367] }, // Inst #630 = AE_EQ16 + { 3, &XtensaDescs.OperandInfo[364] }, // Inst #629 = AE_DIV64D32_L + { 3, &XtensaDescs.OperandInfo[364] }, // Inst #628 = AE_DIV64D32_H + { 3, &XtensaDescs.OperandInfo[358] }, // Inst #627 = AE_DB_IP + { 3, &XtensaDescs.OperandInfo[358] }, // Inst #626 = AE_DB_IC + { 3, &XtensaDescs.OperandInfo[361] }, // Inst #625 = AE_DBI_IP + { 3, &XtensaDescs.OperandInfo[361] }, // Inst #624 = AE_DBI_IC + { 3, &XtensaDescs.OperandInfo[361] }, // Inst #623 = AE_DBI + { 3, &XtensaDescs.OperandInfo[358] }, // Inst #622 = AE_DB + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #621 = AE_CVTQ56P32S_L + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #620 = AE_CVTQ56P32S_H + { 2, &XtensaDescs.OperandInfo[354] }, // Inst #619 = AE_CVTQ56A32S + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #618 = AE_CVTA32F24S_L + { 2, &XtensaDescs.OperandInfo[356] }, // Inst #617 = AE_CVTA32F24S_H + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #616 = AE_CVT64F32_H + { 2, &XtensaDescs.OperandInfo[354] }, // Inst #615 = AE_CVT64A32 + { 2, &XtensaDescs.OperandInfo[354] }, // Inst #614 = AE_CVT48A32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #613 = AE_CVT32X2F16_32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #612 = AE_CVT32X2F16_10 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #611 = AE_AND + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #610 = AE_ADDSUB32S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #609 = AE_ADDSUB32 + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #608 = AE_ADDBRBA32 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #607 = AE_ADD64S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #606 = AE_ADD64 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #605 = AE_ADD32_HL_LH + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #604 = AE_ADD32S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #603 = AE_ADD32 + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #602 = AE_ADD24S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #601 = AE_ADD16S + { 3, &XtensaDescs.OperandInfo[351] }, // Inst #600 = AE_ADD16 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #599 = AE_ABS64S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #598 = AE_ABS64 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #597 = AE_ABS32S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #596 = AE_ABS32 + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #595 = AE_ABS24S + { 2, &XtensaDescs.OperandInfo[349] }, // Inst #594 = AE_ABS16S + { 3, &XtensaDescs.OperandInfo[346] }, // Inst #593 = ADD_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #592 = ADD_N + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #591 = ADDX8 + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #590 = ADDX4 + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #589 = ADDX2 + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #588 = ADDMI + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #587 = ADDI_N + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #586 = ADDI + { 3, &XtensaDescs.OperandInfo[343] }, // Inst #585 = ADDEXP_S + { 3, &XtensaDescs.OperandInfo[343] }, // Inst #584 = ADDEXPM_S + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #583 = ADD + { 2, &XtensaDescs.OperandInfo[341] }, // Inst #582 = ABS_S + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #581 = ABS + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #580 = mv_QR_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #579 = XSR_M3_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #578 = XSR_M2_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #577 = XSR_M1_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #576 = XSR_M0_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #575 = XSR_ACCLO_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #574 = XSR_ACCHI_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #573 = WSR_M3_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #572 = WSR_M2_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #571 = WSR_M1_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #570 = WSR_M0_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #569 = WSR_ACCLO_P + { 1, &XtensaDescs.OperandInfo[340] }, // Inst #568 = WSR_ACCHI_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #567 = SRL_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #566 = SRA_P + { 3, &XtensaDescs.OperandInfo[313] }, // Inst #565 = SPILL_BOOL + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #564 = SLL_P + { 3, &XtensaDescs.OperandInfo[285] }, // Inst #563 = SLLI_BR_P + { 6, &XtensaDescs.OperandInfo[334] }, // Inst #562 = SELECT_CC_INT_FP + { 6, &XtensaDescs.OperandInfo[328] }, // Inst #561 = SELECT_CC_FP_INT + { 6, &XtensaDescs.OperandInfo[322] }, // Inst #560 = SELECT_CC_FP_FP + { 6, &XtensaDescs.OperandInfo[316] }, // Inst #559 = SELECT + { 3, &XtensaDescs.OperandInfo[313] }, // Inst #558 = RESTORE_BOOL + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #557 = MULA_DD_LL_LDINC_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #556 = MULA_DD_LL_LDDEC_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #555 = MULA_DD_LH_LDINC_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #554 = MULA_DD_LH_LDDEC_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #553 = MULA_DD_HL_LDINC_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #552 = MULA_DD_HL_LDDEC_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #551 = MULA_DD_HH_LDINC_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #550 = MULA_DD_HH_LDDEC_P + { 4, &XtensaDescs.OperandInfo[309] }, // Inst #549 = MULA_DA_LL_LDINC_P + { 4, &XtensaDescs.OperandInfo[309] }, // Inst #548 = MULA_DA_LL_LDDEC_P + { 4, &XtensaDescs.OperandInfo[309] }, // Inst #547 = MULA_DA_LH_LDINC_P + { 4, &XtensaDescs.OperandInfo[309] }, // Inst #546 = MULA_DA_LH_LDDEC_P + { 4, &XtensaDescs.OperandInfo[309] }, // Inst #545 = MULA_DA_HL_LDINC_P + { 4, &XtensaDescs.OperandInfo[309] }, // Inst #544 = MULA_DA_HL_LDDEC_P + { 4, &XtensaDescs.OperandInfo[309] }, // Inst #543 = MULA_DA_HH_LDINC_P + { 4, &XtensaDescs.OperandInfo[309] }, // Inst #542 = MULA_DA_HH_LDDEC_P + { 4, &XtensaDescs.OperandInfo[305] }, // Inst #541 = MOVBA_P2 + { 2, &XtensaDescs.OperandInfo[303] }, // Inst #540 = MOVBA_P + { 4, &XtensaDescs.OperandInfo[299] }, // Inst #539 = MOVBA4_P2 + { 2, &XtensaDescs.OperandInfo[297] }, // Inst #538 = MOVBA4_P + { 4, &XtensaDescs.OperandInfo[293] }, // Inst #537 = MOVBA2_P2 + { 2, &XtensaDescs.OperandInfo[291] }, // Inst #536 = MOVBA2_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #535 = LOOPSTART + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #534 = LOOPINIT + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #533 = LOOPEND + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #532 = LOOPDEC + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #531 = LOOPBR + { 2, &XtensaDescs.OperandInfo[156] }, // Inst #530 = LDINC_P + { 2, &XtensaDescs.OperandInfo[156] }, // Inst #529 = LDDEC_P + { 3, &XtensaDescs.OperandInfo[288] }, // Inst #528 = L8I_P + { 3, &XtensaDescs.OperandInfo[285] }, // Inst #527 = EXTUI_BR_P + { 3, &XtensaDescs.OperandInfo[282] }, // Inst #526 = EXTUI_BR4_P + { 3, &XtensaDescs.OperandInfo[279] }, // Inst #525 = EXTUI_BR2_P + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #524 = EE_ZERO_Q_P + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #523 = EE_ZERO_QACC_P + { 0, &XtensaDescs.OperandInfo[1] }, // Inst #522 = EE_ZERO_ACCX_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #521 = EE_XORQ_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #520 = EE_VZIP_8_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #519 = EE_VZIP_32_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #518 = EE_VZIP_16_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #517 = EE_VUNZIP_8_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #516 = EE_VUNZIP_32_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #515 = EE_VUNZIP_16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #514 = EE_VSUBS_S8_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #513 = EE_VSUBS_S8_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #512 = EE_VSUBS_S8_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #511 = EE_VSUBS_S32_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #510 = EE_VSUBS_S32_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #509 = EE_VSUBS_S32_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #508 = EE_VSUBS_S16_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #507 = EE_VSUBS_S16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #506 = EE_VSUBS_S16_LD_INCP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #505 = EE_VST_L_64_XP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #504 = EE_VST_L_64_IP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #503 = EE_VST_H_64_XP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #502 = EE_VST_H_64_IP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #501 = EE_VST_128_XP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #500 = EE_VST_128_IP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #499 = EE_VSR_32_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #498 = EE_VSMULAS_S8_QACC_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #497 = EE_VSMULAS_S8_QACC_LD_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #496 = EE_VSMULAS_S16_QACC_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #495 = EE_VSMULAS_S16_QACC_LD_INCP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #494 = EE_VSL_32_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #493 = EE_VRELU_S8_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #492 = EE_VRELU_S16_P + { 4, &XtensaDescs.OperandInfo[275] }, // Inst #491 = EE_VPRELU_S8_P + { 4, &XtensaDescs.OperandInfo[275] }, // Inst #490 = EE_VPRELU_S16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #489 = EE_VMUL_U8_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #488 = EE_VMUL_U8_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #487 = EE_VMUL_U8_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #486 = EE_VMUL_U16_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #485 = EE_VMUL_U16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #484 = EE_VMUL_U16_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #483 = EE_VMUL_S8_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #482 = EE_VMUL_S8_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #481 = EE_VMUL_S8_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #480 = EE_VMUL_S16_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #479 = EE_VMUL_S16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #478 = EE_VMUL_S16_LD_INCP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #477 = EE_VMULAS_U8_QACC_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #476 = EE_VMULAS_U8_QACC_LD_XP_QUP_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #475 = EE_VMULAS_U8_QACC_LD_XP_P + { 7, &XtensaDescs.OperandInfo[264] }, // Inst #474 = EE_VMULAS_U8_QACC_LD_IP_QUP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #473 = EE_VMULAS_U8_QACC_LD_IP_P + { 6, &XtensaDescs.OperandInfo[158] }, // Inst #472 = EE_VMULAS_U8_QACC_LDBC_INCP_QUP_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #471 = EE_VMULAS_U8_QACC_LDBC_INCP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #470 = EE_VMULAS_U8_ACCX_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #469 = EE_VMULAS_U8_ACCX_LD_XP_QUP_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #468 = EE_VMULAS_U8_ACCX_LD_XP_P + { 7, &XtensaDescs.OperandInfo[264] }, // Inst #467 = EE_VMULAS_U8_ACCX_LD_IP_QUP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #466 = EE_VMULAS_U8_ACCX_LD_IP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #465 = EE_VMULAS_U16_QACC_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #464 = EE_VMULAS_U16_QACC_LD_XP_QUP_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #463 = EE_VMULAS_U16_QACC_LD_XP_P + { 7, &XtensaDescs.OperandInfo[264] }, // Inst #462 = EE_VMULAS_U16_QACC_LD_IP_QUP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #461 = EE_VMULAS_U16_QACC_LD_IP_P + { 6, &XtensaDescs.OperandInfo[158] }, // Inst #460 = EE_VMULAS_U16_QACC_LDBC_INCP_QUP_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #459 = EE_VMULAS_U16_QACC_LDBC_INCP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #458 = EE_VMULAS_U16_ACCX_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #457 = EE_VMULAS_U16_ACCX_LD_XP_QUP_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #456 = EE_VMULAS_U16_ACCX_LD_XP_P + { 7, &XtensaDescs.OperandInfo[264] }, // Inst #455 = EE_VMULAS_U16_ACCX_LD_IP_QUP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #454 = EE_VMULAS_U16_ACCX_LD_IP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #453 = EE_VMULAS_S8_QACC_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #452 = EE_VMULAS_S8_QACC_LD_XP_QUP_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #451 = EE_VMULAS_S8_QACC_LD_XP_P + { 7, &XtensaDescs.OperandInfo[264] }, // Inst #450 = EE_VMULAS_S8_QACC_LD_IP_QUP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #449 = EE_VMULAS_S8_QACC_LD_IP_P + { 6, &XtensaDescs.OperandInfo[158] }, // Inst #448 = EE_VMULAS_S8_QACC_LDBC_INCP_QUP_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #447 = EE_VMULAS_S8_QACC_LDBC_INCP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #446 = EE_VMULAS_S8_ACCX_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #445 = EE_VMULAS_S8_ACCX_LD_XP_QUP_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #444 = EE_VMULAS_S8_ACCX_LD_XP_P + { 7, &XtensaDescs.OperandInfo[264] }, // Inst #443 = EE_VMULAS_S8_ACCX_LD_IP_QUP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #442 = EE_VMULAS_S8_ACCX_LD_IP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #441 = EE_VMULAS_S16_QACC_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #440 = EE_VMULAS_S16_QACC_LD_XP_QUP_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #439 = EE_VMULAS_S16_QACC_LD_XP_P + { 7, &XtensaDescs.OperandInfo[264] }, // Inst #438 = EE_VMULAS_S16_QACC_LD_IP_QUP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #437 = EE_VMULAS_S16_QACC_LD_IP_P + { 6, &XtensaDescs.OperandInfo[158] }, // Inst #436 = EE_VMULAS_S16_QACC_LDBC_INCP_QUP_P + { 4, &XtensaDescs.OperandInfo[271] }, // Inst #435 = EE_VMULAS_S16_QACC_LDBC_INCP_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #434 = EE_VMULAS_S16_ACCX_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #433 = EE_VMULAS_S16_ACCX_LD_XP_QUP_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #432 = EE_VMULAS_S16_ACCX_LD_XP_P + { 7, &XtensaDescs.OperandInfo[264] }, // Inst #431 = EE_VMULAS_S16_ACCX_LD_IP_QUP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #430 = EE_VMULAS_S16_ACCX_LD_IP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #429 = EE_VMIN_S8_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #428 = EE_VMIN_S8_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #427 = EE_VMIN_S8_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #426 = EE_VMIN_S32_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #425 = EE_VMIN_S32_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #424 = EE_VMIN_S32_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #423 = EE_VMIN_S16_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #422 = EE_VMIN_S16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #421 = EE_VMIN_S16_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #420 = EE_VMAX_S8_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #419 = EE_VMAX_S8_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #418 = EE_VMAX_S8_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #417 = EE_VMAX_S32_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #416 = EE_VMAX_S32_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #415 = EE_VMAX_S32_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #414 = EE_VMAX_S16_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #413 = EE_VMAX_S16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #412 = EE_VMAX_S16_LD_INCP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #411 = EE_VLD_L_64_XP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #410 = EE_VLD_L_64_IP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #409 = EE_VLD_H_64_XP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #408 = EE_VLD_H_64_IP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #407 = EE_VLD_128_XP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #406 = EE_VLD_128_IP_P + { 3, &XtensaDescs.OperandInfo[248] }, // Inst #405 = EE_VLDHBC_16_INCP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #404 = EE_VLDBC_8_XP_P + { 2, &XtensaDescs.OperandInfo[156] }, // Inst #403 = EE_VLDBC_8_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #402 = EE_VLDBC_8_IP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #401 = EE_VLDBC_32_XP_P + { 2, &XtensaDescs.OperandInfo[156] }, // Inst #400 = EE_VLDBC_32_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #399 = EE_VLDBC_32_IP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #398 = EE_VLDBC_16_XP_P + { 2, &XtensaDescs.OperandInfo[156] }, // Inst #397 = EE_VLDBC_16_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #396 = EE_VLDBC_16_IP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #395 = EE_VCMP_LT_S8_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #394 = EE_VCMP_LT_S32_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #393 = EE_VCMP_LT_S16_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #392 = EE_VCMP_GT_S8_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #391 = EE_VCMP_GT_S32_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #390 = EE_VCMP_GT_S16_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #389 = EE_VCMP_EQ_S8_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #388 = EE_VCMP_EQ_S32_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #387 = EE_VCMP_EQ_S16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #386 = EE_VADDS_S8_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #385 = EE_VADDS_S8_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #384 = EE_VADDS_S8_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #383 = EE_VADDS_S32_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #382 = EE_VADDS_S32_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #381 = EE_VADDS_S32_LD_INCP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #380 = EE_VADDS_S16_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #379 = EE_VADDS_S16_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #378 = EE_VADDS_S16_LD_INCP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #377 = EE_ST_UA_STATE_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #376 = EE_ST_QACC_L_L_128_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #375 = EE_ST_QACC_L_H_32_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #374 = EE_ST_QACC_H_L_128_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #373 = EE_ST_QACC_H_H_32_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #372 = EE_ST_ACCX_IP_P + { 5, &XtensaDescs.OperandInfo[236] }, // Inst #371 = EE_STXQ_32_P + { 4, &XtensaDescs.OperandInfo[228] }, // Inst #370 = EE_STF_64_XP_P + { 4, &XtensaDescs.OperandInfo[224] }, // Inst #369 = EE_STF_64_IP_P + { 6, &XtensaDescs.OperandInfo[218] }, // Inst #368 = EE_STF_128_XP_P + { 6, &XtensaDescs.OperandInfo[212] }, // Inst #367 = EE_STF_128_IP_P + { 3, &XtensaDescs.OperandInfo[261] }, // Inst #366 = EE_SRS_ACCX_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #365 = EE_SRC_Q_QUP_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #364 = EE_SRC_Q_P + { 5, &XtensaDescs.OperandInfo[256] }, // Inst #363 = EE_SRC_Q_LD_XP_P + { 5, &XtensaDescs.OperandInfo[251] }, // Inst #362 = EE_SRC_Q_LD_IP_P + { 4, &XtensaDescs.OperandInfo[244] }, // Inst #361 = EE_SRCXXP_2Q_P + { 3, &XtensaDescs.OperandInfo[248] }, // Inst #360 = EE_SRCQ_128_ST_INCP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #359 = EE_SRCMB_S8_QACC_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #358 = EE_SRCMB_S16_QACC_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #357 = EE_SRCI_2Q_P + { 4, &XtensaDescs.OperandInfo[244] }, // Inst #356 = EE_SLCXXP_2Q_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #355 = EE_SLCI_2Q_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #354 = EE_ORQ_P + { 2, &XtensaDescs.OperandInfo[13] }, // Inst #353 = EE_NOTQ_P + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #352 = EE_MOV_U8_QACC_P + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #351 = EE_MOV_U16_QACC_P + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #350 = EE_MOV_S8_QACC_P + { 1, &XtensaDescs.OperandInfo[0] }, // Inst #349 = EE_MOV_S16_QACC_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #348 = EE_MOVI_32_Q_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #347 = EE_MOVI_32_A_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #346 = EE_LD_UA_STATE_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #345 = EE_LD_QACC_L_L_128_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #344 = EE_LD_QACC_L_H_32_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #343 = EE_LD_QACC_H_L_128_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #342 = EE_LD_QACC_H_H_32_IP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #341 = EE_LD_ACCX_IP_P + { 3, &XtensaDescs.OperandInfo[241] }, // Inst #340 = EE_LD_128_USAR_XP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #339 = EE_LD_128_USAR_IP_P + { 5, &XtensaDescs.OperandInfo[236] }, // Inst #338 = EE_LDXQ_32_P + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #337 = EE_LDQA_U8_128_XP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #336 = EE_LDQA_U8_128_IP_P + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #335 = EE_LDQA_U16_128_XP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #334 = EE_LDQA_U16_128_IP_P + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #333 = EE_LDQA_S8_128_XP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #332 = EE_LDQA_S8_128_IP_P + { 2, &XtensaDescs.OperandInfo[234] }, // Inst #331 = EE_LDQA_S16_128_XP_P + { 2, &XtensaDescs.OperandInfo[232] }, // Inst #330 = EE_LDQA_S16_128_IP_P + { 4, &XtensaDescs.OperandInfo[228] }, // Inst #329 = EE_LDF_64_XP_P + { 4, &XtensaDescs.OperandInfo[224] }, // Inst #328 = EE_LDF_64_IP_P + { 6, &XtensaDescs.OperandInfo[218] }, // Inst #327 = EE_LDF_128_XP_P + { 6, &XtensaDescs.OperandInfo[212] }, // Inst #326 = EE_LDF_128_IP_P + { 3, &XtensaDescs.OperandInfo[209] }, // Inst #325 = EE_FFT_VST_R32_DECP_P + { 5, &XtensaDescs.OperandInfo[204] }, // Inst #324 = EE_FFT_R2BF_S16_ST_INCP_P + { 5, &XtensaDescs.OperandInfo[199] }, // Inst #323 = EE_FFT_R2BF_S16_P + { 8, &XtensaDescs.OperandInfo[191] }, // Inst #322 = EE_FFT_CMUL_S16_ST_XP_P + { 7, &XtensaDescs.OperandInfo[184] }, // Inst #321 = EE_FFT_CMUL_S16_LD_XP_P + { 8, &XtensaDescs.OperandInfo[176] }, // Inst #320 = EE_FFT_AMS_S16_ST_INCP_P + { 8, &XtensaDescs.OperandInfo[168] }, // Inst #319 = EE_FFT_AMS_S16_LD_R32_DECP_P + { 8, &XtensaDescs.OperandInfo[168] }, // Inst #318 = EE_FFT_AMS_S16_LD_INCP_UAUP_P + { 8, &XtensaDescs.OperandInfo[168] }, // Inst #317 = EE_FFT_AMS_S16_LD_INCP_P + { 6, &XtensaDescs.OperandInfo[158] }, // Inst #316 = EE_CMUL_S16_ST_INCP_P + { 4, &XtensaDescs.OperandInfo[164] }, // Inst #315 = EE_CMUL_S16_P + { 6, &XtensaDescs.OperandInfo[158] }, // Inst #314 = EE_CMUL_S16_LD_INCP_P + { 2, &XtensaDescs.OperandInfo[156] }, // Inst #313 = EE_BITREV_P + { 3, &XtensaDescs.OperandInfo[153] }, // Inst #312 = EE_ANDQ_P + { 3, &XtensaDescs.OperandInfo[2] }, // Inst #311 = CONSTPOOL_ENTRY + { 2, &XtensaDescs.OperandInfo[151] }, // Inst #310 = BR_JT + { 4, &XtensaDescs.OperandInfo[147] }, // Inst #309 = BRCC_FP + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #308 = ATOMIC_SWAP_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #307 = ATOMIC_SWAP_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #306 = ATOMIC_SWAP_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #305 = ATOMIC_LOAD_XOR_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #304 = ATOMIC_LOAD_XOR_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #303 = ATOMIC_LOAD_XOR_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #302 = ATOMIC_LOAD_UMIN_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #301 = ATOMIC_LOAD_UMIN_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #300 = ATOMIC_LOAD_UMIN_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #299 = ATOMIC_LOAD_UMAX_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #298 = ATOMIC_LOAD_UMAX_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #297 = ATOMIC_LOAD_UMAX_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #296 = ATOMIC_LOAD_SUB_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #295 = ATOMIC_LOAD_SUB_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #294 = ATOMIC_LOAD_SUB_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #293 = ATOMIC_LOAD_OR_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #292 = ATOMIC_LOAD_OR_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #291 = ATOMIC_LOAD_OR_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #290 = ATOMIC_LOAD_NAND_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #289 = ATOMIC_LOAD_NAND_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #288 = ATOMIC_LOAD_NAND_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #287 = ATOMIC_LOAD_MIN_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #286 = ATOMIC_LOAD_MIN_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #285 = ATOMIC_LOAD_MIN_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #284 = ATOMIC_LOAD_MAX_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #283 = ATOMIC_LOAD_MAX_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #282 = ATOMIC_LOAD_MAX_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #281 = ATOMIC_LOAD_AND_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #280 = ATOMIC_LOAD_AND_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #279 = ATOMIC_LOAD_AND_16_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #278 = ATOMIC_LOAD_ADD_8_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #277 = ATOMIC_LOAD_ADD_32_P + { 3, &XtensaDescs.OperandInfo[144] }, // Inst #276 = ATOMIC_LOAD_ADD_16_P + { 4, &XtensaDescs.OperandInfo[140] }, // Inst #275 = ATOMIC_CMP_SWAP_8_P + { 4, &XtensaDescs.OperandInfo[140] }, // Inst #274 = ATOMIC_CMP_SWAP_32_P + { 4, &XtensaDescs.OperandInfo[140] }, // Inst #273 = ATOMIC_CMP_SWAP_16_P + { 2, &XtensaDescs.OperandInfo[21] }, // Inst #272 = ADJCALLSTACKUP + { 2, &XtensaDescs.OperandInfo[21] }, // Inst #271 = ADJCALLSTACKDOWN { 4, &XtensaDescs.OperandInfo[136] }, // Inst #270 = G_UBFX { 4, &XtensaDescs.OperandInfo[136] }, // Inst #269 = G_SBFX { 2, &XtensaDescs.OperandInfo[56] }, // Inst #268 = G_VECREDUCE_UMIN @@ -782,21 +4064,200 @@ static const XtensaInstrTable XtensaDescs = { /* 130 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, /* 132 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, /* 136 */ { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, - /* 140 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, - /* 142 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, - /* 145 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, - /* 148 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, - /* 151 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, - /* 153 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, - /* 154 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, - /* 158 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, - /* 161 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_SRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, - /* 163 */ { Xtensa_SRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, - /* 165 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_SRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_SRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, + /* 140 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 144 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 147 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 151 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 153 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 156 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 158 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 164 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 168 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 176 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 184 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 191 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 199 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 204 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 209 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 212 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 218 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 224 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 228 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 232 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 234 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 236 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 241 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 244 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 248 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 251 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 256 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 261 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 264 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 271 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 275 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 279 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 282 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 285 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 288 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + /* 291 */ { Xtensa_BR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 293 */ { Xtensa_BR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 297 */ { Xtensa_BR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 299 */ { Xtensa_BR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 303 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 305 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 309 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 313 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + /* 316 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 322 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 328 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 334 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 340 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 341 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 343 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 346 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 349 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 351 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 354 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 356 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 358 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 361 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 364 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 367 */ { Xtensa_BR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 370 */ { Xtensa_BR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 373 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 376 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 379 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 383 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 386 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 390 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, + /* 393 */ { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, + /* 396 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, + /* 401 */ { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 403 */ { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 406 */ { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 408 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 412 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 416 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 420 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 422 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 426 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 432 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 436 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 443 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 448 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 452 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 456 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 460 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, + /* 463 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, + /* 467 */ { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, + /* 472 */ { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 475 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, + /* 477 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 481 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 485 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 488 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 491 */ { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_AE_DRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 495 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 498 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 502 */ { Xtensa_AE_VALIGNRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 503 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 505 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 508 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 511 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 513 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 516 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 518 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 522 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 525 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, + /* 528 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 532 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 539 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 546 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 555 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 565 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 573 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 582 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 587 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 593 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 597 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(4) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 604 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(4) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 611 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 616 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 621 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 624 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 627 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 632 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 636 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 640 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 643 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 646 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 647 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 649 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 654 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 661 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, + /* 665 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 672 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 679 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 683 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 690 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 697 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 702 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 707 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 713 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 719 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 721 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, + /* 725 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 731 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 740 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 746 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 755 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 760 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 768 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 772 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 776 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 779 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 785 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 789 */ { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_QRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, + /* 793 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 797 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 800 */ { Xtensa_MRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, + /* 803 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + /* 806 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 810 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 813 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 817 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 821 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 825 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 829 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 833 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_MR23RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 835 */ { Xtensa_MR01RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 837 */ { Xtensa_MRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_MR01RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 842 */ { Xtensa_MRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_MRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 847 */ { Xtensa_MR01RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_MR23RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 849 */ { Xtensa_MRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { Xtensa_MR01RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_MR23RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 854 */ { Xtensa_BRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 857 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 859 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_SRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 861 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_URRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 863 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, + /* 867 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 871 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 875 */ { Xtensa_FPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 877 */ { Xtensa_SRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 879 */ { Xtensa_URRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, + /* 881 */ { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_SRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { Xtensa_ARRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { Xtensa_SRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, }, { /* 0 */ - /* 0 */ Xtensa_A0, - /* 1 */ Xtensa_SAR, + /* 0 */ Xtensa_SP, Xtensa_SP, + /* 2 */ Xtensa_BREG, + /* 3 */ Xtensa_A0, + /* 4 */ Xtensa_SP, + /* 5 */ Xtensa_M1, Xtensa_M2, Xtensa_ACCLO, Xtensa_ACCHI, + /* 9 */ Xtensa_ACCLO, Xtensa_ACCHI, Xtensa_M1, Xtensa_M2, Xtensa_ACCLO, Xtensa_ACCHI, + /* 15 */ Xtensa_SCOMPARE1, + /* 16 */ Xtensa_SAR, + /* 17 */ Xtensa_FCR, + /* 18 */ Xtensa_FSR, } }; diff --git a/arch/Xtensa/XtensaGenRegisterInfo.inc b/arch/Xtensa/XtensaGenRegisterInfo.inc index a287b8aefe..2a82b27f87 100644 --- a/arch/Xtensa/XtensaGenRegisterInfo.inc +++ b/arch/Xtensa/XtensaGenRegisterInfo.inc @@ -3,33 +3,207 @@ enum { Xtensa_NoRegister, - Xtensa_SAR = 1, - Xtensa_SP = 2, - Xtensa_A0 = 3, - Xtensa_A2 = 4, - Xtensa_A3 = 5, - Xtensa_A4 = 6, - Xtensa_A5 = 7, - Xtensa_A6 = 8, - Xtensa_A7 = 9, - Xtensa_A8 = 10, - Xtensa_A9 = 11, - Xtensa_A10 = 12, - Xtensa_A11 = 13, - Xtensa_A12 = 14, - Xtensa_A13 = 15, - Xtensa_A14 = 16, - Xtensa_A15 = 17, - NUM_TARGET_REGS // 18 + Xtensa_ACCHI = 1, + Xtensa_ACCLO = 2, + Xtensa_ACCX = 3, + Xtensa_ATOMCTL = 4, + Xtensa_BREG = 5, + Xtensa_CCOUNT = 6, + Xtensa_CPENABLE = 7, + Xtensa_DDR = 8, + Xtensa_DEBUGCAUSE = 9, + Xtensa_DEPC = 10, + Xtensa_EXCCAUSE = 11, + Xtensa_EXCVADDR = 12, + Xtensa_EXPSTATE = 13, + Xtensa_FCR = 14, + Xtensa_FFT_BIT_WIDTH = 15, + Xtensa_FSR = 16, + Xtensa_GPIO_OUT = 17, + Xtensa_IBREAKENABLE = 18, + Xtensa_ICOUNT = 19, + Xtensa_ICOUNTLEVEL = 20, + Xtensa_INTCLEAR = 21, + Xtensa_INTENABLE = 22, + Xtensa_INTERRUPT = 23, + Xtensa_LBEG = 24, + Xtensa_LCOUNT = 25, + Xtensa_LEND = 26, + Xtensa_LITBASE = 27, + Xtensa_MEMCTL = 28, + Xtensa_PRID = 29, + Xtensa_PS = 30, + Xtensa_QACC = 31, + Xtensa_SAR = 32, + Xtensa_SAR_BYTE = 33, + Xtensa_SP = 34, + Xtensa_THREADPTR = 35, + Xtensa_UA_STATE = 36, + Xtensa_VECBASE = 37, + Xtensa_WINDOWBASE = 38, + Xtensa_WINDOWSTART = 39, + Xtensa_A0 = 40, + Xtensa_A2 = 41, + Xtensa_A3 = 42, + Xtensa_A4 = 43, + Xtensa_A5 = 44, + Xtensa_A6 = 45, + Xtensa_A7 = 46, + Xtensa_A8 = 47, + Xtensa_A9 = 48, + Xtensa_A10 = 49, + Xtensa_A11 = 50, + Xtensa_A12 = 51, + Xtensa_A13 = 52, + Xtensa_A14 = 53, + Xtensa_A15 = 54, + Xtensa_AED0 = 55, + Xtensa_AED1 = 56, + Xtensa_AED2 = 57, + Xtensa_AED3 = 58, + Xtensa_AED4 = 59, + Xtensa_AED5 = 60, + Xtensa_AED6 = 61, + Xtensa_AED7 = 62, + Xtensa_AED8 = 63, + Xtensa_AED9 = 64, + Xtensa_AED10 = 65, + Xtensa_AED11 = 66, + Xtensa_AED12 = 67, + Xtensa_AED13 = 68, + Xtensa_AED14 = 69, + Xtensa_AED15 = 70, + Xtensa_B0 = 71, + Xtensa_B1 = 72, + Xtensa_B2 = 73, + Xtensa_B3 = 74, + Xtensa_B4 = 75, + Xtensa_B5 = 76, + Xtensa_B6 = 77, + Xtensa_B7 = 78, + Xtensa_B8 = 79, + Xtensa_B9 = 80, + Xtensa_B10 = 81, + Xtensa_B11 = 82, + Xtensa_B12 = 83, + Xtensa_B13 = 84, + Xtensa_B14 = 85, + Xtensa_B15 = 86, + Xtensa_CCOMPARE0 = 87, + Xtensa_CCOMPARE1 = 88, + Xtensa_CCOMPARE2 = 89, + Xtensa_CONFIGID0 = 90, + Xtensa_CONFIGID1 = 91, + Xtensa_DBREAKA0 = 92, + Xtensa_DBREAKA1 = 93, + Xtensa_DBREAKC0 = 94, + Xtensa_DBREAKC1 = 95, + Xtensa_EPC1 = 96, + Xtensa_EPC2 = 97, + Xtensa_EPC3 = 98, + Xtensa_EPC4 = 99, + Xtensa_EPC5 = 100, + Xtensa_EPC6 = 101, + Xtensa_EPC7 = 102, + Xtensa_EPS2 = 103, + Xtensa_EPS3 = 104, + Xtensa_EPS4 = 105, + Xtensa_EPS5 = 106, + Xtensa_EPS6 = 107, + Xtensa_EPS7 = 108, + Xtensa_EXCSAVE1 = 109, + Xtensa_EXCSAVE2 = 110, + Xtensa_EXCSAVE3 = 111, + Xtensa_EXCSAVE4 = 112, + Xtensa_EXCSAVE5 = 113, + Xtensa_EXCSAVE6 = 114, + Xtensa_EXCSAVE7 = 115, + Xtensa_F0 = 116, + Xtensa_F1 = 117, + Xtensa_F2 = 118, + Xtensa_F3 = 119, + Xtensa_F4 = 120, + Xtensa_F5 = 121, + Xtensa_F6 = 122, + Xtensa_F7 = 123, + Xtensa_F8 = 124, + Xtensa_F9 = 125, + Xtensa_F10 = 126, + Xtensa_F11 = 127, + Xtensa_F12 = 128, + Xtensa_F13 = 129, + Xtensa_F14 = 130, + Xtensa_F15 = 131, + Xtensa_IBREAKA0 = 132, + Xtensa_IBREAKA1 = 133, + Xtensa_M0 = 134, + Xtensa_M1 = 135, + Xtensa_M2 = 136, + Xtensa_M3 = 137, + Xtensa_MISC0 = 138, + Xtensa_MISC1 = 139, + Xtensa_MISC2 = 140, + Xtensa_MISC3 = 141, + Xtensa_Q0 = 142, + Xtensa_Q1 = 143, + Xtensa_Q2 = 144, + Xtensa_Q3 = 145, + Xtensa_Q4 = 146, + Xtensa_Q5 = 147, + Xtensa_Q6 = 148, + Xtensa_Q7 = 149, + Xtensa_SCOMPARE1 = 150, + Xtensa_U0 = 151, + Xtensa_U1 = 152, + Xtensa_U2 = 153, + Xtensa_U3 = 154, + Xtensa_F64R_HI = 155, + Xtensa_F64R_LO = 156, + Xtensa_F64S = 157, + Xtensa_B0_B1 = 158, + Xtensa_B2_B3 = 159, + Xtensa_B4_B5 = 160, + Xtensa_B6_B7 = 161, + Xtensa_B8_B9 = 162, + Xtensa_B10_B11 = 163, + Xtensa_B12_B13 = 164, + Xtensa_B14_B15 = 165, + Xtensa_B0_B1_B2_B3 = 166, + Xtensa_B4_B5_B6_B7 = 167, + Xtensa_B8_B9_B10_B11 = 168, + Xtensa_B12_B13_B14_B15 = 169, + NUM_TARGET_REGS // 170 }; // Register classes enum { - Xtensa_ARRegClassID = 0, - Xtensa_SRRegClassID = 1, + Xtensa_BRRegClassID = 0, + Xtensa_BR2RegClassID = 1, + Xtensa_BR4RegClassID = 2, + Xtensa_SRRegClassID = 3, + Xtensa_ARRegClassID = 4, + Xtensa_FPRRegClassID = 5, + Xtensa_URRegClassID = 6, + Xtensa_MRRegClassID = 7, + Xtensa_MR01RegClassID = 8, + Xtensa_MR23RegClassID = 9, + Xtensa_AE_DRRegClassID = 10, + Xtensa_AE_VALIGNRegClassID = 11, + Xtensa_QRRegClassID = 12, }; + +// Subregister indices + +enum { + Xtensa_NoSubRegister, + Xtensa_bsub0, // 1 + Xtensa_bsub1, // 2 + Xtensa_bsub2, // 3 + Xtensa_bsub3, // 4 + Xtensa_NUM_TARGET_SUBREGS +}; #endif // GET_REGINFO_ENUM /* Capstone Disassembly Engine, https://www.capstone-engine.org */ @@ -49,34 +223,251 @@ enum { #undef GET_REGINFO_MC_DESC static const MCPhysReg XtensaRegDiffLists[] = { - /* 0 */ 0, + /* 0 */ -87, 1, 0, + /* 3 */ -86, 1, 0, + /* 6 */ -85, 1, 0, + /* 9 */ -84, 1, 0, + /* 12 */ -83, 1, 0, + /* 15 */ -82, 1, 0, + /* 18 */ -81, 1, 0, + /* 21 */ -80, 1, 0, + /* 24 */ -95, 1, 1, 1, 0, + /* 29 */ -92, 1, 1, 1, 0, + /* 34 */ -89, 1, 1, 1, 0, + /* 39 */ -86, 1, 1, 1, 0, + /* 44 */ 79, 4, 0, + /* 47 */ 80, 4, 0, + /* 50 */ 80, 5, 0, + /* 53 */ 81, 5, 0, + /* 56 */ 82, 5, 0, + /* 59 */ 82, 6, 0, + /* 62 */ 83, 6, 0, + /* 65 */ 84, 6, 0, + /* 68 */ 84, 7, 0, + /* 71 */ 85, 7, 0, + /* 74 */ 86, 7, 0, + /* 77 */ 86, 8, 0, + /* 80 */ 87, 8, 0, }; static const uint16_t XtensaSubRegIdxLists[] = { - /* 0 */ 0, + /* 0 */ 1, 2, 0, + /* 3 */ 1, 2, 3, 4, 0, }; static const MCRegisterDesc XtensaRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0, 0 }, - { 54, 0, 0, 0, 0, 0 }, - { 51, 0, 0, 0, 1, 0 }, - { 4, 0, 0, 0, 2, 0 }, - { 15, 0, 0, 0, 3, 0 }, - { 22, 0, 0, 0, 4, 0 }, - { 29, 0, 0, 0, 5, 0 }, - { 36, 0, 0, 0, 6, 0 }, - { 39, 0, 0, 0, 7, 0 }, - { 42, 0, 0, 0, 8, 0 }, - { 45, 0, 0, 0, 9, 0 }, - { 48, 0, 0, 0, 10, 0 }, - { 0, 0, 0, 0, 11, 0 }, - { 7, 0, 0, 0, 12, 0 }, - { 11, 0, 0, 0, 13, 0 }, - { 18, 0, 0, 0, 14, 0 }, - { 25, 0, 0, 0, 15, 0 }, - { 32, 0, 0, 0, 16, 0 }, + { 759, 2, 2, 2, 8192, 8 }, + { 800, 2, 2, 2, 8193, 8 }, + { 917, 2, 2, 2, 8194, 8 }, + { 792, 2, 2, 2, 8195, 8 }, + { 740, 2, 2, 2, 8196, 8 }, + { 865, 2, 2, 2, 8197, 8 }, + { 642, 2, 2, 2, 8198, 8 }, + { 839, 2, 2, 2, 8199, 8 }, + { 697, 2, 2, 2, 8200, 8 }, + { 614, 2, 2, 2, 8201, 8 }, + { 688, 2, 2, 2, 8202, 8 }, + { 834, 2, 2, 2, 8203, 8 }, + { 708, 2, 2, 2, 8204, 8 }, + { 830, 2, 2, 2, 8205, 8 }, + { 745, 2, 2, 2, 8206, 8 }, + { 843, 2, 2, 2, 8207, 8 }, + { 908, 2, 2, 2, 8208, 8 }, + { 629, 2, 2, 2, 8209, 8 }, + { 872, 2, 2, 2, 8210, 8 }, + { 773, 2, 2, 2, 8211, 8 }, + { 817, 2, 2, 2, 8212, 8 }, + { 651, 2, 2, 2, 8213, 8 }, + { 886, 2, 2, 2, 8214, 8 }, + { 735, 2, 2, 2, 8215, 8 }, + { 879, 2, 2, 2, 8216, 8 }, + { 624, 2, 2, 2, 8217, 8 }, + { 669, 2, 2, 2, 8218, 8 }, + { 785, 2, 2, 2, 8219, 8 }, + { 619, 2, 2, 2, 8220, 8 }, + { 862, 2, 2, 2, 8221, 8 }, + { 609, 2, 2, 2, 8222, 8 }, + { 826, 2, 2, 2, 8223, 8 }, + { 726, 2, 2, 2, 8224, 8 }, + { 814, 2, 2, 2, 8225, 8 }, + { 847, 2, 2, 2, 8226, 8 }, + { 717, 2, 2, 2, 8227, 8 }, + { 661, 2, 2, 2, 8228, 8 }, + { 677, 2, 2, 2, 8229, 8 }, + { 896, 2, 2, 2, 8230, 8 }, + { 24, 2, 2, 2, 8231, 8 }, + { 237, 2, 2, 2, 8232, 8 }, + { 317, 2, 2, 2, 8233, 8 }, + { 392, 2, 2, 2, 8234, 8 }, + { 458, 2, 2, 2, 8235, 8 }, + { 497, 2, 2, 2, 8236, 8 }, + { 533, 2, 2, 2, 8237, 8 }, + { 578, 2, 2, 2, 8238, 8 }, + { 592, 2, 2, 2, 8239, 8 }, + { 0, 2, 2, 2, 8240, 8 }, + { 91, 2, 2, 2, 8241, 8 }, + { 219, 2, 2, 2, 8242, 8 }, + { 295, 2, 2, 2, 8243, 8 }, + { 374, 2, 2, 2, 8244, 8 }, + { 428, 2, 2, 2, 8245, 8 }, + { 54, 2, 2, 2, 8246, 8 }, + { 163, 2, 2, 2, 8247, 8 }, + { 254, 2, 2, 2, 8248, 8 }, + { 343, 2, 2, 2, 8249, 8 }, + { 403, 2, 2, 2, 8250, 8 }, + { 472, 2, 2, 2, 8251, 8 }, + { 508, 2, 2, 2, 8252, 8 }, + { 553, 2, 2, 2, 8253, 8 }, + { 584, 2, 2, 2, 8254, 8 }, + { 601, 2, 2, 2, 8255, 8 }, + { 8, 2, 2, 2, 8256, 8 }, + { 109, 2, 2, 2, 8257, 8 }, + { 227, 2, 2, 2, 8258, 8 }, + { 307, 2, 2, 2, 8259, 8 }, + { 382, 2, 2, 2, 8260, 8 }, + { 448, 2, 2, 2, 8261, 8 }, + { 36, 2, 80, 2, 8262, 8 }, + { 140, 2, 77, 2, 8263, 8 }, + { 240, 2, 74, 2, 8264, 8 }, + { 329, 2, 71, 2, 8265, 8 }, + { 395, 2, 71, 2, 8266, 8 }, + { 464, 2, 68, 2, 8267, 8 }, + { 500, 2, 65, 2, 8268, 8 }, + { 545, 2, 62, 2, 8269, 8 }, + { 581, 2, 62, 2, 8270, 8 }, + { 598, 2, 59, 2, 8271, 8 }, + { 4, 2, 56, 2, 8272, 8 }, + { 105, 2, 53, 2, 8273, 8 }, + { 223, 2, 53, 2, 8274, 8 }, + { 303, 2, 50, 2, 8275, 8 }, + { 378, 2, 47, 2, 8276, 8 }, + { 444, 2, 44, 2, 8277, 8 }, + { 69, 2, 2, 2, 8278, 8 }, + { 178, 2, 2, 2, 8279, 8 }, + { 259, 2, 2, 2, 8280, 8 }, + { 59, 2, 2, 2, 8281, 8 }, + { 168, 2, 2, 2, 8282, 8 }, + { 18, 2, 2, 2, 8283, 8 }, + { 119, 2, 2, 2, 8284, 8 }, + { 39, 2, 2, 2, 8285, 8 }, + { 143, 2, 2, 2, 8286, 8 }, + { 152, 2, 2, 2, 8287, 8 }, + { 243, 2, 2, 2, 8288, 8 }, + { 332, 2, 2, 2, 8289, 8 }, + { 398, 2, 2, 2, 8290, 8 }, + { 467, 2, 2, 2, 8291, 8 }, + { 503, 2, 2, 2, 8292, 8 }, + { 548, 2, 2, 2, 8293, 8 }, + { 287, 2, 2, 2, 8294, 8 }, + { 366, 2, 2, 2, 8295, 8 }, + { 423, 2, 2, 2, 8296, 8 }, + { 492, 2, 2, 2, 8297, 8 }, + { 528, 2, 2, 2, 8298, 8 }, + { 573, 2, 2, 2, 8299, 8 }, + { 198, 2, 2, 2, 8300, 8 }, + { 269, 2, 2, 2, 8301, 8 }, + { 348, 2, 2, 2, 8302, 8 }, + { 408, 2, 2, 2, 8303, 8 }, + { 477, 2, 2, 2, 8304, 8 }, + { 513, 2, 2, 2, 8305, 8 }, + { 558, 2, 2, 2, 8306, 8 }, + { 79, 2, 2, 2, 8307, 8 }, + { 207, 2, 2, 2, 8308, 8 }, + { 278, 2, 2, 2, 8309, 8 }, + { 357, 2, 2, 2, 8310, 8 }, + { 417, 2, 2, 2, 8311, 8 }, + { 486, 2, 2, 2, 8312, 8 }, + { 522, 2, 2, 2, 8313, 8 }, + { 567, 2, 2, 2, 8314, 8 }, + { 589, 2, 2, 2, 8315, 8 }, + { 606, 2, 2, 2, 8316, 8 }, + { 14, 2, 2, 2, 8317, 8 }, + { 115, 2, 2, 2, 8318, 8 }, + { 233, 2, 2, 2, 8319, 8 }, + { 313, 2, 2, 2, 8320, 8 }, + { 388, 2, 2, 2, 8321, 8 }, + { 454, 2, 2, 2, 8322, 8 }, + { 27, 2, 2, 2, 8323, 8 }, + { 128, 2, 2, 2, 8324, 8 }, + { 82, 2, 2, 2, 8325, 8 }, + { 210, 2, 2, 2, 8326, 8 }, + { 281, 2, 2, 2, 8327, 8 }, + { 360, 2, 2, 2, 8328, 8 }, + { 48, 2, 2, 2, 8329, 8 }, + { 157, 2, 2, 2, 8330, 8 }, + { 248, 2, 2, 2, 8331, 8 }, + { 337, 2, 2, 2, 8332, 8 }, + { 85, 2, 2, 2, 8333, 8 }, + { 213, 2, 2, 2, 8334, 8 }, + { 284, 2, 2, 2, 8335, 8 }, + { 363, 2, 2, 2, 8336, 8 }, + { 420, 2, 2, 2, 8337, 8 }, + { 489, 2, 2, 2, 8338, 8 }, + { 525, 2, 2, 2, 8339, 8 }, + { 570, 2, 2, 2, 8340, 8 }, + { 188, 2, 2, 2, 8341, 8 }, + { 88, 2, 2, 2, 8342, 8 }, + { 216, 2, 2, 2, 8343, 8 }, + { 292, 2, 2, 2, 8344, 8 }, + { 371, 2, 2, 2, 8345, 8 }, + { 765, 2, 2, 2, 8346, 8 }, + { 806, 2, 2, 2, 8347, 8 }, + { 857, 2, 2, 2, 8348, 8 }, + { 137, 0, 2, 0, 4166, 0 }, + { 326, 3, 2, 0, 4168, 0 }, + { 461, 6, 2, 0, 4170, 0 }, + { 542, 9, 2, 0, 4172, 0 }, + { 595, 12, 2, 0, 4174, 0 }, + { 101, 15, 2, 0, 4176, 0 }, + { 299, 18, 2, 0, 4178, 0 }, + { 440, 21, 2, 0, 4180, 0 }, + { 320, 24, 2, 3, 102470, 3 }, + { 536, 29, 2, 3, 102474, 3 }, + { 95, 34, 2, 3, 102478, 3 }, + { 432, 39, 2, 3, 102482, 3 }, }; + // BR Register Class... + static const MCPhysReg BR[] = { + Xtensa_B0, Xtensa_B1, Xtensa_B2, Xtensa_B3, Xtensa_B4, Xtensa_B5, Xtensa_B6, Xtensa_B7, Xtensa_B8, Xtensa_B9, Xtensa_B10, Xtensa_B11, Xtensa_B12, Xtensa_B13, Xtensa_B14, Xtensa_B15, + }; + + // BR Bit set. + static const uint8_t BRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + + // BR2 Register Class... + static const MCPhysReg BR2[] = { + Xtensa_B0_B1, Xtensa_B2_B3, Xtensa_B4_B5, Xtensa_B6_B7, Xtensa_B8_B9, Xtensa_B10_B11, Xtensa_B12_B13, Xtensa_B14_B15, + }; + + // BR2 Bit set. + static const uint8_t BR2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, + }; + + // BR4 Register Class... + static const MCPhysReg BR4[] = { + Xtensa_B0_B1_B2_B3, Xtensa_B4_B5_B6_B7, Xtensa_B8_B9_B10_B11, Xtensa_B12_B13_B14_B15, + }; + + // BR4 Bit set. + static const uint8_t BR4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, + }; + + // SR Register Class... + static const MCPhysReg SR[] = { + Xtensa_LBEG, Xtensa_LEND, Xtensa_LCOUNT, Xtensa_SAR, Xtensa_BREG, Xtensa_LITBASE, Xtensa_SCOMPARE1, Xtensa_ACCLO, Xtensa_ACCHI, Xtensa_M0, Xtensa_M1, Xtensa_M2, Xtensa_M3, Xtensa_WINDOWBASE, Xtensa_WINDOWSTART, Xtensa_IBREAKENABLE, Xtensa_MEMCTL, Xtensa_ATOMCTL, Xtensa_DDR, Xtensa_IBREAKA0, Xtensa_IBREAKA1, Xtensa_DBREAKA0, Xtensa_DBREAKA1, Xtensa_DBREAKC0, Xtensa_DBREAKC1, Xtensa_CONFIGID0, Xtensa_EPC1, Xtensa_EPC2, Xtensa_EPC3, Xtensa_EPC4, Xtensa_EPC5, Xtensa_EPC6, Xtensa_EPC7, Xtensa_DEPC, Xtensa_EPS2, Xtensa_EPS3, Xtensa_EPS4, Xtensa_EPS5, Xtensa_EPS6, Xtensa_EPS7, Xtensa_CONFIGID1, Xtensa_EXCSAVE1, Xtensa_EXCSAVE2, Xtensa_EXCSAVE3, Xtensa_EXCSAVE4, Xtensa_EXCSAVE5, Xtensa_EXCSAVE6, Xtensa_EXCSAVE7, Xtensa_CPENABLE, Xtensa_INTERRUPT, Xtensa_INTCLEAR, Xtensa_INTENABLE, Xtensa_PS, Xtensa_VECBASE, Xtensa_EXCCAUSE, Xtensa_DEBUGCAUSE, Xtensa_CCOUNT, Xtensa_PRID, Xtensa_ICOUNT, Xtensa_ICOUNTLEVEL, Xtensa_EXCVADDR, Xtensa_CCOMPARE0, Xtensa_CCOMPARE1, Xtensa_CCOMPARE2, Xtensa_MISC0, Xtensa_MISC1, Xtensa_MISC2, Xtensa_MISC3, + }; + + // SR Bit set. + static const uint8_t SRBits[] = { + 0xf6, 0x1f, 0xfc, 0x7f, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0x3f, 0x40, + }; + // AR Register Class... static const MCPhysReg AR[] = { Xtensa_A8, Xtensa_A9, Xtensa_A10, Xtensa_A11, Xtensa_A12, Xtensa_A13, Xtensa_A14, Xtensa_A15, Xtensa_A7, Xtensa_A6, Xtensa_A5, Xtensa_A4, Xtensa_A3, Xtensa_A2, Xtensa_A0, Xtensa_SP, @@ -84,28 +475,146 @@ static const MCRegisterDesc XtensaRegDesc[] = { // Descriptors // AR Bit set. static const uint8_t ARBits[] = { - 0xfc, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x04, 0xff, 0x7f, }; - // SR Register Class... - static const MCPhysReg SR[] = { - Xtensa_SAR, + // FPR Register Class... + static const MCPhysReg FPR[] = { + Xtensa_F8, Xtensa_F9, Xtensa_F10, Xtensa_F11, Xtensa_F12, Xtensa_F13, Xtensa_F14, Xtensa_F15, Xtensa_F7, Xtensa_F6, Xtensa_F5, Xtensa_F4, Xtensa_F3, Xtensa_F2, Xtensa_F1, Xtensa_F0, }; - // SR Bit set. - static const uint8_t SRBits[] = { - 0x02, + // FPR Bit set. + static const uint8_t FPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, + }; + + // UR Register Class... + static const MCPhysReg UR[] = { + Xtensa_GPIO_OUT, Xtensa_EXPSTATE, Xtensa_THREADPTR, Xtensa_FCR, Xtensa_FSR, Xtensa_F64R_LO, Xtensa_F64R_HI, Xtensa_F64S, Xtensa_ACCX, Xtensa_QACC, Xtensa_FFT_BIT_WIDTH, Xtensa_SAR_BYTE, Xtensa_UA_STATE, + }; + + // UR Bit set. + static const uint8_t URBits[] = { + 0x08, 0xe0, 0x03, 0x80, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, + }; + + // MR Register Class... + static const MCPhysReg MR[] = { + Xtensa_M0, Xtensa_M1, Xtensa_M2, Xtensa_M3, + }; + + // MR Bit set. + static const uint8_t MRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, + }; + + // MR01 Register Class... + static const MCPhysReg MR01[] = { + Xtensa_M0, Xtensa_M1, + }; + + // MR01 Bit set. + static const uint8_t MR01Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, + }; + + // MR23 Register Class... + static const MCPhysReg MR23[] = { + Xtensa_M2, Xtensa_M3, + }; + + // MR23 Bit set. + static const uint8_t MR23Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, + }; + + // AE_DR Register Class... + static const MCPhysReg AE_DR[] = { + Xtensa_AED0, Xtensa_AED1, Xtensa_AED2, Xtensa_AED3, Xtensa_AED4, Xtensa_AED5, Xtensa_AED6, Xtensa_AED7, Xtensa_AED8, Xtensa_AED9, Xtensa_AED10, Xtensa_AED11, Xtensa_AED12, Xtensa_AED13, Xtensa_AED14, Xtensa_AED15, + }; + + // AE_DR Bit set. + static const uint8_t AE_DRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + + // AE_VALIGN Register Class... + static const MCPhysReg AE_VALIGN[] = { + Xtensa_U0, Xtensa_U1, Xtensa_U2, Xtensa_U3, + }; + + // AE_VALIGN Bit set. + static const uint8_t AE_VALIGNBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, + }; + + // QR Register Class... + static const MCPhysReg QR[] = { + Xtensa_Q0, Xtensa_Q1, Xtensa_Q2, Xtensa_Q3, Xtensa_Q4, Xtensa_Q5, Xtensa_Q6, Xtensa_Q7, + }; + + // QR Bit set. + static const uint8_t QRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, }; static const MCRegisterClass XtensaMCRegisterClasses[] = { - { AR, ARBits, sizeof(ARBits) }, + { BR, BRBits, sizeof(BRBits) }, + { BR2, BR2Bits, sizeof(BR2Bits) }, + { BR4, BR4Bits, sizeof(BR4Bits) }, { SR, SRBits, sizeof(SRBits) }, + { AR, ARBits, sizeof(ARBits) }, + { FPR, FPRBits, sizeof(FPRBits) }, + { UR, URBits, sizeof(URBits) }, + { MR, MRBits, sizeof(MRBits) }, + { MR01, MR01Bits, sizeof(MR01Bits) }, + { MR23, MR23Bits, sizeof(MR23Bits) }, + { AE_DR, AE_DRBits, sizeof(AE_DRBits) }, + { AE_VALIGN, AE_VALIGNBits, sizeof(AE_VALIGNBits) }, + { QR, QRBits, sizeof(QRBits) }, }; static const uint16_t XtensaRegEncodingTable[] = { 0, + 17, + 16, + 237, + 99, + 4, + 234, + 224, + 104, + 233, + 192, + 232, + 238, + 230, + 232, + 239, + 233, + 0, + 96, + 236, + 237, + 227, + 228, + 226, + 0, + 2, + 1, + 5, + 97, + 235, + 230, + 238, 3, + 240, 1, + 231, + 241, + 231, + 72, + 73, 0, 2, 3, @@ -121,6 +630,121 @@ static const uint16_t XtensaRegEncodingTable[] = { 13, 14, 15, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 240, + 241, + 242, + 176, + 208, + 144, + 145, + 160, + 161, + 177, + 178, + 179, + 180, + 181, + 182, + 183, + 194, + 195, + 196, + 197, + 198, + 199, + 209, + 210, + 211, + 212, + 213, + 214, + 215, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 128, + 129, + 32, + 33, + 34, + 35, + 244, + 245, + 246, + 247, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 12, + 0, + 1, + 2, + 3, + 235, + 234, + 236, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, }; #endif // GET_REGINFO_MC_DESC diff --git a/arch/Xtensa/XtensaGenSubtargetInfo.inc b/arch/Xtensa/XtensaGenSubtargetInfo.inc index 8ea1cbdff5..7726fd68e3 100644 --- a/arch/Xtensa/XtensaGenSubtargetInfo.inc +++ b/arch/Xtensa/XtensaGenSubtargetInfo.inc @@ -15,8 +15,41 @@ #undef GET_SUBTARGETINFO_ENUM enum { - Xtensa_FeatureDensity = 0, - Xtensa_NumSubtargetFeatures = 1 + Xtensa_FeatureATOMCTL = 0, + Xtensa_FeatureBoolean = 1, + Xtensa_FeatureCLAMPS = 2, + Xtensa_FeatureCoprocessor = 3, + Xtensa_FeatureDFPAccel = 4, + Xtensa_FeatureDebug = 5, + Xtensa_FeatureDensity = 6, + Xtensa_FeatureDiv32 = 7, + Xtensa_FeatureESP32S2Ops = 8, + Xtensa_FeatureESP32S3Ops = 9, + Xtensa_FeatureException = 10, + Xtensa_FeatureExtendedL32R = 11, + Xtensa_FeatureForcedAtomics = 12, + Xtensa_FeatureHIFI3 = 13, + Xtensa_FeatureHighPriInterrupts = 14, + Xtensa_FeatureInterrupt = 15, + Xtensa_FeatureLoop = 16, + Xtensa_FeatureMAC16 = 17, + Xtensa_FeatureMEMCTL = 18, + Xtensa_FeatureMINMAX = 19, + Xtensa_FeatureMiscSR = 20, + Xtensa_FeatureMul16 = 21, + Xtensa_FeatureMul32 = 22, + Xtensa_FeatureMul32High = 23, + Xtensa_FeatureNSA = 24, + Xtensa_FeaturePRID = 25, + Xtensa_FeatureRegionProtection = 26, + Xtensa_FeatureRelocatableVector = 27, + Xtensa_FeatureS32C1I = 28, + Xtensa_FeatureSEXT = 29, + Xtensa_FeatureSingleFloat = 30, + Xtensa_FeatureTHREADPTR = 31, + Xtensa_FeatureTimerInt = 32, + Xtensa_FeatureWindowed = 33, + Xtensa_NumSubtargetFeatures = 34 }; #endif // GET_SUBTARGETINFO_ENUM diff --git a/arch/Xtensa/XtensaInstPrinter.c b/arch/Xtensa/XtensaInstPrinter.c index a10bfe8dcf..952dcf4420 100644 --- a/arch/Xtensa/XtensaInstPrinter.c +++ b/arch/Xtensa/XtensaInstPrinter.c @@ -35,6 +35,7 @@ #include "../../SStream.h" #include "./priv.h" #include "../../Mapping.h" + #include "XtensaMapping.h" #include "../../MathExtras.h" @@ -45,32 +46,60 @@ static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O); static const char *getRegisterName(unsigned RegNo); -static void printOperand(MCInst *MI, int OpNum, SStream *O) +typedef MCRegister Register; + +static void printRegName(SStream *O, MCRegister Reg) +{ + SStream_concat0(O, getRegisterName(Reg)); +} + +static void printOp(MCInst *MI, MCOperand *MC, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_OPERAND, OpNum); - const MCOperand *MC = MCInst_getOperand(MI, (OpNum)); - if (MCOperand_isReg(MC)) { + if (MCOperand_isReg(MC)) SStream_concat0(O, getRegisterName(MCOperand_getReg(MC))); - } else if (MCOperand_isImm(MC)) { + else if (MCOperand_isImm(MC)) printInt64(O, MCOperand_getImm(MC)); - } else if (MCOperand_isExpr(MC)) { + else if (MCOperand_isExpr(MC)) printExpr(MCOperand_getExpr(MC), O); - } else + else CS_ASSERT("Invalid operand"); } +static void printOperand(MCInst *MI, const int op_num, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Operand, op_num); + printOp(MI, MCInst_getOperand(MI, op_num), O); +} + static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS) { - add_cs_detail(MI, XTENSA_OP_GROUP_MEMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_MemOperand, OpNum); SStream_concat0(OS, getRegisterName(MCOperand_getReg( MCInst_getOperand(MI, (OpNum))))); SStream_concat0(OS, ", "); - printInt64(OS, MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1))); + printOp(MI, MCInst_getOperand(MI, OpNum + 1), OS); } static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS) { - add_cs_detail(MI, XTENSA_OP_GROUP_BRANCHTARGET, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_BranchTarget, OpNum); + MCOperand *MC = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Val = MCOperand_getImm(MC) + 4; + SStream_concat0(OS, ". "); + if (Val > 0) + SStream_concat0(OS, "+"); + + printInt64(OS, Val); + } else if (MCOperand_isExpr(MC)) + CS_ASSERT_RET(0 && "unimplemented expr printing"); + else + CS_ASSERT(0 && "Invalid operand"); +} + +static inline void printLoopTarget(MCInst *MI, int OpNum, SStream *OS) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_LoopTarget, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Val = MCOperand_getImm(MC) + 4; @@ -80,14 +109,14 @@ static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS) printInt64(OS, Val); } else if (MCOperand_isExpr(MC)) - MCExpr_print(MCOperand_getExpr(MC), O, NULL, true); + CS_ASSERT_RET(0 && "unimplemented expr printing"); else CS_ASSERT(0 && "Invalid operand"); } static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS) { - add_cs_detail(MI, XTENSA_OP_GROUP_JUMPTARGET, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_JumpTarget, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MC)) { int64_t Val = MCOperand_getImm(MC) + 4; @@ -97,15 +126,15 @@ static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS) printInt64(OS, Val); } else if (MCOperand_isExpr(MC)) - MCExpr_print(MCOperand_getExpr(MC), O, NULL, true); + CS_ASSERT_RET(0 && "unimplemented expr printing"); else - assert(0 && "Invalid operand"); + CS_ASSERT(0 && "Invalid operand"); ; } static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS) { - add_cs_detail(MI, XTENSA_OP_GROUP_CALLOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_CallOperand, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MC)) { int64_t Val = MCOperand_getImm(MC) + 4; @@ -115,38 +144,27 @@ static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS) printInt64(OS, Val); } else if (MCOperand_isExpr(MC)) - MCExpr_print(MCOperand_getExpr(MC), O, NULL, true); + CS_ASSERT_RET(0 && "unimplemented expr printing"); else - assert(0 && "Invalid operand"); + CS_ASSERT(0 && "Invalid operand"); } static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_L32RTARGET, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_L32RTarget, OpNum); MCOperand *MC = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MC)) { - int64_t Value = - MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); - int32_t InstrOff = (uint32_t)OneExtend32(Value, 16) << 2; - CS_ASSERT( - (InstrOff >= -262144 && InstrOff <= -4) && - "Invalid argument, value must be in ranges [-262144,-4]"); SStream_concat0(O, ". "); - if (MI->csh->LITBASE & 0x1) { - Value = ((MI->csh->LITBASE & 0xfffff000) >> 12) + InstrOff; - } else { - Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff; - } - printInt64(O, Value); + printInt64(O, Xtensa_L32R_Value(MI, OpNum)); } else if (MCOperand_isExpr(MC)) - MCExpr_print(MCOperand_getExpr(MC), O, NULL, true); + CS_ASSERT_RET(0 && "unimplemented expr printing"); else - assert(0 && "Invalid operand"); + CS_ASSERT(0 && "Invalid operand"); } static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_IMM8_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -161,7 +179,7 @@ static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8_sh8_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -174,9 +192,23 @@ static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O) printOperand(MI, OpNum, O); } +static inline void printImm12_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm12_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= -2048 && Value <= 2047) && + "Invalid argument, value must be in ranges [-2048,2047]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_IMM12M_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm12m_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -190,7 +222,7 @@ static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_UIMM4_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Uimm4_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -202,7 +234,7 @@ static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_UIMM5_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Uimm5_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -214,7 +246,7 @@ static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Shimm1_31_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -225,9 +257,22 @@ static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O) printOperand(MI, OpNum, O); } +static inline void printShimm0_31_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Shimm0_31_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= 0 && Value <= 31) && + "Invalid argument, value must be in range [0,31]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_IMM1_16_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm1_16_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -238,9 +283,95 @@ static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O) printOperand(MI, OpNum, O); } +static inline void printImm1n_15_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm1n_15_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= -1 && (Value != 0) && Value <= 15) && + "Invalid argument, value must be in ranges <-1,-1> or <1,15>"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printImm32n_95_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm32n_95_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= -32 && Value <= 95) && + "Invalid argument, value must be in ranges <-32,95>"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printImm8n_7_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8n_7_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= -8 && Value <= 7) && + "Invalid argument, value must be in ranges <-8,7>"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printImm64n_4n_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm64n_4n_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= -64 && Value <= -4) & + ((Value & 0x3) == 0) && + "Invalid argument, value must be in ranges <-64,-4>"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printOffset8m32_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset8m32_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= 0 && Value <= 1020 && ((Value & 0x3) == 0)) && + "Invalid argument, value must be multiples of four in range [0,1020]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printEntry_Imm12_AsmOperand(MCInst *MI, int OpNum, + SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Entry_Imm12_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= 0 && Value <= 32760) && + "Invalid argument, value must be multiples of eight in range " + "<0,32760>"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_B4CONST_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_B4const_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -273,7 +404,7 @@ static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O) static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND, OpNum); + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_B4constu_AsmOperand, OpNum); if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); @@ -304,14 +435,266 @@ static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O) printOperand(MI, OpNum, O); } +static inline void printImm7_22_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm7_22_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= 7 && Value <= 22) && + "Invalid argument, value must be in range <7,22>"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printSelect_2_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_2_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= 0 && Value <= 1) && + "Invalid argument, value must be in range [0,1]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printSelect_4_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_4_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= 0 && Value <= 3) && + "Invalid argument, value must be in range [0,3]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printSelect_8_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_8_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= 0 && Value <= 7) && + "Invalid argument, value must be in range [0,7]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printSelect_16_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_16_AsmOperand, OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= 0 && Value <= 15) && + "Invalid argument, value must be in range [0,15]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printSelect_256_AsmOperand(MCInst *MI, int OpNum, SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_256_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= 0 && Value <= 255) && + "Invalid argument, value must be in range [0,255]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printOffset_16_16_AsmOperand(MCInst *MI, int OpNum, + SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_16_16_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= -128 && Value <= 112 && (Value & 0xf) == 0) && + "Invalid argument, value must be in range [-128,112], first 4 bits " + "should be zero"); + printInt64(O, Value); + } else { + printOperand(MI, OpNum, O); + } +} + +static inline void printOffset_256_8_AsmOperand(MCInst *MI, int OpNum, + SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_8_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= -1024 && Value <= 1016 && + (Value & 0x7) == 0) && + "Invalid argument, value must be in range [-1024,1016], first 3 " + "bits should be zero"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printOffset_256_16_AsmOperand(MCInst *MI, int OpNum, + SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_16_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= -2048 && Value <= 2032 && + (Value & 0xf) == 0) && + "Invalid argument, value must be in range [-2048,2032], first 4 " + "bits should be zero"); + printInt64(O, Value); + } else { + printOperand(MI, OpNum, O); + } +} + +static inline void printOffset_256_4_AsmOperand(MCInst *MI, int OpNum, + SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_4_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= -512 && Value <= 508 && (Value & 0x3) == 0) && + "Invalid argument, value must be in range [-512,508], first 2 bits " + "should be zero"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printOffset_128_2_AsmOperand(MCInst *MI, int OpNum, + SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_128_2_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= 0 && Value <= 254 && (Value & 0x1) == 0) && + "Invalid argument, value must be in range [0,254], first bit should " + "be zero"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printOffset_128_1_AsmOperand(MCInst *MI, int OpNum, + SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_128_1_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Value >= 0 && Value <= 127) && + "Invalid argument, value must be in range [0,127]"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +static inline void printOffset_64_16_AsmOperand(MCInst *MI, int OpNum, + SStream *O) +{ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_64_16_AsmOperand, + OpNum); + if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) { + int64_t Value = + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT( + (Value >= -512 && Value <= 496 && (Value & 0xf) == 0) && + "Invalid argument, value must be in range [-512,496], first 4 bits " + "should be zero"); + printInt64(O, Value); + } else + printOperand(MI, OpNum, O); +} + +#define IMPL_printImmOperand(N, L, H, S) \ + static void printImmOperand_##N(MCInst *MI, int OpNum, SStream *O) \ + { \ + Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_ImmOperand_##N, \ + OpNum); \ + MCOperand *MC = MCInst_getOperand(MI, (OpNum)); \ + if (MCOperand_isImm(MC)) { \ + int64_t Value = MCOperand_getImm(MC); \ + CS_ASSERT((Value >= L && Value <= H && \ + ((Value % S) == 0)) && \ + "Invalid argument"); \ + printInt64(O, Value); \ + } else { \ + printOperand(MI, OpNum, O); \ + } \ + } + +IMPL_printImmOperand(minus64_56_8, -64, 56, 8); +IMPL_printImmOperand(minus32_28_4, -32, 28, 4); +IMPL_printImmOperand(minus16_47_1, -16, 47, 1); +IMPL_printImmOperand(minus16_14_2, -16, 14, 2); +IMPL_printImmOperand(0_56_8, 0, 56, 8); +IMPL_printImmOperand(0_3_1, 0, 3, 1); +IMPL_printImmOperand(0_63_1, 0, 63, 1); + #include "XtensaGenAsmWriter.inc" -const char *Xtensa_LLVM_getRegisterName(unsigned RegNo) +static void printInst(MCInst *MI, uint64_t Address, const char *Annot, + SStream *O) { - return getRegisterName(RegNo); + unsigned Opcode = MCInst_getOpcode(MI); + + switch (Opcode) { + case Xtensa_WSR: { + // INTERRUPT mnemonic is read-only, so use INTSET mnemonic instead + Register SR = MCOperand_getReg(MCInst_getOperand(MI, (0))); + if (SR == Xtensa_INTERRUPT) { + Register Reg = + MCOperand_getReg(MCInst_getOperand(MI, (1))); + SStream_concat1(O, '\t'); + SStream_concat(O, "%s", "wsr"); + SStream_concat0(O, "\t"); + + printRegName(O, Reg); + SStream_concat(O, "%s", ", "); + SStream_concat0(O, "intset"); + ; + return; + } + } + } + printInstruction(MI, Address, O); } void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O) { - printInstruction(MI, Address, O); + printInst(MI, Address, NULL, O); +} + +const char *Xtensa_LLVM_getRegisterName(unsigned RegNo) +{ + return getRegisterName(RegNo); } diff --git a/arch/Xtensa/XtensaMapping.c b/arch/Xtensa/XtensaMapping.c index f6b94e52d5..9f6e0c8009 100644 --- a/arch/Xtensa/XtensaMapping.c +++ b/arch/Xtensa/XtensaMapping.c @@ -59,6 +59,12 @@ static void set_instr_map_data(MCInst *MI) map_implicit_reads(MI, mapping_insns); map_implicit_writes(MI, mapping_insns); map_groups(MI, mapping_insns); + + const xtensa_suppl_info *suppl_info = + map_get_suppl_info(MI, mapping_insns); + if (suppl_info) { + Xtensa_get_detail(MI)->format = suppl_info->form; + } #endif } @@ -162,12 +168,29 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read, } #endif -void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args) +int64_t Xtensa_L32R_Value(MCInst *MI, int op_num) { - int op_num = va_arg(args, int); + int64_t InstrOff = MCOperand_getImm(MCInst_getOperand(MI, (op_num))); + CS_ASSERT((InstrOff >= -262144 && InstrOff <= -4) && + "Invalid argument, value must be in ranges [-262144,-4]"); + int64_t Value = 0; + if (MI->csh->LITBASE & 0x1) { + Value = (MI->csh->LITBASE & 0xfffff000) + InstrOff; + } else { + Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff; + } + return Value; +} + +void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num) +{ + if (!detail_is_set(MI)) { + return; + } + cs_xtensa_op *xop = Xtensa_get_detail_op(MI, 0); switch (op_group) { - case XTENSA_OP_GROUP_OPERAND: { + case Xtensa_OP_GROUP_Operand: { const MCOperand *MC = MCInst_getOperand(MI, op_num); if (MCOperand_isReg(MC)) { xop->type = XTENSA_OP_REG; @@ -177,50 +200,68 @@ void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args) xop->imm = MC->ImmVal; } } break; - case XTENSA_OP_GROUP_IMM8_ASMOPERAND: - case XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND: - case XTENSA_OP_GROUP_UIMM5_ASMOPERAND: - case XTENSA_OP_GROUP_B4CONST_ASMOPERAND: - case XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND: - case XTENSA_OP_GROUP_IMM1_16_ASMOPERAND: - case XTENSA_OP_GROUP_IMM12M_ASMOPERAND: - case XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND: - case XTENSA_OP_GROUP_UIMM4_ASMOPERAND: { + case Xtensa_OP_GROUP_Imm1_16_AsmOperand: + case Xtensa_OP_GROUP_Imm1n_15_AsmOperand: + case Xtensa_OP_GROUP_Imm7_22_AsmOperand: + case Xtensa_OP_GROUP_Imm8_AsmOperand: + case Xtensa_OP_GROUP_Imm8_sh8_AsmOperand: + case Xtensa_OP_GROUP_Imm8n_7_AsmOperand: + case Xtensa_OP_GROUP_Imm12_AsmOperand: + case Xtensa_OP_GROUP_Imm12m_AsmOperand: + case Xtensa_OP_GROUP_Imm32n_95_AsmOperand: + case Xtensa_OP_GROUP_Imm64n_4n_AsmOperand: + case Xtensa_OP_GROUP_ImmOperand_minus32_28_4: + case Xtensa_OP_GROUP_Uimm5_AsmOperand: + case Xtensa_OP_GROUP_Uimm4_AsmOperand: + case Xtensa_OP_GROUP_Shimm0_31_AsmOperand: + case Xtensa_OP_GROUP_Shimm1_31_AsmOperand: + case Xtensa_OP_GROUP_B4const_AsmOperand: + case Xtensa_OP_GROUP_B4constu_AsmOperand: + case Xtensa_OP_GROUP_ImmOperand_minus16_14_2: + case Xtensa_OP_GROUP_ImmOperand_minus64_56_8: + case Xtensa_OP_GROUP_ImmOperand_0_56_8: + case Xtensa_OP_GROUP_ImmOperand_minus16_47_1: + case Xtensa_OP_GROUP_ImmOperand_0_3_1: + case Xtensa_OP_GROUP_ImmOperand_0_63_1: + case Xtensa_OP_GROUP_Entry_Imm12_AsmOperand: + case Xtensa_OP_GROUP_Offset8m32_AsmOperand: + case Xtensa_OP_GROUP_Select_4_AsmOperand: + case Xtensa_OP_GROUP_Select_2_AsmOperand: + case Xtensa_OP_GROUP_Select_8_AsmOperand: + case Xtensa_OP_GROUP_Offset_16_16_AsmOperand: + case Xtensa_OP_GROUP_Offset_256_8_AsmOperand: + case Xtensa_OP_GROUP_Offset_256_16_AsmOperand: + case Xtensa_OP_GROUP_Offset_256_4_AsmOperand: + case Xtensa_OP_GROUP_Select_16_AsmOperand: + case Xtensa_OP_GROUP_Offset_128_2_AsmOperand: + case Xtensa_OP_GROUP_Offset_128_1_AsmOperand: + case Xtensa_OP_GROUP_Offset_64_16_AsmOperand: + case Xtensa_OP_GROUP_Select_256_AsmOperand: { int64_t val = MCOperand_getImm(MCInst_getOperand(MI, op_num)); xop->type = XTENSA_OP_IMM; xop->imm = (int32_t)val; } break; - case XTENSA_OP_GROUP_BRANCHTARGET: - case XTENSA_OP_GROUP_JUMPTARGET: - case XTENSA_OP_GROUP_CALLOPERAND: { + case Xtensa_OP_GROUP_BranchTarget: + case Xtensa_OP_GROUP_JumpTarget: + case Xtensa_OP_GROUP_CallOperand: + case Xtensa_OP_GROUP_LoopTarget: { int64_t val = MCOperand_getImm(MCInst_getOperand(MI, op_num)) + 4; xop->type = XTENSA_OP_IMM; xop->imm = (int32_t)val; } break; - case XTENSA_OP_GROUP_L32RTARGET: { - int64_t Value = - MCOperand_getImm(MCInst_getOperand(MI, (op_num))); - int32_t InstrOff = (uint32_t)OneExtend32(Value, 16) << 2; - CS_ASSERT( - (InstrOff >= -262144 && InstrOff <= -4) && - "Invalid argument, value must be in ranges [-262144,-4]"); - if (MI->csh->LITBASE & 0x1) { - Value = ((MI->csh->LITBASE & 0xfffff000) >> 12) + InstrOff; - } else { - Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff; - } + case Xtensa_OP_GROUP_L32RTarget: { xop->type = XTENSA_OP_L32R; - xop->imm = (int32_t)Value; + xop->imm = (int32_t)Xtensa_L32R_Value(MI, op_num); } break; - case XTENSA_OP_GROUP_MEMOPERAND: { + case Xtensa_OP_GROUP_MemOperand: { unsigned reg = MCOperand_getReg(MCInst_getOperand(MI, (op_num))); int64_t imm8 = MCOperand_getImm(MCInst_getOperand(MI, op_num + 1)); xop->type = XTENSA_OP_MEM; xop->mem.base = reg; - xop->mem.disp = (uint8_t)imm8; + xop->mem.disp = (int32_t)imm8; } break; } diff --git a/arch/Xtensa/XtensaMapping.h b/arch/Xtensa/XtensaMapping.h index 33e2269c0e..2f73e58bf5 100644 --- a/arch/Xtensa/XtensaMapping.h +++ b/arch/Xtensa/XtensaMapping.h @@ -10,6 +10,8 @@ typedef enum { #include "XtensaGenCSOpGroup.inc" } xtensa_op_group; +int64_t Xtensa_L32R_Value(MCInst *MI, int op_num); + void Xtensa_init_mri(MCRegisterInfo *mri); void Xtensa_printer(MCInst *MI, SStream *OS, void *info); bool Xtensa_disasm(csh handle, const uint8_t *code, size_t code_len, @@ -24,16 +26,6 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_write_count); #endif -void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args); - -static inline void add_cs_detail(MCInst *MI, xtensa_op_group op_group, ...) -{ - if (!detail_is_set(MI)) - return; - va_list args; - va_start(args, op_group); - Xtensa_add_cs_detail(MI, op_group, args); - va_end(args); -} +void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num); #endif diff --git a/arch/Xtensa/priv.h b/arch/Xtensa/priv.h index 3fc36cec87..587881bf87 100644 --- a/arch/Xtensa/priv.h +++ b/arch/Xtensa/priv.h @@ -14,4 +14,7 @@ #define GET_INSTRINFO_ENUM #include "XtensaGenInstrInfo.inc" +#define GET_SUBTARGETINFO_ENUM +#include "XtensaGenSubtargetInfo.inc" + #endif //CAPSTONE_PRIV_H diff --git a/bindings/python/MANIFEST.in b/bindings/python/MANIFEST.in index 98776c7d98..6246aac056 100644 --- a/bindings/python/MANIFEST.in +++ b/bindings/python/MANIFEST.in @@ -1,5 +1,8 @@ recursive-include src * -include LICENSE.TXT -include README.txt -include BUILDING.txt -include Makefile +recursive-include prebuilt * +include BUILDING.md +graft capstone/lib +graft capstone/include +global-include *.dll +global-include *.dylib +global-include *.so.* diff --git a/bindings/python/Makefile b/bindings/python/Makefile deleted file mode 100644 index 9b44705e4a..0000000000 --- a/bindings/python/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -PYTHON3 ?= python3 - -.PHONY: gen_const install sdist bdist clean check - -gen_const: - cd .. && $(PYTHON3) const_generator.py python - -install: - rm -rf src/ - if test -n "${DESTDIR}"; then \ - $(PYTHON3) setup.py build install --root="${DESTDIR}"; \ - else \ - $(PYTHON3) setup.py build install; \ - fi - -# build & upload PyPi package with source code of the core -sdist: - rm -rf src/ dist/ - $(PYTHON3) setup.py sdist register upload - -# build & upload PyPi package with prebuilt core -bdist: - rm -rf src/ dist/ - $(PYTHON3) setup.py bdist_wheel register upload - -clean: - rm -rf build/ src/ dist/ *.egg-info - rm -rf capstone/lib capstone/include pyx/lib pyx/include - rm -f pyx/*.c pyx/__init__.py - for f in capstone/*.py; do rm -f pyx/$$(basename $$f)x; done - rm -f MANIFEST - rm -f *.pyc capstone/*.pyc - - -TESTS = test_basic.py test_detail.py test_arm.py test_aarch64.py test_m68k.py test_mips.py -TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py -TESTS += test_m680x.py test_skipdata.py test_mos65xx.py test_bpf.py test_riscv.py -TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py test_hppa.py -TESTS += test_lite.py test_iter.py test_customized_mnem.py test_alpha.py test_xtensa.py - -check: - @for t in $(TESTS); do \ - echo Check $$t ... ; \ - ./tests/$$t > /dev/null; \ - if [ $$? -eq 0 ]; then echo OK; else echo FAILED; exit 1; fi \ - done - diff --git a/bindings/python/README.txt b/bindings/python/README.txt index ed7f711a67..9fda7d8819 100644 --- a/bindings/python/README.txt +++ b/bindings/python/README.txt @@ -1,12 +1,12 @@ To install Capstone, you should run `pip install capstone`. -If you would like to build Capstone with just the source distribution, without -pip, just run `python setup.py install` in the folder with setup.py in it. +If you would like to build and install Capstone with just the source distribution, +just run `python -m pip install .`, considering you are in the folder with setup.py in it. In order to use this source distribution, you will need an environment that can compile C code. On Linux, this is usually easy, but on Windows, this involves installing Visual Studio and using the "Developer Command Prompt" to perform the -installation. See BUILDING.txt for more information. +installation. See BUILDING.md for more information. By default, attempting to install the python bindings will trigger a build of the capstone native core. If this is undesirable for whatever reason, for diff --git a/bindings/python/build_wheel.sh b/bindings/python/build_wheel.sh deleted file mode 100755 index 38a9ceccf3..0000000000 --- a/bindings/python/build_wheel.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/bash -set -e -x - -cd bindings/python -if [ -f /opt/python/cp311-cp311/bin/python3 ];then - # Use manylinux Python - /opt/python/cp311-cp311/bin/python3 -m pip install wheel - /opt/python/cp311-cp311/bin/python3 setup.py bdist_wheel -else - python3 -m pip install wheel - python3 setup.py bdist_wheel -fi - -cd dist -auditwheel repair *.whl -mv -f wheelhouse/*.whl . \ No newline at end of file diff --git a/bindings/python/capstone/xtensa.py b/bindings/python/capstone/xtensa.py index 0e39470d18..bf0f6be1cb 100644 --- a/bindings/python/capstone/xtensa.py +++ b/bindings/python/capstone/xtensa.py @@ -8,7 +8,7 @@ class XtensaOpMem(ctypes.Structure): _fields_ = ( ("base", ctypes.c_uint8), - ("disp", ctypes.c_uint8), + ("disp", ctypes.c_int32), ) @@ -45,6 +45,7 @@ class CsXtensa(ctypes.Structure): _fields_ = ( ("op_count", ctypes.c_uint8), ("operands", XtensaOp * 8), + ("format", ctypes.c_uint32), ) diff --git a/bindings/python/capstone/xtensa_const.py b/bindings/python/capstone/xtensa_const.py index 428ae02145..fa716d9564 100644 --- a/bindings/python/capstone/xtensa_const.py +++ b/bindings/python/capstone/xtensa_const.py @@ -2,116 +2,1645 @@ # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xtensa_const.py] XTENSA_REG_INVALID = 0 -XTENSA_REG_SAR = 1 -XTENSA_REG_SP = 2 -XTENSA_REG_A0 = 3 -XTENSA_REG_A2 = 4 -XTENSA_REG_A3 = 5 -XTENSA_REG_A4 = 6 -XTENSA_REG_A5 = 7 -XTENSA_REG_A6 = 8 -XTENSA_REG_A7 = 9 -XTENSA_REG_A8 = 10 -XTENSA_REG_A9 = 11 -XTENSA_REG_A10 = 12 -XTENSA_REG_A11 = 13 -XTENSA_REG_A12 = 14 -XTENSA_REG_A13 = 15 -XTENSA_REG_A14 = 16 -XTENSA_REG_A15 = 17 -XTENSA_REG_ENDING = 18 +XTENSA_REG_ACCHI = 1 +XTENSA_REG_ACCLO = 2 +XTENSA_REG_ACCX = 3 +XTENSA_REG_ATOMCTL = 4 +XTENSA_REG_BREG = 5 +XTENSA_REG_CCOUNT = 6 +XTENSA_REG_CPENABLE = 7 +XTENSA_REG_DDR = 8 +XTENSA_REG_DEBUGCAUSE = 9 +XTENSA_REG_DEPC = 10 +XTENSA_REG_EXCCAUSE = 11 +XTENSA_REG_EXCVADDR = 12 +XTENSA_REG_EXPSTATE = 13 +XTENSA_REG_FCR = 14 +XTENSA_REG_FFT_BIT_WIDTH = 15 +XTENSA_REG_FSR = 16 +XTENSA_REG_GPIO_OUT = 17 +XTENSA_REG_IBREAKENABLE = 18 +XTENSA_REG_ICOUNT = 19 +XTENSA_REG_ICOUNTLEVEL = 20 +XTENSA_REG_INTCLEAR = 21 +XTENSA_REG_INTENABLE = 22 +XTENSA_REG_INTERRUPT = 23 +XTENSA_REG_LBEG = 24 +XTENSA_REG_LCOUNT = 25 +XTENSA_REG_LEND = 26 +XTENSA_REG_LITBASE = 27 +XTENSA_REG_MEMCTL = 28 +XTENSA_REG_PRID = 29 +XTENSA_REG_PS = 30 +XTENSA_REG_QACC = 31 +XTENSA_REG_SAR = 32 +XTENSA_REG_SAR_BYTE = 33 +XTENSA_REG_SP = 34 +XTENSA_REG_THREADPTR = 35 +XTENSA_REG_UA_STATE = 36 +XTENSA_REG_VECBASE = 37 +XTENSA_REG_WINDOWBASE = 38 +XTENSA_REG_WINDOWSTART = 39 +XTENSA_REG_A0 = 40 +XTENSA_REG_A2 = 41 +XTENSA_REG_A3 = 42 +XTENSA_REG_A4 = 43 +XTENSA_REG_A5 = 44 +XTENSA_REG_A6 = 45 +XTENSA_REG_A7 = 46 +XTENSA_REG_A8 = 47 +XTENSA_REG_A9 = 48 +XTENSA_REG_A10 = 49 +XTENSA_REG_A11 = 50 +XTENSA_REG_A12 = 51 +XTENSA_REG_A13 = 52 +XTENSA_REG_A14 = 53 +XTENSA_REG_A15 = 54 +XTENSA_REG_AED0 = 55 +XTENSA_REG_AED1 = 56 +XTENSA_REG_AED2 = 57 +XTENSA_REG_AED3 = 58 +XTENSA_REG_AED4 = 59 +XTENSA_REG_AED5 = 60 +XTENSA_REG_AED6 = 61 +XTENSA_REG_AED7 = 62 +XTENSA_REG_AED8 = 63 +XTENSA_REG_AED9 = 64 +XTENSA_REG_AED10 = 65 +XTENSA_REG_AED11 = 66 +XTENSA_REG_AED12 = 67 +XTENSA_REG_AED13 = 68 +XTENSA_REG_AED14 = 69 +XTENSA_REG_AED15 = 70 +XTENSA_REG_B0 = 71 +XTENSA_REG_B1 = 72 +XTENSA_REG_B2 = 73 +XTENSA_REG_B3 = 74 +XTENSA_REG_B4 = 75 +XTENSA_REG_B5 = 76 +XTENSA_REG_B6 = 77 +XTENSA_REG_B7 = 78 +XTENSA_REG_B8 = 79 +XTENSA_REG_B9 = 80 +XTENSA_REG_B10 = 81 +XTENSA_REG_B11 = 82 +XTENSA_REG_B12 = 83 +XTENSA_REG_B13 = 84 +XTENSA_REG_B14 = 85 +XTENSA_REG_B15 = 86 +XTENSA_REG_CCOMPARE0 = 87 +XTENSA_REG_CCOMPARE1 = 88 +XTENSA_REG_CCOMPARE2 = 89 +XTENSA_REG_CONFIGID0 = 90 +XTENSA_REG_CONFIGID1 = 91 +XTENSA_REG_DBREAKA0 = 92 +XTENSA_REG_DBREAKA1 = 93 +XTENSA_REG_DBREAKC0 = 94 +XTENSA_REG_DBREAKC1 = 95 +XTENSA_REG_EPC1 = 96 +XTENSA_REG_EPC2 = 97 +XTENSA_REG_EPC3 = 98 +XTENSA_REG_EPC4 = 99 +XTENSA_REG_EPC5 = 100 +XTENSA_REG_EPC6 = 101 +XTENSA_REG_EPC7 = 102 +XTENSA_REG_EPS2 = 103 +XTENSA_REG_EPS3 = 104 +XTENSA_REG_EPS4 = 105 +XTENSA_REG_EPS5 = 106 +XTENSA_REG_EPS6 = 107 +XTENSA_REG_EPS7 = 108 +XTENSA_REG_EXCSAVE1 = 109 +XTENSA_REG_EXCSAVE2 = 110 +XTENSA_REG_EXCSAVE3 = 111 +XTENSA_REG_EXCSAVE4 = 112 +XTENSA_REG_EXCSAVE5 = 113 +XTENSA_REG_EXCSAVE6 = 114 +XTENSA_REG_EXCSAVE7 = 115 +XTENSA_REG_F0 = 116 +XTENSA_REG_F1 = 117 +XTENSA_REG_F2 = 118 +XTENSA_REG_F3 = 119 +XTENSA_REG_F4 = 120 +XTENSA_REG_F5 = 121 +XTENSA_REG_F6 = 122 +XTENSA_REG_F7 = 123 +XTENSA_REG_F8 = 124 +XTENSA_REG_F9 = 125 +XTENSA_REG_F10 = 126 +XTENSA_REG_F11 = 127 +XTENSA_REG_F12 = 128 +XTENSA_REG_F13 = 129 +XTENSA_REG_F14 = 130 +XTENSA_REG_F15 = 131 +XTENSA_REG_IBREAKA0 = 132 +XTENSA_REG_IBREAKA1 = 133 +XTENSA_REG_M0 = 134 +XTENSA_REG_M1 = 135 +XTENSA_REG_M2 = 136 +XTENSA_REG_M3 = 137 +XTENSA_REG_MISC0 = 138 +XTENSA_REG_MISC1 = 139 +XTENSA_REG_MISC2 = 140 +XTENSA_REG_MISC3 = 141 +XTENSA_REG_Q0 = 142 +XTENSA_REG_Q1 = 143 +XTENSA_REG_Q2 = 144 +XTENSA_REG_Q3 = 145 +XTENSA_REG_Q4 = 146 +XTENSA_REG_Q5 = 147 +XTENSA_REG_Q6 = 148 +XTENSA_REG_Q7 = 149 +XTENSA_REG_SCOMPARE1 = 150 +XTENSA_REG_U0 = 151 +XTENSA_REG_U1 = 152 +XTENSA_REG_U2 = 153 +XTENSA_REG_U3 = 154 +XTENSA_REG_F64R_HI = 155 +XTENSA_REG_F64R_LO = 156 +XTENSA_REG_F64S = 157 +XTENSA_REG_B0_B1 = 158 +XTENSA_REG_B2_B3 = 159 +XTENSA_REG_B4_B5 = 160 +XTENSA_REG_B6_B7 = 161 +XTENSA_REG_B8_B9 = 162 +XTENSA_REG_B10_B11 = 163 +XTENSA_REG_B12_B13 = 164 +XTENSA_REG_B14_B15 = 165 +XTENSA_REG_B0_B1_B2_B3 = 166 +XTENSA_REG_B4_B5_B6_B7 = 167 +XTENSA_REG_B8_B9_B10_B11 = 168 +XTENSA_REG_B12_B13_B14_B15 = 169 +XTENSA_REG_ENDING = 170 XTENSA_INS_INVALID = 0 XTENSA_INS_ABS = 1 -XTENSA_INS_ADD = 2 -XTENSA_INS_ADDI = 3 -XTENSA_INS_ADDMI = 4 -XTENSA_INS_ADDX2 = 5 -XTENSA_INS_ADDX4 = 6 -XTENSA_INS_ADDX8 = 7 -XTENSA_INS_AND = 8 -XTENSA_INS_BALL = 9 -XTENSA_INS_BANY = 10 -XTENSA_INS_BBC = 11 -XTENSA_INS_BBCI = 12 -XTENSA_INS_BBS = 13 -XTENSA_INS_BBSI = 14 -XTENSA_INS_BEQ = 15 -XTENSA_INS_BEQI = 16 -XTENSA_INS_BEQZ = 17 -XTENSA_INS_BGE = 18 -XTENSA_INS_BGEI = 19 -XTENSA_INS_BGEU = 20 -XTENSA_INS_BGEUI = 21 -XTENSA_INS_BGEZ = 22 -XTENSA_INS_BLT = 23 -XTENSA_INS_BLTI = 24 -XTENSA_INS_BLTU = 25 -XTENSA_INS_BLTUI = 26 -XTENSA_INS_BLTZ = 27 -XTENSA_INS_BNALL = 28 -XTENSA_INS_BNE = 29 -XTENSA_INS_BNEI = 30 -XTENSA_INS_BNEZ = 31 -XTENSA_INS_BNONE = 32 -XTENSA_INS_CALL0 = 33 -XTENSA_INS_CALLX0 = 34 -XTENSA_INS_DSYNC = 35 -XTENSA_INS_ESYNC = 36 -XTENSA_INS_EXTUI = 37 -XTENSA_INS_EXTW = 38 -XTENSA_INS_ISYNC = 39 -XTENSA_INS_J = 40 -XTENSA_INS_JX = 41 -XTENSA_INS_L16SI = 42 -XTENSA_INS_L16UI = 43 -XTENSA_INS_L32I = 44 -XTENSA_INS_L32R = 45 -XTENSA_INS_L8UI = 46 -XTENSA_INS_MEMW = 47 -XTENSA_INS_MOVEQZ = 48 -XTENSA_INS_MOVGEZ = 49 -XTENSA_INS_MOVI = 50 -XTENSA_INS_MOVLTZ = 51 -XTENSA_INS_MOVNEZ = 52 -XTENSA_INS_NEG = 53 -XTENSA_INS_NOP = 54 -XTENSA_INS_OR = 55 -XTENSA_INS_RET = 56 -XTENSA_INS_RSR = 57 -XTENSA_INS_RSYNC = 58 -XTENSA_INS_S16I = 59 -XTENSA_INS_S32I = 60 -XTENSA_INS_S8I = 61 -XTENSA_INS_SLL = 62 -XTENSA_INS_SLLI = 63 -XTENSA_INS_SRA = 64 -XTENSA_INS_SRAI = 65 -XTENSA_INS_SRC = 66 -XTENSA_INS_SRL = 67 -XTENSA_INS_SRLI = 68 -XTENSA_INS_SSA8L = 69 -XTENSA_INS_SSAI = 70 -XTENSA_INS_SSL = 71 -XTENSA_INS_SSR = 72 -XTENSA_INS_SUB = 73 -XTENSA_INS_SUBX2 = 74 -XTENSA_INS_SUBX4 = 75 -XTENSA_INS_SUBX8 = 76 -XTENSA_INS_WSR = 77 -XTENSA_INS_XOR = 78 -XTENSA_INS_XSR = 79 +XTENSA_INS_ABS_S = 2 +XTENSA_INS_ADD = 3 +XTENSA_INS_ADDEXPM_S = 4 +XTENSA_INS_ADDEXP_S = 5 +XTENSA_INS_ADDI = 6 +XTENSA_INS_ADDI_N = 7 +XTENSA_INS_ADDMI = 8 +XTENSA_INS_ADDX2 = 9 +XTENSA_INS_ADDX4 = 10 +XTENSA_INS_ADDX8 = 11 +XTENSA_INS_ADD_N = 12 +XTENSA_INS_ADD_S = 13 +XTENSA_INS_AE_ABS16S = 14 +XTENSA_INS_AE_ABS24S = 15 +XTENSA_INS_AE_ABS32 = 16 +XTENSA_INS_AE_ABS32S = 17 +XTENSA_INS_AE_ABS64 = 18 +XTENSA_INS_AE_ABS64S = 19 +XTENSA_INS_AE_ADD16 = 20 +XTENSA_INS_AE_ADD16S = 21 +XTENSA_INS_AE_ADD24S = 22 +XTENSA_INS_AE_ADD32 = 23 +XTENSA_INS_AE_ADD32S = 24 +XTENSA_INS_AE_ADD32_HL_LH = 25 +XTENSA_INS_AE_ADD64 = 26 +XTENSA_INS_AE_ADD64S = 27 +XTENSA_INS_AE_ADDBRBA32 = 28 +XTENSA_INS_AE_ADDSUB32 = 29 +XTENSA_INS_AE_ADDSUB32S = 30 +XTENSA_INS_AE_AND = 31 +XTENSA_INS_AE_CVT32X2F16_10 = 32 +XTENSA_INS_AE_CVT32X2F16_32 = 33 +XTENSA_INS_AE_CVT48A32 = 34 +XTENSA_INS_AE_CVT64A32 = 35 +XTENSA_INS_AE_CVT64F32_H = 36 +XTENSA_INS_AE_CVTA32F24S_H = 37 +XTENSA_INS_AE_CVTA32F24S_L = 38 +XTENSA_INS_AE_CVTQ56A32S = 39 +XTENSA_INS_AE_CVTQ56P32S_H = 40 +XTENSA_INS_AE_CVTQ56P32S_L = 41 +XTENSA_INS_AE_DB = 42 +XTENSA_INS_AE_DBI = 43 +XTENSA_INS_AE_DBI_IC = 44 +XTENSA_INS_AE_DBI_IP = 45 +XTENSA_INS_AE_DB_IC = 46 +XTENSA_INS_AE_DB_IP = 47 +XTENSA_INS_AE_DIV64D32_H = 48 +XTENSA_INS_AE_DIV64D32_L = 49 +XTENSA_INS_AE_EQ16 = 50 +XTENSA_INS_AE_EQ32 = 51 +XTENSA_INS_AE_EQ64 = 52 +XTENSA_INS_AE_L16M_I = 53 +XTENSA_INS_AE_L16M_IU = 54 +XTENSA_INS_AE_L16M_X = 55 +XTENSA_INS_AE_L16M_XC = 56 +XTENSA_INS_AE_L16M_XU = 57 +XTENSA_INS_AE_L16X2M_I = 58 +XTENSA_INS_AE_L16X2M_IU = 59 +XTENSA_INS_AE_L16X2M_X = 60 +XTENSA_INS_AE_L16X2M_XC = 61 +XTENSA_INS_AE_L16X2M_XU = 62 +XTENSA_INS_AE_L16X4_I = 63 +XTENSA_INS_AE_L16X4_IP = 64 +XTENSA_INS_AE_L16X4_RIC = 65 +XTENSA_INS_AE_L16X4_RIP = 66 +XTENSA_INS_AE_L16X4_X = 67 +XTENSA_INS_AE_L16X4_XC = 68 +XTENSA_INS_AE_L16X4_XP = 69 +XTENSA_INS_AE_L16_I = 70 +XTENSA_INS_AE_L16_IP = 71 +XTENSA_INS_AE_L16_X = 72 +XTENSA_INS_AE_L16_XC = 73 +XTENSA_INS_AE_L16_XP = 74 +XTENSA_INS_AE_L32F24_I = 75 +XTENSA_INS_AE_L32F24_IP = 76 +XTENSA_INS_AE_L32F24_X = 77 +XTENSA_INS_AE_L32F24_XC = 78 +XTENSA_INS_AE_L32F24_XP = 79 +XTENSA_INS_AE_L32M_I = 80 +XTENSA_INS_AE_L32M_IU = 81 +XTENSA_INS_AE_L32M_X = 82 +XTENSA_INS_AE_L32M_XC = 83 +XTENSA_INS_AE_L32M_XU = 84 +XTENSA_INS_AE_L32X2F24_I = 85 +XTENSA_INS_AE_L32X2F24_IP = 86 +XTENSA_INS_AE_L32X2F24_RIC = 87 +XTENSA_INS_AE_L32X2F24_RIP = 88 +XTENSA_INS_AE_L32X2F24_X = 89 +XTENSA_INS_AE_L32X2F24_XC = 90 +XTENSA_INS_AE_L32X2F24_XP = 91 +XTENSA_INS_AE_L32X2_I = 92 +XTENSA_INS_AE_L32X2_IP = 93 +XTENSA_INS_AE_L32X2_RIC = 94 +XTENSA_INS_AE_L32X2_RIP = 95 +XTENSA_INS_AE_L32X2_X = 96 +XTENSA_INS_AE_L32X2_XC = 97 +XTENSA_INS_AE_L32X2_XP = 98 +XTENSA_INS_AE_L32_I = 99 +XTENSA_INS_AE_L32_IP = 100 +XTENSA_INS_AE_L32_X = 101 +XTENSA_INS_AE_L32_XC = 102 +XTENSA_INS_AE_L32_XP = 103 +XTENSA_INS_AE_L64_I = 104 +XTENSA_INS_AE_L64_IP = 105 +XTENSA_INS_AE_L64_X = 106 +XTENSA_INS_AE_L64_XC = 107 +XTENSA_INS_AE_L64_XP = 108 +XTENSA_INS_AE_LA16X4NEG_PC = 109 +XTENSA_INS_AE_LA16X4POS_PC = 110 +XTENSA_INS_AE_LA16X4_IC = 111 +XTENSA_INS_AE_LA16X4_IP = 112 +XTENSA_INS_AE_LA16X4_RIC = 113 +XTENSA_INS_AE_LA16X4_RIP = 114 +XTENSA_INS_AE_LA24NEG_PC = 115 +XTENSA_INS_AE_LA24POS_PC = 116 +XTENSA_INS_AE_LA24X2NEG_PC = 117 +XTENSA_INS_AE_LA24X2POS_PC = 118 +XTENSA_INS_AE_LA24X2_IC = 119 +XTENSA_INS_AE_LA24X2_IP = 120 +XTENSA_INS_AE_LA24X2_RIC = 121 +XTENSA_INS_AE_LA24X2_RIP = 122 +XTENSA_INS_AE_LA24_IC = 123 +XTENSA_INS_AE_LA24_IP = 124 +XTENSA_INS_AE_LA24_RIC = 125 +XTENSA_INS_AE_LA24_RIP = 126 +XTENSA_INS_AE_LA32X2F24_IC = 127 +XTENSA_INS_AE_LA32X2F24_IP = 128 +XTENSA_INS_AE_LA32X2F24_RIC = 129 +XTENSA_INS_AE_LA32X2F24_RIP = 130 +XTENSA_INS_AE_LA32X2NEG_PC = 131 +XTENSA_INS_AE_LA32X2POS_PC = 132 +XTENSA_INS_AE_LA32X2_IC = 133 +XTENSA_INS_AE_LA32X2_IP = 134 +XTENSA_INS_AE_LA32X2_RIC = 135 +XTENSA_INS_AE_LA32X2_RIP = 136 +XTENSA_INS_AE_LA64_PP = 137 +XTENSA_INS_AE_LALIGN64_I = 138 +XTENSA_INS_AE_LB = 139 +XTENSA_INS_AE_LBI = 140 +XTENSA_INS_AE_LBK = 141 +XTENSA_INS_AE_LBKI = 142 +XTENSA_INS_AE_LBS = 143 +XTENSA_INS_AE_LBSI = 144 +XTENSA_INS_AE_LE16 = 145 +XTENSA_INS_AE_LE32 = 146 +XTENSA_INS_AE_LE64 = 147 +XTENSA_INS_AE_LT16 = 148 +XTENSA_INS_AE_LT32 = 149 +XTENSA_INS_AE_LT64 = 150 +XTENSA_INS_AE_MAX32 = 151 +XTENSA_INS_AE_MAX64 = 152 +XTENSA_INS_AE_MAXABS32S = 153 +XTENSA_INS_AE_MAXABS64S = 154 +XTENSA_INS_AE_MIN32 = 155 +XTENSA_INS_AE_MIN64 = 156 +XTENSA_INS_AE_MINABS32S = 157 +XTENSA_INS_AE_MINABS64S = 158 +XTENSA_INS_AE_MOV = 159 +XTENSA_INS_AE_MOVAD16_0 = 160 +XTENSA_INS_AE_MOVAD16_1 = 161 +XTENSA_INS_AE_MOVAD16_2 = 162 +XTENSA_INS_AE_MOVAD16_3 = 163 +XTENSA_INS_AE_MOVAD32_H = 164 +XTENSA_INS_AE_MOVAD32_L = 165 +XTENSA_INS_AE_MOVALIGN = 166 +XTENSA_INS_AE_MOVDA16 = 167 +XTENSA_INS_AE_MOVDA16X2 = 168 +XTENSA_INS_AE_MOVDA32 = 169 +XTENSA_INS_AE_MOVDA32X2 = 170 +XTENSA_INS_AE_MOVF16X4 = 171 +XTENSA_INS_AE_MOVF32X2 = 172 +XTENSA_INS_AE_MOVF64 = 173 +XTENSA_INS_AE_MOVI = 174 +XTENSA_INS_AE_MOVT16X4 = 175 +XTENSA_INS_AE_MOVT32X2 = 176 +XTENSA_INS_AE_MOVT64 = 177 +XTENSA_INS_AE_MUL16X4 = 178 +XTENSA_INS_AE_MUL32U_LL = 179 +XTENSA_INS_AE_MUL32X16_H0 = 180 +XTENSA_INS_AE_MUL32X16_H0_S2 = 181 +XTENSA_INS_AE_MUL32X16_H1 = 182 +XTENSA_INS_AE_MUL32X16_H1_S2 = 183 +XTENSA_INS_AE_MUL32X16_H2 = 184 +XTENSA_INS_AE_MUL32X16_H2_S2 = 185 +XTENSA_INS_AE_MUL32X16_H3 = 186 +XTENSA_INS_AE_MUL32X16_H3_S2 = 187 +XTENSA_INS_AE_MUL32X16_L0 = 188 +XTENSA_INS_AE_MUL32X16_L0_S2 = 189 +XTENSA_INS_AE_MUL32X16_L1 = 190 +XTENSA_INS_AE_MUL32X16_L1_S2 = 191 +XTENSA_INS_AE_MUL32X16_L2 = 192 +XTENSA_INS_AE_MUL32X16_L2_S2 = 193 +XTENSA_INS_AE_MUL32X16_L3 = 194 +XTENSA_INS_AE_MUL32X16_L3_S2 = 195 +XTENSA_INS_AE_MUL32_HH = 196 +XTENSA_INS_AE_MUL32_LH = 197 +XTENSA_INS_AE_MUL32_LL = 198 +XTENSA_INS_AE_MUL32_LL_S2 = 199 +XTENSA_INS_AE_MULA16X4 = 200 +XTENSA_INS_AE_MULA32U_LL = 201 +XTENSA_INS_AE_MULA32X16_H0 = 202 +XTENSA_INS_AE_MULA32X16_H0_S2 = 203 +XTENSA_INS_AE_MULA32X16_H1 = 204 +XTENSA_INS_AE_MULA32X16_H1_S2 = 205 +XTENSA_INS_AE_MULA32X16_H2 = 206 +XTENSA_INS_AE_MULA32X16_H2_S2 = 207 +XTENSA_INS_AE_MULA32X16_H3 = 208 +XTENSA_INS_AE_MULA32X16_H3_S2 = 209 +XTENSA_INS_AE_MULA32X16_L0 = 210 +XTENSA_INS_AE_MULA32X16_L0_S2 = 211 +XTENSA_INS_AE_MULA32X16_L1 = 212 +XTENSA_INS_AE_MULA32X16_L1_S2 = 213 +XTENSA_INS_AE_MULA32X16_L2 = 214 +XTENSA_INS_AE_MULA32X16_L2_S2 = 215 +XTENSA_INS_AE_MULA32X16_L3 = 216 +XTENSA_INS_AE_MULA32X16_L3_S2 = 217 +XTENSA_INS_AE_MULA32_HH = 218 +XTENSA_INS_AE_MULA32_LH = 219 +XTENSA_INS_AE_MULA32_LL = 220 +XTENSA_INS_AE_MULA32_LL_S2 = 221 +XTENSA_INS_AE_MULAAD24_HH_LL = 222 +XTENSA_INS_AE_MULAAD24_HH_LL_S2 = 223 +XTENSA_INS_AE_MULAAD24_HL_LH = 224 +XTENSA_INS_AE_MULAAD24_HL_LH_S2 = 225 +XTENSA_INS_AE_MULAAD32X16_H0_L1 = 226 +XTENSA_INS_AE_MULAAD32X16_H0_L1_S2 = 227 +XTENSA_INS_AE_MULAAD32X16_H1_L0 = 228 +XTENSA_INS_AE_MULAAD32X16_H1_L0_S2 = 229 +XTENSA_INS_AE_MULAAD32X16_H2_L3 = 230 +XTENSA_INS_AE_MULAAD32X16_H2_L3_S2 = 231 +XTENSA_INS_AE_MULAAD32X16_H3_L2 = 232 +XTENSA_INS_AE_MULAAD32X16_H3_L2_S2 = 233 +XTENSA_INS_AE_MULAAFD16SS_11_00 = 234 +XTENSA_INS_AE_MULAAFD16SS_11_00_S2 = 235 +XTENSA_INS_AE_MULAAFD16SS_13_02 = 236 +XTENSA_INS_AE_MULAAFD16SS_13_02_S2 = 237 +XTENSA_INS_AE_MULAAFD16SS_33_22 = 238 +XTENSA_INS_AE_MULAAFD16SS_33_22_S2 = 239 +XTENSA_INS_AE_MULAAFD24_HH_LL = 240 +XTENSA_INS_AE_MULAAFD24_HH_LL_S2 = 241 +XTENSA_INS_AE_MULAAFD24_HL_LH = 242 +XTENSA_INS_AE_MULAAFD24_HL_LH_S2 = 243 +XTENSA_INS_AE_MULAAFD32X16_H0_L1 = 244 +XTENSA_INS_AE_MULAAFD32X16_H0_L1_S2 = 245 +XTENSA_INS_AE_MULAAFD32X16_H1_L0 = 246 +XTENSA_INS_AE_MULAAFD32X16_H1_L0_S2 = 247 +XTENSA_INS_AE_MULAAFD32X16_H2_L3 = 248 +XTENSA_INS_AE_MULAAFD32X16_H2_L3_S2 = 249 +XTENSA_INS_AE_MULAAFD32X16_H3_L2 = 250 +XTENSA_INS_AE_MULAAFD32X16_H3_L2_S2 = 251 +XTENSA_INS_AE_MULAC24 = 252 +XTENSA_INS_AE_MULAC32X16_H = 253 +XTENSA_INS_AE_MULAC32X16_L = 254 +XTENSA_INS_AE_MULAF16SS_00 = 255 +XTENSA_INS_AE_MULAF16SS_00_S2 = 256 +XTENSA_INS_AE_MULAF16SS_10 = 257 +XTENSA_INS_AE_MULAF16SS_11 = 258 +XTENSA_INS_AE_MULAF16SS_20 = 259 +XTENSA_INS_AE_MULAF16SS_21 = 260 +XTENSA_INS_AE_MULAF16SS_22 = 261 +XTENSA_INS_AE_MULAF16SS_30 = 262 +XTENSA_INS_AE_MULAF16SS_31 = 263 +XTENSA_INS_AE_MULAF16SS_32 = 264 +XTENSA_INS_AE_MULAF16SS_33 = 265 +XTENSA_INS_AE_MULAF16X4SS = 266 +XTENSA_INS_AE_MULAF32R_HH = 267 +XTENSA_INS_AE_MULAF32R_LH = 268 +XTENSA_INS_AE_MULAF32R_LL = 269 +XTENSA_INS_AE_MULAF32R_LL_S2 = 270 +XTENSA_INS_AE_MULAF32S_HH = 271 +XTENSA_INS_AE_MULAF32S_LH = 272 +XTENSA_INS_AE_MULAF32S_LL = 273 +XTENSA_INS_AE_MULAF32S_LL_S2 = 274 +XTENSA_INS_AE_MULAF32X16_H0 = 275 +XTENSA_INS_AE_MULAF32X16_H0_S2 = 276 +XTENSA_INS_AE_MULAF32X16_H1 = 277 +XTENSA_INS_AE_MULAF32X16_H1_S2 = 278 +XTENSA_INS_AE_MULAF32X16_H2 = 279 +XTENSA_INS_AE_MULAF32X16_H2_S2 = 280 +XTENSA_INS_AE_MULAF32X16_H3 = 281 +XTENSA_INS_AE_MULAF32X16_H3_S2 = 282 +XTENSA_INS_AE_MULAF32X16_L0 = 283 +XTENSA_INS_AE_MULAF32X16_L0_S2 = 284 +XTENSA_INS_AE_MULAF32X16_L1 = 285 +XTENSA_INS_AE_MULAF32X16_L1_S2 = 286 +XTENSA_INS_AE_MULAF32X16_L2 = 287 +XTENSA_INS_AE_MULAF32X16_L2_S2 = 288 +XTENSA_INS_AE_MULAF32X16_L3 = 289 +XTENSA_INS_AE_MULAF32X16_L3_S2 = 290 +XTENSA_INS_AE_MULAF48Q32SP16S_L = 291 +XTENSA_INS_AE_MULAF48Q32SP16S_L_S2 = 292 +XTENSA_INS_AE_MULAF48Q32SP16U_L = 293 +XTENSA_INS_AE_MULAF48Q32SP16U_L_S2 = 294 +XTENSA_INS_AE_MULAFC24RA = 295 +XTENSA_INS_AE_MULAFC32X16RAS_H = 296 +XTENSA_INS_AE_MULAFC32X16RAS_L = 297 +XTENSA_INS_AE_MULAFD24X2_FIR_H = 298 +XTENSA_INS_AE_MULAFD24X2_FIR_L = 299 +XTENSA_INS_AE_MULAFD32X16X2_FIR_HH = 300 +XTENSA_INS_AE_MULAFD32X16X2_FIR_HL = 301 +XTENSA_INS_AE_MULAFD32X16X2_FIR_LH = 302 +XTENSA_INS_AE_MULAFD32X16X2_FIR_LL = 303 +XTENSA_INS_AE_MULAFP24X2R = 304 +XTENSA_INS_AE_MULAFP24X2RA = 305 +XTENSA_INS_AE_MULAFP24X2RA_S2 = 306 +XTENSA_INS_AE_MULAFP24X2R_S2 = 307 +XTENSA_INS_AE_MULAFP32X16X2RAS_H = 308 +XTENSA_INS_AE_MULAFP32X16X2RAS_H_S2 = 309 +XTENSA_INS_AE_MULAFP32X16X2RAS_L = 310 +XTENSA_INS_AE_MULAFP32X16X2RAS_L_S2 = 311 +XTENSA_INS_AE_MULAFP32X16X2RS_H = 312 +XTENSA_INS_AE_MULAFP32X16X2RS_H_S2 = 313 +XTENSA_INS_AE_MULAFP32X16X2RS_L = 314 +XTENSA_INS_AE_MULAFP32X16X2RS_L_S2 = 315 +XTENSA_INS_AE_MULAFP32X2RAS = 316 +XTENSA_INS_AE_MULAFP32X2RS = 317 +XTENSA_INS_AE_MULAFQ32SP24S_H_S2 = 318 +XTENSA_INS_AE_MULAFQ32SP24S_L_S2 = 319 +XTENSA_INS_AE_MULAP24X2 = 320 +XTENSA_INS_AE_MULAP24X2_S2 = 321 +XTENSA_INS_AE_MULAP32X16X2_H = 322 +XTENSA_INS_AE_MULAP32X16X2_L = 323 +XTENSA_INS_AE_MULAP32X2 = 324 +XTENSA_INS_AE_MULAQ32SP16S_L_S2 = 325 +XTENSA_INS_AE_MULAQ32SP16U_L_S2 = 326 +XTENSA_INS_AE_MULARFQ32SP24S_H_S2 = 327 +XTENSA_INS_AE_MULARFQ32SP24S_L_S2 = 328 +XTENSA_INS_AE_MULAS32F48P16S_HH = 329 +XTENSA_INS_AE_MULAS32F48P16S_HH_S2 = 330 +XTENSA_INS_AE_MULAS32F48P16S_LH = 331 +XTENSA_INS_AE_MULAS32F48P16S_LH_S2 = 332 +XTENSA_INS_AE_MULAS32F48P16S_LL = 333 +XTENSA_INS_AE_MULAS32F48P16S_LL_S2 = 334 +XTENSA_INS_AE_MULASD24_HH_LL = 335 +XTENSA_INS_AE_MULASD24_HH_LL_S2 = 336 +XTENSA_INS_AE_MULASD24_HL_LH = 337 +XTENSA_INS_AE_MULASD24_HL_LH_S2 = 338 +XTENSA_INS_AE_MULASD32X16_H1_L0 = 339 +XTENSA_INS_AE_MULASD32X16_H1_L0_S2 = 340 +XTENSA_INS_AE_MULASD32X16_H3_L2 = 341 +XTENSA_INS_AE_MULASD32X16_H3_L2_S2 = 342 +XTENSA_INS_AE_MULASFD24_HH_LL = 343 +XTENSA_INS_AE_MULASFD24_HH_LL_S2 = 344 +XTENSA_INS_AE_MULASFD24_HL_LH = 345 +XTENSA_INS_AE_MULASFD24_HL_LH_S2 = 346 +XTENSA_INS_AE_MULASFD32X16_H1_L0 = 347 +XTENSA_INS_AE_MULASFD32X16_H1_L0_S2 = 348 +XTENSA_INS_AE_MULASFD32X16_H3_L2 = 349 +XTENSA_INS_AE_MULASFD32X16_H3_L2_S2 = 350 +XTENSA_INS_AE_MULC24 = 351 +XTENSA_INS_AE_MULC32X16_H = 352 +XTENSA_INS_AE_MULC32X16_L = 353 +XTENSA_INS_AE_MULF16SS_00 = 354 +XTENSA_INS_AE_MULF16SS_00_S2 = 355 +XTENSA_INS_AE_MULF16SS_10 = 356 +XTENSA_INS_AE_MULF16SS_11 = 357 +XTENSA_INS_AE_MULF16SS_20 = 358 +XTENSA_INS_AE_MULF16SS_21 = 359 +XTENSA_INS_AE_MULF16SS_22 = 360 +XTENSA_INS_AE_MULF16SS_30 = 361 +XTENSA_INS_AE_MULF16SS_31 = 362 +XTENSA_INS_AE_MULF16SS_32 = 363 +XTENSA_INS_AE_MULF16SS_33 = 364 +XTENSA_INS_AE_MULF16X4SS = 365 +XTENSA_INS_AE_MULF32R_HH = 366 +XTENSA_INS_AE_MULF32R_LH = 367 +XTENSA_INS_AE_MULF32R_LL = 368 +XTENSA_INS_AE_MULF32R_LL_S2 = 369 +XTENSA_INS_AE_MULF32S_HH = 370 +XTENSA_INS_AE_MULF32S_LH = 371 +XTENSA_INS_AE_MULF32S_LL = 372 +XTENSA_INS_AE_MULF32S_LL_S2 = 373 +XTENSA_INS_AE_MULF32X16_H0 = 374 +XTENSA_INS_AE_MULF32X16_H0_S2 = 375 +XTENSA_INS_AE_MULF32X16_H1 = 376 +XTENSA_INS_AE_MULF32X16_H1_S2 = 377 +XTENSA_INS_AE_MULF32X16_H2 = 378 +XTENSA_INS_AE_MULF32X16_H2_S2 = 379 +XTENSA_INS_AE_MULF32X16_H3 = 380 +XTENSA_INS_AE_MULF32X16_H3_S2 = 381 +XTENSA_INS_AE_MULF32X16_L0 = 382 +XTENSA_INS_AE_MULF32X16_L0_S2 = 383 +XTENSA_INS_AE_MULF32X16_L1 = 384 +XTENSA_INS_AE_MULF32X16_L1_S2 = 385 +XTENSA_INS_AE_MULF32X16_L2 = 386 +XTENSA_INS_AE_MULF32X16_L2_S2 = 387 +XTENSA_INS_AE_MULF32X16_L3 = 388 +XTENSA_INS_AE_MULF32X16_L3_S2 = 389 +XTENSA_INS_AE_MULF48Q32SP16S_L = 390 +XTENSA_INS_AE_MULF48Q32SP16S_L_S2 = 391 +XTENSA_INS_AE_MULF48Q32SP16U_L = 392 +XTENSA_INS_AE_MULF48Q32SP16U_L_S2 = 393 +XTENSA_INS_AE_MULFC24RA = 394 +XTENSA_INS_AE_MULFC32X16RAS_H = 395 +XTENSA_INS_AE_MULFC32X16RAS_L = 396 +XTENSA_INS_AE_MULFD24X2_FIR_H = 397 +XTENSA_INS_AE_MULFD24X2_FIR_L = 398 +XTENSA_INS_AE_MULFD32X16X2_FIR_HH = 399 +XTENSA_INS_AE_MULFD32X16X2_FIR_HL = 400 +XTENSA_INS_AE_MULFD32X16X2_FIR_LH = 401 +XTENSA_INS_AE_MULFD32X16X2_FIR_LL = 402 +XTENSA_INS_AE_MULFP16X4RAS = 403 +XTENSA_INS_AE_MULFP16X4S = 404 +XTENSA_INS_AE_MULFP24X2R = 405 +XTENSA_INS_AE_MULFP24X2RA = 406 +XTENSA_INS_AE_MULFP24X2RA_S2 = 407 +XTENSA_INS_AE_MULFP24X2R_S2 = 408 +XTENSA_INS_AE_MULFP32X16X2RAS_H = 409 +XTENSA_INS_AE_MULFP32X16X2RAS_H_S2 = 410 +XTENSA_INS_AE_MULFP32X16X2RAS_L = 411 +XTENSA_INS_AE_MULFP32X16X2RAS_L_S2 = 412 +XTENSA_INS_AE_MULFP32X16X2RS_H = 413 +XTENSA_INS_AE_MULFP32X16X2RS_H_S2 = 414 +XTENSA_INS_AE_MULFP32X16X2RS_L = 415 +XTENSA_INS_AE_MULFP32X16X2RS_L_S2 = 416 +XTENSA_INS_AE_MULFP32X2RAS = 417 +XTENSA_INS_AE_MULFP32X2RS = 418 +XTENSA_INS_AE_MULFQ32SP24S_H_S2 = 419 +XTENSA_INS_AE_MULFQ32SP24S_L_S2 = 420 +XTENSA_INS_AE_MULP24X2 = 421 +XTENSA_INS_AE_MULP24X2_S2 = 422 +XTENSA_INS_AE_MULP32X16X2_H = 423 +XTENSA_INS_AE_MULP32X16X2_L = 424 +XTENSA_INS_AE_MULP32X2 = 425 +XTENSA_INS_AE_MULQ32SP16S_L_S2 = 426 +XTENSA_INS_AE_MULQ32SP16U_L_S2 = 427 +XTENSA_INS_AE_MULRFQ32SP24S_H_S2 = 428 +XTENSA_INS_AE_MULRFQ32SP24S_L_S2 = 429 +XTENSA_INS_AE_MULS16X4 = 430 +XTENSA_INS_AE_MULS32F48P16S_HH = 431 +XTENSA_INS_AE_MULS32F48P16S_HH_S2 = 432 +XTENSA_INS_AE_MULS32F48P16S_LH = 433 +XTENSA_INS_AE_MULS32F48P16S_LH_S2 = 434 +XTENSA_INS_AE_MULS32F48P16S_LL = 435 +XTENSA_INS_AE_MULS32F48P16S_LL_S2 = 436 +XTENSA_INS_AE_MULS32U_LL = 437 +XTENSA_INS_AE_MULS32X16_H0 = 438 +XTENSA_INS_AE_MULS32X16_H0_S2 = 439 +XTENSA_INS_AE_MULS32X16_H1 = 440 +XTENSA_INS_AE_MULS32X16_H1_S2 = 441 +XTENSA_INS_AE_MULS32X16_H2 = 442 +XTENSA_INS_AE_MULS32X16_H2_S2 = 443 +XTENSA_INS_AE_MULS32X16_H3 = 444 +XTENSA_INS_AE_MULS32X16_H3_S2 = 445 +XTENSA_INS_AE_MULS32X16_L0 = 446 +XTENSA_INS_AE_MULS32X16_L0_S2 = 447 +XTENSA_INS_AE_MULS32X16_L1 = 448 +XTENSA_INS_AE_MULS32X16_L1_S2 = 449 +XTENSA_INS_AE_MULS32X16_L2 = 450 +XTENSA_INS_AE_MULS32X16_L2_S2 = 451 +XTENSA_INS_AE_MULS32X16_L3 = 452 +XTENSA_INS_AE_MULS32X16_L3_S2 = 453 +XTENSA_INS_AE_MULS32_HH = 454 +XTENSA_INS_AE_MULS32_LH = 455 +XTENSA_INS_AE_MULS32_LL = 456 +XTENSA_INS_AE_MULSAD24_HH_LL = 457 +XTENSA_INS_AE_MULSAD24_HH_LL_S2 = 458 +XTENSA_INS_AE_MULSAD32X16_H1_L0 = 459 +XTENSA_INS_AE_MULSAD32X16_H1_L0_S2 = 460 +XTENSA_INS_AE_MULSAD32X16_H3_L2 = 461 +XTENSA_INS_AE_MULSAD32X16_H3_L2_S2 = 462 +XTENSA_INS_AE_MULSAFD24_HH_LL = 463 +XTENSA_INS_AE_MULSAFD24_HH_LL_S2 = 464 +XTENSA_INS_AE_MULSAFD32X16_H1_L0 = 465 +XTENSA_INS_AE_MULSAFD32X16_H1_L0_S2 = 466 +XTENSA_INS_AE_MULSAFD32X16_H3_L2 = 467 +XTENSA_INS_AE_MULSAFD32X16_H3_L2_S2 = 468 +XTENSA_INS_AE_MULSF16SS_00 = 469 +XTENSA_INS_AE_MULSF16SS_00_S2 = 470 +XTENSA_INS_AE_MULSF16SS_10 = 471 +XTENSA_INS_AE_MULSF16SS_11 = 472 +XTENSA_INS_AE_MULSF16SS_20 = 473 +XTENSA_INS_AE_MULSF16SS_21 = 474 +XTENSA_INS_AE_MULSF16SS_22 = 475 +XTENSA_INS_AE_MULSF16SS_30 = 476 +XTENSA_INS_AE_MULSF16SS_31 = 477 +XTENSA_INS_AE_MULSF16SS_32 = 478 +XTENSA_INS_AE_MULSF16SS_33 = 479 +XTENSA_INS_AE_MULSF16X4SS = 480 +XTENSA_INS_AE_MULSF32R_HH = 481 +XTENSA_INS_AE_MULSF32R_LH = 482 +XTENSA_INS_AE_MULSF32R_LL = 483 +XTENSA_INS_AE_MULSF32R_LL_S2 = 484 +XTENSA_INS_AE_MULSF32S_HH = 485 +XTENSA_INS_AE_MULSF32S_LH = 486 +XTENSA_INS_AE_MULSF32S_LL = 487 +XTENSA_INS_AE_MULSF32X16_H0 = 488 +XTENSA_INS_AE_MULSF32X16_H0_S2 = 489 +XTENSA_INS_AE_MULSF32X16_H1 = 490 +XTENSA_INS_AE_MULSF32X16_H1_S2 = 491 +XTENSA_INS_AE_MULSF32X16_H2 = 492 +XTENSA_INS_AE_MULSF32X16_H2_S2 = 493 +XTENSA_INS_AE_MULSF32X16_H3 = 494 +XTENSA_INS_AE_MULSF32X16_H3_S2 = 495 +XTENSA_INS_AE_MULSF32X16_L0 = 496 +XTENSA_INS_AE_MULSF32X16_L0_S2 = 497 +XTENSA_INS_AE_MULSF32X16_L1 = 498 +XTENSA_INS_AE_MULSF32X16_L1_S2 = 499 +XTENSA_INS_AE_MULSF32X16_L2 = 500 +XTENSA_INS_AE_MULSF32X16_L2_S2 = 501 +XTENSA_INS_AE_MULSF32X16_L3 = 502 +XTENSA_INS_AE_MULSF32X16_L3_S2 = 503 +XTENSA_INS_AE_MULSF48Q32SP16S_L = 504 +XTENSA_INS_AE_MULSF48Q32SP16S_L_S2 = 505 +XTENSA_INS_AE_MULSF48Q32SP16U_L = 506 +XTENSA_INS_AE_MULSF48Q32SP16U_L_S2 = 507 +XTENSA_INS_AE_MULSFP24X2R = 508 +XTENSA_INS_AE_MULSFP24X2RA = 509 +XTENSA_INS_AE_MULSFP24X2RA_S2 = 510 +XTENSA_INS_AE_MULSFP24X2R_S2 = 511 +XTENSA_INS_AE_MULSFP32X16X2RAS_H = 512 +XTENSA_INS_AE_MULSFP32X16X2RAS_H_S2 = 513 +XTENSA_INS_AE_MULSFP32X16X2RAS_L = 514 +XTENSA_INS_AE_MULSFP32X16X2RAS_L_S2 = 515 +XTENSA_INS_AE_MULSFP32X16X2RS_H = 516 +XTENSA_INS_AE_MULSFP32X16X2RS_H_S2 = 517 +XTENSA_INS_AE_MULSFP32X16X2RS_L = 518 +XTENSA_INS_AE_MULSFP32X16X2RS_L_S2 = 519 +XTENSA_INS_AE_MULSFP32X2RAS = 520 +XTENSA_INS_AE_MULSFP32X2RS = 521 +XTENSA_INS_AE_MULSFQ32SP24S_H_S2 = 522 +XTENSA_INS_AE_MULSFQ32SP24S_L_S2 = 523 +XTENSA_INS_AE_MULSP24X2 = 524 +XTENSA_INS_AE_MULSP24X2_S2 = 525 +XTENSA_INS_AE_MULSP32X16X2_H = 526 +XTENSA_INS_AE_MULSP32X16X2_L = 527 +XTENSA_INS_AE_MULSP32X2 = 528 +XTENSA_INS_AE_MULSQ32SP16S_L_S2 = 529 +XTENSA_INS_AE_MULSQ32SP16U_L_S2 = 530 +XTENSA_INS_AE_MULSRFQ32SP24S_H_S2 = 531 +XTENSA_INS_AE_MULSRFQ32SP24S_L_S2 = 532 +XTENSA_INS_AE_MULSS32F48P16S_HH = 533 +XTENSA_INS_AE_MULSS32F48P16S_HH_S2 = 534 +XTENSA_INS_AE_MULSS32F48P16S_LH = 535 +XTENSA_INS_AE_MULSS32F48P16S_LH_S2 = 536 +XTENSA_INS_AE_MULSS32F48P16S_LL = 537 +XTENSA_INS_AE_MULSS32F48P16S_LL_S2 = 538 +XTENSA_INS_AE_MULSSD24_HH_LL = 539 +XTENSA_INS_AE_MULSSD24_HH_LL_S2 = 540 +XTENSA_INS_AE_MULSSD24_HL_LH = 541 +XTENSA_INS_AE_MULSSD24_HL_LH_S2 = 542 +XTENSA_INS_AE_MULSSD32X16_H1_L0 = 543 +XTENSA_INS_AE_MULSSD32X16_H1_L0_S2 = 544 +XTENSA_INS_AE_MULSSD32X16_H3_L2 = 545 +XTENSA_INS_AE_MULSSD32X16_H3_L2_S2 = 546 +XTENSA_INS_AE_MULSSFD16SS_11_00 = 547 +XTENSA_INS_AE_MULSSFD16SS_11_00_S2 = 548 +XTENSA_INS_AE_MULSSFD16SS_13_02 = 549 +XTENSA_INS_AE_MULSSFD16SS_13_02_S2 = 550 +XTENSA_INS_AE_MULSSFD16SS_33_22 = 551 +XTENSA_INS_AE_MULSSFD16SS_33_22_S2 = 552 +XTENSA_INS_AE_MULSSFD24_HH_LL = 553 +XTENSA_INS_AE_MULSSFD24_HH_LL_S2 = 554 +XTENSA_INS_AE_MULSSFD24_HL_LH = 555 +XTENSA_INS_AE_MULSSFD24_HL_LH_S2 = 556 +XTENSA_INS_AE_MULSSFD32X16_H1_L0 = 557 +XTENSA_INS_AE_MULSSFD32X16_H1_L0_S2 = 558 +XTENSA_INS_AE_MULSSFD32X16_H3_L2 = 559 +XTENSA_INS_AE_MULSSFD32X16_H3_L2_S2 = 560 +XTENSA_INS_AE_MULZAAD24_HH_LL = 561 +XTENSA_INS_AE_MULZAAD24_HH_LL_S2 = 562 +XTENSA_INS_AE_MULZAAD24_HL_LH = 563 +XTENSA_INS_AE_MULZAAD24_HL_LH_S2 = 564 +XTENSA_INS_AE_MULZAAD32X16_H0_L1 = 565 +XTENSA_INS_AE_MULZAAD32X16_H0_L1_S2 = 566 +XTENSA_INS_AE_MULZAAD32X16_H1_L0 = 567 +XTENSA_INS_AE_MULZAAD32X16_H1_L0_S2 = 568 +XTENSA_INS_AE_MULZAAD32X16_H2_L3 = 569 +XTENSA_INS_AE_MULZAAD32X16_H2_L3_S2 = 570 +XTENSA_INS_AE_MULZAAD32X16_H3_L2 = 571 +XTENSA_INS_AE_MULZAAD32X16_H3_L2_S2 = 572 +XTENSA_INS_AE_MULZAAFD16SS_11_00 = 573 +XTENSA_INS_AE_MULZAAFD16SS_11_00_S2 = 574 +XTENSA_INS_AE_MULZAAFD16SS_13_02 = 575 +XTENSA_INS_AE_MULZAAFD16SS_13_02_S2 = 576 +XTENSA_INS_AE_MULZAAFD16SS_33_22 = 577 +XTENSA_INS_AE_MULZAAFD16SS_33_22_S2 = 578 +XTENSA_INS_AE_MULZAAFD24_HH_LL = 579 +XTENSA_INS_AE_MULZAAFD24_HH_LL_S2 = 580 +XTENSA_INS_AE_MULZAAFD24_HL_LH = 581 +XTENSA_INS_AE_MULZAAFD24_HL_LH_S2 = 582 +XTENSA_INS_AE_MULZAAFD32X16_H0_L1 = 583 +XTENSA_INS_AE_MULZAAFD32X16_H0_L1_S2 = 584 +XTENSA_INS_AE_MULZAAFD32X16_H1_L0 = 585 +XTENSA_INS_AE_MULZAAFD32X16_H1_L0_S2 = 586 +XTENSA_INS_AE_MULZAAFD32X16_H2_L3 = 587 +XTENSA_INS_AE_MULZAAFD32X16_H2_L3_S2 = 588 +XTENSA_INS_AE_MULZAAFD32X16_H3_L2 = 589 +XTENSA_INS_AE_MULZAAFD32X16_H3_L2_S2 = 590 +XTENSA_INS_AE_MULZASD24_HH_LL = 591 +XTENSA_INS_AE_MULZASD24_HH_LL_S2 = 592 +XTENSA_INS_AE_MULZASD24_HL_LH = 593 +XTENSA_INS_AE_MULZASD24_HL_LH_S2 = 594 +XTENSA_INS_AE_MULZASD32X16_H1_L0 = 595 +XTENSA_INS_AE_MULZASD32X16_H1_L0_S2 = 596 +XTENSA_INS_AE_MULZASD32X16_H3_L2 = 597 +XTENSA_INS_AE_MULZASD32X16_H3_L2_S2 = 598 +XTENSA_INS_AE_MULZASFD24_HH_LL = 599 +XTENSA_INS_AE_MULZASFD24_HH_LL_S2 = 600 +XTENSA_INS_AE_MULZASFD24_HL_LH = 601 +XTENSA_INS_AE_MULZASFD24_HL_LH_S2 = 602 +XTENSA_INS_AE_MULZASFD32X16_H1_L0 = 603 +XTENSA_INS_AE_MULZASFD32X16_H1_L0_S2 = 604 +XTENSA_INS_AE_MULZASFD32X16_H3_L2 = 605 +XTENSA_INS_AE_MULZASFD32X16_H3_L2_S2 = 606 +XTENSA_INS_AE_MULZSAD24_HH_LL = 607 +XTENSA_INS_AE_MULZSAD24_HH_LL_S2 = 608 +XTENSA_INS_AE_MULZSAD32X16_H1_L0 = 609 +XTENSA_INS_AE_MULZSAD32X16_H1_L0_S2 = 610 +XTENSA_INS_AE_MULZSAD32X16_H3_L2 = 611 +XTENSA_INS_AE_MULZSAD32X16_H3_L2_S2 = 612 +XTENSA_INS_AE_MULZSAFD24_HH_LL = 613 +XTENSA_INS_AE_MULZSAFD24_HH_LL_S2 = 614 +XTENSA_INS_AE_MULZSAFD32X16_H1_L0 = 615 +XTENSA_INS_AE_MULZSAFD32X16_H1_L0_S2 = 616 +XTENSA_INS_AE_MULZSAFD32X16_H3_L2 = 617 +XTENSA_INS_AE_MULZSAFD32X16_H3_L2_S2 = 618 +XTENSA_INS_AE_MULZSSD24_HH_LL = 619 +XTENSA_INS_AE_MULZSSD24_HH_LL_S2 = 620 +XTENSA_INS_AE_MULZSSD24_HL_LH = 621 +XTENSA_INS_AE_MULZSSD24_HL_LH_S2 = 622 +XTENSA_INS_AE_MULZSSD32X16_H1_L0 = 623 +XTENSA_INS_AE_MULZSSD32X16_H1_L0_S2 = 624 +XTENSA_INS_AE_MULZSSD32X16_H3_L2 = 625 +XTENSA_INS_AE_MULZSSD32X16_H3_L2_S2 = 626 +XTENSA_INS_AE_MULZSSFD16SS_11_00 = 627 +XTENSA_INS_AE_MULZSSFD16SS_11_00_S2 = 628 +XTENSA_INS_AE_MULZSSFD16SS_13_02 = 629 +XTENSA_INS_AE_MULZSSFD16SS_13_02_S2 = 630 +XTENSA_INS_AE_MULZSSFD16SS_33_22 = 631 +XTENSA_INS_AE_MULZSSFD16SS_33_22_S2 = 632 +XTENSA_INS_AE_MULZSSFD24_HH_LL = 633 +XTENSA_INS_AE_MULZSSFD24_HH_LL_S2 = 634 +XTENSA_INS_AE_MULZSSFD24_HL_LH = 635 +XTENSA_INS_AE_MULZSSFD24_HL_LH_S2 = 636 +XTENSA_INS_AE_MULZSSFD32X16_H1_L0 = 637 +XTENSA_INS_AE_MULZSSFD32X16_H1_L0_S2 = 638 +XTENSA_INS_AE_MULZSSFD32X16_H3_L2 = 639 +XTENSA_INS_AE_MULZSSFD32X16_H3_L2_S2 = 640 +XTENSA_INS_AE_NAND = 641 +XTENSA_INS_AE_NEG16S = 642 +XTENSA_INS_AE_NEG24S = 643 +XTENSA_INS_AE_NEG32 = 644 +XTENSA_INS_AE_NEG32S = 645 +XTENSA_INS_AE_NEG64 = 646 +XTENSA_INS_AE_NEG64S = 647 +XTENSA_INS_AE_NSA64 = 648 +XTENSA_INS_AE_NSAZ16_0 = 649 +XTENSA_INS_AE_NSAZ32_L = 650 +XTENSA_INS_AE_OR = 651 +XTENSA_INS_AE_PKSR24 = 652 +XTENSA_INS_AE_PKSR32 = 653 +XTENSA_INS_AE_ROUND16X4F32SASYM = 654 +XTENSA_INS_AE_ROUND16X4F32SSYM = 655 +XTENSA_INS_AE_ROUND24X2F48SASYM = 656 +XTENSA_INS_AE_ROUND24X2F48SSYM = 657 +XTENSA_INS_AE_ROUND32X2F48SASYM = 658 +XTENSA_INS_AE_ROUND32X2F48SSYM = 659 +XTENSA_INS_AE_ROUND32X2F64SASYM = 660 +XTENSA_INS_AE_ROUND32X2F64SSYM = 661 +XTENSA_INS_AE_ROUNDSP16F24ASYM = 662 +XTENSA_INS_AE_ROUNDSP16F24SYM = 663 +XTENSA_INS_AE_ROUNDSP16Q48X2ASYM = 664 +XTENSA_INS_AE_ROUNDSP16Q48X2SYM = 665 +XTENSA_INS_AE_ROUNDSQ32F48ASYM = 666 +XTENSA_INS_AE_ROUNDSQ32F48SYM = 667 +XTENSA_INS_AE_S16M_L_I = 668 +XTENSA_INS_AE_S16M_L_IU = 669 +XTENSA_INS_AE_S16M_L_X = 670 +XTENSA_INS_AE_S16M_L_XC = 671 +XTENSA_INS_AE_S16M_L_XU = 672 +XTENSA_INS_AE_S16X2M_I = 673 +XTENSA_INS_AE_S16X2M_IU = 674 +XTENSA_INS_AE_S16X2M_X = 675 +XTENSA_INS_AE_S16X2M_XC = 676 +XTENSA_INS_AE_S16X2M_XU = 677 +XTENSA_INS_AE_S16X4_I = 678 +XTENSA_INS_AE_S16X4_IP = 679 +XTENSA_INS_AE_S16X4_RIC = 680 +XTENSA_INS_AE_S16X4_RIP = 681 +XTENSA_INS_AE_S16X4_X = 682 +XTENSA_INS_AE_S16X4_XC = 683 +XTENSA_INS_AE_S16X4_XP = 684 +XTENSA_INS_AE_S16_0_I = 685 +XTENSA_INS_AE_S16_0_IP = 686 +XTENSA_INS_AE_S16_0_X = 687 +XTENSA_INS_AE_S16_0_XC = 688 +XTENSA_INS_AE_S16_0_XP = 689 +XTENSA_INS_AE_S24RA64S_I = 690 +XTENSA_INS_AE_S24RA64S_IP = 691 +XTENSA_INS_AE_S24RA64S_X = 692 +XTENSA_INS_AE_S24RA64S_XC = 693 +XTENSA_INS_AE_S24RA64S_XP = 694 +XTENSA_INS_AE_S24X2RA64S_IP = 695 +XTENSA_INS_AE_S32F24_L_I = 696 +XTENSA_INS_AE_S32F24_L_IP = 697 +XTENSA_INS_AE_S32F24_L_X = 698 +XTENSA_INS_AE_S32F24_L_XC = 699 +XTENSA_INS_AE_S32F24_L_XP = 700 +XTENSA_INS_AE_S32M_I = 701 +XTENSA_INS_AE_S32M_IU = 702 +XTENSA_INS_AE_S32M_X = 703 +XTENSA_INS_AE_S32M_XC = 704 +XTENSA_INS_AE_S32M_XU = 705 +XTENSA_INS_AE_S32RA64S_I = 706 +XTENSA_INS_AE_S32RA64S_IP = 707 +XTENSA_INS_AE_S32RA64S_X = 708 +XTENSA_INS_AE_S32RA64S_XC = 709 +XTENSA_INS_AE_S32RA64S_XP = 710 +XTENSA_INS_AE_S32X2F24_I = 711 +XTENSA_INS_AE_S32X2F24_IP = 712 +XTENSA_INS_AE_S32X2F24_RIC = 713 +XTENSA_INS_AE_S32X2F24_RIP = 714 +XTENSA_INS_AE_S32X2F24_X = 715 +XTENSA_INS_AE_S32X2F24_XC = 716 +XTENSA_INS_AE_S32X2F24_XP = 717 +XTENSA_INS_AE_S32X2RA64S_IP = 718 +XTENSA_INS_AE_S32X2_I = 719 +XTENSA_INS_AE_S32X2_IP = 720 +XTENSA_INS_AE_S32X2_RIC = 721 +XTENSA_INS_AE_S32X2_RIP = 722 +XTENSA_INS_AE_S32X2_X = 723 +XTENSA_INS_AE_S32X2_XC = 724 +XTENSA_INS_AE_S32X2_XP = 725 +XTENSA_INS_AE_S32_L_I = 726 +XTENSA_INS_AE_S32_L_IP = 727 +XTENSA_INS_AE_S32_L_X = 728 +XTENSA_INS_AE_S32_L_XC = 729 +XTENSA_INS_AE_S32_L_XP = 730 +XTENSA_INS_AE_S64_I = 731 +XTENSA_INS_AE_S64_IP = 732 +XTENSA_INS_AE_S64_X = 733 +XTENSA_INS_AE_S64_XC = 734 +XTENSA_INS_AE_S64_XP = 735 +XTENSA_INS_AE_SA16X4_IC = 736 +XTENSA_INS_AE_SA16X4_IP = 737 +XTENSA_INS_AE_SA16X4_RIC = 738 +XTENSA_INS_AE_SA16X4_RIP = 739 +XTENSA_INS_AE_SA24X2_IC = 740 +XTENSA_INS_AE_SA24X2_IP = 741 +XTENSA_INS_AE_SA24X2_RIC = 742 +XTENSA_INS_AE_SA24X2_RIP = 743 +XTENSA_INS_AE_SA24_L_IC = 744 +XTENSA_INS_AE_SA24_L_IP = 745 +XTENSA_INS_AE_SA24_L_RIC = 746 +XTENSA_INS_AE_SA24_L_RIP = 747 +XTENSA_INS_AE_SA32X2F24_IC = 748 +XTENSA_INS_AE_SA32X2F24_IP = 749 +XTENSA_INS_AE_SA32X2F24_RIC = 750 +XTENSA_INS_AE_SA32X2F24_RIP = 751 +XTENSA_INS_AE_SA32X2_IC = 752 +XTENSA_INS_AE_SA32X2_IP = 753 +XTENSA_INS_AE_SA32X2_RIC = 754 +XTENSA_INS_AE_SA32X2_RIP = 755 +XTENSA_INS_AE_SA64NEG_FP = 756 +XTENSA_INS_AE_SA64POS_FP = 757 +XTENSA_INS_AE_SALIGN64_I = 758 +XTENSA_INS_AE_SAT16X4 = 759 +XTENSA_INS_AE_SAT24S = 760 +XTENSA_INS_AE_SAT48S = 761 +XTENSA_INS_AE_SATQ56S = 762 +XTENSA_INS_AE_SB = 763 +XTENSA_INS_AE_SBF = 764 +XTENSA_INS_AE_SBF_IC = 765 +XTENSA_INS_AE_SBF_IP = 766 +XTENSA_INS_AE_SBI = 767 +XTENSA_INS_AE_SBI_IC = 768 +XTENSA_INS_AE_SBI_IP = 769 +XTENSA_INS_AE_SB_IC = 770 +XTENSA_INS_AE_SB_IP = 771 +XTENSA_INS_AE_SEL16I = 772 +XTENSA_INS_AE_SEL16I_N = 773 +XTENSA_INS_AE_SEXT32 = 774 +XTENSA_INS_AE_SEXT32X2D16_10 = 775 +XTENSA_INS_AE_SEXT32X2D16_32 = 776 +XTENSA_INS_AE_SHA32 = 777 +XTENSA_INS_AE_SHORTSWAP = 778 +XTENSA_INS_AE_SLAA16S = 779 +XTENSA_INS_AE_SLAA32 = 780 +XTENSA_INS_AE_SLAA32S = 781 +XTENSA_INS_AE_SLAA64 = 782 +XTENSA_INS_AE_SLAA64S = 783 +XTENSA_INS_AE_SLAAQ56 = 784 +XTENSA_INS_AE_SLAI16S = 785 +XTENSA_INS_AE_SLAI24 = 786 +XTENSA_INS_AE_SLAI24S = 787 +XTENSA_INS_AE_SLAI32 = 788 +XTENSA_INS_AE_SLAI32S = 789 +XTENSA_INS_AE_SLAI64 = 790 +XTENSA_INS_AE_SLAI64S = 791 +XTENSA_INS_AE_SLAISQ56S = 792 +XTENSA_INS_AE_SLAS24 = 793 +XTENSA_INS_AE_SLAS24S = 794 +XTENSA_INS_AE_SLAS32 = 795 +XTENSA_INS_AE_SLAS32S = 796 +XTENSA_INS_AE_SLAS64 = 797 +XTENSA_INS_AE_SLAS64S = 798 +XTENSA_INS_AE_SLASQ56 = 799 +XTENSA_INS_AE_SLASSQ56S = 800 +XTENSA_INS_AE_SRA64_32 = 801 +XTENSA_INS_AE_SRAA16RS = 802 +XTENSA_INS_AE_SRAA16S = 803 +XTENSA_INS_AE_SRAA32 = 804 +XTENSA_INS_AE_SRAA32RS = 805 +XTENSA_INS_AE_SRAA32S = 806 +XTENSA_INS_AE_SRAA64 = 807 +XTENSA_INS_AE_SRAI16 = 808 +XTENSA_INS_AE_SRAI16R = 809 +XTENSA_INS_AE_SRAI24 = 810 +XTENSA_INS_AE_SRAI32 = 811 +XTENSA_INS_AE_SRAI32R = 812 +XTENSA_INS_AE_SRAI64 = 813 +XTENSA_INS_AE_SRAS24 = 814 +XTENSA_INS_AE_SRAS32 = 815 +XTENSA_INS_AE_SRAS64 = 816 +XTENSA_INS_AE_SRLA32 = 817 +XTENSA_INS_AE_SRLA64 = 818 +XTENSA_INS_AE_SRLI24 = 819 +XTENSA_INS_AE_SRLI32 = 820 +XTENSA_INS_AE_SRLI64 = 821 +XTENSA_INS_AE_SRLS24 = 822 +XTENSA_INS_AE_SRLS32 = 823 +XTENSA_INS_AE_SRLS64 = 824 +XTENSA_INS_AE_SUB16 = 825 +XTENSA_INS_AE_SUB16S = 826 +XTENSA_INS_AE_SUB24S = 827 +XTENSA_INS_AE_SUB32 = 828 +XTENSA_INS_AE_SUB32S = 829 +XTENSA_INS_AE_SUB64 = 830 +XTENSA_INS_AE_SUB64S = 831 +XTENSA_INS_AE_SUBADD32 = 832 +XTENSA_INS_AE_SUBADD32S = 833 +XTENSA_INS_AE_TRUNCA32F64S_L = 834 +XTENSA_INS_AE_TRUNCA32X2F64S = 835 +XTENSA_INS_AE_TRUNCI32F64S_L = 836 +XTENSA_INS_AE_TRUNCI32X2F64S = 837 +XTENSA_INS_AE_VLDL16C = 838 +XTENSA_INS_AE_VLDL16C_IC = 839 +XTENSA_INS_AE_VLDL16C_IP = 840 +XTENSA_INS_AE_VLDL16T = 841 +XTENSA_INS_AE_VLDL32T = 842 +XTENSA_INS_AE_VLDSHT = 843 +XTENSA_INS_AE_VLEL16T = 844 +XTENSA_INS_AE_VLEL32T = 845 +XTENSA_INS_AE_VLES16C = 846 +XTENSA_INS_AE_VLES16C_IC = 847 +XTENSA_INS_AE_VLES16C_IP = 848 +XTENSA_INS_AE_XOR = 849 +XTENSA_INS_AE_ZALIGN64 = 850 +XTENSA_INS_ALL4 = 851 +XTENSA_INS_ALL8 = 852 +XTENSA_INS_AND = 853 +XTENSA_INS_ANDB = 854 +XTENSA_INS_ANDBC = 855 +XTENSA_INS_ANY4 = 856 +XTENSA_INS_ANY8 = 857 +XTENSA_INS_BALL = 858 +XTENSA_INS_BANY = 859 +XTENSA_INS_BBC = 860 +XTENSA_INS_BBCI = 861 +XTENSA_INS_BBS = 862 +XTENSA_INS_BBSI = 863 +XTENSA_INS_BEQ = 864 +XTENSA_INS_BEQI = 865 +XTENSA_INS_BEQZ = 866 +XTENSA_INS_BF = 867 +XTENSA_INS_BGE = 868 +XTENSA_INS_BGEI = 869 +XTENSA_INS_BGEU = 870 +XTENSA_INS_BGEUI = 871 +XTENSA_INS_BGEZ = 872 +XTENSA_INS_BLT = 873 +XTENSA_INS_BLTI = 874 +XTENSA_INS_BLTU = 875 +XTENSA_INS_BLTUI = 876 +XTENSA_INS_BLTZ = 877 +XTENSA_INS_BNALL = 878 +XTENSA_INS_BNE = 879 +XTENSA_INS_BNEI = 880 +XTENSA_INS_BNEZ = 881 +XTENSA_INS_BNONE = 882 +XTENSA_INS_BREAK = 883 +XTENSA_INS_BREAK_N = 884 +XTENSA_INS_BT = 885 +XTENSA_INS_CALL0 = 886 +XTENSA_INS_CALL12 = 887 +XTENSA_INS_CALL4 = 888 +XTENSA_INS_CALL8 = 889 +XTENSA_INS_CALLX0 = 890 +XTENSA_INS_CALLX12 = 891 +XTENSA_INS_CALLX4 = 892 +XTENSA_INS_CALLX8 = 893 +XTENSA_INS_CEIL_S = 894 +XTENSA_INS_CLAMPS = 895 +XTENSA_INS_CLR_BIT_GPIO_OUT = 896 +XTENSA_INS_CONST_S = 897 +XTENSA_INS_DIV0_S = 898 +XTENSA_INS_DIVN_S = 899 +XTENSA_INS_DSYNC = 900 +XTENSA_INS_EE_ANDQ = 901 +XTENSA_INS_EE_BITREV = 902 +XTENSA_INS_EE_CLR_BIT_GPIO_OUT = 903 +XTENSA_INS_EE_CMUL_S16 = 904 +XTENSA_INS_EE_CMUL_S16_LD_INCP = 905 +XTENSA_INS_EE_CMUL_S16_ST_INCP = 906 +XTENSA_INS_EE_FFT_AMS_S16_LD_INCP = 907 +XTENSA_INS_EE_FFT_AMS_S16_LD_INCP_UAUP = 908 +XTENSA_INS_EE_FFT_AMS_S16_LD_R32_DECP = 909 +XTENSA_INS_EE_FFT_AMS_S16_ST_INCP = 910 +XTENSA_INS_EE_FFT_CMUL_S16_LD_XP = 911 +XTENSA_INS_EE_FFT_CMUL_S16_ST_XP = 912 +XTENSA_INS_EE_FFT_R2BF_S16 = 913 +XTENSA_INS_EE_FFT_R2BF_S16_ST_INCP = 914 +XTENSA_INS_EE_FFT_VST_R32_DECP = 915 +XTENSA_INS_EE_GET_GPIO_IN = 916 +XTENSA_INS_EE_LDF_128_IP = 917 +XTENSA_INS_EE_LDF_128_XP = 918 +XTENSA_INS_EE_LDF_64_IP = 919 +XTENSA_INS_EE_LDF_64_XP = 920 +XTENSA_INS_EE_LDQA_S16_128_IP = 921 +XTENSA_INS_EE_LDQA_S16_128_XP = 922 +XTENSA_INS_EE_LDQA_S8_128_IP = 923 +XTENSA_INS_EE_LDQA_S8_128_XP = 924 +XTENSA_INS_EE_LDQA_U16_128_IP = 925 +XTENSA_INS_EE_LDQA_U16_128_XP = 926 +XTENSA_INS_EE_LDQA_U8_128_IP = 927 +XTENSA_INS_EE_LDQA_U8_128_XP = 928 +XTENSA_INS_EE_LDXQ_32 = 929 +XTENSA_INS_EE_LD_128_USAR_IP = 930 +XTENSA_INS_EE_LD_128_USAR_XP = 931 +XTENSA_INS_EE_LD_ACCX_IP = 932 +XTENSA_INS_EE_LD_QACC_H_H_32_IP = 933 +XTENSA_INS_EE_LD_QACC_H_L_128_IP = 934 +XTENSA_INS_EE_LD_QACC_L_H_32_IP = 935 +XTENSA_INS_EE_LD_QACC_L_L_128_IP = 936 +XTENSA_INS_EE_LD_UA_STATE_IP = 937 +XTENSA_INS_EE_MOVI_32_A = 938 +XTENSA_INS_EE_MOVI_32_Q = 939 +XTENSA_INS_EE_MOV_S16_QACC = 940 +XTENSA_INS_EE_MOV_S8_QACC = 941 +XTENSA_INS_EE_MOV_U16_QACC = 942 +XTENSA_INS_EE_MOV_U8_QACC = 943 +XTENSA_INS_EE_NOTQ = 944 +XTENSA_INS_EE_ORQ = 945 +XTENSA_INS_EE_SET_BIT_GPIO_OUT = 946 +XTENSA_INS_EE_SLCI_2Q = 947 +XTENSA_INS_EE_SLCXXP_2Q = 948 +XTENSA_INS_EE_SRCI_2Q = 949 +XTENSA_INS_EE_SRCMB_S16_QACC = 950 +XTENSA_INS_EE_SRCMB_S8_QACC = 951 +XTENSA_INS_EE_SRCQ_128_ST_INCP = 952 +XTENSA_INS_EE_SRCXXP_2Q = 953 +XTENSA_INS_EE_SRC_Q = 954 +XTENSA_INS_EE_SRC_Q_LD_IP = 955 +XTENSA_INS_EE_SRC_Q_LD_XP = 956 +XTENSA_INS_EE_SRC_Q_QUP = 957 +XTENSA_INS_EE_SRS_ACCX = 958 +XTENSA_INS_EE_STF_128_IP = 959 +XTENSA_INS_EE_STF_128_XP = 960 +XTENSA_INS_EE_STF_64_IP = 961 +XTENSA_INS_EE_STF_64_XP = 962 +XTENSA_INS_EE_STXQ_32 = 963 +XTENSA_INS_EE_ST_ACCX_IP = 964 +XTENSA_INS_EE_ST_QACC_H_H_32_IP = 965 +XTENSA_INS_EE_ST_QACC_H_L_128_IP = 966 +XTENSA_INS_EE_ST_QACC_L_H_32_IP = 967 +XTENSA_INS_EE_ST_QACC_L_L_128_IP = 968 +XTENSA_INS_EE_ST_UA_STATE_IP = 969 +XTENSA_INS_EE_VADDS_S16 = 970 +XTENSA_INS_EE_VADDS_S16_LD_INCP = 971 +XTENSA_INS_EE_VADDS_S16_ST_INCP = 972 +XTENSA_INS_EE_VADDS_S32 = 973 +XTENSA_INS_EE_VADDS_S32_LD_INCP = 974 +XTENSA_INS_EE_VADDS_S32_ST_INCP = 975 +XTENSA_INS_EE_VADDS_S8 = 976 +XTENSA_INS_EE_VADDS_S8_LD_INCP = 977 +XTENSA_INS_EE_VADDS_S8_ST_INCP = 978 +XTENSA_INS_EE_VCMP_EQ_S16 = 979 +XTENSA_INS_EE_VCMP_EQ_S32 = 980 +XTENSA_INS_EE_VCMP_EQ_S8 = 981 +XTENSA_INS_EE_VCMP_GT_S16 = 982 +XTENSA_INS_EE_VCMP_GT_S32 = 983 +XTENSA_INS_EE_VCMP_GT_S8 = 984 +XTENSA_INS_EE_VCMP_LT_S16 = 985 +XTENSA_INS_EE_VCMP_LT_S32 = 986 +XTENSA_INS_EE_VCMP_LT_S8 = 987 +XTENSA_INS_EE_VLDBC_16 = 988 +XTENSA_INS_EE_VLDBC_16_IP = 989 +XTENSA_INS_EE_VLDBC_16_XP = 990 +XTENSA_INS_EE_VLDBC_32 = 991 +XTENSA_INS_EE_VLDBC_32_IP = 992 +XTENSA_INS_EE_VLDBC_32_XP = 993 +XTENSA_INS_EE_VLDBC_8 = 994 +XTENSA_INS_EE_VLDBC_8_IP = 995 +XTENSA_INS_EE_VLDBC_8_XP = 996 +XTENSA_INS_EE_VLDHBC_16_INCP = 997 +XTENSA_INS_EE_VLD_128_IP = 998 +XTENSA_INS_EE_VLD_128_XP = 999 +XTENSA_INS_EE_VLD_H_64_IP = 1000 +XTENSA_INS_EE_VLD_H_64_XP = 1001 +XTENSA_INS_EE_VLD_L_64_IP = 1002 +XTENSA_INS_EE_VLD_L_64_XP = 1003 +XTENSA_INS_EE_VMAX_S16 = 1004 +XTENSA_INS_EE_VMAX_S16_LD_INCP = 1005 +XTENSA_INS_EE_VMAX_S16_ST_INCP = 1006 +XTENSA_INS_EE_VMAX_S32 = 1007 +XTENSA_INS_EE_VMAX_S32_LD_INCP = 1008 +XTENSA_INS_EE_VMAX_S32_ST_INCP = 1009 +XTENSA_INS_EE_VMAX_S8 = 1010 +XTENSA_INS_EE_VMAX_S8_LD_INCP = 1011 +XTENSA_INS_EE_VMAX_S8_ST_INCP = 1012 +XTENSA_INS_EE_VMIN_S16 = 1013 +XTENSA_INS_EE_VMIN_S16_LD_INCP = 1014 +XTENSA_INS_EE_VMIN_S16_ST_INCP = 1015 +XTENSA_INS_EE_VMIN_S32 = 1016 +XTENSA_INS_EE_VMIN_S32_LD_INCP = 1017 +XTENSA_INS_EE_VMIN_S32_ST_INCP = 1018 +XTENSA_INS_EE_VMIN_S8 = 1019 +XTENSA_INS_EE_VMIN_S8_LD_INCP = 1020 +XTENSA_INS_EE_VMIN_S8_ST_INCP = 1021 +XTENSA_INS_EE_VMULAS_S16_ACCX = 1022 +XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP = 1023 +XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP_QUP = 1024 +XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP = 1025 +XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP_QUP = 1026 +XTENSA_INS_EE_VMULAS_S16_QACC = 1027 +XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP = 1028 +XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP_QUP = 1029 +XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP = 1030 +XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP_QUP = 1031 +XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP = 1032 +XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP_QUP = 1033 +XTENSA_INS_EE_VMULAS_S8_ACCX = 1034 +XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP = 1035 +XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP_QUP = 1036 +XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP = 1037 +XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP_QUP = 1038 +XTENSA_INS_EE_VMULAS_S8_QACC = 1039 +XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP = 1040 +XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP_QUP = 1041 +XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP = 1042 +XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP_QUP = 1043 +XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP = 1044 +XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP_QUP = 1045 +XTENSA_INS_EE_VMULAS_U16_ACCX = 1046 +XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP = 1047 +XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP_QUP = 1048 +XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP = 1049 +XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP_QUP = 1050 +XTENSA_INS_EE_VMULAS_U16_QACC = 1051 +XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP = 1052 +XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP_QUP = 1053 +XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP = 1054 +XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP_QUP = 1055 +XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP = 1056 +XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP_QUP = 1057 +XTENSA_INS_EE_VMULAS_U8_ACCX = 1058 +XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP = 1059 +XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP_QUP = 1060 +XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP = 1061 +XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP_QUP = 1062 +XTENSA_INS_EE_VMULAS_U8_QACC = 1063 +XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP = 1064 +XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP_QUP = 1065 +XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP = 1066 +XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP_QUP = 1067 +XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP = 1068 +XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP_QUP = 1069 +XTENSA_INS_EE_VMUL_S16 = 1070 +XTENSA_INS_EE_VMUL_S16_LD_INCP = 1071 +XTENSA_INS_EE_VMUL_S16_ST_INCP = 1072 +XTENSA_INS_EE_VMUL_S8 = 1073 +XTENSA_INS_EE_VMUL_S8_LD_INCP = 1074 +XTENSA_INS_EE_VMUL_S8_ST_INCP = 1075 +XTENSA_INS_EE_VMUL_U16 = 1076 +XTENSA_INS_EE_VMUL_U16_LD_INCP = 1077 +XTENSA_INS_EE_VMUL_U16_ST_INCP = 1078 +XTENSA_INS_EE_VMUL_U8 = 1079 +XTENSA_INS_EE_VMUL_U8_LD_INCP = 1080 +XTENSA_INS_EE_VMUL_U8_ST_INCP = 1081 +XTENSA_INS_EE_VPRELU_S16 = 1082 +XTENSA_INS_EE_VPRELU_S8 = 1083 +XTENSA_INS_EE_VRELU_S16 = 1084 +XTENSA_INS_EE_VRELU_S8 = 1085 +XTENSA_INS_EE_VSL_32 = 1086 +XTENSA_INS_EE_VSMULAS_S16_QACC = 1087 +XTENSA_INS_EE_VSMULAS_S16_QACC_LD_INCP = 1088 +XTENSA_INS_EE_VSMULAS_S8_QACC = 1089 +XTENSA_INS_EE_VSMULAS_S8_QACC_LD_INCP = 1090 +XTENSA_INS_EE_VSR_32 = 1091 +XTENSA_INS_EE_VST_128_IP = 1092 +XTENSA_INS_EE_VST_128_XP = 1093 +XTENSA_INS_EE_VST_H_64_IP = 1094 +XTENSA_INS_EE_VST_H_64_XP = 1095 +XTENSA_INS_EE_VST_L_64_IP = 1096 +XTENSA_INS_EE_VST_L_64_XP = 1097 +XTENSA_INS_EE_VSUBS_S16 = 1098 +XTENSA_INS_EE_VSUBS_S16_LD_INCP = 1099 +XTENSA_INS_EE_VSUBS_S16_ST_INCP = 1100 +XTENSA_INS_EE_VSUBS_S32 = 1101 +XTENSA_INS_EE_VSUBS_S32_LD_INCP = 1102 +XTENSA_INS_EE_VSUBS_S32_ST_INCP = 1103 +XTENSA_INS_EE_VSUBS_S8 = 1104 +XTENSA_INS_EE_VSUBS_S8_LD_INCP = 1105 +XTENSA_INS_EE_VSUBS_S8_ST_INCP = 1106 +XTENSA_INS_EE_VUNZIP_16 = 1107 +XTENSA_INS_EE_VUNZIP_32 = 1108 +XTENSA_INS_EE_VUNZIP_8 = 1109 +XTENSA_INS_EE_VZIP_16 = 1110 +XTENSA_INS_EE_VZIP_32 = 1111 +XTENSA_INS_EE_VZIP_8 = 1112 +XTENSA_INS_EE_WR_MASK_GPIO_OUT = 1113 +XTENSA_INS_EE_XORQ = 1114 +XTENSA_INS_EE_ZERO_ACCX = 1115 +XTENSA_INS_EE_ZERO_Q = 1116 +XTENSA_INS_EE_ZERO_QACC = 1117 +XTENSA_INS_ENTRY = 1118 +XTENSA_INS_ESYNC = 1119 +XTENSA_INS_EXCW = 1120 +XTENSA_INS_EXTUI = 1121 +XTENSA_INS_EXTW = 1122 +XTENSA_INS_FLOAT_S = 1123 +XTENSA_INS_FLOOR_S = 1124 +XTENSA_INS_GET_GPIO_IN = 1125 +XTENSA_INS_ILL = 1126 +XTENSA_INS_ILL_N = 1127 +XTENSA_INS_ISYNC = 1128 +XTENSA_INS_J = 1129 +XTENSA_INS_JX = 1130 +XTENSA_INS_L16SI = 1131 +XTENSA_INS_L16UI = 1132 +XTENSA_INS_L32E = 1133 +XTENSA_INS_L32I = 1134 +XTENSA_INS_L32I_N = 1135 +XTENSA_INS_L32R = 1136 +XTENSA_INS_L8UI = 1137 +XTENSA_INS_LDDEC = 1138 +XTENSA_INS_LDINC = 1139 +XTENSA_INS_LOOP = 1140 +XTENSA_INS_LOOPGTZ = 1141 +XTENSA_INS_LOOPNEZ = 1142 +XTENSA_INS_LSI = 1143 +XTENSA_INS_LSIP = 1144 +XTENSA_INS_LSX = 1145 +XTENSA_INS_LSXP = 1146 +XTENSA_INS_MADDN_S = 1147 +XTENSA_INS_MADD_S = 1148 +XTENSA_INS_MAX = 1149 +XTENSA_INS_MAXU = 1150 +XTENSA_INS_MEMW = 1151 +XTENSA_INS_MIN = 1152 +XTENSA_INS_MINU = 1153 +XTENSA_INS_MKDADJ_S = 1154 +XTENSA_INS_MKSADJ_S = 1155 +XTENSA_INS_MOVEQZ = 1156 +XTENSA_INS_MOVEQZ_S = 1157 +XTENSA_INS_MOVF = 1158 +XTENSA_INS_MOVF_S = 1159 +XTENSA_INS_MOVGEZ = 1160 +XTENSA_INS_MOVGEZ_S = 1161 +XTENSA_INS_MOVI = 1162 +XTENSA_INS_MOVI_N = 1163 +XTENSA_INS_MOVLTZ = 1164 +XTENSA_INS_MOVLTZ_S = 1165 +XTENSA_INS_MOVNEZ = 1166 +XTENSA_INS_MOVNEZ_S = 1167 +XTENSA_INS_MOVSP = 1168 +XTENSA_INS_MOVT = 1169 +XTENSA_INS_MOVT_S = 1170 +XTENSA_INS_MOV_N = 1171 +XTENSA_INS_MOV_S = 1172 +XTENSA_INS_MSUB_S = 1173 +XTENSA_INS_MUL16S = 1174 +XTENSA_INS_MUL16U = 1175 +XTENSA_INS_MULA_AA_HH = 1176 +XTENSA_INS_MULA_AA_HL = 1177 +XTENSA_INS_MULA_AA_LH = 1178 +XTENSA_INS_MULA_AA_LL = 1179 +XTENSA_INS_MULA_AD_HH = 1180 +XTENSA_INS_MULA_AD_HL = 1181 +XTENSA_INS_MULA_AD_LH = 1182 +XTENSA_INS_MULA_AD_LL = 1183 +XTENSA_INS_MULA_DA_HH = 1184 +XTENSA_INS_MULA_DA_HH_LDDEC = 1185 +XTENSA_INS_MULA_DA_HH_LDINC = 1186 +XTENSA_INS_MULA_DA_HL = 1187 +XTENSA_INS_MULA_DA_HL_LDDEC = 1188 +XTENSA_INS_MULA_DA_HL_LDINC = 1189 +XTENSA_INS_MULA_DA_LH = 1190 +XTENSA_INS_MULA_DA_LH_LDDEC = 1191 +XTENSA_INS_MULA_DA_LH_LDINC = 1192 +XTENSA_INS_MULA_DA_LL = 1193 +XTENSA_INS_MULA_DA_LL_LDDEC = 1194 +XTENSA_INS_MULA_DA_LL_LDINC = 1195 +XTENSA_INS_MULA_DD_HH = 1196 +XTENSA_INS_MULA_DD_HH_LDDEC = 1197 +XTENSA_INS_MULA_DD_HH_LDINC = 1198 +XTENSA_INS_MULA_DD_HL = 1199 +XTENSA_INS_MULA_DD_HL_LDDEC = 1200 +XTENSA_INS_MULA_DD_HL_LDINC = 1201 +XTENSA_INS_MULA_DD_LH = 1202 +XTENSA_INS_MULA_DD_LH_LDDEC = 1203 +XTENSA_INS_MULA_DD_LH_LDINC = 1204 +XTENSA_INS_MULA_DD_LL = 1205 +XTENSA_INS_MULA_DD_LL_LDDEC = 1206 +XTENSA_INS_MULA_DD_LL_LDINC = 1207 +XTENSA_INS_MULL = 1208 +XTENSA_INS_MULSH = 1209 +XTENSA_INS_MULS_AA_HH = 1210 +XTENSA_INS_MULS_AA_HL = 1211 +XTENSA_INS_MULS_AA_LH = 1212 +XTENSA_INS_MULS_AA_LL = 1213 +XTENSA_INS_MULS_AD_HH = 1214 +XTENSA_INS_MULS_AD_HL = 1215 +XTENSA_INS_MULS_AD_LH = 1216 +XTENSA_INS_MULS_AD_LL = 1217 +XTENSA_INS_MULS_DA_HH = 1218 +XTENSA_INS_MULS_DA_HL = 1219 +XTENSA_INS_MULS_DA_LH = 1220 +XTENSA_INS_MULS_DA_LL = 1221 +XTENSA_INS_MULS_DD_HH = 1222 +XTENSA_INS_MULS_DD_HL = 1223 +XTENSA_INS_MULS_DD_LH = 1224 +XTENSA_INS_MULS_DD_LL = 1225 +XTENSA_INS_MULUH = 1226 +XTENSA_INS_MUL_AA_HH = 1227 +XTENSA_INS_MUL_AA_HL = 1228 +XTENSA_INS_MUL_AA_LH = 1229 +XTENSA_INS_MUL_AA_LL = 1230 +XTENSA_INS_MUL_AD_HH = 1231 +XTENSA_INS_MUL_AD_HL = 1232 +XTENSA_INS_MUL_AD_LH = 1233 +XTENSA_INS_MUL_AD_LL = 1234 +XTENSA_INS_MUL_DA_HH = 1235 +XTENSA_INS_MUL_DA_HL = 1236 +XTENSA_INS_MUL_DA_LH = 1237 +XTENSA_INS_MUL_DA_LL = 1238 +XTENSA_INS_MUL_DD_HH = 1239 +XTENSA_INS_MUL_DD_HL = 1240 +XTENSA_INS_MUL_DD_LH = 1241 +XTENSA_INS_MUL_DD_LL = 1242 +XTENSA_INS_MUL_S = 1243 +XTENSA_INS_NEG = 1244 +XTENSA_INS_NEG_S = 1245 +XTENSA_INS_NEXP01_S = 1246 +XTENSA_INS_NOP = 1247 +XTENSA_INS_NSA = 1248 +XTENSA_INS_NSAU = 1249 +XTENSA_INS_OEQ_S = 1250 +XTENSA_INS_OLE_S = 1251 +XTENSA_INS_OLT_S = 1252 +XTENSA_INS_OR = 1253 +XTENSA_INS_ORB = 1254 +XTENSA_INS_ORBC = 1255 +XTENSA_INS_QUOS = 1256 +XTENSA_INS_QUOU = 1257 +XTENSA_INS_RECIP0_S = 1258 +XTENSA_INS_REMS = 1259 +XTENSA_INS_REMU = 1260 +XTENSA_INS_RER = 1261 +XTENSA_INS_RET = 1262 +XTENSA_INS_RETW = 1263 +XTENSA_INS_RETW_N = 1264 +XTENSA_INS_RET_N = 1265 +XTENSA_INS_RFDE = 1266 +XTENSA_INS_RFE = 1267 +XTENSA_INS_RFI = 1268 +XTENSA_INS_RFR = 1269 +XTENSA_INS_RFWO = 1270 +XTENSA_INS_RFWU = 1271 +XTENSA_INS_ROTW = 1272 +XTENSA_INS_ROUND_S = 1273 +XTENSA_INS_RSIL = 1274 +XTENSA_INS_RSQRT0_S = 1275 +XTENSA_INS_RSR = 1276 +XTENSA_INS_RSYNC = 1277 +XTENSA_INS_RUR = 1278 +XTENSA_INS_RUR_ACCX_0 = 1279 +XTENSA_INS_RUR_ACCX_1 = 1280 +XTENSA_INS_RUR_AE_BITHEAD = 1281 +XTENSA_INS_RUR_AE_BITPTR = 1282 +XTENSA_INS_RUR_AE_BITSUSED = 1283 +XTENSA_INS_RUR_AE_CBEGIN0 = 1284 +XTENSA_INS_RUR_AE_CEND0 = 1285 +XTENSA_INS_RUR_AE_CWRAP = 1286 +XTENSA_INS_RUR_AE_CW_SD_NO = 1287 +XTENSA_INS_RUR_AE_FIRST_TS = 1288 +XTENSA_INS_RUR_AE_NEXTOFFSET = 1289 +XTENSA_INS_RUR_AE_OVERFLOW = 1290 +XTENSA_INS_RUR_AE_OVF_SAR = 1291 +XTENSA_INS_RUR_AE_SAR = 1292 +XTENSA_INS_RUR_AE_SEARCHDONE = 1293 +XTENSA_INS_RUR_AE_TABLESIZE = 1294 +XTENSA_INS_RUR_AE_TS_FTS_BU_BP = 1295 +XTENSA_INS_RUR_FFT_BIT_WIDTH = 1296 +XTENSA_INS_RUR_GPIO_OUT = 1297 +XTENSA_INS_RUR_QACC_H_0 = 1298 +XTENSA_INS_RUR_QACC_H_1 = 1299 +XTENSA_INS_RUR_QACC_H_2 = 1300 +XTENSA_INS_RUR_QACC_H_3 = 1301 +XTENSA_INS_RUR_QACC_H_4 = 1302 +XTENSA_INS_RUR_QACC_L_0 = 1303 +XTENSA_INS_RUR_QACC_L_1 = 1304 +XTENSA_INS_RUR_QACC_L_2 = 1305 +XTENSA_INS_RUR_QACC_L_3 = 1306 +XTENSA_INS_RUR_QACC_L_4 = 1307 +XTENSA_INS_RUR_SAR_BYTE = 1308 +XTENSA_INS_RUR_UA_STATE_0 = 1309 +XTENSA_INS_RUR_UA_STATE_1 = 1310 +XTENSA_INS_RUR_UA_STATE_2 = 1311 +XTENSA_INS_RUR_UA_STATE_3 = 1312 +XTENSA_INS_S16I = 1313 +XTENSA_INS_S32C1I = 1314 +XTENSA_INS_S32E = 1315 +XTENSA_INS_S32I = 1316 +XTENSA_INS_S32I_N = 1317 +XTENSA_INS_S8I = 1318 +XTENSA_INS_SET_BIT_GPIO_OUT = 1319 +XTENSA_INS_SEXT = 1320 +XTENSA_INS_SIMCALL = 1321 +XTENSA_INS_SLL = 1322 +XTENSA_INS_SLLI = 1323 +XTENSA_INS_SQRT0_S = 1324 +XTENSA_INS_SRA = 1325 +XTENSA_INS_SRAI = 1326 +XTENSA_INS_SRC = 1327 +XTENSA_INS_SRL = 1328 +XTENSA_INS_SRLI = 1329 +XTENSA_INS_SSA8L = 1330 +XTENSA_INS_SSAI = 1331 +XTENSA_INS_SSI = 1332 +XTENSA_INS_SSIP = 1333 +XTENSA_INS_SSL = 1334 +XTENSA_INS_SSR = 1335 +XTENSA_INS_SSX = 1336 +XTENSA_INS_SSXP = 1337 +XTENSA_INS_SUB = 1338 +XTENSA_INS_SUBX2 = 1339 +XTENSA_INS_SUBX4 = 1340 +XTENSA_INS_SUBX8 = 1341 +XTENSA_INS_SUB_S = 1342 +XTENSA_INS_SYSCALL = 1343 +XTENSA_INS_TRUNC_S = 1344 +XTENSA_INS_UEQ_S = 1345 +XTENSA_INS_UFLOAT_S = 1346 +XTENSA_INS_ULE_S = 1347 +XTENSA_INS_ULT_S = 1348 +XTENSA_INS_UMUL_AA_HH = 1349 +XTENSA_INS_UMUL_AA_HL = 1350 +XTENSA_INS_UMUL_AA_LH = 1351 +XTENSA_INS_UMUL_AA_LL = 1352 +XTENSA_INS_UN_S = 1353 +XTENSA_INS_UTRUNC_S = 1354 +XTENSA_INS_WAITI = 1355 +XTENSA_INS_WDTLB = 1356 +XTENSA_INS_WER = 1357 +XTENSA_INS_WFR = 1358 +XTENSA_INS_WITLB = 1359 +XTENSA_INS_WR_MASK_GPIO_OUT = 1360 +XTENSA_INS_WSR = 1361 +XTENSA_INS_WUR = 1362 +XTENSA_INS_WUR_ACCX_0 = 1363 +XTENSA_INS_WUR_ACCX_1 = 1364 +XTENSA_INS_WUR_AE_BITHEAD = 1365 +XTENSA_INS_WUR_AE_BITPTR = 1366 +XTENSA_INS_WUR_AE_BITSUSED = 1367 +XTENSA_INS_WUR_AE_CBEGIN0 = 1368 +XTENSA_INS_WUR_AE_CEND0 = 1369 +XTENSA_INS_WUR_AE_CWRAP = 1370 +XTENSA_INS_WUR_AE_CW_SD_NO = 1371 +XTENSA_INS_WUR_AE_FIRST_TS = 1372 +XTENSA_INS_WUR_AE_NEXTOFFSET = 1373 +XTENSA_INS_WUR_AE_OVERFLOW = 1374 +XTENSA_INS_WUR_AE_OVF_SAR = 1375 +XTENSA_INS_WUR_AE_SAR = 1376 +XTENSA_INS_WUR_AE_SEARCHDONE = 1377 +XTENSA_INS_WUR_AE_TABLESIZE = 1378 +XTENSA_INS_WUR_AE_TS_FTS_BU_BP = 1379 +XTENSA_INS_WUR_FCR = 1380 +XTENSA_INS_WUR_FFT_BIT_WIDTH = 1381 +XTENSA_INS_WUR_FSR = 1382 +XTENSA_INS_WUR_GPIO_OUT = 1383 +XTENSA_INS_WUR_QACC_H_0 = 1384 +XTENSA_INS_WUR_QACC_H_1 = 1385 +XTENSA_INS_WUR_QACC_H_2 = 1386 +XTENSA_INS_WUR_QACC_H_3 = 1387 +XTENSA_INS_WUR_QACC_H_4 = 1388 +XTENSA_INS_WUR_QACC_L_0 = 1389 +XTENSA_INS_WUR_QACC_L_1 = 1390 +XTENSA_INS_WUR_QACC_L_2 = 1391 +XTENSA_INS_WUR_QACC_L_3 = 1392 +XTENSA_INS_WUR_QACC_L_4 = 1393 +XTENSA_INS_WUR_SAR_BYTE = 1394 +XTENSA_INS_WUR_UA_STATE_0 = 1395 +XTENSA_INS_WUR_UA_STATE_1 = 1396 +XTENSA_INS_WUR_UA_STATE_2 = 1397 +XTENSA_INS_WUR_UA_STATE_3 = 1398 +XTENSA_INS_XOR = 1399 +XTENSA_INS_XORB = 1400 +XTENSA_INS_XSR = 1401 +XTENSA_INS__L32I = 1402 +XTENSA_INS__L32I_N = 1403 +XTENSA_INS__MOVI = 1404 +XTENSA_INS__S32I = 1405 +XTENSA_INS__S32I_N = 1406 +XTENSA_INS__SLLI = 1407 +XTENSA_INS__SRLI = 1408 +XTENSA_INS_MV_QR = 1409 XTENSA_GRP_INVALID = 0 XTENSA_GRP_CALL = 1 XTENSA_GRP_JUMP = 2 XTENSA_GRP_RET = 3 XTENSA_FEATURE_HASDENSITY = 128 -XTENSA_GRP_ENDING = 129 +XTENSA_FEATURE_HASSINGLEFLOAT = 129 +XTENSA_FEATURE_HASWINDOWED = 130 +XTENSA_FEATURE_HASBOOLEAN = 131 +XTENSA_FEATURE_HASLOOP = 132 +XTENSA_FEATURE_HASSEXT = 133 +XTENSA_FEATURE_HASCLAMPS = 134 +XTENSA_FEATURE_HASNSA = 135 +XTENSA_FEATURE_HASMINMAX = 136 +XTENSA_FEATURE_HASMUL16 = 137 +XTENSA_FEATURE_HASMUL32 = 138 +XTENSA_FEATURE_HASMUL32HIGH = 139 +XTENSA_FEATURE_HASDIV32 = 140 +XTENSA_FEATURE_HASMAC16 = 141 +XTENSA_FEATURE_HASDFPACCEL = 142 +XTENSA_FEATURE_HASS32C1I = 143 +XTENSA_FEATURE_HASTHREADPTR = 144 +XTENSA_FEATURE_HASEXTENDEDL32R = 145 +XTENSA_FEATURE_HASATOMCTL = 146 +XTENSA_FEATURE_HASMEMCTL = 147 +XTENSA_FEATURE_HASDEBUG = 148 +XTENSA_FEATURE_HASEXCEPTION = 149 +XTENSA_FEATURE_HASHIGHPRIINTERRUPTS = 150 +XTENSA_FEATURE_HASCOPROCESSOR = 151 +XTENSA_FEATURE_HASINTERRUPT = 152 +XTENSA_FEATURE_HASRELOCATABLEVECTOR = 153 +XTENSA_FEATURE_HASTIMERINT = 154 +XTENSA_FEATURE_HASPRID = 155 +XTENSA_FEATURE_HASREGIONPROTECTION = 156 +XTENSA_FEATURE_HASMISCSR = 157 +XTENSA_FEATURE_HASESP32S2OPS = 158 +XTENSA_FEATURE_HASESP32S3OPS = 159 +XTENSA_FEATURE_HASHIFI3 = 160 +XTENSA_FEATURE_HASFORCEDATOMICS = 161 +XTENSA_GRP_ENDING = 162 + +XTENSA_INSN_FORM_INVALID = 0 +XTENSA_INSN_FORM_RRR = 1 +XTENSA_INSN_FORM_RRI8 = 2 +XTENSA_INSN_FORM_RRRN = 3 +XTENSA_INSN_FORM_AEINST24 = 4 +XTENSA_INSN_FORM_BRI12 = 5 +XTENSA_INSN_FORM_CALL = 6 +XTENSA_INSN_FORM_CALLX = 7 +XTENSA_INSN_FORM_EE_INST24 = 8 +XTENSA_INSN_FORM_RRI4 = 9 +XTENSA_INSN_FORM_RI16 = 10 +XTENSA_INSN_FORM_RI7 = 11 +XTENSA_INSN_FORM_RSR = 12 XTENSA_OP_INVALID = CS_OP_INVALID XTENSA_OP_REG = CS_OP_REG XTENSA_OP_IMM = CS_OP_IMM XTENSA_OP_MEM = CS_OP_MEM XTENSA_OP_MEM_REG = CS_OP_MEM_REG XTENSA_OP_MEM_IMM = CS_OP_MEM_IMM -XTENSA_OP_L32R = 130 +XTENSA_OP_L32R = 13 diff --git a/bindings/python/cstest_py/pyproject.toml b/bindings/python/cstest_py/pyproject.toml index 34b27c5aaa..5df6317fef 100644 --- a/bindings/python/cstest_py/pyproject.toml +++ b/bindings/python/cstest_py/pyproject.toml @@ -5,14 +5,14 @@ name = "cstest_py" version = "0.1.0" dependencies = [ - "pyyaml >= 6.0.2", - "capstone >= 5.0.0", + "pyyaml >= 6.0.2", + "capstone >= 5.0.0", ] requires-python = ">= 3.8" [tool.setuptools] packages = ["cstest_py"] -package-dir = {"" = "src"} +package-dir = { "" = "src" } [project.scripts] cstest_py = "cstest_py.cstest:main" diff --git a/bindings/python/cstest_py/src/cstest_py/cstest.py b/bindings/python/cstest_py/src/cstest_py/cstest.py index 4fd244914b..6e3590e2c7 100755 --- a/bindings/python/cstest_py/src/cstest_py/cstest.py +++ b/bindings/python/cstest_py/src/cstest_py/cstest.py @@ -7,7 +7,6 @@ import argparse import logging -import subprocess as sp import sys import os import yaml @@ -405,34 +404,16 @@ def run_tests(self): self.stats.print_evaluate() -def get_repo_root() -> str | None: - res = sp.run(["git", "rev-parse", "--show-toplevel"], capture_output=True) - if res.stderr: - log.error("Could not get repository root directory.") - return None - return res.stdout.decode("utf8").strip() - - def parse_args() -> argparse.Namespace: parser = argparse.ArgumentParser( prog="Python CSTest", - description="Pyton binding cstest implementation.", + description="Python binding cstest implementation.", + ) + parser.add_argument( + dest="search_dir", + help="Directory to search for .yaml test files.", + type=Path, ) - repo_root = get_repo_root() - if repo_root: - parser.add_argument( - dest="search_dir", - help="Directory to search for .yaml test files.", - default=Path(f"{repo_root}/tests/"), - type=Path, - ) - else: - parser.add_argument( - dest="search_dir", - help="Directory to search for .yaml test files.", - required=True, - type=Path, - ) parser.add_argument( "-e", dest="exclude", diff --git a/bindings/python/pyproject.toml b/bindings/python/pyproject.toml index fed528d4a7..3906c86149 100644 --- a/bindings/python/pyproject.toml +++ b/bindings/python/pyproject.toml @@ -1,3 +1,3 @@ [build-system] -requires = ["setuptools"] +requires = ["setuptools", "build"] build-backend = "setuptools.build_meta" diff --git a/bindings/python/setup.py b/bindings/python/setup.py index 63f2451233..f3e4593f41 100755 --- a/bindings/python/setup.py +++ b/bindings/python/setup.py @@ -1,33 +1,25 @@ -#!/usr/bin/env python3 +# SPDX-FileCopyrightText: 2024 Antelox +# SPDX-License-Identifier: BSD-3 import glob +import logging import os import shutil import sys -import platform - -import logging from setuptools import setup -from sysconfig import get_platform -from setuptools.command.build import build +from setuptools.command.build_py import build_py from setuptools.command.sdist import sdist -from setuptools.command.bdist_egg import bdist_egg logger = logging.getLogger(__name__) logging.basicConfig(level=logging.INFO) -SYSTEM = sys.platform - -# adapted from commit e504b81 of Nguyen Tan Cong -# Reference: https://docs.python.org/2/library/platform.html#cross-platform -IS_64BITS = sys.maxsize > 2**32 - # are we building from the repository or from a source distribution? ROOT_DIR = os.path.dirname(os.path.realpath(__file__)) LIBS_DIR = os.path.join(ROOT_DIR, 'capstone', 'lib') HEADERS_DIR = os.path.join(ROOT_DIR, 'capstone', 'include') SRC_DIR = os.path.join(ROOT_DIR, 'src') BUILD_DIR = SRC_DIR if os.path.exists(SRC_DIR) else os.path.join(ROOT_DIR, '../..') +BUILD_PYTHON = os.path.join(BUILD_DIR, 'build_python') # Parse version from pkgconfig.mk VERSION_DATA = {} @@ -50,8 +42,8 @@ VERSION_DATA[k] = v if 'PKG_MAJOR' not in VERSION_DATA or \ - 'PKG_MINOR' not in VERSION_DATA or \ - 'PKG_EXTRA' not in VERSION_DATA: + 'PKG_MINOR' not in VERSION_DATA or \ + 'PKG_EXTRA' not in VERSION_DATA: raise Exception("Malformed pkgconfig.mk") if 'PKG_TAG' in VERSION_DATA: @@ -59,10 +51,10 @@ else: VERSION = '{PKG_MAJOR}.{PKG_MINOR}.{PKG_EXTRA}'.format(**VERSION_DATA) -if SYSTEM == 'darwin': +if sys.platform == 'darwin': VERSIONED_LIBRARY_FILE = "libcapstone.{PKG_MAJOR}.dylib".format(**VERSION_DATA) LIBRARY_FILE = "libcapstone.dylib" -elif SYSTEM in ('win32', 'cygwin'): +elif sys.platform in ('win32', 'cygwin'): VERSIONED_LIBRARY_FILE = "capstone.dll" LIBRARY_FILE = "capstone.dll" else: @@ -76,7 +68,8 @@ def clean_bins(): def copy_sources(): - """Copy the C sources into the source directory. + """ + Copy the C sources into the source directory. This rearranges the source files under the python distribution directory. """ @@ -91,11 +84,11 @@ def copy_sources(): shutil.copytree(os.path.join(BUILD_DIR, "include"), os.path.join(SRC_DIR, "include")) src.extend(glob.glob(os.path.join(BUILD_DIR, "*.[ch]"))) - + src.extend(glob.glob(os.path.join(BUILD_DIR, "*.m[dk]"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "*.in"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "LICENSES/*"))) - src.extend(glob.glob(os.path.join(BUILD_DIR, "README"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "*.TXT"))) - src.extend(glob.glob(os.path.join(BUILD_DIR, "RELEASE_NOTES"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "ChangeLog"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "CMakeLists.txt"))) for filename in src: @@ -125,85 +118,64 @@ def build_libraries(): shutil.copy(os.path.join(ROOT_DIR, 'prebuilt', LIBRARY_FILE), LIBS_DIR) return - os.chdir(BUILD_DIR) - - # Windows build: this process requires few things: - # - MSVC installed - # - Run this command in an environment setup for MSVC - if not os.path.exists("build_py"): - os.mkdir("build_py") - os.chdir("build_py") - print("Build Directory: {}\n".format(os.getcwd())) - # Only build capstone.dll / libcapstone.dylib - if SYSTEM in ('win32', 'cygwin'): - os.system('cmake -DCMAKE_BUILD_TYPE=Release -DCAPSTONE_BUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_STATIC_LIBS=OFF -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "NMake Makefiles" ..') + if not os.path.exists(BUILD_PYTHON): + os.mkdir(BUILD_PYTHON) + + logger.info("Build Directory: {}\n".format(BUILD_PYTHON)) + + conf = 'Debug' if int(os.getenv('DEBUG', 0)) else 'Release' + cmake_args = ['cmake', + '-DCAPSTONE_BUILD_SHARED_LIBS=ON', + '-DCAPSTONE_BUILD_STATIC_LIBS=OFF', + '-DCAPSTONE_BUILD_LEGACY_TESTS=OFF', + '-DCAPSTONE_BUILD_CSTOOL=OFF' + ] + cmake_build = ['cmake', + '--build', + '.' + ] + os.chdir(BUILD_PYTHON) + + if sys.platform in ('win32', 'cygwin'): + # Windows build: this process requires few things: + # - MSVC installed + # - Run this command in an environment setup for MSVC + cmake_args += ['-DCMAKE_BUILD_TYPE=' + conf, + '-G "NMake Makefiles"' + ] elif 'AFL_NOOPT' in os.environ: # build for test_corpus - os.system('cmake -DCAPSTONE_BUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF ..') + pass else: - os.system('cmake -DCMAKE_BUILD_TYPE=Release -DCAPSTONE_BUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "Unix Makefiles" ..') - os.system("cmake --build .") + cmake_args += ['-DCMAKE_BUILD_TYPE=' + conf, + '-G "Unix Makefiles"' + ] + cmake_build += ['-j', str(os.getenv("THREADS", "4"))] + + os.system(' '.join(cmake_args + ['..'])) + os.system(' '.join(cmake_build)) shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE)) os.chdir(cwd) -class custom_sdist(sdist): +class CustomSDist(sdist): def run(self): clean_bins() copy_sources() - return sdist.run(self) + return super().run() -class custom_build(build): +class CustomBuild(build_py): def run(self): if 'LIBCAPSTONE_PATH' in os.environ: logger.info('Skipping building C extensions since LIBCAPSTONE_PATH is set') else: logger.info('Building C extensions') build_libraries() - return build.run(self) - - -class custom_bdist_egg(bdist_egg): - def run(self): - self.run_command('build') - return bdist_egg.run(self) + return super().run() -cmdclass = {} -cmdclass['build'] = custom_build -cmdclass['sdist'] = custom_sdist -cmdclass['bdist_egg'] = custom_bdist_egg - -try: - from setuptools.command.develop import develop - - class custom_develop(develop): - def run(self): - logger.info("Building C extensions") - build_libraries() - return develop.run(self) - - cmdclass['develop'] = custom_develop -except ImportError: - print("Proper 'develop' support unavailable.") - -if 'bdist_wheel' in sys.argv and '--plat-name' not in sys.argv: - # Inject the platform identifier into argv. - # Platform tags are described here: - # https://packaging.python.org/en/latest/specifications/platform-compatibility-tags - # - # I couldn't really find out in time why we need to inject the platform here? - # The cibuildwheel doesn't need it for the Windows job. But for Mac and Linux. - # This here is very dirty and will maybe break in the future. - # Sorry if this is the case and you read this. - # See: https://github.com/capstone-engine/capstone/issues/2445 - idx = sys.argv.index('bdist_wheel') + 1 - sys.argv.insert(idx, '--plat-name') - name = get_platform() - sys.argv.insert(idx + 1, name.replace('.', '_').replace('-', '_')) - setup( provides=['capstone'], packages=['capstone'], @@ -218,14 +190,18 @@ def run(self): python_requires='>=3.8', classifiers=[ 'License :: OSI Approved :: BSD License', - 'Programming Language :: Python :: 3', + 'Programming Language :: Python :: 3.8', + 'Programming Language :: Python :: 3.9', + 'Programming Language :: Python :: 3.10', + 'Programming Language :: Python :: 3.11', + 'Programming Language :: Python :: 3.12', + 'Programming Language :: Python :: 3.13', ], - cmdclass=cmdclass, - zip_safe=False, - include_package_data=True, + cmdclass={'build_py': CustomBuild, 'sdist': CustomSDist}, package_data={ "capstone": ["lib/*", "include/capstone/*"], }, + has_ext_modules=lambda: True, # It's not a Pure Python wheel install_requires=[ "importlib_resources;python_version<'3.9'", ], diff --git a/cs.c b/cs.c index c5a166da9b..126c31f889 100644 --- a/cs.c +++ b/cs.c @@ -260,7 +260,8 @@ typedef struct cs_arch_config { { \ Xtensa_global_init, \ Xtensa_option, \ - ~(CS_MODE_XTENSA), \ + ~(CS_MODE_XTENSA_ESP32 | CS_MODE_XTENSA_ESP32S2 | \ + CS_MODE_XTENSA_ESP8266), \ } #ifdef CAPSTONE_USE_ARCH_REGISTRATION diff --git a/cstool/cstool.c b/cstool/cstool.c index 7669a291bb..af34548f66 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -221,8 +221,9 @@ static struct { { "loongarch32", "LoongArch 32-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 }, { "loongarch64", "LoongArch 64-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 }, - { "xtensa", "Xtensa", CS_ARCH_XTENSA, CS_MODE_XTENSA }, - { "xtensabe", "Xtensa, big endian", CS_ARCH_XTENSA, CS_MODE_XTENSA | CS_MODE_BIG_ENDIAN }, + { "esp32", "Xtensa ESP32", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32 }, + { "esp32s2", "Xtensa ESP32S2", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32S2 }, + { "esp8266", "Xtensa ESP8266", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP8266 }, { NULL } }; diff --git a/cstool/cstool_xtensa.c b/cstool/cstool_xtensa.c index e280a4a703..212b8c49d4 100644 --- a/cstool/cstool_xtensa.c +++ b/cstool/cstool_xtensa.c @@ -3,6 +3,23 @@ #include #include +#include + +static const char *xtensa_insn_form_strs[] = { + [XTENSA_INSN_FORM_INVALID] = "XTENSA_INSN_FORM_INVALID", + [XTENSA_INSN_FORM_RRR] = "XTENSA_INSN_FORM_RRR", + [XTENSA_INSN_FORM_RRI8] = "XTENSA_INSN_FORM_RRI8", + [XTENSA_INSN_FORM_RRRN] = "XTENSA_INSN_FORM_RRRN", + [XTENSA_INSN_FORM_AEINST24] = "XTENSA_INSN_FORM_AEINST24", + [XTENSA_INSN_FORM_BRI12] = "XTENSA_INSN_FORM_BRI12", + [XTENSA_INSN_FORM_CALL] = "XTENSA_INSN_FORM_CALL", + [XTENSA_INSN_FORM_CALLX] = "XTENSA_INSN_FORM_CALLX", + [XTENSA_INSN_FORM_EE_INST24] = "XTENSA_INSN_FORM_EE_INST24", + [XTENSA_INSN_FORM_RRI4] = "XTENSA_INSN_FORM_RRI4", + [XTENSA_INSN_FORM_RI16] = "XTENSA_INSN_FORM_RI16", + [XTENSA_INSN_FORM_RI7] = "XTENSA_INSN_FORM_RI7", + [XTENSA_INSN_FORM_RSR] = "XTENSA_INSN_FORM_RSR", +}; void print_insn_detail_xtensa(csh handle, cs_insn *ins) { @@ -16,6 +33,10 @@ void print_insn_detail_xtensa(csh handle, cs_insn *ins) cs_xtensa *detail = &(ins->detail->xtensa); + if (detail->format && detail->format < XTENSA_INSN_FORM_MAX) { + printf("\tformat: %s\n", xtensa_insn_form_strs[detail->format]); + } + if (detail->op_count) printf("\top_count: %u\n", detail->op_count); @@ -30,7 +51,7 @@ void print_insn_detail_xtensa(csh handle, cs_insn *ins) else if (op->type == CS_OP_MEM) printf("\t\toperands[%u].type: MEM\n" "\t\t\t.mem.base: REG = %s\n" - "\t\t\t.mem.disp: 0x%" PRIx8 "\n", + "\t\t\t.mem.disp: 0x%" PRIx32 "\n", i, cs_reg_name(handle, op->mem.base), op->mem.disp); else if (op->type == XTENSA_OP_L32R) { diff --git a/debian/postinst b/debian/postinst deleted file mode 100644 index 35ec39b8a2..0000000000 --- a/debian/postinst +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/bash -# postinst script for capstone package -set -e - -# Update the shared library cache -ldconfig diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index 32bd3fe128..c8c55d75b8 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -222,7 +222,9 @@ typedef enum cs_mode { CS_MODE_SYSTEMZ_Z15 = 1 << 13, ///< Enables features of the Z15 processor CS_MODE_SYSTEMZ_Z16 = 1 << 14, ///< Enables features of the Z16 processor CS_MODE_SYSTEMZ_GENERIC = 1 << 15, ///< Enables features of the generic processor - CS_MODE_XTENSA = 1 << 1, ///< Xtensa + CS_MODE_XTENSA_ESP32 = 1 << 1, ///< Xtensa ESP32 + CS_MODE_XTENSA_ESP32S2 = 1 << 2, ///< Xtensa ESP32S2 + CS_MODE_XTENSA_ESP8266 = 1 << 3, ///< Xtensa ESP328266 } cs_mode; typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size); diff --git a/include/capstone/xtensa.h b/include/capstone/xtensa.h index affa9c58da..ee34de4a80 100644 --- a/include/capstone/xtensa.h +++ b/include/capstone/xtensa.h @@ -14,24 +14,176 @@ typedef enum xtensa_reg { // clang-format off XTENSA_REG_INVALID = 0, - XTENSA_REG_SAR = 1, - XTENSA_REG_SP = 2, - XTENSA_REG_A0 = 3, - XTENSA_REG_A2 = 4, - XTENSA_REG_A3 = 5, - XTENSA_REG_A4 = 6, - XTENSA_REG_A5 = 7, - XTENSA_REG_A6 = 8, - XTENSA_REG_A7 = 9, - XTENSA_REG_A8 = 10, - XTENSA_REG_A9 = 11, - XTENSA_REG_A10 = 12, - XTENSA_REG_A11 = 13, - XTENSA_REG_A12 = 14, - XTENSA_REG_A13 = 15, - XTENSA_REG_A14 = 16, - XTENSA_REG_A15 = 17, - XTENSA_REG_ENDING, // 18 + XTENSA_REG_ACCHI = 1, + XTENSA_REG_ACCLO = 2, + XTENSA_REG_ACCX = 3, + XTENSA_REG_ATOMCTL = 4, + XTENSA_REG_BREG = 5, + XTENSA_REG_CCOUNT = 6, + XTENSA_REG_CPENABLE = 7, + XTENSA_REG_DDR = 8, + XTENSA_REG_DEBUGCAUSE = 9, + XTENSA_REG_DEPC = 10, + XTENSA_REG_EXCCAUSE = 11, + XTENSA_REG_EXCVADDR = 12, + XTENSA_REG_EXPSTATE = 13, + XTENSA_REG_FCR = 14, + XTENSA_REG_FFT_BIT_WIDTH = 15, + XTENSA_REG_FSR = 16, + XTENSA_REG_GPIO_OUT = 17, + XTENSA_REG_IBREAKENABLE = 18, + XTENSA_REG_ICOUNT = 19, + XTENSA_REG_ICOUNTLEVEL = 20, + XTENSA_REG_INTCLEAR = 21, + XTENSA_REG_INTENABLE = 22, + XTENSA_REG_INTERRUPT = 23, + XTENSA_REG_LBEG = 24, + XTENSA_REG_LCOUNT = 25, + XTENSA_REG_LEND = 26, + XTENSA_REG_LITBASE = 27, + XTENSA_REG_MEMCTL = 28, + XTENSA_REG_PRID = 29, + XTENSA_REG_PS = 30, + XTENSA_REG_QACC = 31, + XTENSA_REG_SAR = 32, + XTENSA_REG_SAR_BYTE = 33, + XTENSA_REG_SP = 34, + XTENSA_REG_THREADPTR = 35, + XTENSA_REG_UA_STATE = 36, + XTENSA_REG_VECBASE = 37, + XTENSA_REG_WINDOWBASE = 38, + XTENSA_REG_WINDOWSTART = 39, + XTENSA_REG_A0 = 40, + XTENSA_REG_A2 = 41, + XTENSA_REG_A3 = 42, + XTENSA_REG_A4 = 43, + XTENSA_REG_A5 = 44, + XTENSA_REG_A6 = 45, + XTENSA_REG_A7 = 46, + XTENSA_REG_A8 = 47, + XTENSA_REG_A9 = 48, + XTENSA_REG_A10 = 49, + XTENSA_REG_A11 = 50, + XTENSA_REG_A12 = 51, + XTENSA_REG_A13 = 52, + XTENSA_REG_A14 = 53, + XTENSA_REG_A15 = 54, + XTENSA_REG_AED0 = 55, + XTENSA_REG_AED1 = 56, + XTENSA_REG_AED2 = 57, + XTENSA_REG_AED3 = 58, + XTENSA_REG_AED4 = 59, + XTENSA_REG_AED5 = 60, + XTENSA_REG_AED6 = 61, + XTENSA_REG_AED7 = 62, + XTENSA_REG_AED8 = 63, + XTENSA_REG_AED9 = 64, + XTENSA_REG_AED10 = 65, + XTENSA_REG_AED11 = 66, + XTENSA_REG_AED12 = 67, + XTENSA_REG_AED13 = 68, + XTENSA_REG_AED14 = 69, + XTENSA_REG_AED15 = 70, + XTENSA_REG_B0 = 71, + XTENSA_REG_B1 = 72, + XTENSA_REG_B2 = 73, + XTENSA_REG_B3 = 74, + XTENSA_REG_B4 = 75, + XTENSA_REG_B5 = 76, + XTENSA_REG_B6 = 77, + XTENSA_REG_B7 = 78, + XTENSA_REG_B8 = 79, + XTENSA_REG_B9 = 80, + XTENSA_REG_B10 = 81, + XTENSA_REG_B11 = 82, + XTENSA_REG_B12 = 83, + XTENSA_REG_B13 = 84, + XTENSA_REG_B14 = 85, + XTENSA_REG_B15 = 86, + XTENSA_REG_CCOMPARE0 = 87, + XTENSA_REG_CCOMPARE1 = 88, + XTENSA_REG_CCOMPARE2 = 89, + XTENSA_REG_CONFIGID0 = 90, + XTENSA_REG_CONFIGID1 = 91, + XTENSA_REG_DBREAKA0 = 92, + XTENSA_REG_DBREAKA1 = 93, + XTENSA_REG_DBREAKC0 = 94, + XTENSA_REG_DBREAKC1 = 95, + XTENSA_REG_EPC1 = 96, + XTENSA_REG_EPC2 = 97, + XTENSA_REG_EPC3 = 98, + XTENSA_REG_EPC4 = 99, + XTENSA_REG_EPC5 = 100, + XTENSA_REG_EPC6 = 101, + XTENSA_REG_EPC7 = 102, + XTENSA_REG_EPS2 = 103, + XTENSA_REG_EPS3 = 104, + XTENSA_REG_EPS4 = 105, + XTENSA_REG_EPS5 = 106, + XTENSA_REG_EPS6 = 107, + XTENSA_REG_EPS7 = 108, + XTENSA_REG_EXCSAVE1 = 109, + XTENSA_REG_EXCSAVE2 = 110, + XTENSA_REG_EXCSAVE3 = 111, + XTENSA_REG_EXCSAVE4 = 112, + XTENSA_REG_EXCSAVE5 = 113, + XTENSA_REG_EXCSAVE6 = 114, + XTENSA_REG_EXCSAVE7 = 115, + XTENSA_REG_F0 = 116, + XTENSA_REG_F1 = 117, + XTENSA_REG_F2 = 118, + XTENSA_REG_F3 = 119, + XTENSA_REG_F4 = 120, + XTENSA_REG_F5 = 121, + XTENSA_REG_F6 = 122, + XTENSA_REG_F7 = 123, + XTENSA_REG_F8 = 124, + XTENSA_REG_F9 = 125, + XTENSA_REG_F10 = 126, + XTENSA_REG_F11 = 127, + XTENSA_REG_F12 = 128, + XTENSA_REG_F13 = 129, + XTENSA_REG_F14 = 130, + XTENSA_REG_F15 = 131, + XTENSA_REG_IBREAKA0 = 132, + XTENSA_REG_IBREAKA1 = 133, + XTENSA_REG_M0 = 134, + XTENSA_REG_M1 = 135, + XTENSA_REG_M2 = 136, + XTENSA_REG_M3 = 137, + XTENSA_REG_MISC0 = 138, + XTENSA_REG_MISC1 = 139, + XTENSA_REG_MISC2 = 140, + XTENSA_REG_MISC3 = 141, + XTENSA_REG_Q0 = 142, + XTENSA_REG_Q1 = 143, + XTENSA_REG_Q2 = 144, + XTENSA_REG_Q3 = 145, + XTENSA_REG_Q4 = 146, + XTENSA_REG_Q5 = 147, + XTENSA_REG_Q6 = 148, + XTENSA_REG_Q7 = 149, + XTENSA_REG_SCOMPARE1 = 150, + XTENSA_REG_U0 = 151, + XTENSA_REG_U1 = 152, + XTENSA_REG_U2 = 153, + XTENSA_REG_U3 = 154, + XTENSA_REG_F64R_HI = 155, + XTENSA_REG_F64R_LO = 156, + XTENSA_REG_F64S = 157, + XTENSA_REG_B0_B1 = 158, + XTENSA_REG_B2_B3 = 159, + XTENSA_REG_B4_B5 = 160, + XTENSA_REG_B6_B7 = 161, + XTENSA_REG_B8_B9 = 162, + XTENSA_REG_B10_B11 = 163, + XTENSA_REG_B12_B13 = 164, + XTENSA_REG_B14_B15 = 165, + XTENSA_REG_B0_B1_B2_B3 = 166, + XTENSA_REG_B4_B5_B6_B7 = 167, + XTENSA_REG_B8_B9_B10_B11 = 168, + XTENSA_REG_B12_B13_B14_B15 = 169, + XTENSA_REG_ENDING, // 170 // clang-format on // generated content end @@ -44,13 +196,862 @@ typedef enum xtensa_insn { XTENSA_INS_INVALID, XTENSA_INS_ABS, + XTENSA_INS_ABS_S, XTENSA_INS_ADD, + XTENSA_INS_ADDEXPM_S, + XTENSA_INS_ADDEXP_S, XTENSA_INS_ADDI, + XTENSA_INS_ADDI_N, XTENSA_INS_ADDMI, XTENSA_INS_ADDX2, XTENSA_INS_ADDX4, XTENSA_INS_ADDX8, + XTENSA_INS_ADD_N, + XTENSA_INS_ADD_S, + XTENSA_INS_AE_ABS16S, + XTENSA_INS_AE_ABS24S, + XTENSA_INS_AE_ABS32, + XTENSA_INS_AE_ABS32S, + XTENSA_INS_AE_ABS64, + XTENSA_INS_AE_ABS64S, + XTENSA_INS_AE_ADD16, + XTENSA_INS_AE_ADD16S, + XTENSA_INS_AE_ADD24S, + XTENSA_INS_AE_ADD32, + XTENSA_INS_AE_ADD32S, + XTENSA_INS_AE_ADD32_HL_LH, + XTENSA_INS_AE_ADD64, + XTENSA_INS_AE_ADD64S, + XTENSA_INS_AE_ADDBRBA32, + XTENSA_INS_AE_ADDSUB32, + XTENSA_INS_AE_ADDSUB32S, + XTENSA_INS_AE_AND, + XTENSA_INS_AE_CVT32X2F16_10, + XTENSA_INS_AE_CVT32X2F16_32, + XTENSA_INS_AE_CVT48A32, + XTENSA_INS_AE_CVT64A32, + XTENSA_INS_AE_CVT64F32_H, + XTENSA_INS_AE_CVTA32F24S_H, + XTENSA_INS_AE_CVTA32F24S_L, + XTENSA_INS_AE_CVTQ56A32S, + XTENSA_INS_AE_CVTQ56P32S_H, + XTENSA_INS_AE_CVTQ56P32S_L, + XTENSA_INS_AE_DB, + XTENSA_INS_AE_DBI, + XTENSA_INS_AE_DBI_IC, + XTENSA_INS_AE_DBI_IP, + XTENSA_INS_AE_DB_IC, + XTENSA_INS_AE_DB_IP, + XTENSA_INS_AE_DIV64D32_H, + XTENSA_INS_AE_DIV64D32_L, + XTENSA_INS_AE_EQ16, + XTENSA_INS_AE_EQ32, + XTENSA_INS_AE_EQ64, + XTENSA_INS_AE_L16M_I, + XTENSA_INS_AE_L16M_IU, + XTENSA_INS_AE_L16M_X, + XTENSA_INS_AE_L16M_XC, + XTENSA_INS_AE_L16M_XU, + XTENSA_INS_AE_L16X2M_I, + XTENSA_INS_AE_L16X2M_IU, + XTENSA_INS_AE_L16X2M_X, + XTENSA_INS_AE_L16X2M_XC, + XTENSA_INS_AE_L16X2M_XU, + XTENSA_INS_AE_L16X4_I, + XTENSA_INS_AE_L16X4_IP, + XTENSA_INS_AE_L16X4_RIC, + XTENSA_INS_AE_L16X4_RIP, + XTENSA_INS_AE_L16X4_X, + XTENSA_INS_AE_L16X4_XC, + XTENSA_INS_AE_L16X4_XP, + XTENSA_INS_AE_L16_I, + XTENSA_INS_AE_L16_IP, + XTENSA_INS_AE_L16_X, + XTENSA_INS_AE_L16_XC, + XTENSA_INS_AE_L16_XP, + XTENSA_INS_AE_L32F24_I, + XTENSA_INS_AE_L32F24_IP, + XTENSA_INS_AE_L32F24_X, + XTENSA_INS_AE_L32F24_XC, + XTENSA_INS_AE_L32F24_XP, + XTENSA_INS_AE_L32M_I, + XTENSA_INS_AE_L32M_IU, + XTENSA_INS_AE_L32M_X, + XTENSA_INS_AE_L32M_XC, + XTENSA_INS_AE_L32M_XU, + XTENSA_INS_AE_L32X2F24_I, + XTENSA_INS_AE_L32X2F24_IP, + XTENSA_INS_AE_L32X2F24_RIC, + XTENSA_INS_AE_L32X2F24_RIP, + XTENSA_INS_AE_L32X2F24_X, + XTENSA_INS_AE_L32X2F24_XC, + XTENSA_INS_AE_L32X2F24_XP, + XTENSA_INS_AE_L32X2_I, + XTENSA_INS_AE_L32X2_IP, + XTENSA_INS_AE_L32X2_RIC, + XTENSA_INS_AE_L32X2_RIP, + XTENSA_INS_AE_L32X2_X, + XTENSA_INS_AE_L32X2_XC, + XTENSA_INS_AE_L32X2_XP, + XTENSA_INS_AE_L32_I, + XTENSA_INS_AE_L32_IP, + XTENSA_INS_AE_L32_X, + XTENSA_INS_AE_L32_XC, + XTENSA_INS_AE_L32_XP, + XTENSA_INS_AE_L64_I, + XTENSA_INS_AE_L64_IP, + XTENSA_INS_AE_L64_X, + XTENSA_INS_AE_L64_XC, + XTENSA_INS_AE_L64_XP, + XTENSA_INS_AE_LA16X4NEG_PC, + XTENSA_INS_AE_LA16X4POS_PC, + XTENSA_INS_AE_LA16X4_IC, + XTENSA_INS_AE_LA16X4_IP, + XTENSA_INS_AE_LA16X4_RIC, + XTENSA_INS_AE_LA16X4_RIP, + XTENSA_INS_AE_LA24NEG_PC, + XTENSA_INS_AE_LA24POS_PC, + XTENSA_INS_AE_LA24X2NEG_PC, + XTENSA_INS_AE_LA24X2POS_PC, + XTENSA_INS_AE_LA24X2_IC, + XTENSA_INS_AE_LA24X2_IP, + XTENSA_INS_AE_LA24X2_RIC, + XTENSA_INS_AE_LA24X2_RIP, + XTENSA_INS_AE_LA24_IC, + XTENSA_INS_AE_LA24_IP, + XTENSA_INS_AE_LA24_RIC, + XTENSA_INS_AE_LA24_RIP, + XTENSA_INS_AE_LA32X2F24_IC, + XTENSA_INS_AE_LA32X2F24_IP, + XTENSA_INS_AE_LA32X2F24_RIC, + XTENSA_INS_AE_LA32X2F24_RIP, + XTENSA_INS_AE_LA32X2NEG_PC, + XTENSA_INS_AE_LA32X2POS_PC, + XTENSA_INS_AE_LA32X2_IC, + XTENSA_INS_AE_LA32X2_IP, + XTENSA_INS_AE_LA32X2_RIC, + XTENSA_INS_AE_LA32X2_RIP, + XTENSA_INS_AE_LA64_PP, + XTENSA_INS_AE_LALIGN64_I, + XTENSA_INS_AE_LB, + XTENSA_INS_AE_LBI, + XTENSA_INS_AE_LBK, + XTENSA_INS_AE_LBKI, + XTENSA_INS_AE_LBS, + XTENSA_INS_AE_LBSI, + XTENSA_INS_AE_LE16, + XTENSA_INS_AE_LE32, + XTENSA_INS_AE_LE64, + XTENSA_INS_AE_LT16, + XTENSA_INS_AE_LT32, + XTENSA_INS_AE_LT64, + XTENSA_INS_AE_MAX32, + XTENSA_INS_AE_MAX64, + XTENSA_INS_AE_MAXABS32S, + XTENSA_INS_AE_MAXABS64S, + XTENSA_INS_AE_MIN32, + XTENSA_INS_AE_MIN64, + XTENSA_INS_AE_MINABS32S, + XTENSA_INS_AE_MINABS64S, + XTENSA_INS_AE_MOV, + XTENSA_INS_AE_MOVAD16_0, + XTENSA_INS_AE_MOVAD16_1, + XTENSA_INS_AE_MOVAD16_2, + XTENSA_INS_AE_MOVAD16_3, + XTENSA_INS_AE_MOVAD32_H, + XTENSA_INS_AE_MOVAD32_L, + XTENSA_INS_AE_MOVALIGN, + XTENSA_INS_AE_MOVDA16, + XTENSA_INS_AE_MOVDA16X2, + XTENSA_INS_AE_MOVDA32, + XTENSA_INS_AE_MOVDA32X2, + XTENSA_INS_AE_MOVF16X4, + XTENSA_INS_AE_MOVF32X2, + XTENSA_INS_AE_MOVF64, + XTENSA_INS_AE_MOVI, + XTENSA_INS_AE_MOVT16X4, + XTENSA_INS_AE_MOVT32X2, + XTENSA_INS_AE_MOVT64, + XTENSA_INS_AE_MUL16X4, + XTENSA_INS_AE_MUL32U_LL, + XTENSA_INS_AE_MUL32X16_H0, + XTENSA_INS_AE_MUL32X16_H0_S2, + XTENSA_INS_AE_MUL32X16_H1, + XTENSA_INS_AE_MUL32X16_H1_S2, + XTENSA_INS_AE_MUL32X16_H2, + XTENSA_INS_AE_MUL32X16_H2_S2, + XTENSA_INS_AE_MUL32X16_H3, + XTENSA_INS_AE_MUL32X16_H3_S2, + XTENSA_INS_AE_MUL32X16_L0, + XTENSA_INS_AE_MUL32X16_L0_S2, + XTENSA_INS_AE_MUL32X16_L1, + XTENSA_INS_AE_MUL32X16_L1_S2, + XTENSA_INS_AE_MUL32X16_L2, + XTENSA_INS_AE_MUL32X16_L2_S2, + XTENSA_INS_AE_MUL32X16_L3, + XTENSA_INS_AE_MUL32X16_L3_S2, + XTENSA_INS_AE_MUL32_HH, + XTENSA_INS_AE_MUL32_LH, + XTENSA_INS_AE_MUL32_LL, + XTENSA_INS_AE_MUL32_LL_S2, + XTENSA_INS_AE_MULA16X4, + XTENSA_INS_AE_MULA32U_LL, + XTENSA_INS_AE_MULA32X16_H0, + XTENSA_INS_AE_MULA32X16_H0_S2, + XTENSA_INS_AE_MULA32X16_H1, + XTENSA_INS_AE_MULA32X16_H1_S2, + XTENSA_INS_AE_MULA32X16_H2, + XTENSA_INS_AE_MULA32X16_H2_S2, + XTENSA_INS_AE_MULA32X16_H3, + XTENSA_INS_AE_MULA32X16_H3_S2, + XTENSA_INS_AE_MULA32X16_L0, + XTENSA_INS_AE_MULA32X16_L0_S2, + XTENSA_INS_AE_MULA32X16_L1, + XTENSA_INS_AE_MULA32X16_L1_S2, + XTENSA_INS_AE_MULA32X16_L2, + XTENSA_INS_AE_MULA32X16_L2_S2, + XTENSA_INS_AE_MULA32X16_L3, + XTENSA_INS_AE_MULA32X16_L3_S2, + XTENSA_INS_AE_MULA32_HH, + XTENSA_INS_AE_MULA32_LH, + XTENSA_INS_AE_MULA32_LL, + XTENSA_INS_AE_MULA32_LL_S2, + XTENSA_INS_AE_MULAAD24_HH_LL, + XTENSA_INS_AE_MULAAD24_HH_LL_S2, + XTENSA_INS_AE_MULAAD24_HL_LH, + XTENSA_INS_AE_MULAAD24_HL_LH_S2, + XTENSA_INS_AE_MULAAD32X16_H0_L1, + XTENSA_INS_AE_MULAAD32X16_H0_L1_S2, + XTENSA_INS_AE_MULAAD32X16_H1_L0, + XTENSA_INS_AE_MULAAD32X16_H1_L0_S2, + XTENSA_INS_AE_MULAAD32X16_H2_L3, + XTENSA_INS_AE_MULAAD32X16_H2_L3_S2, + XTENSA_INS_AE_MULAAD32X16_H3_L2, + XTENSA_INS_AE_MULAAD32X16_H3_L2_S2, + XTENSA_INS_AE_MULAAFD16SS_11_00, + XTENSA_INS_AE_MULAAFD16SS_11_00_S2, + XTENSA_INS_AE_MULAAFD16SS_13_02, + XTENSA_INS_AE_MULAAFD16SS_13_02_S2, + XTENSA_INS_AE_MULAAFD16SS_33_22, + XTENSA_INS_AE_MULAAFD16SS_33_22_S2, + XTENSA_INS_AE_MULAAFD24_HH_LL, + XTENSA_INS_AE_MULAAFD24_HH_LL_S2, + XTENSA_INS_AE_MULAAFD24_HL_LH, + XTENSA_INS_AE_MULAAFD24_HL_LH_S2, + XTENSA_INS_AE_MULAAFD32X16_H0_L1, + XTENSA_INS_AE_MULAAFD32X16_H0_L1_S2, + XTENSA_INS_AE_MULAAFD32X16_H1_L0, + XTENSA_INS_AE_MULAAFD32X16_H1_L0_S2, + XTENSA_INS_AE_MULAAFD32X16_H2_L3, + XTENSA_INS_AE_MULAAFD32X16_H2_L3_S2, + XTENSA_INS_AE_MULAAFD32X16_H3_L2, + XTENSA_INS_AE_MULAAFD32X16_H3_L2_S2, + XTENSA_INS_AE_MULAC24, + XTENSA_INS_AE_MULAC32X16_H, + XTENSA_INS_AE_MULAC32X16_L, + XTENSA_INS_AE_MULAF16SS_00, + XTENSA_INS_AE_MULAF16SS_00_S2, + XTENSA_INS_AE_MULAF16SS_10, + XTENSA_INS_AE_MULAF16SS_11, + XTENSA_INS_AE_MULAF16SS_20, + XTENSA_INS_AE_MULAF16SS_21, + XTENSA_INS_AE_MULAF16SS_22, + XTENSA_INS_AE_MULAF16SS_30, + XTENSA_INS_AE_MULAF16SS_31, + XTENSA_INS_AE_MULAF16SS_32, + XTENSA_INS_AE_MULAF16SS_33, + XTENSA_INS_AE_MULAF16X4SS, + XTENSA_INS_AE_MULAF32R_HH, + XTENSA_INS_AE_MULAF32R_LH, + XTENSA_INS_AE_MULAF32R_LL, + XTENSA_INS_AE_MULAF32R_LL_S2, + XTENSA_INS_AE_MULAF32S_HH, + XTENSA_INS_AE_MULAF32S_LH, + XTENSA_INS_AE_MULAF32S_LL, + XTENSA_INS_AE_MULAF32S_LL_S2, + XTENSA_INS_AE_MULAF32X16_H0, + XTENSA_INS_AE_MULAF32X16_H0_S2, + XTENSA_INS_AE_MULAF32X16_H1, + XTENSA_INS_AE_MULAF32X16_H1_S2, + XTENSA_INS_AE_MULAF32X16_H2, + XTENSA_INS_AE_MULAF32X16_H2_S2, + XTENSA_INS_AE_MULAF32X16_H3, + XTENSA_INS_AE_MULAF32X16_H3_S2, + XTENSA_INS_AE_MULAF32X16_L0, + XTENSA_INS_AE_MULAF32X16_L0_S2, + XTENSA_INS_AE_MULAF32X16_L1, + XTENSA_INS_AE_MULAF32X16_L1_S2, + XTENSA_INS_AE_MULAF32X16_L2, + XTENSA_INS_AE_MULAF32X16_L2_S2, + XTENSA_INS_AE_MULAF32X16_L3, + XTENSA_INS_AE_MULAF32X16_L3_S2, + XTENSA_INS_AE_MULAF48Q32SP16S_L, + XTENSA_INS_AE_MULAF48Q32SP16S_L_S2, + XTENSA_INS_AE_MULAF48Q32SP16U_L, + XTENSA_INS_AE_MULAF48Q32SP16U_L_S2, + XTENSA_INS_AE_MULAFC24RA, + XTENSA_INS_AE_MULAFC32X16RAS_H, + XTENSA_INS_AE_MULAFC32X16RAS_L, + XTENSA_INS_AE_MULAFD24X2_FIR_H, + XTENSA_INS_AE_MULAFD24X2_FIR_L, + XTENSA_INS_AE_MULAFD32X16X2_FIR_HH, + XTENSA_INS_AE_MULAFD32X16X2_FIR_HL, + XTENSA_INS_AE_MULAFD32X16X2_FIR_LH, + XTENSA_INS_AE_MULAFD32X16X2_FIR_LL, + XTENSA_INS_AE_MULAFP24X2R, + XTENSA_INS_AE_MULAFP24X2RA, + XTENSA_INS_AE_MULAFP24X2RA_S2, + XTENSA_INS_AE_MULAFP24X2R_S2, + XTENSA_INS_AE_MULAFP32X16X2RAS_H, + XTENSA_INS_AE_MULAFP32X16X2RAS_H_S2, + XTENSA_INS_AE_MULAFP32X16X2RAS_L, + XTENSA_INS_AE_MULAFP32X16X2RAS_L_S2, + XTENSA_INS_AE_MULAFP32X16X2RS_H, + XTENSA_INS_AE_MULAFP32X16X2RS_H_S2, + XTENSA_INS_AE_MULAFP32X16X2RS_L, + XTENSA_INS_AE_MULAFP32X16X2RS_L_S2, + XTENSA_INS_AE_MULAFP32X2RAS, + XTENSA_INS_AE_MULAFP32X2RS, + XTENSA_INS_AE_MULAFQ32SP24S_H_S2, + XTENSA_INS_AE_MULAFQ32SP24S_L_S2, + XTENSA_INS_AE_MULAP24X2, + XTENSA_INS_AE_MULAP24X2_S2, + XTENSA_INS_AE_MULAP32X16X2_H, + XTENSA_INS_AE_MULAP32X16X2_L, + XTENSA_INS_AE_MULAP32X2, + XTENSA_INS_AE_MULAQ32SP16S_L_S2, + XTENSA_INS_AE_MULAQ32SP16U_L_S2, + XTENSA_INS_AE_MULARFQ32SP24S_H_S2, + XTENSA_INS_AE_MULARFQ32SP24S_L_S2, + XTENSA_INS_AE_MULAS32F48P16S_HH, + XTENSA_INS_AE_MULAS32F48P16S_HH_S2, + XTENSA_INS_AE_MULAS32F48P16S_LH, + XTENSA_INS_AE_MULAS32F48P16S_LH_S2, + XTENSA_INS_AE_MULAS32F48P16S_LL, + XTENSA_INS_AE_MULAS32F48P16S_LL_S2, + XTENSA_INS_AE_MULASD24_HH_LL, + XTENSA_INS_AE_MULASD24_HH_LL_S2, + XTENSA_INS_AE_MULASD24_HL_LH, + XTENSA_INS_AE_MULASD24_HL_LH_S2, + XTENSA_INS_AE_MULASD32X16_H1_L0, + XTENSA_INS_AE_MULASD32X16_H1_L0_S2, + XTENSA_INS_AE_MULASD32X16_H3_L2, + XTENSA_INS_AE_MULASD32X16_H3_L2_S2, + XTENSA_INS_AE_MULASFD24_HH_LL, + XTENSA_INS_AE_MULASFD24_HH_LL_S2, + XTENSA_INS_AE_MULASFD24_HL_LH, + XTENSA_INS_AE_MULASFD24_HL_LH_S2, + XTENSA_INS_AE_MULASFD32X16_H1_L0, + XTENSA_INS_AE_MULASFD32X16_H1_L0_S2, + XTENSA_INS_AE_MULASFD32X16_H3_L2, + XTENSA_INS_AE_MULASFD32X16_H3_L2_S2, + XTENSA_INS_AE_MULC24, + XTENSA_INS_AE_MULC32X16_H, + XTENSA_INS_AE_MULC32X16_L, + XTENSA_INS_AE_MULF16SS_00, + XTENSA_INS_AE_MULF16SS_00_S2, + XTENSA_INS_AE_MULF16SS_10, + XTENSA_INS_AE_MULF16SS_11, + XTENSA_INS_AE_MULF16SS_20, + XTENSA_INS_AE_MULF16SS_21, + XTENSA_INS_AE_MULF16SS_22, + XTENSA_INS_AE_MULF16SS_30, + XTENSA_INS_AE_MULF16SS_31, + XTENSA_INS_AE_MULF16SS_32, + XTENSA_INS_AE_MULF16SS_33, + XTENSA_INS_AE_MULF16X4SS, + XTENSA_INS_AE_MULF32R_HH, + XTENSA_INS_AE_MULF32R_LH, + XTENSA_INS_AE_MULF32R_LL, + XTENSA_INS_AE_MULF32R_LL_S2, + XTENSA_INS_AE_MULF32S_HH, + XTENSA_INS_AE_MULF32S_LH, + XTENSA_INS_AE_MULF32S_LL, + XTENSA_INS_AE_MULF32S_LL_S2, + XTENSA_INS_AE_MULF32X16_H0, + XTENSA_INS_AE_MULF32X16_H0_S2, + XTENSA_INS_AE_MULF32X16_H1, + XTENSA_INS_AE_MULF32X16_H1_S2, + XTENSA_INS_AE_MULF32X16_H2, + XTENSA_INS_AE_MULF32X16_H2_S2, + XTENSA_INS_AE_MULF32X16_H3, + XTENSA_INS_AE_MULF32X16_H3_S2, + XTENSA_INS_AE_MULF32X16_L0, + XTENSA_INS_AE_MULF32X16_L0_S2, + XTENSA_INS_AE_MULF32X16_L1, + XTENSA_INS_AE_MULF32X16_L1_S2, + XTENSA_INS_AE_MULF32X16_L2, + XTENSA_INS_AE_MULF32X16_L2_S2, + XTENSA_INS_AE_MULF32X16_L3, + XTENSA_INS_AE_MULF32X16_L3_S2, + XTENSA_INS_AE_MULF48Q32SP16S_L, + XTENSA_INS_AE_MULF48Q32SP16S_L_S2, + XTENSA_INS_AE_MULF48Q32SP16U_L, + XTENSA_INS_AE_MULF48Q32SP16U_L_S2, + XTENSA_INS_AE_MULFC24RA, + XTENSA_INS_AE_MULFC32X16RAS_H, + XTENSA_INS_AE_MULFC32X16RAS_L, + XTENSA_INS_AE_MULFD24X2_FIR_H, + XTENSA_INS_AE_MULFD24X2_FIR_L, + XTENSA_INS_AE_MULFD32X16X2_FIR_HH, + XTENSA_INS_AE_MULFD32X16X2_FIR_HL, + XTENSA_INS_AE_MULFD32X16X2_FIR_LH, + XTENSA_INS_AE_MULFD32X16X2_FIR_LL, + XTENSA_INS_AE_MULFP16X4RAS, + XTENSA_INS_AE_MULFP16X4S, + XTENSA_INS_AE_MULFP24X2R, + XTENSA_INS_AE_MULFP24X2RA, + XTENSA_INS_AE_MULFP24X2RA_S2, + XTENSA_INS_AE_MULFP24X2R_S2, + XTENSA_INS_AE_MULFP32X16X2RAS_H, + XTENSA_INS_AE_MULFP32X16X2RAS_H_S2, + XTENSA_INS_AE_MULFP32X16X2RAS_L, + XTENSA_INS_AE_MULFP32X16X2RAS_L_S2, + XTENSA_INS_AE_MULFP32X16X2RS_H, + XTENSA_INS_AE_MULFP32X16X2RS_H_S2, + XTENSA_INS_AE_MULFP32X16X2RS_L, + XTENSA_INS_AE_MULFP32X16X2RS_L_S2, + XTENSA_INS_AE_MULFP32X2RAS, + XTENSA_INS_AE_MULFP32X2RS, + XTENSA_INS_AE_MULFQ32SP24S_H_S2, + XTENSA_INS_AE_MULFQ32SP24S_L_S2, + XTENSA_INS_AE_MULP24X2, + XTENSA_INS_AE_MULP24X2_S2, + XTENSA_INS_AE_MULP32X16X2_H, + XTENSA_INS_AE_MULP32X16X2_L, + XTENSA_INS_AE_MULP32X2, + XTENSA_INS_AE_MULQ32SP16S_L_S2, + XTENSA_INS_AE_MULQ32SP16U_L_S2, + XTENSA_INS_AE_MULRFQ32SP24S_H_S2, + XTENSA_INS_AE_MULRFQ32SP24S_L_S2, + XTENSA_INS_AE_MULS16X4, + XTENSA_INS_AE_MULS32F48P16S_HH, + XTENSA_INS_AE_MULS32F48P16S_HH_S2, + XTENSA_INS_AE_MULS32F48P16S_LH, + XTENSA_INS_AE_MULS32F48P16S_LH_S2, + XTENSA_INS_AE_MULS32F48P16S_LL, + XTENSA_INS_AE_MULS32F48P16S_LL_S2, + XTENSA_INS_AE_MULS32U_LL, + XTENSA_INS_AE_MULS32X16_H0, + XTENSA_INS_AE_MULS32X16_H0_S2, + XTENSA_INS_AE_MULS32X16_H1, + XTENSA_INS_AE_MULS32X16_H1_S2, + XTENSA_INS_AE_MULS32X16_H2, + XTENSA_INS_AE_MULS32X16_H2_S2, + XTENSA_INS_AE_MULS32X16_H3, + XTENSA_INS_AE_MULS32X16_H3_S2, + XTENSA_INS_AE_MULS32X16_L0, + XTENSA_INS_AE_MULS32X16_L0_S2, + XTENSA_INS_AE_MULS32X16_L1, + XTENSA_INS_AE_MULS32X16_L1_S2, + XTENSA_INS_AE_MULS32X16_L2, + XTENSA_INS_AE_MULS32X16_L2_S2, + XTENSA_INS_AE_MULS32X16_L3, + XTENSA_INS_AE_MULS32X16_L3_S2, + XTENSA_INS_AE_MULS32_HH, + XTENSA_INS_AE_MULS32_LH, + XTENSA_INS_AE_MULS32_LL, + XTENSA_INS_AE_MULSAD24_HH_LL, + XTENSA_INS_AE_MULSAD24_HH_LL_S2, + XTENSA_INS_AE_MULSAD32X16_H1_L0, + XTENSA_INS_AE_MULSAD32X16_H1_L0_S2, + XTENSA_INS_AE_MULSAD32X16_H3_L2, + XTENSA_INS_AE_MULSAD32X16_H3_L2_S2, + XTENSA_INS_AE_MULSAFD24_HH_LL, + XTENSA_INS_AE_MULSAFD24_HH_LL_S2, + XTENSA_INS_AE_MULSAFD32X16_H1_L0, + XTENSA_INS_AE_MULSAFD32X16_H1_L0_S2, + XTENSA_INS_AE_MULSAFD32X16_H3_L2, + XTENSA_INS_AE_MULSAFD32X16_H3_L2_S2, + XTENSA_INS_AE_MULSF16SS_00, + XTENSA_INS_AE_MULSF16SS_00_S2, + XTENSA_INS_AE_MULSF16SS_10, + XTENSA_INS_AE_MULSF16SS_11, + XTENSA_INS_AE_MULSF16SS_20, + XTENSA_INS_AE_MULSF16SS_21, + XTENSA_INS_AE_MULSF16SS_22, + XTENSA_INS_AE_MULSF16SS_30, + XTENSA_INS_AE_MULSF16SS_31, + XTENSA_INS_AE_MULSF16SS_32, + XTENSA_INS_AE_MULSF16SS_33, + XTENSA_INS_AE_MULSF16X4SS, + XTENSA_INS_AE_MULSF32R_HH, + XTENSA_INS_AE_MULSF32R_LH, + XTENSA_INS_AE_MULSF32R_LL, + XTENSA_INS_AE_MULSF32R_LL_S2, + XTENSA_INS_AE_MULSF32S_HH, + XTENSA_INS_AE_MULSF32S_LH, + XTENSA_INS_AE_MULSF32S_LL, + XTENSA_INS_AE_MULSF32X16_H0, + XTENSA_INS_AE_MULSF32X16_H0_S2, + XTENSA_INS_AE_MULSF32X16_H1, + XTENSA_INS_AE_MULSF32X16_H1_S2, + XTENSA_INS_AE_MULSF32X16_H2, + XTENSA_INS_AE_MULSF32X16_H2_S2, + XTENSA_INS_AE_MULSF32X16_H3, + XTENSA_INS_AE_MULSF32X16_H3_S2, + XTENSA_INS_AE_MULSF32X16_L0, + XTENSA_INS_AE_MULSF32X16_L0_S2, + XTENSA_INS_AE_MULSF32X16_L1, + XTENSA_INS_AE_MULSF32X16_L1_S2, + XTENSA_INS_AE_MULSF32X16_L2, + XTENSA_INS_AE_MULSF32X16_L2_S2, + XTENSA_INS_AE_MULSF32X16_L3, + XTENSA_INS_AE_MULSF32X16_L3_S2, + XTENSA_INS_AE_MULSF48Q32SP16S_L, + XTENSA_INS_AE_MULSF48Q32SP16S_L_S2, + XTENSA_INS_AE_MULSF48Q32SP16U_L, + XTENSA_INS_AE_MULSF48Q32SP16U_L_S2, + XTENSA_INS_AE_MULSFP24X2R, + XTENSA_INS_AE_MULSFP24X2RA, + XTENSA_INS_AE_MULSFP24X2RA_S2, + XTENSA_INS_AE_MULSFP24X2R_S2, + XTENSA_INS_AE_MULSFP32X16X2RAS_H, + XTENSA_INS_AE_MULSFP32X16X2RAS_H_S2, + XTENSA_INS_AE_MULSFP32X16X2RAS_L, + XTENSA_INS_AE_MULSFP32X16X2RAS_L_S2, + XTENSA_INS_AE_MULSFP32X16X2RS_H, + XTENSA_INS_AE_MULSFP32X16X2RS_H_S2, + XTENSA_INS_AE_MULSFP32X16X2RS_L, + XTENSA_INS_AE_MULSFP32X16X2RS_L_S2, + XTENSA_INS_AE_MULSFP32X2RAS, + XTENSA_INS_AE_MULSFP32X2RS, + XTENSA_INS_AE_MULSFQ32SP24S_H_S2, + XTENSA_INS_AE_MULSFQ32SP24S_L_S2, + XTENSA_INS_AE_MULSP24X2, + XTENSA_INS_AE_MULSP24X2_S2, + XTENSA_INS_AE_MULSP32X16X2_H, + XTENSA_INS_AE_MULSP32X16X2_L, + XTENSA_INS_AE_MULSP32X2, + XTENSA_INS_AE_MULSQ32SP16S_L_S2, + XTENSA_INS_AE_MULSQ32SP16U_L_S2, + XTENSA_INS_AE_MULSRFQ32SP24S_H_S2, + XTENSA_INS_AE_MULSRFQ32SP24S_L_S2, + XTENSA_INS_AE_MULSS32F48P16S_HH, + XTENSA_INS_AE_MULSS32F48P16S_HH_S2, + XTENSA_INS_AE_MULSS32F48P16S_LH, + XTENSA_INS_AE_MULSS32F48P16S_LH_S2, + XTENSA_INS_AE_MULSS32F48P16S_LL, + XTENSA_INS_AE_MULSS32F48P16S_LL_S2, + XTENSA_INS_AE_MULSSD24_HH_LL, + XTENSA_INS_AE_MULSSD24_HH_LL_S2, + XTENSA_INS_AE_MULSSD24_HL_LH, + XTENSA_INS_AE_MULSSD24_HL_LH_S2, + XTENSA_INS_AE_MULSSD32X16_H1_L0, + XTENSA_INS_AE_MULSSD32X16_H1_L0_S2, + XTENSA_INS_AE_MULSSD32X16_H3_L2, + XTENSA_INS_AE_MULSSD32X16_H3_L2_S2, + XTENSA_INS_AE_MULSSFD16SS_11_00, + XTENSA_INS_AE_MULSSFD16SS_11_00_S2, + XTENSA_INS_AE_MULSSFD16SS_13_02, + XTENSA_INS_AE_MULSSFD16SS_13_02_S2, + XTENSA_INS_AE_MULSSFD16SS_33_22, + XTENSA_INS_AE_MULSSFD16SS_33_22_S2, + XTENSA_INS_AE_MULSSFD24_HH_LL, + XTENSA_INS_AE_MULSSFD24_HH_LL_S2, + XTENSA_INS_AE_MULSSFD24_HL_LH, + XTENSA_INS_AE_MULSSFD24_HL_LH_S2, + XTENSA_INS_AE_MULSSFD32X16_H1_L0, + XTENSA_INS_AE_MULSSFD32X16_H1_L0_S2, + XTENSA_INS_AE_MULSSFD32X16_H3_L2, + XTENSA_INS_AE_MULSSFD32X16_H3_L2_S2, + XTENSA_INS_AE_MULZAAD24_HH_LL, + XTENSA_INS_AE_MULZAAD24_HH_LL_S2, + XTENSA_INS_AE_MULZAAD24_HL_LH, + XTENSA_INS_AE_MULZAAD24_HL_LH_S2, + XTENSA_INS_AE_MULZAAD32X16_H0_L1, + XTENSA_INS_AE_MULZAAD32X16_H0_L1_S2, + XTENSA_INS_AE_MULZAAD32X16_H1_L0, + XTENSA_INS_AE_MULZAAD32X16_H1_L0_S2, + XTENSA_INS_AE_MULZAAD32X16_H2_L3, + XTENSA_INS_AE_MULZAAD32X16_H2_L3_S2, + XTENSA_INS_AE_MULZAAD32X16_H3_L2, + XTENSA_INS_AE_MULZAAD32X16_H3_L2_S2, + XTENSA_INS_AE_MULZAAFD16SS_11_00, + XTENSA_INS_AE_MULZAAFD16SS_11_00_S2, + XTENSA_INS_AE_MULZAAFD16SS_13_02, + XTENSA_INS_AE_MULZAAFD16SS_13_02_S2, + XTENSA_INS_AE_MULZAAFD16SS_33_22, + XTENSA_INS_AE_MULZAAFD16SS_33_22_S2, + XTENSA_INS_AE_MULZAAFD24_HH_LL, + XTENSA_INS_AE_MULZAAFD24_HH_LL_S2, + XTENSA_INS_AE_MULZAAFD24_HL_LH, + XTENSA_INS_AE_MULZAAFD24_HL_LH_S2, + XTENSA_INS_AE_MULZAAFD32X16_H0_L1, + XTENSA_INS_AE_MULZAAFD32X16_H0_L1_S2, + XTENSA_INS_AE_MULZAAFD32X16_H1_L0, + XTENSA_INS_AE_MULZAAFD32X16_H1_L0_S2, + XTENSA_INS_AE_MULZAAFD32X16_H2_L3, + XTENSA_INS_AE_MULZAAFD32X16_H2_L3_S2, + XTENSA_INS_AE_MULZAAFD32X16_H3_L2, + XTENSA_INS_AE_MULZAAFD32X16_H3_L2_S2, + XTENSA_INS_AE_MULZASD24_HH_LL, + XTENSA_INS_AE_MULZASD24_HH_LL_S2, + XTENSA_INS_AE_MULZASD24_HL_LH, + XTENSA_INS_AE_MULZASD24_HL_LH_S2, + XTENSA_INS_AE_MULZASD32X16_H1_L0, + XTENSA_INS_AE_MULZASD32X16_H1_L0_S2, + XTENSA_INS_AE_MULZASD32X16_H3_L2, + XTENSA_INS_AE_MULZASD32X16_H3_L2_S2, + XTENSA_INS_AE_MULZASFD24_HH_LL, + XTENSA_INS_AE_MULZASFD24_HH_LL_S2, + XTENSA_INS_AE_MULZASFD24_HL_LH, + XTENSA_INS_AE_MULZASFD24_HL_LH_S2, + XTENSA_INS_AE_MULZASFD32X16_H1_L0, + XTENSA_INS_AE_MULZASFD32X16_H1_L0_S2, + XTENSA_INS_AE_MULZASFD32X16_H3_L2, + XTENSA_INS_AE_MULZASFD32X16_H3_L2_S2, + XTENSA_INS_AE_MULZSAD24_HH_LL, + XTENSA_INS_AE_MULZSAD24_HH_LL_S2, + XTENSA_INS_AE_MULZSAD32X16_H1_L0, + XTENSA_INS_AE_MULZSAD32X16_H1_L0_S2, + XTENSA_INS_AE_MULZSAD32X16_H3_L2, + XTENSA_INS_AE_MULZSAD32X16_H3_L2_S2, + XTENSA_INS_AE_MULZSAFD24_HH_LL, + XTENSA_INS_AE_MULZSAFD24_HH_LL_S2, + XTENSA_INS_AE_MULZSAFD32X16_H1_L0, + XTENSA_INS_AE_MULZSAFD32X16_H1_L0_S2, + XTENSA_INS_AE_MULZSAFD32X16_H3_L2, + XTENSA_INS_AE_MULZSAFD32X16_H3_L2_S2, + XTENSA_INS_AE_MULZSSD24_HH_LL, + XTENSA_INS_AE_MULZSSD24_HH_LL_S2, + XTENSA_INS_AE_MULZSSD24_HL_LH, + XTENSA_INS_AE_MULZSSD24_HL_LH_S2, + XTENSA_INS_AE_MULZSSD32X16_H1_L0, + XTENSA_INS_AE_MULZSSD32X16_H1_L0_S2, + XTENSA_INS_AE_MULZSSD32X16_H3_L2, + XTENSA_INS_AE_MULZSSD32X16_H3_L2_S2, + XTENSA_INS_AE_MULZSSFD16SS_11_00, + XTENSA_INS_AE_MULZSSFD16SS_11_00_S2, + XTENSA_INS_AE_MULZSSFD16SS_13_02, + XTENSA_INS_AE_MULZSSFD16SS_13_02_S2, + XTENSA_INS_AE_MULZSSFD16SS_33_22, + XTENSA_INS_AE_MULZSSFD16SS_33_22_S2, + XTENSA_INS_AE_MULZSSFD24_HH_LL, + XTENSA_INS_AE_MULZSSFD24_HH_LL_S2, + XTENSA_INS_AE_MULZSSFD24_HL_LH, + XTENSA_INS_AE_MULZSSFD24_HL_LH_S2, + XTENSA_INS_AE_MULZSSFD32X16_H1_L0, + XTENSA_INS_AE_MULZSSFD32X16_H1_L0_S2, + XTENSA_INS_AE_MULZSSFD32X16_H3_L2, + XTENSA_INS_AE_MULZSSFD32X16_H3_L2_S2, + XTENSA_INS_AE_NAND, + XTENSA_INS_AE_NEG16S, + XTENSA_INS_AE_NEG24S, + XTENSA_INS_AE_NEG32, + XTENSA_INS_AE_NEG32S, + XTENSA_INS_AE_NEG64, + XTENSA_INS_AE_NEG64S, + XTENSA_INS_AE_NSA64, + XTENSA_INS_AE_NSAZ16_0, + XTENSA_INS_AE_NSAZ32_L, + XTENSA_INS_AE_OR, + XTENSA_INS_AE_PKSR24, + XTENSA_INS_AE_PKSR32, + XTENSA_INS_AE_ROUND16X4F32SASYM, + XTENSA_INS_AE_ROUND16X4F32SSYM, + XTENSA_INS_AE_ROUND24X2F48SASYM, + XTENSA_INS_AE_ROUND24X2F48SSYM, + XTENSA_INS_AE_ROUND32X2F48SASYM, + XTENSA_INS_AE_ROUND32X2F48SSYM, + XTENSA_INS_AE_ROUND32X2F64SASYM, + XTENSA_INS_AE_ROUND32X2F64SSYM, + XTENSA_INS_AE_ROUNDSP16F24ASYM, + XTENSA_INS_AE_ROUNDSP16F24SYM, + XTENSA_INS_AE_ROUNDSP16Q48X2ASYM, + XTENSA_INS_AE_ROUNDSP16Q48X2SYM, + XTENSA_INS_AE_ROUNDSQ32F48ASYM, + XTENSA_INS_AE_ROUNDSQ32F48SYM, + XTENSA_INS_AE_S16M_L_I, + XTENSA_INS_AE_S16M_L_IU, + XTENSA_INS_AE_S16M_L_X, + XTENSA_INS_AE_S16M_L_XC, + XTENSA_INS_AE_S16M_L_XU, + XTENSA_INS_AE_S16X2M_I, + XTENSA_INS_AE_S16X2M_IU, + XTENSA_INS_AE_S16X2M_X, + XTENSA_INS_AE_S16X2M_XC, + XTENSA_INS_AE_S16X2M_XU, + XTENSA_INS_AE_S16X4_I, + XTENSA_INS_AE_S16X4_IP, + XTENSA_INS_AE_S16X4_RIC, + XTENSA_INS_AE_S16X4_RIP, + XTENSA_INS_AE_S16X4_X, + XTENSA_INS_AE_S16X4_XC, + XTENSA_INS_AE_S16X4_XP, + XTENSA_INS_AE_S16_0_I, + XTENSA_INS_AE_S16_0_IP, + XTENSA_INS_AE_S16_0_X, + XTENSA_INS_AE_S16_0_XC, + XTENSA_INS_AE_S16_0_XP, + XTENSA_INS_AE_S24RA64S_I, + XTENSA_INS_AE_S24RA64S_IP, + XTENSA_INS_AE_S24RA64S_X, + XTENSA_INS_AE_S24RA64S_XC, + XTENSA_INS_AE_S24RA64S_XP, + XTENSA_INS_AE_S24X2RA64S_IP, + XTENSA_INS_AE_S32F24_L_I, + XTENSA_INS_AE_S32F24_L_IP, + XTENSA_INS_AE_S32F24_L_X, + XTENSA_INS_AE_S32F24_L_XC, + XTENSA_INS_AE_S32F24_L_XP, + XTENSA_INS_AE_S32M_I, + XTENSA_INS_AE_S32M_IU, + XTENSA_INS_AE_S32M_X, + XTENSA_INS_AE_S32M_XC, + XTENSA_INS_AE_S32M_XU, + XTENSA_INS_AE_S32RA64S_I, + XTENSA_INS_AE_S32RA64S_IP, + XTENSA_INS_AE_S32RA64S_X, + XTENSA_INS_AE_S32RA64S_XC, + XTENSA_INS_AE_S32RA64S_XP, + XTENSA_INS_AE_S32X2F24_I, + XTENSA_INS_AE_S32X2F24_IP, + XTENSA_INS_AE_S32X2F24_RIC, + XTENSA_INS_AE_S32X2F24_RIP, + XTENSA_INS_AE_S32X2F24_X, + XTENSA_INS_AE_S32X2F24_XC, + XTENSA_INS_AE_S32X2F24_XP, + XTENSA_INS_AE_S32X2RA64S_IP, + XTENSA_INS_AE_S32X2_I, + XTENSA_INS_AE_S32X2_IP, + XTENSA_INS_AE_S32X2_RIC, + XTENSA_INS_AE_S32X2_RIP, + XTENSA_INS_AE_S32X2_X, + XTENSA_INS_AE_S32X2_XC, + XTENSA_INS_AE_S32X2_XP, + XTENSA_INS_AE_S32_L_I, + XTENSA_INS_AE_S32_L_IP, + XTENSA_INS_AE_S32_L_X, + XTENSA_INS_AE_S32_L_XC, + XTENSA_INS_AE_S32_L_XP, + XTENSA_INS_AE_S64_I, + XTENSA_INS_AE_S64_IP, + XTENSA_INS_AE_S64_X, + XTENSA_INS_AE_S64_XC, + XTENSA_INS_AE_S64_XP, + XTENSA_INS_AE_SA16X4_IC, + XTENSA_INS_AE_SA16X4_IP, + XTENSA_INS_AE_SA16X4_RIC, + XTENSA_INS_AE_SA16X4_RIP, + XTENSA_INS_AE_SA24X2_IC, + XTENSA_INS_AE_SA24X2_IP, + XTENSA_INS_AE_SA24X2_RIC, + XTENSA_INS_AE_SA24X2_RIP, + XTENSA_INS_AE_SA24_L_IC, + XTENSA_INS_AE_SA24_L_IP, + XTENSA_INS_AE_SA24_L_RIC, + XTENSA_INS_AE_SA24_L_RIP, + XTENSA_INS_AE_SA32X2F24_IC, + XTENSA_INS_AE_SA32X2F24_IP, + XTENSA_INS_AE_SA32X2F24_RIC, + XTENSA_INS_AE_SA32X2F24_RIP, + XTENSA_INS_AE_SA32X2_IC, + XTENSA_INS_AE_SA32X2_IP, + XTENSA_INS_AE_SA32X2_RIC, + XTENSA_INS_AE_SA32X2_RIP, + XTENSA_INS_AE_SA64NEG_FP, + XTENSA_INS_AE_SA64POS_FP, + XTENSA_INS_AE_SALIGN64_I, + XTENSA_INS_AE_SAT16X4, + XTENSA_INS_AE_SAT24S, + XTENSA_INS_AE_SAT48S, + XTENSA_INS_AE_SATQ56S, + XTENSA_INS_AE_SB, + XTENSA_INS_AE_SBF, + XTENSA_INS_AE_SBF_IC, + XTENSA_INS_AE_SBF_IP, + XTENSA_INS_AE_SBI, + XTENSA_INS_AE_SBI_IC, + XTENSA_INS_AE_SBI_IP, + XTENSA_INS_AE_SB_IC, + XTENSA_INS_AE_SB_IP, + XTENSA_INS_AE_SEL16I, + XTENSA_INS_AE_SEL16I_N, + XTENSA_INS_AE_SEXT32, + XTENSA_INS_AE_SEXT32X2D16_10, + XTENSA_INS_AE_SEXT32X2D16_32, + XTENSA_INS_AE_SHA32, + XTENSA_INS_AE_SHORTSWAP, + XTENSA_INS_AE_SLAA16S, + XTENSA_INS_AE_SLAA32, + XTENSA_INS_AE_SLAA32S, + XTENSA_INS_AE_SLAA64, + XTENSA_INS_AE_SLAA64S, + XTENSA_INS_AE_SLAAQ56, + XTENSA_INS_AE_SLAI16S, + XTENSA_INS_AE_SLAI24, + XTENSA_INS_AE_SLAI24S, + XTENSA_INS_AE_SLAI32, + XTENSA_INS_AE_SLAI32S, + XTENSA_INS_AE_SLAI64, + XTENSA_INS_AE_SLAI64S, + XTENSA_INS_AE_SLAISQ56S, + XTENSA_INS_AE_SLAS24, + XTENSA_INS_AE_SLAS24S, + XTENSA_INS_AE_SLAS32, + XTENSA_INS_AE_SLAS32S, + XTENSA_INS_AE_SLAS64, + XTENSA_INS_AE_SLAS64S, + XTENSA_INS_AE_SLASQ56, + XTENSA_INS_AE_SLASSQ56S, + XTENSA_INS_AE_SRA64_32, + XTENSA_INS_AE_SRAA16RS, + XTENSA_INS_AE_SRAA16S, + XTENSA_INS_AE_SRAA32, + XTENSA_INS_AE_SRAA32RS, + XTENSA_INS_AE_SRAA32S, + XTENSA_INS_AE_SRAA64, + XTENSA_INS_AE_SRAI16, + XTENSA_INS_AE_SRAI16R, + XTENSA_INS_AE_SRAI24, + XTENSA_INS_AE_SRAI32, + XTENSA_INS_AE_SRAI32R, + XTENSA_INS_AE_SRAI64, + XTENSA_INS_AE_SRAS24, + XTENSA_INS_AE_SRAS32, + XTENSA_INS_AE_SRAS64, + XTENSA_INS_AE_SRLA32, + XTENSA_INS_AE_SRLA64, + XTENSA_INS_AE_SRLI24, + XTENSA_INS_AE_SRLI32, + XTENSA_INS_AE_SRLI64, + XTENSA_INS_AE_SRLS24, + XTENSA_INS_AE_SRLS32, + XTENSA_INS_AE_SRLS64, + XTENSA_INS_AE_SUB16, + XTENSA_INS_AE_SUB16S, + XTENSA_INS_AE_SUB24S, + XTENSA_INS_AE_SUB32, + XTENSA_INS_AE_SUB32S, + XTENSA_INS_AE_SUB64, + XTENSA_INS_AE_SUB64S, + XTENSA_INS_AE_SUBADD32, + XTENSA_INS_AE_SUBADD32S, + XTENSA_INS_AE_TRUNCA32F64S_L, + XTENSA_INS_AE_TRUNCA32X2F64S, + XTENSA_INS_AE_TRUNCI32F64S_L, + XTENSA_INS_AE_TRUNCI32X2F64S, + XTENSA_INS_AE_VLDL16C, + XTENSA_INS_AE_VLDL16C_IC, + XTENSA_INS_AE_VLDL16C_IP, + XTENSA_INS_AE_VLDL16T, + XTENSA_INS_AE_VLDL32T, + XTENSA_INS_AE_VLDSHT, + XTENSA_INS_AE_VLEL16T, + XTENSA_INS_AE_VLEL32T, + XTENSA_INS_AE_VLES16C, + XTENSA_INS_AE_VLES16C_IC, + XTENSA_INS_AE_VLES16C_IP, + XTENSA_INS_AE_XOR, + XTENSA_INS_AE_ZALIGN64, + XTENSA_INS_ALL4, + XTENSA_INS_ALL8, XTENSA_INS_AND, + XTENSA_INS_ANDB, + XTENSA_INS_ANDBC, + XTENSA_INS_ANY4, + XTENSA_INS_ANY8, XTENSA_INS_BALL, XTENSA_INS_BANY, XTENSA_INS_BBC, @@ -60,6 +1061,7 @@ typedef enum xtensa_insn { XTENSA_INS_BEQ, XTENSA_INS_BEQI, XTENSA_INS_BEQZ, + XTENSA_INS_BF, XTENSA_INS_BGE, XTENSA_INS_BGEI, XTENSA_INS_BGEU, @@ -75,37 +1077,448 @@ typedef enum xtensa_insn { XTENSA_INS_BNEI, XTENSA_INS_BNEZ, XTENSA_INS_BNONE, + XTENSA_INS_BREAK, + XTENSA_INS_BREAK_N, + XTENSA_INS_BT, XTENSA_INS_CALL0, + XTENSA_INS_CALL12, + XTENSA_INS_CALL4, + XTENSA_INS_CALL8, XTENSA_INS_CALLX0, + XTENSA_INS_CALLX12, + XTENSA_INS_CALLX4, + XTENSA_INS_CALLX8, + XTENSA_INS_CEIL_S, + XTENSA_INS_CLAMPS, + XTENSA_INS_CLR_BIT_GPIO_OUT, + XTENSA_INS_CONST_S, + XTENSA_INS_DIV0_S, + XTENSA_INS_DIVN_S, XTENSA_INS_DSYNC, + XTENSA_INS_EE_ANDQ, + XTENSA_INS_EE_BITREV, + XTENSA_INS_EE_CLR_BIT_GPIO_OUT, + XTENSA_INS_EE_CMUL_S16, + XTENSA_INS_EE_CMUL_S16_LD_INCP, + XTENSA_INS_EE_CMUL_S16_ST_INCP, + XTENSA_INS_EE_FFT_AMS_S16_LD_INCP, + XTENSA_INS_EE_FFT_AMS_S16_LD_INCP_UAUP, + XTENSA_INS_EE_FFT_AMS_S16_LD_R32_DECP, + XTENSA_INS_EE_FFT_AMS_S16_ST_INCP, + XTENSA_INS_EE_FFT_CMUL_S16_LD_XP, + XTENSA_INS_EE_FFT_CMUL_S16_ST_XP, + XTENSA_INS_EE_FFT_R2BF_S16, + XTENSA_INS_EE_FFT_R2BF_S16_ST_INCP, + XTENSA_INS_EE_FFT_VST_R32_DECP, + XTENSA_INS_EE_GET_GPIO_IN, + XTENSA_INS_EE_LDF_128_IP, + XTENSA_INS_EE_LDF_128_XP, + XTENSA_INS_EE_LDF_64_IP, + XTENSA_INS_EE_LDF_64_XP, + XTENSA_INS_EE_LDQA_S16_128_IP, + XTENSA_INS_EE_LDQA_S16_128_XP, + XTENSA_INS_EE_LDQA_S8_128_IP, + XTENSA_INS_EE_LDQA_S8_128_XP, + XTENSA_INS_EE_LDQA_U16_128_IP, + XTENSA_INS_EE_LDQA_U16_128_XP, + XTENSA_INS_EE_LDQA_U8_128_IP, + XTENSA_INS_EE_LDQA_U8_128_XP, + XTENSA_INS_EE_LDXQ_32, + XTENSA_INS_EE_LD_128_USAR_IP, + XTENSA_INS_EE_LD_128_USAR_XP, + XTENSA_INS_EE_LD_ACCX_IP, + XTENSA_INS_EE_LD_QACC_H_H_32_IP, + XTENSA_INS_EE_LD_QACC_H_L_128_IP, + XTENSA_INS_EE_LD_QACC_L_H_32_IP, + XTENSA_INS_EE_LD_QACC_L_L_128_IP, + XTENSA_INS_EE_LD_UA_STATE_IP, + XTENSA_INS_EE_MOVI_32_A, + XTENSA_INS_EE_MOVI_32_Q, + XTENSA_INS_EE_MOV_S16_QACC, + XTENSA_INS_EE_MOV_S8_QACC, + XTENSA_INS_EE_MOV_U16_QACC, + XTENSA_INS_EE_MOV_U8_QACC, + XTENSA_INS_EE_NOTQ, + XTENSA_INS_EE_ORQ, + XTENSA_INS_EE_SET_BIT_GPIO_OUT, + XTENSA_INS_EE_SLCI_2Q, + XTENSA_INS_EE_SLCXXP_2Q, + XTENSA_INS_EE_SRCI_2Q, + XTENSA_INS_EE_SRCMB_S16_QACC, + XTENSA_INS_EE_SRCMB_S8_QACC, + XTENSA_INS_EE_SRCQ_128_ST_INCP, + XTENSA_INS_EE_SRCXXP_2Q, + XTENSA_INS_EE_SRC_Q, + XTENSA_INS_EE_SRC_Q_LD_IP, + XTENSA_INS_EE_SRC_Q_LD_XP, + XTENSA_INS_EE_SRC_Q_QUP, + XTENSA_INS_EE_SRS_ACCX, + XTENSA_INS_EE_STF_128_IP, + XTENSA_INS_EE_STF_128_XP, + XTENSA_INS_EE_STF_64_IP, + XTENSA_INS_EE_STF_64_XP, + XTENSA_INS_EE_STXQ_32, + XTENSA_INS_EE_ST_ACCX_IP, + XTENSA_INS_EE_ST_QACC_H_H_32_IP, + XTENSA_INS_EE_ST_QACC_H_L_128_IP, + XTENSA_INS_EE_ST_QACC_L_H_32_IP, + XTENSA_INS_EE_ST_QACC_L_L_128_IP, + XTENSA_INS_EE_ST_UA_STATE_IP, + XTENSA_INS_EE_VADDS_S16, + XTENSA_INS_EE_VADDS_S16_LD_INCP, + XTENSA_INS_EE_VADDS_S16_ST_INCP, + XTENSA_INS_EE_VADDS_S32, + XTENSA_INS_EE_VADDS_S32_LD_INCP, + XTENSA_INS_EE_VADDS_S32_ST_INCP, + XTENSA_INS_EE_VADDS_S8, + XTENSA_INS_EE_VADDS_S8_LD_INCP, + XTENSA_INS_EE_VADDS_S8_ST_INCP, + XTENSA_INS_EE_VCMP_EQ_S16, + XTENSA_INS_EE_VCMP_EQ_S32, + XTENSA_INS_EE_VCMP_EQ_S8, + XTENSA_INS_EE_VCMP_GT_S16, + XTENSA_INS_EE_VCMP_GT_S32, + XTENSA_INS_EE_VCMP_GT_S8, + XTENSA_INS_EE_VCMP_LT_S16, + XTENSA_INS_EE_VCMP_LT_S32, + XTENSA_INS_EE_VCMP_LT_S8, + XTENSA_INS_EE_VLDBC_16, + XTENSA_INS_EE_VLDBC_16_IP, + XTENSA_INS_EE_VLDBC_16_XP, + XTENSA_INS_EE_VLDBC_32, + XTENSA_INS_EE_VLDBC_32_IP, + XTENSA_INS_EE_VLDBC_32_XP, + XTENSA_INS_EE_VLDBC_8, + XTENSA_INS_EE_VLDBC_8_IP, + XTENSA_INS_EE_VLDBC_8_XP, + XTENSA_INS_EE_VLDHBC_16_INCP, + XTENSA_INS_EE_VLD_128_IP, + XTENSA_INS_EE_VLD_128_XP, + XTENSA_INS_EE_VLD_H_64_IP, + XTENSA_INS_EE_VLD_H_64_XP, + XTENSA_INS_EE_VLD_L_64_IP, + XTENSA_INS_EE_VLD_L_64_XP, + XTENSA_INS_EE_VMAX_S16, + XTENSA_INS_EE_VMAX_S16_LD_INCP, + XTENSA_INS_EE_VMAX_S16_ST_INCP, + XTENSA_INS_EE_VMAX_S32, + XTENSA_INS_EE_VMAX_S32_LD_INCP, + XTENSA_INS_EE_VMAX_S32_ST_INCP, + XTENSA_INS_EE_VMAX_S8, + XTENSA_INS_EE_VMAX_S8_LD_INCP, + XTENSA_INS_EE_VMAX_S8_ST_INCP, + XTENSA_INS_EE_VMIN_S16, + XTENSA_INS_EE_VMIN_S16_LD_INCP, + XTENSA_INS_EE_VMIN_S16_ST_INCP, + XTENSA_INS_EE_VMIN_S32, + XTENSA_INS_EE_VMIN_S32_LD_INCP, + XTENSA_INS_EE_VMIN_S32_ST_INCP, + XTENSA_INS_EE_VMIN_S8, + XTENSA_INS_EE_VMIN_S8_LD_INCP, + XTENSA_INS_EE_VMIN_S8_ST_INCP, + XTENSA_INS_EE_VMULAS_S16_ACCX, + XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP, + XTENSA_INS_EE_VMULAS_S16_ACCX_LD_IP_QUP, + XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP, + XTENSA_INS_EE_VMULAS_S16_ACCX_LD_XP_QUP, + XTENSA_INS_EE_VMULAS_S16_QACC, + XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP, + XTENSA_INS_EE_VMULAS_S16_QACC_LDBC_INCP_QUP, + XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP, + XTENSA_INS_EE_VMULAS_S16_QACC_LD_IP_QUP, + XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP, + XTENSA_INS_EE_VMULAS_S16_QACC_LD_XP_QUP, + XTENSA_INS_EE_VMULAS_S8_ACCX, + XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP, + XTENSA_INS_EE_VMULAS_S8_ACCX_LD_IP_QUP, + XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP, + XTENSA_INS_EE_VMULAS_S8_ACCX_LD_XP_QUP, + XTENSA_INS_EE_VMULAS_S8_QACC, + XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP, + XTENSA_INS_EE_VMULAS_S8_QACC_LDBC_INCP_QUP, + XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP, + XTENSA_INS_EE_VMULAS_S8_QACC_LD_IP_QUP, + XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP, + XTENSA_INS_EE_VMULAS_S8_QACC_LD_XP_QUP, + XTENSA_INS_EE_VMULAS_U16_ACCX, + XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP, + XTENSA_INS_EE_VMULAS_U16_ACCX_LD_IP_QUP, + XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP, + XTENSA_INS_EE_VMULAS_U16_ACCX_LD_XP_QUP, + XTENSA_INS_EE_VMULAS_U16_QACC, + XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP, + XTENSA_INS_EE_VMULAS_U16_QACC_LDBC_INCP_QUP, + XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP, + XTENSA_INS_EE_VMULAS_U16_QACC_LD_IP_QUP, + XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP, + XTENSA_INS_EE_VMULAS_U16_QACC_LD_XP_QUP, + XTENSA_INS_EE_VMULAS_U8_ACCX, + XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP, + XTENSA_INS_EE_VMULAS_U8_ACCX_LD_IP_QUP, + XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP, + XTENSA_INS_EE_VMULAS_U8_ACCX_LD_XP_QUP, + XTENSA_INS_EE_VMULAS_U8_QACC, + XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP, + XTENSA_INS_EE_VMULAS_U8_QACC_LDBC_INCP_QUP, + XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP, + XTENSA_INS_EE_VMULAS_U8_QACC_LD_IP_QUP, + XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP, + XTENSA_INS_EE_VMULAS_U8_QACC_LD_XP_QUP, + XTENSA_INS_EE_VMUL_S16, + XTENSA_INS_EE_VMUL_S16_LD_INCP, + XTENSA_INS_EE_VMUL_S16_ST_INCP, + XTENSA_INS_EE_VMUL_S8, + XTENSA_INS_EE_VMUL_S8_LD_INCP, + XTENSA_INS_EE_VMUL_S8_ST_INCP, + XTENSA_INS_EE_VMUL_U16, + XTENSA_INS_EE_VMUL_U16_LD_INCP, + XTENSA_INS_EE_VMUL_U16_ST_INCP, + XTENSA_INS_EE_VMUL_U8, + XTENSA_INS_EE_VMUL_U8_LD_INCP, + XTENSA_INS_EE_VMUL_U8_ST_INCP, + XTENSA_INS_EE_VPRELU_S16, + XTENSA_INS_EE_VPRELU_S8, + XTENSA_INS_EE_VRELU_S16, + XTENSA_INS_EE_VRELU_S8, + XTENSA_INS_EE_VSL_32, + XTENSA_INS_EE_VSMULAS_S16_QACC, + XTENSA_INS_EE_VSMULAS_S16_QACC_LD_INCP, + XTENSA_INS_EE_VSMULAS_S8_QACC, + XTENSA_INS_EE_VSMULAS_S8_QACC_LD_INCP, + XTENSA_INS_EE_VSR_32, + XTENSA_INS_EE_VST_128_IP, + XTENSA_INS_EE_VST_128_XP, + XTENSA_INS_EE_VST_H_64_IP, + XTENSA_INS_EE_VST_H_64_XP, + XTENSA_INS_EE_VST_L_64_IP, + XTENSA_INS_EE_VST_L_64_XP, + XTENSA_INS_EE_VSUBS_S16, + XTENSA_INS_EE_VSUBS_S16_LD_INCP, + XTENSA_INS_EE_VSUBS_S16_ST_INCP, + XTENSA_INS_EE_VSUBS_S32, + XTENSA_INS_EE_VSUBS_S32_LD_INCP, + XTENSA_INS_EE_VSUBS_S32_ST_INCP, + XTENSA_INS_EE_VSUBS_S8, + XTENSA_INS_EE_VSUBS_S8_LD_INCP, + XTENSA_INS_EE_VSUBS_S8_ST_INCP, + XTENSA_INS_EE_VUNZIP_16, + XTENSA_INS_EE_VUNZIP_32, + XTENSA_INS_EE_VUNZIP_8, + XTENSA_INS_EE_VZIP_16, + XTENSA_INS_EE_VZIP_32, + XTENSA_INS_EE_VZIP_8, + XTENSA_INS_EE_WR_MASK_GPIO_OUT, + XTENSA_INS_EE_XORQ, + XTENSA_INS_EE_ZERO_ACCX, + XTENSA_INS_EE_ZERO_Q, + XTENSA_INS_EE_ZERO_QACC, + XTENSA_INS_ENTRY, XTENSA_INS_ESYNC, + XTENSA_INS_EXCW, XTENSA_INS_EXTUI, XTENSA_INS_EXTW, + XTENSA_INS_FLOAT_S, + XTENSA_INS_FLOOR_S, + XTENSA_INS_GET_GPIO_IN, + XTENSA_INS_ILL, + XTENSA_INS_ILL_N, XTENSA_INS_ISYNC, XTENSA_INS_J, XTENSA_INS_JX, XTENSA_INS_L16SI, XTENSA_INS_L16UI, + XTENSA_INS_L32E, XTENSA_INS_L32I, + XTENSA_INS_L32I_N, XTENSA_INS_L32R, XTENSA_INS_L8UI, + XTENSA_INS_LDDEC, + XTENSA_INS_LDINC, + XTENSA_INS_LOOP, + XTENSA_INS_LOOPGTZ, + XTENSA_INS_LOOPNEZ, + XTENSA_INS_LSI, + XTENSA_INS_LSIP, + XTENSA_INS_LSX, + XTENSA_INS_LSXP, + XTENSA_INS_MADDN_S, + XTENSA_INS_MADD_S, + XTENSA_INS_MAX, + XTENSA_INS_MAXU, XTENSA_INS_MEMW, + XTENSA_INS_MIN, + XTENSA_INS_MINU, + XTENSA_INS_MKDADJ_S, + XTENSA_INS_MKSADJ_S, XTENSA_INS_MOVEQZ, + XTENSA_INS_MOVEQZ_S, + XTENSA_INS_MOVF, + XTENSA_INS_MOVF_S, XTENSA_INS_MOVGEZ, + XTENSA_INS_MOVGEZ_S, XTENSA_INS_MOVI, + XTENSA_INS_MOVI_N, XTENSA_INS_MOVLTZ, + XTENSA_INS_MOVLTZ_S, XTENSA_INS_MOVNEZ, + XTENSA_INS_MOVNEZ_S, + XTENSA_INS_MOVSP, + XTENSA_INS_MOVT, + XTENSA_INS_MOVT_S, + XTENSA_INS_MOV_N, + XTENSA_INS_MOV_S, + XTENSA_INS_MSUB_S, + XTENSA_INS_MUL16S, + XTENSA_INS_MUL16U, + XTENSA_INS_MULA_AA_HH, + XTENSA_INS_MULA_AA_HL, + XTENSA_INS_MULA_AA_LH, + XTENSA_INS_MULA_AA_LL, + XTENSA_INS_MULA_AD_HH, + XTENSA_INS_MULA_AD_HL, + XTENSA_INS_MULA_AD_LH, + XTENSA_INS_MULA_AD_LL, + XTENSA_INS_MULA_DA_HH, + XTENSA_INS_MULA_DA_HH_LDDEC, + XTENSA_INS_MULA_DA_HH_LDINC, + XTENSA_INS_MULA_DA_HL, + XTENSA_INS_MULA_DA_HL_LDDEC, + XTENSA_INS_MULA_DA_HL_LDINC, + XTENSA_INS_MULA_DA_LH, + XTENSA_INS_MULA_DA_LH_LDDEC, + XTENSA_INS_MULA_DA_LH_LDINC, + XTENSA_INS_MULA_DA_LL, + XTENSA_INS_MULA_DA_LL_LDDEC, + XTENSA_INS_MULA_DA_LL_LDINC, + XTENSA_INS_MULA_DD_HH, + XTENSA_INS_MULA_DD_HH_LDDEC, + XTENSA_INS_MULA_DD_HH_LDINC, + XTENSA_INS_MULA_DD_HL, + XTENSA_INS_MULA_DD_HL_LDDEC, + XTENSA_INS_MULA_DD_HL_LDINC, + XTENSA_INS_MULA_DD_LH, + XTENSA_INS_MULA_DD_LH_LDDEC, + XTENSA_INS_MULA_DD_LH_LDINC, + XTENSA_INS_MULA_DD_LL, + XTENSA_INS_MULA_DD_LL_LDDEC, + XTENSA_INS_MULA_DD_LL_LDINC, + XTENSA_INS_MULL, + XTENSA_INS_MULSH, + XTENSA_INS_MULS_AA_HH, + XTENSA_INS_MULS_AA_HL, + XTENSA_INS_MULS_AA_LH, + XTENSA_INS_MULS_AA_LL, + XTENSA_INS_MULS_AD_HH, + XTENSA_INS_MULS_AD_HL, + XTENSA_INS_MULS_AD_LH, + XTENSA_INS_MULS_AD_LL, + XTENSA_INS_MULS_DA_HH, + XTENSA_INS_MULS_DA_HL, + XTENSA_INS_MULS_DA_LH, + XTENSA_INS_MULS_DA_LL, + XTENSA_INS_MULS_DD_HH, + XTENSA_INS_MULS_DD_HL, + XTENSA_INS_MULS_DD_LH, + XTENSA_INS_MULS_DD_LL, + XTENSA_INS_MULUH, + XTENSA_INS_MUL_AA_HH, + XTENSA_INS_MUL_AA_HL, + XTENSA_INS_MUL_AA_LH, + XTENSA_INS_MUL_AA_LL, + XTENSA_INS_MUL_AD_HH, + XTENSA_INS_MUL_AD_HL, + XTENSA_INS_MUL_AD_LH, + XTENSA_INS_MUL_AD_LL, + XTENSA_INS_MUL_DA_HH, + XTENSA_INS_MUL_DA_HL, + XTENSA_INS_MUL_DA_LH, + XTENSA_INS_MUL_DA_LL, + XTENSA_INS_MUL_DD_HH, + XTENSA_INS_MUL_DD_HL, + XTENSA_INS_MUL_DD_LH, + XTENSA_INS_MUL_DD_LL, + XTENSA_INS_MUL_S, XTENSA_INS_NEG, + XTENSA_INS_NEG_S, + XTENSA_INS_NEXP01_S, XTENSA_INS_NOP, + XTENSA_INS_NSA, + XTENSA_INS_NSAU, + XTENSA_INS_OEQ_S, + XTENSA_INS_OLE_S, + XTENSA_INS_OLT_S, XTENSA_INS_OR, + XTENSA_INS_ORB, + XTENSA_INS_ORBC, + XTENSA_INS_QUOS, + XTENSA_INS_QUOU, + XTENSA_INS_RECIP0_S, + XTENSA_INS_REMS, + XTENSA_INS_REMU, + XTENSA_INS_RER, XTENSA_INS_RET, + XTENSA_INS_RETW, + XTENSA_INS_RETW_N, + XTENSA_INS_RET_N, + XTENSA_INS_RFDE, + XTENSA_INS_RFE, + XTENSA_INS_RFI, + XTENSA_INS_RFR, + XTENSA_INS_RFWO, + XTENSA_INS_RFWU, + XTENSA_INS_ROTW, + XTENSA_INS_ROUND_S, + XTENSA_INS_RSIL, + XTENSA_INS_RSQRT0_S, XTENSA_INS_RSR, XTENSA_INS_RSYNC, + XTENSA_INS_RUR, + XTENSA_INS_RUR_ACCX_0, + XTENSA_INS_RUR_ACCX_1, + XTENSA_INS_RUR_AE_BITHEAD, + XTENSA_INS_RUR_AE_BITPTR, + XTENSA_INS_RUR_AE_BITSUSED, + XTENSA_INS_RUR_AE_CBEGIN0, + XTENSA_INS_RUR_AE_CEND0, + XTENSA_INS_RUR_AE_CWRAP, + XTENSA_INS_RUR_AE_CW_SD_NO, + XTENSA_INS_RUR_AE_FIRST_TS, + XTENSA_INS_RUR_AE_NEXTOFFSET, + XTENSA_INS_RUR_AE_OVERFLOW, + XTENSA_INS_RUR_AE_OVF_SAR, + XTENSA_INS_RUR_AE_SAR, + XTENSA_INS_RUR_AE_SEARCHDONE, + XTENSA_INS_RUR_AE_TABLESIZE, + XTENSA_INS_RUR_AE_TS_FTS_BU_BP, + XTENSA_INS_RUR_FFT_BIT_WIDTH, + XTENSA_INS_RUR_GPIO_OUT, + XTENSA_INS_RUR_QACC_H_0, + XTENSA_INS_RUR_QACC_H_1, + XTENSA_INS_RUR_QACC_H_2, + XTENSA_INS_RUR_QACC_H_3, + XTENSA_INS_RUR_QACC_H_4, + XTENSA_INS_RUR_QACC_L_0, + XTENSA_INS_RUR_QACC_L_1, + XTENSA_INS_RUR_QACC_L_2, + XTENSA_INS_RUR_QACC_L_3, + XTENSA_INS_RUR_QACC_L_4, + XTENSA_INS_RUR_SAR_BYTE, + XTENSA_INS_RUR_UA_STATE_0, + XTENSA_INS_RUR_UA_STATE_1, + XTENSA_INS_RUR_UA_STATE_2, + XTENSA_INS_RUR_UA_STATE_3, XTENSA_INS_S16I, + XTENSA_INS_S32C1I, + XTENSA_INS_S32E, XTENSA_INS_S32I, + XTENSA_INS_S32I_N, XTENSA_INS_S8I, + XTENSA_INS_SET_BIT_GPIO_OUT, + XTENSA_INS_SEXT, + XTENSA_INS_SIMCALL, XTENSA_INS_SLL, XTENSA_INS_SLLI, + XTENSA_INS_SQRT0_S, XTENSA_INS_SRA, XTENSA_INS_SRAI, XTENSA_INS_SRC, @@ -113,15 +1526,84 @@ typedef enum xtensa_insn { XTENSA_INS_SRLI, XTENSA_INS_SSA8L, XTENSA_INS_SSAI, + XTENSA_INS_SSI, + XTENSA_INS_SSIP, XTENSA_INS_SSL, XTENSA_INS_SSR, + XTENSA_INS_SSX, + XTENSA_INS_SSXP, XTENSA_INS_SUB, XTENSA_INS_SUBX2, XTENSA_INS_SUBX4, XTENSA_INS_SUBX8, + XTENSA_INS_SUB_S, + XTENSA_INS_SYSCALL, + XTENSA_INS_TRUNC_S, + XTENSA_INS_UEQ_S, + XTENSA_INS_UFLOAT_S, + XTENSA_INS_ULE_S, + XTENSA_INS_ULT_S, + XTENSA_INS_UMUL_AA_HH, + XTENSA_INS_UMUL_AA_HL, + XTENSA_INS_UMUL_AA_LH, + XTENSA_INS_UMUL_AA_LL, + XTENSA_INS_UN_S, + XTENSA_INS_UTRUNC_S, + XTENSA_INS_WAITI, + XTENSA_INS_WDTLB, + XTENSA_INS_WER, + XTENSA_INS_WFR, + XTENSA_INS_WITLB, + XTENSA_INS_WR_MASK_GPIO_OUT, XTENSA_INS_WSR, + XTENSA_INS_WUR, + XTENSA_INS_WUR_ACCX_0, + XTENSA_INS_WUR_ACCX_1, + XTENSA_INS_WUR_AE_BITHEAD, + XTENSA_INS_WUR_AE_BITPTR, + XTENSA_INS_WUR_AE_BITSUSED, + XTENSA_INS_WUR_AE_CBEGIN0, + XTENSA_INS_WUR_AE_CEND0, + XTENSA_INS_WUR_AE_CWRAP, + XTENSA_INS_WUR_AE_CW_SD_NO, + XTENSA_INS_WUR_AE_FIRST_TS, + XTENSA_INS_WUR_AE_NEXTOFFSET, + XTENSA_INS_WUR_AE_OVERFLOW, + XTENSA_INS_WUR_AE_OVF_SAR, + XTENSA_INS_WUR_AE_SAR, + XTENSA_INS_WUR_AE_SEARCHDONE, + XTENSA_INS_WUR_AE_TABLESIZE, + XTENSA_INS_WUR_AE_TS_FTS_BU_BP, + XTENSA_INS_WUR_FCR, + XTENSA_INS_WUR_FFT_BIT_WIDTH, + XTENSA_INS_WUR_FSR, + XTENSA_INS_WUR_GPIO_OUT, + XTENSA_INS_WUR_QACC_H_0, + XTENSA_INS_WUR_QACC_H_1, + XTENSA_INS_WUR_QACC_H_2, + XTENSA_INS_WUR_QACC_H_3, + XTENSA_INS_WUR_QACC_H_4, + XTENSA_INS_WUR_QACC_L_0, + XTENSA_INS_WUR_QACC_L_1, + XTENSA_INS_WUR_QACC_L_2, + XTENSA_INS_WUR_QACC_L_3, + XTENSA_INS_WUR_QACC_L_4, + XTENSA_INS_WUR_SAR_BYTE, + XTENSA_INS_WUR_UA_STATE_0, + XTENSA_INS_WUR_UA_STATE_1, + XTENSA_INS_WUR_UA_STATE_2, + XTENSA_INS_WUR_UA_STATE_3, XTENSA_INS_XOR, + XTENSA_INS_XORB, XTENSA_INS_XSR, + XTENSA_INS__L32I, + XTENSA_INS__L32I_N, + XTENSA_INS__MOVI, + XTENSA_INS__S32I, + XTENSA_INS__S32I_N, + XTENSA_INS__SLLI, + XTENSA_INS__SRLI, + XTENSA_INS_MV_QR, // clang-format on // generated content end @@ -136,12 +1618,74 @@ typedef enum xtensa_feature { // clang-format off XTENSA_FEATURE_HASDENSITY = 128, + XTENSA_FEATURE_HASSINGLEFLOAT, + XTENSA_FEATURE_HASWINDOWED, + XTENSA_FEATURE_HASBOOLEAN, + XTENSA_FEATURE_HASLOOP, + XTENSA_FEATURE_HASSEXT, + XTENSA_FEATURE_HASCLAMPS, + XTENSA_FEATURE_HASNSA, + XTENSA_FEATURE_HASMINMAX, + XTENSA_FEATURE_HASMUL16, + XTENSA_FEATURE_HASMUL32, + XTENSA_FEATURE_HASMUL32HIGH, + XTENSA_FEATURE_HASDIV32, + XTENSA_FEATURE_HASMAC16, + XTENSA_FEATURE_HASDFPACCEL, + XTENSA_FEATURE_HASS32C1I, + XTENSA_FEATURE_HASTHREADPTR, + XTENSA_FEATURE_HASEXTENDEDL32R, + XTENSA_FEATURE_HASATOMCTL, + XTENSA_FEATURE_HASMEMCTL, + XTENSA_FEATURE_HASDEBUG, + XTENSA_FEATURE_HASEXCEPTION, + XTENSA_FEATURE_HASHIGHPRIINTERRUPTS, + XTENSA_FEATURE_HASCOPROCESSOR, + XTENSA_FEATURE_HASINTERRUPT, + XTENSA_FEATURE_HASRELOCATABLEVECTOR, + XTENSA_FEATURE_HASTIMERINT, + XTENSA_FEATURE_HASPRID, + XTENSA_FEATURE_HASREGIONPROTECTION, + XTENSA_FEATURE_HASMISCSR, + XTENSA_FEATURE_HASESP32S2OPS, + XTENSA_FEATURE_HASESP32S3OPS, + XTENSA_FEATURE_HASHIFI3, + XTENSA_FEATURE_HASFORCEDATOMICS, // clang-format on // generated content end XTENSA_GRP_ENDING, ///< mark the end of the list of features } xtensa_feature; +/// Xtensa instruction formats. To get details about them please +/// refer to `XtensaInstrFormats.td` in LLVM. +typedef enum { + XTENSA_INSN_FORM_INVALID = 0, + // generated content begin + // clang-format off + + XTENSA_INSN_FORM_RRR, + XTENSA_INSN_FORM_RRI8, + XTENSA_INSN_FORM_RRRN, + XTENSA_INSN_FORM_AEINST24, + XTENSA_INSN_FORM_BRI12, + XTENSA_INSN_FORM_CALL, + XTENSA_INSN_FORM_CALLX, + XTENSA_INSN_FORM_EE_INST24, + XTENSA_INSN_FORM_RRI4, + XTENSA_INSN_FORM_RI16, + XTENSA_INSN_FORM_RI7, + XTENSA_INSN_FORM_RSR, + + // clang-format on + // generated content end + XTENSA_INSN_FORM_MAX, +} xtensa_insn_form; + +typedef struct { + xtensa_insn_form form; +} xtensa_suppl_info; + typedef enum cs_xtensa_op_type { XTENSA_OP_INVALID = CS_OP_INVALID, ///< = (Uninitialized). XTENSA_OP_REG = CS_OP_REG, ///< = (Register operand). @@ -154,7 +1698,7 @@ typedef enum cs_xtensa_op_type { typedef struct cs_xtensa_op_mem { uint8_t base; - uint8_t disp; + int32_t disp; } cs_xtensa_op_mem; typedef struct cs_xtensa_operand { @@ -173,6 +1717,7 @@ typedef struct cs_xtensa_operand { typedef struct cs_xtensa { uint8_t op_count; cs_xtensa_op operands[MAX_XTENSA_OPS]; + xtensa_insn_form format; } cs_xtensa; #ifdef __cplusplus diff --git a/debian/.gitignore b/packages/deb/.gitignore similarity index 100% rename from debian/.gitignore rename to packages/deb/.gitignore diff --git a/debian/Dockerfile b/packages/deb/Dockerfile similarity index 52% rename from debian/Dockerfile rename to packages/deb/Dockerfile index c3fb4966cb..ba833b1870 100644 --- a/debian/Dockerfile +++ b/packages/deb/Dockerfile @@ -1,8 +1,7 @@ ARG VERSION="" -# Assume this is run from capstone/debian directory # Run in the root of the repo -# docker build -f ./debian/Dockerfile -t packager . +# docker build -f ./packages/deb/Dockerfile -t packager . FROM debian:bookworm-slim # Install necessary tools for packaging @@ -10,10 +9,10 @@ RUN apt-get -qq update && \ DEBIAN_FRONTEND=noninteractive apt-get -qq install -y \ fakeroot dpkg-dev dos2unix cmake -# Copy your project files into the container +# Copy project files into the container RUN mkdir /capstone COPY . /capstone -WORKDIR /capstone/ +WORKDIR /capstone/ # Using cmake, see BUILDING.md file # For debug build change "Release" to "Debug" @@ -23,36 +22,29 @@ RUN cmake --build build # List files before cmake install # RUN find / -type f > /before-install.txt -# Run cmake install, by default everything goes into /usr/local -RUN cmake --install build +# Make directories as needed +RUN mkdir -p /package-root/usr/include/capstone/ +RUN mkdir -p /package-root/usr/lib/pkgconfig/ +RUN mkdir -p /package-root/usr/bin/ + +# Run cmake install +RUN cmake --install build --prefix /package-root/usr/ # List files after cmake install # RUN find / -type f > /after-install.txt -# Make directories as needed -RUN mkdir -p /package-root/usr/local/include/capstone/ -RUN mkdir -p /package-root/usr/local/lib/pkgconfig/ -RUN mkdir -p /package-root/usr/local/bin/ - -# Copy /usr/local/include/capstone/ to /package-root/usr/local/include/capstone/ and all other cases -RUN cp -r /usr/local/include/capstone/* /package-root/usr/local/include/capstone/ -RUN cp -r /usr/local/lib/libcapstone* /package-root/usr/local/lib/ -RUN cp -r /usr/local/lib/pkgconfig/capstone* /package-root/usr/local/lib/pkgconfig/ -RUN cp -r /usr/local/bin/cstool /package-root/usr/local/bin/ - # Create DEBIAN directory and control file -COPY ./debian/control /package-root/DEBIAN/control +COPY ./packages/deb/control /package-root/DEBIAN/control # Update capstone.pc file with the correct version and remove archs field # Update control file with the correct version ARG VERSION RUN sed -i "s/^Version:.*/Version: ${VERSION}/" /package-root/DEBIAN/control -RUN sed -i "s/^Version:.*/Version: ${VERSION}/" /package-root/usr/local/lib/pkgconfig/capstone.pc -RUN sed -i "/^archs=/d" /package-root/usr/local/lib/pkgconfig/capstone.pc +RUN sed -i "s/^Version:.*/Version: ${VERSION}/" /package-root/usr/lib/pkgconfig/capstone.pc +RUN sed -i "/^archs=/d" /package-root/usr/lib/pkgconfig/capstone.pc -# Add postinst script to run ldconfig after installation -COPY ./debian/postinst /package-root/DEBIAN/postinst -RUN chmod 755 /package-root/DEBIAN/postinst +# Add triggers script to run ldconfig after installation +COPY ./packages/deb/triggers /package-root/DEBIAN/triggers # Build the package RUN fakeroot dpkg-deb --build /package-root /libcapstone-dev.deb diff --git a/packages/deb/README.md b/packages/deb/README.md new file mode 100644 index 0000000000..fc79aa4e0e --- /dev/null +++ b/packages/deb/README.md @@ -0,0 +1,7 @@ +Incomplete Debian package implementation. +It can be used to generate an easily installable Capstone, but misses a lot of +mandatory things to add it in the Debian repos (`debian/control` is incomplete, no dependencies added etc.). + +You can build the package by dispatching the `Build Debian Package` workflow or executing the commands in the `Dockerfile`. +It assumes the current commit is tagged and `"$(git describe --tags --abbrev=0)"` returns a valid version number. +The package is uploaded as artifact. diff --git a/debian/check_capstone.sh b/packages/deb/check_capstone.sh old mode 100644 new mode 100755 similarity index 90% rename from debian/check_capstone.sh rename to packages/deb/check_capstone.sh index bd0e39183e..4460f41846 --- a/debian/check_capstone.sh +++ b/packages/deb/check_capstone.sh @@ -18,7 +18,7 @@ TEMP_DIR=$(mktemp -d) dpkg-deb -x "$DEB_FILE" "$TEMP_DIR" # Path to the capstone.pc file -CAPSTONE_PC="$TEMP_DIR/usr/local/lib/pkgconfig/capstone.pc" +CAPSTONE_PC="$TEMP_DIR/usr/lib/pkgconfig/capstone.pc" # Check if the capstone.pc file exists if [[ ! -f "$CAPSTONE_PC" ]]; then @@ -48,7 +48,7 @@ if [[ "$ACTUAL_VERSION" != "$EXPECTED_VERSION" ]]; then fi # Check if libcapstone.a is included in the package -LIBCAPSTONE_A="$TEMP_DIR/usr/local/lib/libcapstone.a" +LIBCAPSTONE_A="$TEMP_DIR/usr/lib/libcapstone.a" if [[ ! -f "$LIBCAPSTONE_A" ]]; then echo "libcapstone.a not found in the package!" rm -rf "$TEMP_DIR" @@ -56,7 +56,7 @@ if [[ ! -f "$LIBCAPSTONE_A" ]]; then fi # Check if libcapstone.so is included in the package -LIBCAPSTONE_SO="$TEMP_DIR/usr/local/lib/libcapstone.so" +LIBCAPSTONE_SO="$TEMP_DIR/usr/lib/libcapstone.so" if [[ ! -f "$LIBCAPSTONE_SO" ]]; then echo "libcapstone.so not found in the package!" rm -rf "$TEMP_DIR" @@ -65,4 +65,4 @@ fi echo "libcapstone-dev.deb file is correct." rm -rf "$TEMP_DIR" -exit 0 \ No newline at end of file +exit 0 diff --git a/debian/control b/packages/deb/control similarity index 100% rename from debian/control rename to packages/deb/control diff --git a/debian/setup.sh b/packages/deb/setup.sh old mode 100644 new mode 100755 similarity index 80% rename from debian/setup.sh rename to packages/deb/setup.sh index c02212ef0b..a3595dfd2c --- a/debian/setup.sh +++ b/packages/deb/setup.sh @@ -6,9 +6,9 @@ get_os_version() { lsb_release -i -s 2>/dev/null } -# Check if the script is running in the ./debian folder -if [[ $(basename "$PWD") != "debian" ]]; then - echo "ERROR: Script must be run from the ./debian directory" +# Check if the script is running in the ./packages/deb folder +if [[ $(basename "$PWD") != "deb" ]]; then + echo "ERROR: Script must be run from the ./deb directory" exit 1 fi @@ -40,8 +40,8 @@ if [[ ! "$version" =~ ^[0-9]+\.[0-9]+\.[0-9]+$ ]]; then fi # Now build the packager container from that -pushd ../ -docker build -f ./debian/Dockerfile -t packager --build-arg VERSION="${version}" . +pushd ../../ +docker build -f ./packages/deb/Dockerfile -t packager --build-arg VERSION="${version}" . popd # Copy deb file out of container to host @@ -50,4 +50,4 @@ docker run --rm -v $(pwd):/out packager bash -c "cp /libcapstone-dev.deb /out" # Check which files existed before and after 'make install' was executed. # docker run --rm -v $(pwd):/out packager bash -c "cp /before-install.txt /out" # docker run --rm -v $(pwd):/out packager bash -c "cp /after-install.txt /out" -# diff before-install.txt after-install.txt \ No newline at end of file +# diff before-install.txt after-install.txt diff --git a/packages/deb/triggers b/packages/deb/triggers new file mode 100644 index 0000000000..eafa63be77 --- /dev/null +++ b/packages/deb/triggers @@ -0,0 +1,2 @@ +# Trigger ldconfig after install +activate-noawait ldconfig diff --git a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py index 3a509236a2..a5ae11e5c8 100755 --- a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py @@ -50,6 +50,7 @@ from autosync.cpptranslator.patches.IsRegImm import IsOperandRegImm from autosync.cpptranslator.patches.LLVMFallThrough import LLVMFallThrough from autosync.cpptranslator.patches.LLVMunreachable import LLVMUnreachable +from autosync.cpptranslator.patches.LLVM_DEBUG import LLVM_DEBUG from autosync.cpptranslator.patches.MethodToFunctions import MethodToFunction from autosync.cpptranslator.patches.MethodTypeQualifier import MethodTypeQualifier from autosync.cpptranslator.patches.NamespaceAnon import NamespaceAnon @@ -153,6 +154,7 @@ class Translator: Assert.__name__: 0, # ◁─────────┐ The llvm_unreachable calls are replaced with asserts. LLVMUnreachable.__name__: 1, # ─┘ Those assert should stay. LLVMFallThrough.__name__: 0, + LLVM_DEBUG.__name__: 0, DeclarationInConditionalClause.__name__: 0, StreamOperations.__name__: 0, OutStreamParam.__name__: 0, # ◁──────┐ add_cs_detail() is added to printOperand functions with a certain @@ -323,6 +325,8 @@ def init_patches(self): patch = ConstMCInstParameter(p) case LLVMUnreachable.__name__: patch = LLVMUnreachable(p) + case LLVM_DEBUG.__name__: + patch = LLVM_DEBUG(p) case ClassConstructorDef.__name__: patch = ClassConstructorDef(p) case ConstMCOperand.__name__: @@ -434,7 +438,8 @@ def translate(self) -> None: else: # A capture which is part of the main capture. # Add it to the bundle. - captures_bundle[-1].append(q) + if len(captures_bundle) > 0: + captures_bundle[-1].append(q) log.debug( f"Patch {patch.__class__.__name__} (to patch: {len(captures_bundle)})." diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py index 79361c5cb9..0c5ea484db 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py @@ -46,6 +46,7 @@ from autosync.cpptranslator.patches.IsPredicate import IsPredicate from autosync.cpptranslator.patches.IsRegImm import IsOperandRegImm from autosync.cpptranslator.patches.LLVMFallThrough import LLVMFallThrough +from autosync.cpptranslator.patches.LLVM_DEBUG import LLVM_DEBUG from autosync.cpptranslator.patches.LLVMunreachable import LLVMUnreachable from autosync.cpptranslator.patches.Override import Override from autosync.cpptranslator.patches.MethodToFunctions import MethodToFunction @@ -413,7 +414,12 @@ def test_llvmfallthrough(self): def test_llvmunreachable(self): patch = LLVMUnreachable(0) syntax = b'llvm_unreachable("Error msg")' - self.check_patching_result(patch, syntax, b'assert(0 && "Error msg")') + self.check_patching_result(patch, syntax, b'CS_ASSERT(0 && "Error msg")') + + def test_llvmdebug(self): + patch = LLVM_DEBUG(0) + syntax = b'LLVM_DEBUG(dbgs() << "Error msg")' + self.check_patching_result(patch, syntax, b"") def test_methodtofunctions(self): patch = MethodToFunction(0) diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py index 2a0a74de1c..26c90f0382 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py @@ -90,8 +90,6 @@ def get_add_cs_detail( op_group_enum = ( self.arch.encode("utf8") + b"_OP_GROUP_" + fcn_id[5:] ) # Remove "print" from function id - if self.arch == "Xtensa": - op_group_enum = op_group_enum.upper() is_template = fcn_def.prev_sibling.type == "template_parameter_list" if b"OpNum" in params: diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/LLVM_DEBUG.py b/suite/auto-sync/src/autosync/cpptranslator/patches/LLVM_DEBUG.py new file mode 100644 index 0000000000..8209135e72 --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/LLVM_DEBUG.py @@ -0,0 +1,36 @@ +# Copyright © 2022 Rot127 +# Copyright © 2024 Billow +# SPDX-License-Identifier: BSD-3 + +from tree_sitter import Node + +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch + + +class LLVM_DEBUG(Patch): + """ + Patch LLVM_DEBUG(dbgs() << "Error msg") + to "" + """ + + def __init__(self, priority: int): + super().__init__(priority) + + def get_search_pattern(self) -> str: + return """ + (call_expression ( + (identifier) @fcn_name (#eq? @fcn_name "LLVM_DEBUG") + (argument_list ( + (binary_expression ( + (call_expression) + (string_literal) @err_msg + )) + )) + )) @llvm_debug""" + + def get_main_capture_name(self) -> str: + return "llvm_debug" + + def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: + return b"" diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/LLVMunreachable.py b/suite/auto-sync/src/autosync/cpptranslator/patches/LLVMunreachable.py index 1bd243a66e..3f695f452f 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/LLVMunreachable.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/LLVMunreachable.py @@ -30,5 +30,5 @@ def get_main_capture_name(self) -> str: def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: err_msg = captures[2][0] err_msg = get_text(src, err_msg.start_byte, err_msg.end_byte).strip(b"()") - res = b"assert(0 && " + err_msg + b")" + res = b"CS_ASSERT(0 && " + err_msg + b")" return res diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py b/suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py index 69403a1d27..4553e1817c 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py @@ -10,8 +10,8 @@ class IsUInt(Patch): """ - Patch isUInt(...) - to isUInt(..., N) + Patch isUInt|isInt(...) + to isUInt|isInt(..., N) """ def __init__(self, priority: int): @@ -21,7 +21,7 @@ def get_search_pattern(self) -> str: return ( "(call_expression" " (template_function" - ' ((identifier) @id (#eq? @id "isUInt"))' + ' ((identifier) @id (#match? @id "isUInt|isInt"))' " ((template_argument_list) @templ_args)" " )" " ((argument_list) @arg_list)" diff --git a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json index ff5b8448af..d1c198cb5f 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json +++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json @@ -2328,77 +2328,125 @@ } }, "XtensaDisassembler.c": { - "\"../../SStream.h\"": { + "\"../../utils.h\"": { "apply_type": "OLD", - "old_hash": "2b45d68382f855f8fdc8a7cf177cda2d4dee75318bab9e1304026375ba05284f", + "old_hash": "bba3ceddc5b6ca88f7f5a17acc4d2545a08e4011ca8224462a64a30eff35e9eb", "new_hash": "", "edit": "" }, - "\"../../cs_priv.h\"": { + "CheckRegister": { "apply_type": "OLD", - "old_hash": "9cf77913cc1ba047983eb15f5e6dce657fb26b09f32757f02de5df2cf4023d87", - "new_hash": "", + "old_hash": "596295adf943c3f7beb2eb2897d51a34f839e0907e13e1df5a3b3f4b203a174b", + "new_hash": "9fdad4704876c8820a8976e2bec1444690bd884ccab181e383666fc7d7f84f0d", "edit": "" }, - "\"XtensaGenInstrInfo.inc\"": { + "DecodeARRegisterClass": { "apply_type": "OLD", - "old_hash": "7dada799dde9a9ea873fe6933799f19a60273bd85d56804c06e7e87b761c973d", - "new_hash": "", + "old_hash": "0c96c29f2eb8b45ba4b68d3f8c4f2df555b547cee3038a3a9617de93ccbfe967", + "new_hash": "7cb44a5bb5cc06edc8437fe201265278602fb87948b8ab93701dd9f33f890a72", "edit": "" }, - "\"priv.h\"": { + "DecodeBR2RegisterClass": { "apply_type": "OLD", - "old_hash": "d09344b441eba2a943ba1323088ec14a8bad410b94e47900e170c51876794892", - "new_hash": "", + "old_hash": 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"6ca58c91fb8b87d0eb7763591edd07ccc9a8b369cfdf4bb806507ff766ab0fb5", "new_hash": "", "edit": "" } diff --git a/suite/cstest/include/test_detail.h b/suite/cstest/include/test_detail.h index fe682f0891..0d82cd51df 100644 --- a/suite/cstest/include/test_detail.h +++ b/suite/cstest/include/test_detail.h @@ -31,6 +31,7 @@ #include "test_detail_wasm.h" #include "test_detail_x86.h" #include "test_detail_m68k.h" +#include "test_detail_xtensa.h" #include "test_compare.h" #include #include @@ -59,6 +60,7 @@ typedef struct { TestDetailWASM *wasm; TestDetailX86 *x86; TestDetailM68K *m68k; + TestDetailXtensa *xtensa; char **regs_read; uint8_t regs_read_count; @@ -145,6 +147,9 @@ static const cyaml_schema_field_t test_detail_mapping_schema[] = { CYAML_FIELD_MAPPING_PTR( "m68k", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, m68k, test_detail_m68k_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "xtensa", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + xtensa, test_detail_xtensa_mapping_schema), CYAML_FIELD_SEQUENCE("regs_read", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, regs_read, &single_string_schema, 0, 255), diff --git a/suite/cstest/include/test_detail_xtensa.h b/suite/cstest/include/test_detail_xtensa.h new file mode 100644 index 0000000000..9e35c82454 --- /dev/null +++ b/suite/cstest/include/test_detail_xtensa.h @@ -0,0 +1,73 @@ +// Copyright © 2024 Rot127 +// Copyright © 2024 Billow +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_XTENSA_H +#define TEST_DETAIL_XTENSA_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + int32_t imm; + char *mem_base; + int32_t mem_disp; +} TestDetailXtensaOp; + +static const cyaml_schema_field_t test_detail_xtensa_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXtensaOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXtensaOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXtensaOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailXtensaOp, imm), + CYAML_FIELD_STRING_PTR( + "mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXtensaOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailXtensaOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_xtensa_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailXtensaOp, + test_detail_xtensa_op_mapping_schema), +}; + +typedef struct { + TestDetailXtensaOp **operands; + uint32_t operands_count; + char *format; +} TestDetailXtensa; + +static const cyaml_schema_field_t test_detail_xtensa_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXtensa, operands, &test_detail_xtensa_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_STRING_PTR("format", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXtensa, format, 0, CYAML_UNLIMITED), + CYAML_FIELD_END +}; + +TestDetailXtensa *test_detail_xtensa_new(); +TestDetailXtensa *test_detail_xtensa_clone(const TestDetailXtensa *detail); +void test_detail_xtensa_free(TestDetailXtensa *detail); + +TestDetailXtensaOp *test_detail_xtensa_op_new(); +TestDetailXtensaOp * +test_detail_xtensa_op_clone(const TestDetailXtensaOp *detail); +void test_detail_xtensa_op_free(TestDetailXtensaOp *detail); + +bool test_expected_xtensa(csh *handle, const cs_xtensa *actual, + const TestDetailXtensa *expected); + +#endif // TEST_DETAIL_XTENSA_H diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h index 9638e08d7c..a61945fed0 100644 --- a/suite/cstest/include/test_mapping.h +++ b/suite/cstest/include/test_mapping.h @@ -169,7 +169,9 @@ static const cs_enum_id_map test_mode_map[] = { { .str = "CS_MODE_TRICORE_162", .val = CS_MODE_TRICORE_162 }, { .str = "CS_MODE_V8", .val = CS_MODE_V8 }, { .str = "CS_MODE_V9", .val = CS_MODE_V9 }, - { .str = "CS_MODE_XTENSA", .val = CS_MODE_XTENSA }, + { .str = "CS_MODE_XTENSA_ESP32", .val = CS_MODE_XTENSA_ESP32 }, + { .str = "CS_MODE_XTENSA_ESP32S2", .val = CS_MODE_XTENSA_ESP32S2 }, + { .str = "CS_MODE_XTENSA_ESP8266", .val = CS_MODE_XTENSA_ESP8266 }, }; static const TestOptionMapEntry test_option_map[] = { @@ -1191,81 +1193,153 @@ static const cs_enum_id_map cs_enum_map[] = { { .str = "SYSTEMZ_INSN_FORM_INSTE", .val = SYSTEMZ_INSN_FORM_INSTE }, { .str = "SYSTEMZ_INSN_FORM_INSTI", .val = SYSTEMZ_INSN_FORM_INSTI }, { .str = "SYSTEMZ_INSN_FORM_INSTIE", .val = SYSTEMZ_INSN_FORM_INSTIE }, - { .str = "SYSTEMZ_INSN_FORM_INSTMII", .val = SYSTEMZ_INSN_FORM_INSTMII }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIA", .val = SYSTEMZ_INSN_FORM_INSTRIA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIB", .val = SYSTEMZ_INSN_FORM_INSTRIB }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIC", .val = SYSTEMZ_INSN_FORM_INSTRIC }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIEA", .val = SYSTEMZ_INSN_FORM_INSTRIEA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIEB", .val = SYSTEMZ_INSN_FORM_INSTRIEB }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIEC", .val = SYSTEMZ_INSN_FORM_INSTRIEC }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIED", .val = SYSTEMZ_INSN_FORM_INSTRIED }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIEE", .val = SYSTEMZ_INSN_FORM_INSTRIEE }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIEF", .val = SYSTEMZ_INSN_FORM_INSTRIEF }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIEG", .val = SYSTEMZ_INSN_FORM_INSTRIEG }, - { .str = "SYSTEMZ_INSN_FORM_INSTRILA", .val = SYSTEMZ_INSN_FORM_INSTRILA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRILB", .val = SYSTEMZ_INSN_FORM_INSTRILB }, - { .str = "SYSTEMZ_INSN_FORM_INSTRILC", .val = SYSTEMZ_INSN_FORM_INSTRILC }, - { .str = "SYSTEMZ_INSN_FORM_INSTRIS", .val = SYSTEMZ_INSN_FORM_INSTRIS }, + { .str = "SYSTEMZ_INSN_FORM_INSTMII", + .val = SYSTEMZ_INSN_FORM_INSTMII }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIA", + .val = SYSTEMZ_INSN_FORM_INSTRIA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIB", + .val = SYSTEMZ_INSN_FORM_INSTRIB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIC", + .val = SYSTEMZ_INSN_FORM_INSTRIC }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEA", + .val = SYSTEMZ_INSN_FORM_INSTRIEA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEB", + .val = SYSTEMZ_INSN_FORM_INSTRIEB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEC", + .val = SYSTEMZ_INSN_FORM_INSTRIEC }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIED", + .val = SYSTEMZ_INSN_FORM_INSTRIED }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEE", + .val = SYSTEMZ_INSN_FORM_INSTRIEE }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEF", + .val = SYSTEMZ_INSN_FORM_INSTRIEF }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEG", + .val = SYSTEMZ_INSN_FORM_INSTRIEG }, + { .str = "SYSTEMZ_INSN_FORM_INSTRILA", + .val = SYSTEMZ_INSN_FORM_INSTRILA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRILB", + .val = SYSTEMZ_INSN_FORM_INSTRILB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRILC", + .val = SYSTEMZ_INSN_FORM_INSTRILC }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIS", + .val = SYSTEMZ_INSN_FORM_INSTRIS }, { .str = "SYSTEMZ_INSN_FORM_INSTRR", .val = SYSTEMZ_INSN_FORM_INSTRR }, - { .str = "SYSTEMZ_INSN_FORM_INSTRRD", .val = SYSTEMZ_INSN_FORM_INSTRRD }, - { .str = "SYSTEMZ_INSN_FORM_INSTRRE", .val = SYSTEMZ_INSN_FORM_INSTRRE }, - { .str = "SYSTEMZ_INSN_FORM_INSTRRFA", .val = SYSTEMZ_INSN_FORM_INSTRRFA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRRFB", .val = SYSTEMZ_INSN_FORM_INSTRRFB }, - { .str = "SYSTEMZ_INSN_FORM_INSTRRFC", .val = SYSTEMZ_INSN_FORM_INSTRRFC }, - { .str = "SYSTEMZ_INSN_FORM_INSTRRFD", .val = SYSTEMZ_INSN_FORM_INSTRRFD }, - { .str = "SYSTEMZ_INSN_FORM_INSTRRFE", .val = SYSTEMZ_INSN_FORM_INSTRRFE }, - { .str = "SYSTEMZ_INSN_FORM_INSTRRS", .val = SYSTEMZ_INSN_FORM_INSTRRS }, - { .str = "SYSTEMZ_INSN_FORM_INSTRSA", .val = SYSTEMZ_INSN_FORM_INSTRSA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRSB", .val = SYSTEMZ_INSN_FORM_INSTRSB }, - { .str = "SYSTEMZ_INSN_FORM_INSTRSI", .val = SYSTEMZ_INSN_FORM_INSTRSI }, - { .str = "SYSTEMZ_INSN_FORM_INSTRSLA", .val = SYSTEMZ_INSN_FORM_INSTRSLA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRSLB", .val = SYSTEMZ_INSN_FORM_INSTRSLB }, - { .str = "SYSTEMZ_INSN_FORM_INSTRSYA", .val = SYSTEMZ_INSN_FORM_INSTRSYA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRSYB", .val = SYSTEMZ_INSN_FORM_INSTRSYB }, - { .str = "SYSTEMZ_INSN_FORM_INSTRXA", .val = SYSTEMZ_INSN_FORM_INSTRXA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRXB", .val = SYSTEMZ_INSN_FORM_INSTRXB }, - { .str = "SYSTEMZ_INSN_FORM_INSTRXE", .val = SYSTEMZ_INSN_FORM_INSTRXE }, - { .str = "SYSTEMZ_INSN_FORM_INSTRXF", .val = SYSTEMZ_INSN_FORM_INSTRXF }, - { .str = "SYSTEMZ_INSN_FORM_INSTRXYA", .val = SYSTEMZ_INSN_FORM_INSTRXYA }, - { .str = "SYSTEMZ_INSN_FORM_INSTRXYB", .val = SYSTEMZ_INSN_FORM_INSTRXYB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRD", + .val = SYSTEMZ_INSN_FORM_INSTRRD }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRE", + .val = SYSTEMZ_INSN_FORM_INSTRRE }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFA", + .val = SYSTEMZ_INSN_FORM_INSTRRFA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFB", + .val = SYSTEMZ_INSN_FORM_INSTRRFB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFC", + .val = SYSTEMZ_INSN_FORM_INSTRRFC }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFD", + .val = SYSTEMZ_INSN_FORM_INSTRRFD }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFE", + .val = SYSTEMZ_INSN_FORM_INSTRRFE }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRS", + .val = SYSTEMZ_INSN_FORM_INSTRRS }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSA", + .val = SYSTEMZ_INSN_FORM_INSTRSA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSB", + .val = SYSTEMZ_INSN_FORM_INSTRSB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSI", + .val = SYSTEMZ_INSN_FORM_INSTRSI }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSLA", + .val = SYSTEMZ_INSN_FORM_INSTRSLA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSLB", + .val = SYSTEMZ_INSN_FORM_INSTRSLB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSYA", + .val = SYSTEMZ_INSN_FORM_INSTRSYA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSYB", + .val = SYSTEMZ_INSN_FORM_INSTRSYB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXA", + .val = SYSTEMZ_INSN_FORM_INSTRXA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXB", + .val = SYSTEMZ_INSN_FORM_INSTRXB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXE", + .val = SYSTEMZ_INSN_FORM_INSTRXE }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXF", + .val = SYSTEMZ_INSN_FORM_INSTRXF }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXYA", + .val = SYSTEMZ_INSN_FORM_INSTRXYA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXYB", + .val = SYSTEMZ_INSN_FORM_INSTRXYB }, { .str = "SYSTEMZ_INSN_FORM_INSTS", .val = SYSTEMZ_INSN_FORM_INSTS }, { .str = "SYSTEMZ_INSN_FORM_INSTSI", .val = SYSTEMZ_INSN_FORM_INSTSI }, - { .str = "SYSTEMZ_INSN_FORM_INSTSIL", .val = SYSTEMZ_INSN_FORM_INSTSIL }, - { .str = "SYSTEMZ_INSN_FORM_INSTSIY", .val = SYSTEMZ_INSN_FORM_INSTSIY }, - { .str = "SYSTEMZ_INSN_FORM_INSTSMI", .val = SYSTEMZ_INSN_FORM_INSTSMI }, - { .str = "SYSTEMZ_INSN_FORM_INSTSSA", .val = SYSTEMZ_INSN_FORM_INSTSSA }, - { .str = "SYSTEMZ_INSN_FORM_INSTSSB", .val = SYSTEMZ_INSN_FORM_INSTSSB }, - { .str = "SYSTEMZ_INSN_FORM_INSTSSC", .val = SYSTEMZ_INSN_FORM_INSTSSC }, - { .str = "SYSTEMZ_INSN_FORM_INSTSSD", .val = SYSTEMZ_INSN_FORM_INSTSSD }, - { .str = "SYSTEMZ_INSN_FORM_INSTSSE", .val = SYSTEMZ_INSN_FORM_INSTSSE }, - { .str = "SYSTEMZ_INSN_FORM_INSTSSF", .val = SYSTEMZ_INSN_FORM_INSTSSF }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRIA", .val = SYSTEMZ_INSN_FORM_INSTVRIA }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRIB", .val = SYSTEMZ_INSN_FORM_INSTVRIB }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRIC", .val = SYSTEMZ_INSN_FORM_INSTVRIC }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRID", .val = SYSTEMZ_INSN_FORM_INSTVRID }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRIE", .val = SYSTEMZ_INSN_FORM_INSTVRIE }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRIF", .val = SYSTEMZ_INSN_FORM_INSTVRIF }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRIG", .val = SYSTEMZ_INSN_FORM_INSTVRIG }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRIH", .val = SYSTEMZ_INSN_FORM_INSTVRIH }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRII", .val = SYSTEMZ_INSN_FORM_INSTVRII }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRA", .val = SYSTEMZ_INSN_FORM_INSTVRRA }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRB", .val = SYSTEMZ_INSN_FORM_INSTVRRB }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRC", .val = SYSTEMZ_INSN_FORM_INSTVRRC }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRD", .val = SYSTEMZ_INSN_FORM_INSTVRRD }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRE", .val = SYSTEMZ_INSN_FORM_INSTVRRE }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRF", .val = SYSTEMZ_INSN_FORM_INSTVRRF }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRG", .val = SYSTEMZ_INSN_FORM_INSTVRRG }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRH", .val = SYSTEMZ_INSN_FORM_INSTVRRH }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRI", .val = SYSTEMZ_INSN_FORM_INSTVRRI }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRJ", .val = SYSTEMZ_INSN_FORM_INSTVRRJ }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRRK", .val = SYSTEMZ_INSN_FORM_INSTVRRK }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRSA", .val = SYSTEMZ_INSN_FORM_INSTVRSA }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRSB", .val = SYSTEMZ_INSN_FORM_INSTVRSB }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRSC", .val = SYSTEMZ_INSN_FORM_INSTVRSC }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRSD", .val = SYSTEMZ_INSN_FORM_INSTVRSD }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRV", .val = SYSTEMZ_INSN_FORM_INSTVRV }, - { .str = "SYSTEMZ_INSN_FORM_INSTVRX", .val = SYSTEMZ_INSN_FORM_INSTVRX }, - { .str = "SYSTEMZ_INSN_FORM_INSTVSI", .val = SYSTEMZ_INSN_FORM_INSTVSI }, + { .str = "SYSTEMZ_INSN_FORM_INSTSIL", + .val = SYSTEMZ_INSN_FORM_INSTSIL }, + { .str = "SYSTEMZ_INSN_FORM_INSTSIY", + .val = SYSTEMZ_INSN_FORM_INSTSIY }, + { .str = "SYSTEMZ_INSN_FORM_INSTSMI", + .val = SYSTEMZ_INSN_FORM_INSTSMI }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSA", + .val = SYSTEMZ_INSN_FORM_INSTSSA }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSB", + .val = SYSTEMZ_INSN_FORM_INSTSSB }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSC", + .val = SYSTEMZ_INSN_FORM_INSTSSC }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSD", + .val = SYSTEMZ_INSN_FORM_INSTSSD }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSE", + .val = SYSTEMZ_INSN_FORM_INSTSSE }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSF", + .val = SYSTEMZ_INSN_FORM_INSTSSF }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIA", + .val = SYSTEMZ_INSN_FORM_INSTVRIA }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIB", + .val = SYSTEMZ_INSN_FORM_INSTVRIB }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIC", + .val = SYSTEMZ_INSN_FORM_INSTVRIC }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRID", + .val = SYSTEMZ_INSN_FORM_INSTVRID }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIE", + .val = SYSTEMZ_INSN_FORM_INSTVRIE }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIF", + .val = SYSTEMZ_INSN_FORM_INSTVRIF }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIG", + .val = SYSTEMZ_INSN_FORM_INSTVRIG }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIH", + .val = SYSTEMZ_INSN_FORM_INSTVRIH }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRII", + .val = SYSTEMZ_INSN_FORM_INSTVRII }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRA", + .val = SYSTEMZ_INSN_FORM_INSTVRRA }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRB", + .val = SYSTEMZ_INSN_FORM_INSTVRRB }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRC", + .val = SYSTEMZ_INSN_FORM_INSTVRRC }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRD", + .val = SYSTEMZ_INSN_FORM_INSTVRRD }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRE", + .val = SYSTEMZ_INSN_FORM_INSTVRRE }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRF", + .val = SYSTEMZ_INSN_FORM_INSTVRRF }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRG", + .val = SYSTEMZ_INSN_FORM_INSTVRRG }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRH", + .val = SYSTEMZ_INSN_FORM_INSTVRRH }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRI", + .val = SYSTEMZ_INSN_FORM_INSTVRRI }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRJ", + .val = SYSTEMZ_INSN_FORM_INSTVRRJ }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRK", + .val = SYSTEMZ_INSN_FORM_INSTVRRK }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRSA", + .val = SYSTEMZ_INSN_FORM_INSTVRSA }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRSB", + .val = SYSTEMZ_INSN_FORM_INSTVRSB }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRSC", + .val = SYSTEMZ_INSN_FORM_INSTVRSC }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRSD", + .val = SYSTEMZ_INSN_FORM_INSTVRSD }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRV", + .val = SYSTEMZ_INSN_FORM_INSTVRV }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRX", + .val = SYSTEMZ_INSN_FORM_INSTVRX }, + { .str = "SYSTEMZ_INSN_FORM_INSTVSI", + .val = SYSTEMZ_INSN_FORM_INSTVSI }, { .str = "SYSTEMZ_OP_IMM", .val = SYSTEMZ_OP_IMM }, { .str = "SYSTEMZ_OP_MEM", .val = SYSTEMZ_OP_MEM }, { .str = "SYSTEMZ_OP_REG", .val = SYSTEMZ_OP_REG }, @@ -1467,6 +1541,24 @@ static const cs_enum_id_map cs_enum_map[] = { { .str = "XCORE_OP_IMM", .val = XCORE_OP_IMM }, { .str = "XCORE_OP_MEM", .val = XCORE_OP_MEM }, { .str = "XCORE_OP_REG", .val = XCORE_OP_REG }, + { .str = "XTENSA_INSN_FORM_AEINST24", + .val = XTENSA_INSN_FORM_AEINST24 }, + { .str = "XTENSA_INSN_FORM_BRI12", .val = XTENSA_INSN_FORM_BRI12 }, + { .str = "XTENSA_INSN_FORM_CALL", .val = XTENSA_INSN_FORM_CALL }, + { .str = "XTENSA_INSN_FORM_CALLX", .val = XTENSA_INSN_FORM_CALLX }, + { .str = "XTENSA_INSN_FORM_EE_INST24", + .val = XTENSA_INSN_FORM_EE_INST24 }, + { .str = "XTENSA_INSN_FORM_RI16", .val = XTENSA_INSN_FORM_RI16 }, + { .str = "XTENSA_INSN_FORM_RI7", .val = XTENSA_INSN_FORM_RI7 }, + { .str = "XTENSA_INSN_FORM_RRI4", .val = XTENSA_INSN_FORM_RRI4 }, + { .str = "XTENSA_INSN_FORM_RRI8", .val = XTENSA_INSN_FORM_RRI8 }, + { .str = "XTENSA_INSN_FORM_RRR", .val = XTENSA_INSN_FORM_RRR }, + { .str = "XTENSA_INSN_FORM_RRRN", .val = XTENSA_INSN_FORM_RRRN }, + { .str = "XTENSA_INSN_FORM_RSR", .val = XTENSA_INSN_FORM_RSR }, + { .str = "XTENSA_OP_IMM", .val = XTENSA_OP_IMM }, + { .str = "XTENSA_OP_L32R", .val = XTENSA_OP_L32R }, + { .str = "XTENSA_OP_MEM", .val = XTENSA_OP_MEM }, + { .str = "XTENSA_OP_REG", .val = XTENSA_OP_REG }, { .str = "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzx", .val = 0xffffff }, // For testing { .str = "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz", diff --git a/suite/cstest/src/test_detail.c b/suite/cstest/src/test_detail.c index f63c38c904..4755dc2273 100644 --- a/suite/cstest/src/test_detail.c +++ b/suite/cstest/src/test_detail.c @@ -127,6 +127,9 @@ TestDetail *test_detail_clone(TestDetail *detail) if (detail->m68k) { clone->m68k = test_detail_m68k_clone(detail->m68k); } + if (detail->xtensa) { + clone->xtensa = test_detail_xtensa_clone(detail->xtensa); + } return clone; } @@ -225,7 +228,9 @@ void test_detail_free(TestDetail *detail) if (detail->m68k) { test_detail_m68k_free(detail->m68k); } - + if (detail->xtensa) { + test_detail_xtensa_free(detail->xtensa); + } cs_mem_free(detail); } @@ -404,5 +409,9 @@ bool test_expected_detail(csh *handle, const cs_insn *insn, return test_expected_m68k(handle, &actual->m68k, expected->m68k); } + if (expected->xtensa) { + return test_expected_xtensa(handle, &actual->xtensa, + expected->xtensa); + } return true; } diff --git a/suite/cstest/src/test_detail_xtensa.c b/suite/cstest/src/test_detail_xtensa.c new file mode 100644 index 0000000000..983829b1da --- /dev/null +++ b/suite/cstest/src/test_detail_xtensa.c @@ -0,0 +1,111 @@ +// Copyright © 2024 Rot127 +// Copyright © 2024 Billow +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include +#include +#include +#include + +TestDetailXtensa *test_detail_xtensa_new() +{ + return cs_mem_calloc(sizeof(TestDetailXtensa), 1); +} + +void test_detail_xtensa_free(TestDetailXtensa *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_xtensa_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->format); + cs_mem_free(detail); +} + +TestDetailXtensa *test_detail_xtensa_clone(const TestDetailXtensa *detail) +{ + TestDetailXtensa *clone = test_detail_xtensa_new(); + clone->format = detail->format ? strdup(detail->format) : NULL; + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailXtensaOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_xtensa_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailXtensaOp *test_detail_xtensa_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailXtensaOp), 1); +} + +TestDetailXtensaOp *test_detail_xtensa_op_clone(const TestDetailXtensaOp *op) +{ + TestDetailXtensaOp *clone = test_detail_xtensa_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_xtensa_op_free(TestDetailXtensaOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op); +} + +bool test_expected_xtensa(csh *handle, const cs_xtensa *actual, + const TestDetailXtensa *expected) +{ + assert(handle && actual && expected); + + compare_enum_ret(actual->format, expected->format, false); + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_xtensa_op *op = &actual->operands[i]; + TestDetailXtensaOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "xtensa op type %" PRId32 " not handled.\n", + op->type); + return false; + case XTENSA_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case XTENSA_OP_L32R: + case XTENSA_OP_IMM: + compare_int32_ret(op->imm, eop->imm, false); + break; + case XTENSA_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_int32_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/test/integration_tests.py b/suite/cstest/test/integration_tests.py index 6ca6d57117..d2354a39cf 100755 --- a/suite/cstest/test/integration_tests.py +++ b/suite/cstest/test/integration_tests.py @@ -5,10 +5,8 @@ # Typing for Python3.8 from __future__ import annotations - import sys import subprocess as sp - from pathlib import Path @@ -34,13 +32,7 @@ def check(cmd: list[str], expected_stdout: str, expected_stderr: str, fail_msg: def run_tests(cmd: str): - p = ( - sp.run(["git", "rev-parse", "--show-toplevel"], check=True, capture_output=True) - .stdout.decode("utf8") - .strip() - ) - path = Path(p).joinpath("suite").joinpath("cstest").joinpath("test") - + path = Path(__file__).parent.resolve() cmd = cmd.split(" ") check( cmd + [f"{path.joinpath('empty_test_file.yaml')}"], diff --git a/suite/fuzz/drivermc.c b/suite/fuzz/drivermc.c index 3f0b7e0405..0eddb43642 100644 --- a/suite/fuzz/drivermc.c +++ b/suite/fuzz/drivermc.c @@ -91,10 +91,12 @@ int main(int argc, char** argv) Data[0] = 24; } else if (strcmp(arch, "CS_ARCH_EVM") == 0 && strcmp(mode, "0") == 0) { Data[0] = 25; - } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA") == 0) { + } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA_ESP32") == 0) { Data[0] = 26; - } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA+CS_MODE_BIG_ENDIAN") == 0) { + } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA_ESP32S2") == 0) { Data[0] = 27; + } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA_ESP8266") == 0) { + Data[0] = 28; } else if (strcmp(arch, "CS_ARCH_BPF") == 0 && strstr(mode, "CS_MODE_BPF_CLASSIC") != NULL) { Data[0] = 29; } else if (strcmp(arch, "CS_ARCH_BPF") == 0 && strstr(mode, "CS_MODE_BPF_EXTENDED") != NULL) { diff --git a/suite/fuzz/fuzz_diff.c b/suite/fuzz/fuzz_diff.c index 20a4c94cb9..674013ce50 100644 --- a/suite/fuzz/fuzz_diff.c +++ b/suite/fuzz/fuzz_diff.c @@ -175,14 +175,20 @@ struct platform platforms[] = { { //item 26 CS_ARCH_XTENSA, - (cs_mode)CS_MODE_XTENSA, - "Xtensa" + (cs_mode)CS_MODE_XTENSA_ESP32, + "Xtensa ESP32" }, { //item 27 CS_ARCH_XTENSA, - (cs_mode)CS_MODE_XTENSA + CS_MODE_BIG_ENDIAN, - "Xtensa (Big-Endian)" + (cs_mode)CS_MODE_XTENSA_ESP32S2, + "Xtensa ESP32S2" + }, + { + //item 28 + CS_ARCH_XTENSA, + (cs_mode)CS_MODE_XTENSA_ESP8266, + "Xtensa ESP8266" }, }; diff --git a/suite/fuzz/fuzz_harness.c b/suite/fuzz/fuzz_harness.c index efd0b1d9b9..2c943fd483 100644 --- a/suite/fuzz/fuzz_harness.c +++ b/suite/fuzz/fuzz_harness.c @@ -119,13 +119,18 @@ int main(int argc, char **argv) }, { CS_ARCH_XTENSA, - (cs_mode)CS_MODE_XTENSA, - "Xtensa" + (cs_mode)CS_MODE_XTENSA_ESP32, + "Xtensa ESP32" }, { CS_ARCH_XTENSA, - (cs_mode)CS_MODE_XTENSA + CS_MODE_BIG_ENDIAN, - "Xtensa (Big-Endian)" + (cs_mode)CS_MODE_XTENSA_ESP32S2, + "Xtensa ESP32S2" + }, + { + CS_ARCH_XTENSA, + (cs_mode)CS_MODE_XTENSA_ESP8266, + "Xtensa ESP8266" }, }; diff --git a/suite/fuzz/platform.c b/suite/fuzz/platform.c index 8cb277e832..d3b679a9ad 100644 --- a/suite/fuzz/platform.c +++ b/suite/fuzz/platform.c @@ -381,15 +381,21 @@ struct platform platforms[] = { }, { CS_ARCH_XTENSA, - CS_MODE_XTENSA, - "XTENSA", - "xtensa" + CS_MODE_XTENSA_ESP32, + "XTENSA ESP32", + "esp32" }, { CS_ARCH_XTENSA, - CS_MODE_XTENSA + CS_MODE_BIG_ENDIAN, - "XTENSA (Big-Endian)", - "xtensabe" + CS_MODE_XTENSA_ESP32S2, + "XTENSA ESP32S2", + "esp32s2" + }, + { + CS_ARCH_XTENSA, + CS_MODE_XTENSA_ESP8266, + "XTENSA ESP8266", + "esp8266" }, // dummy entry to mark the end of this array. // DO NOT DELETE THIS diff --git a/suite/run_tests.py b/suite/run_tests.py new file mode 100644 index 0000000000..b975564235 --- /dev/null +++ b/suite/run_tests.py @@ -0,0 +1,25 @@ +# SPDX-FileCopyrightText: 2024 Antelox +# SPDX-License-Identifier: BSD-3 + +import logging +import subprocess +import sys +from pathlib import Path + +logger = logging.getLogger('tests') +logging.basicConfig(level=logging.INFO) +root_dir = Path(__file__).parent.parent.resolve() +tests = [ + f"{sys.executable} {root_dir}/bindings/python/tests/test_all.py", + f"{sys.executable} {root_dir}/suite/cstest/test/integration_tests.py cstest_py", + f"cstest_py {root_dir}/tests/MC/", + f"cstest_py {root_dir}/tests/details/", + f"cstest_py {root_dir}/tests/issues/", + f"cstest_py {root_dir}/tests/features/", +] + +for test in tests: + logger.info(f'Running {test}') + logger.info("#######################") + subprocess.run(test.split(" "), check=True) + logger.info("-----------------------") diff --git a/tests/MC/Xtensa/l32r.yaml b/tests/MC/Xtensa/l32r.yaml new file mode 100644 index 0000000000..cb1a41d1a1 --- /dev/null +++ b/tests/MC/Xtensa/l32r.yaml @@ -0,0 +1,25 @@ +test_cases: + - input: + bytes: [ 0x01,0x00,0x00 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "l32r a0, . -0x40000" + - input: + bytes: [ 0xf1,0x00,0x00 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "l32r a15, . -0x40000" + - input: + bytes: [ 0x01,0xff,0xff ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "l32r a0, . -0x4" diff --git a/tests/details/xtensa.yaml b/tests/details/xtensa.yaml new file mode 100644 index 0000000000..d0a6ceccad --- /dev/null +++ b/tests/details/xtensa.yaml @@ -0,0 +1,67 @@ +test_cases: + - input: + bytes: [ 0x60, 0x51, 0x60, 0x1a, 0x23 ] + arch: "CS_ARCH_XTENSA" + options: [ CS_OPT_DETAIL ] + expected: + insns: + - asm_text: "abs a5, a6" + details: + xtensa: + format: XTENSA_INSN_FORM_RRR + operands: + - type: XTENSA_OP_REG + reg: a5 + access: CS_AC_WRITE + - type: XTENSA_OP_REG + reg: a6 + access: CS_AC_READ + - asm_text: "add.n a2, a3, a1" + details: + xtensa: + format: XTENSA_INSN_FORM_RRRN + operands: + - type: XTENSA_OP_REG + reg: a2 + access: CS_AC_WRITE + - type: XTENSA_OP_REG + reg: a3 + access: CS_AC_READ + - type: XTENSA_OP_REG + reg: a1 + access: CS_AC_READ + - input: + bytes: [ 0x18, 0x23 ] + arch: "CS_ARCH_XTENSA" + options: [ CS_OPT_DETAIL ] + expected: + insns: + - asm_text: "l32i.n a1, a3, 8" + details: + xtensa: + format: XTENSA_INSN_FORM_RRRN + operands: + - type: XTENSA_OP_REG + reg: a1 + access: CS_AC_WRITE + - type: XTENSA_OP_MEM + mem_base: a3 + mem_disp: 8 + access: CS_AC_READ + - input: + bytes: [ 0x12, 0xaf, 0xff ] + arch: "CS_ARCH_XTENSA" + options: [ CS_OPT_DETAIL ] + expected: + insns: + - asm_text: "movi a1, -1" + details: + xtensa: + format: XTENSA_INSN_FORM_RRI8 + operands: + - type: XTENSA_OP_REG + reg: a1 + access: CS_AC_WRITE + - type: XTENSA_OP_IMM + imm: -1 + access: CS_AC_READ diff --git a/tests/integration/test_litbase.c b/tests/integration/test_litbase.c index 1ce63084c3..b9712982a2 100644 --- a/tests/integration/test_litbase.c +++ b/tests/integration/test_litbase.c @@ -45,7 +45,7 @@ static void test() csh handle; cs_err err; - err = cs_open(CS_ARCH_XTENSA, CS_MODE_XTENSA, &handle); + err = cs_open(CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32, &handle); if (err) { if (cs_support(CS_ARCH_XTENSA)) { printf("Failed on cs_open() with error returned: %u\n", @@ -74,8 +74,8 @@ static void test() 0x100000, 2, &insn); // 2. Now print out the instruction in newly customized setup. - check_insn(insn, "l32r", "a1, . 0xbffff"); - check_insn(insn + 1, "l32r", "a1, . 0xffffb"); + check_insn(insn, "l32r", "a1, . 0xfffbf000"); + check_insn(insn + 1, "l32r", "a1, . 0xffffeffc"); print_insn(insn, count); // Done