From 7a36c58a012495dbcf434aa17396ab65659e8bb4 Mon Sep 17 00:00:00 2001 From: billow Date: Sat, 23 Nov 2024 13:29:23 +0800 Subject: [PATCH] fix xtensa `DecodeMR23RegisterClass` and add tests for `MAC16` instructions --- arch/Xtensa/XtensaDisassembler.c | 19 +------ tests/MC/Xtensa/mac16.s.yaml | 97 ++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 17 deletions(-) create mode 100644 tests/MC/Xtensa/mac16.s.yaml diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c index 0fb216758c..f6172ca60b 100644 --- a/arch/Xtensa/XtensaDisassembler.c +++ b/arch/Xtensa/XtensaDisassembler.c @@ -225,10 +225,10 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - if ((RegNo < 2) || (RegNo > 3)) + if (RegNo >= ARR_SIZE(MR23DecoderTable)) return MCDisassembler_Fail; - unsigned Reg = MR23DecoderTable[RegNo - 2]; + unsigned Reg = MR23DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } @@ -978,21 +978,6 @@ static DecodeStatus readInstructionN(const uint8_t *Bytes, size_t BytesLen, #include "XtensaGenDisassemblerTables.inc" -FieldFromInstruction(fieldFromInstruction_2, uint64_t); -DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint64_t); -DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, - uint64_t); - -FieldFromInstruction(fieldFromInstruction_4, uint64_t); -DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint64_t); -DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, - uint64_t); - -FieldFromInstruction(fieldFromInstruction_6, uint64_t); -DecodeToMCInst(decodeToMCInst_6, fieldFromInstruction_6, uint64_t); -DecodeInstruction(decodeInstruction_6, fieldFromInstruction_6, decodeToMCInst_6, - uint64_t); - static bool hasDensity() { return true; diff --git a/tests/MC/Xtensa/mac16.s.yaml b/tests/MC/Xtensa/mac16.s.yaml new file mode 100644 index 0000000000..d4b9401e4e --- /dev/null +++ b/tests/MC/Xtensa/mac16.s.yaml @@ -0,0 +1,97 @@ +test_cases: + - input: + bytes: [ 0x04,0x01,0x34 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mul.ad.ll a1, m2" + - input: + bytes: [ 0x14,0x02,0x74 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mul.aa.ll a2, a1" + - input: + bytes: [ 0x14,0x00,0x64 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mul.da.ll m0, a1" + - input: + bytes: [ 0x04,0x00,0x24 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mul.dd.ll m0, m2" + - input: + bytes: [ 0x04,0x01,0x38 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mula.ad.ll a1, m2" + - input: + bytes: [ 0x14,0x02,0x78 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mula.aa.ll a2, a1" + - input: + bytes: [ 0x14,0x00,0x68 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mula.da.ll m0, a1" + - input: + bytes: [ 0x04,0x00,0x28 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mula.dd.ll m0, m2" + - input: + bytes: [ 0x14,0x00,0x58 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mula.da.ll.lddec m0, a0, m0, a1" + - input: + bytes: [ 0x14,0x00,0x48 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mula.da.ll.ldinc m0, a0, m0, a1" + - input: + bytes: [ 0x04,0x00,0x18 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mula.dd.ll.lddec m0, a0, m0, m2" + - input: + bytes: [ 0x04,0x00,0x08 ] + arch: "xtensa" + options: [ ] + address: 0x0 + expected: + insns: + - asm_text: "mula.dd.ll.ldinc m0, a0, m0, m2" \ No newline at end of file