From 18714ca180de35361bc82cd18a985c6a1a8be299 Mon Sep 17 00:00:00 2001 From: gsinside <119340018+gsinside@users.noreply.github.com> Date: Sat, 24 Aug 2024 14:34:08 -0700 Subject: [PATCH] Adding Wolf Pack to VeeRwolves branch (#75) Adding support for Agilex 5 premium dev kit --- README.md | 9 + data/agilex5_pack.sdc | 4 + data/agilex5_pack.tcl | 113 ++++++++ data/avant_pack.sdc | 1 + rtl/veerwolf_nospi.v | 525 +++++++++++++++++++++++++++++++++++++ rtl/veerwolf_pack_agilex.v | 59 +++++ rtl/veerwolf_pack_avant.v | 70 +++++ rtl/veerwolf_tile.v | 195 ++++++++++++++ sw/pack_rom.S | 100 +++++++ sw/pack_rom.vh | 15 ++ sw/radiant_pre_build.sh | 26 ++ sw/verilogwriter.py | 142 ++++++++++ sw/wolfpack_gen.py | 53 ++++ tb/pack_tb.cpp | 200 ++++++++++++++ tb/veerwolf_pack_tb.v | 48 ++++ veerwolf-chain.png | Bin 0 -> 19444 bytes veerwolf.core | 144 +++++++++- veerwolves.svg | 4 + 18 files changed, 1707 insertions(+), 1 deletion(-) create mode 100755 data/agilex5_pack.sdc create mode 100755 data/agilex5_pack.tcl create mode 100755 data/avant_pack.sdc create mode 100755 rtl/veerwolf_nospi.v create mode 100755 rtl/veerwolf_pack_agilex.v create mode 100755 rtl/veerwolf_pack_avant.v create mode 100755 rtl/veerwolf_tile.v create mode 100755 sw/pack_rom.S create mode 100755 sw/pack_rom.vh create mode 100755 sw/radiant_pre_build.sh create mode 100755 sw/verilogwriter.py create mode 100755 sw/wolfpack_gen.py create mode 100755 tb/pack_tb.cpp create mode 100755 tb/veerwolf_pack_tb.v create mode 100755 veerwolf-chain.png create mode 100755 veerwolves.svg diff --git a/README.md b/README.md index fd785bb..758eb7d 100644 --- a/README.md +++ b/README.md @@ -7,6 +7,15 @@ This can be used to run the [RISC-V compliance tests](https://github.com/riscv/r This project was previously called SweRVolf. The last released version using the old name is v0.7.5 +VeeRwolves +========== + +![](veerwolves.svg) + +VeeRwolves is a pack of VeeRwolf cores in a daisy-chain configuration primarily intended for comparing the capacity of FPGAs. The cores self contained and run out of ROM with GPIO and UART peripherals. The UART and GPIO outputs from each core are passed to the next in a daisy-chain fashion. The ROM code reads the UART and GPIO inputs, increments the value, and repeats the incremented value on its output so that the final output is the input value plus the number of cores. + +![](veerwolf-chain.png) + # Structure To ease portability, the SoC consists of a portable technology-agnostic core with target-specific wrappers. This chapter describes the functionality of the core and the technology-specific targets. diff --git a/data/agilex5_pack.sdc b/data/agilex5_pack.sdc new file mode 100755 index 0000000..dc58be2 --- /dev/null +++ b/data/agilex5_pack.sdc @@ -0,0 +1,4 @@ +create_clock -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; + +# main system clock (25 Mhz) +create_generated_clock -name "clk25MHz" -multiply_by 8 -divide_by 32 -source [get_ports {clk}] [get_nets {clk_gen|o_clk_pll}] diff --git a/data/agilex5_pack.tcl b/data/agilex5_pack.tcl new file mode 100755 index 0000000..5c85cef --- /dev/null +++ b/data/agilex5_pack.tcl @@ -0,0 +1,113 @@ +set_global_assignment -name VERILOG_CU_MODE MFCU +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" +* +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation + +set_global_assignment -name GENERATE_COMPRESSED_SOF ON +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +set_global_assignment -name USE_CONF_DONE SDM_IO12 +set_global_assignment -name USE_HPS_COLD_RESET SDM_IO7 +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ +set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL + +set_global_assignment -name ERROR_ON_WARNINGS_PARSING_SDC_ON_RTL_CONSTRAINTS ON +set_global_assignment -name ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS ON +set_global_assignment -name RTL_SDC_FILE src/veerwolf_0.7.5/data/agilex5.sdc + +# Clock +set_location_assignment PIN_D8 -to clk -comment IOBANK_6C +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk -entity veerwolf_agilex + +# Reset PB SW11 HPS_COLD_RESETn Bank 5B 3.3V +set_location_assignment PIN_BM109 -to rstn -comment IOBANK_5B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rstn -entity veerwolf_agilex + +# UART RX +set_location_assignment PIN_CJ2 -to i_uart_rx -comment IOBANK_6B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_uart_rx -entity veerwolf_agilex + +# UART TX +set_location_assignment PIN_CK4 -to o_uart_tx -comment IOBANK_6B +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to o_uart_tx -entity veerwolf_agilex + +# GPIO (inputs) +# User PB Bank 6A 3.3V +set_location_assignment PIN_BK31 -to i_sw[0] -comment IOBANK_6A +set_location_assignment PIN_BP22 -to i_sw[1] -comment IOBANK_6A +set_location_assignment PIN_BK28 -to i_sw[2] -comment IOBANK_6A +set_location_assignment PIN_BR22 -to i_sw[3] -comment IOBANK_6A +# User SW Bank 6A 3.3V +set_location_assignment PIN_CH12 -to i_sw[4] -comment IOBANK_6A +set_location_assignment PIN_BU22 -to i_sw[5] -comment IOBANK_6A +set_location_assignment PIN_BW19 -to i_sw[6] -comment IOBANK_6A +set_location_assignment PIN_BH28 -to i_sw[7] -comment IOBANK_6A +# MAX SPARE Bank 5A 3.3V +set_location_assignment PIN_CD134 -to i_sw[8] -comment IOBANK_5A +set_location_assignment PIN_CD135 -to i_sw[9] -comment IOBANK_5A +set_location_assignment PIN_CG134 -to i_sw[10] -comment IOBANK_5A +set_location_assignment PIN_CH132 -to i_sw[11] -comment IOBANK_5A +# HSIO SW24 Bank 2AT 1.1V +set_location_assignment PIN_BE93 -to i_sw[12] -comment IOBANK_2A_T +set_location_assignment PIN_BE79 -to i_sw[13] -comment IOBANK_2A_T +set_location_assignment PIN_BF83 -to i_sw[14] -comment IOBANK_2A_T +set_location_assignment PIN_BE83 -to i_sw[15] -comment IOBANK_2A_T + +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[0] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[1] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[2] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[3] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[4] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[5] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[6] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[7] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[8] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[9] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[10] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i_sw[11] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.1-V" -to i_sw[12] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.1-V" -to i_sw[13] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.1-V" -to i_sw[14] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.1-V" -to i_sw[15] -entity veerwolf_agilex + + +# GPIO (outputs) +# User LED Bank 2AT 1.1V +set_location_assignment PIN_BM59 -to o_led[0] -comment IOBANK_2A_T +set_location_assignment PIN_BH59 -to o_led[1] -comment IOBANK_2A_T +set_location_assignment PIN_BH62 -to o_led[2] -comment IOBANK_2A_T +set_location_assignment PIN_BK59 -to o_led[3] -comment IOBANK_2A_T +# FMC LA Bank 3BT 1.2V +set_location_assignment PIN_B42 -to o_led[4] -comment IOBANK_3B_B +set_location_assignment PIN_A45 -to o_led[5] -comment IOBANK_3B_B +set_location_assignment PIN_A48 -to o_led[6] -comment IOBANK_3B_B +set_location_assignment PIN_B45 -to o_led[7] -comment IOBANK_3B_B +set_location_assignment PIN_A51 -to o_led[8] -comment IOBANK_3B_B +set_location_assignment PIN_B51 -to o_led[9] -comment IOBANK_3B_B +set_location_assignment PIN_B54 -to o_led[10] -comment IOBANK_3B_B +set_location_assignment PIN_A54 -to o_led[11] -comment IOBANK_3B_B +set_location_assignment PIN_B60 -to o_led[12] -comment IOBANK_3B_B +set_location_assignment PIN_A63 -to o_led[13] -comment IOBANK_3B_B +set_location_assignment PIN_A60 -to o_led[14] -comment IOBANK_3B_B +set_location_assignment PIN_B56 -to o_led[15] -comment IOBANK_3B_B + +set_instance_assignment -name IO_STANDARD "1.1-V" -to o_led[0] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.1-V" -to o_led[1] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.1-V" -to o_led[2] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.1-V" -to o_led[3] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[8] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[9] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[10] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[11] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[12] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[13] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[14] -entity veerwolf_agilex +set_instance_assignment -name IO_STANDARD "1.2-V" -to o_led[15] -entity veerwolf_agilex \ No newline at end of file diff --git a/data/avant_pack.sdc b/data/avant_pack.sdc new file mode 100755 index 0000000..d910089 --- /dev/null +++ b/data/avant_pack.sdc @@ -0,0 +1 @@ +create_clock -name {Core Clock} -period 80.0 [get_nets clk] diff --git a/rtl/veerwolf_nospi.v b/rtl/veerwolf_nospi.v new file mode 100755 index 0000000..fd26631 --- /dev/null +++ b/rtl/veerwolf_nospi.v @@ -0,0 +1,525 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019-2020 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//******************************************************************************** +// $Id$ +// +// Function: VeeRwolf tech-agnostic toplevel +// Comments: +// +//******************************************************************************** + +`default_nettype none +module veerwolf_nospi + #(parameter bootrom_file = "", + parameter [0:0] insn_trace = 1'b0, + parameter clk_freq_hz = 0) + (input wire clk, + input wire rstn, + input wire dmi_reg_en, + input wire [6:0] dmi_reg_addr, + input wire dmi_reg_wr_en, + input wire [31:0] dmi_reg_wdata, + output wire [31:0] dmi_reg_rdata, + input wire dmi_hard_reset, + input wire i_uart_rx, + output wire o_uart_tx, + output wire [5:0] o_ram_awid, + output wire [31:0] o_ram_awaddr, + output wire [7:0] o_ram_awlen, + output wire [2:0] o_ram_awsize, + output wire [1:0] o_ram_awburst, + output wire o_ram_awlock, + output wire [3:0] o_ram_awcache, + output wire [2:0] o_ram_awprot, + output wire [3:0] o_ram_awregion, + output wire [3:0] o_ram_awqos, + output wire o_ram_awvalid, + input wire i_ram_awready, + output wire [5:0] o_ram_arid, + output wire [31:0] o_ram_araddr, + output wire [7:0] o_ram_arlen, + output wire [2:0] o_ram_arsize, + output wire [1:0] o_ram_arburst, + output wire o_ram_arlock, + output wire [3:0] o_ram_arcache, + output wire [2:0] o_ram_arprot, + output wire [3:0] o_ram_arregion, + output wire [3:0] o_ram_arqos, + output wire o_ram_arvalid, + input wire i_ram_arready, + output wire [63:0] o_ram_wdata, + output wire [7:0] o_ram_wstrb, + output wire o_ram_wlast, + output wire o_ram_wvalid, + input wire i_ram_wready, + input wire [5:0] i_ram_bid, + input wire [1:0] i_ram_bresp, + input wire i_ram_bvalid, + output wire o_ram_bready, + input wire [5:0] i_ram_rid, + input wire [63:0] i_ram_rdata, + input wire [1:0] i_ram_rresp, + input wire i_ram_rlast, + input wire i_ram_rvalid, + output wire o_ram_rready, + input wire i_ram_init_done, + input wire i_ram_init_error, + input wire [63:0] i_gpio, + output wire [63:0] o_gpio); + + localparam BOOTROM_SIZE = 32'h1000; + + wire rst_n = rstn; + wire timer_irq; + wire uart_irq; + wire sw_irq4; + wire sw_irq3; + wire nmi_int; + + wire [31:0] nmi_vec; + +`include "axi_intercon.vh" + + assign o_ram_awid = ram_awid; + assign o_ram_awaddr = ram_awaddr; + assign o_ram_awlen = ram_awlen; + assign o_ram_awsize = ram_awsize; + assign o_ram_awburst = ram_awburst; + assign o_ram_awlock = ram_awlock; + assign o_ram_awcache = ram_awcache; + assign o_ram_awprot = ram_awprot; + assign o_ram_awregion = ram_awregion; + assign o_ram_awqos = ram_awqos; + assign o_ram_awvalid = ram_awvalid; + assign ram_awready = i_ram_awready; + assign o_ram_arid = ram_arid; + assign o_ram_araddr = ram_araddr; + assign o_ram_arlen = ram_arlen; + assign o_ram_arsize = ram_arsize; + assign o_ram_arburst = ram_arburst; + assign o_ram_arlock = ram_arlock; + assign o_ram_arcache = ram_arcache; + assign o_ram_arprot = ram_arprot; + assign o_ram_arregion = ram_arregion; + assign o_ram_arqos = ram_arqos; + assign o_ram_arvalid = ram_arvalid; + assign ram_arready = i_ram_arready; + assign o_ram_wdata = ram_wdata; + assign o_ram_wstrb = ram_wstrb; + assign o_ram_wlast = ram_wlast; + assign o_ram_wvalid = ram_wvalid; + assign ram_wready = i_ram_wready; + assign ram_bid = i_ram_bid; + assign ram_bresp = i_ram_bresp; + assign ram_bvalid = i_ram_bvalid; + assign o_ram_bready = ram_bready; + assign ram_rid = i_ram_rid; + assign ram_rdata = i_ram_rdata; + assign ram_rresp = i_ram_rresp; + assign ram_rlast = i_ram_rlast; + assign ram_rvalid = i_ram_rvalid; + assign o_ram_rready = ram_rready; + + wire wb_clk = clk; + wire wb_rst = ~rst_n; + +`include "wb_intercon.vh" + + wire [15:2] wb_adr; + + assign wb_io_adr = {16'd0,wb_adr,2'b00}; + assign wb_io_cti = 3'b000; + assign wb_io_bte = 2'b00; + + axi2wb + #(.AW (16), + .IW (6)) + axi2wb + ( + .i_clk (clk), + .i_rst (~rst_n), + .o_wb_adr (wb_adr), + .o_wb_dat (wb_io_dat), + .o_wb_sel (wb_io_sel), + .o_wb_we (wb_io_we), + .o_wb_cyc (wb_io_cyc), + .o_wb_stb (wb_io_stb), + .i_wb_rdt (wb_io_rdt), + .i_wb_ack (wb_io_ack), + .i_wb_err (wb_io_err), + + .i_awaddr (io_awaddr[15:0]), + .i_awid (io_awid), + .i_awvalid (io_awvalid), + .o_awready (io_awready), + + .i_araddr (io_araddr[15:0]), + .i_arid (io_arid), + .i_arvalid (io_arvalid), + .o_arready (io_arready), + + .i_wdata (io_wdata), + .i_wstrb (io_wstrb), + .i_wvalid (io_wvalid), + .o_wready (io_wready), + + .o_bid (io_bid), + .o_bresp (io_bresp), + .o_bvalid (io_bvalid), + .i_bready (io_bready), + + .o_rdata (io_rdata), + .o_rid (io_rid), + .o_rresp (io_rresp), + .o_rlast (io_rlast), + .o_rvalid (io_rvalid), + .i_rready (io_rready)); + + wb_mem_wrapper + #(.MEM_SIZE (BOOTROM_SIZE), + .INIT_FILE (bootrom_file)) + bootrom + (.i_clk (wb_clk), + .i_rst (wb_rst), + .i_wb_adr (wb_rom_adr[$clog2(BOOTROM_SIZE)-1:2]), + .i_wb_dat (wb_rom_dat), + .i_wb_sel (wb_rom_sel), + .i_wb_we (wb_rom_we), + .i_wb_cyc (wb_rom_cyc), + .i_wb_stb (wb_rom_stb), + .o_wb_rdt (wb_rom_rdt), + .o_wb_ack (wb_rom_ack)); + + assign wb_rom_err = 1'b0; + assign wb_rom_rty = 1'b0; + + veerwolf_syscon + #(.clk_freq_hz (clk_freq_hz)) + syscon + (.i_clk (clk), + .i_rst (wb_rst), + + .i_gpio (i_gpio), + .o_gpio (o_gpio), + .o_timer_irq (timer_irq), + .o_sw_irq3 (sw_irq3), + .o_sw_irq4 (sw_irq4), + .i_ram_init_done (i_ram_init_done), + .i_ram_init_error (i_ram_init_error), + .o_nmi_vec (nmi_vec), + .o_nmi_int (nmi_int), + + .i_wb_adr (wb_sys_adr[5:0]), + .i_wb_dat (wb_sys_dat), + .i_wb_sel (wb_sys_sel), + .i_wb_we (wb_sys_we), + .i_wb_cyc (wb_sys_cyc), + .i_wb_stb (wb_sys_stb), + .o_wb_rdt (wb_sys_rdt), + .o_wb_ack (wb_sys_ack)); + + assign wb_sys_err = 1'b0; + assign wb_sys_rty = 1'b0; + + wire [7:0] uart_rdt; + assign wb_uart_rdt = {24'd0, uart_rdt}; + assign wb_uart_err = 1'b0; + assign wb_uart_rty = 1'b0; + + uart_top uart16550_0 + (// Wishbone slave interface + .wb_clk_i (clk), + .wb_rst_i (~rst_n), + .wb_adr_i (wb_uart_adr[4:2]), + .wb_dat_i (wb_uart_dat[7:0]), + .wb_we_i (wb_uart_we), + .wb_cyc_i (wb_uart_cyc), + .wb_stb_i (wb_uart_stb), + .wb_sel_i (4'b0), // Not used in 8-bit mode + .wb_dat_o (uart_rdt), + .wb_ack_o (wb_uart_ack), + + // Outputs + .int_o (uart_irq), + .stx_pad_o (o_uart_tx), + .rts_pad_o (), + .dtr_pad_o (), + + // Inputs + .srx_pad_i (i_uart_rx), + .cts_pad_i (1'b0), + .dsr_pad_i (1'b0), + .ri_pad_i (1'b0), + .dcd_pad_i (1'b0)); + + wire [2:0] valid_ip; + wire [63:0] address_ip; + generate + if (insn_trace) begin + + integer tf; + + initial tf = $fopen("trace.bin", "wb"); + + always @(posedge clk) begin + if (valid_ip[0]) $fwrite(tf, "%u", address_ip[31:0]); + if (valid_ip[1]) $fwrite(tf, "%u", address_ip[63:32]); + end + end + endgenerate + + /* There is currently no nice way to ensure consistency between + the ID width specified in the VeeR config and the width specified + when generating the AXI interconnect. The interconnect is sized + for the worst case value (4), so we explicitly resize the ID signals + to this. + */ + + wire [`RV_LSU_BUS_TAG-1:0] lsu_awid_int; + wire [`RV_LSU_BUS_TAG-1:0] lsu_arid_int; + wire [`RV_LSU_BUS_TAG-1:0] lsu_bid_int; + wire [`RV_LSU_BUS_TAG-1:0] lsu_rid_int; + + assign lsu_awid = 4'(lsu_awid_int); + assign lsu_arid = 4'(lsu_arid_int); + assign lsu_bid_int = lsu_bid[`RV_LSU_BUS_TAG-1:0]; + assign lsu_rid_int = lsu_rid[`RV_LSU_BUS_TAG-1:0]; + + veer_wrapper_dmi rvtop + ( + .clk (clk), + .rst_l (rstn), + .dbg_rst_l (rstn), + .rst_vec (31'h40000000), + .nmi_int (nmi_int), + .nmi_vec (nmi_vec[31:1]), + + .trace_rv_i_insn_ip (), + .trace_rv_i_address_ip (address_ip), + .trace_rv_i_valid_ip (valid_ip), + .trace_rv_i_exception_ip (), + .trace_rv_i_ecause_ip (), + .trace_rv_i_interrupt_ip (), + .trace_rv_i_tval_ip (), + + // Bus signals + //-------------------------- LSU AXI signals-------------------------- + .lsu_axi_awvalid (lsu_awvalid), + .lsu_axi_awready (lsu_awready), + .lsu_axi_awid (lsu_awid_int), + .lsu_axi_awaddr (lsu_awaddr ), + .lsu_axi_awregion (lsu_awregion), + .lsu_axi_awlen (lsu_awlen ), + .lsu_axi_awsize (lsu_awsize ), + .lsu_axi_awburst (lsu_awburst), + .lsu_axi_awlock (lsu_awlock ), + .lsu_axi_awcache (lsu_awcache), + .lsu_axi_awprot (lsu_awprot ), + .lsu_axi_awqos (lsu_awqos ), + + .lsu_axi_wvalid (lsu_wvalid), + .lsu_axi_wready (lsu_wready), + .lsu_axi_wdata (lsu_wdata), + .lsu_axi_wstrb (lsu_wstrb), + .lsu_axi_wlast (lsu_wlast), + + .lsu_axi_bvalid (lsu_bvalid), + .lsu_axi_bready (lsu_bready), + .lsu_axi_bresp (lsu_bresp ), + .lsu_axi_bid (lsu_bid_int), + + .lsu_axi_arvalid (lsu_arvalid ), + .lsu_axi_arready (lsu_arready ), + .lsu_axi_arid (lsu_arid_int), + .lsu_axi_araddr (lsu_araddr ), + .lsu_axi_arregion (lsu_arregion), + .lsu_axi_arlen (lsu_arlen ), + .lsu_axi_arsize (lsu_arsize ), + .lsu_axi_arburst (lsu_arburst ), + .lsu_axi_arlock (lsu_arlock ), + .lsu_axi_arcache (lsu_arcache ), + .lsu_axi_arprot (lsu_arprot ), + .lsu_axi_arqos (lsu_arqos ), + + .lsu_axi_rvalid (lsu_rvalid), + .lsu_axi_rready (lsu_rready), + .lsu_axi_rid (lsu_rid_int), + .lsu_axi_rdata (lsu_rdata ), + .lsu_axi_rresp (lsu_rresp ), + .lsu_axi_rlast (lsu_rlast ), + + //-------------------------- IFU AXI signals-------------------------- + .ifu_axi_awvalid (), + .ifu_axi_awready (1'b0), + .ifu_axi_awid (), + .ifu_axi_awaddr (), + .ifu_axi_awregion (), + .ifu_axi_awlen (), + .ifu_axi_awsize (), + .ifu_axi_awburst (), + .ifu_axi_awlock (), + .ifu_axi_awcache (), + .ifu_axi_awprot (), + .ifu_axi_awqos (), + + .ifu_axi_wvalid (), + .ifu_axi_wready (1'b0), + .ifu_axi_wdata (), + .ifu_axi_wstrb (), + .ifu_axi_wlast (), + + .ifu_axi_bvalid (1'b0), + .ifu_axi_bready (), + .ifu_axi_bresp (2'b00), + .ifu_axi_bid (3'd0), + + .ifu_axi_arvalid (ifu_arvalid ), + .ifu_axi_arready (ifu_arready ), + .ifu_axi_arid (ifu_arid ), + .ifu_axi_araddr (ifu_araddr ), + .ifu_axi_arregion (ifu_arregion), + .ifu_axi_arlen (ifu_arlen ), + .ifu_axi_arsize (ifu_arsize ), + .ifu_axi_arburst (ifu_arburst ), + .ifu_axi_arlock (ifu_arlock ), + .ifu_axi_arcache (ifu_arcache ), + .ifu_axi_arprot (ifu_arprot ), + .ifu_axi_arqos (ifu_arqos ), + + .ifu_axi_rvalid (ifu_rvalid), + .ifu_axi_rready (ifu_rready), + .ifu_axi_rid (ifu_rid ), + .ifu_axi_rdata (ifu_rdata ), + .ifu_axi_rresp (ifu_rresp ), + .ifu_axi_rlast (ifu_rlast ), + + //-------------------------- SB AXI signals------------------------- + .sb_axi_awvalid (sb_awvalid ), + .sb_axi_awready (sb_awready ), + .sb_axi_awid (sb_awid ), + .sb_axi_awaddr (sb_awaddr ), + .sb_axi_awregion (sb_awregion), + .sb_axi_awlen (sb_awlen ), + .sb_axi_awsize (sb_awsize ), + .sb_axi_awburst (sb_awburst ), + .sb_axi_awlock (sb_awlock ), + .sb_axi_awcache (sb_awcache ), + .sb_axi_awprot (sb_awprot ), + .sb_axi_awqos (sb_awqos ), + .sb_axi_wvalid (sb_wvalid ), + .sb_axi_wready (sb_wready ), + .sb_axi_wdata (sb_wdata ), + .sb_axi_wstrb (sb_wstrb ), + .sb_axi_wlast (sb_wlast ), + .sb_axi_bvalid (sb_bvalid ), + .sb_axi_bready (sb_bready ), + .sb_axi_bresp (sb_bresp ), + .sb_axi_bid (sb_bid ), + .sb_axi_arvalid (sb_arvalid ), + .sb_axi_arready (sb_arready ), + .sb_axi_arid (sb_arid ), + .sb_axi_araddr (sb_araddr ), + .sb_axi_arregion (sb_arregion), + .sb_axi_arlen (sb_arlen ), + .sb_axi_arsize (sb_arsize ), + .sb_axi_arburst (sb_arburst ), + .sb_axi_arlock (sb_arlock ), + .sb_axi_arcache (sb_arcache ), + .sb_axi_arprot (sb_arprot ), + .sb_axi_arqos (sb_arqos ), + .sb_axi_rvalid (sb_rvalid ), + .sb_axi_rready (sb_rready ), + .sb_axi_rid (sb_rid ), + .sb_axi_rdata (sb_rdata ), + .sb_axi_rresp (sb_rresp ), + .sb_axi_rlast (sb_rlast ), + + //-------------------------- DMA AXI signals-------------------------- + .dma_axi_awvalid (1'b0), + .dma_axi_awready (), + .dma_axi_awid (`RV_DMA_BUS_TAG'd0), + .dma_axi_awaddr (32'd0), + .dma_axi_awsize (3'd0), + .dma_axi_awprot (3'd0), + .dma_axi_awlen (8'd0), + .dma_axi_awburst (2'd0), + + .dma_axi_wvalid (1'b0), + .dma_axi_wready (), + .dma_axi_wdata (64'd0), + .dma_axi_wstrb (8'd0), + .dma_axi_wlast (1'b0), + + .dma_axi_bvalid (), + .dma_axi_bready (1'b0), + .dma_axi_bresp (), + .dma_axi_bid (), + + .dma_axi_arvalid (1'b0), + .dma_axi_arready (), + .dma_axi_arid (`RV_DMA_BUS_TAG'd0), + .dma_axi_araddr (32'd0), + .dma_axi_arsize (3'd0), + .dma_axi_arprot (3'd0), + .dma_axi_arlen (8'd0), + .dma_axi_arburst (2'd0), + + .dma_axi_rvalid (), + .dma_axi_rready (1'b0), + .dma_axi_rid (), + .dma_axi_rdata (), + .dma_axi_rresp (), + .dma_axi_rlast (), + + // clk ratio signals + .lsu_bus_clk_en (1'b1), + .ifu_bus_clk_en (1'b1), + .dbg_bus_clk_en (1'b1), + .dma_bus_clk_en (1'b1), + + .timer_int (timer_irq), + .extintsrc_req ({4'd0, sw_irq4, sw_irq3, 1'b0, uart_irq}), + + .dec_tlu_perfcnt0 (), + .dec_tlu_perfcnt1 (), + .dec_tlu_perfcnt2 (), + .dec_tlu_perfcnt3 (), + + .dmi_reg_rdata (dmi_reg_rdata), + .dmi_reg_wdata (dmi_reg_wdata), + .dmi_reg_addr (dmi_reg_addr), + .dmi_reg_en (dmi_reg_en), + .dmi_reg_wr_en (dmi_reg_wr_en), + .dmi_hard_reset (dmi_hard_reset), + + .mpc_debug_halt_req (1'b0), + .mpc_debug_run_req (1'b0), + .mpc_reset_run_req (1'b1), + .mpc_debug_halt_ack (), + .mpc_debug_run_ack (), + .debug_brkpt_status (), + + .i_cpu_halt_req (1'b0), + .o_cpu_halt_ack (), + .o_cpu_halt_status (), + .o_debug_mode_status (), + .i_cpu_run_req (1'b0), + .o_cpu_run_ack (), + + .scan_mode (1'b0), + .mbist_mode (1'b0)); + +endmodule diff --git a/rtl/veerwolf_pack_agilex.v b/rtl/veerwolf_pack_agilex.v new file mode 100755 index 0000000..865db4c --- /dev/null +++ b/rtl/veerwolf_pack_agilex.v @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//******************************************************************************** +// $Id$ +// +// Function: VeeRwolf toplevel for Intel Agilex 5 +// Comments: +// +//******************************************************************************** + +`default_nettype none +module veerwolf_pack_agilex + #(parameter bootrom_file = "pack_rom.vh", + parameter cpu_type = "EL2") + (input wire clk, + input wire rstn, + input wire i_uart_rx, + output wire o_uart_tx, + input wire [15:0] i_sw, + output reg [15:0] o_led); + + wire [63:0] gpio_out; + reg [15:0] led_int_r; + + wire clk_core; + wire rst_core; + + clk_gen_agilex + #(.CPU_TYPE (cpu_type)) + clk_gen + (.i_clk (clk), + .i_rst (~rstn), + .o_clk_core (clk_core), + .o_rst_core (rst_core)); + + veerwolf_pack + #(.pack_code (bootrom_file)) + veerwolfs + (.clk_core (clk_core), + .rst_core (rst_core), + .i_uart_rx (i_uart_rx), + .o_uart_tx (o_uart_tx), + .i_sw (i_sw), + .o_led (o_led)); + +endmodule diff --git a/rtl/veerwolf_pack_avant.v b/rtl/veerwolf_pack_avant.v new file mode 100755 index 0000000..609bc61 --- /dev/null +++ b/rtl/veerwolf_pack_avant.v @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//******************************************************************************** +// $Id$ +// +// Function: VeeRwolf toplevel for Lattice Avant E-Series +// Comments: +// +//******************************************************************************** + +`default_nettype none +module veerwolf_pack_avant + #(parameter bootrom_file = "pack_rom.vh", + parameter cpu_type = "EL2") + (input wire clk, + input wire rstn, + input wire i_uart_rx, + output wire o_uart_tx, + input wire [15:0] i_sw, + output reg [15:0] o_led); + + wire [63:0] gpio_out; + reg [15:0] led_int_r; + + wire clk_core; + wire rst_core; + + reg rst_reg1; + reg rst_reg2; + + assign rst_core = rst_reg2; + assign clk_core = clk; + + // ================================================================ + // Synchronize Reset + // ================================================================ + always @(posedge clk) begin + if (!rstn) begin + rst_reg1 <= 1'b1; + rst_reg2 <= 1'b1; + end else begin + rst_reg1 <= 1'b0; + rst_reg2 <= rst_reg1; + end + end + + veerwolf_pack + #(.pack_code (bootrom_file)) + veerwolfs + (.clk_core (clk_core), + .rst_core (rst_core), + .i_uart_rx (i_uart_rx), + .o_uart_tx (o_uart_tx), + .i_sw (i_sw), + .o_led (o_led)); + +endmodule diff --git a/rtl/veerwolf_tile.v b/rtl/veerwolf_tile.v new file mode 100755 index 0000000..61de6a6 --- /dev/null +++ b/rtl/veerwolf_tile.v @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//******************************************************************************** +// $Id$ +// +// Function: VeeRwolf processor core with memory board +// Comments: +// +//******************************************************************************** + +`default_nettype none +module veerwolf_tile + #(parameter bootrom_file = "bootloader.vh", + parameter cpu_type = "EH1") + (input wire clk_core, + input wire rst_core, + input wire i_uart_rx, + output wire o_uart_tx, + input wire [15:0] i_sw, + output reg [15:0] o_led); + + wire [63:0] gpio_out; + reg [15:0] led_int_r; + + reg [15:0] sw_r; + reg [15:0] sw_2r; + + localparam RAM_SIZE = 32'h10000; + + wire [5:0] ram_awid; + wire [31:0] ram_awaddr; + wire [7:0] ram_awlen; + wire [2:0] ram_awsize; + wire [1:0] ram_awburst; + wire ram_awlock; + wire [3:0] ram_awcache; + wire [2:0] ram_awprot; + wire [3:0] ram_awregion; + wire [3:0] ram_awqos; + wire ram_awvalid; + wire ram_awready; + wire [5:0] ram_arid; + wire [31:0] ram_araddr; + wire [7:0] ram_arlen; + wire [2:0] ram_arsize; + wire [1:0] ram_arburst; + wire ram_arlock; + wire [3:0] ram_arcache; + wire [2:0] ram_arprot; + wire [3:0] ram_arregion; + wire [3:0] ram_arqos; + wire ram_arvalid; + wire ram_arready; + wire [63:0] ram_wdata; + wire [7:0] ram_wstrb; + wire ram_wlast; + wire ram_wvalid; + wire ram_wready; + wire [5:0] ram_bid; + wire [1:0] ram_bresp; + wire ram_bvalid; + wire ram_bready; + wire [5:0] ram_rid; + wire [63:0] ram_rdata; + wire [1:0] ram_rresp; + wire ram_rlast; + wire ram_rvalid; + wire ram_rready; + + axi_ram + #(.DATA_WIDTH (64), + .ADDR_WIDTH ($clog2(RAM_SIZE)), + .ID_WIDTH (`RV_LSU_BUS_TAG+3)) + ram + (.clk (clk_core), + .rst (rst_core), + .s_axi_awid (ram_awid), + .s_axi_awaddr (ram_awaddr[$clog2(RAM_SIZE)-1:0]), + .s_axi_awlen (ram_awlen), + .s_axi_awsize (ram_awsize), + .s_axi_awburst (ram_awburst), + .s_axi_awlock (1'd0), + .s_axi_awcache (4'd0), + .s_axi_awprot (3'd0), + .s_axi_awvalid (ram_awvalid), + .s_axi_awready (ram_awready), + + .s_axi_arid (ram_arid), + .s_axi_araddr (ram_araddr[$clog2(RAM_SIZE)-1:0]), + .s_axi_arlen (ram_arlen), + .s_axi_arsize (ram_arsize), + .s_axi_arburst (ram_arburst), + .s_axi_arlock (1'd0), + .s_axi_arcache (4'd0), + .s_axi_arprot (3'd0), + .s_axi_arvalid (ram_arvalid), + .s_axi_arready (ram_arready), + + .s_axi_wdata (ram_wdata), + .s_axi_wstrb (ram_wstrb), + .s_axi_wlast (ram_wlast), + .s_axi_wvalid (ram_wvalid), + .s_axi_wready (ram_wready), + + .s_axi_bid (ram_bid), + .s_axi_bresp (ram_bresp), + .s_axi_bvalid (ram_bvalid), + .s_axi_bready (ram_bready), + + .s_axi_rid (ram_rid), + .s_axi_rdata (ram_rdata), + .s_axi_rresp (ram_rresp), + .s_axi_rlast (ram_rlast), + .s_axi_rvalid (ram_rvalid), + .s_axi_rready (ram_rready)); + + veerwolf_nospi + #(.bootrom_file (bootrom_file), + .clk_freq_hz ((cpu_type == "EL2") ? 32'd25_000_000 : 32'd50_000_000)) + veerwolf + (.clk (clk_core), + .rstn (~rst_core), + .dmi_reg_rdata (), + .dmi_reg_wdata (32'd0), + .dmi_reg_addr (7'd0), + .dmi_reg_en (1'b0), + .dmi_reg_wr_en (1'b0), + .dmi_hard_reset (1'b0), + .i_uart_rx (i_uart_rx), + .o_uart_tx (o_uart_tx), + .o_ram_awid (ram_awid), + .o_ram_awaddr (ram_awaddr), + .o_ram_awlen (ram_awlen), + .o_ram_awsize (ram_awsize), + .o_ram_awburst (ram_awburst), + .o_ram_awlock (ram_awlock), + .o_ram_awcache (ram_awcache), + .o_ram_awprot (ram_awprot), + .o_ram_awregion (ram_awregion), + .o_ram_awqos (ram_awqos), + .o_ram_awvalid (ram_awvalid), + .i_ram_awready (ram_awready), + .o_ram_arid (ram_arid), + .o_ram_araddr (ram_araddr), + .o_ram_arlen (ram_arlen), + .o_ram_arsize (ram_arsize), + .o_ram_arburst (ram_arburst), + .o_ram_arlock (ram_arlock), + .o_ram_arcache (ram_arcache), + .o_ram_arprot (ram_arprot), + .o_ram_arregion (ram_arregion), + .o_ram_arqos (ram_arqos), + .o_ram_arvalid (ram_arvalid), + .i_ram_arready (ram_arready), + .o_ram_wdata (ram_wdata), + .o_ram_wstrb (ram_wstrb), + .o_ram_wlast (ram_wlast), + .o_ram_wvalid (ram_wvalid), + .i_ram_wready (ram_wready), + .i_ram_bid (ram_bid), + .i_ram_bresp (ram_bresp), + .i_ram_bvalid (ram_bvalid), + .o_ram_bready (ram_bready), + .i_ram_rid (ram_rid), + .i_ram_rdata (ram_rdata), + .i_ram_rresp (ram_rresp), + .i_ram_rlast (ram_rlast), + .i_ram_rvalid (ram_rvalid), + .o_ram_rready (ram_rready), + .i_ram_init_done (1'b1), + .i_ram_init_error (1'b0), + .i_gpio ({32'd0,16'd0,sw_2r}), + .o_gpio (gpio_out)); + + always @(posedge clk_core) begin + o_led <= led_int_r; + led_int_r <= gpio_out[31:16]; + sw_r <= i_sw; + sw_2r <= sw_r; + end + +endmodule diff --git a/sw/pack_rom.S b/sw/pack_rom.S new file mode 100755 index 0000000..c35609d --- /dev/null +++ b/sw/pack_rom.S @@ -0,0 +1,100 @@ +/* +* Firmware for the Veerwolf Wolf Pack project +* +* Reads a number from UART, adds 1 and writes it to UART +* Same thing for GPIOs +* +*/ +#define CONSOLE_ADDR 0x80001008 +#define HALT_ADDR 0x80001009 +#define UART_BASE 0x80002000 +#define GPIO_BASE 0x80001010 + +#define REG_BRDL (4*0x00) /* Baud rate divisor (LSB) */ +#define REG_RDR (4*0x00) /* Receiver data reg. */ +#define REG_IER (4*0x01) /* Interrupt enable reg. */ +#define REG_FCR (4*0x02) /* FIFO control reg. */ +#define REG_LCR (4*0x03) /* Line control reg. */ +#define REG_LSR (4*0x05) /* Line status reg. */ +#define LCR_CS8 0x03 /* 8 bits data size */ +#define LCR_1_STB 0x00 /* 1 stop bit */ +#define LCR_PDIS 0x00 /* parity disable */ + +#define LSR_THRE 0x20 +#define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */ +#define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */ +#define FCR_XMITCLR 0x04 /* clear XMIT FIFO */ +#define FCR_MODE0 0x00 /* set receiver in mode 0 */ +#define FCR_MODE1 0x08 /* set receiver in mode 1 */ +#define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */ + + /* + a0 = UART address + a1 = GPIO base address + t0 = Byte to write + */ + +.globl _start +_start: + /* Init UART */ + li a0, UART_BASE + + /* Load GPIO base address to a0 */ + lui a1, %hi(GPIO_BASE) + addi a1, a1, %lo(GPIO_BASE) + + /* Set DLAB bit in LCR */ + li t3, 0x80 + sb t3, REG_LCR(a0) + + /* Set divisor regs */ + li t4, 27 + sb t4, REG_BRDL(a0) + + /* 8 data bits, 1 stop bit, no parity, clear DLAB */ + li t3, LCR_CS8 | LCR_1_STB | LCR_PDIS + sb t3, REG_LCR(a0) + + li t3, FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR + sb t3, REG_FCR(a0) + + /* disable interrupts */ + sb zero, REG_IER(a0) + +get_byte: + /* Read line status reg and check data available bit */ + lb t6, REG_LSR(a0) + andi t6, t6, 1 + beqz t6, do_gpio + + /* Get byte */ + lbu t0, REG_RDR(a0) + +put_byte: + /* Check for space in UART FIFO */ + lb t6, REG_LSR(a0) + andi t6, t6, LSR_THRE + beqz t6, put_byte + + /* Add 1 */ + addi t0, t0, 1 + + /* Write to UART */ + sb t0, 0(a0) + +do_gpio: + /* Read first 2 bytes of GPIO */ + lhu t1, 0(a1) + + /* Add 1 */ + addi t1, t1, 1 + + /* Store number in 3rd and 4th byte of GPIO */ + sh t1, 2(a1) + + j get_byte + + + /* Halt simulation (never happens) */ + li a1, HALT_ADDR + sw zero, 0(a1) \ No newline at end of file diff --git a/sw/pack_rom.vh b/sw/pack_rom.vh new file mode 100755 index 0000000..565018f --- /dev/null +++ b/sw/pack_rom.vh @@ -0,0 +1,15 @@ +800015B780002537 +08000E1301058593 +01B00E9301C50623 +00300E1301D50023 +08700E1301C50623 +0005022301C50423 +001FFF9301450F83 +00054283000F8E63 +020FFF9301450F83 +00128293FE0F8CE3 +0005D30300550023 +0065912300130313 +800015B7FD1FF06F +0005A02300958593 +0000000000000000 diff --git a/sw/radiant_pre_build.sh b/sw/radiant_pre_build.sh new file mode 100755 index 0000000..135cfcf --- /dev/null +++ b/sw/radiant_pre_build.sh @@ -0,0 +1,26 @@ +#!/bin/bash + +sed 's/VERSION_DIRTY=True/VERSION_DIRTY=1/' -i veerwolf_0.7.5.tcl +sed 's/VERSION_DIRTY=False/VERSION_DIRTY=0/' -i veerwolf_0.7.5.tcl +sed '4iprj_set_impl_opt VerilogStandard "System Verilog"' -i veerwolf_0.7.5.tcl +sed 's/.*el2_pdef.vh.*//' -i veerwolf_0.7.5.tcl +sed "s/unsigned'/uint'/" -i src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv +sed "1itypedef int unsigned uint;" -i src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv +sed "s/unsigned'/uint'/" -i src/pulp-platform.org__common_cells_1.20.0/src/stream_omega_net.sv + +incl_path='src/pulp-platform.org__common_cells_1.20.0/include;src/pulp-platform.org__axi_0.25.0/include;src/uart16550_1.5.5-r1/rtl/verilog;src/wb_common_1.0.3;src/veerwolf-intercon_0.7.5' + +if test -d 'src/veerwolf-veer_el2_pack_config_0.7.5' ; then + incl_path='src/veerwolf-veer_el2_pack_config_0.7.5;src/veerwolf-wb_nospi_intercon_0.7.5;'$incl_path + sed "1s/.*/parameter el2_pkg::el2_param_t pt = \'{/" -i src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh + sed '/package el2_pkg;/a`include "el2_pdef.vh"' -i src/chipsalliance.org_cores_VeeR_EL2_1.4/design/include/el2_def.sv +elif test -d 'src/veerwolf-veer_el2_default_config_0.7.5' ; then + incl_path='src/veerwolf-veer_el2_default_config_0.7.5;src/veerwolf-wb_intercon_0.7.5;'$incl_path + sed "1s/.*/parameter el2_pkg::el2_param_t pt = \'{/" -i src/veerwolf-veer_el2_default_config_0.7.5/el2_param.vh + sed '/package el2_pkg;/a`include "el2_pdef.vh"' -i src/chipsalliance.org_cores_VeeR_EL2_1.4/design/include/el2_def.sv +else + incl_path='src/veerwolf-veer_eh1_default_config_0.7.5;src/veerwolf-wb_intercon_0.7.5;src/chipsalliance.org_cores_VeeR_EH1_1.9/design/include;config;'$incl_path +fi +sed 's@.*include path.*@prj_set_impl_opt -impl "impl" "include path" '"\"$incl_path\"@" -i veerwolf_0.7.5.tcl + +sed '/prj_open veerwolf_0_7_5.rdf/a prj_set_strategy "Area" \nprj_save' -i veerwolf_0.7.5_run.tcl diff --git a/sw/verilogwriter.py b/sw/verilogwriter.py new file mode 100755 index 0000000..a0fd11c --- /dev/null +++ b/sw/verilogwriter.py @@ -0,0 +1,142 @@ +class Signal(object): + def __init__(self, name, width=0, low=0, asc=False, vec=0): + self.name = name + self.width = width + self.low = low + self.asc = asc + + def range(self): + if self.width > 0: + l = self.width+self.low-1 + r = self.low + if self.asc: + return '['+str(r)+':'+str(l)+']' + else: + return '['+str(l)+':'+str(r)+']' + return '' + + +class Wire(Signal): + def write(self, width): + return 'wire{range} {name};\n'.format(range=self.range().rjust(width), name=self.name) + + +class Assign: + def __init__(self, name, value): + self.name = name + self.value = value + + def write(self): + return 'assign {name} = {value};\n'.format(name=self.name, value=self.value) + + +class Parameter: + def __init__(self, name, value): + self.name = name + self.value = value + + +class Port: + def __init__(self, name, value): + self.name = name + self.value = value + + +class ModulePort(Signal): + def __init__(self, name, dir, width=0, low=0, asc=False): + super(ModulePort, self).__init__(name, width, low, asc) + self.dir = dir + + def write(self, range_width=0): + return '{dir} wire {range} {name}'.format(dir=self.dir.ljust(6), range=self.range().rjust(range_width), name=self.name) + + +class Instance: + def __init__(self, module, name, parameters, ports): + self.module = module + self.name = name + self.parameters = parameters + self.ports = ports + + def write(self): + s = self.module + if self.parameters: + max_len = max([len(p.name) for p in self.parameters]) + s += '\n #(' + s += ',\n '.join(['.' + p.name.ljust(max_len) + + ' (' + str(p.value) + ')' for p in self.parameters]) + s += ')\n' + s += ' ' + self.name + + if self.ports: + s += '\n (' + max_len = max([len(p.name) for p in self.ports]) + s += ',\n '.join(['.' + p.name.ljust(max_len) + + ' (' + str(p.value) + ')' for p in self.ports]) + s += ')' + s += ';\n' + return s + + +class VerilogWriter: + raw = "" + + def __init__(self, name): + self.name = name + self.instances = [] + self.ports = [] + self.wires = [] + self.assigns = [] + self.parameters = [] + + def add(self, obj): + if isinstance(obj, Instance): + self.instances += [obj] + elif isinstance(obj, ModulePort): + self.ports += [obj] + elif isinstance(obj, Wire): + self.wires += [obj] + elif isinstance(obj, Assign): + self.assigns += [obj] + elif isinstance(obj, Parameter): + self.parameters += [obj] + else: + raise Exception("Invalid type!" + str(obj)) + + def write(self, file=None): + s = ("// THIS FILE IS AUTOGENERATED BY verilogwriter.py\n" + "// ANY MANUAL CHANGES WILL BE LOST\n") + if self.ports: + s += "`default_nettype none\n" + s += "module {name}\n".format(name=self.name) + if self.parameters: + max_len = max([len(p.name) for p in self.parameters]) + s += '#(' + s += ',\n '.join([' parameter ' + p.name.ljust(max_len) + + ' = ' + str(p.value) for p in self.parameters]) + s += ')\n' + max_len = max([len(p.range()) for p in self.ports]) + s += ' (' + s += ',\n '.join([p.write(max_len) for p in self.ports]) + s += ')' + s += ';\n\n' + if self.wires: + max_len = max([len(w.range()) for w in self.wires]) + for w in self.wires: + s += w.write(max_len + 1) + s += '\n' + if self.assigns: + for a in self.assigns: + s += a.write() + s += '\n' + s += self.raw + for i in self.instances: + s += i.write() + s += '\n' + if self.ports: + s += 'endmodule\n' + if file is None: + return s + else: + f = open(file, 'w') + f.write(s) diff --git a/sw/wolfpack_gen.py b/sw/wolfpack_gen.py new file mode 100755 index 0000000..1f1ce32 --- /dev/null +++ b/sw/wolfpack_gen.py @@ -0,0 +1,53 @@ +#!/usr/bin/python3 +from fusesoc.capi2.generator import Generator +import os +import shutil +import subprocess + +from verilogwriter import Instance, ModulePort, Parameter, Port, VerilogWriter, Wire, Assign + + +class WolfPackGenerator(Generator): + def run(self): + files = [{'veerwolf_pack.v': {'file_type': 'verilogSource'}}] + count = self.config.get('count') + self.gen_veerwolf_pack(count) + self.add_files(files) + print(f'Generating {count} tiles') + + def gen_veerwolf_pack(self, count): + veerwolf_pack = VerilogWriter('veerwolf_pack') + + veerwolf_pack.add(ModulePort('clk_core', 'input')) + veerwolf_pack.add(ModulePort('rst_core', 'input')) + veerwolf_pack.add(ModulePort('i_uart_rx', 'input')) + veerwolf_pack.add(ModulePort('o_uart_tx', 'output')) + veerwolf_pack.add(ModulePort('i_sw', 'input', 16)) + veerwolf_pack.add(ModulePort('o_led', 'output', 16)) + veerwolf_pack.add(Parameter('pack_code', '"bootloader.vh"')) + + for idx in range(count+1): + veerwolf_pack.add(Wire('gpio'+str(idx), 16)) + veerwolf_pack.add(Wire('uart'+str(idx))) + + veerwolf_pack.add(Assign('gpio0', 'i_sw')) + veerwolf_pack.add(Assign('o_led', 'gpio'+str(count))) + veerwolf_pack.add(Assign('uart0', 'i_uart_rx')) + veerwolf_pack.add(Assign('o_uart_tx', 'uart'+str(count))) + + for idx in range(count): + veerwolf_pack.add(Instance('veerwolf_tile', 'tile'+str(idx), + [Parameter('bootrom_file', 'pack_code')], + [Port('clk_core', 'clk_core'), + Port('rst_core', 'rst_core'), + Port('i_uart_rx', 'uart'+str(idx)), + Port('o_uart_tx', 'uart'+str(idx+1)), + Port('i_sw', 'gpio'+str(idx)), + Port('o_led', 'gpio'+str(idx+1)) ])) + + veerwolf_pack.write('veerwolf_pack.v') + + +g = WolfPackGenerator() +g.run() +g.write() diff --git a/tb/pack_tb.cpp b/tb/pack_tb.cpp new file mode 100755 index 0000000..54f8aea --- /dev/null +++ b/tb/pack_tb.cpp @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//******************************************************************************** +// $Id$ +// +// Function: Verilator testbench for VeeRwolf +// Comments: +// +//******************************************************************************** + +#include +#include + +#include "Vveerwolf_pack_top.h" + +// For std::unique_ptr +#include + +// Include common routines +#include + +using namespace std; + +static bool done; + +void INThandler(int signal) +{ + printf("\nCaught ctrl-c\n"); + done = true; +} + +typedef struct { + uint8_t state; + char ch; + uint32_t baud_t; + vluint64_t last_update; + bool ready_to_read; // flag to keep track of whether we wrote to UART before reading +} uart_context_t; + +void uart_init(volatile uart_context_t *context, uint32_t baud_rate) { + context->baud_t = 1000*1000*1000/baud_rate; + context->state = 0; + context->ready_to_read = false; +} + +// FSM to read a byte from UART +int read_uart(volatile uart_context_t *context, uint64_t main_time, bool rx) { + if (context->state == 0) { + if (rx) + context->state++; + } + else if (context->state == 1) { + if (!rx) { + context->last_update = main_time + context->baud_t/2; + context->state++; + } + } + else if(context->state == 2) { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + context->ch = 0; + context->state++; + } + } + else if (context->state < 11) { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + context->ch |= rx << (context->state-3); + context->state++; + } + } + else { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + context->state=1; + return 1; + } + } + return 0; +} + +// FSM to write a byte to UART +int write_uart(volatile uart_context_t *context, vluint64_t main_time, uint8_t *tx) { + if (context->state == 0) { + *tx = 1; + context->state++; + } + else if (context->state == 1) { + *tx = 0; + context->last_update = main_time + context->baud_t/2; + context->state++; + } + else if(context->state == 2) { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + context->ch = 0; + context->state++; + } + } + else if (context->state < 11) { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + *tx = context->ch & 1; + context->ch >>= 1; + context->state++; + } + } + else { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + context->state=0; + context->ready_to_read = true; + *tx = 1; + return 1; + } + } + return 0; +} + +int main(int argc, char **argv, char **env) +{ + const unique_ptr contextp{new VerilatedContext}; + contextp->commandArgs(argc, argv); + + // Set debug level, 0 is off, 9 is highest presently used + // May be overridden by commandArgs argument parsing + contextp->debug(0); + + uint16_t gpios[2] = {0, 0}; + const unique_ptr top{new Vveerwolf_pack_top{contextp.get(), "TOP"}}; + + volatile uart_context_t uart_context; + int baud_rate = 115200; + + uart_init(&uart_context, baud_rate); + + vluint64_t timeout = 0; + const vluint64_t incr_gpio = 10000000; + const char *arg_timeout = contextp->commandArgsPlusMatch("timeout="); + + if (arg_timeout[0]) + timeout = atoi(arg_timeout+9); + + signal(SIGINT, INThandler); + + top->clk = 1; + top->rstn = 0; + top->i_sw = gpios[0]; + + while (!(done || contextp->gotFinish())) { + if (contextp->time() == 100) { + printf("Releasing reset\n"); + top->rstn = 1; + } + + top->eval(); + + if(!uart_context.ready_to_read && write_uart(&uart_context, contextp->time(), &top->i_uart_rx)){ + printf("%lu: Successfully sent a byte through UART!\n", contextp->time()); + } + + if (uart_context.ready_to_read && read_uart(&uart_context, contextp->time(), top->o_uart_tx)){ + printf("%lu: Read \"%d\" from UART\n", contextp->time(), uart_context.ch); + fflush(stdout); + } + + if (gpios[1] != (top->o_led)) { + gpios[1] = top->o_led; + printf("%lu: gpio output is %u\n", contextp->time(), gpios[1]); + } + + if (timeout && (contextp->time() >= timeout)) { + printf("Timeout: Exiting at time %lu\n", contextp->time()); + done = true; + } + + top->clk = !top->clk; + contextp->timeInc(10); + + if(contextp->time() % incr_gpio == 0){ + printf("%lu: Incrementing GPIO input\n"); + top->i_sw = ++gpios[0]; + } + } + + return 0; +} diff --git a/tb/veerwolf_pack_tb.v b/tb/veerwolf_pack_tb.v new file mode 100755 index 0000000..02fe22c --- /dev/null +++ b/tb/veerwolf_pack_tb.v @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//******************************************************************************** +// $Id$ +// +// Function: VeeRwolf Wolf Pack toplevel +// Comments: +// +//******************************************************************************** + +`default_nettype none +module veerwolf_pack_tb + #(parameter bootrom_file = "pack_rom.vh", + parameter cpu_type = "EL2") + (input wire clk, + input wire rstn, + input wire i_uart_rx, + output wire o_uart_tx, + input wire [15:0] i_sw, + output reg [15:0] o_led); + + wire [63:0] gpio_out; + reg [15:0] led_int_r; + + veerwolf_pack + #(.pack_code (bootrom_file)) + veerwolfs + (.clk_core (clk), + .rst_core (~rstn), + .i_uart_rx (i_uart_rx), + .o_uart_tx (o_uart_tx), + .i_sw (i_sw), + .o_led (o_led)); + +endmodule diff --git a/veerwolf-chain.png b/veerwolf-chain.png new file mode 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zbM>3bAmCX=t2#Tp;wMf!s-w#fnlCwQ?^+Z$8?@jId|nao$fB>!9j7!s!=fifgaK!L z0?jtp=pulp-platform.org::axi:0.23.0-r1" + - ::wb_intercon:1.4.1 + bfm: files: - tb/uart_decoder.v @@ -38,6 +52,14 @@ filesets: - rtl/axi_ram.v : {file_type : verilogSource} - tb/veerwolf_core_tb.v : {file_type : systemVerilogSource} + pack_tb: + files: + - tb/veerwolf_core_tb.v : {file_type : systemVerilogSource} + - tb/veerwolf_pack_tb.v : {file_type : systemVerilogSource} + - rtl/veerwolf_tile.v : {file_type : systemVerilogSource} + - rtl/axi_ram.v : {file_type : verilogSource} + - tb/pack_tb.cpp : {file_type : cppSource} + verilator_tb: files: [tb/tb.cpp : {file_type : cppSource}] depend : [">=::jtag_vpi:0-r5"] @@ -59,6 +81,23 @@ filesets: - rtl/veerwolf_agilex.v : {file_type : systemVerilogSource} - rtl/axi_ram.v : {file_type : verilogSource} + agilex5_pack_files: + files : + - data/agilex5_pack.sdc : {file_type : SDC} + - data/agilex5_pack.tcl : {file_type : tclSource} + - rtl/clk_gen_agilex.v : {file_type : verilogSource} + - rtl/veerwolf_pack_agilex.v : {file_type : systemVerilogSource} + - rtl/veerwolf_tile.v : {file_type : systemVerilogSource} + - rtl/axi_ram.v : {file_type : verilogSource} + + avant_pack_files: + files: + - data/avant_pack.sdc : {file_type : PDC} + - rtl/veerwolf_pack_avant.v : {file_type : systemVerilogSource} + - rtl/veerwolf_tile.v : {file_type : systemVerilogSource} + - rtl/axi_ram.v : {file_type : verilogSource} + - sw/radiant_pre_build.sh : {file_type : user, copyto : radiant_pre_build.sh} + nexys_a7_files: files : - data/vivado_waiver.tcl : {file_type : tclSource} @@ -99,6 +138,10 @@ filesets: files : - sw/bootloader.vh : {file_type : user, copyto : bootloader.vh} + pack_bootrom: + files : + - sw/pack_rom.vh : {file_type : user, copyto : pack_rom.vh} + targets: agilex5: default_tool : quartus @@ -109,7 +152,7 @@ targets: - bootrom - core - agilex5_files - generate : [intercon, "!cpu_el2? (veer_eh1_default_config)", "cpu_el2? (veer_el2_default_config)", version, wb_intercon] + generate : [intercon, "!cpu_el2? (veer_eh1_default_config)", "cpu_el2? (veer_el2_pack_config)", version, wb_intercon] parameters : [bootrom_file, "cpu_el2? (cpu_type=EL2)"] tools: quartus: @@ -117,6 +160,39 @@ targets: device : A5ED065BB32AE6SR0 toplevel : veerwolf_agilex + agilex5_pack: + default_tool : quartus + description : FPGA image VeeR EL2 pack for the Intel Agilex 5 FPGA E-Series DK A5E065BB32AES1 Premium devkit + filesets : + - el2 + - pack_bootrom + - nospi_core + - agilex5_pack_files + generate : [wolfpack: {count: 18}, intercon, veer_el2_pack_config, version, wb_nospi_intercon] + parameters : [bootrom_file, "cpu_type=EL2"] + tools: + quartus: + family : Agilex 5 + device : A5ED065BB32AE6SR0 + toplevel : veerwolf_pack_agilex + + avant_pack: + default_tool : radiant + description : FPGA image VeeR EL2 pack for Lattice Avant E-Series + filesets : + - el2 + - pack_bootrom + - nospi_core + - avant_pack_files + generate : [wolfpack: {count: 13}, intercon, veer_el2_pack_config, version, wb_nospi_intercon] + parameters : [bootrom_file, "cpu_type=EL2"] + hooks : + pre_build : [radiant_patch_script] + tools: + radiant: + part: LAV-AT-E70ES1-3LFG1156C + toplevel : veerwolf_pack_avant + basys3: default_tool : vivado description : FPGA image with VeeR EL2 for the Digilent Basys 3 FPGA board @@ -187,6 +263,23 @@ targets: xelab_options : [-d, XSIM] toplevel : veerwolf_core_tb + pack_sim: + default_tool : verilator + description : Simulate the Veerwolf pack project + filesets : + - "cpu_el2? (el2)" + - "!cpu_el2? (eh1)" + - nospi_core + - pack_tb + - pack_bootrom + - verilator_waiver + generate : [wolfpack, intercon, "cpu_el2? (veer_el2_pack_config)", "!cpu_el2? (veer_eh1_default_config)", version, wb_nospi_intercon] + parameters : [SIMPRINT=true, rom_init_file, signature, timeout, "cpu_el2? (cpu_type=EL2)"] + tools: + verilator: + verilator_options : [--trace, -Wno-fatal] + toplevel : veerwolf_pack_tb + spi_tb: default_tool : modelsim description : Simulation target with real SPI Flash model @@ -260,6 +353,11 @@ targets: toplevel : veerwolf_arty_a7 generate: + wolfpack: + generator: wolfpack_gen + parameters: + count : 2 + wb_intercon: generator: wb_intercon_gen parameters: @@ -303,6 +401,23 @@ generate: offset : 0x00000000 size : 0x08000000 #128MiB + wb_nospi_intercon: + generator: wb_intercon_gen + parameters: + masters: + io: + slaves : [rom, sys, uart] + slaves: + rom: + offset : 0x00000000 + size : 0x00001000 + sys: + offset : 0x00001000 + size : 0x00000040 + uart: + offset : 0x00002000 + size : 0x00001000 + veer_eh1_default_config: generator: veer_eh1_config position : first @@ -315,6 +430,24 @@ generate: parameters: args : [-unset=assert_on, -set=reset_vec=0x80000000, -set=fpga_optimize=1, -set=pic_total_int=8] + veer_el2_pack_config: + generator: veer_el2_config + position : first + parameters: + args : + - -unset=assert_on + - -set=reset_vec=0x80000000 + - -set=fpga_optimize=1 + - -set=ret_stack_size=2 + - -set=btb_size=32 + - -set=bht_size=128 + - -set=dccm_size=16 + - -set=dccm_num_banks=2 + - -set=iccm_enable=0 + - -set=icache_enable=0 + - -set=dccm_enable=0 + - -set=pic_total_int=8 + veer_el2_nexys_a7_config: generator: veer_el2_config position : first @@ -357,6 +490,11 @@ generate: version: generator: gitversion +generators: + wolfpack_gen: + interpreter: python3 + command: sw/wolfpack_gen.py + parameters: SIMPRINT: datatype : bool @@ -410,3 +548,7 @@ parameters: datatype : bool description : Dump VCD paramtype : plusarg + +scripts: + radiant_patch_script: + cmd : [bash, "radiant_pre_build.sh"] diff --git a/veerwolves.svg b/veerwolves.svg new file mode 100755 index 0000000..656c845 --- /dev/null +++ b/veerwolves.svg @@ -0,0 +1,4 @@ + + + + \ No newline at end of file