bscan_tap module - how does it work?

[agrobman]

Hi Olof,

I'm new in FPGAs and wondering how does your bscan_tap module work ? where are the definitions / descriptions of the BSCAN2 modules? How are some internal wires driven?

Thanks in advance
Alex

[agrobman]

More question:
what is clk_gen_nexus module? and where the user_clk, user_rst signals driven from?

[JanMatCodasip]

I'm new in FPGAs and wondering how does your bscan_tap module work ?

Hi @agrobman,

The bscan_tap module in SweRVolf is a wrapper over Xilinx BSCANE2 primitives, provided only as black-box IP blocks by Xilinx. BSCANE2 allows to connect the user's custom design to the JTAG TAP of the FPGA component.

It works this way: If the JTAG debugger writes one of the special "user instructions" to the FPGA's JTAG instruction register, the following JTAG data scans will go directly to the user design through the BSCANE2 instances.

In SweRVolf, this mechanism is utilized to expose SweRV's JTAG registers of SweRV in the JTAG TAP of the FPGA.

Pointers to Xilinx documentation about BSCANE2:

• https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/7series_hdl.pdf, page 72
• https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf, page 175

Hope this helped to answer at least some of your questions.

Jan

[olofk]

Thanks @JanMatCodasip,

That sums it up quite well. I guess the other half of the answer is why we do it like this. On the Nexys A7 board, the dedicated FPGA JTAG pins are connected to an FTDI chip together with the UART channel. This way we only need to connect a single USB cable to the board for power, UART and JTAG instead of requiring a separate JTAG adapter.

In extension, by exposing the debug interface from the CPU instead of the JTAG pins, this allows us to tunnel the debug interface over basically any connection. Not all FPGA boards have JTAG-to-USB or even convenient user-accessible I/O pins. We could e.g. do debug over ethernet or debug over UART or debug over pciE if those are more convenient ways to access the SoC on other boards

[agrobman]

thanks Olof and Jan for explanation, BTW, FTDI chip has two serial channels can be configured as JTAG IFs,

Can the 2nd one be connected/used as original swerv JTAG interface to test original JTAG logic?
Digilent does not provide schematics for FTDI chip connections on the board for some reason.
Does anybody from you know how to configure openocd to use channel A or B of the FTDI ?

what's about my 2nd question(s)?

what is clk_gen_nexus module? and where the user_clk, user_rst signals driven from?

[olofk]

That part about the missing FTDI connections rang a bell so I did some research and yep, been through this before. :) So to sum it up, it's a good idea and it might be possible. It seems like at least tx, rx, cts and rts are connected and if we're lucky enough they might map to the four jtag pins we need. But further investigation would be needed.

Regarding the other question, user_clk and user_rst are created by PLLs in the DDR controller. Those PLLs are in turn driven by the external 100MHz input clock. I took the opportunity to make a clocking diagram. Will clean this up and add to the doccs eventually

[agrobman]

thanks Olof,
this diagram is really good.
A few more wishes:

1. user_rst - what is its source? where it come from? How is it related to the board "reset" pushbutton?
   We need probably have rst_l of the core be driven by external reset pushbutton/FPGA pin and by debugger (from debugger connector) Latest EH1 has dbg_rst_l reset for DM block only allowing to start debug session, while the CPU is in reset ..

2. how are the FPGA clocks configured? Are their frequencies hardwired to 100MHz FPGA input clock or can be programmed?

3. Does the DDR controller comes out of reset programmed/ready to be used or needs initialization by the SweRV boot code?

4. what are your thoughts about TRST reset our design have, but seems FPGA does not.

5. what tool do you use to draw block diagrams, I'm looking for something simple for Mac .

[JanMatCodasip]

FTDI chip has two serial channels can be configured as JTAG IFs,

Can the 2nd one be connected/used as original swerv JTAG interface to test original JTAG logic?
Digilent does not provide schematics for FTDI chip connections on the board for some reason.
Does anybody from you know how to configure openocd to use channel A or B of the FTDI ?

I am afraid it is not possible.

If the pins BDBUS2 & BDBUS3 of the FTDI chip on Nexys A7 were connected to some FPGA's general purpose I/Os, it would be possible to have a standard 4-wire JTAG on the channel B of the FTDI chip. Unfortunately, those pins are not connected.

The USB-to-JTAG part of the Nexys A7 design is proprietary (Digilent does not provide its schematic), but they at the very least confirmed to me that these two pins are not connected on the board: https://forum.digilentinc.com/topic/18999-arty-a7-fpga-board-access-to-pins-bdbus2-and-bdbus3-of-ft2232h/

So the options are:

• use the SweRVolf's approach to RISC-V debug tunneling via BSCAN
• or if testing of the original SweRV's JTAG logic is a must, then go for a standalone USB-JTAG adapter (e.g. Digilent JTAG-HS2 works well)

[agrobman]

or solder these two pins to some FPGA IO/connector (QFP package pins are exposed to soldering ...)
Oh, they actually confirmed that we CAN connect/solder these pins with wires to FPGA , as their design does not use these 2 pins.

I agree that for general public current solution is the best, but not that good for debugger vendors and somebody wants to use swerv as is, without modifications.

[agrobman]

the 2nd option is questionable.
a) there is no TRST line in their adapter/pin connector.
b) Not sure if we can connect/use the FPGA JTAG pins to/in our design directly, especially TDO
c) how will debugger know to work with this adapter ?

[JanMatCodasip]

a) there is no TRST line in their adapter/pin connector.

Correct, in Digilent JTAG HS2 there is no TRST output. From user perspective, this is not important. TRST is optional in the JTAG standard. The debugger can replace the assertion of TRST by issuing 5x TMS=1, which also causes the FSM inside the JTAG TAP to transtion to its initial state.

If TRST is really needed some reason, you may pick a debug adapter that contains TRST. For example:

• Segger J-Link: https://www.segger.com/products/debug-probes/j-link/
• Olimex ARM-USB-TINY-H: https://www.olimex.com/Products/ARM/JTAG/ARM-USB-TINY-H/

b) Not sure if we can connect/use the FPGA JTAG pins to/in our design directly, especially TDO

I don't think there is an issue with exposing the JTAG signals onto the FPGA pins. Do you see any specific concern here?

c) how will debugger know to work with this adapter ?

OpenOCD has its configuration commands that allow to specify which JTAG adapter to use.

The list of adapters that OpenOCD supports is in the documentaiton, incl. their configurable options: http://openocd.org/doc/html/Debug-Adapter-Configuration.html#Debug-Adapter-Configuration

Usually you don't need to configure the adapter yourself, as there are ready-made configuration files for the supported adapters, shipped with OpenOCD: https://github.com/riscv/riscv-openocd/tree/riscv/tcl/interface

[JanMatCodasip]

or solder these two pins to some FPGA IO/connector (QFP package pins are exposed to soldering ...)
Oh, they actually confirmed that we CAN connect/solder these pins with wires to FPGA , as their design does not use these 2 pins.

Soldering custom wires to the board to interconnect FT2232 and the FPGA pins is possible, but I do not recommend it. It is inherently unreliable (small QFN pads). Other than saving few $ for an external debug adapter, it brings no advantage.

[agrobman]

I meant to use FPGA TDI/TDO/TCK/TMS pins as SweRV JTAG pins. Does Vivado allow to reuse these pins for emulated design?

Regarding adapters - I couldn't find one which can be seamlessly connected to the board PMOD connectors .. Adapter's connectors pinouts don't have VREF/GND pins in the same place, where the board has them :(

So looks like we'll need to do some soldering if we want to emulate original JTAG design ..

[JanMatCodasip]

I meant to use FPGA TDI/TDO/TCK/TMS pins as SweRV JTAG pins. Does Vivado allow to reuse these pins for emulated design?

My understanding is that TDI, TDO, TCK & TMS FPGA pins cannot be re-purposed for the user design. The only (limited) way how to use them for custom purposes is through the BSCAN primitive, as SweRVolf does.

Regarding adapters - I couldn't find one which can be seamlessly connected to the board PMOD connectors .. Adapter's connectors pinouts don't have VREF/GND pins in the same place, where the board has them :(
So looks like we'll need to do some soldering if we want to emulate original JTAG design ..

If operation without TRST is sufficient, then Digilent JTAG-HS2 can be used. It fits into a PMOD connector directly, see the picture. It works well and I often use it this way (also on other processors than SweRV).

If you'd like to have TRST, too, then my recommendation is to take one of the USB-JTAG adapters that have it (Segger J-Link, ARM-USB-TINY-H, ....). Then build a simple custom adapter between the standard JTAG 20-pin connector and the PMOD connector on Nexys A7.

[agrobman]

Jan, BTW, did you ever use/check original SwerV DMI module in FPGA emulation with any debugger?

[JanMatCodasip]

Jan, BTW, did you ever use/check original SwerV DMI module in FPGA emulation with any debugger?

Yes, I have worked with plain-vanilla SweRV w/ original DMI & JTAG interface on the Nexys A7 board. It was some time ago, though. The debug adapter was Olimex ARM-USB-TINY-H. I believe it was SweRV version 1.4 or 1.5.

Since then, I've been using SweRVolf.

[MatthewMFLai]

Newbie question for @JanMatCodasip regarding the photo showing the JTAG-HS2 connected to the pmod JD on the Nexys A7: I'm trying to set up the same connection, JTAG-HS2 to pmod JD, but not sure whether to use the top row or the bottom row of the pmod (the pmod is 2x6)? Also, if I connect the JTAG-HS2 to the jumper J10 do you think that will work too?

[olofk]

@MatthewMFLai Is there any particular reason you need a separate JTAG cable? SweRVolf supports both JTAG, UART and power over the same USB connection and this is the normal way to connect a debugger

[MatthewMFLai]

@olofk Oh I'm not using SweRVolf here (and I do apologize for asking a non-SwerRVolf question in this forum). The RISC-V that I'm testing with the Nexys A7 explicitly mentions using the JTAG-HS2 to connect to the Nexys A7, and then I googled and found the picture from @JanMatCodasip, that's why I'm asking here.

[JanMatCodasip]

Hi @MatthewMFLai,

so this is not SweRVolf-related question, all right.

In general, if you work with a 3rd party design on Nexys A7 board, it is best to ask the author where the JTAG pins are mapped in that particular design. There is no "standard" and the designer is free to pick any of the general-purpose pins on the Nexys A7 board. So in other words, the JTAG pins could be anywhere.

[chithize]

@JanMatCodasip HI, BSCAN is very good design for the single debug connection, but I found a problem with it , that is when I tried the ila inserting to netlist to debug some issue , the usb-jtag connection is occupied by vivado, open-ocd can't connect to SWERV core, which cause I can't download testing code. is there any way to resolve it with single jtag usb connection? the solution I can get is to sperarate debug jtag connection to PMOD

[olofk]

That is a very valid comment, and I would like to have the option to support an external JTAG adapter through PMOD for other reasons as well. It shouldn't be too much work but hasn't been done yet