diff --git a/.github/workflows/build-test-verilator.yml b/.github/workflows/build-test-verilator.yml
index 53d8b407c..4e2795b14 100644
--- a/.github/workflows/build-test-verilator.yml
+++ b/.github/workflows/build-test-verilator.yml
@@ -123,7 +123,7 @@ jobs:
     outputs:
       test_names: ${{ steps.output-matrix.outputs.test_names  }}
     env:
-      EXCLUDE_TESTS: "smoke_test_clk_gating, smoke_test_cg_wdt, smoke_test_mbox_cg, smoke_test_kv_cg, smoke_test_doe_cg"
+      EXCLUDE_TESTS: "smoke_test_clk_gating"
     steps:
       - uses: actions/checkout@v3
       - name: Install deps
diff --git a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
index 921975a55..c63f54e1a 100644
--- a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
+++ b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
@@ -761,16 +761,10 @@ module `TEC_RV_ICG
 
    assign      enable = EN | SE;
 
-`ifdef VERILATOR
-   always @(negedge CK) begin
-      en_ff <= enable;
-   end
-`else
    always @(CK, enable) begin
       if(!CK)
         en_ff = enable;
    end
-`endif
    assign Q = CK & en_ff;
 
 endmodule
diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile
index 03c9b10c5..09ed7c843 100644
--- a/tools/scripts/Makefile
+++ b/tools/scripts/Makefile
@@ -119,43 +119,47 @@ $(eval TBFILES = $(shell cat $(TBDIR)/../config/caliptra_top_tb.vf | grep -v '+i
 #defines += $(RV_ROOT)/design/include/el2_def.sv
 #defines += $(BUILD_DIR)/el2_pdef.vh
 includes = -I$(BUILD_DIR)
-#
-#         .--------------------------------------------------------------------------------.
-#         | Verilator does not support unpacked structs/unions - waive this warning so     |
-#         | that unpacked structs are treated as packed. This should only impact files     |
-#         | generated from RDL register files, which use unpacked structs liberally.       |
-#         '-----------------------------------------------------------------------------+--'
-#                                                                                       |
-#         .---------------------------------------------------------------------.       |
-#         | This is flagged for every generated SystemVerilog file defining a   |       |
-#         | register block. The field_storage signal is the target of the       |       |
-#         | warning, indicating multiple drivers/different clocking.            |       |
-#         '----------------------------------------------------------------+----'       |
-#                                                                          |            |
-#         .------------------------------------------------------.         |            |
-#         | PeakRDL implements the default incrsaturate behavior |         |            |
-#         | for counter registers by performing a > comparison   |         |            |
-#         | with an all-ones value (i.e. cnt > 32'hFFFFFFFF)     |         |            |
-#         | which, by definition, can never be true. Verilator   |         |            |
-#         | warns that this will compile to a constant 0.        |         |            |
-#         '------------------------------------------------+-----'         |            |
-#                                                          |               |            |
-#         .--------------------------------------------.   |               |            |
-#         | Vectors that are little bit-endian are not |   |               |            |
-#         | supported by Verilator, according to a     |   |               |            |
-#         | warning that is thrown. This is supposedly |   |               |            |
-#         | resolved as of version 3.720, according    |   |               |            |
-#         | to the release notes.                      |   |               |            |
-#         '-----------------------------------+--------'   |               |            |
-#                                             |            |               |            |
-#         .------------------------------.    |            |               |            |
-#         | Inherited from ChipsAlliance |    |            |               |            |
-#         | VeeR repository provided     |    |            |               |            |
-#         | Makefile                     |    |            |               |            |
-#         '-----+------------+-----------'    |            |               |            |
-#               |            |                |            |               |            |
-#               v            v                v            v               v            v
-suppress = -Wno-WIDTH -Wno-UNOPTFLAT -Wno-LITENDIAN -Wno-CMPCONST -Wno-MULTIDRIVEN -Wno-UNPACKED
+#         .----------------------------------------------------------------------------------------------.
+#         | Verilator is optimized for edge-sensitive (flop-based) designs. However, it supports latches |
+#         | with most performance optimizations disabled and warns that it may be non-intentional latch. |
+#         '-------------------------------------------------------------------------------------------+--'
+#                                                                                                     |
+#         .--------------------------------------------------------------------------------.          |
+#         | Verilator does not support unpacked structs/unions - waive this warning so     |          |
+#         | that unpacked structs are treated as packed. This should only impact files     |          |
+#         | generated from RDL register files, which use unpacked structs liberally.       |          |
+#         '-----------------------------------------------------------------------------+--'          |
+#                                                                                       |             |
+#         .---------------------------------------------------------------------.       |             |
+#         | This is flagged for every generated SystemVerilog file defining a   |       |             |
+#         | register block. The field_storage signal is the target of the       |       |             |
+#         | warning, indicating multiple drivers/different clocking.            |       |             |
+#         '----------------------------------------------------------------+----'       |             |
+#                                                                          |            |             |
+#         .------------------------------------------------------.         |            |             |
+#         | PeakRDL implements the default incrsaturate behavior |         |            |             |
+#         | for counter registers by performing a > comparison   |         |            |             |
+#         | with an all-ones value (i.e. cnt > 32'hFFFFFFFF)     |         |            |             |
+#         | which, by definition, can never be true. Verilator   |         |            |             |
+#         | warns that this will compile to a constant 0.        |         |            |             |
+#         '------------------------------------------------+-----'         |            |             |
+#                                                          |               |            |             |
+#         .--------------------------------------------.   |               |            |             |
+#         | Vectors that are little bit-endian are not |   |               |            |             |
+#         | supported by Verilator, according to a     |   |               |            |             |
+#         | warning that is thrown. This is supposedly |   |               |            |             |
+#         | resolved as of version 3.720, according    |   |               |            |             |
+#         | to the release notes.                      |   |               |            |             |
+#         '-----------------------------------+--------'   |               |            |             |
+#                                             |            |               |            |             |
+#         .------------------------------.    |            |               |            |             |
+#         | Inherited from ChipsAlliance |    |            |               |            |             |
+#         | VeeR repository provided     |    |            |               |            |             |
+#         | Makefile                     |    |            |               |            |             |
+#         '-----+------------+-----------'    |            |               |            |             |
+#               |            |                |            |               |            |             |
+#               v            v                v            v               v            v             v
+suppress = -Wno-WIDTH -Wno-UNOPTFLAT -Wno-LITENDIAN -Wno-CMPCONST -Wno-MULTIDRIVEN -Wno-UNPACKED -Wno-LATCH
 
 # CFLAGS for verilator generated Makefiles. Without -std=c++17 it
 # complains for `auto` variables
diff --git a/tools/scripts/run_verilator_l0_regression.py b/tools/scripts/run_verilator_l0_regression.py
index a4cbbd2ee..12889dffb 100644
--- a/tools/scripts/run_verilator_l0_regression.py
+++ b/tools/scripts/run_verilator_l0_regression.py
@@ -123,7 +123,7 @@ def getTestNames():
         # Skip clk gating tests in Verilator until PC issue is resolved
         # https://github.com/chipsalliance/Cores-VeeR-EL2/issues/88
         # https://github.com/chipsalliance/caliptra-rtl/issues/126
-        if (re.search(r'(smoke_test_clk_gating|smoke_test_cg_wdt)',x.groups()[0])) :
+        if (re.search(r'(smoke_test_clk_gating)',x.groups()[0])) :
             continue
         integrationTestSuiteList.append(x.groups()[0])