From 8b0f2d452b4faaf944dcbf417905cba40f17a4f2 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Wed, 20 Nov 2024 18:19:29 -0800 Subject: [PATCH] Intercept latest RV core updates from VeeR repo --- src/riscv_core/veer_el2/rtl/common_defines.sv | 4 ++-- src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv | 3 +++ src/riscv_core/veer_el2/rtl/dec/el2_dec.sv | 3 +++ .../veer_el2/rtl/dec/el2_dec_decode_ctl.sv | 3 +++ .../veer_el2/rtl/dec/el2_dec_gpr_ctl.sv | 3 +++ .../veer_el2/rtl/dec/el2_dec_pmp_ctl.sv | 3 +++ .../veer_el2/rtl/dec/el2_dec_tlu_ctl.sv | 6 +++++ src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv | 3 +++ src/riscv_core/veer_el2/rtl/el2_mem.sv | 3 +++ src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv | 3 +++ src/riscv_core/veer_el2/rtl/el2_veer.sv | 3 +++ .../veer_el2/rtl/el2_veer_wrapper.sv | 2 +- src/riscv_core/veer_el2/rtl/exu/el2_exu.sv | 3 +++ .../veer_el2/rtl/exu/el2_exu_alu_ctl.sv | 3 +++ .../veer_el2/rtl/exu/el2_exu_div_ctl.sv | 18 ++++++++++++++ .../veer_el2/rtl/exu/el2_exu_mul_ctl.sv | 3 +++ src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv | 3 +++ .../veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv | 3 +++ .../veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv | 3 +++ .../veer_el2/rtl/ifu/el2_ifu_ic_mem.sv | 9 +++++++ .../veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv | 3 +++ .../veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv | 3 +++ .../veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv | 3 +++ .../rtl/include/el2_dec_csr_equ_m.svh | 3 +++ .../veer_el2/rtl/lib/axi4_to_ahb.sv | 3 +++ src/riscv_core/veer_el2/rtl/lib/beh_lib.sv | 24 +++++++++++++++++++ src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_addrcheck.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_bus_intf.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_clkdomain.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_ecc.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv | 3 +++ .../veer_el2/rtl/lsu/el2_lsu_stbuf.sv | 3 +++ src/riscv_core/veer_el2/rtl/riscv_rev_info | 10 ++++---- 37 files changed, 155 insertions(+), 8 deletions(-) diff --git a/src/riscv_core/veer_el2/rtl/common_defines.sv b/src/riscv_core/veer_el2/rtl/common_defines.sv index bf10f8dba..33a2ea04b 100644 --- a/src/riscv_core/veer_el2/rtl/common_defines.sv +++ b/src/riscv_core/veer_el2/rtl/common_defines.sv @@ -16,9 +16,9 @@ // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -// This is an automatically generated file by cwhitehead on Wed Nov 13 10:25:09 PST 2024 +// This is an automatically generated file by cwhitehead on Wed Nov 20 18:12:03 PST 2024 // -// cmd: veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241106_cptra_en_pmp +// cmd: veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241120_latest_fixes // `ifndef RV_COMMON_DEFINES `define RV_COMMON_DEFINES diff --git a/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv b/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv index 67f424047..cc498108c 100644 --- a/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv +++ b/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv @@ -133,7 +133,10 @@ import el2_pkg::*; input logic rst_l, // This includes both top rst and debug rst input logic dbg_rst_l, input logic clk_override, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv index 3a960ae2b..5d340feff 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv @@ -320,7 +320,10 @@ module el2_dec output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating output logic dec_tlu_i0_commit_cmt, // committed i0 instruction + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // Flop scan mode control + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv index 0afac252a..c0410e86f 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv @@ -196,7 +196,10 @@ import el2_pkg::*; output logic dec_div_active, // non-block divide is active + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv index b551d9d65..d406ba977 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv @@ -39,7 +39,10 @@ import el2_pkg::*; output logic [31:0] rd0, // read data output logic [31:0] rd1, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); logic [31:1] [31:0] gpr_out; // 31 x 32 bit GPRs diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv index 3459843d7..204462293 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv @@ -58,7 +58,10 @@ module el2_dec_pmp_ctl output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES], output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES], + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); logic wr_pmpcfg_r; diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv index 2c239eb58..2ab8de9dd 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv @@ -33,7 +33,10 @@ import el2_pkg::*; input logic free_clk, input logic free_l2clk, input logic rst_l, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ input logic [31:1] rst_vec, // reset vector, from core pins input logic nmi_int, // nmi pin @@ -3030,7 +3033,10 @@ import el2_pkg::*; output logic dec_timer_t0_pulse, // timer0 int output logic dec_timer_t1_pulse, // timer1 int + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); localparam MITCTL_ENABLE = 0; localparam MITCTL_ENABLE_HALTED = 1; diff --git a/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv b/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv index 9e247035a..a3ca7f6cb 100644 --- a/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +++ b/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv @@ -31,7 +31,10 @@ import el2_pkg::*; input logic rst_l, input logic dma_bus_clk_en, // slave bus clock enable input logic clk_override, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ // Debug signals input logic [31:0] dbg_cmd_addr, diff --git a/src/riscv_core/veer_el2/rtl/el2_mem.sv b/src/riscv_core/veer_el2/rtl/el2_mem.sv index 48d04d366..adfcfc4a2 100644 --- a/src/riscv_core/veer_el2/rtl/el2_mem.sv +++ b/src/riscv_core/veer_el2/rtl/el2_mem.sv @@ -85,7 +85,10 @@ import el2_pkg::*; el2_mem_if.veer_sram_src mem_export, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv b/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv index 797872e15..755fb56e4 100644 --- a/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv +++ b/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv @@ -47,7 +47,10 @@ import el2_pkg::*; output logic [3:0] pl, // Priority level of the requested interrupt output logic [31:0] picm_rd_data, // Read data of the register output logic mhwakeup, // Wake-up interrupt request + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // scan mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/el2_veer.sv b/src/riscv_core/veer_el2/rtl/el2_veer.sv index de7fe13c5..def2cc498 100644 --- a/src/riscv_core/veer_el2/rtl/el2_veer.sv +++ b/src/riscv_core/veer_el2/rtl/el2_veer.sv @@ -458,7 +458,10 @@ import el2_pkg::*; input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, input logic timer_int, input logic soft_int, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv index 3d6e179c2..935518b7e 100644 --- a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv +++ b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv @@ -428,7 +428,7 @@ import el2_pkg::*; input logic i_cpu_run_req, // Async restart req to CPU output logic o_cpu_run_ack, // Core response to run req - /* exclude signals that are tied to constant value or left unconnected in tb_top.sv */ + // Excluding scan_mode and mbist_mode from coverage as their usage is determined by the integrator of the VeeR core. /* verilator coverage_off */ input logic scan_mode, // To enable scan mode input logic mbist_mode, // to enable mbist diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu.sv index 5f7319bba..f02ba5d87 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu.sv @@ -22,7 +22,10 @@ import el2_pkg::*; ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan control + /*verilator coverage_on*/ input logic [1:0] dec_data_en, // Clock enable {x,r}, one cycle pulse input logic [1:0] dec_ctl_en, // Clock enable {x,r}, two cycle pulse diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv index 5fd027692..f339220a6 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv @@ -22,7 +22,10 @@ import el2_pkg::*; ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan control + /*verilator coverage_on*/ input logic flush_upper_x, // Branch flush from previous cycle input logic flush_lower_r, // Master flush of entire pipeline diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv index 696039408..9a8eb2d84 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv @@ -22,7 +22,10 @@ import el2_pkg::*; ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan mode + /*verilator coverage_on*/ input el2_div_pkt_t dp, // valid, sign, rem input logic [31:0] dividend, // Numerator @@ -140,7 +143,10 @@ module el2_exu_div_existing_1bit_cheapshortq ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan mode + /*verilator coverage_on*/ input logic cancel, // Flush pipeline input logic valid_in, @@ -448,7 +454,10 @@ module el2_exu_div_new_1bit_fullshortq ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan mode + /*verilator coverage_on*/ input logic cancel, // Flush pipeline input logic valid_in, @@ -706,7 +715,10 @@ module el2_exu_div_new_2bit_fullshortq ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan mode + /*verilator coverage_on*/ input logic cancel, // Flush pipeline input logic valid_in, @@ -980,7 +992,10 @@ module el2_exu_div_new_3bit_fullshortq ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan mode + /*verilator coverage_on*/ input logic cancel, // Flush pipeline input logic valid_in, @@ -1312,7 +1327,10 @@ module el2_exu_div_new_4bit_fullshortq ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan mode + /*verilator coverage_on*/ input logic cancel, // Flush pipeline input logic valid_in, diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv index 48e00b37b..a8cd32798 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv @@ -22,7 +22,10 @@ import el2_pkg::*; ( input logic clk, // Top level clock input logic rst_l, // Reset + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Scan mode + /*verilator coverage_on*/ input el2_mul_pkt_t mul_p, // {Valid, RS1 signed operand, RS2 signed operand, Select low 32-bits of result} diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv index 1d9858d13..68842a19d 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv @@ -214,7 +214,10 @@ import el2_pkg::*; output logic iccm_buf_correct_ecc, output logic iccm_correction_state, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); localparam TAGWIDTH = 2 ; diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv index 3d114a1f2..3648cd461 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv @@ -25,7 +25,10 @@ import el2_pkg::*; ) ( + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // Flop scan mode control + /*verilator coverage_on*/ input logic rst_l, // reset, active low input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv index 87a956ca3..a08c3c30d 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv @@ -75,7 +75,10 @@ import el2_pkg::*; output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option) + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv index 7e9765ae3..2b13d1335 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv @@ -54,7 +54,10 @@ import el2_pkg::*; output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, // ic_rd_hit[3:0] output logic ic_tag_perr, // Tag Parity error + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // Flop scan mode control + /*verilator coverage_on*/ ) ; @@ -113,7 +116,10 @@ import el2_pkg::*; input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit, input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ) ; @@ -824,7 +830,10 @@ import el2_pkg::*; output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, output logic ic_tag_perr, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ) ; logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] ic_tag_data_raw; diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv index 2ae73d762..a7f3752da 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv @@ -42,7 +42,10 @@ import el2_pkg::*; output logic [63:0] iccm_rd_data, // ICCM read data output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // Scan mode control + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv index 57c6f0b59..bac034cb8 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv @@ -30,7 +30,10 @@ import el2_pkg::*; input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. input logic rst_l, // reset enable, from core pin + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // scan + /*verilator coverage_on*/ input logic ic_hit_f, // Icache hit input logic ifu_ic_mb_empty, // Miss buffer empty diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv index 48ff2ab49..1fe098b56 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv @@ -194,7 +194,10 @@ import el2_pkg::*; input logic ifu_pmp_error, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); // Create different defines for ICACHE and ICCM enable combinations diff --git a/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh b/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh index 528d55de8..282fe960d 100644 --- a/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh +++ b/src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh @@ -50,6 +50,8 @@ logic csr_mitb0; logic csr_mitb1; logic csr_mitcnt0; logic csr_mitcnt1; +/* exclude signals that are tied to constant value in this file */ +/*verilator coverage_off*/ logic csr_perfva; logic csr_perfvb; logic csr_perfvc; @@ -59,6 +61,7 @@ logic csr_perfvf; logic csr_perfvg; logic csr_perfvh; logic csr_perfvi; +/*verilator coverage_on*/ logic csr_mpmc; logic csr_mcpc; logic csr_meicpct; diff --git a/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv b/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv index 51abd8403..cb833397d 100644 --- a/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv +++ b/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv @@ -30,7 +30,10 @@ import el2_pkg::*; input clk, input free_clk, input rst_l, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input scan_mode, + /*verilator coverage_on*/ input bus_clk_en, input clk_override, input dec_tlu_force_halt, diff --git a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv index 083989933..48a54fbf6 100644 --- a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv +++ b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv @@ -169,7 +169,10 @@ module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 ) input logic en, input logic clk, input logic rst_l, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ output logic [WIDTH-1:0] dout ); @@ -209,7 +212,10 @@ module rvdffpcie #( parameter WIDTH=31 ) input logic clk, input logic rst_l, input logic en, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ output logic [WIDTH-1:0] dout ); @@ -242,7 +248,10 @@ module rvdfflie #( parameter WIDTH=16, LEFT=8 ) input logic clk, input logic rst_l, input logic en, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ output logic [WIDTH-1:0] dout ); @@ -297,7 +306,10 @@ module rvdffppe #( parameter integer WIDTH = 39 ) input logic clk, input logic rst_l, input logic en, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ output logic [WIDTH-1:0] dout ); @@ -340,7 +352,10 @@ module rvdffie #( parameter WIDTH=1, OVERRIDE=0 ) input logic clk, input logic rst_l, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ output logic [WIDTH-1:0] dout ); @@ -383,7 +398,10 @@ module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 ) input logic clk, input logic rst_l, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ input logic en, output logic [WIDTH-1:0] dout ); @@ -780,7 +798,10 @@ module rvclkhdr ( input logic en, input logic clk, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ output logic l1clk ); @@ -800,7 +821,10 @@ module rvoclkhdr ( input logic en, input logic clk, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, + /*verilator coverage_on*/ output logic l1clk ); diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv index fd58f71cd..9ed2bf421 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv @@ -202,7 +202,10 @@ import el2_pkg::*; output logic lsu_dccm_rd_ecc_single_err, output logic lsu_dccm_rd_ecc_double_err, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // scan mode + /*verilator coverage_on*/ input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic rst_l, // reset, active low diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv index 16e6a6979..f838b50fa 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv @@ -53,7 +53,10 @@ import el2_pkg::*; input logic lsu_pmp_error_start, input logic lsu_pmp_error_end, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // Scan mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv index 80a97ddae..25ecfb1f4 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv @@ -31,7 +31,10 @@ import el2_pkg::*; input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic clk_override, // Override non-functional clock gating input logic rst_l, // reset, active low + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // scan mode + /*verilator coverage_on*/ input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals input logic dec_tlu_wb_coalescing_disable, // disable write buffer coalescing input logic dec_tlu_sideeffect_posted_disable, // Don't block the sideeffect load store to the bus diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv index 71622e92f..e3ee28414 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv @@ -30,7 +30,10 @@ import el2_pkg::*; input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic clk_override, // Override non-functional clock gating input logic rst_l, // reset, active low + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // scan mode + /*verilator coverage_on*/ input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals input logic dec_tlu_wb_coalescing_disable, // disable write buffer coalescing input logic dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_clkdomain.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_clkdomain.sv index e5b4abf8a..c4c87f785 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_clkdomain.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_clkdomain.sv @@ -73,7 +73,10 @@ import el2_pkg::*; output logic lsu_free_c2_clk, // free double pulse clock + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // Scan mode + /*verilator coverage_on*/ ); logic lsu_c1_m_clken, lsu_c1_r_clken; diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv index be9575c33..8293680b9 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv @@ -153,7 +153,10 @@ import el2_pkg::*; output logic [31:0] picm_wr_data, // write data input logic [31:0] picm_rd_data, // read data + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // scan mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv index 83bf5a90a..fe818a1fc 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv @@ -50,7 +50,10 @@ module el2_lsu_dccm_mem output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_ecc.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_ecc.sv index 99484e0af..59c204c51 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_ecc.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_ecc.sv @@ -35,7 +35,10 @@ import el2_pkg::*; input logic lsu_c2_r_clk, // clock input logic clk_override, // Override non-functional clock gating input logic rst_l, // reset, active low + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode, // scan mode + /*verilator coverage_on*/ input el2_lsu_pkt_t lsu_pkt_m, // packet in m input el2_lsu_pkt_t lsu_pkt_r, // packet in r diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv index 75d95acda..98d0b04d8 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv @@ -114,7 +114,10 @@ import el2_pkg::*; input logic lsu_pmp_error_start, input logic lsu_pmp_error_end, + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // Scan mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv index 2b19778ed..e14928892 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv @@ -81,7 +81,10 @@ import el2_pkg::*; output logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_m, // stbuf data output logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_m, // stbuf data + // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. + /*verilator coverage_off*/ input logic scan_mode // Scan mode + /*verilator coverage_on*/ ); diff --git a/src/riscv_core/veer_el2/rtl/riscv_rev_info b/src/riscv_core/veer_el2/rtl/riscv_rev_info index 8658a2dfb..b2718679a 100644 --- a/src/riscv_core/veer_el2/rtl/riscv_rev_info +++ b/src/riscv_core/veer_el2/rtl/riscv_rev_info @@ -1,8 +1,8 @@ -commit fe63594a775c1258a6fec06e574c4fe03f629cd4 -Merge: 78cac32bfcc 2d868166ce3 +commit 2388ae0ccd41cbcb301bf452a3c87561596ff45d +Merge: 3085254cc68 b6a17d0909b Author: Tomasz Michalak -Date: Fri Nov 8 15:57:47 2024 +0100 +Date: Mon Nov 18 10:44:23 2024 +0100 - Merge pull request #259 from chipsalliance/wsip/export_dmi + Merge pull request #269 from antmicro/kiryk/fix-custom-reports - export DMI signals + Fix custom report runs