From aacb888237ae2d8658fca58730c998327d160bb3 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Fri, 8 Dec 2023 22:29:58 +0000
Subject: [PATCH 01/17] Merged PR 137951: Increase ROM nightly regression
 timeout from 12 to 24 hours

Increase ROM nightly regression timeout from 12 to 24 hours

Related work items: #602523
---
 .../uvmf_caliptra_top_nightly_directed_regression.yml         | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml b/src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml
index 5baa312a8..dd668520b 100644
--- a/src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml
+++ b/src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml
@@ -7,8 +7,8 @@ contents:
       path: ""
       config:
         params:
-          # 12 hours
-          timeout: 720
+          # 24 hours
+          timeout: 1440
       weight: 100
       generations: 1
       formats: 

From 6b3f0f528c575e7116a9fa9f3bd885f2838cb05a Mon Sep 17 00:00:00 2001
From: Kiran Upadhyayula <kupadhyayula@microsoft.com>
Date: Mon, 11 Dec 2023 19:23:26 +0000
Subject: [PATCH 02/17] Merged PR 138140: Add delay to let KV writes finish
 before clear_secrets reg is modified

Delay to let KV writes finish on all clients before clear_secrets reg is programmed to avoid reg update issues in UVM

Related work items: #602886
---
 .../kv_env_pkg/src/kv_wr_rd_debug_sequence.svh           | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh
index 319fb1c02..ecde9fa38 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh
@@ -198,15 +198,16 @@ class kv_wr_rd_debug_sequence #(
         fork //clear secrets
             begin
                 repeat(20) begin
+                    configuration.kv_hmac_write_agent_config.wait_for_num_clocks(2);
+                    configuration.kv_sha512_write_agent_config.wait_for_num_clocks(2);
+                    configuration.kv_ecc_write_agent_config.wait_for_num_clocks(2);
+                    configuration.kv_doe_write_agent_config.wait_for_num_clocks(2); 
+                    
                     std::randomize(clear_secrets_data); //wren, debug_value0/1
 
                     reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this);
                     assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!")
 
-                    configuration.kv_hmac_write_agent_config.wait_for_num_clocks(2);
-                    configuration.kv_sha512_write_agent_config.wait_for_num_clocks(2);
-                    configuration.kv_ecc_write_agent_config.wait_for_num_clocks(2);
-                    configuration.kv_doe_write_agent_config.wait_for_num_clocks(2);
                 end //repeat
             end
             begin

From fb854a281ddd651e9d3825412440fc01db69f2a4 Mon Sep 17 00:00:00 2001
From: Michael Norris <michnorris@microsoft.com>
Date: Wed, 13 Dec 2023 19:54:34 +0000
Subject: [PATCH 03/17] Merged PR 138250: Patch for QVIP failure due to soc ifc
 arb perf bug

updating wait state count to 67 to accommodate perf bug in soc ifc arb

Wait state count worst case can last for two entire block reads from mailbox during the first/second block reads that occur with 2 clock delay (32 + 2 + 32 + 1)

two full block reads, 2 clock delay between, and 1 clock delay for SRAM read.

Related work items: #603171
---
 .../config_policies/ahb_lite_slave_0_config_policy.svh          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh b/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh
index 1057eb119..55943973e 100644
--- a/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh
+++ b/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh
@@ -121,7 +121,7 @@ class ahb_lite_slave_0_config_policy;
         //    // If true, drives previous address when bus is IDLE
         //    cfg.m_bfm.config_address_on_idle = 1'b0;
         //    // Maximum number of successive wait states
-              cfg.m_bfm.config_max_wait_states_count = 34;
+              cfg.m_bfm.config_max_wait_states_count = 67;
         //    // Data endianness
         //    cfg.m_bfm.config_endianness = AHB_LITTLE_ENDIAN;
         //    // Sets the domain

From 86d39ffc98afab2547b3e8df0fca164fa6a30b46 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Thu, 14 Dec 2023 23:48:38 +0000
Subject: [PATCH 04/17] Merged PR 138791: [UVM] Fix a prediction bug that
 results in missed 'expected' txn

Resolve UVM prediction bug by calculating if txn is expected closer to performing the reset prediction. This catches a missing 'expected' signal transition on mailbox_data_avail during a reset edge case.

Related work items: #604229
---
 .../soc_ifc_env_pkg/src/soc_ifc_predictor.svh                  | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
index 8ea5ce3e5..426b8eeac 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
@@ -3345,7 +3345,7 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
             begin: DELAY_INTERNAL_RESET_ASSERTION
             cptra_sb_ap_output_transaction_t local_cptra_sb_ap_txn;
             soc_ifc_sb_ap_output_transaction_t local_soc_ifc_sb_ap_txn;
-            bit send_soc_ifc_sts_txn = soc_ifc_status_txn_expected_after_noncore_reset();
+            bit send_soc_ifc_sts_txn;
 
             // Do the noncore reset
             `uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p results in assertion of internal resets after a delay", kind), UVM_MEDIUM)
@@ -3361,6 +3361,7 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
                 end
                 configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(SOC_IFC_CPTRA_RST_NONCORE_RST_DELAY);
             join
+            send_soc_ifc_sts_txn = soc_ifc_status_txn_expected_after_noncore_reset();
             // Synchronize the noncore reset with the reset of the environment and allow other
             // components to reset before proceeding with predicted activity
             reset_handled.trigger(noncore_reset_flag);

From 781db29883b1a27a6b17298974419791c5fca5b2 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Fri, 15 Dec 2023 00:04:02 +0000
Subject: [PATCH 05/17] Merged PR 138845: Filesystem merge from caliptra-rtl
 GitHub to MSFT internal

Manual file-copy sync from GH 'dev-msft' to MSFT internal repo.
Capture 1.0-rc2 updates for internal regressions.

Related work items: #604278
---
 src/sha512/formal/model/tb/sc_main.cpp | 15 +++++++++++++++
 src/sha512/formal/model/tb/tb.cpp      | 15 +++++++++++++++
 src/sha512/formal/model/tb/tb.h        | 15 +++++++++++++++
 3 files changed, 45 insertions(+)

diff --git a/src/sha512/formal/model/tb/sc_main.cpp b/src/sha512/formal/model/tb/sc_main.cpp
index 7bf012fe0..665c4db06 100644
--- a/src/sha512/formal/model/tb/sc_main.cpp
+++ b/src/sha512/formal/model/tb/sc_main.cpp
@@ -1,3 +1,18 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
 #include "systemc.h"
 #include "../Interfaces/Interfaces.h"
 #include "../sha512.h"
diff --git a/src/sha512/formal/model/tb/tb.cpp b/src/sha512/formal/model/tb/tb.cpp
index a4202ddf2..92efdec46 100644
--- a/src/sha512/formal/model/tb/tb.cpp
+++ b/src/sha512/formal/model/tb/tb.cpp
@@ -1,3 +1,18 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
 using namespace std;
 #include <array>
 #include "systemc.h"
diff --git a/src/sha512/formal/model/tb/tb.h b/src/sha512/formal/model/tb/tb.h
index 14218adcd..83a443291 100644
--- a/src/sha512/formal/model/tb/tb.h
+++ b/src/sha512/formal/model/tb/tb.h
@@ -1,3 +1,18 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
 #ifndef TB_H
 #define TB_H
 

From e6f173ce84342577a7780e6d116f1b2a39d5d42c Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Fri, 29 Dec 2023 19:20:26 +0000
Subject: [PATCH 06/17] Merged PR 140496: [UVM] Testcase enhancements

Add updates to improve code coverage in UVM regressions:
- Add extended checking in UVM regressions that throw errors for unexpected error interrupts from the SOC_IFC block (previously, the interrupts were serviced without being checked for context).
- Add randomization constraints to make interesting test values on PAUSER more likely to occur
- Update coverpoints for the RISC-V (VeeR) ECC error signals

Related work items: #608192
---
 ...oc_ifc_env_cptra_mbox_handler_sequence.svh |  3 +++
 ...mbox_rand_medium_interference_sequence.svh |  2 +-
 .../soc_ifc_env_mbox_rand_pauser_sequence.svh |  1 +
 ..._ifc_env_mbox_reg_axs_invalid_sequence.svh |  1 +
 .../soc_ifc_env_mbox_sequence_base.svh        | 25 ++++++++++++++++---
 ...env_mbox_sram_double_bit_flip_sequence.svh |  1 +
 ...v_top_mbox_rand_medium_unlock_sequence.svh |  1 +
 .../src/cptra_ctrl_transaction_coverage.svh   |  5 +++-
 8 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
index 028f82379..40a8ca6c3 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
@@ -370,6 +370,7 @@ task soc_ifc_env_cptra_mbox_handler_sequence::mbox_wait_and_force_unlock();
     // unlock causes this routine to break
     while(!inject_force_unlock) begin
         if (err_rsp_count > 0 && cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending) begin
+            unlock_proc_active = 1'b1;
             `uvm_info("CPTRA_MBOX_HANDLER", "Received soc_ifc_err_intr, clearing and (if needed) proceeding to mbox_unlock", UVM_MEDIUM)
             // Read and clear any error interrupts
             reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
@@ -380,6 +381,7 @@ task soc_ifc_env_cptra_mbox_handler_sequence::mbox_wait_and_force_unlock();
             err_rsp_count = 0;
             // Next, check if we need to proceed to mbox_unlock step
             if (!data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_cmd_fail_sts.get_lsb_pos()]) begin
+                unlock_proc_active = 1'b0;
                 continue;
             end
             reg_model.mbox_csr_rm.mbox_status.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
@@ -390,6 +392,7 @@ task soc_ifc_env_cptra_mbox_handler_sequence::mbox_wait_and_force_unlock();
                 `uvm_info("CPTRA_MBOX_HANDLER", "After servicing soc_ifc_err_intr, proceeding with mbox_unlock", UVM_MEDIUM)
                 break;
             end
+            unlock_proc_active = 1'b0;
         end
         configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(10/*TODO rand delays*/);
     end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_interference_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_interference_sequence.svh
index 058454ca9..0f3f699fe 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_interference_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_interference_sequence.svh
@@ -94,7 +94,7 @@ task soc_ifc_env_mbox_rand_medium_interference_sequence::mbox_poll_status();
         end
     end
     else if (sts == CMD_FAILURE) begin
-        `uvm_error("MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", sts))
+        `uvm_error("MBOX_SEQ", $sformatf("Received mailbox status %p unexpectedly, since no error is anticipated for this sequence", sts))
     end
     else if (sts == CMD_COMPLETE) begin
         if (mbox_resp_expected_dlen != 0)
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_pauser_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_pauser_sequence.svh
index e1bbe05c9..496b74b1c 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_pauser_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_pauser_sequence.svh
@@ -38,6 +38,7 @@ class soc_ifc_env_mbox_rand_pauser_sequence extends soc_ifc_env_mbox_sequence_ba
 
   function new(string name = "" );
     super.new(name);
+    this.mbox_sts_exp_error = 1;
   endfunction
 
 endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh
index 2cde1d81f..0a99d3eeb 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh
@@ -37,6 +37,7 @@ class soc_ifc_env_mbox_reg_axs_invalid_sequence extends soc_ifc_env_mbox_sequenc
 
   function new(string name = "" );
     super.new(name);
+    this.mbox_sts_exp_error = 1;
   endfunction
 
   //==========================================
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
index ceaee7f2a..acc5f8bce 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
@@ -41,6 +41,8 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
   uvm_event in_report_reg_sts;
   rand bit do_apb_lock_check;
   rand bit retry_failed_reg_axs;
+  bit mbox_sts_exp_error = 0; // Indicates this sequence will inject an error, which should manifest as a CMD_FAILURE response status
+                              // TODO make this more comprehensive/intelligent about randomized error injection
 
   typedef enum byte {
     DLY_ZERO,
@@ -563,11 +565,11 @@ task soc_ifc_env_mbox_sequence_base::mbox_poll_status();
         end
     end
     else if (data == CMD_FAILURE) begin
-        if (sts_rsp_count > 0 && soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending) begin
+        if (sts_rsp_count > 0 && soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending && mbox_sts_exp_error) begin
             `uvm_info("MBOX_SEQ", $sformatf("Unexpected mailbox status [%p] likely is the result of a spurious reg access injection specifically intended to cause a protocol violation or a mailbox SRAM double bit flip", data), UVM_HIGH)
         end
         else begin
-            `uvm_error("MBOX_SEQ", $sformatf("Received mailbox status %p unexpectedly, since there is no pending non_fatal error interrupt", data))
+            `uvm_error("MBOX_SEQ", $sformatf("Received mailbox status %p unexpectedly, since there is no pending non_fatal error interrupt (or error injection was unexpected)", data))
         end
     end
     else if (data == CMD_COMPLETE) begin
@@ -610,6 +612,8 @@ task soc_ifc_env_mbox_sequence_base::mbox_clr_execute();
         `uvm_error("MBOX_SEQ", "Unexpected error on read from CPTRA_HW_ERROR_NON_FATAL")
     end
     if (|err) begin
+        if (!mbox_sts_exp_error)
+            `uvm_error("MBOX_SEQ", "Observed error in CPTRA_HW_ERROR_NON_FATAL unexpectedly, since sequence was not anticipating mailbox ECC errors or protocol violations")
         `uvm_info("MBOX_SEQ", "Detected non-fatal errors at end of mailbox flow. Clearing.", UVM_LOW)
         reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.write(reg_sts, err, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(500)));
         if (reg_sts != UVM_IS_OK) begin
@@ -686,6 +690,13 @@ endfunction
 //              A legal addr_user is defined as:
 //               - A random selection from valid_users if the mbox_lock has yet to be acquired
 //               - The value in mbox_user if mbox_lock has been acquired already
+// NOTE:        In the context of this function, the term 'valid' is overloaded.
+//              mbox_valid_users contains the list of 'allowed' agent PAUSER values
+//              that have access to issue commands to the mailbox.
+//              Once the mailbox is locked, the only PAUSER value that is actually
+//              considered "valid" is the value that was locked - other entries from
+//              mbox_valid_users are not legal and will trigger protocol violations.
+//              This function uses the more restrictive definition to evaluate constraints.
 //==========================================
 function caliptra_apb_user soc_ifc_env_mbox_sequence_base::get_rand_user(int unsigned invalid_prob = FORCE_VALID_PAUSER);
     apb_user_obj = new();
@@ -699,7 +710,15 @@ function caliptra_apb_user soc_ifc_env_mbox_sequence_base::get_rand_user(int uns
                                              else
                                                  (addr_user inside {mbox_valid_users}) dist
                                                  {1 :/ 1000,
-                                                  0 :/ invalid_prob}; })
+                                                  0 :/ invalid_prob};
+                                             // When randomizing to a non-valid USER value after
+                                             // PAUSER has been locked, make the assigned USER value
+                                             // equally likely to be from the allowed agents as it is
+                                             // to be some totally random (non-allowed) value
+                                             if (pauser_locked.locked)
+                                                 (addr_user inside {mbox_valid_users}) dist
+                                                 {1 :/ 1,
+                                                  0 :/ 1}; })
         `uvm_error("MBOX_SEQ", "Failed to randomize APB PAUSER override value")
     else
         `uvm_info("MBOX_SEQ", $sformatf("Randomized APB PAUSER override value to 0x%x", this.apb_user_obj.addr_user), UVM_HIGH)
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh
index 22f0a3134..e9e9f013e 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh
@@ -45,6 +45,7 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se
 
   function new(string name = "" );
     super.new(name);
+    this.mbox_sts_exp_error = 1;
   endfunction
 
   //==========================================
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_medium_unlock_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_medium_unlock_sequence.svh
index 299e1d929..10ec8b8a7 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_medium_unlock_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_medium_unlock_sequence.svh
@@ -46,6 +46,7 @@ endfunction
 function soc_ifc_env_top_mbox_rand_medium_unlock_sequence::randomize_seqs();
     if(!soc_ifc_env_mbox_seq.randomize())
         `uvm_fatal("SOC_IFC_MBOX_TOP", $sformatf("soc_ifc_env_top_mbox_rand_medium_unlock_sequence::body() - %s randomization failed", soc_ifc_env_mbox_seq.get_type_name()));
+    soc_ifc_env_mbox_seq.mbox_sts_exp_error = 1'b1;
     if(!soc_ifc_env_cptra_handler_seq.randomize() with { inject_force_unlock == 1'b1; })
         `uvm_fatal("SOC_IFC_MBOX_TOP", $sformatf("soc_ifc_env_top_mbox_rand_medium_unlock_sequence::body() - %s randomization failed", soc_ifc_env_cptra_handler_seq.get_type_name()));
 endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction_coverage.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction_coverage.svh
index 8a1d6e013..4945067b0 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction_coverage.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction_coverage.svh
@@ -45,7 +45,10 @@ class cptra_ctrl_transaction_coverage  extends uvm_subscriber #(.T(cptra_ctrl_tr
     option.per_instance=1;
     assert_clear_secrets: coverpoint coverage_trans.assert_clear_secrets;
     iccm_axs_blocked: coverpoint coverage_trans.iccm_axs_blocked;
-    pulse_rv_ecc_error: coverpoint coverage_trans.pulse_rv_ecc_error;
+    pulse_rv_ic_single_ecc_error: coverpoint coverage_trans.pulse_rv_ecc_error.cptra_iccm_ecc_single_error;
+    pulse_rv_ic_double_ecc_error: coverpoint coverage_trans.pulse_rv_ecc_error.cptra_iccm_ecc_double_error;
+    pulse_rv_dc_single_ecc_error: coverpoint coverage_trans.pulse_rv_ecc_error.cptra_dccm_ecc_single_error;
+    pulse_rv_dc_double_ecc_error: coverpoint coverage_trans.pulse_rv_ecc_error.cptra_dccm_ecc_double_error;
     // pragma uvmf custom covergroup end
   endgroup
 

From 4b83147ec4843405b4ee2ac97500593789385989 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Fri, 29 Dec 2023 20:03:37 +0000
Subject: [PATCH 07/17] Merged PR 140812: [UVM] Fix for stale error report
 during rst sequence

Demote UVM_ERROR to UVM_INFO on unexpected transactions between cptra_rst_b->cptra_noncore_rst_b (this is a legal scenario)

Related work items: #608843
---
 .../bringup/cptra/soc_ifc_env_cptra_rst_wait_sequence.svh  | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra/soc_ifc_env_cptra_rst_wait_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra/soc_ifc_env_cptra_rst_wait_sequence.svh
index b2efda83d..118ff593d 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra/soc_ifc_env_cptra_rst_wait_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra/soc_ifc_env_cptra_rst_wait_sequence.svh
@@ -76,7 +76,12 @@ class soc_ifc_env_cptra_rst_wait_sequence extends soc_ifc_env_sequence_base #(.C
         core_rst_asserted = cptra_status_agent_rsp_seq.rsp.uc_rst_asserted;
         sts_rsp_count--;
         if (!noncore_rst_asserted || !core_rst_asserted)
-            `uvm_error("CPTRA_RESET_WAIT", "Unexpected status transition, with noncore/core resets deasserted, while waiting for noncore reset to assert")
+            // This might be an error, but the delay from cptra_rst_b -> cptra_noncore_rst_b
+            // means that some additional activity might complete before the noncore rst asserts.
+            // That activity might be legal, so this is an INFO and not an ERROR.
+            // soc_ifc_predictor is responsible for detecting invalid activity during a
+            // reset condition.
+            `uvm_info("CPTRA_RESET_WAIT", "Unexpected status transition, with noncore/core resets deasserted, while waiting for noncore reset to assert!", UVM_LOW)
         else
             `uvm_info("CPTRA_RESET_WAIT", "Detected Caliptra noncore reset assertion", UVM_LOW)
     end

From f7cb22fdd166ae5e7443faebc51156e707afa833 Mon Sep 17 00:00:00 2001
From: Kiran Upadhyayula <kupadhyayula@microsoft.com>
Date: Wed, 3 Jan 2024 18:41:55 +0000
Subject: [PATCH 08/17] Merged PR 141156: Delayed prediction for clear_secrets
 reg

Updates to UVM to delay KV clear by 1 clk when clear_secrets reg is set
Updates to sequence to turn on scan mode, perform writes and then turn off scan mode

Related work items: #609997
---
 .../kv_env_pkg/src/kv_predictor.svh           | 69 ++++++++++++++-----
 .../src/kv_wr_rd_debug_sequence.svh           | 49 +++++++------
 .../src/kv_rst_scan_on_sequence.svh           |  1 +
 3 files changed, 78 insertions(+), 41 deletions(-)

diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh
index d17b1a2ac..2dc9b85d7 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh
@@ -210,6 +210,8 @@ class kv_predictor #(
   // int unsigned job_end_count[time];
   // bit write_entry_pending = 0;
   // bit send_hmac_write_txn = 0;
+  logic [KV_NUM_KEYS-1:0] clear_secrets_debug0 = 0; 
+  logic [KV_NUM_KEYS-1:0] clear_secrets_debug1 = 0;
   bit set_val_ctrl_derived = 0;
   logic [KV_NUM_KEYS-1:0] val_ctrl_derived_data = 0;
   logic [KV_NUM_KEYS-1:0] key_entry_ctrl_we = 0;
@@ -221,6 +223,7 @@ class kv_predictor #(
   extern function void populate_expected_kv_read_txn(ref kv_sb_ap_output_transaction_t t_expected, kv_read_transaction t_received, string client);
   extern function void populate_expected_kv_write_txn(ref kv_sb_ap_output_transaction_write_t t_expected, kv_write_transaction t_received);
   extern task          poll_and_run_delay_jobs();
+  extern task          poll_and_run_clr_secrets_delay_job();
   // extern function      send_delayed_expected_transactions_hmac_write(kv_write_transaction t);
   // extern function      send_delayed_expected_transactions_sha512_write(kv_write_transaction t);
   // extern function      send_delayed_expected_transactions_ecc_write(kv_write_transaction t);
@@ -292,6 +295,7 @@ class kv_predictor #(
   task run_phase (uvm_phase phase);
     fork
       poll_and_run_delay_jobs();
+      poll_and_run_clr_secrets_delay_job();
     join_none
     super.run_phase(phase);
   endtask
@@ -323,6 +327,8 @@ class kv_predictor #(
       p_kv_rm.reset(); //all regs cleared on hard rst
       for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
         last_dword_written[entry] = 'h0; //Clear last dword on hard rst
+        // clear_secrets_debug0[entry] = 'h0;
+        // clear_secrets_debug1[entry] = 'h0;
       end
       key_ctrl_lock_wr = 'h0;
       key_ctrl_lock_use = 'h0;
@@ -332,22 +338,18 @@ class kv_predictor #(
       p_kv_rm.val_reg.debug_mode_unlocked.set(1'b1);
       p_kv_rm.val_reg.cptra_in_debug_scan_mode.set(1'b1);
       
-      `uvm_info("PRED", "Clear_secrets reg is set in debug/scan mode. Flushing KV", UVM_MEDIUM)
+      `uvm_info("PRED", "Debug mode switch, KV will be flushed", UVM_MEDIUM)
       if (clear_secrets_data[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()] == 'h1) begin
         for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
           //Debug mode should flush all regs inspite of locks
-          for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
-            p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_1);
-            p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_1);
-          end
+          clear_secrets_debug0[entry] = 'h0;
+          clear_secrets_debug1[entry] = 'h1;
         end
       end
       else begin
         for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
-          for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
-            p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_0);
-            p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_0);
-          end
+          clear_secrets_debug0[entry] = 'h1;
+          clear_secrets_debug1[entry] = 'h0;
         end
       end
     end
@@ -655,31 +657,27 @@ class kv_predictor #(
           //Only allow clear operation if in debug mode
           //if (data_active[1:0] == 'h1) begin
           if (data_active [p_kv_rm.kv_reg_rm.CLEAR_SECRETS.wr_debug_values.get_lsb_pos()] && !data_active[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()]) begin
-            `uvm_info("PRED", "Clear_secrets reg is set in debug/scan mode. Flushing KV with DEBUG0 values", UVM_MEDIUM)
+            `uvm_info("PRED", "Clear_secrets reg is set in debug/scan mode", UVM_MEDIUM)
             for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
               //Read locks before clearing - do not clear if locked
               kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry));
               kv_reg_data = kv_reg.get_mirrored_value();
               if(kv_reg_data[1:0] == 2'b00) begin
-                for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin              
-                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_0);
-                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_0);
-                end
+                clear_secrets_debug0[entry] = 'h1;
+                clear_secrets_debug1[entry] = 'h0;
               end
             end
           end
           //else if(data_active[1:0] == 'h3) begin
           else if (data_active [p_kv_rm.kv_reg_rm.CLEAR_SECRETS.wr_debug_values.get_lsb_pos()] && data_active[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()]) begin
-            `uvm_info("PRED", "Clear_secrets reg is set in debug/scan mode. Flushing KV with DEBUG1 values", UVM_MEDIUM)
+            `uvm_info("PRED", "Clear_secrets reg is set in debug/scan mode", UVM_MEDIUM)
             for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
               //Read locks before clearing
               kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry));
               kv_reg_data = kv_reg.get_mirrored_value();
               if(kv_reg_data[1:0] == 2'b00) begin
-                for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
-                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_1);
-                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_1);
-                end
+                clear_secrets_debug0[entry] = 'h0;
+                clear_secrets_debug1[entry] = 'h1;
               end
             end
           end
@@ -967,5 +965,38 @@ endclass
       configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1);
     end
   endtask
+
+  task kv_predictor::poll_and_run_clr_secrets_delay_job();
+    int entry, offset;
+    forever begin
+      fork
+        begin
+          //CLEAR SECRETS:
+          configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1);
+          `uvm_info("Delay Jobs",$sformatf(" |clear_secrets_debug0 = %b, |debug1 = %b\n", |clear_secrets_debug0, |clear_secrets_debug1), UVM_DEBUG)
+          if (|clear_secrets_debug0 || |clear_secrets_debug1) begin
+            `uvm_info("Delay Jobs", "Flushing key vault", UVM_MEDIUM)
+            for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
+              if(clear_secrets_debug0[entry] == 'h1) begin
+                for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
+                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_0);
+                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_0);
+                end
+                clear_secrets_debug0[entry] = 'h0;
+              end
+              else if (clear_secrets_debug1[entry]== 'h1) begin
+                for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
+                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_1);
+                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_1);
+                end
+                clear_secrets_debug1[entry] = 'h0;
+              end
+            end //for loop
+          end //if block
+        end //begin
+      join_none
+      configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1);
+    end
+  endtask
 // pragma uvmf custom external end
 
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh
index ecde9fa38..f8138067d 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh
@@ -167,7 +167,7 @@ class kv_wr_rd_debug_sequence #(
             end
             join
         
-            `uvm_info("DEBUG_WR_RD", "Waiting for sha512 write/read to finish", UVM_FULL)
+        `uvm_info("DEBUG_WR_RD", "Waiting for sha512 write/read to finish", UVM_MEDIUM)
         configuration.kv_rst_agent_config.wait_for_num_clocks(1000);
         configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1000);
         configuration.kv_sha512_write_agent_config.wait_for_num_clocks(1000);
@@ -179,35 +179,40 @@ class kv_wr_rd_debug_sequence #(
         configuration.kv_ecc_privkey_read_agent_config.wait_for_num_clocks(1000);
         configuration.kv_ecc_seed_read_agent_config.wait_for_num_clocks(1000);
 
-        `uvm_info("DEBUG_WR_RD", "Scan mode and queue writes", UVM_FULL)
-        fork //debug mode
-            begin
-                kv_rst_agent_scan_on_seq.start(configuration.kv_rst_agent_config.sequencer);
-            end
-            begin
-                queue_writes();
-                //Wait for these writes to finish before setting next CTRL reg to avoid collision (test trying to write to CTRL and predictor trying to read from CTRL)
-                configuration.kv_hmac_write_agent_config.wait_for_num_clocks(100);
-                configuration.kv_sha512_write_agent_config.wait_for_num_clocks(100);
-                configuration.kv_ecc_write_agent_config.wait_for_num_clocks(100);
-                configuration.kv_doe_write_agent_config.wait_for_num_clocks(100);
-            end
-        join
-
-        `uvm_info("DEBUG_WR_RD", "clear_secrets and queue writes", UVM_FULL)
+        `uvm_info("DEBUG_WR_RD", "Scan mode and queue writes", UVM_MEDIUM)
+        `uvm_info("DEBUG_WR_RD", "Turning on scan mode", UVM_MEDIUM)
+        
+        kv_rst_agent_scan_on_seq.start(configuration.kv_rst_agent_config.sequencer);
+        
+        `uvm_info("DEBUG_WR_RD", "Queuing writes", UVM_MEDIUM)
+        queue_writes();
+        //Wait for these writes to finish before setting next CTRL reg to avoid collision (test trying to write to CTRL and predictor trying to read from CTRL)
+        configuration.kv_hmac_write_agent_config.wait_for_num_clocks(100);
+        configuration.kv_sha512_write_agent_config.wait_for_num_clocks(100);
+        configuration.kv_ecc_write_agent_config.wait_for_num_clocks(100);
+        configuration.kv_doe_write_agent_config.wait_for_num_clocks(100);
+
+        `uvm_info("DEBUG_WR_RD", "Turning off scan mode", UVM_MEDIUM)
+        kv_rst_agent_scan_off_seq.start(configuration.kv_rst_agent_config.sequencer);
+
+        `uvm_info("DEBUG_WR_RD", "clear_secrets and queue writes", UVM_MEDIUM)
         fork //clear secrets
             begin
                 repeat(20) begin
-                    configuration.kv_hmac_write_agent_config.wait_for_num_clocks(2);
-                    configuration.kv_sha512_write_agent_config.wait_for_num_clocks(2);
-                    configuration.kv_ecc_write_agent_config.wait_for_num_clocks(2);
-                    configuration.kv_doe_write_agent_config.wait_for_num_clocks(2); 
+                    configuration.kv_hmac_write_agent_config.wait_for_num_clocks(5);
+                    configuration.kv_sha512_write_agent_config.wait_for_num_clocks(5);
+                    configuration.kv_ecc_write_agent_config.wait_for_num_clocks(5);
+                    configuration.kv_doe_write_agent_config.wait_for_num_clocks(5); 
                     
                     std::randomize(clear_secrets_data); //wren, debug_value0/1
 
                     reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this);
                     assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!")
-
+                    
+                    configuration.kv_hmac_write_agent_config.wait_for_num_clocks(5);
+                    configuration.kv_sha512_write_agent_config.wait_for_num_clocks(5);
+                    configuration.kv_ecc_write_agent_config.wait_for_num_clocks(5);
+                    configuration.kv_doe_write_agent_config.wait_for_num_clocks(5); 
                 end //repeat
             end
             begin
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh
index 960931259..97c66f90d 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_scan_on_sequence.svh
@@ -57,6 +57,7 @@ class kv_rst_scan_on_sequence extends kv_rst_sequence_base;
     req.assert_core_rst = 1'b0;
     req.debug_mode = 1'b1;
     req.scan_mode = 1'b1;
+    req.wait_cycles = 'h0;
     
     finish_item(req);
     `uvm_info("KV_RST_SCAN_ON", {"Response:",req.convert2string()},UVM_MEDIUM)

From e3fc3b0ddb6aff48ca1fa204e34236b6db87e87d Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Thu, 4 Jan 2024 20:30:58 +0000
Subject: [PATCH 09/17] Merged PR 141380: [SVA] Add assertions for bus-idle
 condition during fw upd rst

Add assertions for bus-idle condition during fw upd rst

Related work items: #610696
---
 src/integration/asserts/caliptra_top_sva.sv | 57 +++++++++++++++------
 1 file changed, 42 insertions(+), 15 deletions(-)

diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv
index cdb92c125..1eb03a3a7 100644
--- a/src/integration/asserts/caliptra_top_sva.sv
+++ b/src/integration/asserts/caliptra_top_sva.sv
@@ -24,22 +24,29 @@
 `else
 `define CPTRA_TB_TOP_NAME caliptra_top_tb
 `endif
-`define CPTRA_TOP_PATH  `CPTRA_TB_TOP_NAME.caliptra_top_dut
-`define KEYVAULT_PATH   `CPTRA_TOP_PATH.key_vault1
-`define DOE_INST_PATH   `CPTRA_TOP_PATH.doe.doe_inst
-`define DOE_PATH        `DOE_INST_PATH.doe_fsm1
-`define DOE_REG_PATH    `DOE_INST_PATH.i_doe_reg
-`define SERVICES_PATH   `CPTRA_TB_TOP_NAME.tb_services_i
-`define SHA512_PATH     `CPTRA_TOP_PATH.sha512.sha512_inst
-`define HMAC_PATH       `CPTRA_TOP_PATH.hmac.hmac_inst
-`define ECC_PATH        `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i
-`define ECC_REG_PATH    `CPTRA_TOP_PATH.ecc_top1.ecc_reg1
-`define SHA256_PATH     `CPTRA_TOP_PATH.sha256.sha256_inst
-`define SHA512_MASKED_PATH `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i.ecc_hmac_drbg_interface_i.hmac_drbg_i.HMAC_K.u_sha512_core_h1
-`define SOC_IFC_TOP_PATH   `CPTRA_TOP_PATH.soc_ifc_top1
-`define WDT_PATH        `SOC_IFC_TOP_PATH.i_wdt
+`define CPTRA_TOP_PATH      `CPTRA_TB_TOP_NAME.caliptra_top_dut
+`define KEYVAULT_PATH       `CPTRA_TOP_PATH.key_vault1
+`define KEYVAULT_REG_PATH   `KEYVAULT_PATH.kv_reg1
+`define PCRVAULT_PATH       `CPTRA_TOP_PATH.pcr_vault1
+`define PCRVAULT_REG_PATH   `PCRVAULT_PATH.pv_reg1
+`define DATA_VAULT_PATH     `CPTRA_TOP_PATH.data_vault1
+`define DATA_VAULT_REG_PATH `DATA_VAULT_PATH.dv_reg1
+`define DOE_INST_PATH       `CPTRA_TOP_PATH.doe.doe_inst
+`define DOE_PATH            `DOE_INST_PATH.doe_fsm1
+`define DOE_REG_PATH        `DOE_INST_PATH.i_doe_reg
+`define SERVICES_PATH       `CPTRA_TB_TOP_NAME.tb_services_i
+`define SHA512_PATH         `CPTRA_TOP_PATH.sha512.sha512_inst
+`define HMAC_PATH           `CPTRA_TOP_PATH.hmac.hmac_inst
+`define HMAC_REG_PATH       `HMAC_PATH.i_hmac_reg
+`define ECC_PATH            `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i
+`define ECC_REG_PATH        `CPTRA_TOP_PATH.ecc_top1.ecc_reg1
+`define SHA256_PATH         `CPTRA_TOP_PATH.sha256.sha256_inst
+`define SHA512_MASKED_PATH  `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i.ecc_hmac_drbg_interface_i.hmac_drbg_i.HMAC_K.u_sha512_core_h1
+`define SOC_IFC_TOP_PATH    `CPTRA_TOP_PATH.soc_ifc_top1
+`define WDT_PATH            `SOC_IFC_TOP_PATH.i_wdt
 
 `define SVA_RDC_CLK `CPTRA_TOP_PATH.rdc_clk_cg
+`define CPTRA_FW_UPD_RST_WINDOW `SOC_IFC_TOP_PATH.i_soc_ifc_boot_fsm.fw_update_rst_window
 `ifdef UVMF_CALIPTRA_TOP
   `define SVA_CLK `CPTRA_TB_TOP_NAME.clk
   `define SVA_RST `CPTRA_TB_TOP_NAME.soc_ifc_subenv_soc_ifc_ctrl_agent_bus.cptra_rst_b
@@ -552,5 +559,25 @@ module caliptra_top_sva
                                       `ECC_PATH.ecc_arith_unit_i.ecc_instr_s.opcode.mult_we |-> (`ECC_PATH.ecc_arith_unit_i.mult_res_s < `ECC_PATH.ecc_arith_unit_i.adder_prime)
                                       )
                           else $display("SVA ERROR: ECC multiplier result is not valid!"); 
-endmodule
 
+  // Bus IDLE on Firmware Update Reset
+  fw_upd_rst_doe_idle:     assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`DOE_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: DOE bus not idle after Firmware Update Reset!");
+  fw_upd_rst_ecc_idle:     assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`ECC_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: ECC bus not idle after Firmware Update Reset!");
+  fw_upd_rst_hmac_idle:    assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`HMAC_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: HMAC bus not idle after Firmware Update Reset!");
+  fw_upd_rst_kv_idle:      assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`KEYVAULT_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: Key Vault bus not idle after Firmware Update Reset!");
+  fw_upd_rst_pv_idle:      assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`PCRVAULT_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: PCR Vault bus not idle after Firmware Update Reset!");
+  fw_upd_rst_dv_idle:      assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`DATA_VAULT_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: Data Vault bus not idle after Firmware Update Reset!");
+  fw_upd_rst_sha256_idle:  assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`SHA256_PATH.i_sha256_reg.s_cpuif_req)
+                           else $display("SVA ERROR: SHA256 bus not idle after Firmware Update Reset!");
+  fw_upd_rst_sha512_idle:  assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`SHA512_PATH.i_sha512_reg.s_cpuif_req)
+                           else $display("SVA ERROR: SHA512 bus not idle after Firmware Update Reset!");
+  fw_upd_rst_soc_ifc_idle: assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`SOC_IFC_TOP_PATH.i_ahb_slv_sif_soc_ifc.dv)
+                           else $display("SVA ERROR: SHA512 bus not idle after Firmware Update Reset!");
+
+endmodule

From ca096879c0049261a0a65a1335162dba34d57290 Mon Sep 17 00:00:00 2001
From: Kiran Upadhyayula <kupadhyayula@microsoft.com>
Date: Thu, 4 Jan 2024 22:42:01 +0000
Subject: [PATCH 10/17] Merged PR 141389: Reenable cg tests in L0 regression

Reenable cg tests in L0 regression

Related work items: #610712
---
 src/integration/stimulus/L0_regression.yml    |  6 ++---
 .../smoke_test_doe_cg/smoke_test_doe_cg.c     | 27 +++++++++++++++++--
 .../smoke_test_kv_cg/smoke_test_kv_cg.c       |  5 ++++
 tools/scripts/run_verilator_l0_regression.py  |  2 +-
 4 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/src/integration/stimulus/L0_regression.yml b/src/integration/stimulus/L0_regression.yml
index 2614e6710..c8b240084 100644
--- a/src/integration/stimulus/L0_regression.yml
+++ b/src/integration/stimulus/L0_regression.yml
@@ -9,7 +9,7 @@ contents:
         #add back for aes
         #- ../test_suites/smoke_test_aes/smoke_test_aes.yml
         - ../test_suites/smoke_test_mbox/smoke_test_mbox.yml
-        #- ../test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
+        - ../test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
         - ../test_suites/smoke_test_sha512/smoke_test_sha512.yml
         - ../test_suites/smoke_test_sha256/smoke_test_sha256.yml
         - ../test_suites/smoke_test_sha_accel/smoke_test_sha_accel.yml
@@ -37,7 +37,7 @@ contents:
         - ../test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.yml
         - ../test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.yml
         - ../test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.yml
-        #- ../test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
+        - ../test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
         - ../test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
         - ../test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
         - ../test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
@@ -47,7 +47,7 @@ contents:
         - ../test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml
         - ../test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml
         - ../test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
-        #- ../test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
+        - ../test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
         # data vault tests
         - ../test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.yml
         - ../test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.yml
diff --git a/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.c b/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.c
index abab48c5c..04ab79691 100644
--- a/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.c
+++ b/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.c
@@ -94,7 +94,6 @@ void main() {
     //Call interrupt init
     init_interrupts();
 
-    if (rst_count == 1) {
     //Enable clk gating and halt core
     SEND_STDOUT_CTRL(0xf2);
     set_mit0(mitb0, mie_timer0_en);
@@ -106,7 +105,31 @@ void main() {
     SEND_STDOUT_CTRL(0xec);
     *doe_ctrl = 0x0000000D;
 
-    printf("Dummy\n");
+    __asm__ volatile ("csrwi    %0, %1" \
+                    : /* output: none */        \
+                    : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                    : /* clobbers: none */);
+
+    // //Poll for DOE status
+    while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+        doe_status_int = *doe_status;
+        doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+    }
+
+    //Clear doe_status_int
+    doe_status_int = 0;
+    
+    //--------------------------------------------------------------------
+    //Enable clk gating and halt core
+    SEND_STDOUT_CTRL(0xf2);
+    set_mit0(mitb0, mie_timer0_en);
+    
+    printf("Rand FE\n");
+
+    //Start FE and store in KV7
+    SEND_STDOUT_CTRL(0xed);
+    *doe_ctrl = 0x0000001E;
+
     __asm__ volatile ("csrwi    %0, %1" \
                     : /* output: none */        \
                     : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
diff --git a/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.c b/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.c
index c90f3fcf6..6929ed929 100644
--- a/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.c
+++ b/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.c
@@ -140,6 +140,11 @@ void main() {
     VPRINTF(LOW, "Starting UDS again\n");
     *doe_ctrl = 0x00000001;
 
+    //Enable clk gating and halt core
+    // SEND_STDOUT_CTRL(0xf2);
+    set_mit0(mitb0, mie_timer0_en);
+    halt_core();
+
     // //Poll for DOE status
     doe_status_int = 0x00000000;
         while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
diff --git a/tools/scripts/run_verilator_l0_regression.py b/tools/scripts/run_verilator_l0_regression.py
index a4cbbd2ee..05a1f5c84 100644
--- a/tools/scripts/run_verilator_l0_regression.py
+++ b/tools/scripts/run_verilator_l0_regression.py
@@ -123,7 +123,7 @@ def getTestNames():
         # Skip clk gating tests in Verilator until PC issue is resolved
         # https://github.com/chipsalliance/Cores-VeeR-EL2/issues/88
         # https://github.com/chipsalliance/caliptra-rtl/issues/126
-        if (re.search(r'(smoke_test_clk_gating|smoke_test_cg_wdt)',x.groups()[0])) :
+        if (re.search(r'(smoke_test_clk_gating|smoke_test_cg_wdt|smoke_test_mbox_cg|smoke_test_kv_cg|smoke_test_doe_cg)',x.groups()[0])) :
             continue
         integrationTestSuiteList.append(x.groups()[0])
 

From 31c3fa7ffa56b4c7f03648da60e4f02044d8c74f Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Wed, 10 Jan 2024 23:45:22 +0000
Subject: [PATCH 11/17] Merged PR 142708: [Regression] Logging and disk space
 fixups

Disable verbose trace logs by default to reduce disk requirement for regressions
Also fix a typo in an assertion error message

Related work items: #611074, #613438
---
 src/integration/asserts/caliptra_top_sva.sv    |  2 +-
 src/integration/tb/caliptra_top_tb_services.sv | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv
index 1eb03a3a7..619690d92 100644
--- a/src/integration/asserts/caliptra_top_sva.sv
+++ b/src/integration/asserts/caliptra_top_sva.sv
@@ -578,6 +578,6 @@ module caliptra_top_sva
   fw_upd_rst_sha512_idle:  assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`SHA512_PATH.i_sha512_reg.s_cpuif_req)
                            else $display("SVA ERROR: SHA512 bus not idle after Firmware Update Reset!");
   fw_upd_rst_soc_ifc_idle: assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`SOC_IFC_TOP_PATH.i_ahb_slv_sif_soc_ifc.dv)
-                           else $display("SVA ERROR: SHA512 bus not idle after Firmware Update Reset!");
+                           else $display("SVA ERROR: SOC_IFC bus not idle after Firmware Update Reset!");
 
 endmodule
diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv
index 8d167d0e7..400aa8c85 100644
--- a/src/integration/tb/caliptra_top_tb_services.sv
+++ b/src/integration/tb/caliptra_top_tb_services.sv
@@ -1059,7 +1059,7 @@ endgenerate //IV_NO
         wb_valid  <= `DEC.dec_i0_wen_r;
         wb_dest   <= `DEC.dec_i0_waddr_r;
         wb_data   <= `DEC.dec_i0_wdata_r;
-        if (caliptra_top_dut.trace_rv_i_valid_ip && !$test$plusargs("CLP_REGRESSION")) begin
+        if (caliptra_top_dut.trace_rv_i_valid_ip && $test$plusargs("CLP_BUS_LOGS")) begin
 
            $fwrite(tp,"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", caliptra_top_dut.trace_rv_i_valid_ip, 0, caliptra_top_dut.trace_rv_i_address_ip,
                   0, caliptra_top_dut.trace_rv_i_insn_ip,caliptra_top_dut.trace_rv_i_exception_ip,caliptra_top_dut.trace_rv_i_ecause_ip,
@@ -1074,18 +1074,18 @@ endgenerate //IV_NO
                    );
         end
         if(`DEC.dec_nonblock_load_wen) begin
-            if (!$test$plusargs("CLP_REGRESSION")) $fwrite (el, "%10d : %32s=%h ; nbL\n", cycleCnt, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
+            if ($test$plusargs("CLP_BUS_LOGS")) $fwrite (el, "%10d : %32s=%h ; nbL\n", cycleCnt, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
             caliptra_top_tb_services.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;
         end
         if(`DEC.exu_div_wren) begin
-            if (!$test$plusargs("CLP_REGRESSION")) $fwrite (el, "%10d : %32s=%h ; nbD\n", cycleCnt, abi_reg[`DEC.div_waddr_wb], `DEC.exu_div_result);
+            if ($test$plusargs("CLP_BUS_LOGS")) $fwrite (el, "%10d : %32s=%h ; nbD\n", cycleCnt, abi_reg[`DEC.div_waddr_wb], `DEC.exu_div_result);
             caliptra_top_tb_services.gpr[0][`DEC.div_waddr_wb] = `DEC.exu_div_result;
         end
     end
 
     // IFU Initiator monitor
     always @(posedge clk) begin
-        if (!$test$plusargs("CLP_REGRESSION"))
+        if (!$test$plusargs("CLP_BUS_LOGS"))
         $fstrobe(ifu_p, "%10d : 0x%0h %h %b %h %h %h %b 0x%08h_%08h %b %b\n", cycleCnt, 
                         caliptra_top_dut.ic_haddr, caliptra_top_dut.ic_hburst, caliptra_top_dut.ic_hmastlock, 
                         caliptra_top_dut.ic_hprot, caliptra_top_dut.ic_hsize, caliptra_top_dut.ic_htrans, 
@@ -1095,7 +1095,7 @@ endgenerate //IV_NO
 
     // LSU Initiator monitor
     always @(posedge clk) begin
-        if (!$test$plusargs("CLP_REGRESSION"))
+        if ($test$plusargs("CLP_BUS_LOGS"))
         $fstrobe(lsu_p, "%10d : 0x%0h %h %h %b 0x%08h_%08h 0x%08h_%08h %b %b\n", cycleCnt, 
                         caliptra_top_dut.initiator_inst.haddr, caliptra_top_dut.initiator_inst.hsize, caliptra_top_dut.initiator_inst.htrans, 
                         caliptra_top_dut.initiator_inst.hwrite, caliptra_top_dut.initiator_inst.hrdata[63:32], caliptra_top_dut.initiator_inst.hrdata[31:0], 
@@ -1108,7 +1108,7 @@ endgenerate //IV_NO
     generate
         for (sl_i = 0; sl_i < `CALIPTRA_AHB_SLAVES_NUM; sl_i = sl_i + 1) begin: gen_responder_inf_monitor
             always @(posedge clk) begin
-                if (!$test$plusargs("CLP_REGRESSION"))
+                if ($test$plusargs("CLP_BUS_LOGS"))
                 $fstrobe(sl_p[sl_i], "%10d : 0x%0h %h %h %b 0x%08h_%08h 0x%08h_%08h %b %b %b %b\n", cycleCnt, 
                         caliptra_top_dut.responder_inst[sl_i].haddr, caliptra_top_dut.responder_inst[sl_i].hsize, caliptra_top_dut.responder_inst[sl_i].htrans, 
                         caliptra_top_dut.responder_inst[sl_i].hwrite, caliptra_top_dut.responder_inst[sl_i].hrdata[63:32], caliptra_top_dut.responder_inst[sl_i].hrdata[31:0], 
@@ -1167,13 +1167,13 @@ endgenerate //IV_NO
         if (!hex_file_is_empty) $readmemh("dccm.hex",     dummy_dccm_preloader.ram,0,32'h0001_FFFF);
         hex_file_is_empty = $system("test -s iccm.hex");
         if (!hex_file_is_empty) $readmemh("iccm.hex",     dummy_iccm_preloader.ram,0,32'h0001_FFFF);
-        if (!$test$plusargs("CLP_REGRESSION")) begin
+        if ($test$plusargs("CLP_BUS_LOGS")) begin
             tp = $fopen("trace_port.csv","w");
             el = $fopen("exec.log","w");
             ifu_p = $fopen("ifu_master_ahb_trace.log", "w");
             lsu_p = $fopen("lsu_master_ahb_trace.log", "w");
         end
-        if (!$test$plusargs("CLP_REGRESSION")) begin
+        if ($test$plusargs("CLP_BUS_LOGS")) begin
             $fwrite (el, "//   Cycle : #inst    0    pc    opcode    reg=value   ; mnemonic\n");
             $fwrite(ifu_p, "//   Cycle: ic_haddr     ic_hburst     ic_hmastlock     ic_hprot     ic_hsize     ic_htrans     ic_hwrite     ic_hrdata     ic_hwdata     ic_hready     ic_hresp\n");
             $fwrite(lsu_p, "//   Cycle: lsu_haddr     lsu_hsize     lsu_htrans     lsu_hwrite     lsu_hrdata     lsu_hwdata     lsu_hready     lsu_hresp\n");

From 29b8dc47fbdf4d83df6897b7f5b76bd7bdacfdb0 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Thu, 18 Jan 2024 18:03:21 -0800
Subject: [PATCH 12/17] Add smoke_test_clk_gating yml file

---
 .../smoke_test_clk_gating.yml                 |  17 ++
 .../smoke_test_clk_gating_asm.s               | 242 ++++++++++++++++++
 2 files changed, 259 insertions(+)
 create mode 100644 src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml
 create mode 100644 src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s

diff --git a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml
new file mode 100644
index 000000000..d919ef2e9
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_clk_gating
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s
new file mode 100644
index 000000000..29fdaecfc
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+// Assembly code for Hello World
+// Not using only ALU ops for creating the string
+
+
+#include "../includes/caliptra_defines.h"
+//#include "../smoke_test_sha512/smoke_test_sha512_vectors.s"
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+    // Clear minstret
+    csrw minstret, zero
+    csrw minstreth, zero
+
+    // Set up MTVEC - not expecting to use it though
+    li x1, RV_ICCM_SADR
+    csrw mtvec, x1
+
+    la sp, STACK
+
+    call init_interrupts
+
+    // Enable Caches in MRAC
+    li x1, 0xaaaaaaaa
+    csrw 0x7c0, x1
+
+    
+    
+   
+
+//----------------------------------------------------
+//Wake up using internal timer0
+//----------------------------------------------------
+    //Internal timer 0 counter 
+    li x1, 0x00000000
+    csrw 0x7d2,x1
+
+    //Internal timer 0 upper bound
+    li x1, 0x00000020
+    csrw 0x7d3,x1
+
+    //Internal timer 0 control (halt_en = 1, enable = 1)
+    li x1, 0x00000003
+    csrw 0x7d4, x1
+
+    //Machine intr enable reg (mie) - enable internal timer 0 intr
+    li x1, 0x20000000
+    csrw 0x304, x1
+
+    //mstatus - mie enable
+    li x1, 0x00000008
+    csrw 0x300, x1
+
+    //FW halt (mpmc) - halt, haltie
+    li x1,0x00000003
+    csrw 0x7c6,x1
+
+//------------------------------------------------------
+//Set STDOUT to F8 until all cases below finish running
+//------------------------------------------------------
+    li x3, STDOUT
+    li x5, 0xf8
+    sb x5, 0(x3) //write F8 to STDOUT to cause NMI event
+//------------------------------------------------------
+//Wake up using software int
+//------------------------------------------------------
+    //Machine intr enable reg (mie) - enable software int
+    li x1, 0x00000008
+    csrw 0x304, x1
+
+    //FW halt (mpmc) - halt, haltie
+    li x1,0x00000003
+    csrw 0x7c6,x1
+//------------------------------------------------------
+//Wake up using timer int
+//------------------------------------------------------
+    //Machine intr enable reg (mie) - enable timer int
+    li x1, 0x00000080
+    csrw 0x304, x1
+
+    //FW halt (mpmc) - halt, haltie
+    li x1,0x00000003
+    csrw 0x7c6,x1
+//------------------------------------------------------
+//Wake up using external int - TODO
+//------------------------------------------------------
+    //Machine intr enable reg (mie) - enable timer int
+    //li x1, 0x00000800
+    //csrw 0x304, x1
+
+
+    //FW halt (mpmc) - halt, haltie
+    //li x1,0x00000003
+    //csrw 0x7c6,x1
+//------------------------------------------------------
+//Wake up using generic input wires
+//------------------------------------------------------
+    //FW halt (mpmc) - halt, haltie
+    li x1,0x00000003
+    csrw 0x7c6,x1
+//------------------------------------------------------
+//Wake up using APB tx int and exit halt using NMI - TODO
+//------------------------------------------------------
+
+    //TODO: how to write a dword in asm
+    //Trigger APB tx
+    li x3, CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS
+    li x4, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK
+    //sb x5, 0(x3)
+    
+    loop1:
+        lw x5, 0(x4)
+        sw x5, 0(x3)
+        addi x4, x4, 4
+        bnez x5, loop1
+
+    //FW halt (mpmc) - halt, haltie
+    li x1,0x00000003
+    csrw 0x7c6,x1
+
+
+//------------------------------------------------------
+//End test
+//------------------------------------------------------
+    // Load string from hw_data
+    // and write to stdout address
+
+    li x3, STDOUT
+    la x4, hw_data_out
+
+loop:
+   lb x5, 0(x4)
+   sb x5, 0(x3)
+   addi x4, x4, 1
+   bnez x5, loop
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr
+
+.section .dccm
+hw_data_out:
+.ascii "----------------------------------\n"
+.ascii "Running clk gating test\n"
+.ascii "----------------------------------\n"
+.byte 0
+
+//.data
+//key_data:
+////this is the key 384-bit
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//.word 0x0b0b0b0b
+//block_data:
+//.word 0x48692054
+//.word 0x68657265
+//.word 0x80000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000000
+//.word 0x00000440
+//expected_data:
+//.word 0xb6a8d563
+//.word 0x6f5c6a72
+//.word 0x24f9977d
+//.word 0xcf7ee6c7
+//.word 0xfb6d0c48
+//.word 0xcbdee973
+//.word 0x7a959796
+//.word 0x489bddbc
+//.word 0x4c5df61d
+//.word 0x5b3297b4
+//.word 0xfb68dab9
+//.word 0xf1b582c2
+
+.align 4
+.global stdout
+stdout: .word STDOUT
+.global verbosity_g
+verbosity_g: .word 2
+
+.global intr_count
+intr_count: .word 0

From 40a1136587191ac921a5950d30918e92407de5b5 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Thu, 18 Jan 2024 18:14:43 -0800
Subject: [PATCH 13/17] Add environment variables for building Caliptra UVM
 testbench

---
 README.md | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index ec40a8b0c..bc83ec61c 100644
--- a/README.md
+++ b/README.md
@@ -208,7 +208,12 @@ The UVM Framework generation tool was used to create the baseline UVM testbench
 - UVM 1.1d installation
 - Mentor Graphics UVM-Framework installation
 
-Steps:<BR>
+**Environment Variables**:<BR>
+`UVM_HOME`: Filesystem path to the parent directory containing SystemVerilog source code for the UVM library of the desired version.
+`UVMF_HOME`: Filesystem path to the parent directory containing source code (uvmf_base_pkg) for the UVM Frameworks library, a tool available from Mentor Graphics for generating baseline UVM projects.
+`QUESTA_MVC_HOME`: Filesystem path to the parent directory containing source code for Mentor Graphics QVIP, the verification library from which AHB/APB UVM agents are pulled in the Caliptra UVM environment.
+
+**Steps:**<BR>
 1. Compile UVM 1.1d library
 1. Compile the AHB/APB QVIP source
 1. Compile the Mentor Graphics UVM-Frameworks base library
@@ -244,7 +249,7 @@ The UVM Framework generation tool was used to create the baseline UVM testbench
 - UVM 1.1d installation
 - Mentor Graphics UVM-Framework installation
 
-Steps:<BR>
+**Steps:**<BR>
 1. Compile UVM 1.1d library
 1. Compile the AHB/APB QVIP source
 1. Compile the Mentor Graphics UVM-Frameworks base library

From 97000a0936e7656a61bccee95060ddb1361cb220 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Fri, 19 Jan 2024 10:56:13 -0800
Subject: [PATCH 14/17] Point to sglint waiver files in Microsoft Internal
 Build structure

---
 src/ahb_lite_bus/config/compile.yml        | 2 +-
 src/datavault/config/compile.yml           | 2 +-
 src/doe/config/compile.yml                 | 2 +-
 src/ecc/config/compile.yml                 | 2 +-
 src/hmac/config/compile.yml                | 2 +-
 src/integration/config/compile.yml         | 2 +-
 src/keyvault/config/compile.yml            | 2 +-
 src/pcrvault/config/compile.yml            | 2 +-
 src/riscv_core/veer_el2/config/compile.yml | 2 +-
 src/sha256/config/compile.yml              | 2 +-
 src/sha512/config/compile.yml              | 2 +-
 src/soc_ifc/config/compile.yml             | 2 +-
 12 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/ahb_lite_bus/config/compile.yml b/src/ahb_lite_bus/config/compile.yml
index 2529a1177..e710a7c4d 100755
--- a/src/ahb_lite_bus/config/compile.yml
+++ b/src/ahb_lite_bus/config/compile.yml
@@ -15,5 +15,5 @@ targets:
   rtl_lint:
     directories: []
     waiver_files: 
-    - $COMPILE_ROOT/config/design_lint/ahb_lite_bus/sglint_waivers
+    - $MSFT_REPO_ROOT/src/ahb_lite_bus/config/design_lint/ahb_lite_bus/sglint_waivers
 
diff --git a/src/datavault/config/compile.yml b/src/datavault/config/compile.yml
index 2691979d4..d15f1319f 100644
--- a/src/datavault/config/compile.yml
+++ b/src/datavault/config/compile.yml
@@ -36,7 +36,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/datavault/sglint_waivers
+      - $MSFT_REPO_ROOT/src/datavault/config/design_lint/datavault/sglint_waivers
     black_box:
       - dv_reg
 global:
diff --git a/src/doe/config/compile.yml b/src/doe/config/compile.yml
index 39c70d8c4..c2556d00d 100755
--- a/src/doe/config/compile.yml
+++ b/src/doe/config/compile.yml
@@ -38,7 +38,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/doe_ctrl/sglint_waivers
+      - $MSFT_REPO_ROOT/src/doe/config/design_lint/doe_ctrl/sglint_waivers
     black_box:
       - doe_reg
 ---
diff --git a/src/ecc/config/compile.yml b/src/ecc/config/compile.yml
index 369d1ed2c..92b109284 100755
--- a/src/ecc/config/compile.yml
+++ b/src/ecc/config/compile.yml
@@ -40,7 +40,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/ecc_top/sglint_waivers
+      - $MSFT_REPO_ROOT/src/ecc/config/design_lint/ecc_top/sglint_waivers
     black_box:
       - ecc_reg
 ---
diff --git a/src/hmac/config/compile.yml b/src/hmac/config/compile.yml
index 181ae1ce8..480936e76 100755
--- a/src/hmac/config/compile.yml
+++ b/src/hmac/config/compile.yml
@@ -19,7 +19,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files: 
-      - $COMPILE_ROOT/config/design_lint/hmac_ctrl/sglint_waivers
+      - $MSFT_REPO_ROOT/src/hmac/config/design_lint/hmac_ctrl/sglint_waivers
     black_box:
       - hmac_reg
 ---
diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml
index ef8f9ca6f..5dd82de0f 100644
--- a/src/integration/config/compile.yml
+++ b/src/integration/config/compile.yml
@@ -45,7 +45,7 @@ targets:
     tops: [caliptra_top]
   rtl_lint:
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/sglint_waivers
+      - $MSFT_REPO_ROOT/src/integration/config/design_lint/sglint_waivers
     black_box:
       - el2_veer_wrapper
   cdc:
diff --git a/src/keyvault/config/compile.yml b/src/keyvault/config/compile.yml
index e0d516e0e..6bebe194c 100644
--- a/src/keyvault/config/compile.yml
+++ b/src/keyvault/config/compile.yml
@@ -52,7 +52,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/keyvault/sglint_waivers
+      - $MSFT_REPO_ROOT/src/keyvault/config/design_lint/keyvault/sglint_waivers
     black_box:
       - kv_reg
 global:
diff --git a/src/pcrvault/config/compile.yml b/src/pcrvault/config/compile.yml
index 8e17ba963..b52d4c33e 100644
--- a/src/pcrvault/config/compile.yml
+++ b/src/pcrvault/config/compile.yml
@@ -52,7 +52,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/pcrvault/sglint_waivers
+      - $MSFT_REPO_ROOT/src/pcrvault/config/design_lint/pcrvault/sglint_waivers
     black_box:
       - pv_reg
 global:
diff --git a/src/riscv_core/veer_el2/config/compile.yml b/src/riscv_core/veer_el2/config/compile.yml
index dad981819..883ece5df 100755
--- a/src/riscv_core/veer_el2/config/compile.yml
+++ b/src/riscv_core/veer_el2/config/compile.yml
@@ -71,7 +71,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/el2_veer_wrapper/sglint_waivers
+      - $MSFT_REPO_ROOT/src/riscv_core/veer_el2/config/design_lint/el2_veer_wrapper/sglint_waivers
 global:
   tool:
     vcs:
diff --git a/src/sha256/config/compile.yml b/src/sha256/config/compile.yml
index 03ecae0e0..15af97656 100755
--- a/src/sha256/config/compile.yml
+++ b/src/sha256/config/compile.yml
@@ -20,7 +20,7 @@ targets:
     directories: []
     waiver_files: 
       #- $COMPILE_ROOT/config/rtl_lint/sha256.waiver
-      - $COMPILE_ROOT/config/design_lint/sha256_ctrl/sglint_waivers
+      - $MSFT_REPO_ROOT/src/sha256/config/design_lint/sha256_ctrl/sglint_waivers
     black_box:
       - sha256_reg
 ---
diff --git a/src/sha512/config/compile.yml b/src/sha512/config/compile.yml
index 690ae1c4a..f7c6f56f6 100755
--- a/src/sha512/config/compile.yml
+++ b/src/sha512/config/compile.yml
@@ -23,7 +23,7 @@ targets:
     directories: []
     waiver_files: 
       #- $COMPILE_ROOT/config/rtl_lint/sha512.waiver
-      - $COMPILE_ROOT/config/design_lint/sha512_ctrl/sglint_waivers
+      - $MSFT_REPO_ROOT/src/sha512/config/design_lint/sha512_ctrl/sglint_waivers
     black_box:
       - sha512_reg
 ---
diff --git a/src/soc_ifc/config/compile.yml b/src/soc_ifc/config/compile.yml
index 203ddb636..85cdd473b 100644
--- a/src/soc_ifc/config/compile.yml
+++ b/src/soc_ifc/config/compile.yml
@@ -74,7 +74,7 @@ targets:
       - soc_ifc_reg
       - soc_ifc_reg_pkg
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/soc_ifc/sglint_waivers
+      - $MSFT_REPO_ROOT/src/soc_ifc/config/design_lint/soc_ifc/sglint_waivers
     black_box:
       - sha512_acc_csr
       - mbox_csr

From 6cfcb483d12b13ecb85d5cee24211bf640f4dcf1 Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Fri, 19 Jan 2024 11:48:23 -0800
Subject: [PATCH 15/17] Fix ref to run_test_makefile (MSFT internal tool)

---
 src/integration/config/compile.yml                   | 2 +-
 src/integration/uvmf_caliptra_top/config/compile.yml | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml
index 5dd82de0f..841335776 100644
--- a/src/integration/config/compile.yml
+++ b/src/integration/config/compile.yml
@@ -109,7 +109,7 @@ targets:
       - $COMPILE_ROOT/tb/caliptra_top_tb.sv
     tops: [caliptra_top_tb]
   sim:
-    pre_exec: '$MSFT_TOOLS/scripts/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../ecc/tb/ecdsa_secp384r1.exe . 
+    pre_exec: '$MSFT_SCRIPTS_DIR/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../ecc/tb/ecdsa_secp384r1.exe . 
                 && echo "[PRE-EXEC] Copying DOE vector generator to ${pwd}" && cp $COMPILE_ROOT/../doe/tb/doe_test_gen.py .'
 global:
   tool:
diff --git a/src/integration/uvmf_caliptra_top/config/compile.yml b/src/integration/uvmf_caliptra_top/config/compile.yml
index a2f5c1c7e..1029c8669 100644
--- a/src/integration/uvmf_caliptra_top/config/compile.yml
+++ b/src/integration/uvmf_caliptra_top/config/compile.yml
@@ -51,7 +51,7 @@ targets:
     pre_exec: |
         echo "[PRE-EXEC] Copying SHA512 Vectors to $(pwd)"
         cp ${COMPILE_ROOT}/../tb/vectors/SHA*.rsp .
-        $TOOLS/scripts/run_test_makefile
+        $MSFT_SCRIPTS_DIR/run_test_makefile
 global:
   tool:
     vcs:
@@ -97,7 +97,7 @@ targets:
     pre_exec: |
         echo "[PRE-EXEC] Copying SHA512 Vectors to $(pwd)"
         cp ${COMPILE_ROOT}/../tb/vectors/SHA*.rsp .
-        $TOOLS/scripts/run_test_makefile
+        $MSFT_SCRIPTS_DIR/run_test_makefile
 global:
   tool:
     vcs:

From 51240a28f38e32aecb51a039e136fac3a43cd9be Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Fri, 19 Jan 2024 12:06:36 -0800
Subject: [PATCH 16/17] Remove duplicate entry from file list

---
 src/caliptra_prim/config/caliptra_prim_pkg.vf | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/caliptra_prim/config/caliptra_prim_pkg.vf b/src/caliptra_prim/config/caliptra_prim_pkg.vf
index dfed9ddd5..f97774292 100644
--- a/src/caliptra_prim/config/caliptra_prim_pkg.vf
+++ b/src/caliptra_prim/config/caliptra_prim_pkg.vf
@@ -6,4 +6,3 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
-${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv

From a8b0b3de885a93042a104e1d142b87b086a4adfc Mon Sep 17 00:00:00 2001
From: Caleb Whitehead <cwhitehead@microsoft.com>
Date: Sun, 21 Jan 2024 20:19:12 -0800
Subject: [PATCH 17/17] Add Apache license headers to GitHub workflow scripts

---
 .github/scripts/build_tests_matrix.py | 14 ++++++++++++++
 .github/scripts/gdb_test.sh           | 13 +++++++++++++
 .github/scripts/openocd_test.sh       | 13 +++++++++++++
 .github/scripts/utils.sh              | 14 ++++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/.github/scripts/build_tests_matrix.py b/.github/scripts/build_tests_matrix.py
index 69d18560e..c33ece199 100644
--- a/.github/scripts/build_tests_matrix.py
+++ b/.github/scripts/build_tests_matrix.py
@@ -1,4 +1,18 @@
 #!/usr/bin/env python3
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
 import os
 import yaml
 
diff --git a/.github/scripts/gdb_test.sh b/.github/scripts/gdb_test.sh
index 20f783040..1ffaf73a9 100755
--- a/.github/scripts/gdb_test.sh
+++ b/.github/scripts/gdb_test.sh
@@ -1,4 +1,17 @@
 #!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
 #
 # This script runs Verilator RTL simulation and OpenOCD in background, invokes
 # the supplied test command and shuts everything down.
diff --git a/.github/scripts/openocd_test.sh b/.github/scripts/openocd_test.sh
index 75a96ba6a..a30cccee4 100755
--- a/.github/scripts/openocd_test.sh
+++ b/.github/scripts/openocd_test.sh
@@ -1,4 +1,17 @@
 #!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
 #
 # This script runs Verilator RTL simulation in background and invokes OpenOCD
 # to perform JTAG access test
diff --git a/.github/scripts/utils.sh b/.github/scripts/utils.sh
index e5496afd9..24bd83242 100644
--- a/.github/scripts/utils.sh
+++ b/.github/scripts/utils.sh
@@ -1,4 +1,18 @@
 #!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
 
 # Colors
 COLOR_OFF='\033[0m'