From 94a09d2e5a318b2d1499825523c6a1d554c44fbb Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Wed, 18 Dec 2024 16:28:01 -0800 Subject: [PATCH 1/9] Reduce fuse_key_manifest_pk_hash_mask back to 4-bit reg --- src/integration/rtl/caliptra_reg.h | 20 +- src/integration/rtl/caliptra_reg_defines.svh | 20 +- src/soc_ifc/rtl/caliptra_top_reg.h | 20 +- src/soc_ifc/rtl/caliptra_top_reg_defines.svh | 20 +- src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl | 4 +- src/soc_ifc/rtl/soc_ifc_reg.sv | 377 +++++++++---------- src/soc_ifc/rtl/soc_ifc_reg_pkg.sv | 24 +- src/soc_ifc/rtl/soc_ifc_reg_uvm.sv | 18 +- 8 files changed, 224 insertions(+), 279 deletions(-) diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index 9bb202352..e53da24fe 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -6075,22 +6075,10 @@ #define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (0x288) #define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x3003028c) #define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x28c) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (0x30030290) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (0x290) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (0x30030294) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (0x294) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (0x30030298) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (0x298) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (0x3003029c) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (0x29c) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (0x300302a0) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (0x2a0) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (0x300302a4) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (0x2a4) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (0x300302a8) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (0x2a8) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (0x300302ac) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (0x2ac) +#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x30030290) +#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x290) +#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0) +#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (0xf) #define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x300302b4) #define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2b4) #define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (0x300302b8) diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index ffc760a4e..f40346a71 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -6075,22 +6075,10 @@ `define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (32'h288) `define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h3003028c) `define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h28c) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (32'h30030290) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (32'h290) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (32'h30030294) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (32'h294) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (32'h30030298) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (32'h298) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (32'h3003029c) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (32'h29c) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (32'h300302a0) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (32'h2a0) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (32'h300302a4) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (32'h2a4) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (32'h300302a8) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (32'h2a8) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (32'h300302ac) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (32'h2ac) +`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h30030290) +`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h290) +`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0) +`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (32'hf) `define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h300302b4) `define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) `define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h300302b8) diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index 79ff4ee3a..fbcffa8c3 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -417,22 +417,10 @@ #define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (0x288) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x3028c) #define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x28c) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (0x30290) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (0x290) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (0x30294) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (0x294) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (0x30298) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (0x298) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (0x3029c) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (0x29c) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (0x302a0) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (0x2a0) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (0x302a4) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (0x2a4) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (0x302a8) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (0x2a8) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (0x302ac) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (0x2ac) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x30290) +#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x290) +#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0) +#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (0xf) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x302b4) #define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2b4) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (0x302b8) diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index 78e952ae7..f734a0907 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -417,22 +417,10 @@ `define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (32'h288) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h3028c) `define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h28c) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (32'h30290) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (32'h290) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (32'h30294) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (32'h294) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (32'h30298) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (32'h298) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (32'h3029c) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (32'h29c) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (32'h302a0) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (32'h2a0) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (32'h302a4) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (32'h2a4) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (32'h302a8) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (32'h2a8) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (32'h302ac) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (32'h2ac) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h30290) +`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h290) +`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (32'hf) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h302b4) `define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h302b8) diff --git a/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl b/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl index c7ae8f405..7e42254df 100644 --- a/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl @@ -44,8 +44,8 @@ reg { desc = "Key Manifest Mask Fuse (ECC Revocation). [br]Caliptra Access: RO [br]SOC Access: RWL-S"; - Fuse mask[32]=0; -} fuse_key_manifest_pk_hash_mask[8]; + Fuse mask[4]=0; +} fuse_key_manifest_pk_hash_mask; reg { desc = "FMC Security Version Number. diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index 1df823f23..9d3183b18 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -115,7 +115,7 @@ module soc_ifc_reg ( logic [16-1:0]fuse_uds_seed; logic [8-1:0]fuse_field_entropy; logic [12-1:0]fuse_key_manifest_pk_hash; - logic [8-1:0]fuse_key_manifest_pk_hash_mask; + logic fuse_key_manifest_pk_hash_mask; logic fuse_fmc_key_manifest_svn; logic [4-1:0]fuse_runtime_svn; logic fuse_anti_rollback_disable; @@ -282,9 +282,7 @@ module soc_ifc_reg ( for(int i0=0; i0<12; i0++) begin decoded_reg_strb.fuse_key_manifest_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h260 + i0*12'h4); end - for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.fuse_key_manifest_pk_hash_mask[i0] = cpuif_req_masked & (cpuif_addr == 12'h290 + i0*12'h4); - end + decoded_reg_strb.fuse_key_manifest_pk_hash_mask = cpuif_req_masked & (cpuif_addr == 12'h290); decoded_reg_strb.fuse_fmc_key_manifest_svn = cpuif_req_masked & (cpuif_addr == 12'h2b4); for(int i0=0; i0<4; i0++) begin decoded_reg_strb.fuse_runtime_svn[i0] = cpuif_req_masked & (cpuif_addr == 12'h2b8 + i0*12'h4); @@ -724,10 +722,10 @@ module soc_ifc_reg ( } [12-1:0]fuse_key_manifest_pk_hash; struct packed{ struct packed{ - logic [31:0] next; + logic [3:0] next; logic load_next; } mask; - } [8-1:0]fuse_key_manifest_pk_hash_mask; + } fuse_key_manifest_pk_hash_mask; struct packed{ struct packed{ logic [31:0] next; @@ -1734,9 +1732,9 @@ module soc_ifc_reg ( } [12-1:0]fuse_key_manifest_pk_hash; struct packed{ struct packed{ - logic [31:0] value; + logic [3:0] value; } mask; - } [8-1:0]fuse_key_manifest_pk_hash_mask; + } fuse_key_manifest_pk_hash_mask; struct packed{ struct packed{ logic [31:0] value; @@ -3622,29 +3620,27 @@ module soc_ifc_reg ( end assign hwif_out.fuse_key_manifest_pk_hash[i0].hash.value = field_storage.fuse_key_manifest_pk_hash[i0].hash.value; end - for(genvar i0=0; i0<8; i0++) begin - // Field: soc_ifc_reg.fuse_key_manifest_pk_hash_mask[].mask - always_comb begin - automatic logic [31:0] next_c; - automatic logic load_next_c; - next_c = field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value; - load_next_c = '0; - if(decoded_reg_strb.fuse_key_manifest_pk_hash_mask[i0] && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash_mask[i0].mask.swwel)) begin // SW write - next_c = (field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); - load_next_c = '1; - end - field_combo.fuse_key_manifest_pk_hash_mask[i0].mask.next = next_c; - field_combo.fuse_key_manifest_pk_hash_mask[i0].mask.load_next = load_next_c; + // Field: soc_ifc_reg.fuse_key_manifest_pk_hash_mask.mask + always_comb begin + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_key_manifest_pk_hash_mask.mask.value; + load_next_c = '0; + if(decoded_reg_strb.fuse_key_manifest_pk_hash_mask && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel)) begin // SW write + next_c = (field_storage.fuse_key_manifest_pk_hash_mask.mask.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]); + load_next_c = '1; end - always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin - if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value <= 32'h0; - end else if(field_combo.fuse_key_manifest_pk_hash_mask[i0].mask.load_next) begin - field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value <= field_combo.fuse_key_manifest_pk_hash_mask[i0].mask.next; - end + field_combo.fuse_key_manifest_pk_hash_mask.mask.next = next_c; + field_combo.fuse_key_manifest_pk_hash_mask.mask.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin + if(~hwif_in.cptra_pwrgood) begin + field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= 4'h0; + end else if(field_combo.fuse_key_manifest_pk_hash_mask.mask.load_next) begin + field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= field_combo.fuse_key_manifest_pk_hash_mask.mask.next; end - assign hwif_out.fuse_key_manifest_pk_hash_mask[i0].mask.value = field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value; end + assign hwif_out.fuse_key_manifest_pk_hash_mask.mask.value = field_storage.fuse_key_manifest_pk_hash_mask.mask.value; // Field: soc_ifc_reg.fuse_fmc_key_manifest_svn.svn always_comb begin automatic logic [31:0] next_c; @@ -6896,7 +6892,7 @@ module soc_ifc_reg ( logic [31:0] readback_data; // Assign readback values to a flattened array - logic [225-1:0][31:0] readback_array; + logic [218-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value : '0; assign readback_array[0][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value : '0; assign readback_array[0][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value : '0; @@ -7012,185 +7008,184 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin assign readback_array[i0*1 + 90][31:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash[i0].hash.value : '0; end - for(genvar i0=0; i0<8; i0++) begin - assign readback_array[i0*1 + 102][31:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash_mask[i0] && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value : '0; - end - assign readback_array[110][31:0] = (decoded_reg_strb.fuse_fmc_key_manifest_svn && !decoded_req_is_wr) ? field_storage.fuse_fmc_key_manifest_svn.svn.value : '0; + assign readback_array[102][3:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash_mask && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash_mask.mask.value : '0; + assign readback_array[102][31:4] = '0; + assign readback_array[103][31:0] = (decoded_reg_strb.fuse_fmc_key_manifest_svn && !decoded_req_is_wr) ? field_storage.fuse_fmc_key_manifest_svn.svn.value : '0; for(genvar i0=0; i0<4; i0++) begin - assign readback_array[i0*1 + 111][31:0] = (decoded_reg_strb.fuse_runtime_svn[i0] && !decoded_req_is_wr) ? field_storage.fuse_runtime_svn[i0].svn.value : '0; + assign readback_array[i0*1 + 104][31:0] = (decoded_reg_strb.fuse_runtime_svn[i0] && !decoded_req_is_wr) ? field_storage.fuse_runtime_svn[i0].svn.value : '0; end - assign readback_array[115][0:0] = (decoded_reg_strb.fuse_anti_rollback_disable && !decoded_req_is_wr) ? field_storage.fuse_anti_rollback_disable.dis.value : '0; - assign readback_array[115][31:1] = '0; + assign readback_array[108][0:0] = (decoded_reg_strb.fuse_anti_rollback_disable && !decoded_req_is_wr) ? field_storage.fuse_anti_rollback_disable.dis.value : '0; + assign readback_array[108][31:1] = '0; for(genvar i0=0; i0<24; i0++) begin - assign readback_array[i0*1 + 116][31:0] = (decoded_reg_strb.fuse_idevid_cert_attr[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_cert_attr[i0].cert.value : '0; + assign readback_array[i0*1 + 109][31:0] = (decoded_reg_strb.fuse_idevid_cert_attr[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_cert_attr[i0].cert.value : '0; end for(genvar i0=0; i0<4; i0++) begin - assign readback_array[i0*1 + 140][31:0] = (decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value : '0; + assign readback_array[i0*1 + 133][31:0] = (decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value : '0; end - assign readback_array[144][31:0] = (decoded_reg_strb.fuse_lms_revocation && !decoded_req_is_wr) ? field_storage.fuse_lms_revocation.lms_revocation.value : '0; - assign readback_array[145][3:0] = (decoded_reg_strb.fuse_mldsa_revocation && !decoded_req_is_wr) ? field_storage.fuse_mldsa_revocation.mldsa_revocation.value : '0; - assign readback_array[145][31:4] = '0; - assign readback_array[146][15:0] = (decoded_reg_strb.fuse_soc_stepping_id && !decoded_req_is_wr) ? field_storage.fuse_soc_stepping_id.soc_stepping_id.value : '0; - assign readback_array[146][31:16] = '0; + assign readback_array[137][31:0] = (decoded_reg_strb.fuse_lms_revocation && !decoded_req_is_wr) ? field_storage.fuse_lms_revocation.lms_revocation.value : '0; + assign readback_array[138][3:0] = (decoded_reg_strb.fuse_mldsa_revocation && !decoded_req_is_wr) ? field_storage.fuse_mldsa_revocation.mldsa_revocation.value : '0; + assign readback_array[138][31:4] = '0; + assign readback_array[139][15:0] = (decoded_reg_strb.fuse_soc_stepping_id && !decoded_req_is_wr) ? field_storage.fuse_soc_stepping_id.soc_stepping_id.value : '0; + assign readback_array[139][31:16] = '0; for(genvar i0=0; i0<4; i0++) begin - assign readback_array[i0*1 + 147][31:0] = (decoded_reg_strb.fuse_manuf_dbg_unlock_token[i0] && !decoded_req_is_wr) ? field_storage.fuse_manuf_dbg_unlock_token[i0].token.value : '0; - end - assign readback_array[151][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[152][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[153][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[154][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[155][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[156][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[157][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[158][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[159][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[160][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[161][31:0] = (decoded_reg_strb.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET && !decoded_req_is_wr) ? field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value : '0; - assign readback_array[162][31:0] = (decoded_reg_strb.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES && !decoded_req_is_wr) ? field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value : '0; - assign readback_array[163][0:0] = (decoded_reg_strb.SS_DEBUG_INTENT && !decoded_req_is_wr) ? field_storage.SS_DEBUG_INTENT.debug_intent.value : '0; - assign readback_array[163][31:1] = '0; + assign readback_array[i0*1 + 140][31:0] = (decoded_reg_strb.fuse_manuf_dbg_unlock_token[i0] && !decoded_req_is_wr) ? field_storage.fuse_manuf_dbg_unlock_token[i0].token.value : '0; + end + assign readback_array[144][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[145][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[146][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[147][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[148][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[149][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[150][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[151][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[152][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[153][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[154][31:0] = (decoded_reg_strb.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET && !decoded_req_is_wr) ? field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value : '0; + assign readback_array[155][31:0] = (decoded_reg_strb.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES && !decoded_req_is_wr) ? field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value : '0; + assign readback_array[156][0:0] = (decoded_reg_strb.SS_DEBUG_INTENT && !decoded_req_is_wr) ? field_storage.SS_DEBUG_INTENT.debug_intent.value : '0; + assign readback_array[156][31:1] = '0; for(genvar i0=0; i0<4; i0++) begin - assign readback_array[i0*1 + 164][31:0] = (decoded_reg_strb.SS_STRAP_GENERIC[i0] && !decoded_req_is_wr) ? field_storage.SS_STRAP_GENERIC[i0].data.value : '0; - end - assign readback_array[168][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value : '0; - assign readback_array[168][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value : '0; - assign readback_array[168][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value : '0; - assign readback_array[168][31:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.RSVD.next : '0; - assign readback_array[169][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value : '0; - assign readback_array[169][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value : '0; - assign readback_array[169][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value : '0; - assign readback_array[169][3:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value : '0; - assign readback_array[169][4:4] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value : '0; - assign readback_array[169][5:5] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value : '0; - assign readback_array[169][6:6] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value : '0; - assign readback_array[169][7:7] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value : '0; - assign readback_array[169][8:8] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value : '0; - assign readback_array[169][31:9] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.RSVD.next : '0; + assign readback_array[i0*1 + 157][31:0] = (decoded_reg_strb.SS_STRAP_GENERIC[i0] && !decoded_req_is_wr) ? field_storage.SS_STRAP_GENERIC[i0].data.value : '0; + end + assign readback_array[161][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value : '0; + assign readback_array[161][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value : '0; + assign readback_array[161][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value : '0; + assign readback_array[161][31:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.RSVD.next : '0; + assign readback_array[162][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value : '0; + assign readback_array[162][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value : '0; + assign readback_array[162][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value : '0; + assign readback_array[162][3:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value : '0; + assign readback_array[162][4:4] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value : '0; + assign readback_array[162][5:5] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value : '0; + assign readback_array[162][6:6] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value : '0; + assign readback_array[162][7:7] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value : '0; + assign readback_array[162][8:8] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value : '0; + assign readback_array[162][31:9] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.RSVD.next : '0; for(genvar i0=0; i0<2; i0++) begin - assign readback_array[i0*1 + 170][31:0] = (decoded_reg_strb.SS_SOC_DBG_UNLOCK_LEVEL[i0] && !decoded_req_is_wr) ? field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value : '0; + assign readback_array[i0*1 + 163][31:0] = (decoded_reg_strb.SS_SOC_DBG_UNLOCK_LEVEL[i0] && !decoded_req_is_wr) ? field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value : '0; end for(genvar i0=0; i0<4; i0++) begin - assign readback_array[i0*1 + 172][31:0] = (decoded_reg_strb.SS_GENERIC_FW_EXEC_CTRL[i0] && !decoded_req_is_wr) ? field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value : '0; - end - assign readback_array[176][0:0] = (decoded_reg_strb.internal_iccm_lock && !decoded_req_is_wr) ? field_storage.internal_iccm_lock.lock.value : '0; - assign readback_array[176][31:1] = '0; - assign readback_array[177][0:0] = (decoded_reg_strb.internal_fw_update_reset && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset.core_rst.value : '0; - assign readback_array[177][31:1] = '0; - assign readback_array[178][7:0] = (decoded_reg_strb.internal_fw_update_reset_wait_cycles && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value : '0; - assign readback_array[178][31:8] = '0; - assign readback_array[179][31:0] = (decoded_reg_strb.internal_nmi_vector && !decoded_req_is_wr) ? field_storage.internal_nmi_vector.vec.value : '0; - assign readback_array[180][0:0] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value : '0; - assign readback_array[180][1:1] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value : '0; - assign readback_array[180][2:2] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value : '0; - assign readback_array[180][3:3] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? 1'h0 : '0; - assign readback_array[180][31:4] = '0; - assign readback_array[181][0:0] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value : '0; - assign readback_array[181][1:1] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value : '0; - assign readback_array[181][2:2] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value : '0; - assign readback_array[181][31:3] = '0; - assign readback_array[182][31:0] = (decoded_reg_strb.internal_fw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_fatal_mask.mask.value : '0; - assign readback_array[183][31:0] = (decoded_reg_strb.internal_fw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_non_fatal_mask.mask.value : '0; - assign readback_array[184][31:0] = (decoded_reg_strb.internal_rv_mtime_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_l.count_l.value : '0; - assign readback_array[185][31:0] = (decoded_reg_strb.internal_rv_mtime_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_h.count_h.value : '0; - assign readback_array[186][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_l.compare_l.value : '0; - assign readback_array[187][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_h.compare_h.value : '0; - assign readback_array[188][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0; - assign readback_array[188][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0; - assign readback_array[188][31:2] = '0; - assign readback_array[189][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0; - assign readback_array[189][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value : '0; - assign readback_array[189][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value : '0; - assign readback_array[189][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value : '0; - assign readback_array[189][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value : '0; - assign readback_array[189][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value : '0; - assign readback_array[189][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value : '0; - assign readback_array[189][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value : '0; - assign readback_array[189][31:8] = '0; - assign readback_array[190][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value : '0; - assign readback_array[190][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value : '0; - assign readback_array[190][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value : '0; - assign readback_array[190][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value : '0; - assign readback_array[190][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value : '0; - assign readback_array[190][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value : '0; - assign readback_array[190][31:6] = '0; - assign readback_array[191][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0; - assign readback_array[191][31:1] = '0; - assign readback_array[192][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0; - assign readback_array[192][31:1] = '0; - assign readback_array[193][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0; - assign readback_array[193][1:1] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value : '0; - assign readback_array[193][2:2] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value : '0; - assign readback_array[193][3:3] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value : '0; - assign readback_array[193][4:4] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value : '0; - assign readback_array[193][5:5] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value : '0; - assign readback_array[193][6:6] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value : '0; - assign readback_array[193][7:7] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value : '0; - assign readback_array[193][31:8] = '0; - assign readback_array[194][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value : '0; - assign readback_array[194][1:1] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value : '0; - assign readback_array[194][2:2] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value : '0; - assign readback_array[194][3:3] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value : '0; - assign readback_array[194][4:4] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value : '0; - assign readback_array[194][5:5] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value : '0; - assign readback_array[194][31:6] = '0; - assign readback_array[195][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0; - assign readback_array[195][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value : '0; - assign readback_array[195][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value : '0; - assign readback_array[195][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value : '0; - assign readback_array[195][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value : '0; - assign readback_array[195][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value : '0; - assign readback_array[195][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value : '0; - assign readback_array[195][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value : '0; - assign readback_array[195][31:8] = '0; - assign readback_array[196][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value : '0; - assign readback_array[196][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value : '0; - assign readback_array[196][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value : '0; - assign readback_array[196][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value : '0; - assign readback_array[196][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value : '0; - assign readback_array[196][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value : '0; - assign readback_array[196][31:6] = '0; - assign readback_array[197][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0; - assign readback_array[198][31:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value : '0; - assign readback_array[199][31:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value : '0; - assign readback_array[200][31:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value : '0; - assign readback_array[201][31:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value : '0; - assign readback_array[202][31:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value : '0; - assign readback_array[203][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value : '0; - assign readback_array[204][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value : '0; - assign readback_array[205][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value : '0; - assign readback_array[206][31:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value : '0; - assign readback_array[207][31:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value : '0; - assign readback_array[208][31:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value : '0; - assign readback_array[209][31:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value : '0; - assign readback_array[210][31:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value : '0; - assign readback_array[211][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0; + assign readback_array[i0*1 + 165][31:0] = (decoded_reg_strb.SS_GENERIC_FW_EXEC_CTRL[i0] && !decoded_req_is_wr) ? field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value : '0; + end + assign readback_array[169][0:0] = (decoded_reg_strb.internal_iccm_lock && !decoded_req_is_wr) ? field_storage.internal_iccm_lock.lock.value : '0; + assign readback_array[169][31:1] = '0; + assign readback_array[170][0:0] = (decoded_reg_strb.internal_fw_update_reset && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset.core_rst.value : '0; + assign readback_array[170][31:1] = '0; + assign readback_array[171][7:0] = (decoded_reg_strb.internal_fw_update_reset_wait_cycles && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value : '0; + assign readback_array[171][31:8] = '0; + assign readback_array[172][31:0] = (decoded_reg_strb.internal_nmi_vector && !decoded_req_is_wr) ? field_storage.internal_nmi_vector.vec.value : '0; + assign readback_array[173][0:0] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value : '0; + assign readback_array[173][1:1] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value : '0; + assign readback_array[173][2:2] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value : '0; + assign readback_array[173][3:3] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? 1'h0 : '0; + assign readback_array[173][31:4] = '0; + assign readback_array[174][0:0] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value : '0; + assign readback_array[174][1:1] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value : '0; + assign readback_array[174][2:2] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value : '0; + assign readback_array[174][31:3] = '0; + assign readback_array[175][31:0] = (decoded_reg_strb.internal_fw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_fatal_mask.mask.value : '0; + assign readback_array[176][31:0] = (decoded_reg_strb.internal_fw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_non_fatal_mask.mask.value : '0; + assign readback_array[177][31:0] = (decoded_reg_strb.internal_rv_mtime_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_l.count_l.value : '0; + assign readback_array[178][31:0] = (decoded_reg_strb.internal_rv_mtime_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_h.count_h.value : '0; + assign readback_array[179][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_l.compare_l.value : '0; + assign readback_array[180][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_h.compare_h.value : '0; + assign readback_array[181][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0; + assign readback_array[181][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0; + assign readback_array[181][31:2] = '0; + assign readback_array[182][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0; + assign readback_array[182][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value : '0; + assign readback_array[182][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value : '0; + assign readback_array[182][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value : '0; + assign readback_array[182][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value : '0; + assign readback_array[182][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value : '0; + assign readback_array[182][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value : '0; + assign readback_array[182][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value : '0; + assign readback_array[182][31:8] = '0; + assign readback_array[183][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value : '0; + assign readback_array[183][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value : '0; + assign readback_array[183][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value : '0; + assign readback_array[183][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value : '0; + assign readback_array[183][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value : '0; + assign readback_array[183][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value : '0; + assign readback_array[183][31:6] = '0; + assign readback_array[184][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0; + assign readback_array[184][31:1] = '0; + assign readback_array[185][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0; + assign readback_array[185][31:1] = '0; + assign readback_array[186][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0; + assign readback_array[186][1:1] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value : '0; + assign readback_array[186][2:2] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value : '0; + assign readback_array[186][3:3] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value : '0; + assign readback_array[186][4:4] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value : '0; + assign readback_array[186][5:5] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value : '0; + assign readback_array[186][6:6] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value : '0; + assign readback_array[186][7:7] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value : '0; + assign readback_array[186][31:8] = '0; + assign readback_array[187][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value : '0; + assign readback_array[187][1:1] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value : '0; + assign readback_array[187][2:2] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value : '0; + assign readback_array[187][3:3] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value : '0; + assign readback_array[187][4:4] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value : '0; + assign readback_array[187][5:5] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value : '0; + assign readback_array[187][31:6] = '0; + assign readback_array[188][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0; + assign readback_array[188][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value : '0; + assign readback_array[188][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value : '0; + assign readback_array[188][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value : '0; + assign readback_array[188][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value : '0; + assign readback_array[188][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value : '0; + assign readback_array[188][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value : '0; + assign readback_array[188][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value : '0; + assign readback_array[188][31:8] = '0; + assign readback_array[189][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value : '0; + assign readback_array[189][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value : '0; + assign readback_array[189][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value : '0; + assign readback_array[189][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value : '0; + assign readback_array[189][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value : '0; + assign readback_array[189][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value : '0; + assign readback_array[189][31:6] = '0; + assign readback_array[190][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0; + assign readback_array[191][31:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value : '0; + assign readback_array[192][31:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value : '0; + assign readback_array[193][31:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value : '0; + assign readback_array[194][31:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value : '0; + assign readback_array[195][31:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value : '0; + assign readback_array[196][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value : '0; + assign readback_array[197][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value : '0; + assign readback_array[198][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value : '0; + assign readback_array[199][31:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value : '0; + assign readback_array[200][31:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value : '0; + assign readback_array[201][31:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value : '0; + assign readback_array[202][31:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value : '0; + assign readback_array[203][31:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value : '0; + assign readback_array[204][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0; + assign readback_array[204][31:1] = '0; + assign readback_array[205][0:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value : '0; + assign readback_array[205][31:1] = '0; + assign readback_array[206][0:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value : '0; + assign readback_array[206][31:1] = '0; + assign readback_array[207][0:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value : '0; + assign readback_array[207][31:1] = '0; + assign readback_array[208][0:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value : '0; + assign readback_array[208][31:1] = '0; + assign readback_array[209][0:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value : '0; + assign readback_array[209][31:1] = '0; + assign readback_array[210][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value : '0; + assign readback_array[210][31:1] = '0; + assign readback_array[211][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value : '0; assign readback_array[211][31:1] = '0; - assign readback_array[212][0:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value : '0; + assign readback_array[212][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value : '0; assign readback_array[212][31:1] = '0; - assign readback_array[213][0:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value : '0; + assign readback_array[213][0:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value : '0; assign readback_array[213][31:1] = '0; - assign readback_array[214][0:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value : '0; + assign readback_array[214][0:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value : '0; assign readback_array[214][31:1] = '0; - assign readback_array[215][0:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value : '0; + assign readback_array[215][0:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value : '0; assign readback_array[215][31:1] = '0; - assign readback_array[216][0:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value : '0; + assign readback_array[216][0:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value : '0; assign readback_array[216][31:1] = '0; - assign readback_array[217][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value : '0; + assign readback_array[217][0:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value : '0; assign readback_array[217][31:1] = '0; - assign readback_array[218][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value : '0; - assign readback_array[218][31:1] = '0; - assign readback_array[219][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value : '0; - assign readback_array[219][31:1] = '0; - assign readback_array[220][0:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value : '0; - assign readback_array[220][31:1] = '0; - assign readback_array[221][0:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value : '0; - assign readback_array[221][31:1] = '0; - assign readback_array[222][0:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value : '0; - assign readback_array[222][31:1] = '0; - assign readback_array[223][0:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value : '0; - assign readback_array[223][31:1] = '0; - assign readback_array[224][0:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value : '0; - assign readback_array[224][31:1] = '0; // Reduce the array always_comb begin @@ -7198,7 +7193,7 @@ module soc_ifc_reg ( readback_done = decoded_req & ~decoded_req_is_wr; readback_err = '0; readback_data_var = '0; - for(int i=0; i<225; i++) readback_data_var |= readback_array[i]; + for(int i=0; i<218; i++) readback_data_var |= readback_array[i]; readback_data = readback_data_var; end diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index e3c456864..83256e4cd 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -298,7 +298,11 @@ package soc_ifc_reg_pkg; } soc_ifc_reg__fuse_key_manifest_pk_hash__in_t; typedef struct packed{ - soc_ifc_reg__Fuse_w32__in_t mask; + logic swwel; + } soc_ifc_reg__Fuse_w4__in_t; + + typedef struct packed{ + soc_ifc_reg__Fuse_w4__in_t mask; } soc_ifc_reg__fuse_key_manifest_pk_hash_mask__in_t; typedef struct packed{ @@ -329,10 +333,6 @@ package soc_ifc_reg_pkg; soc_ifc_reg__Fuse_w32__in_t lms_revocation; } soc_ifc_reg__fuse_lms_revocation__in_t; - typedef struct packed{ - logic swwel; - } soc_ifc_reg__Fuse_w4__in_t; - typedef struct packed{ soc_ifc_reg__Fuse_w4__in_t mldsa_revocation; } soc_ifc_reg__fuse_mldsa_revocation__in_t; @@ -676,7 +676,7 @@ package soc_ifc_reg_pkg; soc_ifc_reg__fuse_uds_seed__in_t [16-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__in_t [8-1:0]fuse_field_entropy; soc_ifc_reg__fuse_key_manifest_pk_hash__in_t [12-1:0]fuse_key_manifest_pk_hash; - soc_ifc_reg__fuse_key_manifest_pk_hash_mask__in_t [8-1:0]fuse_key_manifest_pk_hash_mask; + soc_ifc_reg__fuse_key_manifest_pk_hash_mask__in_t fuse_key_manifest_pk_hash_mask; soc_ifc_reg__fuse_fmc_key_manifest_svn__in_t fuse_fmc_key_manifest_svn; soc_ifc_reg__fuse_runtime_svn__in_t [4-1:0]fuse_runtime_svn; soc_ifc_reg__fuse_anti_rollback_disable__in_t fuse_anti_rollback_disable; @@ -1043,7 +1043,11 @@ package soc_ifc_reg_pkg; } soc_ifc_reg__fuse_key_manifest_pk_hash__out_t; typedef struct packed{ - soc_ifc_reg__Fuse_w32__out_t mask; + logic [3:0] value; + } soc_ifc_reg__Fuse_w4__out_t; + + typedef struct packed{ + soc_ifc_reg__Fuse_w4__out_t mask; } soc_ifc_reg__fuse_key_manifest_pk_hash_mask__out_t; typedef struct packed{ @@ -1074,10 +1078,6 @@ package soc_ifc_reg_pkg; soc_ifc_reg__Fuse_w32__out_t lms_revocation; } soc_ifc_reg__fuse_lms_revocation__out_t; - typedef struct packed{ - logic [3:0] value; - } soc_ifc_reg__Fuse_w4__out_t; - typedef struct packed{ soc_ifc_reg__Fuse_w4__out_t mldsa_revocation; } soc_ifc_reg__fuse_mldsa_revocation__out_t; @@ -1406,7 +1406,7 @@ package soc_ifc_reg_pkg; soc_ifc_reg__fuse_uds_seed__out_t [16-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__out_t [8-1:0]fuse_field_entropy; soc_ifc_reg__fuse_key_manifest_pk_hash__out_t [12-1:0]fuse_key_manifest_pk_hash; - soc_ifc_reg__fuse_key_manifest_pk_hash_mask__out_t [8-1:0]fuse_key_manifest_pk_hash_mask; + soc_ifc_reg__fuse_key_manifest_pk_hash_mask__out_t fuse_key_manifest_pk_hash_mask; soc_ifc_reg__fuse_fmc_key_manifest_svn__out_t fuse_fmc_key_manifest_svn; soc_ifc_reg__fuse_runtime_svn__out_t [4-1:0]fuse_runtime_svn; soc_ifc_reg__fuse_anti_rollback_disable__out_t fuse_anti_rollback_disable; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv index df96f25fc..7af7479f9 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv @@ -1605,7 +1605,7 @@ package soc_ifc_reg_uvm; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__fuse_key_manifest_pk_hash_mask_bit_cg mask_bit_cg[32]; + soc_ifc_reg__fuse_key_manifest_pk_hash_mask_bit_cg mask_bit_cg[4]; soc_ifc_reg__fuse_key_manifest_pk_hash_mask_fld_cg fld_cg; rand uvm_reg_field mask; @@ -1620,7 +1620,7 @@ package soc_ifc_reg_uvm; virtual function void build(); this.mask = new("mask"); - this.mask.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0); + this.mask.configure(this, 4, 0, "RW", 0, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin foreach(mask_bit_cg[bt]) mask_bit_cg[bt] = new(); end @@ -4494,7 +4494,7 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__fuse_uds_seed fuse_uds_seed[16]; rand soc_ifc_reg__fuse_field_entropy fuse_field_entropy[8]; rand soc_ifc_reg__fuse_key_manifest_pk_hash fuse_key_manifest_pk_hash[12]; - rand soc_ifc_reg__fuse_key_manifest_pk_hash_mask fuse_key_manifest_pk_hash_mask[8]; + rand soc_ifc_reg__fuse_key_manifest_pk_hash_mask fuse_key_manifest_pk_hash_mask; rand soc_ifc_reg__fuse_fmc_key_manifest_svn fuse_fmc_key_manifest_svn; rand soc_ifc_reg__fuse_runtime_svn fuse_runtime_svn[4]; rand soc_ifc_reg__fuse_anti_rollback_disable fuse_anti_rollback_disable; @@ -4818,13 +4818,11 @@ package soc_ifc_reg_uvm; this.fuse_key_manifest_pk_hash[i0].build(); this.default_map.add_reg(this.fuse_key_manifest_pk_hash[i0], 'h260 + i0*'h4); end - foreach(this.fuse_key_manifest_pk_hash_mask[i0]) begin - this.fuse_key_manifest_pk_hash_mask[i0] = new($sformatf("fuse_key_manifest_pk_hash_mask[%0d]", i0)); - this.fuse_key_manifest_pk_hash_mask[i0].configure(this); - - this.fuse_key_manifest_pk_hash_mask[i0].build(); - this.default_map.add_reg(this.fuse_key_manifest_pk_hash_mask[i0], 'h290 + i0*'h4); - end + this.fuse_key_manifest_pk_hash_mask = new("fuse_key_manifest_pk_hash_mask"); + this.fuse_key_manifest_pk_hash_mask.configure(this); + + this.fuse_key_manifest_pk_hash_mask.build(); + this.default_map.add_reg(this.fuse_key_manifest_pk_hash_mask, 'h290); this.fuse_fmc_key_manifest_svn = new("fuse_fmc_key_manifest_svn"); this.fuse_fmc_key_manifest_svn.configure(this); From 68445231f13fd6b795e195c482fbb38173eaf362 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 19 Dec 2024 10:42:39 -0800 Subject: [PATCH 2/9] Fix swwel to hash mask fuse --- src/soc_ifc/rtl/soc_ifc_top.sv | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 06d7c8f86..15a314aed 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -649,9 +649,6 @@ always_comb begin for (int i=0; i<12; i++) begin soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash[i].hash.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; end - for (int i=0; i<8; i++) begin - soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash_mask[i].mask.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; - end for (int i=0; i < `CLP_OBF_FE_DWORDS; i++) begin soc_ifc_reg_hwif_in.fuse_field_entropy[i].seed.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; @@ -674,6 +671,7 @@ always_comb begin end end +always_comb soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; always_comb soc_ifc_reg_hwif_in.fuse_fmc_key_manifest_svn.svn.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; always_comb soc_ifc_reg_hwif_in.fuse_anti_rollback_disable.dis.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; always_comb soc_ifc_reg_hwif_in.fuse_lms_revocation.lms_revocation.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; From 411fc9e8240b1bc8e587e26cac634449ba8d9d03 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 19 Dec 2024 13:47:33 -0800 Subject: [PATCH 3/9] Update soc_ifc_cov_if for fuse resize --- src/soc_ifc/coverage/soc_ifc_cov_if.sv | 82 +++----------------------- 1 file changed, 9 insertions(+), 73 deletions(-) diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv index 6a08acf95..9ac30dc99 100644 --- a/src/soc_ifc/coverage/soc_ifc_cov_if.sv +++ b/src/soc_ifc/coverage/soc_ifc_cov_if.sv @@ -717,17 +717,9 @@ interface soc_ifc_cov_if assign full_addr_fuse_key_manifest_pk_hash[10] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10; assign full_addr_fuse_key_manifest_pk_hash[11] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11; - logic hit_fuse_key_manifest_pk_hash_mask[0:7]; - logic [3:0] bus_fuse_key_manifest_pk_hash_mask[0:7]; - logic [31:0] full_addr_fuse_key_manifest_pk_hash_mask[0:7]; - assign full_addr_fuse_key_manifest_pk_hash_mask[0] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0; - assign full_addr_fuse_key_manifest_pk_hash_mask[1] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1; - assign full_addr_fuse_key_manifest_pk_hash_mask[2] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2; - assign full_addr_fuse_key_manifest_pk_hash_mask[3] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3; - assign full_addr_fuse_key_manifest_pk_hash_mask[4] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4; - assign full_addr_fuse_key_manifest_pk_hash_mask[5] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5; - assign full_addr_fuse_key_manifest_pk_hash_mask[6] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6; - assign full_addr_fuse_key_manifest_pk_hash_mask[7] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7; + logic hit_fuse_key_manifest_pk_hash_mask; + logic [3:0] bus_fuse_key_manifest_pk_hash_mask; + logic [31:0] full_addr_fuse_key_manifest_pk_hash_mask = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK; logic hit_fuse_fmc_key_manifest_svn; logic [3:0] bus_fuse_fmc_key_manifest_svn; @@ -1470,29 +1462,8 @@ interface soc_ifc_cov_if assign hit_fuse_key_manifest_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[11][18-1:0]); assign bus_fuse_key_manifest_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[11]}}; - assign hit_fuse_key_manifest_pk_hash_mask[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[0][AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[0]}}; - - assign hit_fuse_key_manifest_pk_hash_mask[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[1][AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[1]}}; - - assign hit_fuse_key_manifest_pk_hash_mask[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[2][AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[2]}}; - - assign hit_fuse_key_manifest_pk_hash_mask[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[3][AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[3]}}; - - assign hit_fuse_key_manifest_pk_hash_mask[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[4][AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[4]}}; - - assign hit_fuse_key_manifest_pk_hash_mask[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[5][AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[5]}}; - - assign hit_fuse_key_manifest_pk_hash_mask[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[6][AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[6]}}; - - assign hit_fuse_key_manifest_pk_hash_mask[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[7][AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[7]}}; + assign hit_fuse_key_manifest_pk_hash_mask = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[AXI_ADDR_WIDTH-1:0]); + assign bus_fuse_key_manifest_pk_hash_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask}}; assign hit_fuse_fmc_key_manifest_svn = (soc_ifc_reg_req_data.addr == full_addr_fuse_fmc_key_manifest_svn[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_fmc_key_manifest_svn = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_fmc_key_manifest_svn}}; @@ -2689,45 +2660,10 @@ interface soc_ifc_cov_if } endgroup - // ----------------------- COVERGROUP fuse_key_manifest_pk_hash_mask [0:7] ----------------------- - covergroup soc_ifc_fuse_key_manifest_pk_hash_mask_cg (ref logic [3:0] bus_event[0:7]) @(posedge clk); - fuse_key_manifest_pk_hash_mask0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask[0]; - bus_fuse_key_manifest_pk_hash_mask0_cp : coverpoint bus_event[0] { - bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); - ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; - } - fuse_key_manifest_pk_hash_mask1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask[1]; - bus_fuse_key_manifest_pk_hash_mask1_cp : coverpoint bus_event[1] { - bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); - ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; - } - fuse_key_manifest_pk_hash_mask2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask[2]; - bus_fuse_key_manifest_pk_hash_mask2_cp : coverpoint bus_event[2] { - bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); - ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; - } - fuse_key_manifest_pk_hash_mask3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask[3]; - bus_fuse_key_manifest_pk_hash_mask3_cp : coverpoint bus_event[3] { - bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); - ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; - } - fuse_key_manifest_pk_hash_mask4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask[4]; - bus_fuse_key_manifest_pk_hash_mask4_cp : coverpoint bus_event[4] { - bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); - ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; - } - fuse_key_manifest_pk_hash_mask5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask[5]; - bus_fuse_key_manifest_pk_hash_mask5_cp : coverpoint bus_event[5] { - bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); - ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; - } - fuse_key_manifest_pk_hash_mask6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask[6]; - bus_fuse_key_manifest_pk_hash_mask6_cp : coverpoint bus_event[6] { - bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); - ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; - } - fuse_key_manifest_pk_hash_mask7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask[7]; - bus_fuse_key_manifest_pk_hash_mask7_cp : coverpoint bus_event[7] { + // ----------------------- COVERGROUP fuse_key_manifest_pk_hash_mask ----------------------- + covergroup soc_ifc_fuse_key_manifest_pk_hash_mask_cg (ref logic [3:0] bus_event) @(posedge clk); + fuse_key_manifest_pk_hash_mask_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask; + bus_fuse_key_manifest_pk_hash_mask_cp : coverpoint bus_event { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } From 266b6e1abbbe610393b27a4416ddab80156b2132 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 16 Jan 2025 16:57:54 -0800 Subject: [PATCH 4/9] Rename key_manifest hash fuses; add new 2.0 fuses; regenerate RDL and coverage files --- src/integration/rtl/caliptra_reg.h | 72 +-- src/integration/rtl/caliptra_reg_defines.svh | 72 +-- src/soc_ifc/coverage/soc_ifc_cov_if.sv | 233 +++++++--- src/soc_ifc/rtl/caliptra_top_reg.h | 72 +-- src/soc_ifc/rtl/caliptra_top_reg_defines.svh | 72 +-- src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl | 47 +- src/soc_ifc/rtl/soc_ifc_reg.sv | 465 ++++++++++++------- src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh | 76 ++- src/soc_ifc/rtl/soc_ifc_reg_pkg.sv | 66 ++- src/soc_ifc/rtl/soc_ifc_reg_sample.svh | 95 +++- src/soc_ifc/rtl/soc_ifc_reg_uvm.sv | 164 +++++-- src/soc_ifc/rtl/soc_ifc_top.sv | 10 +- src/soc_ifc/tb/fuse_reg_pauser_test.svh | 14 +- tools/scripts/gen_soc_ifc_covergroups.py | 7 +- 14 files changed, 1029 insertions(+), 436 deletions(-) diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index e53da24fe..f2e26ec37 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -6051,34 +6051,34 @@ #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 (0x258) #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (0x3003025c) #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (0x25c) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0 (0x30030260) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0 (0x260) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_1 (0x30030264) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_1 (0x264) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_2 (0x30030268) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_2 (0x268) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_3 (0x3003026c) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_3 (0x26c) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_4 (0x30030270) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_4 (0x270) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_5 (0x30030274) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_5 (0x274) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_6 (0x30030278) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_6 (0x278) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_7 (0x3003027c) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_7 (0x27c) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_8 (0x30030280) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_8 (0x280) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_9 (0x30030284) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_9 (0x284) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (0x30030288) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (0x288) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x3003028c) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x28c) -#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x30030290) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x290) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0) -#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (0xf) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (0x30030260) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (0x260) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (0x30030264) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (0x264) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (0x30030268) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (0x268) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (0x3003026c) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (0x26c) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (0x30030270) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (0x270) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (0x30030274) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (0x274) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (0x30030278) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (0x278) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (0x3003027c) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (0x27c) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (0x30030280) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (0x280) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (0x30030284) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (0x284) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (0x30030288) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (0x288) +#define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (0x3003028c) +#define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (0x28c) +#define CLP_SOC_IFC_REG_FUSE_ECC_REVOCATION (0x30030290) +#define SOC_IFC_REG_FUSE_ECC_REVOCATION (0x290) +#define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) +#define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (0xf) #define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x300302b4) #define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2b4) #define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (0x300302b8) @@ -6167,6 +6167,22 @@ #define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x354) #define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x30030358) #define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x358) +#define CLP_SOC_IFC_REG_FUSE_PQC_KEY_TYPE (0x3003035c) +#define SOC_IFC_REG_FUSE_PQC_KEY_TYPE (0x35c) +#define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) +#define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (0x3) +#define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (0x30030360) +#define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (0x360) +#define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (0x30030364) +#define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (0x364) +#define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (0x30030368) +#define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (0x368) +#define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (0x3003036c) +#define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (0x36c) +#define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (0x30030370) +#define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (0x370) +#define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) +#define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (0xff) #define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (0x30030500) #define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (0x500) #define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (0x30030504) diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index f40346a71..293318681 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -6051,34 +6051,34 @@ `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 (32'h258) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (32'h3003025c) `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (32'h25c) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0 (32'h30030260) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0 (32'h260) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_1 (32'h30030264) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_1 (32'h264) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_2 (32'h30030268) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_2 (32'h268) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_3 (32'h3003026c) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_3 (32'h26c) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_4 (32'h30030270) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_4 (32'h270) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_5 (32'h30030274) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_5 (32'h274) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_6 (32'h30030278) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_6 (32'h278) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_7 (32'h3003027c) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_7 (32'h27c) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_8 (32'h30030280) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_8 (32'h280) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_9 (32'h30030284) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_9 (32'h284) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (32'h30030288) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (32'h288) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h3003028c) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h28c) -`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h30030290) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h290) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0) -`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (32'hf) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (32'h30030260) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (32'h260) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (32'h30030264) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (32'h264) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (32'h30030268) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (32'h268) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (32'h3003026c) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (32'h26c) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (32'h30030270) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (32'h270) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (32'h30030274) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (32'h274) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (32'h30030278) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (32'h278) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (32'h3003027c) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (32'h27c) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (32'h30030280) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (32'h280) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (32'h30030284) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (32'h284) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (32'h30030288) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (32'h288) +`define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (32'h3003028c) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (32'h28c) +`define CLP_SOC_IFC_REG_FUSE_ECC_REVOCATION (32'h30030290) +`define SOC_IFC_REG_FUSE_ECC_REVOCATION (32'h290) +`define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) +`define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (32'hf) `define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h300302b4) `define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) `define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h300302b8) @@ -6167,6 +6167,22 @@ `define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354) `define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h30030358) `define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358) +`define CLP_SOC_IFC_REG_FUSE_PQC_KEY_TYPE (32'h3003035c) +`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE (32'h35c) +`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) +`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (32'h3) +`define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h30030360) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h360) +`define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h30030364) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h364) +`define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h30030368) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h368) +`define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h3003036c) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h36c) +`define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h30030370) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h370) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (32'hff) `define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (32'h30030500) `define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500) `define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (32'h30030504) diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv index 9ac30dc99..4dac98725 100644 --- a/src/soc_ifc/coverage/soc_ifc_cov_if.sv +++ b/src/soc_ifc/coverage/soc_ifc_cov_if.sv @@ -701,25 +701,25 @@ interface soc_ifc_cov_if assign full_addr_fuse_field_entropy[6] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_6; assign full_addr_fuse_field_entropy[7] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_7; - logic hit_fuse_key_manifest_pk_hash[0:11]; - logic [3:0] bus_fuse_key_manifest_pk_hash[0:11]; - logic [31:0] full_addr_fuse_key_manifest_pk_hash[0:11]; - assign full_addr_fuse_key_manifest_pk_hash[0] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0; - assign full_addr_fuse_key_manifest_pk_hash[1] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_1; - assign full_addr_fuse_key_manifest_pk_hash[2] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_2; - assign full_addr_fuse_key_manifest_pk_hash[3] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_3; - assign full_addr_fuse_key_manifest_pk_hash[4] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_4; - assign full_addr_fuse_key_manifest_pk_hash[5] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_5; - assign full_addr_fuse_key_manifest_pk_hash[6] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_6; - assign full_addr_fuse_key_manifest_pk_hash[7] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_7; - assign full_addr_fuse_key_manifest_pk_hash[8] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_8; - assign full_addr_fuse_key_manifest_pk_hash[9] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_9; - assign full_addr_fuse_key_manifest_pk_hash[10] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10; - assign full_addr_fuse_key_manifest_pk_hash[11] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11; - - logic hit_fuse_key_manifest_pk_hash_mask; - logic [3:0] bus_fuse_key_manifest_pk_hash_mask; - logic [31:0] full_addr_fuse_key_manifest_pk_hash_mask = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK; + logic hit_fuse_vendor_pk_hash[0:11]; + logic [3:0] bus_fuse_vendor_pk_hash[0:11]; + logic [31:0] full_addr_fuse_vendor_pk_hash[0:11]; + assign full_addr_fuse_vendor_pk_hash[0] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0; + assign full_addr_fuse_vendor_pk_hash[1] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1; + assign full_addr_fuse_vendor_pk_hash[2] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2; + assign full_addr_fuse_vendor_pk_hash[3] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3; + assign full_addr_fuse_vendor_pk_hash[4] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4; + assign full_addr_fuse_vendor_pk_hash[5] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5; + assign full_addr_fuse_vendor_pk_hash[6] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6; + assign full_addr_fuse_vendor_pk_hash[7] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7; + assign full_addr_fuse_vendor_pk_hash[8] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8; + assign full_addr_fuse_vendor_pk_hash[9] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9; + assign full_addr_fuse_vendor_pk_hash[10] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10; + assign full_addr_fuse_vendor_pk_hash[11] = `CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11; + + logic hit_fuse_ecc_revocation; + logic [3:0] bus_fuse_ecc_revocation; + logic [31:0] full_addr_fuse_ecc_revocation = `CLP_SOC_IFC_REG_FUSE_ECC_REVOCATION; logic hit_fuse_fmc_key_manifest_svn; logic [3:0] bus_fuse_fmc_key_manifest_svn; @@ -793,6 +793,22 @@ interface soc_ifc_cov_if assign full_addr_fuse_manuf_dbg_unlock_token[2] = `CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2; assign full_addr_fuse_manuf_dbg_unlock_token[3] = `CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3; + logic hit_fuse_pqc_key_type; + logic [3:0] bus_fuse_pqc_key_type; + logic [31:0] full_addr_fuse_pqc_key_type = `CLP_SOC_IFC_REG_FUSE_PQC_KEY_TYPE; + + logic hit_fuse_soc_manifest_svn[0:3]; + logic [3:0] bus_fuse_soc_manifest_svn[0:3]; + logic [31:0] full_addr_fuse_soc_manifest_svn[0:3]; + assign full_addr_fuse_soc_manifest_svn[0] = `CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0; + assign full_addr_fuse_soc_manifest_svn[1] = `CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1; + assign full_addr_fuse_soc_manifest_svn[2] = `CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2; + assign full_addr_fuse_soc_manifest_svn[3] = `CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3; + + logic hit_fuse_soc_manifest_max_svn; + logic [3:0] bus_fuse_soc_manifest_max_svn; + logic [31:0] full_addr_fuse_soc_manifest_max_svn = `CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN; + logic hit_SS_CALIPTRA_BASE_ADDR_L; logic [3:0] bus_SS_CALIPTRA_BASE_ADDR_L; logic [31:0] full_addr_SS_CALIPTRA_BASE_ADDR_L = `CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L; @@ -1426,44 +1442,44 @@ interface soc_ifc_cov_if assign hit_fuse_field_entropy[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[7][18-1:0]); assign bus_fuse_field_entropy[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[7]}}; - assign hit_fuse_key_manifest_pk_hash[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[0][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[0]}}; + assign hit_fuse_vendor_pk_hash[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[0][18-1:0]); + assign bus_fuse_vendor_pk_hash[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[0]}}; - assign hit_fuse_key_manifest_pk_hash[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[1][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[1]}}; + assign hit_fuse_vendor_pk_hash[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[1][18-1:0]); + assign bus_fuse_vendor_pk_hash[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[1]}}; - assign hit_fuse_key_manifest_pk_hash[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[2][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[2]}}; + assign hit_fuse_vendor_pk_hash[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[2][18-1:0]); + assign bus_fuse_vendor_pk_hash[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[2]}}; - assign hit_fuse_key_manifest_pk_hash[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[3][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[3]}}; + assign hit_fuse_vendor_pk_hash[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[3][18-1:0]); + assign bus_fuse_vendor_pk_hash[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[3]}}; - assign hit_fuse_key_manifest_pk_hash[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[4][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[4]}}; + assign hit_fuse_vendor_pk_hash[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[4][18-1:0]); + assign bus_fuse_vendor_pk_hash[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[4]}}; - assign hit_fuse_key_manifest_pk_hash[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[5][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[5]}}; + assign hit_fuse_vendor_pk_hash[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[5][18-1:0]); + assign bus_fuse_vendor_pk_hash[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[5]}}; - assign hit_fuse_key_manifest_pk_hash[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[6][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[6]}}; + assign hit_fuse_vendor_pk_hash[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[6][18-1:0]); + assign bus_fuse_vendor_pk_hash[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[6]}}; - assign hit_fuse_key_manifest_pk_hash[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[7][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[7]}}; + assign hit_fuse_vendor_pk_hash[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[7][18-1:0]); + assign bus_fuse_vendor_pk_hash[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[7]}}; - assign hit_fuse_key_manifest_pk_hash[8] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[8][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[8]}}; + assign hit_fuse_vendor_pk_hash[8] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[8][18-1:0]); + assign bus_fuse_vendor_pk_hash[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[8]}}; - assign hit_fuse_key_manifest_pk_hash[9] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[9][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[9]}}; + assign hit_fuse_vendor_pk_hash[9] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[9][18-1:0]); + assign bus_fuse_vendor_pk_hash[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[9]}}; - assign hit_fuse_key_manifest_pk_hash[10] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[10][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[10]}}; + assign hit_fuse_vendor_pk_hash[10] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[10][18-1:0]); + assign bus_fuse_vendor_pk_hash[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[10]}}; - assign hit_fuse_key_manifest_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[11][18-1:0]); - assign bus_fuse_key_manifest_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[11]}}; + assign hit_fuse_vendor_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_vendor_pk_hash[11][18-1:0]); + assign bus_fuse_vendor_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_vendor_pk_hash[11]}}; - assign hit_fuse_key_manifest_pk_hash_mask = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[AXI_ADDR_WIDTH-1:0]); - assign bus_fuse_key_manifest_pk_hash_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask}}; + assign hit_fuse_ecc_revocation = (soc_ifc_reg_req_data.addr == full_addr_fuse_ecc_revocation[AXI_ADDR_WIDTH-1:0]); + assign bus_fuse_ecc_revocation = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_ecc_revocation}}; assign hit_fuse_fmc_key_manifest_svn = (soc_ifc_reg_req_data.addr == full_addr_fuse_fmc_key_manifest_svn[AXI_ADDR_WIDTH-1:0]); assign bus_fuse_fmc_key_manifest_svn = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_fmc_key_manifest_svn}}; @@ -1588,6 +1604,24 @@ interface soc_ifc_cov_if assign hit_fuse_manuf_dbg_unlock_token[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_manuf_dbg_unlock_token[3][18-1:0]); assign bus_fuse_manuf_dbg_unlock_token[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_manuf_dbg_unlock_token[3]}}; + assign hit_fuse_pqc_key_type = (soc_ifc_reg_req_data.addr == full_addr_fuse_pqc_key_type[AXI_ADDR_WIDTH-1:0]); + assign bus_fuse_pqc_key_type = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_pqc_key_type}}; + + assign hit_fuse_soc_manifest_svn[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_manifest_svn[0][18-1:0]); + assign bus_fuse_soc_manifest_svn[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_manifest_svn[0]}}; + + assign hit_fuse_soc_manifest_svn[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_manifest_svn[1][18-1:0]); + assign bus_fuse_soc_manifest_svn[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_manifest_svn[1]}}; + + assign hit_fuse_soc_manifest_svn[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_manifest_svn[2][18-1:0]); + assign bus_fuse_soc_manifest_svn[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_manifest_svn[2]}}; + + assign hit_fuse_soc_manifest_svn[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_manifest_svn[3][18-1:0]); + assign bus_fuse_soc_manifest_svn[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_manifest_svn[3]}}; + + assign hit_fuse_soc_manifest_max_svn = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_manifest_max_svn[AXI_ADDR_WIDTH-1:0]); + assign bus_fuse_soc_manifest_max_svn = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_manifest_max_svn}}; + assign hit_SS_CALIPTRA_BASE_ADDR_L = (soc_ifc_reg_req_data.addr == full_addr_SS_CALIPTRA_BASE_ADDR_L[AXI_ADDR_WIDTH-1:0]); assign bus_SS_CALIPTRA_BASE_ADDR_L = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_SS_CALIPTRA_BASE_ADDR_L}}; @@ -2596,74 +2630,74 @@ interface soc_ifc_cov_if } endgroup - // ----------------------- COVERGROUP fuse_key_manifest_pk_hash [0:11] ----------------------- - covergroup soc_ifc_fuse_key_manifest_pk_hash_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk); - fuse_key_manifest_pk_hash0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[0]; - bus_fuse_key_manifest_pk_hash0_cp : coverpoint bus_event[0] { + // ----------------------- COVERGROUP fuse_vendor_pk_hash [0:11] ----------------------- + covergroup soc_ifc_fuse_vendor_pk_hash_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk); + fuse_vendor_pk_hash0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[0]; + bus_fuse_vendor_pk_hash0_cp : coverpoint bus_event[0] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[1]; - bus_fuse_key_manifest_pk_hash1_cp : coverpoint bus_event[1] { + fuse_vendor_pk_hash1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[1]; + bus_fuse_vendor_pk_hash1_cp : coverpoint bus_event[1] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[2]; - bus_fuse_key_manifest_pk_hash2_cp : coverpoint bus_event[2] { + fuse_vendor_pk_hash2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[2]; + bus_fuse_vendor_pk_hash2_cp : coverpoint bus_event[2] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[3]; - bus_fuse_key_manifest_pk_hash3_cp : coverpoint bus_event[3] { + fuse_vendor_pk_hash3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[3]; + bus_fuse_vendor_pk_hash3_cp : coverpoint bus_event[3] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[4]; - bus_fuse_key_manifest_pk_hash4_cp : coverpoint bus_event[4] { + fuse_vendor_pk_hash4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[4]; + bus_fuse_vendor_pk_hash4_cp : coverpoint bus_event[4] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[5]; - bus_fuse_key_manifest_pk_hash5_cp : coverpoint bus_event[5] { + fuse_vendor_pk_hash5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[5]; + bus_fuse_vendor_pk_hash5_cp : coverpoint bus_event[5] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[6]; - bus_fuse_key_manifest_pk_hash6_cp : coverpoint bus_event[6] { + fuse_vendor_pk_hash6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[6]; + bus_fuse_vendor_pk_hash6_cp : coverpoint bus_event[6] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[7]; - bus_fuse_key_manifest_pk_hash7_cp : coverpoint bus_event[7] { + fuse_vendor_pk_hash7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[7]; + bus_fuse_vendor_pk_hash7_cp : coverpoint bus_event[7] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[8]; - bus_fuse_key_manifest_pk_hash8_cp : coverpoint bus_event[8] { + fuse_vendor_pk_hash8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[8]; + bus_fuse_vendor_pk_hash8_cp : coverpoint bus_event[8] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[9]; - bus_fuse_key_manifest_pk_hash9_cp : coverpoint bus_event[9] { + fuse_vendor_pk_hash9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[9]; + bus_fuse_vendor_pk_hash9_cp : coverpoint bus_event[9] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[10]; - bus_fuse_key_manifest_pk_hash10_cp : coverpoint bus_event[10] { + fuse_vendor_pk_hash10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[10]; + bus_fuse_vendor_pk_hash10_cp : coverpoint bus_event[10] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } - fuse_key_manifest_pk_hash11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[11]; - bus_fuse_key_manifest_pk_hash11_cp : coverpoint bus_event[11] { + fuse_vendor_pk_hash11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_vendor_pk_hash[11]; + bus_fuse_vendor_pk_hash11_cp : coverpoint bus_event[11] { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } endgroup - // ----------------------- COVERGROUP fuse_key_manifest_pk_hash_mask ----------------------- - covergroup soc_ifc_fuse_key_manifest_pk_hash_mask_cg (ref logic [3:0] bus_event) @(posedge clk); - fuse_key_manifest_pk_hash_mask_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask; - bus_fuse_key_manifest_pk_hash_mask_cp : coverpoint bus_event { + // ----------------------- COVERGROUP fuse_ecc_revocation ----------------------- + covergroup soc_ifc_fuse_ecc_revocation_cg (ref logic [3:0] bus_event) @(posedge clk); + fuse_ecc_revocation_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_ecc_revocation; + bus_fuse_ecc_revocation_cp : coverpoint bus_event { bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; } @@ -2910,6 +2944,48 @@ interface soc_ifc_cov_if } endgroup + // ----------------------- COVERGROUP fuse_pqc_key_type ----------------------- + covergroup soc_ifc_fuse_pqc_key_type_cg (ref logic [3:0] bus_event) @(posedge clk); + fuse_pqc_key_type_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_pqc_key_type; + bus_fuse_pqc_key_type_cp : coverpoint bus_event { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; + } + endgroup + + // ----------------------- COVERGROUP fuse_soc_manifest_svn [0:3] ----------------------- + covergroup soc_ifc_fuse_soc_manifest_svn_cg (ref logic [3:0] bus_event[0:3]) @(posedge clk); + fuse_soc_manifest_svn0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_soc_manifest_svn[0]; + bus_fuse_soc_manifest_svn0_cp : coverpoint bus_event[0] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; + } + fuse_soc_manifest_svn1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_soc_manifest_svn[1]; + bus_fuse_soc_manifest_svn1_cp : coverpoint bus_event[1] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; + } + fuse_soc_manifest_svn2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_soc_manifest_svn[2]; + bus_fuse_soc_manifest_svn2_cp : coverpoint bus_event[2] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; + } + fuse_soc_manifest_svn3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_soc_manifest_svn[3]; + bus_fuse_soc_manifest_svn3_cp : coverpoint bus_event[3] { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; + } + endgroup + + // ----------------------- COVERGROUP fuse_soc_manifest_max_svn ----------------------- + covergroup soc_ifc_fuse_soc_manifest_max_svn_cg (ref logic [3:0] bus_event) @(posedge clk); + fuse_soc_manifest_max_svn_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_soc_manifest_max_svn; + bus_fuse_soc_manifest_max_svn_cp : coverpoint bus_event { + bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD); + ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)}; + } + endgroup + // ----------------------- COVERGROUP SS_CALIPTRA_BASE_ADDR_L ----------------------- covergroup soc_ifc_SS_CALIPTRA_BASE_ADDR_L_cg (ref logic [3:0] bus_event) @(posedge clk); SS_CALIPTRA_BASE_ADDR_L_cp : coverpoint i_soc_ifc_reg.field_storage.SS_CALIPTRA_BASE_ADDR_L; @@ -3643,8 +3719,8 @@ interface soc_ifc_cov_if soc_ifc_CPTRA_OWNER_PK_HASH_LOCK_cg CPTRA_OWNER_PK_HASH_LOCK_cg = new(bus_CPTRA_OWNER_PK_HASH_LOCK); soc_ifc_fuse_uds_seed_cg fuse_uds_seed_cg = new(bus_fuse_uds_seed); soc_ifc_fuse_field_entropy_cg fuse_field_entropy_cg = new(bus_fuse_field_entropy); - soc_ifc_fuse_key_manifest_pk_hash_cg fuse_key_manifest_pk_hash_cg = new(bus_fuse_key_manifest_pk_hash); - soc_ifc_fuse_key_manifest_pk_hash_mask_cg fuse_key_manifest_pk_hash_mask_cg = new(bus_fuse_key_manifest_pk_hash_mask); + soc_ifc_fuse_vendor_pk_hash_cg fuse_vendor_pk_hash_cg = new(bus_fuse_vendor_pk_hash); + soc_ifc_fuse_ecc_revocation_cg fuse_ecc_revocation_cg = new(bus_fuse_ecc_revocation); soc_ifc_fuse_fmc_key_manifest_svn_cg fuse_fmc_key_manifest_svn_cg = new(bus_fuse_fmc_key_manifest_svn); soc_ifc_fuse_runtime_svn_cg fuse_runtime_svn_cg = new(bus_fuse_runtime_svn); soc_ifc_fuse_anti_rollback_disable_cg fuse_anti_rollback_disable_cg = new(bus_fuse_anti_rollback_disable); @@ -3654,6 +3730,9 @@ interface soc_ifc_cov_if soc_ifc_fuse_mldsa_revocation_cg fuse_mldsa_revocation_cg = new(bus_fuse_mldsa_revocation); soc_ifc_fuse_soc_stepping_id_cg fuse_soc_stepping_id_cg = new(bus_fuse_soc_stepping_id); soc_ifc_fuse_manuf_dbg_unlock_token_cg fuse_manuf_dbg_unlock_token_cg = new(bus_fuse_manuf_dbg_unlock_token); + soc_ifc_fuse_pqc_key_type_cg fuse_pqc_key_type_cg = new(bus_fuse_pqc_key_type); + soc_ifc_fuse_soc_manifest_svn_cg fuse_soc_manifest_svn_cg = new(bus_fuse_soc_manifest_svn); + soc_ifc_fuse_soc_manifest_max_svn_cg fuse_soc_manifest_max_svn_cg = new(bus_fuse_soc_manifest_max_svn); soc_ifc_SS_CALIPTRA_BASE_ADDR_L_cg SS_CALIPTRA_BASE_ADDR_L_cg = new(bus_SS_CALIPTRA_BASE_ADDR_L); soc_ifc_SS_CALIPTRA_BASE_ADDR_H_cg SS_CALIPTRA_BASE_ADDR_H_cg = new(bus_SS_CALIPTRA_BASE_ADDR_H); soc_ifc_SS_MCI_BASE_ADDR_L_cg SS_MCI_BASE_ADDR_L_cg = new(bus_SS_MCI_BASE_ADDR_L); diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index fbcffa8c3..dc0794cf1 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -393,34 +393,34 @@ #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 (0x258) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (0x3025c) #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (0x25c) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_0 (0x30260) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_0 (0x260) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_1 (0x30264) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_1 (0x264) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_2 (0x30268) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_2 (0x268) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_3 (0x3026c) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_3 (0x26c) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_4 (0x30270) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_4 (0x270) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_5 (0x30274) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_5 (0x274) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_6 (0x30278) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_6 (0x278) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_7 (0x3027c) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_7 (0x27c) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_8 (0x30280) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_8 (0x280) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_9 (0x30284) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_9 (0x284) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (0x30288) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (0x288) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x3028c) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x28c) -#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x30290) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x290) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0) -#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (0xf) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (0x30260) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (0x260) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (0x30264) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (0x264) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (0x30268) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (0x268) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (0x3026c) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (0x26c) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (0x30270) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (0x270) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (0x30274) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (0x274) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (0x30278) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (0x278) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (0x3027c) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (0x27c) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (0x30280) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (0x280) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (0x30284) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (0x284) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (0x30288) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (0x288) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (0x3028c) +#define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (0x28c) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (0x30290) +#define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (0x290) +#define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) +#define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (0xf) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x302b4) #define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2b4) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (0x302b8) @@ -509,6 +509,22 @@ #define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x354) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x30358) #define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x358) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (0x3035c) +#define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (0x35c) +#define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) +#define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (0x3) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (0x30360) +#define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (0x360) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (0x30364) +#define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (0x364) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (0x30368) +#define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (0x368) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (0x3036c) +#define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (0x36c) +#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (0x30370) +#define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (0x370) +#define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) +#define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (0xff) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (0x30500) #define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (0x500) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (0x30504) diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index f734a0907..da059b043 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -393,34 +393,34 @@ `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 (32'h258) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (32'h3025c) `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (32'h25c) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_0 (32'h30260) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_0 (32'h260) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_1 (32'h30264) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_1 (32'h264) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_2 (32'h30268) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_2 (32'h268) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_3 (32'h3026c) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_3 (32'h26c) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_4 (32'h30270) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_4 (32'h270) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_5 (32'h30274) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_5 (32'h274) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_6 (32'h30278) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_6 (32'h278) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_7 (32'h3027c) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_7 (32'h27c) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_8 (32'h30280) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_8 (32'h280) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_9 (32'h30284) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_9 (32'h284) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (32'h30288) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (32'h288) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h3028c) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h28c) -`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h30290) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h290) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0) -`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (32'hf) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (32'h30260) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (32'h260) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (32'h30264) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (32'h264) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (32'h30268) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (32'h268) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (32'h3026c) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (32'h26c) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (32'h30270) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (32'h270) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (32'h30274) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (32'h274) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (32'h30278) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (32'h278) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (32'h3027c) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (32'h27c) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (32'h30280) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (32'h280) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (32'h30284) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (32'h284) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (32'h30288) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (32'h288) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (32'h3028c) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (32'h28c) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (32'h30290) +`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (32'h290) +`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (32'hf) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h302b4) `define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h302b8) @@ -509,6 +509,22 @@ `define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h30358) `define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (32'h3035c) +`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (32'h35c) +`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (32'h3) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h30360) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h360) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h30364) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h364) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h30368) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h368) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h3036c) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h36c) +`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h30370) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h370) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (32'hff) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (32'h30500) `define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (32'h30504) diff --git a/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl b/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl index 7e42254df..db8ff8fee 100644 --- a/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl @@ -35,43 +35,50 @@ reg { secret seed[32]=0; } fuse_field_entropy[8]; reg { - desc = "Key Manifest PK hash Fuse. + name = "Vendor PK hash Fuse"; + desc = "Vendor PK hash Fuse. [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse hash[32]=0; -} fuse_key_manifest_pk_hash[12]; +} fuse_vendor_pk_hash[12]; reg { - desc = "Key Manifest Mask Fuse (ECC Revocation). + name = "ECC Revocation Fuse"; + desc = "ECC Revocation Fuse. [br]Caliptra Access: RO [br]SOC Access: RWL-S"; - Fuse mask[4]=0; -} fuse_key_manifest_pk_hash_mask; + Fuse ecc_revocation[4]=0; +} fuse_ecc_revocation; reg { + name = "FMC Security Version Number Fuse"; desc = "FMC Security Version Number. [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse svn[32]=0; } fuse_fmc_key_manifest_svn @0x2b4; reg { + name = "Runtime SVN Fuse"; desc = "Runtime SVN Fuse. [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse svn[32]=0; } fuse_runtime_svn[4]; reg { + name = "Anti Rollback Disable Fuse"; desc = "Anti Rollback Disable Fuse. [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse dis[1]=0; } fuse_anti_rollback_disable; reg { + name = "Manufacturer IEEE IDevID Certificate Gen Attributes Fuse"; desc = "Manufacturer IEEE IDevID Certificate Gen Attributes. [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse cert[32]=0; } fuse_idevid_cert_attr[24]; reg { + name = "Manufacturer IDevID HSM ID Fuse"; desc = " Manufacturer IDEVID Manufacturer’s HSM identifier (this is used to find the certificate chain from the boot media) [br]Caliptra Access: RO [br]SOC Access: RWL-S"; @@ -79,26 +86,56 @@ reg { } fuse_idevid_manuf_hsm_id[4]; reg { + name = "LMS Revocation Fuse"; desc = "One-hot encoded list of revoked Vendor LMS Public Keys (up to 32 keys) [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse lms_revocation[32]=0; } fuse_lms_revocation @0x340; reg { + name = "ML-DSA Revocation Fuse"; desc = "One-hot encoded list of revoked Vendor MLDSA Public Keys (up to 4 keys) [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse mldsa_revocation[4]=0; } fuse_mldsa_revocation; reg { + name = "SOC stepping ID Fuse"; desc = "SOC stepping ID [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse soc_stepping_id[16]=0; } fuse_soc_stepping_id; reg { + name = "Manufacturing Debug Unlock Token Fuse"; desc = "Manufacturing debug unlock token [br]Caliptra Access: RO [br]SOC Access: RWL-S"; Fuse token[32]=0; } fuse_manuf_dbg_unlock_token[4]; +reg { + name = "PQC Key Type Fuse"; + desc = "One-hot encoded selection of PQC key type for firmware validation. + [br] + [br]Field decode: + [br] [lb]0[rb] - MLDSA + [br] [lb]1[rb] - LMS + [br] + [br]Caliptra Access: RO + [br]SOC Access: RWL-S"; + Fuse key_type[2]=2'b0; +} fuse_pqc_key_type; +reg { + name = "SOC Manifest SVN Fuse"; + desc = "One-hot encoded value for the SOC authorization manifest minimum supported SVN. + [br]Caliptra Access: RO + [br]SOC Access: RWL-S"; + Fuse svn[32]=32'b0; +} fuse_soc_manifest_svn[4]; +reg { + name = "SOC Manifest Max SVN Fuse"; + desc = "Maximum value for the SOC authorization manifest SVN. + [br]Caliptra Access: RO + [br]SOC Access: RWL-S"; + Fuse svn[8]=8'b0; +} fuse_soc_manifest_max_svn; diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index 9d3183b18..421a38566 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -114,8 +114,8 @@ module soc_ifc_reg ( logic CPTRA_OWNER_PK_HASH_LOCK; logic [16-1:0]fuse_uds_seed; logic [8-1:0]fuse_field_entropy; - logic [12-1:0]fuse_key_manifest_pk_hash; - logic fuse_key_manifest_pk_hash_mask; + logic [12-1:0]fuse_vendor_pk_hash; + logic fuse_ecc_revocation; logic fuse_fmc_key_manifest_svn; logic [4-1:0]fuse_runtime_svn; logic fuse_anti_rollback_disable; @@ -125,6 +125,9 @@ module soc_ifc_reg ( logic fuse_mldsa_revocation; logic fuse_soc_stepping_id; logic [4-1:0]fuse_manuf_dbg_unlock_token; + logic fuse_pqc_key_type; + logic [4-1:0]fuse_soc_manifest_svn; + logic fuse_soc_manifest_max_svn; logic SS_CALIPTRA_BASE_ADDR_L; logic SS_CALIPTRA_BASE_ADDR_H; logic SS_MCI_BASE_ADDR_L; @@ -280,9 +283,9 @@ module soc_ifc_reg ( decoded_reg_strb.fuse_field_entropy[i0] = cpuif_req_masked & (cpuif_addr == 12'h240 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.fuse_key_manifest_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h260 + i0*12'h4); + decoded_reg_strb.fuse_vendor_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h260 + i0*12'h4); end - decoded_reg_strb.fuse_key_manifest_pk_hash_mask = cpuif_req_masked & (cpuif_addr == 12'h290); + decoded_reg_strb.fuse_ecc_revocation = cpuif_req_masked & (cpuif_addr == 12'h290); decoded_reg_strb.fuse_fmc_key_manifest_svn = cpuif_req_masked & (cpuif_addr == 12'h2b4); for(int i0=0; i0<4; i0++) begin decoded_reg_strb.fuse_runtime_svn[i0] = cpuif_req_masked & (cpuif_addr == 12'h2b8 + i0*12'h4); @@ -300,6 +303,11 @@ module soc_ifc_reg ( for(int i0=0; i0<4; i0++) begin decoded_reg_strb.fuse_manuf_dbg_unlock_token[i0] = cpuif_req_masked & (cpuif_addr == 12'h34c + i0*12'h4); end + decoded_reg_strb.fuse_pqc_key_type = cpuif_req_masked & (cpuif_addr == 12'h35c); + for(int i0=0; i0<4; i0++) begin + decoded_reg_strb.fuse_soc_manifest_svn[i0] = cpuif_req_masked & (cpuif_addr == 12'h360 + i0*12'h4); + end + decoded_reg_strb.fuse_soc_manifest_max_svn = cpuif_req_masked & (cpuif_addr == 12'h370); decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_L = cpuif_req_masked & (cpuif_addr == 12'h500); decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_H = cpuif_req_masked & (cpuif_addr == 12'h504); decoded_reg_strb.SS_MCI_BASE_ADDR_L = cpuif_req_masked & (cpuif_addr == 12'h508); @@ -719,13 +727,13 @@ module soc_ifc_reg ( logic [31:0] next; logic load_next; } hash; - } [12-1:0]fuse_key_manifest_pk_hash; + } [12-1:0]fuse_vendor_pk_hash; struct packed{ struct packed{ logic [3:0] next; logic load_next; - } mask; - } fuse_key_manifest_pk_hash_mask; + } ecc_revocation; + } fuse_ecc_revocation; struct packed{ struct packed{ logic [31:0] next; @@ -780,6 +788,24 @@ module soc_ifc_reg ( logic load_next; } token; } [4-1:0]fuse_manuf_dbg_unlock_token; + struct packed{ + struct packed{ + logic [1:0] next; + logic load_next; + } key_type; + } fuse_pqc_key_type; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + } svn; + } [4-1:0]fuse_soc_manifest_svn; + struct packed{ + struct packed{ + logic [7:0] next; + logic load_next; + } svn; + } fuse_soc_manifest_max_svn; struct packed{ struct packed{ logic [31:0] next; @@ -1729,12 +1755,12 @@ module soc_ifc_reg ( struct packed{ logic [31:0] value; } hash; - } [12-1:0]fuse_key_manifest_pk_hash; + } [12-1:0]fuse_vendor_pk_hash; struct packed{ struct packed{ logic [3:0] value; - } mask; - } fuse_key_manifest_pk_hash_mask; + } ecc_revocation; + } fuse_ecc_revocation; struct packed{ struct packed{ logic [31:0] value; @@ -1780,6 +1806,21 @@ module soc_ifc_reg ( logic [31:0] value; } token; } [4-1:0]fuse_manuf_dbg_unlock_token; + struct packed{ + struct packed{ + logic [1:0] value; + } key_type; + } fuse_pqc_key_type; + struct packed{ + struct packed{ + logic [31:0] value; + } svn; + } [4-1:0]fuse_soc_manifest_svn; + struct packed{ + struct packed{ + logic [7:0] value; + } svn; + } fuse_soc_manifest_max_svn; struct packed{ struct packed{ logic [31:0] value; @@ -3598,49 +3639,49 @@ module soc_ifc_reg ( assign hwif_out.fuse_field_entropy[i0].seed.value = field_storage.fuse_field_entropy[i0].seed.value; end for(genvar i0=0; i0<12; i0++) begin - // Field: soc_ifc_reg.fuse_key_manifest_pk_hash[].hash + // Field: soc_ifc_reg.fuse_vendor_pk_hash[].hash always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.fuse_key_manifest_pk_hash[i0].hash.value; + next_c = field_storage.fuse_vendor_pk_hash[i0].hash.value; load_next_c = '0; - if(decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash[i0].hash.swwel)) begin // SW write - next_c = (field_storage.fuse_key_manifest_pk_hash[i0].hash.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.fuse_vendor_pk_hash[i0] && decoded_req_is_wr && !(hwif_in.fuse_vendor_pk_hash[i0].hash.swwel)) begin // SW write + next_c = (field_storage.fuse_vendor_pk_hash[i0].hash.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.fuse_key_manifest_pk_hash[i0].hash.next = next_c; - field_combo.fuse_key_manifest_pk_hash[i0].hash.load_next = load_next_c; + field_combo.fuse_vendor_pk_hash[i0].hash.next = next_c; + field_combo.fuse_vendor_pk_hash[i0].hash.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= 32'h0; - end else if(field_combo.fuse_key_manifest_pk_hash[i0].hash.load_next) begin - field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= field_combo.fuse_key_manifest_pk_hash[i0].hash.next; + field_storage.fuse_vendor_pk_hash[i0].hash.value <= 32'h0; + end else if(field_combo.fuse_vendor_pk_hash[i0].hash.load_next) begin + field_storage.fuse_vendor_pk_hash[i0].hash.value <= field_combo.fuse_vendor_pk_hash[i0].hash.next; end end - assign hwif_out.fuse_key_manifest_pk_hash[i0].hash.value = field_storage.fuse_key_manifest_pk_hash[i0].hash.value; + assign hwif_out.fuse_vendor_pk_hash[i0].hash.value = field_storage.fuse_vendor_pk_hash[i0].hash.value; end - // Field: soc_ifc_reg.fuse_key_manifest_pk_hash_mask.mask + // Field: soc_ifc_reg.fuse_ecc_revocation.ecc_revocation always_comb begin automatic logic [3:0] next_c; automatic logic load_next_c; - next_c = field_storage.fuse_key_manifest_pk_hash_mask.mask.value; + next_c = field_storage.fuse_ecc_revocation.ecc_revocation.value; load_next_c = '0; - if(decoded_reg_strb.fuse_key_manifest_pk_hash_mask && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel)) begin // SW write - next_c = (field_storage.fuse_key_manifest_pk_hash_mask.mask.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]); + if(decoded_reg_strb.fuse_ecc_revocation && decoded_req_is_wr && !(hwif_in.fuse_ecc_revocation.ecc_revocation.swwel)) begin // SW write + next_c = (field_storage.fuse_ecc_revocation.ecc_revocation.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]); load_next_c = '1; end - field_combo.fuse_key_manifest_pk_hash_mask.mask.next = next_c; - field_combo.fuse_key_manifest_pk_hash_mask.mask.load_next = load_next_c; + field_combo.fuse_ecc_revocation.ecc_revocation.next = next_c; + field_combo.fuse_ecc_revocation.ecc_revocation.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= 4'h0; - end else if(field_combo.fuse_key_manifest_pk_hash_mask.mask.load_next) begin - field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= field_combo.fuse_key_manifest_pk_hash_mask.mask.next; + field_storage.fuse_ecc_revocation.ecc_revocation.value <= 4'h0; + end else if(field_combo.fuse_ecc_revocation.ecc_revocation.load_next) begin + field_storage.fuse_ecc_revocation.ecc_revocation.value <= field_combo.fuse_ecc_revocation.ecc_revocation.next; end end - assign hwif_out.fuse_key_manifest_pk_hash_mask.mask.value = field_storage.fuse_key_manifest_pk_hash_mask.mask.value; + assign hwif_out.fuse_ecc_revocation.ecc_revocation.value = field_storage.fuse_ecc_revocation.ecc_revocation.value; // Field: soc_ifc_reg.fuse_fmc_key_manifest_svn.svn always_comb begin automatic logic [31:0] next_c; @@ -3838,6 +3879,71 @@ module soc_ifc_reg ( end assign hwif_out.fuse_manuf_dbg_unlock_token[i0].token.value = field_storage.fuse_manuf_dbg_unlock_token[i0].token.value; end + // Field: soc_ifc_reg.fuse_pqc_key_type.key_type + always_comb begin + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_pqc_key_type.key_type.value; + load_next_c = '0; + if(decoded_reg_strb.fuse_pqc_key_type && decoded_req_is_wr && !(hwif_in.fuse_pqc_key_type.key_type.swwel)) begin // SW write + next_c = (field_storage.fuse_pqc_key_type.key_type.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); + load_next_c = '1; + end + field_combo.fuse_pqc_key_type.key_type.next = next_c; + field_combo.fuse_pqc_key_type.key_type.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin + if(~hwif_in.cptra_pwrgood) begin + field_storage.fuse_pqc_key_type.key_type.value <= 2'h0; + end else if(field_combo.fuse_pqc_key_type.key_type.load_next) begin + field_storage.fuse_pqc_key_type.key_type.value <= field_combo.fuse_pqc_key_type.key_type.next; + end + end + assign hwif_out.fuse_pqc_key_type.key_type.value = field_storage.fuse_pqc_key_type.key_type.value; + for(genvar i0=0; i0<4; i0++) begin + // Field: soc_ifc_reg.fuse_soc_manifest_svn[].svn + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_soc_manifest_svn[i0].svn.value; + load_next_c = '0; + if(decoded_reg_strb.fuse_soc_manifest_svn[i0] && decoded_req_is_wr && !(hwif_in.fuse_soc_manifest_svn[i0].svn.swwel)) begin // SW write + next_c = (field_storage.fuse_soc_manifest_svn[i0].svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + field_combo.fuse_soc_manifest_svn[i0].svn.next = next_c; + field_combo.fuse_soc_manifest_svn[i0].svn.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin + if(~hwif_in.cptra_pwrgood) begin + field_storage.fuse_soc_manifest_svn[i0].svn.value <= 32'h0; + end else if(field_combo.fuse_soc_manifest_svn[i0].svn.load_next) begin + field_storage.fuse_soc_manifest_svn[i0].svn.value <= field_combo.fuse_soc_manifest_svn[i0].svn.next; + end + end + assign hwif_out.fuse_soc_manifest_svn[i0].svn.value = field_storage.fuse_soc_manifest_svn[i0].svn.value; + end + // Field: soc_ifc_reg.fuse_soc_manifest_max_svn.svn + always_comb begin + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_soc_manifest_max_svn.svn.value; + load_next_c = '0; + if(decoded_reg_strb.fuse_soc_manifest_max_svn && decoded_req_is_wr && !(hwif_in.fuse_soc_manifest_max_svn.svn.swwel)) begin // SW write + next_c = (field_storage.fuse_soc_manifest_max_svn.svn.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]); + load_next_c = '1; + end + field_combo.fuse_soc_manifest_max_svn.svn.next = next_c; + field_combo.fuse_soc_manifest_max_svn.svn.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin + if(~hwif_in.cptra_pwrgood) begin + field_storage.fuse_soc_manifest_max_svn.svn.value <= 8'h0; + end else if(field_combo.fuse_soc_manifest_max_svn.svn.load_next) begin + field_storage.fuse_soc_manifest_max_svn.svn.value <= field_combo.fuse_soc_manifest_max_svn.svn.next; + end + end + assign hwif_out.fuse_soc_manifest_max_svn.svn.value = field_storage.fuse_soc_manifest_max_svn.svn.value; // Field: soc_ifc_reg.SS_CALIPTRA_BASE_ADDR_L.addr_l always_comb begin automatic logic [31:0] next_c; @@ -6892,7 +6998,7 @@ module soc_ifc_reg ( logic [31:0] readback_data; // Assign readback values to a flattened array - logic [218-1:0][31:0] readback_array; + logic [224-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value : '0; assign readback_array[0][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value : '0; assign readback_array[0][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value : '0; @@ -7006,9 +7112,9 @@ module soc_ifc_reg ( assign readback_array[89][0:0] = (decoded_reg_strb.CPTRA_OWNER_PK_HASH_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_OWNER_PK_HASH_LOCK.lock.value : '0; assign readback_array[89][31:1] = '0; for(genvar i0=0; i0<12; i0++) begin - assign readback_array[i0*1 + 90][31:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash[i0].hash.value : '0; + assign readback_array[i0*1 + 90][31:0] = (decoded_reg_strb.fuse_vendor_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_vendor_pk_hash[i0].hash.value : '0; end - assign readback_array[102][3:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash_mask && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash_mask.mask.value : '0; + assign readback_array[102][3:0] = (decoded_reg_strb.fuse_ecc_revocation && !decoded_req_is_wr) ? field_storage.fuse_ecc_revocation.ecc_revocation.value : '0; assign readback_array[102][31:4] = '0; assign readback_array[103][31:0] = (decoded_reg_strb.fuse_fmc_key_manifest_svn && !decoded_req_is_wr) ? field_storage.fuse_fmc_key_manifest_svn.svn.value : '0; for(genvar i0=0; i0<4; i0++) begin @@ -7030,162 +7136,169 @@ module soc_ifc_reg ( for(genvar i0=0; i0<4; i0++) begin assign readback_array[i0*1 + 140][31:0] = (decoded_reg_strb.fuse_manuf_dbg_unlock_token[i0] && !decoded_req_is_wr) ? field_storage.fuse_manuf_dbg_unlock_token[i0].token.value : '0; end - assign readback_array[144][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[145][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[146][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[147][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[148][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[149][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[150][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[151][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[152][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value : '0; - assign readback_array[153][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value : '0; - assign readback_array[154][31:0] = (decoded_reg_strb.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET && !decoded_req_is_wr) ? field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value : '0; - assign readback_array[155][31:0] = (decoded_reg_strb.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES && !decoded_req_is_wr) ? field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value : '0; - assign readback_array[156][0:0] = (decoded_reg_strb.SS_DEBUG_INTENT && !decoded_req_is_wr) ? field_storage.SS_DEBUG_INTENT.debug_intent.value : '0; - assign readback_array[156][31:1] = '0; + assign readback_array[144][1:0] = (decoded_reg_strb.fuse_pqc_key_type && !decoded_req_is_wr) ? field_storage.fuse_pqc_key_type.key_type.value : '0; + assign readback_array[144][31:2] = '0; + for(genvar i0=0; i0<4; i0++) begin + assign readback_array[i0*1 + 145][31:0] = (decoded_reg_strb.fuse_soc_manifest_svn[i0] && !decoded_req_is_wr) ? field_storage.fuse_soc_manifest_svn[i0].svn.value : '0; + end + assign readback_array[149][7:0] = (decoded_reg_strb.fuse_soc_manifest_max_svn && !decoded_req_is_wr) ? field_storage.fuse_soc_manifest_max_svn.svn.value : '0; + assign readback_array[149][31:8] = '0; + assign readback_array[150][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[151][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[152][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[153][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[154][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[155][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[156][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[157][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[158][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value : '0; + assign readback_array[159][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value : '0; + assign readback_array[160][31:0] = (decoded_reg_strb.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET && !decoded_req_is_wr) ? field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value : '0; + assign readback_array[161][31:0] = (decoded_reg_strb.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES && !decoded_req_is_wr) ? field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value : '0; + assign readback_array[162][0:0] = (decoded_reg_strb.SS_DEBUG_INTENT && !decoded_req_is_wr) ? field_storage.SS_DEBUG_INTENT.debug_intent.value : '0; + assign readback_array[162][31:1] = '0; for(genvar i0=0; i0<4; i0++) begin - assign readback_array[i0*1 + 157][31:0] = (decoded_reg_strb.SS_STRAP_GENERIC[i0] && !decoded_req_is_wr) ? field_storage.SS_STRAP_GENERIC[i0].data.value : '0; - end - assign readback_array[161][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value : '0; - assign readback_array[161][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value : '0; - assign readback_array[161][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value : '0; - assign readback_array[161][31:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.RSVD.next : '0; - assign readback_array[162][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value : '0; - assign readback_array[162][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value : '0; - assign readback_array[162][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value : '0; - assign readback_array[162][3:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value : '0; - assign readback_array[162][4:4] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value : '0; - assign readback_array[162][5:5] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value : '0; - assign readback_array[162][6:6] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value : '0; - assign readback_array[162][7:7] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value : '0; - assign readback_array[162][8:8] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value : '0; - assign readback_array[162][31:9] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.RSVD.next : '0; + assign readback_array[i0*1 + 163][31:0] = (decoded_reg_strb.SS_STRAP_GENERIC[i0] && !decoded_req_is_wr) ? field_storage.SS_STRAP_GENERIC[i0].data.value : '0; + end + assign readback_array[167][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value : '0; + assign readback_array[167][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value : '0; + assign readback_array[167][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value : '0; + assign readback_array[167][31:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.RSVD.next : '0; + assign readback_array[168][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value : '0; + assign readback_array[168][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value : '0; + assign readback_array[168][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value : '0; + assign readback_array[168][3:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value : '0; + assign readback_array[168][4:4] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value : '0; + assign readback_array[168][5:5] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value : '0; + assign readback_array[168][6:6] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value : '0; + assign readback_array[168][7:7] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value : '0; + assign readback_array[168][8:8] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value : '0; + assign readback_array[168][31:9] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.RSVD.next : '0; for(genvar i0=0; i0<2; i0++) begin - assign readback_array[i0*1 + 163][31:0] = (decoded_reg_strb.SS_SOC_DBG_UNLOCK_LEVEL[i0] && !decoded_req_is_wr) ? field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value : '0; + assign readback_array[i0*1 + 169][31:0] = (decoded_reg_strb.SS_SOC_DBG_UNLOCK_LEVEL[i0] && !decoded_req_is_wr) ? field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value : '0; end for(genvar i0=0; i0<4; i0++) begin - assign readback_array[i0*1 + 165][31:0] = (decoded_reg_strb.SS_GENERIC_FW_EXEC_CTRL[i0] && !decoded_req_is_wr) ? field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value : '0; - end - assign readback_array[169][0:0] = (decoded_reg_strb.internal_iccm_lock && !decoded_req_is_wr) ? field_storage.internal_iccm_lock.lock.value : '0; - assign readback_array[169][31:1] = '0; - assign readback_array[170][0:0] = (decoded_reg_strb.internal_fw_update_reset && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset.core_rst.value : '0; - assign readback_array[170][31:1] = '0; - assign readback_array[171][7:0] = (decoded_reg_strb.internal_fw_update_reset_wait_cycles && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value : '0; - assign readback_array[171][31:8] = '0; - assign readback_array[172][31:0] = (decoded_reg_strb.internal_nmi_vector && !decoded_req_is_wr) ? field_storage.internal_nmi_vector.vec.value : '0; - assign readback_array[173][0:0] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value : '0; - assign readback_array[173][1:1] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value : '0; - assign readback_array[173][2:2] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value : '0; - assign readback_array[173][3:3] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? 1'h0 : '0; - assign readback_array[173][31:4] = '0; - assign readback_array[174][0:0] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value : '0; - assign readback_array[174][1:1] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value : '0; - assign readback_array[174][2:2] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value : '0; - assign readback_array[174][31:3] = '0; - assign readback_array[175][31:0] = (decoded_reg_strb.internal_fw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_fatal_mask.mask.value : '0; - assign readback_array[176][31:0] = (decoded_reg_strb.internal_fw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_non_fatal_mask.mask.value : '0; - assign readback_array[177][31:0] = (decoded_reg_strb.internal_rv_mtime_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_l.count_l.value : '0; - assign readback_array[178][31:0] = (decoded_reg_strb.internal_rv_mtime_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_h.count_h.value : '0; - assign readback_array[179][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_l.compare_l.value : '0; - assign readback_array[180][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_h.compare_h.value : '0; - assign readback_array[181][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0; - assign readback_array[181][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0; - assign readback_array[181][31:2] = '0; - assign readback_array[182][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0; - assign readback_array[182][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value : '0; - assign readback_array[182][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value : '0; - assign readback_array[182][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value : '0; - assign readback_array[182][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value : '0; - assign readback_array[182][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value : '0; - assign readback_array[182][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value : '0; - assign readback_array[182][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value : '0; - assign readback_array[182][31:8] = '0; - assign readback_array[183][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value : '0; - assign readback_array[183][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value : '0; - assign readback_array[183][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value : '0; - assign readback_array[183][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value : '0; - assign readback_array[183][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value : '0; - assign readback_array[183][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value : '0; - assign readback_array[183][31:6] = '0; - assign readback_array[184][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0; - assign readback_array[184][31:1] = '0; - assign readback_array[185][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0; - assign readback_array[185][31:1] = '0; - assign readback_array[186][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0; - assign readback_array[186][1:1] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value : '0; - assign readback_array[186][2:2] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value : '0; - assign readback_array[186][3:3] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value : '0; - assign readback_array[186][4:4] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value : '0; - assign readback_array[186][5:5] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value : '0; - assign readback_array[186][6:6] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value : '0; - assign readback_array[186][7:7] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value : '0; - assign readback_array[186][31:8] = '0; - assign readback_array[187][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value : '0; - assign readback_array[187][1:1] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value : '0; - assign readback_array[187][2:2] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value : '0; - assign readback_array[187][3:3] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value : '0; - assign readback_array[187][4:4] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value : '0; - assign readback_array[187][5:5] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value : '0; - assign readback_array[187][31:6] = '0; - assign readback_array[188][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0; - assign readback_array[188][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value : '0; - assign readback_array[188][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value : '0; - assign readback_array[188][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value : '0; - assign readback_array[188][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value : '0; - assign readback_array[188][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value : '0; - assign readback_array[188][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value : '0; - assign readback_array[188][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value : '0; + assign readback_array[i0*1 + 171][31:0] = (decoded_reg_strb.SS_GENERIC_FW_EXEC_CTRL[i0] && !decoded_req_is_wr) ? field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value : '0; + end + assign readback_array[175][0:0] = (decoded_reg_strb.internal_iccm_lock && !decoded_req_is_wr) ? field_storage.internal_iccm_lock.lock.value : '0; + assign readback_array[175][31:1] = '0; + assign readback_array[176][0:0] = (decoded_reg_strb.internal_fw_update_reset && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset.core_rst.value : '0; + assign readback_array[176][31:1] = '0; + assign readback_array[177][7:0] = (decoded_reg_strb.internal_fw_update_reset_wait_cycles && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value : '0; + assign readback_array[177][31:8] = '0; + assign readback_array[178][31:0] = (decoded_reg_strb.internal_nmi_vector && !decoded_req_is_wr) ? field_storage.internal_nmi_vector.vec.value : '0; + assign readback_array[179][0:0] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value : '0; + assign readback_array[179][1:1] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value : '0; + assign readback_array[179][2:2] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value : '0; + assign readback_array[179][3:3] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? 1'h0 : '0; + assign readback_array[179][31:4] = '0; + assign readback_array[180][0:0] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value : '0; + assign readback_array[180][1:1] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value : '0; + assign readback_array[180][2:2] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value : '0; + assign readback_array[180][31:3] = '0; + assign readback_array[181][31:0] = (decoded_reg_strb.internal_fw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_fatal_mask.mask.value : '0; + assign readback_array[182][31:0] = (decoded_reg_strb.internal_fw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_non_fatal_mask.mask.value : '0; + assign readback_array[183][31:0] = (decoded_reg_strb.internal_rv_mtime_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_l.count_l.value : '0; + assign readback_array[184][31:0] = (decoded_reg_strb.internal_rv_mtime_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_h.count_h.value : '0; + assign readback_array[185][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_l.compare_l.value : '0; + assign readback_array[186][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_h.compare_h.value : '0; + assign readback_array[187][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0; + assign readback_array[187][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0; + assign readback_array[187][31:2] = '0; + assign readback_array[188][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0; + assign readback_array[188][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value : '0; + assign readback_array[188][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value : '0; + assign readback_array[188][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value : '0; + assign readback_array[188][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value : '0; + assign readback_array[188][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value : '0; + assign readback_array[188][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value : '0; + assign readback_array[188][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value : '0; assign readback_array[188][31:8] = '0; - assign readback_array[189][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value : '0; - assign readback_array[189][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value : '0; - assign readback_array[189][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value : '0; - assign readback_array[189][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value : '0; - assign readback_array[189][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value : '0; - assign readback_array[189][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value : '0; + assign readback_array[189][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value : '0; + assign readback_array[189][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value : '0; + assign readback_array[189][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value : '0; + assign readback_array[189][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value : '0; + assign readback_array[189][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value : '0; + assign readback_array[189][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value : '0; assign readback_array[189][31:6] = '0; - assign readback_array[190][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0; - assign readback_array[191][31:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value : '0; - assign readback_array[192][31:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value : '0; - assign readback_array[193][31:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value : '0; - assign readback_array[194][31:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value : '0; - assign readback_array[195][31:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value : '0; - assign readback_array[196][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value : '0; - assign readback_array[197][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value : '0; - assign readback_array[198][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value : '0; - assign readback_array[199][31:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value : '0; - assign readback_array[200][31:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value : '0; - assign readback_array[201][31:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value : '0; - assign readback_array[202][31:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value : '0; - assign readback_array[203][31:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value : '0; - assign readback_array[204][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0; - assign readback_array[204][31:1] = '0; - assign readback_array[205][0:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value : '0; - assign readback_array[205][31:1] = '0; - assign readback_array[206][0:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value : '0; - assign readback_array[206][31:1] = '0; - assign readback_array[207][0:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value : '0; - assign readback_array[207][31:1] = '0; - assign readback_array[208][0:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value : '0; - assign readback_array[208][31:1] = '0; - assign readback_array[209][0:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value : '0; - assign readback_array[209][31:1] = '0; - assign readback_array[210][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value : '0; + assign readback_array[190][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0; + assign readback_array[190][31:1] = '0; + assign readback_array[191][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0; + assign readback_array[191][31:1] = '0; + assign readback_array[192][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0; + assign readback_array[192][1:1] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value : '0; + assign readback_array[192][2:2] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value : '0; + assign readback_array[192][3:3] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value : '0; + assign readback_array[192][4:4] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value : '0; + assign readback_array[192][5:5] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value : '0; + assign readback_array[192][6:6] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value : '0; + assign readback_array[192][7:7] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value : '0; + assign readback_array[192][31:8] = '0; + assign readback_array[193][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value : '0; + assign readback_array[193][1:1] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value : '0; + assign readback_array[193][2:2] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value : '0; + assign readback_array[193][3:3] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value : '0; + assign readback_array[193][4:4] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value : '0; + assign readback_array[193][5:5] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value : '0; + assign readback_array[193][31:6] = '0; + assign readback_array[194][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0; + assign readback_array[194][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value : '0; + assign readback_array[194][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value : '0; + assign readback_array[194][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value : '0; + assign readback_array[194][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value : '0; + assign readback_array[194][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value : '0; + assign readback_array[194][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value : '0; + assign readback_array[194][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value : '0; + assign readback_array[194][31:8] = '0; + assign readback_array[195][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value : '0; + assign readback_array[195][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value : '0; + assign readback_array[195][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value : '0; + assign readback_array[195][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value : '0; + assign readback_array[195][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value : '0; + assign readback_array[195][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value : '0; + assign readback_array[195][31:6] = '0; + assign readback_array[196][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0; + assign readback_array[197][31:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value : '0; + assign readback_array[198][31:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value : '0; + assign readback_array[199][31:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value : '0; + assign readback_array[200][31:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value : '0; + assign readback_array[201][31:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value : '0; + assign readback_array[202][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value : '0; + assign readback_array[203][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value : '0; + assign readback_array[204][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value : '0; + assign readback_array[205][31:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value : '0; + assign readback_array[206][31:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value : '0; + assign readback_array[207][31:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value : '0; + assign readback_array[208][31:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value : '0; + assign readback_array[209][31:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value : '0; + assign readback_array[210][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0; assign readback_array[210][31:1] = '0; - assign readback_array[211][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value : '0; + assign readback_array[211][0:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value : '0; assign readback_array[211][31:1] = '0; - assign readback_array[212][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value : '0; + assign readback_array[212][0:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value : '0; assign readback_array[212][31:1] = '0; - assign readback_array[213][0:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value : '0; + assign readback_array[213][0:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value : '0; assign readback_array[213][31:1] = '0; - assign readback_array[214][0:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value : '0; + assign readback_array[214][0:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value : '0; assign readback_array[214][31:1] = '0; - assign readback_array[215][0:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value : '0; + assign readback_array[215][0:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value : '0; assign readback_array[215][31:1] = '0; - assign readback_array[216][0:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value : '0; + assign readback_array[216][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value : '0; assign readback_array[216][31:1] = '0; - assign readback_array[217][0:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value : '0; + assign readback_array[217][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value : '0; assign readback_array[217][31:1] = '0; + assign readback_array[218][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value : '0; + assign readback_array[218][31:1] = '0; + assign readback_array[219][0:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value : '0; + assign readback_array[219][31:1] = '0; + assign readback_array[220][0:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value : '0; + assign readback_array[220][31:1] = '0; + assign readback_array[221][0:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value : '0; + assign readback_array[221][31:1] = '0; + assign readback_array[222][0:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value : '0; + assign readback_array[222][31:1] = '0; + assign readback_array[223][0:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value : '0; + assign readback_array[223][31:1] = '0; // Reduce the array always_comb begin @@ -7193,7 +7306,7 @@ module soc_ifc_reg ( readback_done = decoded_req & ~decoded_req_is_wr; readback_err = '0; readback_data_var = '0; - for(int i=0; i<218; i++) readback_data_var |= readback_array[i]; + for(int i=0; i<224; i++) readback_data_var |= readback_array[i]; readback_data = readback_data_var; end diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh index b3b94bc89..f78fe1775 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh @@ -1073,8 +1073,8 @@ endgroup - /*----------------------- SOC_IFC_REG__FUSE_KEY_MANIFEST_PK_HASH COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__FUSE_VENDOR_PK_HASH COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__fuse_vendor_pk_hash_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -1085,7 +1085,7 @@ } endgroup - covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_fld_cg with function sample( + covergroup soc_ifc_reg__fuse_vendor_pk_hash_fld_cg with function sample( input bit [32-1:0] hash ); option.per_instance = 1; @@ -1099,8 +1099,8 @@ endgroup - /*----------------------- SOC_IFC_REG__FUSE_KEY_MANIFEST_PK_HASH_MASK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_mask_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__FUSE_ECC_REVOCATION COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__fuse_ecc_revocation_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -1111,11 +1111,11 @@ } endgroup - covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_mask_fld_cg with function sample( - input bit [32-1:0] mask + covergroup soc_ifc_reg__fuse_ecc_revocation_fld_cg with function sample( + input bit [4-1:0] ecc_revocation ); option.per_instance = 1; - mask_cp : coverpoint mask { + ecc_revocation_cp : coverpoint ecc_revocation { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -1329,6 +1329,66 @@ endgroup + /*----------------------- SOC_IFC_REG__FUSE_PQC_KEY_TYPE COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__fuse_pqc_key_type_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup soc_ifc_reg__fuse_pqc_key_type_fld_cg with function sample( + input bit [2-1:0] key_type + ); + option.per_instance = 1; + key_type_cp : coverpoint key_type; + + endgroup + + /*----------------------- SOC_IFC_REG__FUSE_SOC_MANIFEST_SVN COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__fuse_soc_manifest_svn_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup soc_ifc_reg__fuse_soc_manifest_svn_fld_cg with function sample( + input bit [32-1:0] svn + ); + option.per_instance = 1; + svn_cp : coverpoint svn; + + endgroup + + /*----------------------- SOC_IFC_REG__FUSE_SOC_MANIFEST_MAX_SVN COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__fuse_soc_manifest_max_svn_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup soc_ifc_reg__fuse_soc_manifest_max_svn_fld_cg with function sample( + input bit [8-1:0] svn + ); + option.per_instance = 1; + svn_cp : coverpoint svn; + + endgroup + /*----------------------- SOC_IFC_REG__SS_CALIPTRA_BASE_ADDR_L COVERGROUPS -----------------------*/ covergroup soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index 83256e4cd..f49dcb846 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -295,15 +295,15 @@ package soc_ifc_reg_pkg; typedef struct packed{ soc_ifc_reg__Fuse_w32__in_t hash; - } soc_ifc_reg__fuse_key_manifest_pk_hash__in_t; + } soc_ifc_reg__fuse_vendor_pk_hash__in_t; typedef struct packed{ logic swwel; } soc_ifc_reg__Fuse_w4__in_t; typedef struct packed{ - soc_ifc_reg__Fuse_w4__in_t mask; - } soc_ifc_reg__fuse_key_manifest_pk_hash_mask__in_t; + soc_ifc_reg__Fuse_w4__in_t ecc_revocation; + } soc_ifc_reg__fuse_ecc_revocation__in_t; typedef struct packed{ soc_ifc_reg__Fuse_w32__in_t svn; @@ -349,6 +349,26 @@ package soc_ifc_reg_pkg; soc_ifc_reg__Fuse_w32__in_t token; } soc_ifc_reg__fuse_manuf_dbg_unlock_token__in_t; + typedef struct packed{ + logic swwel; + } soc_ifc_reg__Fuse_w2__in_t; + + typedef struct packed{ + soc_ifc_reg__Fuse_w2__in_t key_type; + } soc_ifc_reg__fuse_pqc_key_type__in_t; + + typedef struct packed{ + soc_ifc_reg__Fuse_w32__in_t svn; + } soc_ifc_reg__fuse_soc_manifest_svn__in_t; + + typedef struct packed{ + logic swwel; + } soc_ifc_reg__Fuse_w8__in_t; + + typedef struct packed{ + soc_ifc_reg__Fuse_w8__in_t svn; + } soc_ifc_reg__fuse_soc_manifest_max_svn__in_t; + typedef struct packed{ logic [31:0] next; logic we; @@ -675,8 +695,8 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__in_t CPTRA_OWNER_PK_HASH_LOCK; soc_ifc_reg__fuse_uds_seed__in_t [16-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__in_t [8-1:0]fuse_field_entropy; - soc_ifc_reg__fuse_key_manifest_pk_hash__in_t [12-1:0]fuse_key_manifest_pk_hash; - soc_ifc_reg__fuse_key_manifest_pk_hash_mask__in_t fuse_key_manifest_pk_hash_mask; + soc_ifc_reg__fuse_vendor_pk_hash__in_t [12-1:0]fuse_vendor_pk_hash; + soc_ifc_reg__fuse_ecc_revocation__in_t fuse_ecc_revocation; soc_ifc_reg__fuse_fmc_key_manifest_svn__in_t fuse_fmc_key_manifest_svn; soc_ifc_reg__fuse_runtime_svn__in_t [4-1:0]fuse_runtime_svn; soc_ifc_reg__fuse_anti_rollback_disable__in_t fuse_anti_rollback_disable; @@ -686,6 +706,9 @@ package soc_ifc_reg_pkg; soc_ifc_reg__fuse_mldsa_revocation__in_t fuse_mldsa_revocation; soc_ifc_reg__fuse_soc_stepping_id__in_t fuse_soc_stepping_id; soc_ifc_reg__fuse_manuf_dbg_unlock_token__in_t [4-1:0]fuse_manuf_dbg_unlock_token; + soc_ifc_reg__fuse_pqc_key_type__in_t fuse_pqc_key_type; + soc_ifc_reg__fuse_soc_manifest_svn__in_t [4-1:0]fuse_soc_manifest_svn; + soc_ifc_reg__fuse_soc_manifest_max_svn__in_t fuse_soc_manifest_max_svn; soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L__in_t SS_CALIPTRA_BASE_ADDR_L; soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H__in_t SS_CALIPTRA_BASE_ADDR_H; soc_ifc_reg__SS_MCI_BASE_ADDR_L__in_t SS_MCI_BASE_ADDR_L; @@ -1040,15 +1063,15 @@ package soc_ifc_reg_pkg; typedef struct packed{ soc_ifc_reg__Fuse_w32__out_t hash; - } soc_ifc_reg__fuse_key_manifest_pk_hash__out_t; + } soc_ifc_reg__fuse_vendor_pk_hash__out_t; typedef struct packed{ logic [3:0] value; } soc_ifc_reg__Fuse_w4__out_t; typedef struct packed{ - soc_ifc_reg__Fuse_w4__out_t mask; - } soc_ifc_reg__fuse_key_manifest_pk_hash_mask__out_t; + soc_ifc_reg__Fuse_w4__out_t ecc_revocation; + } soc_ifc_reg__fuse_ecc_revocation__out_t; typedef struct packed{ soc_ifc_reg__Fuse_w32__out_t svn; @@ -1094,6 +1117,26 @@ package soc_ifc_reg_pkg; soc_ifc_reg__Fuse_w32__out_t token; } soc_ifc_reg__fuse_manuf_dbg_unlock_token__out_t; + typedef struct packed{ + logic [1:0] value; + } soc_ifc_reg__Fuse_w2__out_t; + + typedef struct packed{ + soc_ifc_reg__Fuse_w2__out_t key_type; + } soc_ifc_reg__fuse_pqc_key_type__out_t; + + typedef struct packed{ + soc_ifc_reg__Fuse_w32__out_t svn; + } soc_ifc_reg__fuse_soc_manifest_svn__out_t; + + typedef struct packed{ + logic [7:0] value; + } soc_ifc_reg__Fuse_w8__out_t; + + typedef struct packed{ + soc_ifc_reg__Fuse_w8__out_t svn; + } soc_ifc_reg__fuse_soc_manifest_max_svn__out_t; + typedef struct packed{ logic [31:0] value; } soc_ifc_reg__strap_w32__out_t; @@ -1405,8 +1448,8 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__out_t CPTRA_OWNER_PK_HASH_LOCK; soc_ifc_reg__fuse_uds_seed__out_t [16-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__out_t [8-1:0]fuse_field_entropy; - soc_ifc_reg__fuse_key_manifest_pk_hash__out_t [12-1:0]fuse_key_manifest_pk_hash; - soc_ifc_reg__fuse_key_manifest_pk_hash_mask__out_t fuse_key_manifest_pk_hash_mask; + soc_ifc_reg__fuse_vendor_pk_hash__out_t [12-1:0]fuse_vendor_pk_hash; + soc_ifc_reg__fuse_ecc_revocation__out_t fuse_ecc_revocation; soc_ifc_reg__fuse_fmc_key_manifest_svn__out_t fuse_fmc_key_manifest_svn; soc_ifc_reg__fuse_runtime_svn__out_t [4-1:0]fuse_runtime_svn; soc_ifc_reg__fuse_anti_rollback_disable__out_t fuse_anti_rollback_disable; @@ -1416,6 +1459,9 @@ package soc_ifc_reg_pkg; soc_ifc_reg__fuse_mldsa_revocation__out_t fuse_mldsa_revocation; soc_ifc_reg__fuse_soc_stepping_id__out_t fuse_soc_stepping_id; soc_ifc_reg__fuse_manuf_dbg_unlock_token__out_t [4-1:0]fuse_manuf_dbg_unlock_token; + soc_ifc_reg__fuse_pqc_key_type__out_t fuse_pqc_key_type; + soc_ifc_reg__fuse_soc_manifest_svn__out_t [4-1:0]fuse_soc_manifest_svn; + soc_ifc_reg__fuse_soc_manifest_max_svn__out_t fuse_soc_manifest_max_svn; soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L__out_t SS_CALIPTRA_BASE_ADDR_L; soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H__out_t SS_CALIPTRA_BASE_ADDR_H; soc_ifc_reg__SS_MCI_BASE_ADDR_L__out_t SS_MCI_BASE_ADDR_L; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh index f7c178b26..7c222ac5e 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh @@ -1265,8 +1265,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__FUSE_KEY_MANIFEST_PK_HASH SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__fuse_key_manifest_pk_hash::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__FUSE_VENDOR_PK_HASH SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__fuse_vendor_pk_hash::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -1281,7 +1281,7 @@ end endfunction - function void soc_ifc_reg__fuse_key_manifest_pk_hash::sample_values(); + function void soc_ifc_reg__fuse_vendor_pk_hash::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(hash.get_mirrored_value() >> bt); end @@ -1290,8 +1290,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__FUSE_KEY_MANIFEST_PK_HASH_MASK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__fuse_key_manifest_pk_hash_mask::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__FUSE_ECC_REVOCATION SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__fuse_ecc_revocation::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -1299,19 +1299,19 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(data[0 + bt]); + foreach(ecc_revocation_bit_cg[bt]) this.ecc_revocation_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*mask*/ ); + this.fld_cg.sample( data[3:0]/*ecc_revocation*/ ); end endfunction - function void soc_ifc_reg__fuse_key_manifest_pk_hash_mask::sample_values(); + function void soc_ifc_reg__fuse_ecc_revocation::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(mask.get_mirrored_value() >> bt); + foreach(ecc_revocation_bit_cg[bt]) this.ecc_revocation_bit_cg[bt].sample(ecc_revocation.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( mask.get_mirrored_value() ); + this.fld_cg.sample( ecc_revocation.get_mirrored_value() ); end endfunction @@ -1540,6 +1540,81 @@ end endfunction + /*----------------------- SOC_IFC_REG__FUSE_PQC_KEY_TYPE SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__fuse_pqc_key_type::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(key_type_bit_cg[bt]) this.key_type_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[1:0]/*key_type*/ ); + end + endfunction + + function void soc_ifc_reg__fuse_pqc_key_type::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(key_type_bit_cg[bt]) this.key_type_bit_cg[bt].sample(key_type.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( key_type.get_mirrored_value() ); + end + endfunction + + /*----------------------- SOC_IFC_REG__FUSE_SOC_MANIFEST_SVN SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__fuse_soc_manifest_svn::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(svn_bit_cg[bt]) this.svn_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*svn*/ ); + end + endfunction + + function void soc_ifc_reg__fuse_soc_manifest_svn::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(svn_bit_cg[bt]) this.svn_bit_cg[bt].sample(svn.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( svn.get_mirrored_value() ); + end + endfunction + + /*----------------------- SOC_IFC_REG__FUSE_SOC_MANIFEST_MAX_SVN SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__fuse_soc_manifest_max_svn::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(svn_bit_cg[bt]) this.svn_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[7:0]/*svn*/ ); + end + endfunction + + function void soc_ifc_reg__fuse_soc_manifest_max_svn::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(svn_bit_cg[bt]) this.svn_bit_cg[bt].sample(svn.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( svn.get_mirrored_value() ); + end + endfunction + /*----------------------- SOC_IFC_REG__SS_CALIPTRA_BASE_ADDR_L SAMPLE FUNCTIONS -----------------------*/ function void soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv index 7af7479f9..6d1099d6a 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv @@ -1569,17 +1569,17 @@ package soc_ifc_reg_uvm; endfunction : build endclass : soc_ifc_reg__fuse_field_entropy - // Reg - soc_ifc_reg::fuse_key_manifest_pk_hash - class soc_ifc_reg__fuse_key_manifest_pk_hash extends uvm_reg; + // Reg - soc_ifc_reg::fuse_vendor_pk_hash + class soc_ifc_reg__fuse_vendor_pk_hash extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__fuse_key_manifest_pk_hash_bit_cg hash_bit_cg[32]; - soc_ifc_reg__fuse_key_manifest_pk_hash_fld_cg fld_cg; + soc_ifc_reg__fuse_vendor_pk_hash_bit_cg hash_bit_cg[32]; + soc_ifc_reg__fuse_vendor_pk_hash_fld_cg fld_cg; rand uvm_reg_field hash; - function new(string name = "soc_ifc_reg__fuse_key_manifest_pk_hash"); + function new(string name = "soc_ifc_reg__fuse_vendor_pk_hash"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -1597,19 +1597,19 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__fuse_key_manifest_pk_hash + endclass : soc_ifc_reg__fuse_vendor_pk_hash - // Reg - soc_ifc_reg::fuse_key_manifest_pk_hash_mask - class soc_ifc_reg__fuse_key_manifest_pk_hash_mask extends uvm_reg; + // Reg - soc_ifc_reg::fuse_ecc_revocation + class soc_ifc_reg__fuse_ecc_revocation extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__fuse_key_manifest_pk_hash_mask_bit_cg mask_bit_cg[4]; - soc_ifc_reg__fuse_key_manifest_pk_hash_mask_fld_cg fld_cg; - rand uvm_reg_field mask; + soc_ifc_reg__fuse_ecc_revocation_bit_cg ecc_revocation_bit_cg[4]; + soc_ifc_reg__fuse_ecc_revocation_fld_cg fld_cg; + rand uvm_reg_field ecc_revocation; - function new(string name = "soc_ifc_reg__fuse_key_manifest_pk_hash_mask"); + function new(string name = "soc_ifc_reg__fuse_ecc_revocation"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -1619,15 +1619,15 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.mask = new("mask"); - this.mask.configure(this, 4, 0, "RW", 0, 'h0, 1, 1, 0); + this.ecc_revocation = new("ecc_revocation"); + this.ecc_revocation.configure(this, 4, 0, "RW", 0, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(mask_bit_cg[bt]) mask_bit_cg[bt] = new(); + foreach(ecc_revocation_bit_cg[bt]) ecc_revocation_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__fuse_key_manifest_pk_hash_mask + endclass : soc_ifc_reg__fuse_ecc_revocation // Reg - soc_ifc_reg::fuse_fmc_key_manifest_svn class soc_ifc_reg__fuse_fmc_key_manifest_svn extends uvm_reg; @@ -1899,6 +1899,96 @@ package soc_ifc_reg_uvm; endfunction : build endclass : soc_ifc_reg__fuse_manuf_dbg_unlock_token + // Reg - soc_ifc_reg::fuse_pqc_key_type + class soc_ifc_reg__fuse_pqc_key_type extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + soc_ifc_reg__fuse_pqc_key_type_bit_cg key_type_bit_cg[2]; + soc_ifc_reg__fuse_pqc_key_type_fld_cg fld_cg; + rand uvm_reg_field key_type; + + function new(string name = "soc_ifc_reg__fuse_pqc_key_type"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.key_type = new("key_type"); + this.key_type.configure(this, 2, 0, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(key_type_bit_cg[bt]) key_type_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : soc_ifc_reg__fuse_pqc_key_type + + // Reg - soc_ifc_reg::fuse_soc_manifest_svn + class soc_ifc_reg__fuse_soc_manifest_svn extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + soc_ifc_reg__fuse_soc_manifest_svn_bit_cg svn_bit_cg[32]; + soc_ifc_reg__fuse_soc_manifest_svn_fld_cg fld_cg; + rand uvm_reg_field svn; + + function new(string name = "soc_ifc_reg__fuse_soc_manifest_svn"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.svn = new("svn"); + this.svn.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(svn_bit_cg[bt]) svn_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : soc_ifc_reg__fuse_soc_manifest_svn + + // Reg - soc_ifc_reg::fuse_soc_manifest_max_svn + class soc_ifc_reg__fuse_soc_manifest_max_svn extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + soc_ifc_reg__fuse_soc_manifest_max_svn_bit_cg svn_bit_cg[8]; + soc_ifc_reg__fuse_soc_manifest_max_svn_fld_cg fld_cg; + rand uvm_reg_field svn; + + function new(string name = "soc_ifc_reg__fuse_soc_manifest_max_svn"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.svn = new("svn"); + this.svn.configure(this, 8, 0, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(svn_bit_cg[bt]) svn_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : soc_ifc_reg__fuse_soc_manifest_max_svn + // Reg - soc_ifc_reg::SS_CALIPTRA_BASE_ADDR_L class soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L extends uvm_reg; protected uvm_reg_data_t m_current; @@ -4493,8 +4583,8 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK CPTRA_OWNER_PK_HASH_LOCK; rand soc_ifc_reg__fuse_uds_seed fuse_uds_seed[16]; rand soc_ifc_reg__fuse_field_entropy fuse_field_entropy[8]; - rand soc_ifc_reg__fuse_key_manifest_pk_hash fuse_key_manifest_pk_hash[12]; - rand soc_ifc_reg__fuse_key_manifest_pk_hash_mask fuse_key_manifest_pk_hash_mask; + rand soc_ifc_reg__fuse_vendor_pk_hash fuse_vendor_pk_hash[12]; + rand soc_ifc_reg__fuse_ecc_revocation fuse_ecc_revocation; rand soc_ifc_reg__fuse_fmc_key_manifest_svn fuse_fmc_key_manifest_svn; rand soc_ifc_reg__fuse_runtime_svn fuse_runtime_svn[4]; rand soc_ifc_reg__fuse_anti_rollback_disable fuse_anti_rollback_disable; @@ -4504,6 +4594,9 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__fuse_mldsa_revocation fuse_mldsa_revocation; rand soc_ifc_reg__fuse_soc_stepping_id fuse_soc_stepping_id; rand soc_ifc_reg__fuse_manuf_dbg_unlock_token fuse_manuf_dbg_unlock_token[4]; + rand soc_ifc_reg__fuse_pqc_key_type fuse_pqc_key_type; + rand soc_ifc_reg__fuse_soc_manifest_svn fuse_soc_manifest_svn[4]; + rand soc_ifc_reg__fuse_soc_manifest_max_svn fuse_soc_manifest_max_svn; rand soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L SS_CALIPTRA_BASE_ADDR_L; rand soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H SS_CALIPTRA_BASE_ADDR_H; rand soc_ifc_reg__SS_MCI_BASE_ADDR_L SS_MCI_BASE_ADDR_L; @@ -4811,18 +4904,18 @@ package soc_ifc_reg_uvm; this.fuse_field_entropy[i0].build(); this.default_map.add_reg(this.fuse_field_entropy[i0], 'h240 + i0*'h4); end - foreach(this.fuse_key_manifest_pk_hash[i0]) begin - this.fuse_key_manifest_pk_hash[i0] = new($sformatf("fuse_key_manifest_pk_hash[%0d]", i0)); - this.fuse_key_manifest_pk_hash[i0].configure(this); + foreach(this.fuse_vendor_pk_hash[i0]) begin + this.fuse_vendor_pk_hash[i0] = new($sformatf("fuse_vendor_pk_hash[%0d]", i0)); + this.fuse_vendor_pk_hash[i0].configure(this); - this.fuse_key_manifest_pk_hash[i0].build(); - this.default_map.add_reg(this.fuse_key_manifest_pk_hash[i0], 'h260 + i0*'h4); + this.fuse_vendor_pk_hash[i0].build(); + this.default_map.add_reg(this.fuse_vendor_pk_hash[i0], 'h260 + i0*'h4); end - this.fuse_key_manifest_pk_hash_mask = new("fuse_key_manifest_pk_hash_mask"); - this.fuse_key_manifest_pk_hash_mask.configure(this); + this.fuse_ecc_revocation = new("fuse_ecc_revocation"); + this.fuse_ecc_revocation.configure(this); - this.fuse_key_manifest_pk_hash_mask.build(); - this.default_map.add_reg(this.fuse_key_manifest_pk_hash_mask, 'h290); + this.fuse_ecc_revocation.build(); + this.default_map.add_reg(this.fuse_ecc_revocation, 'h290); this.fuse_fmc_key_manifest_svn = new("fuse_fmc_key_manifest_svn"); this.fuse_fmc_key_manifest_svn.configure(this); @@ -4876,6 +4969,23 @@ package soc_ifc_reg_uvm; this.fuse_manuf_dbg_unlock_token[i0].build(); this.default_map.add_reg(this.fuse_manuf_dbg_unlock_token[i0], 'h34c + i0*'h4); end + this.fuse_pqc_key_type = new("fuse_pqc_key_type"); + this.fuse_pqc_key_type.configure(this); + + this.fuse_pqc_key_type.build(); + this.default_map.add_reg(this.fuse_pqc_key_type, 'h35c); + foreach(this.fuse_soc_manifest_svn[i0]) begin + this.fuse_soc_manifest_svn[i0] = new($sformatf("fuse_soc_manifest_svn[%0d]", i0)); + this.fuse_soc_manifest_svn[i0].configure(this); + + this.fuse_soc_manifest_svn[i0].build(); + this.default_map.add_reg(this.fuse_soc_manifest_svn[i0], 'h360 + i0*'h4); + end + this.fuse_soc_manifest_max_svn = new("fuse_soc_manifest_max_svn"); + this.fuse_soc_manifest_max_svn.configure(this); + + this.fuse_soc_manifest_max_svn.build(); + this.default_map.add_reg(this.fuse_soc_manifest_max_svn, 'h370); this.SS_CALIPTRA_BASE_ADDR_L = new("SS_CALIPTRA_BASE_ADDR_L"); this.SS_CALIPTRA_BASE_ADDR_L.configure(this); diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 15a314aed..ac2ab17a8 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -647,7 +647,7 @@ always_comb begin soc_ifc_reg_hwif_in.fuse_uds_seed[i].seed.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; end for (int i=0; i<12; i++) begin - soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash[i].hash.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; + soc_ifc_reg_hwif_in.fuse_vendor_pk_hash[i].hash.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; end for (int i=0; i < `CLP_OBF_FE_DWORDS; i++) begin @@ -669,14 +669,20 @@ always_comb begin for (int i=0; i<4; i++) begin soc_ifc_reg_hwif_in.fuse_manuf_dbg_unlock_token[i].token.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; end + + for (int i=0; i<4; i++) begin + soc_ifc_reg_hwif_in.fuse_soc_manifest_svn[i].svn.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; + end end -always_comb soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; +always_comb soc_ifc_reg_hwif_in.fuse_ecc_revocation.ecc_revocation.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; always_comb soc_ifc_reg_hwif_in.fuse_fmc_key_manifest_svn.svn.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; always_comb soc_ifc_reg_hwif_in.fuse_anti_rollback_disable.dis.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; always_comb soc_ifc_reg_hwif_in.fuse_lms_revocation.lms_revocation.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; always_comb soc_ifc_reg_hwif_in.fuse_mldsa_revocation.mldsa_revocation.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; always_comb soc_ifc_reg_hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; +always_comb soc_ifc_reg_hwif_in.fuse_pqc_key_type.key_type.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; +always_comb soc_ifc_reg_hwif_in.fuse_soc_manifest_max_svn.svn.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; // Lockable registers always_comb begin diff --git a/src/soc_ifc/tb/fuse_reg_pauser_test.svh b/src/soc_ifc/tb/fuse_reg_pauser_test.svh index ffc535c34..ff80ef46c 100644 --- a/src/soc_ifc/tb/fuse_reg_pauser_test.svh +++ b/src/soc_ifc/tb/fuse_reg_pauser_test.svh @@ -19,8 +19,8 @@ // Declarations for internal signal probing logic [31:0] fuse_uds_seed [0:11]; logic [31:0] fuse_field_entropy [0:7]; -logic [31:0] fuse_key_manifest_pk_hash [0:11]; -logic [3:0] fuse_key_manifest_pk_hash_mask; +logic [31:0] fuse_vendor_pk_hash [0:11]; +logic [3:0] fuse_ecc_revocation; logic [31:0] fuse_fmc_key_manifest_svn; logic [31:0] fuse_runtime_svn [0:3]; logic fuse_anti_rollback_disable; @@ -32,8 +32,8 @@ logic [31:0] fuse_mldsa_revocation; `FORLOOP_COMB( 12 ) fuse_uds_seed[j] = `REG_HIER_PFX.fuse_uds_seed[j].seed.value; `FORLOOP_COMB( 8 ) fuse_field_entropy[j] = `REG_HIER_PFX.fuse_field_entropy[j].seed.value; -`FORLOOP_COMB( 12 ) fuse_key_manifest_pk_hash[j] = `REG_HIER_PFX.fuse_key_manifest_pk_hash[j].hash.value; - always_comb fuse_key_manifest_pk_hash_mask = `REG_HIER_PFX.fuse_key_manifest_pk_hash_mask.mask.value; +`FORLOOP_COMB( 12 ) fuse_vendor_pk_hash[j] = `REG_HIER_PFX.fuse_vendor_pk_hash[j].hash.value; + always_comb fuse_ecc_revocation = `REG_HIER_PFX.fuse_ecc_revocation.mask.value; always_comb fuse_fmc_key_manifest_svn = `REG_HIER_PFX.fuse_fmc_key_manifest_svn.svn.value; `FORLOOP_COMB( 4 ) fuse_runtime_svn[j] = `REG_HIER_PFX.fuse_runtime_svn[j].svn.value; always_comb fuse_anti_rollback_disable = `REG_HIER_PFX.fuse_anti_rollback_disable.dis.value; @@ -269,12 +269,12 @@ function dword_t get_fuse_regval(string rname); string pfx = "unknown"; automatic int j; - strq_t prefixes = {"FUSE_UDS_SEED", "FUSE_FIELD_ENTROPY", "FUSE_KEY_MANIFEST_PK_HASH", + strq_t prefixes = {"FUSE_UDS_SEED", "FUSE_FIELD_ENTROPY", "FUSE_VENDOR_PK_HASH", "FUSE_RUNTIME_SVN", "FUSE_IDEVID_CERT_ATTR", "FUSE_IDEVID_MANUF_HSM_ID"}; begin case (rname) - "FUSE_KEY_MANIFEST_PK_HASH_MASK" : regval = fuse_key_manifest_pk_hash_mask; + "FUSE_ECC_REVOCATION" : regval = fuse_ecc_revocation; "FUSE_FMC_KEY_MANIFEST_SVN" : regval = fuse_fmc_key_manifest_svn; "FUSE_ANTI_ROLLBACK_DISABLE" : regval = fuse_anti_rollback_disable; "FUSE_LMS_REVOCATION" : regval = fuse_lms_revocation; @@ -296,7 +296,7 @@ function dword_t get_fuse_regval(string rname); // $display ("prefix = %s, j = %d", pfx, j); regval = (pfx == "FUSE_UDS_SEED" ) ? fuse_uds_seed[j]: (pfx == "FUSE_FIELD_ENTROPY" ) ? fuse_field_entropy[j] : - (pfx == "FUSE_KEY_MANIFEST_PK_HASH") ? fuse_key_manifest_pk_hash[j] : + (pfx == "FUSE_VENDOR_PK_HASH" ) ? fuse_vendor_pk_hash[j] : (pfx == "FUSE_RUNTIME_SVN" ) ? fuse_runtime_svn[j] : (pfx == "FUSE_IDEVID_CERT_ATTR" ) ? fuse_idevid_cert_attr[j] : (pfx == "FUSE_IDEVID_MANUF_HSM_ID" ) ? fuse_idevid_manuf_hsm_id[j] : 'x; diff --git a/tools/scripts/gen_soc_ifc_covergroups.py b/tools/scripts/gen_soc_ifc_covergroups.py index abd4bc45d..4021a79a7 100644 --- a/tools/scripts/gen_soc_ifc_covergroups.py +++ b/tools/scripts/gen_soc_ifc_covergroups.py @@ -70,8 +70,8 @@ CPTRA_OWNER_PK_HASH_LOCK fuse_uds_seed 16 fuse_field_entropy 8 - fuse_key_manifest_pk_hash 12 - fuse_key_manifest_pk_hash_mask 8 + fuse_vendor_pk_hash 12 + fuse_ecc_revocation fuse_fmc_key_manifest_svn fuse_runtime_svn 4 fuse_anti_rollback_disable @@ -81,6 +81,9 @@ fuse_mldsa_revocation fuse_soc_stepping_id fuse_manuf_dbg_unlock_token 4 + fuse_pqc_key_type + fuse_soc_manifest_svn 4 + fuse_soc_manifest_max_svn SS_CALIPTRA_BASE_ADDR_L SS_CALIPTRA_BASE_ADDR_H SS_MCI_BASE_ADDR_L From 9d44365f680dcf9112eddcb9b9d817a933b9e917 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 16 Jan 2025 23:37:59 -0800 Subject: [PATCH 5/9] Split global/relative reg macros into separate header files when generating RDL --- src/ecc/tb/ecc_top_tb.sv | 1 + src/hmac/tb/hmac_ctrl_tb.sv | 1 + src/integration/config/compile.yml | 3 +- src/integration/rtl/caliptra_reg_defines.svh | 4310 ---------------- .../rtl/caliptra_reg_field_defines.svh | 4331 +++++++++++++++++ src/integration/tb/caliptra_top_tb.sv | 1 + .../tb/caliptra_top_tb_services.sv | 1 + src/integration/tb/caliptra_top_tb_soc_bfm.sv | 1 + src/sha256/tb/sha256_random_test.sv | 1 + src/sha512/tb/sha512_ctrl_32bit_tb.sv | 1 + src/soc_ifc/rtl/caliptra_top_reg_defines.svh | 377 -- .../rtl/caliptra_top_reg_field_defines.svh | 398 ++ src/soc_ifc/rtl/soc_ifc_pkg.sv | 1 + src/soc_ifc/rtl/soc_ifc_top.sv | 1 + src/soc_ifc/tb/soc_ifc_tb_pkg.sv | 1 + tools/scripts/reg_doc_gen.py | 38 +- 16 files changed, 4767 insertions(+), 4700 deletions(-) create mode 100644 src/integration/rtl/caliptra_reg_field_defines.svh create mode 100644 src/soc_ifc/rtl/caliptra_top_reg_field_defines.svh diff --git a/src/ecc/tb/ecc_top_tb.sv b/src/ecc/tb/ecc_top_tb.sv index 54ba90fdf..c6e960889 100644 --- a/src/ecc/tb/ecc_top_tb.sv +++ b/src/ecc/tb/ecc_top_tb.sv @@ -23,6 +23,7 @@ `default_nettype none `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" module ecc_top_tb import kv_defines_pkg::*; diff --git a/src/hmac/tb/hmac_ctrl_tb.sv b/src/hmac/tb/hmac_ctrl_tb.sv index 7b41839bc..f2e4934a6 100644 --- a/src/hmac/tb/hmac_ctrl_tb.sv +++ b/src/hmac/tb/hmac_ctrl_tb.sv @@ -23,6 +23,7 @@ //====================================================================== `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" module hmac_ctrl_tb(); diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml index 859067193..8a249d664 100644 --- a/src/integration/config/compile.yml +++ b/src/integration/config/compile.yml @@ -7,11 +7,12 @@ targets: files: - $COMPILE_ROOT/rtl/config_defines.svh - $COMPILE_ROOT/rtl/caliptra_reg_defines.svh + - $COMPILE_ROOT/rtl/caliptra_reg_field_defines.svh rtl: directories: [$COMPILE_ROOT/rtl] files: - $COMPILE_ROOT/rtl/config_defines.svh - - $COMPILE_ROOT/rtl/caliptra_reg_defines.svh + - $COMPILE_ROOT/rtl/caliptra_reg_field_defines.svh --- provides: [caliptra_top] schema_version: 2.4.0 diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index 293318681..8166c3050 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -19,4673 +19,1732 @@ `define CLP_BASE_ADDR (32'h0) `define CLP_DOE_REG_BASE_ADDR (32'h10000000) `define CLP_DOE_REG_DOE_IV_0 (32'h10000000) -`define DOE_REG_DOE_IV_0 (32'h0) `define CLP_DOE_REG_DOE_IV_1 (32'h10000004) -`define DOE_REG_DOE_IV_1 (32'h4) `define CLP_DOE_REG_DOE_IV_2 (32'h10000008) -`define DOE_REG_DOE_IV_2 (32'h8) `define CLP_DOE_REG_DOE_IV_3 (32'h1000000c) -`define DOE_REG_DOE_IV_3 (32'hc) `define CLP_DOE_REG_DOE_CTRL (32'h10000010) -`define DOE_REG_DOE_CTRL (32'h10) -`define DOE_REG_DOE_CTRL_CMD_LOW (0) -`define DOE_REG_DOE_CTRL_CMD_MASK (32'h3) -`define DOE_REG_DOE_CTRL_DEST_LOW (2) -`define DOE_REG_DOE_CTRL_DEST_MASK (32'h7c) `define CLP_DOE_REG_DOE_STATUS (32'h10000014) -`define DOE_REG_DOE_STATUS (32'h14) -`define DOE_REG_DOE_STATUS_READY_LOW (0) -`define DOE_REG_DOE_STATUS_READY_MASK (32'h1) -`define DOE_REG_DOE_STATUS_VALID_LOW (1) -`define DOE_REG_DOE_STATUS_VALID_MASK (32'h2) -`define DOE_REG_DOE_STATUS_UDS_FLOW_DONE_LOW (2) -`define DOE_REG_DOE_STATUS_UDS_FLOW_DONE_MASK (32'h4) -`define DOE_REG_DOE_STATUS_FE_FLOW_DONE_LOW (3) -`define DOE_REG_DOE_STATUS_FE_FLOW_DONE_MASK (32'h8) -`define DOE_REG_DOE_STATUS_DEOBF_SECRETS_CLEARED_LOW (4) -`define DOE_REG_DOE_STATUS_DEOBF_SECRETS_CLEARED_MASK (32'h10) `define CLP_DOE_REG_INTR_BLOCK_RF_START (32'h10000800) `define CLP_DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h10000800) -`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h10000804) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) `define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h10000808) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h1000080c) -`define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h10000810) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h10000814) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) `define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h10000818) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h1000081c) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) -`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) `define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h10000820) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h10000900) -`define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h10000904) -`define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h10000908) -`define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h1000090c) -`define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) `define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h10000980) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'h10000a00) -`define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) -`define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'h10000a04) -`define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) -`define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'h10000a08) -`define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) -`define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'h10000a0c) -`define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) -`define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h10000a10) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_ECC_REG_BASE_ADDR (32'h10008000) `define CLP_ECC_REG_ECC_NAME_0 (32'h10008000) -`define ECC_REG_ECC_NAME_0 (32'h0) `define CLP_ECC_REG_ECC_NAME_1 (32'h10008004) -`define ECC_REG_ECC_NAME_1 (32'h4) `define CLP_ECC_REG_ECC_VERSION_0 (32'h10008008) -`define ECC_REG_ECC_VERSION_0 (32'h8) `define CLP_ECC_REG_ECC_VERSION_1 (32'h1000800c) -`define ECC_REG_ECC_VERSION_1 (32'hc) `define CLP_ECC_REG_ECC_CTRL (32'h10008010) -`define ECC_REG_ECC_CTRL (32'h10) -`define ECC_REG_ECC_CTRL_CTRL_LOW (0) -`define ECC_REG_ECC_CTRL_CTRL_MASK (32'h3) -`define ECC_REG_ECC_CTRL_ZEROIZE_LOW (2) -`define ECC_REG_ECC_CTRL_ZEROIZE_MASK (32'h4) -`define ECC_REG_ECC_CTRL_PCR_SIGN_LOW (3) -`define ECC_REG_ECC_CTRL_PCR_SIGN_MASK (32'h8) -`define ECC_REG_ECC_CTRL_DH_SHAREDKEY_LOW (4) -`define ECC_REG_ECC_CTRL_DH_SHAREDKEY_MASK (32'h10) `define CLP_ECC_REG_ECC_STATUS (32'h10008018) -`define ECC_REG_ECC_STATUS (32'h18) -`define ECC_REG_ECC_STATUS_READY_LOW (0) -`define ECC_REG_ECC_STATUS_READY_MASK (32'h1) -`define ECC_REG_ECC_STATUS_VALID_LOW (1) -`define ECC_REG_ECC_STATUS_VALID_MASK (32'h2) `define CLP_ECC_REG_ECC_SEED_0 (32'h10008080) -`define ECC_REG_ECC_SEED_0 (32'h80) `define CLP_ECC_REG_ECC_SEED_1 (32'h10008084) -`define ECC_REG_ECC_SEED_1 (32'h84) `define CLP_ECC_REG_ECC_SEED_2 (32'h10008088) -`define ECC_REG_ECC_SEED_2 (32'h88) `define CLP_ECC_REG_ECC_SEED_3 (32'h1000808c) -`define ECC_REG_ECC_SEED_3 (32'h8c) `define CLP_ECC_REG_ECC_SEED_4 (32'h10008090) -`define ECC_REG_ECC_SEED_4 (32'h90) `define CLP_ECC_REG_ECC_SEED_5 (32'h10008094) -`define ECC_REG_ECC_SEED_5 (32'h94) `define CLP_ECC_REG_ECC_SEED_6 (32'h10008098) -`define ECC_REG_ECC_SEED_6 (32'h98) `define CLP_ECC_REG_ECC_SEED_7 (32'h1000809c) -`define ECC_REG_ECC_SEED_7 (32'h9c) `define CLP_ECC_REG_ECC_SEED_8 (32'h100080a0) -`define ECC_REG_ECC_SEED_8 (32'ha0) `define CLP_ECC_REG_ECC_SEED_9 (32'h100080a4) -`define ECC_REG_ECC_SEED_9 (32'ha4) `define CLP_ECC_REG_ECC_SEED_10 (32'h100080a8) -`define ECC_REG_ECC_SEED_10 (32'ha8) `define CLP_ECC_REG_ECC_SEED_11 (32'h100080ac) -`define ECC_REG_ECC_SEED_11 (32'hac) `define CLP_ECC_REG_ECC_MSG_0 (32'h10008100) -`define ECC_REG_ECC_MSG_0 (32'h100) `define CLP_ECC_REG_ECC_MSG_1 (32'h10008104) -`define ECC_REG_ECC_MSG_1 (32'h104) `define CLP_ECC_REG_ECC_MSG_2 (32'h10008108) -`define ECC_REG_ECC_MSG_2 (32'h108) `define CLP_ECC_REG_ECC_MSG_3 (32'h1000810c) -`define ECC_REG_ECC_MSG_3 (32'h10c) `define CLP_ECC_REG_ECC_MSG_4 (32'h10008110) -`define ECC_REG_ECC_MSG_4 (32'h110) `define CLP_ECC_REG_ECC_MSG_5 (32'h10008114) -`define ECC_REG_ECC_MSG_5 (32'h114) `define CLP_ECC_REG_ECC_MSG_6 (32'h10008118) -`define ECC_REG_ECC_MSG_6 (32'h118) `define CLP_ECC_REG_ECC_MSG_7 (32'h1000811c) -`define ECC_REG_ECC_MSG_7 (32'h11c) `define CLP_ECC_REG_ECC_MSG_8 (32'h10008120) -`define ECC_REG_ECC_MSG_8 (32'h120) `define CLP_ECC_REG_ECC_MSG_9 (32'h10008124) -`define ECC_REG_ECC_MSG_9 (32'h124) `define CLP_ECC_REG_ECC_MSG_10 (32'h10008128) -`define ECC_REG_ECC_MSG_10 (32'h128) `define CLP_ECC_REG_ECC_MSG_11 (32'h1000812c) -`define ECC_REG_ECC_MSG_11 (32'h12c) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_0 (32'h10008180) -`define ECC_REG_ECC_PRIVKEY_OUT_0 (32'h180) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_1 (32'h10008184) -`define ECC_REG_ECC_PRIVKEY_OUT_1 (32'h184) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_2 (32'h10008188) -`define ECC_REG_ECC_PRIVKEY_OUT_2 (32'h188) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_3 (32'h1000818c) -`define ECC_REG_ECC_PRIVKEY_OUT_3 (32'h18c) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_4 (32'h10008190) -`define ECC_REG_ECC_PRIVKEY_OUT_4 (32'h190) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_5 (32'h10008194) -`define ECC_REG_ECC_PRIVKEY_OUT_5 (32'h194) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_6 (32'h10008198) -`define ECC_REG_ECC_PRIVKEY_OUT_6 (32'h198) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_7 (32'h1000819c) -`define ECC_REG_ECC_PRIVKEY_OUT_7 (32'h19c) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_8 (32'h100081a0) -`define ECC_REG_ECC_PRIVKEY_OUT_8 (32'h1a0) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_9 (32'h100081a4) -`define ECC_REG_ECC_PRIVKEY_OUT_9 (32'h1a4) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_10 (32'h100081a8) -`define ECC_REG_ECC_PRIVKEY_OUT_10 (32'h1a8) `define CLP_ECC_REG_ECC_PRIVKEY_OUT_11 (32'h100081ac) -`define ECC_REG_ECC_PRIVKEY_OUT_11 (32'h1ac) `define CLP_ECC_REG_ECC_PUBKEY_X_0 (32'h10008200) -`define ECC_REG_ECC_PUBKEY_X_0 (32'h200) `define CLP_ECC_REG_ECC_PUBKEY_X_1 (32'h10008204) -`define ECC_REG_ECC_PUBKEY_X_1 (32'h204) `define CLP_ECC_REG_ECC_PUBKEY_X_2 (32'h10008208) -`define ECC_REG_ECC_PUBKEY_X_2 (32'h208) `define CLP_ECC_REG_ECC_PUBKEY_X_3 (32'h1000820c) -`define ECC_REG_ECC_PUBKEY_X_3 (32'h20c) `define CLP_ECC_REG_ECC_PUBKEY_X_4 (32'h10008210) -`define ECC_REG_ECC_PUBKEY_X_4 (32'h210) `define CLP_ECC_REG_ECC_PUBKEY_X_5 (32'h10008214) -`define ECC_REG_ECC_PUBKEY_X_5 (32'h214) `define CLP_ECC_REG_ECC_PUBKEY_X_6 (32'h10008218) -`define ECC_REG_ECC_PUBKEY_X_6 (32'h218) `define CLP_ECC_REG_ECC_PUBKEY_X_7 (32'h1000821c) -`define ECC_REG_ECC_PUBKEY_X_7 (32'h21c) `define CLP_ECC_REG_ECC_PUBKEY_X_8 (32'h10008220) -`define ECC_REG_ECC_PUBKEY_X_8 (32'h220) `define CLP_ECC_REG_ECC_PUBKEY_X_9 (32'h10008224) -`define ECC_REG_ECC_PUBKEY_X_9 (32'h224) `define CLP_ECC_REG_ECC_PUBKEY_X_10 (32'h10008228) -`define ECC_REG_ECC_PUBKEY_X_10 (32'h228) `define CLP_ECC_REG_ECC_PUBKEY_X_11 (32'h1000822c) -`define ECC_REG_ECC_PUBKEY_X_11 (32'h22c) `define CLP_ECC_REG_ECC_PUBKEY_Y_0 (32'h10008280) -`define ECC_REG_ECC_PUBKEY_Y_0 (32'h280) `define CLP_ECC_REG_ECC_PUBKEY_Y_1 (32'h10008284) -`define ECC_REG_ECC_PUBKEY_Y_1 (32'h284) `define CLP_ECC_REG_ECC_PUBKEY_Y_2 (32'h10008288) -`define ECC_REG_ECC_PUBKEY_Y_2 (32'h288) `define CLP_ECC_REG_ECC_PUBKEY_Y_3 (32'h1000828c) -`define ECC_REG_ECC_PUBKEY_Y_3 (32'h28c) `define CLP_ECC_REG_ECC_PUBKEY_Y_4 (32'h10008290) -`define ECC_REG_ECC_PUBKEY_Y_4 (32'h290) `define CLP_ECC_REG_ECC_PUBKEY_Y_5 (32'h10008294) -`define ECC_REG_ECC_PUBKEY_Y_5 (32'h294) `define CLP_ECC_REG_ECC_PUBKEY_Y_6 (32'h10008298) -`define ECC_REG_ECC_PUBKEY_Y_6 (32'h298) `define CLP_ECC_REG_ECC_PUBKEY_Y_7 (32'h1000829c) -`define ECC_REG_ECC_PUBKEY_Y_7 (32'h29c) `define CLP_ECC_REG_ECC_PUBKEY_Y_8 (32'h100082a0) -`define ECC_REG_ECC_PUBKEY_Y_8 (32'h2a0) `define CLP_ECC_REG_ECC_PUBKEY_Y_9 (32'h100082a4) -`define ECC_REG_ECC_PUBKEY_Y_9 (32'h2a4) `define CLP_ECC_REG_ECC_PUBKEY_Y_10 (32'h100082a8) -`define ECC_REG_ECC_PUBKEY_Y_10 (32'h2a8) `define CLP_ECC_REG_ECC_PUBKEY_Y_11 (32'h100082ac) -`define ECC_REG_ECC_PUBKEY_Y_11 (32'h2ac) `define CLP_ECC_REG_ECC_SIGN_R_0 (32'h10008300) -`define ECC_REG_ECC_SIGN_R_0 (32'h300) `define CLP_ECC_REG_ECC_SIGN_R_1 (32'h10008304) -`define ECC_REG_ECC_SIGN_R_1 (32'h304) `define CLP_ECC_REG_ECC_SIGN_R_2 (32'h10008308) -`define ECC_REG_ECC_SIGN_R_2 (32'h308) `define CLP_ECC_REG_ECC_SIGN_R_3 (32'h1000830c) -`define ECC_REG_ECC_SIGN_R_3 (32'h30c) `define CLP_ECC_REG_ECC_SIGN_R_4 (32'h10008310) -`define ECC_REG_ECC_SIGN_R_4 (32'h310) `define CLP_ECC_REG_ECC_SIGN_R_5 (32'h10008314) -`define ECC_REG_ECC_SIGN_R_5 (32'h314) `define CLP_ECC_REG_ECC_SIGN_R_6 (32'h10008318) -`define ECC_REG_ECC_SIGN_R_6 (32'h318) `define CLP_ECC_REG_ECC_SIGN_R_7 (32'h1000831c) -`define ECC_REG_ECC_SIGN_R_7 (32'h31c) `define CLP_ECC_REG_ECC_SIGN_R_8 (32'h10008320) -`define ECC_REG_ECC_SIGN_R_8 (32'h320) `define CLP_ECC_REG_ECC_SIGN_R_9 (32'h10008324) -`define ECC_REG_ECC_SIGN_R_9 (32'h324) `define CLP_ECC_REG_ECC_SIGN_R_10 (32'h10008328) -`define ECC_REG_ECC_SIGN_R_10 (32'h328) `define CLP_ECC_REG_ECC_SIGN_R_11 (32'h1000832c) -`define ECC_REG_ECC_SIGN_R_11 (32'h32c) `define CLP_ECC_REG_ECC_SIGN_S_0 (32'h10008380) -`define ECC_REG_ECC_SIGN_S_0 (32'h380) `define CLP_ECC_REG_ECC_SIGN_S_1 (32'h10008384) -`define ECC_REG_ECC_SIGN_S_1 (32'h384) `define CLP_ECC_REG_ECC_SIGN_S_2 (32'h10008388) -`define ECC_REG_ECC_SIGN_S_2 (32'h388) `define CLP_ECC_REG_ECC_SIGN_S_3 (32'h1000838c) -`define ECC_REG_ECC_SIGN_S_3 (32'h38c) `define CLP_ECC_REG_ECC_SIGN_S_4 (32'h10008390) -`define ECC_REG_ECC_SIGN_S_4 (32'h390) `define CLP_ECC_REG_ECC_SIGN_S_5 (32'h10008394) -`define ECC_REG_ECC_SIGN_S_5 (32'h394) `define CLP_ECC_REG_ECC_SIGN_S_6 (32'h10008398) -`define ECC_REG_ECC_SIGN_S_6 (32'h398) `define CLP_ECC_REG_ECC_SIGN_S_7 (32'h1000839c) -`define ECC_REG_ECC_SIGN_S_7 (32'h39c) `define CLP_ECC_REG_ECC_SIGN_S_8 (32'h100083a0) -`define ECC_REG_ECC_SIGN_S_8 (32'h3a0) `define CLP_ECC_REG_ECC_SIGN_S_9 (32'h100083a4) -`define ECC_REG_ECC_SIGN_S_9 (32'h3a4) `define CLP_ECC_REG_ECC_SIGN_S_10 (32'h100083a8) -`define ECC_REG_ECC_SIGN_S_10 (32'h3a8) `define CLP_ECC_REG_ECC_SIGN_S_11 (32'h100083ac) -`define ECC_REG_ECC_SIGN_S_11 (32'h3ac) `define CLP_ECC_REG_ECC_VERIFY_R_0 (32'h10008400) -`define ECC_REG_ECC_VERIFY_R_0 (32'h400) `define CLP_ECC_REG_ECC_VERIFY_R_1 (32'h10008404) -`define ECC_REG_ECC_VERIFY_R_1 (32'h404) `define CLP_ECC_REG_ECC_VERIFY_R_2 (32'h10008408) -`define ECC_REG_ECC_VERIFY_R_2 (32'h408) `define CLP_ECC_REG_ECC_VERIFY_R_3 (32'h1000840c) -`define ECC_REG_ECC_VERIFY_R_3 (32'h40c) `define CLP_ECC_REG_ECC_VERIFY_R_4 (32'h10008410) -`define ECC_REG_ECC_VERIFY_R_4 (32'h410) `define CLP_ECC_REG_ECC_VERIFY_R_5 (32'h10008414) -`define ECC_REG_ECC_VERIFY_R_5 (32'h414) `define CLP_ECC_REG_ECC_VERIFY_R_6 (32'h10008418) -`define ECC_REG_ECC_VERIFY_R_6 (32'h418) `define CLP_ECC_REG_ECC_VERIFY_R_7 (32'h1000841c) -`define ECC_REG_ECC_VERIFY_R_7 (32'h41c) `define CLP_ECC_REG_ECC_VERIFY_R_8 (32'h10008420) -`define ECC_REG_ECC_VERIFY_R_8 (32'h420) `define CLP_ECC_REG_ECC_VERIFY_R_9 (32'h10008424) -`define ECC_REG_ECC_VERIFY_R_9 (32'h424) `define CLP_ECC_REG_ECC_VERIFY_R_10 (32'h10008428) -`define ECC_REG_ECC_VERIFY_R_10 (32'h428) `define CLP_ECC_REG_ECC_VERIFY_R_11 (32'h1000842c) -`define ECC_REG_ECC_VERIFY_R_11 (32'h42c) `define CLP_ECC_REG_ECC_IV_0 (32'h10008480) -`define ECC_REG_ECC_IV_0 (32'h480) `define CLP_ECC_REG_ECC_IV_1 (32'h10008484) -`define ECC_REG_ECC_IV_1 (32'h484) `define CLP_ECC_REG_ECC_IV_2 (32'h10008488) -`define ECC_REG_ECC_IV_2 (32'h488) `define CLP_ECC_REG_ECC_IV_3 (32'h1000848c) -`define ECC_REG_ECC_IV_3 (32'h48c) `define CLP_ECC_REG_ECC_IV_4 (32'h10008490) -`define ECC_REG_ECC_IV_4 (32'h490) `define CLP_ECC_REG_ECC_IV_5 (32'h10008494) -`define ECC_REG_ECC_IV_5 (32'h494) `define CLP_ECC_REG_ECC_IV_6 (32'h10008498) -`define ECC_REG_ECC_IV_6 (32'h498) `define CLP_ECC_REG_ECC_IV_7 (32'h1000849c) -`define ECC_REG_ECC_IV_7 (32'h49c) `define CLP_ECC_REG_ECC_IV_8 (32'h100084a0) -`define ECC_REG_ECC_IV_8 (32'h4a0) `define CLP_ECC_REG_ECC_IV_9 (32'h100084a4) -`define ECC_REG_ECC_IV_9 (32'h4a4) `define CLP_ECC_REG_ECC_IV_10 (32'h100084a8) -`define ECC_REG_ECC_IV_10 (32'h4a8) `define CLP_ECC_REG_ECC_IV_11 (32'h100084ac) -`define ECC_REG_ECC_IV_11 (32'h4ac) `define CLP_ECC_REG_ECC_NONCE_0 (32'h10008500) -`define ECC_REG_ECC_NONCE_0 (32'h500) `define CLP_ECC_REG_ECC_NONCE_1 (32'h10008504) -`define ECC_REG_ECC_NONCE_1 (32'h504) `define CLP_ECC_REG_ECC_NONCE_2 (32'h10008508) -`define ECC_REG_ECC_NONCE_2 (32'h508) `define CLP_ECC_REG_ECC_NONCE_3 (32'h1000850c) -`define ECC_REG_ECC_NONCE_3 (32'h50c) `define CLP_ECC_REG_ECC_NONCE_4 (32'h10008510) -`define ECC_REG_ECC_NONCE_4 (32'h510) `define CLP_ECC_REG_ECC_NONCE_5 (32'h10008514) -`define ECC_REG_ECC_NONCE_5 (32'h514) `define CLP_ECC_REG_ECC_NONCE_6 (32'h10008518) -`define ECC_REG_ECC_NONCE_6 (32'h518) `define CLP_ECC_REG_ECC_NONCE_7 (32'h1000851c) -`define ECC_REG_ECC_NONCE_7 (32'h51c) `define CLP_ECC_REG_ECC_NONCE_8 (32'h10008520) -`define ECC_REG_ECC_NONCE_8 (32'h520) `define CLP_ECC_REG_ECC_NONCE_9 (32'h10008524) -`define ECC_REG_ECC_NONCE_9 (32'h524) `define CLP_ECC_REG_ECC_NONCE_10 (32'h10008528) -`define ECC_REG_ECC_NONCE_10 (32'h528) `define CLP_ECC_REG_ECC_NONCE_11 (32'h1000852c) -`define ECC_REG_ECC_NONCE_11 (32'h52c) `define CLP_ECC_REG_ECC_PRIVKEY_IN_0 (32'h10008580) -`define ECC_REG_ECC_PRIVKEY_IN_0 (32'h580) `define CLP_ECC_REG_ECC_PRIVKEY_IN_1 (32'h10008584) -`define ECC_REG_ECC_PRIVKEY_IN_1 (32'h584) `define CLP_ECC_REG_ECC_PRIVKEY_IN_2 (32'h10008588) -`define ECC_REG_ECC_PRIVKEY_IN_2 (32'h588) `define CLP_ECC_REG_ECC_PRIVKEY_IN_3 (32'h1000858c) -`define ECC_REG_ECC_PRIVKEY_IN_3 (32'h58c) `define CLP_ECC_REG_ECC_PRIVKEY_IN_4 (32'h10008590) -`define ECC_REG_ECC_PRIVKEY_IN_4 (32'h590) `define CLP_ECC_REG_ECC_PRIVKEY_IN_5 (32'h10008594) -`define ECC_REG_ECC_PRIVKEY_IN_5 (32'h594) `define CLP_ECC_REG_ECC_PRIVKEY_IN_6 (32'h10008598) -`define ECC_REG_ECC_PRIVKEY_IN_6 (32'h598) `define CLP_ECC_REG_ECC_PRIVKEY_IN_7 (32'h1000859c) -`define ECC_REG_ECC_PRIVKEY_IN_7 (32'h59c) `define CLP_ECC_REG_ECC_PRIVKEY_IN_8 (32'h100085a0) -`define ECC_REG_ECC_PRIVKEY_IN_8 (32'h5a0) `define CLP_ECC_REG_ECC_PRIVKEY_IN_9 (32'h100085a4) -`define ECC_REG_ECC_PRIVKEY_IN_9 (32'h5a4) `define CLP_ECC_REG_ECC_PRIVKEY_IN_10 (32'h100085a8) -`define ECC_REG_ECC_PRIVKEY_IN_10 (32'h5a8) `define CLP_ECC_REG_ECC_PRIVKEY_IN_11 (32'h100085ac) -`define ECC_REG_ECC_PRIVKEY_IN_11 (32'h5ac) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_0 (32'h100085c0) -`define ECC_REG_ECC_DH_SHARED_KEY_0 (32'h5c0) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_1 (32'h100085c4) -`define ECC_REG_ECC_DH_SHARED_KEY_1 (32'h5c4) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_2 (32'h100085c8) -`define ECC_REG_ECC_DH_SHARED_KEY_2 (32'h5c8) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_3 (32'h100085cc) -`define ECC_REG_ECC_DH_SHARED_KEY_3 (32'h5cc) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_4 (32'h100085d0) -`define ECC_REG_ECC_DH_SHARED_KEY_4 (32'h5d0) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_5 (32'h100085d4) -`define ECC_REG_ECC_DH_SHARED_KEY_5 (32'h5d4) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_6 (32'h100085d8) -`define ECC_REG_ECC_DH_SHARED_KEY_6 (32'h5d8) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_7 (32'h100085dc) -`define ECC_REG_ECC_DH_SHARED_KEY_7 (32'h5dc) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_8 (32'h100085e0) -`define ECC_REG_ECC_DH_SHARED_KEY_8 (32'h5e0) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_9 (32'h100085e4) -`define ECC_REG_ECC_DH_SHARED_KEY_9 (32'h5e4) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_10 (32'h100085e8) -`define ECC_REG_ECC_DH_SHARED_KEY_10 (32'h5e8) `define CLP_ECC_REG_ECC_DH_SHARED_KEY_11 (32'h100085ec) -`define ECC_REG_ECC_DH_SHARED_KEY_11 (32'h5ec) `define CLP_ECC_REG_ECC_KV_RD_PKEY_CTRL (32'h10008600) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL (32'h600) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_LOW (0) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_MASK (32'h1) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_ENTRY_LOW (1) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_ENTRY_MASK (32'h3e) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL_PCR_HASH_EXTEND_LOW (6) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_LOW (7) -`define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_MASK (32'hffffff80) `define CLP_ECC_REG_ECC_KV_RD_PKEY_STATUS (32'h10008604) -`define ECC_REG_ECC_KV_RD_PKEY_STATUS (32'h604) -`define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_LOW (0) -`define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_MASK (32'h1) -`define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_LOW (1) -`define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_MASK (32'h2) -`define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_LOW (2) -`define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_MASK (32'h3fc) `define CLP_ECC_REG_ECC_KV_RD_SEED_CTRL (32'h10008608) -`define ECC_REG_ECC_KV_RD_SEED_CTRL (32'h608) -`define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_LOW (0) -`define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_MASK (32'h1) -`define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_ENTRY_LOW (1) -`define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_ENTRY_MASK (32'h3e) -`define ECC_REG_ECC_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_LOW (6) -`define ECC_REG_ECC_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (32'h40) -`define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_LOW (7) -`define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_MASK (32'hffffff80) `define CLP_ECC_REG_ECC_KV_RD_SEED_STATUS (32'h1000860c) -`define ECC_REG_ECC_KV_RD_SEED_STATUS (32'h60c) -`define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_LOW (0) -`define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_MASK (32'h1) -`define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_LOW (1) -`define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_MASK (32'h2) -`define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_LOW (2) -`define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_MASK (32'h3fc) `define CLP_ECC_REG_ECC_KV_WR_PKEY_CTRL (32'h10008610) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL (32'h610) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_LOW (0) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_MASK (32'h1) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_ENTRY_LOW (1) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_ENTRY_MASK (32'h3e) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_HMAC_KEY_DEST_VALID_LOW (6) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_HMAC_KEY_DEST_VALID_MASK (32'h40) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_HMAC_BLOCK_DEST_VALID_LOW (7) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_HMAC_BLOCK_DEST_VALID_MASK (32'h80) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_MLDSA_SEED_DEST_VALID_LOW (8) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_MLDSA_SEED_DEST_VALID_MASK (32'h100) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_PKEY_DEST_VALID_LOW (9) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_PKEY_DEST_VALID_MASK (32'h200) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_SEED_DEST_VALID_LOW (10) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_SEED_DEST_VALID_MASK (32'h400) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_AES_KEY_DEST_VALID_LOW (11) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_LOW (12) -`define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_MASK (32'hfffff000) `define CLP_ECC_REG_ECC_KV_WR_PKEY_STATUS (32'h10008614) -`define ECC_REG_ECC_KV_WR_PKEY_STATUS (32'h614) -`define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_LOW (0) -`define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_MASK (32'h1) -`define ECC_REG_ECC_KV_WR_PKEY_STATUS_VALID_LOW (1) -`define ECC_REG_ECC_KV_WR_PKEY_STATUS_VALID_MASK (32'h2) -`define ECC_REG_ECC_KV_WR_PKEY_STATUS_ERROR_LOW (2) -`define ECC_REG_ECC_KV_WR_PKEY_STATUS_ERROR_MASK (32'h3fc) `define CLP_ECC_REG_INTR_BLOCK_RF_START (32'h10008800) `define CLP_ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h10008800) -`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h10008804) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h10008808) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h1000880c) -`define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h10008810) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h10008814) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h10008818) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h1000881c) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h10008820) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h10008900) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h900) `define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h10008980) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) `define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'h10008a00) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'ha00) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h10008a04) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha04) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_HMAC_REG_BASE_ADDR (32'h10010000) `define CLP_HMAC_REG_HMAC512_NAME_0 (32'h10010000) -`define HMAC_REG_HMAC512_NAME_0 (32'h0) `define CLP_HMAC_REG_HMAC512_NAME_1 (32'h10010004) -`define HMAC_REG_HMAC512_NAME_1 (32'h4) `define CLP_HMAC_REG_HMAC512_VERSION_0 (32'h10010008) -`define HMAC_REG_HMAC512_VERSION_0 (32'h8) `define CLP_HMAC_REG_HMAC512_VERSION_1 (32'h1001000c) -`define HMAC_REG_HMAC512_VERSION_1 (32'hc) `define CLP_HMAC_REG_HMAC512_CTRL (32'h10010010) -`define HMAC_REG_HMAC512_CTRL (32'h10) -`define HMAC_REG_HMAC512_CTRL_INIT_LOW (0) -`define HMAC_REG_HMAC512_CTRL_INIT_MASK (32'h1) -`define HMAC_REG_HMAC512_CTRL_NEXT_LOW (1) -`define HMAC_REG_HMAC512_CTRL_NEXT_MASK (32'h2) -`define HMAC_REG_HMAC512_CTRL_ZEROIZE_LOW (2) -`define HMAC_REG_HMAC512_CTRL_ZEROIZE_MASK (32'h4) -`define HMAC_REG_HMAC512_CTRL_MODE_LOW (3) -`define HMAC_REG_HMAC512_CTRL_MODE_MASK (32'h8) -`define HMAC_REG_HMAC512_CTRL_CSR_MODE_LOW (4) -`define HMAC_REG_HMAC512_CTRL_CSR_MODE_MASK (32'h10) -`define HMAC_REG_HMAC512_CTRL_RESERVED_LOW (5) -`define HMAC_REG_HMAC512_CTRL_RESERVED_MASK (32'h20) `define CLP_HMAC_REG_HMAC512_STATUS (32'h10010018) -`define HMAC_REG_HMAC512_STATUS (32'h18) -`define HMAC_REG_HMAC512_STATUS_READY_LOW (0) -`define HMAC_REG_HMAC512_STATUS_READY_MASK (32'h1) -`define HMAC_REG_HMAC512_STATUS_VALID_LOW (1) -`define HMAC_REG_HMAC512_STATUS_VALID_MASK (32'h2) `define CLP_HMAC_REG_HMAC512_KEY_0 (32'h10010040) -`define HMAC_REG_HMAC512_KEY_0 (32'h40) `define CLP_HMAC_REG_HMAC512_KEY_1 (32'h10010044) -`define HMAC_REG_HMAC512_KEY_1 (32'h44) `define CLP_HMAC_REG_HMAC512_KEY_2 (32'h10010048) -`define HMAC_REG_HMAC512_KEY_2 (32'h48) `define CLP_HMAC_REG_HMAC512_KEY_3 (32'h1001004c) -`define HMAC_REG_HMAC512_KEY_3 (32'h4c) `define CLP_HMAC_REG_HMAC512_KEY_4 (32'h10010050) -`define HMAC_REG_HMAC512_KEY_4 (32'h50) `define CLP_HMAC_REG_HMAC512_KEY_5 (32'h10010054) -`define HMAC_REG_HMAC512_KEY_5 (32'h54) `define CLP_HMAC_REG_HMAC512_KEY_6 (32'h10010058) -`define HMAC_REG_HMAC512_KEY_6 (32'h58) `define CLP_HMAC_REG_HMAC512_KEY_7 (32'h1001005c) -`define HMAC_REG_HMAC512_KEY_7 (32'h5c) `define CLP_HMAC_REG_HMAC512_KEY_8 (32'h10010060) -`define HMAC_REG_HMAC512_KEY_8 (32'h60) `define CLP_HMAC_REG_HMAC512_KEY_9 (32'h10010064) -`define HMAC_REG_HMAC512_KEY_9 (32'h64) `define CLP_HMAC_REG_HMAC512_KEY_10 (32'h10010068) -`define HMAC_REG_HMAC512_KEY_10 (32'h68) `define CLP_HMAC_REG_HMAC512_KEY_11 (32'h1001006c) -`define HMAC_REG_HMAC512_KEY_11 (32'h6c) `define CLP_HMAC_REG_HMAC512_KEY_12 (32'h10010070) -`define HMAC_REG_HMAC512_KEY_12 (32'h70) `define CLP_HMAC_REG_HMAC512_KEY_13 (32'h10010074) -`define HMAC_REG_HMAC512_KEY_13 (32'h74) `define CLP_HMAC_REG_HMAC512_KEY_14 (32'h10010078) -`define HMAC_REG_HMAC512_KEY_14 (32'h78) `define CLP_HMAC_REG_HMAC512_KEY_15 (32'h1001007c) -`define HMAC_REG_HMAC512_KEY_15 (32'h7c) `define CLP_HMAC_REG_HMAC512_BLOCK_0 (32'h10010080) -`define HMAC_REG_HMAC512_BLOCK_0 (32'h80) `define CLP_HMAC_REG_HMAC512_BLOCK_1 (32'h10010084) -`define HMAC_REG_HMAC512_BLOCK_1 (32'h84) `define CLP_HMAC_REG_HMAC512_BLOCK_2 (32'h10010088) -`define HMAC_REG_HMAC512_BLOCK_2 (32'h88) `define CLP_HMAC_REG_HMAC512_BLOCK_3 (32'h1001008c) -`define HMAC_REG_HMAC512_BLOCK_3 (32'h8c) `define CLP_HMAC_REG_HMAC512_BLOCK_4 (32'h10010090) -`define HMAC_REG_HMAC512_BLOCK_4 (32'h90) `define CLP_HMAC_REG_HMAC512_BLOCK_5 (32'h10010094) -`define HMAC_REG_HMAC512_BLOCK_5 (32'h94) `define CLP_HMAC_REG_HMAC512_BLOCK_6 (32'h10010098) -`define HMAC_REG_HMAC512_BLOCK_6 (32'h98) `define CLP_HMAC_REG_HMAC512_BLOCK_7 (32'h1001009c) -`define HMAC_REG_HMAC512_BLOCK_7 (32'h9c) `define CLP_HMAC_REG_HMAC512_BLOCK_8 (32'h100100a0) -`define HMAC_REG_HMAC512_BLOCK_8 (32'ha0) `define CLP_HMAC_REG_HMAC512_BLOCK_9 (32'h100100a4) -`define HMAC_REG_HMAC512_BLOCK_9 (32'ha4) `define CLP_HMAC_REG_HMAC512_BLOCK_10 (32'h100100a8) -`define HMAC_REG_HMAC512_BLOCK_10 (32'ha8) `define CLP_HMAC_REG_HMAC512_BLOCK_11 (32'h100100ac) -`define HMAC_REG_HMAC512_BLOCK_11 (32'hac) `define CLP_HMAC_REG_HMAC512_BLOCK_12 (32'h100100b0) -`define HMAC_REG_HMAC512_BLOCK_12 (32'hb0) `define CLP_HMAC_REG_HMAC512_BLOCK_13 (32'h100100b4) -`define HMAC_REG_HMAC512_BLOCK_13 (32'hb4) `define CLP_HMAC_REG_HMAC512_BLOCK_14 (32'h100100b8) -`define HMAC_REG_HMAC512_BLOCK_14 (32'hb8) `define CLP_HMAC_REG_HMAC512_BLOCK_15 (32'h100100bc) -`define HMAC_REG_HMAC512_BLOCK_15 (32'hbc) `define CLP_HMAC_REG_HMAC512_BLOCK_16 (32'h100100c0) -`define HMAC_REG_HMAC512_BLOCK_16 (32'hc0) `define CLP_HMAC_REG_HMAC512_BLOCK_17 (32'h100100c4) -`define HMAC_REG_HMAC512_BLOCK_17 (32'hc4) `define CLP_HMAC_REG_HMAC512_BLOCK_18 (32'h100100c8) -`define HMAC_REG_HMAC512_BLOCK_18 (32'hc8) `define CLP_HMAC_REG_HMAC512_BLOCK_19 (32'h100100cc) -`define HMAC_REG_HMAC512_BLOCK_19 (32'hcc) `define CLP_HMAC_REG_HMAC512_BLOCK_20 (32'h100100d0) -`define HMAC_REG_HMAC512_BLOCK_20 (32'hd0) `define CLP_HMAC_REG_HMAC512_BLOCK_21 (32'h100100d4) -`define HMAC_REG_HMAC512_BLOCK_21 (32'hd4) `define CLP_HMAC_REG_HMAC512_BLOCK_22 (32'h100100d8) -`define HMAC_REG_HMAC512_BLOCK_22 (32'hd8) `define CLP_HMAC_REG_HMAC512_BLOCK_23 (32'h100100dc) -`define HMAC_REG_HMAC512_BLOCK_23 (32'hdc) `define CLP_HMAC_REG_HMAC512_BLOCK_24 (32'h100100e0) -`define HMAC_REG_HMAC512_BLOCK_24 (32'he0) `define CLP_HMAC_REG_HMAC512_BLOCK_25 (32'h100100e4) -`define HMAC_REG_HMAC512_BLOCK_25 (32'he4) `define CLP_HMAC_REG_HMAC512_BLOCK_26 (32'h100100e8) -`define HMAC_REG_HMAC512_BLOCK_26 (32'he8) `define CLP_HMAC_REG_HMAC512_BLOCK_27 (32'h100100ec) -`define HMAC_REG_HMAC512_BLOCK_27 (32'hec) `define CLP_HMAC_REG_HMAC512_BLOCK_28 (32'h100100f0) -`define HMAC_REG_HMAC512_BLOCK_28 (32'hf0) `define CLP_HMAC_REG_HMAC512_BLOCK_29 (32'h100100f4) -`define HMAC_REG_HMAC512_BLOCK_29 (32'hf4) `define CLP_HMAC_REG_HMAC512_BLOCK_30 (32'h100100f8) -`define HMAC_REG_HMAC512_BLOCK_30 (32'hf8) `define CLP_HMAC_REG_HMAC512_BLOCK_31 (32'h100100fc) -`define HMAC_REG_HMAC512_BLOCK_31 (32'hfc) `define CLP_HMAC_REG_HMAC512_TAG_0 (32'h10010100) -`define HMAC_REG_HMAC512_TAG_0 (32'h100) `define CLP_HMAC_REG_HMAC512_TAG_1 (32'h10010104) -`define HMAC_REG_HMAC512_TAG_1 (32'h104) `define CLP_HMAC_REG_HMAC512_TAG_2 (32'h10010108) -`define HMAC_REG_HMAC512_TAG_2 (32'h108) `define CLP_HMAC_REG_HMAC512_TAG_3 (32'h1001010c) -`define HMAC_REG_HMAC512_TAG_3 (32'h10c) `define CLP_HMAC_REG_HMAC512_TAG_4 (32'h10010110) -`define HMAC_REG_HMAC512_TAG_4 (32'h110) `define CLP_HMAC_REG_HMAC512_TAG_5 (32'h10010114) -`define HMAC_REG_HMAC512_TAG_5 (32'h114) `define CLP_HMAC_REG_HMAC512_TAG_6 (32'h10010118) -`define HMAC_REG_HMAC512_TAG_6 (32'h118) `define CLP_HMAC_REG_HMAC512_TAG_7 (32'h1001011c) -`define HMAC_REG_HMAC512_TAG_7 (32'h11c) `define CLP_HMAC_REG_HMAC512_TAG_8 (32'h10010120) -`define HMAC_REG_HMAC512_TAG_8 (32'h120) `define CLP_HMAC_REG_HMAC512_TAG_9 (32'h10010124) -`define HMAC_REG_HMAC512_TAG_9 (32'h124) `define CLP_HMAC_REG_HMAC512_TAG_10 (32'h10010128) -`define HMAC_REG_HMAC512_TAG_10 (32'h128) `define CLP_HMAC_REG_HMAC512_TAG_11 (32'h1001012c) -`define HMAC_REG_HMAC512_TAG_11 (32'h12c) `define CLP_HMAC_REG_HMAC512_TAG_12 (32'h10010130) -`define HMAC_REG_HMAC512_TAG_12 (32'h130) `define CLP_HMAC_REG_HMAC512_TAG_13 (32'h10010134) -`define HMAC_REG_HMAC512_TAG_13 (32'h134) `define CLP_HMAC_REG_HMAC512_TAG_14 (32'h10010138) -`define HMAC_REG_HMAC512_TAG_14 (32'h138) `define CLP_HMAC_REG_HMAC512_TAG_15 (32'h1001013c) -`define HMAC_REG_HMAC512_TAG_15 (32'h13c) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_0 (32'h10010140) -`define HMAC_REG_HMAC512_LFSR_SEED_0 (32'h140) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_1 (32'h10010144) -`define HMAC_REG_HMAC512_LFSR_SEED_1 (32'h144) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_2 (32'h10010148) -`define HMAC_REG_HMAC512_LFSR_SEED_2 (32'h148) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_3 (32'h1001014c) -`define HMAC_REG_HMAC512_LFSR_SEED_3 (32'h14c) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_4 (32'h10010150) -`define HMAC_REG_HMAC512_LFSR_SEED_4 (32'h150) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_5 (32'h10010154) -`define HMAC_REG_HMAC512_LFSR_SEED_5 (32'h154) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_6 (32'h10010158) -`define HMAC_REG_HMAC512_LFSR_SEED_6 (32'h158) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_7 (32'h1001015c) -`define HMAC_REG_HMAC512_LFSR_SEED_7 (32'h15c) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_8 (32'h10010160) -`define HMAC_REG_HMAC512_LFSR_SEED_8 (32'h160) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_9 (32'h10010164) -`define HMAC_REG_HMAC512_LFSR_SEED_9 (32'h164) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_10 (32'h10010168) -`define HMAC_REG_HMAC512_LFSR_SEED_10 (32'h168) `define CLP_HMAC_REG_HMAC512_LFSR_SEED_11 (32'h1001016c) -`define HMAC_REG_HMAC512_LFSR_SEED_11 (32'h16c) `define CLP_HMAC_REG_HMAC512_KV_RD_KEY_CTRL (32'h10010600) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL (32'h600) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_LOW (0) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_MASK (32'h1) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_ENTRY_LOW (1) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_ENTRY_MASK (32'h3e) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_LOW (6) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_RSVD_LOW (7) -`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_RSVD_MASK (32'hffffff80) `define CLP_HMAC_REG_HMAC512_KV_RD_KEY_STATUS (32'h10010604) -`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS (32'h604) -`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_READY_LOW (0) -`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_READY_MASK (32'h1) -`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_VALID_LOW (1) -`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_VALID_MASK (32'h2) -`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_ERROR_LOW (2) -`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_ERROR_MASK (32'h3fc) `define CLP_HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL (32'h10010608) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL (32'h608) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_EN_LOW (0) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_EN_MASK (32'h1) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_ENTRY_LOW (1) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_ENTRY_MASK (32'h3e) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_PCR_HASH_EXTEND_LOW (6) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_PCR_HASH_EXTEND_MASK (32'h40) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_RSVD_LOW (7) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_RSVD_MASK (32'hffffff80) `define CLP_HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS (32'h1001060c) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS (32'h60c) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_READY_LOW (0) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_READY_MASK (32'h1) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_VALID_LOW (1) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_VALID_MASK (32'h2) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_ERROR_LOW (2) -`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_ERROR_MASK (32'h3fc) `define CLP_HMAC_REG_HMAC512_KV_WR_CTRL (32'h10010610) -`define HMAC_REG_HMAC512_KV_WR_CTRL (32'h610) -`define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_EN_LOW (0) -`define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_EN_MASK (32'h1) -`define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_ENTRY_LOW (1) -`define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_ENTRY_MASK (32'h3e) -`define HMAC_REG_HMAC512_KV_WR_CTRL_HMAC_KEY_DEST_VALID_LOW (6) -`define HMAC_REG_HMAC512_KV_WR_CTRL_HMAC_KEY_DEST_VALID_MASK (32'h40) -`define HMAC_REG_HMAC512_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_LOW (7) -`define HMAC_REG_HMAC512_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_MASK (32'h80) -`define HMAC_REG_HMAC512_KV_WR_CTRL_MLDSA_SEED_DEST_VALID_LOW (8) -`define HMAC_REG_HMAC512_KV_WR_CTRL_MLDSA_SEED_DEST_VALID_MASK (32'h100) -`define HMAC_REG_HMAC512_KV_WR_CTRL_ECC_PKEY_DEST_VALID_LOW (9) -`define HMAC_REG_HMAC512_KV_WR_CTRL_ECC_PKEY_DEST_VALID_MASK (32'h200) -`define HMAC_REG_HMAC512_KV_WR_CTRL_ECC_SEED_DEST_VALID_LOW (10) -`define HMAC_REG_HMAC512_KV_WR_CTRL_ECC_SEED_DEST_VALID_MASK (32'h400) -`define HMAC_REG_HMAC512_KV_WR_CTRL_AES_KEY_DEST_VALID_LOW (11) -`define HMAC_REG_HMAC512_KV_WR_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) -`define HMAC_REG_HMAC512_KV_WR_CTRL_RSVD_LOW (12) -`define HMAC_REG_HMAC512_KV_WR_CTRL_RSVD_MASK (32'hfffff000) `define CLP_HMAC_REG_HMAC512_KV_WR_STATUS (32'h10010614) -`define HMAC_REG_HMAC512_KV_WR_STATUS (32'h614) -`define HMAC_REG_HMAC512_KV_WR_STATUS_READY_LOW (0) -`define HMAC_REG_HMAC512_KV_WR_STATUS_READY_MASK (32'h1) -`define HMAC_REG_HMAC512_KV_WR_STATUS_VALID_LOW (1) -`define HMAC_REG_HMAC512_KV_WR_STATUS_VALID_MASK (32'h2) -`define HMAC_REG_HMAC512_KV_WR_STATUS_ERROR_LOW (2) -`define HMAC_REG_HMAC512_KV_WR_STATUS_ERROR_MASK (32'h3fc) `define CLP_HMAC_REG_INTR_BLOCK_RF_START (32'h10010800) `define CLP_HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h10010800) -`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h10010804) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_MODE_ERROR_EN_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_MODE_ERROR_EN_MASK (32'h1) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_ZERO_ERROR_EN_LOW (1) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_ZERO_ERROR_EN_MASK (32'h2) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) `define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h10010808) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h1001080c) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h10010810) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h10010814) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_MODE_ERROR_STS_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_MODE_ERROR_STS_MASK (32'h1) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_ZERO_ERROR_STS_LOW (1) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_ZERO_ERROR_STS_MASK (32'h2) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) `define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h10010818) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h1001081c) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_MODE_ERROR_TRIG_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_MODE_ERROR_TRIG_MASK (32'h1) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_ZERO_ERROR_TRIG_LOW (1) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_ZERO_ERROR_TRIG_MASK (32'h2) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) -`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) `define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h10010820) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_R (32'h10010900) -`define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_R (32'h900) `define CLP_HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_R (32'h10010904) -`define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_R (32'h904) `define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h10010908) -`define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) `define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h1001090c) -`define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) `define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h10010980) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) `define CLP_HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R (32'h10010a00) -`define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R (32'ha00) -`define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R (32'h10010a04) -`define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R (32'ha04) -`define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'h10010a08) -`define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) -`define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'h10010a0c) -`define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) -`define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h10010a10) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AES_REG_BASE_ADDR (32'h10011000) `define CLP_AES_REG_KEY_SHARE0_0 (32'h10011004) -`define AES_REG_KEY_SHARE0_0 (32'h4) `define CLP_AES_REG_KEY_SHARE0_1 (32'h10011008) -`define AES_REG_KEY_SHARE0_1 (32'h8) `define CLP_AES_REG_KEY_SHARE0_2 (32'h1001100c) -`define AES_REG_KEY_SHARE0_2 (32'hc) `define CLP_AES_REG_KEY_SHARE0_3 (32'h10011010) -`define AES_REG_KEY_SHARE0_3 (32'h10) `define CLP_AES_REG_KEY_SHARE0_4 (32'h10011014) -`define AES_REG_KEY_SHARE0_4 (32'h14) `define CLP_AES_REG_KEY_SHARE0_5 (32'h10011018) -`define AES_REG_KEY_SHARE0_5 (32'h18) `define CLP_AES_REG_KEY_SHARE0_6 (32'h1001101c) -`define AES_REG_KEY_SHARE0_6 (32'h1c) `define CLP_AES_REG_KEY_SHARE0_7 (32'h10011020) -`define AES_REG_KEY_SHARE0_7 (32'h20) `define CLP_AES_REG_KEY_SHARE1_0 (32'h10011024) -`define AES_REG_KEY_SHARE1_0 (32'h24) `define CLP_AES_REG_KEY_SHARE1_1 (32'h10011028) -`define AES_REG_KEY_SHARE1_1 (32'h28) `define CLP_AES_REG_KEY_SHARE1_2 (32'h1001102c) -`define AES_REG_KEY_SHARE1_2 (32'h2c) `define CLP_AES_REG_KEY_SHARE1_3 (32'h10011030) -`define AES_REG_KEY_SHARE1_3 (32'h30) `define CLP_AES_REG_KEY_SHARE1_4 (32'h10011034) -`define AES_REG_KEY_SHARE1_4 (32'h34) `define CLP_AES_REG_KEY_SHARE1_5 (32'h10011038) -`define AES_REG_KEY_SHARE1_5 (32'h38) `define CLP_AES_REG_KEY_SHARE1_6 (32'h1001103c) -`define AES_REG_KEY_SHARE1_6 (32'h3c) `define CLP_AES_REG_KEY_SHARE1_7 (32'h10011040) -`define AES_REG_KEY_SHARE1_7 (32'h40) `define CLP_AES_REG_IV_0 (32'h10011044) -`define AES_REG_IV_0 (32'h44) `define CLP_AES_REG_IV_1 (32'h10011048) -`define AES_REG_IV_1 (32'h48) `define CLP_AES_REG_IV_2 (32'h1001104c) -`define AES_REG_IV_2 (32'h4c) `define CLP_AES_REG_IV_3 (32'h10011050) -`define AES_REG_IV_3 (32'h50) `define CLP_AES_REG_DATA_IN_0 (32'h10011054) -`define AES_REG_DATA_IN_0 (32'h54) `define CLP_AES_REG_DATA_IN_1 (32'h10011058) -`define AES_REG_DATA_IN_1 (32'h58) `define CLP_AES_REG_DATA_IN_2 (32'h1001105c) -`define AES_REG_DATA_IN_2 (32'h5c) `define CLP_AES_REG_DATA_IN_3 (32'h10011060) -`define AES_REG_DATA_IN_3 (32'h60) `define CLP_AES_REG_DATA_OUT_0 (32'h10011064) -`define AES_REG_DATA_OUT_0 (32'h64) `define CLP_AES_REG_DATA_OUT_1 (32'h10011068) -`define AES_REG_DATA_OUT_1 (32'h68) `define CLP_AES_REG_DATA_OUT_2 (32'h1001106c) -`define AES_REG_DATA_OUT_2 (32'h6c) `define CLP_AES_REG_DATA_OUT_3 (32'h10011070) -`define AES_REG_DATA_OUT_3 (32'h70) `define CLP_AES_REG_CTRL_SHADOWED (32'h10011074) -`define AES_REG_CTRL_SHADOWED (32'h74) -`define AES_REG_CTRL_SHADOWED_OPERATION_LOW (0) -`define AES_REG_CTRL_SHADOWED_OPERATION_MASK (32'h3) -`define AES_REG_CTRL_SHADOWED_MODE_LOW (2) -`define AES_REG_CTRL_SHADOWED_MODE_MASK (32'hfc) -`define AES_REG_CTRL_SHADOWED_KEY_LEN_LOW (8) -`define AES_REG_CTRL_SHADOWED_KEY_LEN_MASK (32'h700) -`define AES_REG_CTRL_SHADOWED_SIDELOAD_LOW (11) -`define AES_REG_CTRL_SHADOWED_SIDELOAD_MASK (32'h800) -`define AES_REG_CTRL_SHADOWED_PRNG_RESEED_RATE_LOW (12) -`define AES_REG_CTRL_SHADOWED_PRNG_RESEED_RATE_MASK (32'h7000) -`define AES_REG_CTRL_SHADOWED_MANUAL_OPERATION_LOW (15) -`define AES_REG_CTRL_SHADOWED_MANUAL_OPERATION_MASK (32'h8000) `define CLP_AES_REG_CTRL_AUX_SHADOWED (32'h10011078) -`define AES_REG_CTRL_AUX_SHADOWED (32'h78) -`define AES_REG_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_LOW (0) -`define AES_REG_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_MASK (32'h1) -`define AES_REG_CTRL_AUX_SHADOWED_FORCE_MASKS_LOW (1) -`define AES_REG_CTRL_AUX_SHADOWED_FORCE_MASKS_MASK (32'h2) `define CLP_AES_REG_CTRL_AUX_REGWEN (32'h1001107c) -`define AES_REG_CTRL_AUX_REGWEN (32'h7c) -`define AES_REG_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_LOW (0) -`define AES_REG_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_MASK (32'h1) `define CLP_AES_REG_TRIGGER (32'h10011080) -`define AES_REG_TRIGGER (32'h80) -`define AES_REG_TRIGGER_START_LOW (0) -`define AES_REG_TRIGGER_START_MASK (32'h1) -`define AES_REG_TRIGGER_KEY_IV_DATA_IN_CLEAR_LOW (1) -`define AES_REG_TRIGGER_KEY_IV_DATA_IN_CLEAR_MASK (32'h2) -`define AES_REG_TRIGGER_DATA_OUT_CLEAR_LOW (2) -`define AES_REG_TRIGGER_DATA_OUT_CLEAR_MASK (32'h4) -`define AES_REG_TRIGGER_PRNG_RESEED_LOW (3) -`define AES_REG_TRIGGER_PRNG_RESEED_MASK (32'h8) `define CLP_AES_REG_STATUS (32'h10011084) -`define AES_REG_STATUS (32'h84) -`define AES_REG_STATUS_IDLE_LOW (0) -`define AES_REG_STATUS_IDLE_MASK (32'h1) -`define AES_REG_STATUS_STALL_LOW (1) -`define AES_REG_STATUS_STALL_MASK (32'h2) -`define AES_REG_STATUS_OUTPUT_LOST_LOW (2) -`define AES_REG_STATUS_OUTPUT_LOST_MASK (32'h4) -`define AES_REG_STATUS_OUTPUT_VALID_LOW (3) -`define AES_REG_STATUS_OUTPUT_VALID_MASK (32'h8) -`define AES_REG_STATUS_INPUT_READY_LOW (4) -`define AES_REG_STATUS_INPUT_READY_MASK (32'h10) -`define AES_REG_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_LOW (5) -`define AES_REG_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK (32'h20) -`define AES_REG_STATUS_ALERT_FATAL_FAULT_LOW (6) -`define AES_REG_STATUS_ALERT_FATAL_FAULT_MASK (32'h40) `define CLP_AES_REG_CTRL_GCM_SHADOWED (32'h10011088) -`define AES_REG_CTRL_GCM_SHADOWED (32'h88) -`define AES_REG_CTRL_GCM_SHADOWED_PHASE_LOW (0) -`define AES_REG_CTRL_GCM_SHADOWED_PHASE_MASK (32'h3f) -`define AES_REG_CTRL_GCM_SHADOWED_NUM_VALID_BYTES_LOW (6) -`define AES_REG_CTRL_GCM_SHADOWED_NUM_VALID_BYTES_MASK (32'h7c0) `define CLP_AES_CLP_REG_BASE_ADDR (32'h10011100) `define CLP_AES_CLP_REG_AES_NAME_0 (32'h10011200) -`define AES_CLP_REG_AES_NAME_0 (32'h100) `define CLP_AES_CLP_REG_AES_NAME_1 (32'h10011204) -`define AES_CLP_REG_AES_NAME_1 (32'h104) `define CLP_AES_CLP_REG_AES_VERSION_0 (32'h10011208) -`define AES_CLP_REG_AES_VERSION_0 (32'h108) `define CLP_AES_CLP_REG_AES_VERSION_1 (32'h1001120c) -`define AES_CLP_REG_AES_VERSION_1 (32'h10c) `define CLP_AES_CLP_REG_AES_KV_RD_KEY_CTRL (32'h10011700) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL (32'h600) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_EN_LOW (0) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_EN_MASK (32'h1) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_ENTRY_LOW (1) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_ENTRY_MASK (32'h3e) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_LOW (6) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_RSVD_LOW (7) -`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_RSVD_MASK (32'hffffff80) `define CLP_AES_CLP_REG_AES_KV_RD_KEY_STATUS (32'h10011704) -`define AES_CLP_REG_AES_KV_RD_KEY_STATUS (32'h604) -`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_READY_LOW (0) -`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_READY_MASK (32'h1) -`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_VALID_LOW (1) -`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_VALID_MASK (32'h2) -`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_ERROR_LOW (2) -`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_ERROR_MASK (32'h3fc) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_START (32'h10011900) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h10011900) -`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h10011904) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h10011908) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h1001190c) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h10011910) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h10011914) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h10011918) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h1001191c) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h10011920) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h10011a00) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h10011a04) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h10011a08) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h10011a0c) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h10011a80) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'h10011b00) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'h10011b04) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'h10011b08) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'h10011b0c) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h10011b10) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_KV_REG_BASE_ADDR (32'h10018000) `define CLP_KV_REG_KEY_CTRL_0 (32'h10018000) -`define KV_REG_KEY_CTRL_0 (32'h0) -`define KV_REG_KEY_CTRL_0_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_0_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_0_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_0_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_0_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_0_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_0_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_0_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_0_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_0_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_0_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_0_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_0_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_0_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_1 (32'h10018004) -`define KV_REG_KEY_CTRL_1 (32'h4) -`define KV_REG_KEY_CTRL_1_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_1_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_1_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_1_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_1_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_1_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_1_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_1_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_1_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_1_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_1_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_1_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_1_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_1_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_2 (32'h10018008) -`define KV_REG_KEY_CTRL_2 (32'h8) -`define KV_REG_KEY_CTRL_2_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_2_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_2_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_2_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_2_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_2_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_2_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_2_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_2_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_2_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_2_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_2_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_2_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_2_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_3 (32'h1001800c) -`define KV_REG_KEY_CTRL_3 (32'hc) -`define KV_REG_KEY_CTRL_3_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_3_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_3_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_3_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_3_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_3_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_3_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_3_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_3_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_3_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_3_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_3_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_3_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_3_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_4 (32'h10018010) -`define KV_REG_KEY_CTRL_4 (32'h10) -`define KV_REG_KEY_CTRL_4_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_4_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_4_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_4_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_4_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_4_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_4_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_4_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_4_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_4_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_4_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_4_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_4_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_4_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_5 (32'h10018014) -`define KV_REG_KEY_CTRL_5 (32'h14) -`define KV_REG_KEY_CTRL_5_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_5_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_5_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_5_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_5_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_5_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_5_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_5_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_5_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_5_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_5_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_5_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_5_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_5_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_6 (32'h10018018) -`define KV_REG_KEY_CTRL_6 (32'h18) -`define KV_REG_KEY_CTRL_6_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_6_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_6_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_6_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_6_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_6_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_6_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_6_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_6_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_6_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_6_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_6_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_6_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_6_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_7 (32'h1001801c) -`define KV_REG_KEY_CTRL_7 (32'h1c) -`define KV_REG_KEY_CTRL_7_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_7_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_7_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_7_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_7_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_7_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_7_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_7_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_7_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_7_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_7_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_7_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_7_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_7_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_8 (32'h10018020) -`define KV_REG_KEY_CTRL_8 (32'h20) -`define KV_REG_KEY_CTRL_8_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_8_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_8_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_8_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_8_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_8_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_8_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_8_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_8_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_8_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_8_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_8_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_8_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_8_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_9 (32'h10018024) -`define KV_REG_KEY_CTRL_9 (32'h24) -`define KV_REG_KEY_CTRL_9_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_9_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_9_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_9_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_9_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_9_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_9_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_9_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_9_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_9_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_9_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_9_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_9_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_9_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_10 (32'h10018028) -`define KV_REG_KEY_CTRL_10 (32'h28) -`define KV_REG_KEY_CTRL_10_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_10_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_10_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_10_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_10_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_10_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_10_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_10_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_10_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_10_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_10_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_10_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_10_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_10_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_11 (32'h1001802c) -`define KV_REG_KEY_CTRL_11 (32'h2c) -`define KV_REG_KEY_CTRL_11_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_11_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_11_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_11_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_11_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_11_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_11_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_11_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_11_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_11_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_11_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_11_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_11_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_11_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_12 (32'h10018030) -`define KV_REG_KEY_CTRL_12 (32'h30) -`define KV_REG_KEY_CTRL_12_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_12_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_12_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_12_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_12_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_12_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_12_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_12_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_12_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_12_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_12_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_12_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_12_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_12_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_13 (32'h10018034) -`define KV_REG_KEY_CTRL_13 (32'h34) -`define KV_REG_KEY_CTRL_13_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_13_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_13_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_13_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_13_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_13_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_13_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_13_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_13_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_13_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_13_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_13_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_13_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_13_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_14 (32'h10018038) -`define KV_REG_KEY_CTRL_14 (32'h38) -`define KV_REG_KEY_CTRL_14_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_14_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_14_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_14_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_14_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_14_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_14_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_14_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_14_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_14_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_14_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_14_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_14_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_14_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_15 (32'h1001803c) -`define KV_REG_KEY_CTRL_15 (32'h3c) -`define KV_REG_KEY_CTRL_15_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_15_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_15_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_15_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_15_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_15_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_15_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_15_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_15_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_15_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_15_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_15_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_15_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_15_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_16 (32'h10018040) -`define KV_REG_KEY_CTRL_16 (32'h40) -`define KV_REG_KEY_CTRL_16_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_16_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_16_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_16_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_16_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_16_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_16_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_16_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_16_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_16_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_16_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_16_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_16_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_16_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_17 (32'h10018044) -`define KV_REG_KEY_CTRL_17 (32'h44) -`define KV_REG_KEY_CTRL_17_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_17_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_17_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_17_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_17_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_17_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_17_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_17_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_17_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_17_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_17_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_17_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_17_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_17_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_18 (32'h10018048) -`define KV_REG_KEY_CTRL_18 (32'h48) -`define KV_REG_KEY_CTRL_18_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_18_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_18_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_18_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_18_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_18_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_18_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_18_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_18_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_18_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_18_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_18_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_18_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_18_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_19 (32'h1001804c) -`define KV_REG_KEY_CTRL_19 (32'h4c) -`define KV_REG_KEY_CTRL_19_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_19_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_19_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_19_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_19_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_19_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_19_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_19_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_19_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_19_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_19_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_19_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_19_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_19_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_20 (32'h10018050) -`define KV_REG_KEY_CTRL_20 (32'h50) -`define KV_REG_KEY_CTRL_20_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_20_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_20_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_20_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_20_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_20_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_20_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_20_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_20_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_20_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_20_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_20_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_20_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_20_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_21 (32'h10018054) -`define KV_REG_KEY_CTRL_21 (32'h54) -`define KV_REG_KEY_CTRL_21_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_21_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_21_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_21_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_21_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_21_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_21_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_21_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_21_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_21_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_21_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_21_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_21_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_21_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_22 (32'h10018058) -`define KV_REG_KEY_CTRL_22 (32'h58) -`define KV_REG_KEY_CTRL_22_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_22_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_22_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_22_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_22_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_22_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_22_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_22_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_22_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_22_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_22_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_22_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_22_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_22_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_CTRL_23 (32'h1001805c) -`define KV_REG_KEY_CTRL_23 (32'h5c) -`define KV_REG_KEY_CTRL_23_LOCK_WR_LOW (0) -`define KV_REG_KEY_CTRL_23_LOCK_WR_MASK (32'h1) -`define KV_REG_KEY_CTRL_23_LOCK_USE_LOW (1) -`define KV_REG_KEY_CTRL_23_LOCK_USE_MASK (32'h2) -`define KV_REG_KEY_CTRL_23_CLEAR_LOW (2) -`define KV_REG_KEY_CTRL_23_CLEAR_MASK (32'h4) -`define KV_REG_KEY_CTRL_23_RSVD0_LOW (3) -`define KV_REG_KEY_CTRL_23_RSVD0_MASK (32'h8) -`define KV_REG_KEY_CTRL_23_RSVD1_LOW (4) -`define KV_REG_KEY_CTRL_23_RSVD1_MASK (32'h1f0) -`define KV_REG_KEY_CTRL_23_DEST_VALID_LOW (9) -`define KV_REG_KEY_CTRL_23_DEST_VALID_MASK (32'h1fe00) -`define KV_REG_KEY_CTRL_23_LAST_DWORD_LOW (17) -`define KV_REG_KEY_CTRL_23_LAST_DWORD_MASK (32'h1e0000) `define CLP_KV_REG_KEY_ENTRY_0_0 (32'h10018600) -`define KV_REG_KEY_ENTRY_0_0 (32'h600) `define CLP_KV_REG_KEY_ENTRY_0_1 (32'h10018604) -`define KV_REG_KEY_ENTRY_0_1 (32'h604) `define CLP_KV_REG_KEY_ENTRY_0_2 (32'h10018608) -`define KV_REG_KEY_ENTRY_0_2 (32'h608) `define CLP_KV_REG_KEY_ENTRY_0_3 (32'h1001860c) -`define KV_REG_KEY_ENTRY_0_3 (32'h60c) `define CLP_KV_REG_KEY_ENTRY_0_4 (32'h10018610) -`define KV_REG_KEY_ENTRY_0_4 (32'h610) `define CLP_KV_REG_KEY_ENTRY_0_5 (32'h10018614) -`define KV_REG_KEY_ENTRY_0_5 (32'h614) `define CLP_KV_REG_KEY_ENTRY_0_6 (32'h10018618) -`define KV_REG_KEY_ENTRY_0_6 (32'h618) `define CLP_KV_REG_KEY_ENTRY_0_7 (32'h1001861c) -`define KV_REG_KEY_ENTRY_0_7 (32'h61c) `define CLP_KV_REG_KEY_ENTRY_0_8 (32'h10018620) -`define KV_REG_KEY_ENTRY_0_8 (32'h620) `define CLP_KV_REG_KEY_ENTRY_0_9 (32'h10018624) -`define KV_REG_KEY_ENTRY_0_9 (32'h624) `define CLP_KV_REG_KEY_ENTRY_0_10 (32'h10018628) -`define KV_REG_KEY_ENTRY_0_10 (32'h628) `define CLP_KV_REG_KEY_ENTRY_0_11 (32'h1001862c) -`define KV_REG_KEY_ENTRY_0_11 (32'h62c) `define CLP_KV_REG_KEY_ENTRY_0_12 (32'h10018630) -`define KV_REG_KEY_ENTRY_0_12 (32'h630) `define CLP_KV_REG_KEY_ENTRY_0_13 (32'h10018634) -`define KV_REG_KEY_ENTRY_0_13 (32'h634) `define CLP_KV_REG_KEY_ENTRY_0_14 (32'h10018638) -`define KV_REG_KEY_ENTRY_0_14 (32'h638) `define CLP_KV_REG_KEY_ENTRY_0_15 (32'h1001863c) -`define KV_REG_KEY_ENTRY_0_15 (32'h63c) `define CLP_KV_REG_KEY_ENTRY_1_0 (32'h10018640) -`define KV_REG_KEY_ENTRY_1_0 (32'h640) `define CLP_KV_REG_KEY_ENTRY_1_1 (32'h10018644) -`define KV_REG_KEY_ENTRY_1_1 (32'h644) `define CLP_KV_REG_KEY_ENTRY_1_2 (32'h10018648) -`define KV_REG_KEY_ENTRY_1_2 (32'h648) `define CLP_KV_REG_KEY_ENTRY_1_3 (32'h1001864c) -`define KV_REG_KEY_ENTRY_1_3 (32'h64c) `define CLP_KV_REG_KEY_ENTRY_1_4 (32'h10018650) -`define KV_REG_KEY_ENTRY_1_4 (32'h650) `define CLP_KV_REG_KEY_ENTRY_1_5 (32'h10018654) -`define KV_REG_KEY_ENTRY_1_5 (32'h654) `define CLP_KV_REG_KEY_ENTRY_1_6 (32'h10018658) -`define KV_REG_KEY_ENTRY_1_6 (32'h658) `define CLP_KV_REG_KEY_ENTRY_1_7 (32'h1001865c) -`define KV_REG_KEY_ENTRY_1_7 (32'h65c) `define CLP_KV_REG_KEY_ENTRY_1_8 (32'h10018660) -`define KV_REG_KEY_ENTRY_1_8 (32'h660) `define CLP_KV_REG_KEY_ENTRY_1_9 (32'h10018664) -`define KV_REG_KEY_ENTRY_1_9 (32'h664) `define CLP_KV_REG_KEY_ENTRY_1_10 (32'h10018668) -`define KV_REG_KEY_ENTRY_1_10 (32'h668) `define CLP_KV_REG_KEY_ENTRY_1_11 (32'h1001866c) -`define KV_REG_KEY_ENTRY_1_11 (32'h66c) `define CLP_KV_REG_KEY_ENTRY_1_12 (32'h10018670) -`define KV_REG_KEY_ENTRY_1_12 (32'h670) `define CLP_KV_REG_KEY_ENTRY_1_13 (32'h10018674) -`define KV_REG_KEY_ENTRY_1_13 (32'h674) `define CLP_KV_REG_KEY_ENTRY_1_14 (32'h10018678) -`define KV_REG_KEY_ENTRY_1_14 (32'h678) `define CLP_KV_REG_KEY_ENTRY_1_15 (32'h1001867c) -`define KV_REG_KEY_ENTRY_1_15 (32'h67c) `define CLP_KV_REG_KEY_ENTRY_2_0 (32'h10018680) -`define KV_REG_KEY_ENTRY_2_0 (32'h680) `define CLP_KV_REG_KEY_ENTRY_2_1 (32'h10018684) -`define KV_REG_KEY_ENTRY_2_1 (32'h684) `define CLP_KV_REG_KEY_ENTRY_2_2 (32'h10018688) -`define KV_REG_KEY_ENTRY_2_2 (32'h688) `define CLP_KV_REG_KEY_ENTRY_2_3 (32'h1001868c) -`define KV_REG_KEY_ENTRY_2_3 (32'h68c) `define CLP_KV_REG_KEY_ENTRY_2_4 (32'h10018690) -`define KV_REG_KEY_ENTRY_2_4 (32'h690) `define CLP_KV_REG_KEY_ENTRY_2_5 (32'h10018694) -`define KV_REG_KEY_ENTRY_2_5 (32'h694) `define CLP_KV_REG_KEY_ENTRY_2_6 (32'h10018698) -`define KV_REG_KEY_ENTRY_2_6 (32'h698) `define CLP_KV_REG_KEY_ENTRY_2_7 (32'h1001869c) -`define KV_REG_KEY_ENTRY_2_7 (32'h69c) `define CLP_KV_REG_KEY_ENTRY_2_8 (32'h100186a0) -`define KV_REG_KEY_ENTRY_2_8 (32'h6a0) `define CLP_KV_REG_KEY_ENTRY_2_9 (32'h100186a4) -`define KV_REG_KEY_ENTRY_2_9 (32'h6a4) `define CLP_KV_REG_KEY_ENTRY_2_10 (32'h100186a8) -`define KV_REG_KEY_ENTRY_2_10 (32'h6a8) `define CLP_KV_REG_KEY_ENTRY_2_11 (32'h100186ac) -`define KV_REG_KEY_ENTRY_2_11 (32'h6ac) `define CLP_KV_REG_KEY_ENTRY_2_12 (32'h100186b0) -`define KV_REG_KEY_ENTRY_2_12 (32'h6b0) `define CLP_KV_REG_KEY_ENTRY_2_13 (32'h100186b4) -`define KV_REG_KEY_ENTRY_2_13 (32'h6b4) `define CLP_KV_REG_KEY_ENTRY_2_14 (32'h100186b8) -`define KV_REG_KEY_ENTRY_2_14 (32'h6b8) `define CLP_KV_REG_KEY_ENTRY_2_15 (32'h100186bc) -`define KV_REG_KEY_ENTRY_2_15 (32'h6bc) `define CLP_KV_REG_KEY_ENTRY_3_0 (32'h100186c0) -`define KV_REG_KEY_ENTRY_3_0 (32'h6c0) `define CLP_KV_REG_KEY_ENTRY_3_1 (32'h100186c4) -`define KV_REG_KEY_ENTRY_3_1 (32'h6c4) `define CLP_KV_REG_KEY_ENTRY_3_2 (32'h100186c8) -`define KV_REG_KEY_ENTRY_3_2 (32'h6c8) `define CLP_KV_REG_KEY_ENTRY_3_3 (32'h100186cc) -`define KV_REG_KEY_ENTRY_3_3 (32'h6cc) `define CLP_KV_REG_KEY_ENTRY_3_4 (32'h100186d0) -`define KV_REG_KEY_ENTRY_3_4 (32'h6d0) `define CLP_KV_REG_KEY_ENTRY_3_5 (32'h100186d4) -`define KV_REG_KEY_ENTRY_3_5 (32'h6d4) `define CLP_KV_REG_KEY_ENTRY_3_6 (32'h100186d8) -`define KV_REG_KEY_ENTRY_3_6 (32'h6d8) `define CLP_KV_REG_KEY_ENTRY_3_7 (32'h100186dc) -`define KV_REG_KEY_ENTRY_3_7 (32'h6dc) `define CLP_KV_REG_KEY_ENTRY_3_8 (32'h100186e0) -`define KV_REG_KEY_ENTRY_3_8 (32'h6e0) `define CLP_KV_REG_KEY_ENTRY_3_9 (32'h100186e4) -`define KV_REG_KEY_ENTRY_3_9 (32'h6e4) `define CLP_KV_REG_KEY_ENTRY_3_10 (32'h100186e8) -`define KV_REG_KEY_ENTRY_3_10 (32'h6e8) `define CLP_KV_REG_KEY_ENTRY_3_11 (32'h100186ec) -`define KV_REG_KEY_ENTRY_3_11 (32'h6ec) `define CLP_KV_REG_KEY_ENTRY_3_12 (32'h100186f0) -`define KV_REG_KEY_ENTRY_3_12 (32'h6f0) `define CLP_KV_REG_KEY_ENTRY_3_13 (32'h100186f4) -`define KV_REG_KEY_ENTRY_3_13 (32'h6f4) `define CLP_KV_REG_KEY_ENTRY_3_14 (32'h100186f8) -`define KV_REG_KEY_ENTRY_3_14 (32'h6f8) `define CLP_KV_REG_KEY_ENTRY_3_15 (32'h100186fc) -`define KV_REG_KEY_ENTRY_3_15 (32'h6fc) `define CLP_KV_REG_KEY_ENTRY_4_0 (32'h10018700) -`define KV_REG_KEY_ENTRY_4_0 (32'h700) `define CLP_KV_REG_KEY_ENTRY_4_1 (32'h10018704) -`define KV_REG_KEY_ENTRY_4_1 (32'h704) `define CLP_KV_REG_KEY_ENTRY_4_2 (32'h10018708) -`define KV_REG_KEY_ENTRY_4_2 (32'h708) `define CLP_KV_REG_KEY_ENTRY_4_3 (32'h1001870c) -`define KV_REG_KEY_ENTRY_4_3 (32'h70c) `define CLP_KV_REG_KEY_ENTRY_4_4 (32'h10018710) -`define KV_REG_KEY_ENTRY_4_4 (32'h710) `define CLP_KV_REG_KEY_ENTRY_4_5 (32'h10018714) -`define KV_REG_KEY_ENTRY_4_5 (32'h714) `define CLP_KV_REG_KEY_ENTRY_4_6 (32'h10018718) -`define KV_REG_KEY_ENTRY_4_6 (32'h718) `define CLP_KV_REG_KEY_ENTRY_4_7 (32'h1001871c) -`define KV_REG_KEY_ENTRY_4_7 (32'h71c) `define CLP_KV_REG_KEY_ENTRY_4_8 (32'h10018720) -`define KV_REG_KEY_ENTRY_4_8 (32'h720) `define CLP_KV_REG_KEY_ENTRY_4_9 (32'h10018724) -`define KV_REG_KEY_ENTRY_4_9 (32'h724) `define CLP_KV_REG_KEY_ENTRY_4_10 (32'h10018728) -`define KV_REG_KEY_ENTRY_4_10 (32'h728) `define CLP_KV_REG_KEY_ENTRY_4_11 (32'h1001872c) -`define KV_REG_KEY_ENTRY_4_11 (32'h72c) `define CLP_KV_REG_KEY_ENTRY_4_12 (32'h10018730) -`define KV_REG_KEY_ENTRY_4_12 (32'h730) `define CLP_KV_REG_KEY_ENTRY_4_13 (32'h10018734) -`define KV_REG_KEY_ENTRY_4_13 (32'h734) `define CLP_KV_REG_KEY_ENTRY_4_14 (32'h10018738) -`define KV_REG_KEY_ENTRY_4_14 (32'h738) `define CLP_KV_REG_KEY_ENTRY_4_15 (32'h1001873c) -`define KV_REG_KEY_ENTRY_4_15 (32'h73c) `define CLP_KV_REG_KEY_ENTRY_5_0 (32'h10018740) -`define KV_REG_KEY_ENTRY_5_0 (32'h740) `define CLP_KV_REG_KEY_ENTRY_5_1 (32'h10018744) -`define KV_REG_KEY_ENTRY_5_1 (32'h744) `define CLP_KV_REG_KEY_ENTRY_5_2 (32'h10018748) -`define KV_REG_KEY_ENTRY_5_2 (32'h748) `define CLP_KV_REG_KEY_ENTRY_5_3 (32'h1001874c) -`define KV_REG_KEY_ENTRY_5_3 (32'h74c) `define CLP_KV_REG_KEY_ENTRY_5_4 (32'h10018750) -`define KV_REG_KEY_ENTRY_5_4 (32'h750) `define CLP_KV_REG_KEY_ENTRY_5_5 (32'h10018754) -`define KV_REG_KEY_ENTRY_5_5 (32'h754) `define CLP_KV_REG_KEY_ENTRY_5_6 (32'h10018758) -`define KV_REG_KEY_ENTRY_5_6 (32'h758) `define CLP_KV_REG_KEY_ENTRY_5_7 (32'h1001875c) -`define KV_REG_KEY_ENTRY_5_7 (32'h75c) `define CLP_KV_REG_KEY_ENTRY_5_8 (32'h10018760) -`define KV_REG_KEY_ENTRY_5_8 (32'h760) `define CLP_KV_REG_KEY_ENTRY_5_9 (32'h10018764) -`define KV_REG_KEY_ENTRY_5_9 (32'h764) `define CLP_KV_REG_KEY_ENTRY_5_10 (32'h10018768) -`define KV_REG_KEY_ENTRY_5_10 (32'h768) `define CLP_KV_REG_KEY_ENTRY_5_11 (32'h1001876c) -`define KV_REG_KEY_ENTRY_5_11 (32'h76c) `define CLP_KV_REG_KEY_ENTRY_5_12 (32'h10018770) -`define KV_REG_KEY_ENTRY_5_12 (32'h770) `define CLP_KV_REG_KEY_ENTRY_5_13 (32'h10018774) -`define KV_REG_KEY_ENTRY_5_13 (32'h774) `define CLP_KV_REG_KEY_ENTRY_5_14 (32'h10018778) -`define KV_REG_KEY_ENTRY_5_14 (32'h778) `define CLP_KV_REG_KEY_ENTRY_5_15 (32'h1001877c) -`define KV_REG_KEY_ENTRY_5_15 (32'h77c) `define CLP_KV_REG_KEY_ENTRY_6_0 (32'h10018780) -`define KV_REG_KEY_ENTRY_6_0 (32'h780) `define CLP_KV_REG_KEY_ENTRY_6_1 (32'h10018784) -`define KV_REG_KEY_ENTRY_6_1 (32'h784) `define CLP_KV_REG_KEY_ENTRY_6_2 (32'h10018788) -`define KV_REG_KEY_ENTRY_6_2 (32'h788) `define CLP_KV_REG_KEY_ENTRY_6_3 (32'h1001878c) -`define KV_REG_KEY_ENTRY_6_3 (32'h78c) `define CLP_KV_REG_KEY_ENTRY_6_4 (32'h10018790) -`define KV_REG_KEY_ENTRY_6_4 (32'h790) `define CLP_KV_REG_KEY_ENTRY_6_5 (32'h10018794) -`define KV_REG_KEY_ENTRY_6_5 (32'h794) `define CLP_KV_REG_KEY_ENTRY_6_6 (32'h10018798) -`define KV_REG_KEY_ENTRY_6_6 (32'h798) `define CLP_KV_REG_KEY_ENTRY_6_7 (32'h1001879c) -`define KV_REG_KEY_ENTRY_6_7 (32'h79c) `define CLP_KV_REG_KEY_ENTRY_6_8 (32'h100187a0) -`define KV_REG_KEY_ENTRY_6_8 (32'h7a0) `define CLP_KV_REG_KEY_ENTRY_6_9 (32'h100187a4) -`define KV_REG_KEY_ENTRY_6_9 (32'h7a4) `define CLP_KV_REG_KEY_ENTRY_6_10 (32'h100187a8) -`define KV_REG_KEY_ENTRY_6_10 (32'h7a8) `define CLP_KV_REG_KEY_ENTRY_6_11 (32'h100187ac) -`define KV_REG_KEY_ENTRY_6_11 (32'h7ac) `define CLP_KV_REG_KEY_ENTRY_6_12 (32'h100187b0) -`define KV_REG_KEY_ENTRY_6_12 (32'h7b0) `define CLP_KV_REG_KEY_ENTRY_6_13 (32'h100187b4) -`define KV_REG_KEY_ENTRY_6_13 (32'h7b4) `define CLP_KV_REG_KEY_ENTRY_6_14 (32'h100187b8) -`define KV_REG_KEY_ENTRY_6_14 (32'h7b8) `define CLP_KV_REG_KEY_ENTRY_6_15 (32'h100187bc) -`define KV_REG_KEY_ENTRY_6_15 (32'h7bc) `define CLP_KV_REG_KEY_ENTRY_7_0 (32'h100187c0) -`define KV_REG_KEY_ENTRY_7_0 (32'h7c0) `define CLP_KV_REG_KEY_ENTRY_7_1 (32'h100187c4) -`define KV_REG_KEY_ENTRY_7_1 (32'h7c4) `define CLP_KV_REG_KEY_ENTRY_7_2 (32'h100187c8) -`define KV_REG_KEY_ENTRY_7_2 (32'h7c8) `define CLP_KV_REG_KEY_ENTRY_7_3 (32'h100187cc) -`define KV_REG_KEY_ENTRY_7_3 (32'h7cc) `define CLP_KV_REG_KEY_ENTRY_7_4 (32'h100187d0) -`define KV_REG_KEY_ENTRY_7_4 (32'h7d0) `define CLP_KV_REG_KEY_ENTRY_7_5 (32'h100187d4) -`define KV_REG_KEY_ENTRY_7_5 (32'h7d4) `define CLP_KV_REG_KEY_ENTRY_7_6 (32'h100187d8) -`define KV_REG_KEY_ENTRY_7_6 (32'h7d8) `define CLP_KV_REG_KEY_ENTRY_7_7 (32'h100187dc) -`define KV_REG_KEY_ENTRY_7_7 (32'h7dc) `define CLP_KV_REG_KEY_ENTRY_7_8 (32'h100187e0) -`define KV_REG_KEY_ENTRY_7_8 (32'h7e0) `define CLP_KV_REG_KEY_ENTRY_7_9 (32'h100187e4) -`define KV_REG_KEY_ENTRY_7_9 (32'h7e4) `define CLP_KV_REG_KEY_ENTRY_7_10 (32'h100187e8) -`define KV_REG_KEY_ENTRY_7_10 (32'h7e8) `define CLP_KV_REG_KEY_ENTRY_7_11 (32'h100187ec) -`define KV_REG_KEY_ENTRY_7_11 (32'h7ec) `define CLP_KV_REG_KEY_ENTRY_7_12 (32'h100187f0) -`define KV_REG_KEY_ENTRY_7_12 (32'h7f0) `define CLP_KV_REG_KEY_ENTRY_7_13 (32'h100187f4) -`define KV_REG_KEY_ENTRY_7_13 (32'h7f4) `define CLP_KV_REG_KEY_ENTRY_7_14 (32'h100187f8) -`define KV_REG_KEY_ENTRY_7_14 (32'h7f8) `define CLP_KV_REG_KEY_ENTRY_7_15 (32'h100187fc) -`define KV_REG_KEY_ENTRY_7_15 (32'h7fc) `define CLP_KV_REG_KEY_ENTRY_8_0 (32'h10018800) -`define KV_REG_KEY_ENTRY_8_0 (32'h800) `define CLP_KV_REG_KEY_ENTRY_8_1 (32'h10018804) -`define KV_REG_KEY_ENTRY_8_1 (32'h804) `define CLP_KV_REG_KEY_ENTRY_8_2 (32'h10018808) -`define KV_REG_KEY_ENTRY_8_2 (32'h808) `define CLP_KV_REG_KEY_ENTRY_8_3 (32'h1001880c) -`define KV_REG_KEY_ENTRY_8_3 (32'h80c) `define CLP_KV_REG_KEY_ENTRY_8_4 (32'h10018810) -`define KV_REG_KEY_ENTRY_8_4 (32'h810) `define CLP_KV_REG_KEY_ENTRY_8_5 (32'h10018814) -`define KV_REG_KEY_ENTRY_8_5 (32'h814) `define CLP_KV_REG_KEY_ENTRY_8_6 (32'h10018818) -`define KV_REG_KEY_ENTRY_8_6 (32'h818) `define CLP_KV_REG_KEY_ENTRY_8_7 (32'h1001881c) -`define KV_REG_KEY_ENTRY_8_7 (32'h81c) `define CLP_KV_REG_KEY_ENTRY_8_8 (32'h10018820) -`define KV_REG_KEY_ENTRY_8_8 (32'h820) `define CLP_KV_REG_KEY_ENTRY_8_9 (32'h10018824) -`define KV_REG_KEY_ENTRY_8_9 (32'h824) `define CLP_KV_REG_KEY_ENTRY_8_10 (32'h10018828) -`define KV_REG_KEY_ENTRY_8_10 (32'h828) `define CLP_KV_REG_KEY_ENTRY_8_11 (32'h1001882c) -`define KV_REG_KEY_ENTRY_8_11 (32'h82c) `define CLP_KV_REG_KEY_ENTRY_8_12 (32'h10018830) -`define KV_REG_KEY_ENTRY_8_12 (32'h830) `define CLP_KV_REG_KEY_ENTRY_8_13 (32'h10018834) -`define KV_REG_KEY_ENTRY_8_13 (32'h834) `define CLP_KV_REG_KEY_ENTRY_8_14 (32'h10018838) -`define KV_REG_KEY_ENTRY_8_14 (32'h838) `define CLP_KV_REG_KEY_ENTRY_8_15 (32'h1001883c) -`define KV_REG_KEY_ENTRY_8_15 (32'h83c) `define CLP_KV_REG_KEY_ENTRY_9_0 (32'h10018840) -`define KV_REG_KEY_ENTRY_9_0 (32'h840) `define CLP_KV_REG_KEY_ENTRY_9_1 (32'h10018844) -`define KV_REG_KEY_ENTRY_9_1 (32'h844) `define CLP_KV_REG_KEY_ENTRY_9_2 (32'h10018848) -`define KV_REG_KEY_ENTRY_9_2 (32'h848) `define CLP_KV_REG_KEY_ENTRY_9_3 (32'h1001884c) -`define KV_REG_KEY_ENTRY_9_3 (32'h84c) `define CLP_KV_REG_KEY_ENTRY_9_4 (32'h10018850) -`define KV_REG_KEY_ENTRY_9_4 (32'h850) `define CLP_KV_REG_KEY_ENTRY_9_5 (32'h10018854) -`define KV_REG_KEY_ENTRY_9_5 (32'h854) `define CLP_KV_REG_KEY_ENTRY_9_6 (32'h10018858) -`define KV_REG_KEY_ENTRY_9_6 (32'h858) `define CLP_KV_REG_KEY_ENTRY_9_7 (32'h1001885c) -`define KV_REG_KEY_ENTRY_9_7 (32'h85c) `define CLP_KV_REG_KEY_ENTRY_9_8 (32'h10018860) -`define KV_REG_KEY_ENTRY_9_8 (32'h860) `define CLP_KV_REG_KEY_ENTRY_9_9 (32'h10018864) -`define KV_REG_KEY_ENTRY_9_9 (32'h864) `define CLP_KV_REG_KEY_ENTRY_9_10 (32'h10018868) -`define KV_REG_KEY_ENTRY_9_10 (32'h868) `define CLP_KV_REG_KEY_ENTRY_9_11 (32'h1001886c) -`define KV_REG_KEY_ENTRY_9_11 (32'h86c) `define CLP_KV_REG_KEY_ENTRY_9_12 (32'h10018870) -`define KV_REG_KEY_ENTRY_9_12 (32'h870) `define CLP_KV_REG_KEY_ENTRY_9_13 (32'h10018874) -`define KV_REG_KEY_ENTRY_9_13 (32'h874) `define CLP_KV_REG_KEY_ENTRY_9_14 (32'h10018878) -`define KV_REG_KEY_ENTRY_9_14 (32'h878) `define CLP_KV_REG_KEY_ENTRY_9_15 (32'h1001887c) -`define KV_REG_KEY_ENTRY_9_15 (32'h87c) `define CLP_KV_REG_KEY_ENTRY_10_0 (32'h10018880) -`define KV_REG_KEY_ENTRY_10_0 (32'h880) `define CLP_KV_REG_KEY_ENTRY_10_1 (32'h10018884) -`define KV_REG_KEY_ENTRY_10_1 (32'h884) `define CLP_KV_REG_KEY_ENTRY_10_2 (32'h10018888) -`define KV_REG_KEY_ENTRY_10_2 (32'h888) `define CLP_KV_REG_KEY_ENTRY_10_3 (32'h1001888c) -`define KV_REG_KEY_ENTRY_10_3 (32'h88c) `define CLP_KV_REG_KEY_ENTRY_10_4 (32'h10018890) -`define KV_REG_KEY_ENTRY_10_4 (32'h890) `define CLP_KV_REG_KEY_ENTRY_10_5 (32'h10018894) -`define KV_REG_KEY_ENTRY_10_5 (32'h894) `define CLP_KV_REG_KEY_ENTRY_10_6 (32'h10018898) -`define KV_REG_KEY_ENTRY_10_6 (32'h898) `define CLP_KV_REG_KEY_ENTRY_10_7 (32'h1001889c) -`define KV_REG_KEY_ENTRY_10_7 (32'h89c) `define CLP_KV_REG_KEY_ENTRY_10_8 (32'h100188a0) -`define KV_REG_KEY_ENTRY_10_8 (32'h8a0) `define CLP_KV_REG_KEY_ENTRY_10_9 (32'h100188a4) -`define KV_REG_KEY_ENTRY_10_9 (32'h8a4) `define CLP_KV_REG_KEY_ENTRY_10_10 (32'h100188a8) -`define KV_REG_KEY_ENTRY_10_10 (32'h8a8) `define CLP_KV_REG_KEY_ENTRY_10_11 (32'h100188ac) -`define KV_REG_KEY_ENTRY_10_11 (32'h8ac) `define CLP_KV_REG_KEY_ENTRY_10_12 (32'h100188b0) -`define KV_REG_KEY_ENTRY_10_12 (32'h8b0) `define CLP_KV_REG_KEY_ENTRY_10_13 (32'h100188b4) -`define KV_REG_KEY_ENTRY_10_13 (32'h8b4) `define CLP_KV_REG_KEY_ENTRY_10_14 (32'h100188b8) -`define KV_REG_KEY_ENTRY_10_14 (32'h8b8) `define CLP_KV_REG_KEY_ENTRY_10_15 (32'h100188bc) -`define KV_REG_KEY_ENTRY_10_15 (32'h8bc) `define CLP_KV_REG_KEY_ENTRY_11_0 (32'h100188c0) -`define KV_REG_KEY_ENTRY_11_0 (32'h8c0) `define CLP_KV_REG_KEY_ENTRY_11_1 (32'h100188c4) -`define KV_REG_KEY_ENTRY_11_1 (32'h8c4) `define CLP_KV_REG_KEY_ENTRY_11_2 (32'h100188c8) -`define KV_REG_KEY_ENTRY_11_2 (32'h8c8) `define CLP_KV_REG_KEY_ENTRY_11_3 (32'h100188cc) -`define KV_REG_KEY_ENTRY_11_3 (32'h8cc) `define CLP_KV_REG_KEY_ENTRY_11_4 (32'h100188d0) -`define KV_REG_KEY_ENTRY_11_4 (32'h8d0) `define CLP_KV_REG_KEY_ENTRY_11_5 (32'h100188d4) -`define KV_REG_KEY_ENTRY_11_5 (32'h8d4) `define CLP_KV_REG_KEY_ENTRY_11_6 (32'h100188d8) -`define KV_REG_KEY_ENTRY_11_6 (32'h8d8) `define CLP_KV_REG_KEY_ENTRY_11_7 (32'h100188dc) -`define KV_REG_KEY_ENTRY_11_7 (32'h8dc) `define CLP_KV_REG_KEY_ENTRY_11_8 (32'h100188e0) -`define KV_REG_KEY_ENTRY_11_8 (32'h8e0) `define CLP_KV_REG_KEY_ENTRY_11_9 (32'h100188e4) -`define KV_REG_KEY_ENTRY_11_9 (32'h8e4) `define CLP_KV_REG_KEY_ENTRY_11_10 (32'h100188e8) -`define KV_REG_KEY_ENTRY_11_10 (32'h8e8) `define CLP_KV_REG_KEY_ENTRY_11_11 (32'h100188ec) -`define KV_REG_KEY_ENTRY_11_11 (32'h8ec) `define CLP_KV_REG_KEY_ENTRY_11_12 (32'h100188f0) -`define KV_REG_KEY_ENTRY_11_12 (32'h8f0) `define CLP_KV_REG_KEY_ENTRY_11_13 (32'h100188f4) -`define KV_REG_KEY_ENTRY_11_13 (32'h8f4) `define CLP_KV_REG_KEY_ENTRY_11_14 (32'h100188f8) -`define KV_REG_KEY_ENTRY_11_14 (32'h8f8) `define CLP_KV_REG_KEY_ENTRY_11_15 (32'h100188fc) -`define KV_REG_KEY_ENTRY_11_15 (32'h8fc) `define CLP_KV_REG_KEY_ENTRY_12_0 (32'h10018900) -`define KV_REG_KEY_ENTRY_12_0 (32'h900) `define CLP_KV_REG_KEY_ENTRY_12_1 (32'h10018904) -`define KV_REG_KEY_ENTRY_12_1 (32'h904) `define CLP_KV_REG_KEY_ENTRY_12_2 (32'h10018908) -`define KV_REG_KEY_ENTRY_12_2 (32'h908) `define CLP_KV_REG_KEY_ENTRY_12_3 (32'h1001890c) -`define KV_REG_KEY_ENTRY_12_3 (32'h90c) `define CLP_KV_REG_KEY_ENTRY_12_4 (32'h10018910) -`define KV_REG_KEY_ENTRY_12_4 (32'h910) `define CLP_KV_REG_KEY_ENTRY_12_5 (32'h10018914) -`define KV_REG_KEY_ENTRY_12_5 (32'h914) `define CLP_KV_REG_KEY_ENTRY_12_6 (32'h10018918) -`define KV_REG_KEY_ENTRY_12_6 (32'h918) `define CLP_KV_REG_KEY_ENTRY_12_7 (32'h1001891c) -`define KV_REG_KEY_ENTRY_12_7 (32'h91c) `define CLP_KV_REG_KEY_ENTRY_12_8 (32'h10018920) -`define KV_REG_KEY_ENTRY_12_8 (32'h920) `define CLP_KV_REG_KEY_ENTRY_12_9 (32'h10018924) -`define KV_REG_KEY_ENTRY_12_9 (32'h924) `define CLP_KV_REG_KEY_ENTRY_12_10 (32'h10018928) -`define KV_REG_KEY_ENTRY_12_10 (32'h928) `define CLP_KV_REG_KEY_ENTRY_12_11 (32'h1001892c) -`define KV_REG_KEY_ENTRY_12_11 (32'h92c) `define CLP_KV_REG_KEY_ENTRY_12_12 (32'h10018930) -`define KV_REG_KEY_ENTRY_12_12 (32'h930) `define CLP_KV_REG_KEY_ENTRY_12_13 (32'h10018934) -`define KV_REG_KEY_ENTRY_12_13 (32'h934) `define CLP_KV_REG_KEY_ENTRY_12_14 (32'h10018938) -`define KV_REG_KEY_ENTRY_12_14 (32'h938) `define CLP_KV_REG_KEY_ENTRY_12_15 (32'h1001893c) -`define KV_REG_KEY_ENTRY_12_15 (32'h93c) `define CLP_KV_REG_KEY_ENTRY_13_0 (32'h10018940) -`define KV_REG_KEY_ENTRY_13_0 (32'h940) `define CLP_KV_REG_KEY_ENTRY_13_1 (32'h10018944) -`define KV_REG_KEY_ENTRY_13_1 (32'h944) `define CLP_KV_REG_KEY_ENTRY_13_2 (32'h10018948) -`define KV_REG_KEY_ENTRY_13_2 (32'h948) `define CLP_KV_REG_KEY_ENTRY_13_3 (32'h1001894c) -`define KV_REG_KEY_ENTRY_13_3 (32'h94c) `define CLP_KV_REG_KEY_ENTRY_13_4 (32'h10018950) -`define KV_REG_KEY_ENTRY_13_4 (32'h950) `define CLP_KV_REG_KEY_ENTRY_13_5 (32'h10018954) -`define KV_REG_KEY_ENTRY_13_5 (32'h954) `define CLP_KV_REG_KEY_ENTRY_13_6 (32'h10018958) -`define KV_REG_KEY_ENTRY_13_6 (32'h958) `define CLP_KV_REG_KEY_ENTRY_13_7 (32'h1001895c) -`define KV_REG_KEY_ENTRY_13_7 (32'h95c) `define CLP_KV_REG_KEY_ENTRY_13_8 (32'h10018960) -`define KV_REG_KEY_ENTRY_13_8 (32'h960) `define CLP_KV_REG_KEY_ENTRY_13_9 (32'h10018964) -`define KV_REG_KEY_ENTRY_13_9 (32'h964) `define CLP_KV_REG_KEY_ENTRY_13_10 (32'h10018968) -`define KV_REG_KEY_ENTRY_13_10 (32'h968) `define CLP_KV_REG_KEY_ENTRY_13_11 (32'h1001896c) -`define KV_REG_KEY_ENTRY_13_11 (32'h96c) `define CLP_KV_REG_KEY_ENTRY_13_12 (32'h10018970) -`define KV_REG_KEY_ENTRY_13_12 (32'h970) `define CLP_KV_REG_KEY_ENTRY_13_13 (32'h10018974) -`define KV_REG_KEY_ENTRY_13_13 (32'h974) `define CLP_KV_REG_KEY_ENTRY_13_14 (32'h10018978) -`define KV_REG_KEY_ENTRY_13_14 (32'h978) `define CLP_KV_REG_KEY_ENTRY_13_15 (32'h1001897c) -`define KV_REG_KEY_ENTRY_13_15 (32'h97c) `define CLP_KV_REG_KEY_ENTRY_14_0 (32'h10018980) -`define KV_REG_KEY_ENTRY_14_0 (32'h980) `define CLP_KV_REG_KEY_ENTRY_14_1 (32'h10018984) -`define KV_REG_KEY_ENTRY_14_1 (32'h984) `define CLP_KV_REG_KEY_ENTRY_14_2 (32'h10018988) -`define KV_REG_KEY_ENTRY_14_2 (32'h988) `define CLP_KV_REG_KEY_ENTRY_14_3 (32'h1001898c) -`define KV_REG_KEY_ENTRY_14_3 (32'h98c) `define CLP_KV_REG_KEY_ENTRY_14_4 (32'h10018990) -`define KV_REG_KEY_ENTRY_14_4 (32'h990) `define CLP_KV_REG_KEY_ENTRY_14_5 (32'h10018994) -`define KV_REG_KEY_ENTRY_14_5 (32'h994) `define CLP_KV_REG_KEY_ENTRY_14_6 (32'h10018998) -`define KV_REG_KEY_ENTRY_14_6 (32'h998) `define CLP_KV_REG_KEY_ENTRY_14_7 (32'h1001899c) -`define KV_REG_KEY_ENTRY_14_7 (32'h99c) `define CLP_KV_REG_KEY_ENTRY_14_8 (32'h100189a0) -`define KV_REG_KEY_ENTRY_14_8 (32'h9a0) `define CLP_KV_REG_KEY_ENTRY_14_9 (32'h100189a4) -`define KV_REG_KEY_ENTRY_14_9 (32'h9a4) `define CLP_KV_REG_KEY_ENTRY_14_10 (32'h100189a8) -`define KV_REG_KEY_ENTRY_14_10 (32'h9a8) `define CLP_KV_REG_KEY_ENTRY_14_11 (32'h100189ac) -`define KV_REG_KEY_ENTRY_14_11 (32'h9ac) `define CLP_KV_REG_KEY_ENTRY_14_12 (32'h100189b0) -`define KV_REG_KEY_ENTRY_14_12 (32'h9b0) `define CLP_KV_REG_KEY_ENTRY_14_13 (32'h100189b4) -`define KV_REG_KEY_ENTRY_14_13 (32'h9b4) `define CLP_KV_REG_KEY_ENTRY_14_14 (32'h100189b8) -`define KV_REG_KEY_ENTRY_14_14 (32'h9b8) `define CLP_KV_REG_KEY_ENTRY_14_15 (32'h100189bc) -`define KV_REG_KEY_ENTRY_14_15 (32'h9bc) `define CLP_KV_REG_KEY_ENTRY_15_0 (32'h100189c0) -`define KV_REG_KEY_ENTRY_15_0 (32'h9c0) `define CLP_KV_REG_KEY_ENTRY_15_1 (32'h100189c4) -`define KV_REG_KEY_ENTRY_15_1 (32'h9c4) `define CLP_KV_REG_KEY_ENTRY_15_2 (32'h100189c8) -`define KV_REG_KEY_ENTRY_15_2 (32'h9c8) `define CLP_KV_REG_KEY_ENTRY_15_3 (32'h100189cc) -`define KV_REG_KEY_ENTRY_15_3 (32'h9cc) `define CLP_KV_REG_KEY_ENTRY_15_4 (32'h100189d0) -`define KV_REG_KEY_ENTRY_15_4 (32'h9d0) `define CLP_KV_REG_KEY_ENTRY_15_5 (32'h100189d4) -`define KV_REG_KEY_ENTRY_15_5 (32'h9d4) `define CLP_KV_REG_KEY_ENTRY_15_6 (32'h100189d8) -`define KV_REG_KEY_ENTRY_15_6 (32'h9d8) `define CLP_KV_REG_KEY_ENTRY_15_7 (32'h100189dc) -`define KV_REG_KEY_ENTRY_15_7 (32'h9dc) `define CLP_KV_REG_KEY_ENTRY_15_8 (32'h100189e0) -`define KV_REG_KEY_ENTRY_15_8 (32'h9e0) `define CLP_KV_REG_KEY_ENTRY_15_9 (32'h100189e4) -`define KV_REG_KEY_ENTRY_15_9 (32'h9e4) `define CLP_KV_REG_KEY_ENTRY_15_10 (32'h100189e8) -`define KV_REG_KEY_ENTRY_15_10 (32'h9e8) `define CLP_KV_REG_KEY_ENTRY_15_11 (32'h100189ec) -`define KV_REG_KEY_ENTRY_15_11 (32'h9ec) `define CLP_KV_REG_KEY_ENTRY_15_12 (32'h100189f0) -`define KV_REG_KEY_ENTRY_15_12 (32'h9f0) `define CLP_KV_REG_KEY_ENTRY_15_13 (32'h100189f4) -`define KV_REG_KEY_ENTRY_15_13 (32'h9f4) `define CLP_KV_REG_KEY_ENTRY_15_14 (32'h100189f8) -`define KV_REG_KEY_ENTRY_15_14 (32'h9f8) `define CLP_KV_REG_KEY_ENTRY_15_15 (32'h100189fc) -`define KV_REG_KEY_ENTRY_15_15 (32'h9fc) `define CLP_KV_REG_KEY_ENTRY_16_0 (32'h10018a00) -`define KV_REG_KEY_ENTRY_16_0 (32'ha00) `define CLP_KV_REG_KEY_ENTRY_16_1 (32'h10018a04) -`define KV_REG_KEY_ENTRY_16_1 (32'ha04) `define CLP_KV_REG_KEY_ENTRY_16_2 (32'h10018a08) -`define KV_REG_KEY_ENTRY_16_2 (32'ha08) `define CLP_KV_REG_KEY_ENTRY_16_3 (32'h10018a0c) -`define KV_REG_KEY_ENTRY_16_3 (32'ha0c) `define CLP_KV_REG_KEY_ENTRY_16_4 (32'h10018a10) -`define KV_REG_KEY_ENTRY_16_4 (32'ha10) `define CLP_KV_REG_KEY_ENTRY_16_5 (32'h10018a14) -`define KV_REG_KEY_ENTRY_16_5 (32'ha14) `define CLP_KV_REG_KEY_ENTRY_16_6 (32'h10018a18) -`define KV_REG_KEY_ENTRY_16_6 (32'ha18) `define CLP_KV_REG_KEY_ENTRY_16_7 (32'h10018a1c) -`define KV_REG_KEY_ENTRY_16_7 (32'ha1c) `define CLP_KV_REG_KEY_ENTRY_16_8 (32'h10018a20) -`define KV_REG_KEY_ENTRY_16_8 (32'ha20) `define CLP_KV_REG_KEY_ENTRY_16_9 (32'h10018a24) -`define KV_REG_KEY_ENTRY_16_9 (32'ha24) `define CLP_KV_REG_KEY_ENTRY_16_10 (32'h10018a28) -`define KV_REG_KEY_ENTRY_16_10 (32'ha28) `define CLP_KV_REG_KEY_ENTRY_16_11 (32'h10018a2c) -`define KV_REG_KEY_ENTRY_16_11 (32'ha2c) `define CLP_KV_REG_KEY_ENTRY_16_12 (32'h10018a30) -`define KV_REG_KEY_ENTRY_16_12 (32'ha30) `define CLP_KV_REG_KEY_ENTRY_16_13 (32'h10018a34) -`define KV_REG_KEY_ENTRY_16_13 (32'ha34) `define CLP_KV_REG_KEY_ENTRY_16_14 (32'h10018a38) -`define KV_REG_KEY_ENTRY_16_14 (32'ha38) `define CLP_KV_REG_KEY_ENTRY_16_15 (32'h10018a3c) -`define KV_REG_KEY_ENTRY_16_15 (32'ha3c) `define CLP_KV_REG_KEY_ENTRY_17_0 (32'h10018a40) -`define KV_REG_KEY_ENTRY_17_0 (32'ha40) `define CLP_KV_REG_KEY_ENTRY_17_1 (32'h10018a44) -`define KV_REG_KEY_ENTRY_17_1 (32'ha44) `define CLP_KV_REG_KEY_ENTRY_17_2 (32'h10018a48) -`define KV_REG_KEY_ENTRY_17_2 (32'ha48) `define CLP_KV_REG_KEY_ENTRY_17_3 (32'h10018a4c) -`define KV_REG_KEY_ENTRY_17_3 (32'ha4c) `define CLP_KV_REG_KEY_ENTRY_17_4 (32'h10018a50) -`define KV_REG_KEY_ENTRY_17_4 (32'ha50) `define CLP_KV_REG_KEY_ENTRY_17_5 (32'h10018a54) -`define KV_REG_KEY_ENTRY_17_5 (32'ha54) `define CLP_KV_REG_KEY_ENTRY_17_6 (32'h10018a58) -`define KV_REG_KEY_ENTRY_17_6 (32'ha58) `define CLP_KV_REG_KEY_ENTRY_17_7 (32'h10018a5c) -`define KV_REG_KEY_ENTRY_17_7 (32'ha5c) `define CLP_KV_REG_KEY_ENTRY_17_8 (32'h10018a60) -`define KV_REG_KEY_ENTRY_17_8 (32'ha60) `define CLP_KV_REG_KEY_ENTRY_17_9 (32'h10018a64) -`define KV_REG_KEY_ENTRY_17_9 (32'ha64) `define CLP_KV_REG_KEY_ENTRY_17_10 (32'h10018a68) -`define KV_REG_KEY_ENTRY_17_10 (32'ha68) `define CLP_KV_REG_KEY_ENTRY_17_11 (32'h10018a6c) -`define KV_REG_KEY_ENTRY_17_11 (32'ha6c) `define CLP_KV_REG_KEY_ENTRY_17_12 (32'h10018a70) -`define KV_REG_KEY_ENTRY_17_12 (32'ha70) `define CLP_KV_REG_KEY_ENTRY_17_13 (32'h10018a74) -`define KV_REG_KEY_ENTRY_17_13 (32'ha74) `define CLP_KV_REG_KEY_ENTRY_17_14 (32'h10018a78) -`define KV_REG_KEY_ENTRY_17_14 (32'ha78) `define CLP_KV_REG_KEY_ENTRY_17_15 (32'h10018a7c) -`define KV_REG_KEY_ENTRY_17_15 (32'ha7c) `define CLP_KV_REG_KEY_ENTRY_18_0 (32'h10018a80) -`define KV_REG_KEY_ENTRY_18_0 (32'ha80) `define CLP_KV_REG_KEY_ENTRY_18_1 (32'h10018a84) -`define KV_REG_KEY_ENTRY_18_1 (32'ha84) `define CLP_KV_REG_KEY_ENTRY_18_2 (32'h10018a88) -`define KV_REG_KEY_ENTRY_18_2 (32'ha88) `define CLP_KV_REG_KEY_ENTRY_18_3 (32'h10018a8c) -`define KV_REG_KEY_ENTRY_18_3 (32'ha8c) `define CLP_KV_REG_KEY_ENTRY_18_4 (32'h10018a90) -`define KV_REG_KEY_ENTRY_18_4 (32'ha90) `define CLP_KV_REG_KEY_ENTRY_18_5 (32'h10018a94) -`define KV_REG_KEY_ENTRY_18_5 (32'ha94) `define CLP_KV_REG_KEY_ENTRY_18_6 (32'h10018a98) -`define KV_REG_KEY_ENTRY_18_6 (32'ha98) `define CLP_KV_REG_KEY_ENTRY_18_7 (32'h10018a9c) -`define KV_REG_KEY_ENTRY_18_7 (32'ha9c) `define CLP_KV_REG_KEY_ENTRY_18_8 (32'h10018aa0) -`define KV_REG_KEY_ENTRY_18_8 (32'haa0) `define CLP_KV_REG_KEY_ENTRY_18_9 (32'h10018aa4) -`define KV_REG_KEY_ENTRY_18_9 (32'haa4) `define CLP_KV_REG_KEY_ENTRY_18_10 (32'h10018aa8) -`define KV_REG_KEY_ENTRY_18_10 (32'haa8) `define CLP_KV_REG_KEY_ENTRY_18_11 (32'h10018aac) -`define KV_REG_KEY_ENTRY_18_11 (32'haac) `define CLP_KV_REG_KEY_ENTRY_18_12 (32'h10018ab0) -`define KV_REG_KEY_ENTRY_18_12 (32'hab0) `define CLP_KV_REG_KEY_ENTRY_18_13 (32'h10018ab4) -`define KV_REG_KEY_ENTRY_18_13 (32'hab4) `define CLP_KV_REG_KEY_ENTRY_18_14 (32'h10018ab8) -`define KV_REG_KEY_ENTRY_18_14 (32'hab8) `define CLP_KV_REG_KEY_ENTRY_18_15 (32'h10018abc) -`define KV_REG_KEY_ENTRY_18_15 (32'habc) `define CLP_KV_REG_KEY_ENTRY_19_0 (32'h10018ac0) -`define KV_REG_KEY_ENTRY_19_0 (32'hac0) `define CLP_KV_REG_KEY_ENTRY_19_1 (32'h10018ac4) -`define KV_REG_KEY_ENTRY_19_1 (32'hac4) `define CLP_KV_REG_KEY_ENTRY_19_2 (32'h10018ac8) -`define KV_REG_KEY_ENTRY_19_2 (32'hac8) `define CLP_KV_REG_KEY_ENTRY_19_3 (32'h10018acc) -`define KV_REG_KEY_ENTRY_19_3 (32'hacc) `define CLP_KV_REG_KEY_ENTRY_19_4 (32'h10018ad0) -`define KV_REG_KEY_ENTRY_19_4 (32'had0) `define CLP_KV_REG_KEY_ENTRY_19_5 (32'h10018ad4) -`define KV_REG_KEY_ENTRY_19_5 (32'had4) `define CLP_KV_REG_KEY_ENTRY_19_6 (32'h10018ad8) -`define KV_REG_KEY_ENTRY_19_6 (32'had8) `define CLP_KV_REG_KEY_ENTRY_19_7 (32'h10018adc) -`define KV_REG_KEY_ENTRY_19_7 (32'hadc) `define CLP_KV_REG_KEY_ENTRY_19_8 (32'h10018ae0) -`define KV_REG_KEY_ENTRY_19_8 (32'hae0) `define CLP_KV_REG_KEY_ENTRY_19_9 (32'h10018ae4) -`define KV_REG_KEY_ENTRY_19_9 (32'hae4) `define CLP_KV_REG_KEY_ENTRY_19_10 (32'h10018ae8) -`define KV_REG_KEY_ENTRY_19_10 (32'hae8) `define CLP_KV_REG_KEY_ENTRY_19_11 (32'h10018aec) -`define KV_REG_KEY_ENTRY_19_11 (32'haec) `define CLP_KV_REG_KEY_ENTRY_19_12 (32'h10018af0) -`define KV_REG_KEY_ENTRY_19_12 (32'haf0) `define CLP_KV_REG_KEY_ENTRY_19_13 (32'h10018af4) -`define KV_REG_KEY_ENTRY_19_13 (32'haf4) `define CLP_KV_REG_KEY_ENTRY_19_14 (32'h10018af8) -`define KV_REG_KEY_ENTRY_19_14 (32'haf8) `define CLP_KV_REG_KEY_ENTRY_19_15 (32'h10018afc) -`define KV_REG_KEY_ENTRY_19_15 (32'hafc) `define CLP_KV_REG_KEY_ENTRY_20_0 (32'h10018b00) -`define KV_REG_KEY_ENTRY_20_0 (32'hb00) `define CLP_KV_REG_KEY_ENTRY_20_1 (32'h10018b04) -`define KV_REG_KEY_ENTRY_20_1 (32'hb04) `define CLP_KV_REG_KEY_ENTRY_20_2 (32'h10018b08) -`define KV_REG_KEY_ENTRY_20_2 (32'hb08) `define CLP_KV_REG_KEY_ENTRY_20_3 (32'h10018b0c) -`define KV_REG_KEY_ENTRY_20_3 (32'hb0c) `define CLP_KV_REG_KEY_ENTRY_20_4 (32'h10018b10) -`define KV_REG_KEY_ENTRY_20_4 (32'hb10) `define CLP_KV_REG_KEY_ENTRY_20_5 (32'h10018b14) -`define KV_REG_KEY_ENTRY_20_5 (32'hb14) `define CLP_KV_REG_KEY_ENTRY_20_6 (32'h10018b18) -`define KV_REG_KEY_ENTRY_20_6 (32'hb18) `define CLP_KV_REG_KEY_ENTRY_20_7 (32'h10018b1c) -`define KV_REG_KEY_ENTRY_20_7 (32'hb1c) `define CLP_KV_REG_KEY_ENTRY_20_8 (32'h10018b20) -`define KV_REG_KEY_ENTRY_20_8 (32'hb20) `define CLP_KV_REG_KEY_ENTRY_20_9 (32'h10018b24) -`define KV_REG_KEY_ENTRY_20_9 (32'hb24) `define CLP_KV_REG_KEY_ENTRY_20_10 (32'h10018b28) -`define KV_REG_KEY_ENTRY_20_10 (32'hb28) `define CLP_KV_REG_KEY_ENTRY_20_11 (32'h10018b2c) -`define KV_REG_KEY_ENTRY_20_11 (32'hb2c) `define CLP_KV_REG_KEY_ENTRY_20_12 (32'h10018b30) -`define KV_REG_KEY_ENTRY_20_12 (32'hb30) `define CLP_KV_REG_KEY_ENTRY_20_13 (32'h10018b34) -`define KV_REG_KEY_ENTRY_20_13 (32'hb34) `define CLP_KV_REG_KEY_ENTRY_20_14 (32'h10018b38) -`define KV_REG_KEY_ENTRY_20_14 (32'hb38) `define CLP_KV_REG_KEY_ENTRY_20_15 (32'h10018b3c) -`define KV_REG_KEY_ENTRY_20_15 (32'hb3c) `define CLP_KV_REG_KEY_ENTRY_21_0 (32'h10018b40) -`define KV_REG_KEY_ENTRY_21_0 (32'hb40) `define CLP_KV_REG_KEY_ENTRY_21_1 (32'h10018b44) -`define KV_REG_KEY_ENTRY_21_1 (32'hb44) `define CLP_KV_REG_KEY_ENTRY_21_2 (32'h10018b48) -`define KV_REG_KEY_ENTRY_21_2 (32'hb48) `define CLP_KV_REG_KEY_ENTRY_21_3 (32'h10018b4c) -`define KV_REG_KEY_ENTRY_21_3 (32'hb4c) `define CLP_KV_REG_KEY_ENTRY_21_4 (32'h10018b50) -`define KV_REG_KEY_ENTRY_21_4 (32'hb50) `define CLP_KV_REG_KEY_ENTRY_21_5 (32'h10018b54) -`define KV_REG_KEY_ENTRY_21_5 (32'hb54) `define CLP_KV_REG_KEY_ENTRY_21_6 (32'h10018b58) -`define KV_REG_KEY_ENTRY_21_6 (32'hb58) `define CLP_KV_REG_KEY_ENTRY_21_7 (32'h10018b5c) -`define KV_REG_KEY_ENTRY_21_7 (32'hb5c) `define CLP_KV_REG_KEY_ENTRY_21_8 (32'h10018b60) -`define KV_REG_KEY_ENTRY_21_8 (32'hb60) `define CLP_KV_REG_KEY_ENTRY_21_9 (32'h10018b64) -`define KV_REG_KEY_ENTRY_21_9 (32'hb64) `define CLP_KV_REG_KEY_ENTRY_21_10 (32'h10018b68) -`define KV_REG_KEY_ENTRY_21_10 (32'hb68) `define CLP_KV_REG_KEY_ENTRY_21_11 (32'h10018b6c) -`define KV_REG_KEY_ENTRY_21_11 (32'hb6c) `define CLP_KV_REG_KEY_ENTRY_21_12 (32'h10018b70) -`define KV_REG_KEY_ENTRY_21_12 (32'hb70) `define CLP_KV_REG_KEY_ENTRY_21_13 (32'h10018b74) -`define KV_REG_KEY_ENTRY_21_13 (32'hb74) `define CLP_KV_REG_KEY_ENTRY_21_14 (32'h10018b78) -`define KV_REG_KEY_ENTRY_21_14 (32'hb78) `define CLP_KV_REG_KEY_ENTRY_21_15 (32'h10018b7c) -`define KV_REG_KEY_ENTRY_21_15 (32'hb7c) `define CLP_KV_REG_KEY_ENTRY_22_0 (32'h10018b80) -`define KV_REG_KEY_ENTRY_22_0 (32'hb80) `define CLP_KV_REG_KEY_ENTRY_22_1 (32'h10018b84) -`define KV_REG_KEY_ENTRY_22_1 (32'hb84) `define CLP_KV_REG_KEY_ENTRY_22_2 (32'h10018b88) -`define KV_REG_KEY_ENTRY_22_2 (32'hb88) `define CLP_KV_REG_KEY_ENTRY_22_3 (32'h10018b8c) -`define KV_REG_KEY_ENTRY_22_3 (32'hb8c) `define CLP_KV_REG_KEY_ENTRY_22_4 (32'h10018b90) -`define KV_REG_KEY_ENTRY_22_4 (32'hb90) `define CLP_KV_REG_KEY_ENTRY_22_5 (32'h10018b94) -`define KV_REG_KEY_ENTRY_22_5 (32'hb94) `define CLP_KV_REG_KEY_ENTRY_22_6 (32'h10018b98) -`define KV_REG_KEY_ENTRY_22_6 (32'hb98) `define CLP_KV_REG_KEY_ENTRY_22_7 (32'h10018b9c) -`define KV_REG_KEY_ENTRY_22_7 (32'hb9c) `define CLP_KV_REG_KEY_ENTRY_22_8 (32'h10018ba0) -`define KV_REG_KEY_ENTRY_22_8 (32'hba0) `define CLP_KV_REG_KEY_ENTRY_22_9 (32'h10018ba4) -`define KV_REG_KEY_ENTRY_22_9 (32'hba4) `define CLP_KV_REG_KEY_ENTRY_22_10 (32'h10018ba8) -`define KV_REG_KEY_ENTRY_22_10 (32'hba8) `define CLP_KV_REG_KEY_ENTRY_22_11 (32'h10018bac) -`define KV_REG_KEY_ENTRY_22_11 (32'hbac) `define CLP_KV_REG_KEY_ENTRY_22_12 (32'h10018bb0) -`define KV_REG_KEY_ENTRY_22_12 (32'hbb0) `define CLP_KV_REG_KEY_ENTRY_22_13 (32'h10018bb4) -`define KV_REG_KEY_ENTRY_22_13 (32'hbb4) `define CLP_KV_REG_KEY_ENTRY_22_14 (32'h10018bb8) -`define KV_REG_KEY_ENTRY_22_14 (32'hbb8) `define CLP_KV_REG_KEY_ENTRY_22_15 (32'h10018bbc) -`define KV_REG_KEY_ENTRY_22_15 (32'hbbc) `define CLP_KV_REG_KEY_ENTRY_23_0 (32'h10018bc0) -`define KV_REG_KEY_ENTRY_23_0 (32'hbc0) `define CLP_KV_REG_KEY_ENTRY_23_1 (32'h10018bc4) -`define KV_REG_KEY_ENTRY_23_1 (32'hbc4) `define CLP_KV_REG_KEY_ENTRY_23_2 (32'h10018bc8) -`define KV_REG_KEY_ENTRY_23_2 (32'hbc8) `define CLP_KV_REG_KEY_ENTRY_23_3 (32'h10018bcc) -`define KV_REG_KEY_ENTRY_23_3 (32'hbcc) `define CLP_KV_REG_KEY_ENTRY_23_4 (32'h10018bd0) -`define KV_REG_KEY_ENTRY_23_4 (32'hbd0) `define CLP_KV_REG_KEY_ENTRY_23_5 (32'h10018bd4) -`define KV_REG_KEY_ENTRY_23_5 (32'hbd4) `define CLP_KV_REG_KEY_ENTRY_23_6 (32'h10018bd8) -`define KV_REG_KEY_ENTRY_23_6 (32'hbd8) `define CLP_KV_REG_KEY_ENTRY_23_7 (32'h10018bdc) -`define KV_REG_KEY_ENTRY_23_7 (32'hbdc) `define CLP_KV_REG_KEY_ENTRY_23_8 (32'h10018be0) -`define KV_REG_KEY_ENTRY_23_8 (32'hbe0) `define CLP_KV_REG_KEY_ENTRY_23_9 (32'h10018be4) -`define KV_REG_KEY_ENTRY_23_9 (32'hbe4) `define CLP_KV_REG_KEY_ENTRY_23_10 (32'h10018be8) -`define KV_REG_KEY_ENTRY_23_10 (32'hbe8) `define CLP_KV_REG_KEY_ENTRY_23_11 (32'h10018bec) -`define KV_REG_KEY_ENTRY_23_11 (32'hbec) `define CLP_KV_REG_KEY_ENTRY_23_12 (32'h10018bf0) -`define KV_REG_KEY_ENTRY_23_12 (32'hbf0) `define CLP_KV_REG_KEY_ENTRY_23_13 (32'h10018bf4) -`define KV_REG_KEY_ENTRY_23_13 (32'hbf4) `define CLP_KV_REG_KEY_ENTRY_23_14 (32'h10018bf8) -`define KV_REG_KEY_ENTRY_23_14 (32'hbf8) `define CLP_KV_REG_KEY_ENTRY_23_15 (32'h10018bfc) -`define KV_REG_KEY_ENTRY_23_15 (32'hbfc) `define CLP_KV_REG_CLEAR_SECRETS (32'h10018c00) -`define KV_REG_CLEAR_SECRETS (32'hc00) -`define KV_REG_CLEAR_SECRETS_WR_DEBUG_VALUES_LOW (0) -`define KV_REG_CLEAR_SECRETS_WR_DEBUG_VALUES_MASK (32'h1) -`define KV_REG_CLEAR_SECRETS_SEL_DEBUG_VALUE_LOW (1) -`define KV_REG_CLEAR_SECRETS_SEL_DEBUG_VALUE_MASK (32'h2) `define CLP_PV_REG_BASE_ADDR (32'h1001a000) `define CLP_PV_REG_PCR_CTRL_0 (32'h1001a000) -`define PV_REG_PCR_CTRL_0 (32'h0) -`define PV_REG_PCR_CTRL_0_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_0_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_0_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_0_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_0_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_0_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_0_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_0_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_1 (32'h1001a004) -`define PV_REG_PCR_CTRL_1 (32'h4) -`define PV_REG_PCR_CTRL_1_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_1_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_1_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_1_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_1_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_1_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_1_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_1_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_2 (32'h1001a008) -`define PV_REG_PCR_CTRL_2 (32'h8) -`define PV_REG_PCR_CTRL_2_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_2_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_2_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_2_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_2_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_2_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_2_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_2_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_3 (32'h1001a00c) -`define PV_REG_PCR_CTRL_3 (32'hc) -`define PV_REG_PCR_CTRL_3_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_3_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_3_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_3_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_3_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_3_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_3_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_3_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_4 (32'h1001a010) -`define PV_REG_PCR_CTRL_4 (32'h10) -`define PV_REG_PCR_CTRL_4_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_4_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_4_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_4_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_4_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_4_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_4_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_4_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_5 (32'h1001a014) -`define PV_REG_PCR_CTRL_5 (32'h14) -`define PV_REG_PCR_CTRL_5_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_5_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_5_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_5_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_5_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_5_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_5_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_5_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_6 (32'h1001a018) -`define PV_REG_PCR_CTRL_6 (32'h18) -`define PV_REG_PCR_CTRL_6_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_6_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_6_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_6_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_6_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_6_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_6_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_6_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_7 (32'h1001a01c) -`define PV_REG_PCR_CTRL_7 (32'h1c) -`define PV_REG_PCR_CTRL_7_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_7_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_7_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_7_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_7_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_7_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_7_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_7_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_8 (32'h1001a020) -`define PV_REG_PCR_CTRL_8 (32'h20) -`define PV_REG_PCR_CTRL_8_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_8_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_8_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_8_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_8_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_8_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_8_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_8_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_9 (32'h1001a024) -`define PV_REG_PCR_CTRL_9 (32'h24) -`define PV_REG_PCR_CTRL_9_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_9_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_9_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_9_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_9_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_9_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_9_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_9_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_10 (32'h1001a028) -`define PV_REG_PCR_CTRL_10 (32'h28) -`define PV_REG_PCR_CTRL_10_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_10_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_10_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_10_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_10_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_10_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_10_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_10_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_11 (32'h1001a02c) -`define PV_REG_PCR_CTRL_11 (32'h2c) -`define PV_REG_PCR_CTRL_11_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_11_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_11_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_11_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_11_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_11_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_11_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_11_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_12 (32'h1001a030) -`define PV_REG_PCR_CTRL_12 (32'h30) -`define PV_REG_PCR_CTRL_12_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_12_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_12_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_12_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_12_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_12_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_12_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_12_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_13 (32'h1001a034) -`define PV_REG_PCR_CTRL_13 (32'h34) -`define PV_REG_PCR_CTRL_13_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_13_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_13_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_13_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_13_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_13_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_13_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_13_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_14 (32'h1001a038) -`define PV_REG_PCR_CTRL_14 (32'h38) -`define PV_REG_PCR_CTRL_14_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_14_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_14_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_14_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_14_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_14_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_14_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_14_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_15 (32'h1001a03c) -`define PV_REG_PCR_CTRL_15 (32'h3c) -`define PV_REG_PCR_CTRL_15_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_15_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_15_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_15_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_15_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_15_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_15_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_15_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_16 (32'h1001a040) -`define PV_REG_PCR_CTRL_16 (32'h40) -`define PV_REG_PCR_CTRL_16_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_16_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_16_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_16_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_16_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_16_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_16_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_16_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_17 (32'h1001a044) -`define PV_REG_PCR_CTRL_17 (32'h44) -`define PV_REG_PCR_CTRL_17_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_17_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_17_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_17_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_17_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_17_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_17_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_17_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_18 (32'h1001a048) -`define PV_REG_PCR_CTRL_18 (32'h48) -`define PV_REG_PCR_CTRL_18_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_18_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_18_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_18_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_18_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_18_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_18_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_18_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_19 (32'h1001a04c) -`define PV_REG_PCR_CTRL_19 (32'h4c) -`define PV_REG_PCR_CTRL_19_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_19_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_19_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_19_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_19_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_19_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_19_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_19_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_20 (32'h1001a050) -`define PV_REG_PCR_CTRL_20 (32'h50) -`define PV_REG_PCR_CTRL_20_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_20_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_20_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_20_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_20_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_20_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_20_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_20_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_21 (32'h1001a054) -`define PV_REG_PCR_CTRL_21 (32'h54) -`define PV_REG_PCR_CTRL_21_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_21_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_21_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_21_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_21_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_21_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_21_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_21_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_22 (32'h1001a058) -`define PV_REG_PCR_CTRL_22 (32'h58) -`define PV_REG_PCR_CTRL_22_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_22_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_22_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_22_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_22_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_22_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_22_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_22_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_23 (32'h1001a05c) -`define PV_REG_PCR_CTRL_23 (32'h5c) -`define PV_REG_PCR_CTRL_23_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_23_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_23_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_23_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_23_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_23_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_23_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_23_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_24 (32'h1001a060) -`define PV_REG_PCR_CTRL_24 (32'h60) -`define PV_REG_PCR_CTRL_24_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_24_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_24_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_24_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_24_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_24_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_24_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_24_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_25 (32'h1001a064) -`define PV_REG_PCR_CTRL_25 (32'h64) -`define PV_REG_PCR_CTRL_25_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_25_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_25_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_25_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_25_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_25_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_25_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_25_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_26 (32'h1001a068) -`define PV_REG_PCR_CTRL_26 (32'h68) -`define PV_REG_PCR_CTRL_26_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_26_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_26_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_26_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_26_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_26_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_26_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_26_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_27 (32'h1001a06c) -`define PV_REG_PCR_CTRL_27 (32'h6c) -`define PV_REG_PCR_CTRL_27_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_27_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_27_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_27_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_27_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_27_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_27_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_27_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_28 (32'h1001a070) -`define PV_REG_PCR_CTRL_28 (32'h70) -`define PV_REG_PCR_CTRL_28_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_28_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_28_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_28_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_28_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_28_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_28_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_28_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_29 (32'h1001a074) -`define PV_REG_PCR_CTRL_29 (32'h74) -`define PV_REG_PCR_CTRL_29_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_29_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_29_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_29_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_29_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_29_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_29_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_29_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_30 (32'h1001a078) -`define PV_REG_PCR_CTRL_30 (32'h78) -`define PV_REG_PCR_CTRL_30_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_30_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_30_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_30_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_30_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_30_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_30_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_30_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_CTRL_31 (32'h1001a07c) -`define PV_REG_PCR_CTRL_31 (32'h7c) -`define PV_REG_PCR_CTRL_31_LOCK_LOW (0) -`define PV_REG_PCR_CTRL_31_LOCK_MASK (32'h1) -`define PV_REG_PCR_CTRL_31_CLEAR_LOW (1) -`define PV_REG_PCR_CTRL_31_CLEAR_MASK (32'h2) -`define PV_REG_PCR_CTRL_31_RSVD0_LOW (2) -`define PV_REG_PCR_CTRL_31_RSVD0_MASK (32'h4) -`define PV_REG_PCR_CTRL_31_RSVD1_LOW (3) -`define PV_REG_PCR_CTRL_31_RSVD1_MASK (32'hf8) `define CLP_PV_REG_PCR_ENTRY_0_0 (32'h1001a600) -`define PV_REG_PCR_ENTRY_0_0 (32'h600) `define CLP_PV_REG_PCR_ENTRY_0_1 (32'h1001a604) -`define PV_REG_PCR_ENTRY_0_1 (32'h604) `define CLP_PV_REG_PCR_ENTRY_0_2 (32'h1001a608) -`define PV_REG_PCR_ENTRY_0_2 (32'h608) `define CLP_PV_REG_PCR_ENTRY_0_3 (32'h1001a60c) -`define PV_REG_PCR_ENTRY_0_3 (32'h60c) `define CLP_PV_REG_PCR_ENTRY_0_4 (32'h1001a610) -`define PV_REG_PCR_ENTRY_0_4 (32'h610) `define CLP_PV_REG_PCR_ENTRY_0_5 (32'h1001a614) -`define PV_REG_PCR_ENTRY_0_5 (32'h614) `define CLP_PV_REG_PCR_ENTRY_0_6 (32'h1001a618) -`define PV_REG_PCR_ENTRY_0_6 (32'h618) `define CLP_PV_REG_PCR_ENTRY_0_7 (32'h1001a61c) -`define PV_REG_PCR_ENTRY_0_7 (32'h61c) `define CLP_PV_REG_PCR_ENTRY_0_8 (32'h1001a620) -`define PV_REG_PCR_ENTRY_0_8 (32'h620) `define CLP_PV_REG_PCR_ENTRY_0_9 (32'h1001a624) -`define PV_REG_PCR_ENTRY_0_9 (32'h624) `define CLP_PV_REG_PCR_ENTRY_0_10 (32'h1001a628) -`define PV_REG_PCR_ENTRY_0_10 (32'h628) `define CLP_PV_REG_PCR_ENTRY_0_11 (32'h1001a62c) -`define PV_REG_PCR_ENTRY_0_11 (32'h62c) `define CLP_PV_REG_PCR_ENTRY_1_0 (32'h1001a630) -`define PV_REG_PCR_ENTRY_1_0 (32'h630) `define CLP_PV_REG_PCR_ENTRY_1_1 (32'h1001a634) -`define PV_REG_PCR_ENTRY_1_1 (32'h634) `define CLP_PV_REG_PCR_ENTRY_1_2 (32'h1001a638) -`define PV_REG_PCR_ENTRY_1_2 (32'h638) `define CLP_PV_REG_PCR_ENTRY_1_3 (32'h1001a63c) -`define PV_REG_PCR_ENTRY_1_3 (32'h63c) `define CLP_PV_REG_PCR_ENTRY_1_4 (32'h1001a640) -`define PV_REG_PCR_ENTRY_1_4 (32'h640) `define CLP_PV_REG_PCR_ENTRY_1_5 (32'h1001a644) -`define PV_REG_PCR_ENTRY_1_5 (32'h644) `define CLP_PV_REG_PCR_ENTRY_1_6 (32'h1001a648) -`define PV_REG_PCR_ENTRY_1_6 (32'h648) `define CLP_PV_REG_PCR_ENTRY_1_7 (32'h1001a64c) -`define PV_REG_PCR_ENTRY_1_7 (32'h64c) `define CLP_PV_REG_PCR_ENTRY_1_8 (32'h1001a650) -`define PV_REG_PCR_ENTRY_1_8 (32'h650) `define CLP_PV_REG_PCR_ENTRY_1_9 (32'h1001a654) -`define PV_REG_PCR_ENTRY_1_9 (32'h654) `define CLP_PV_REG_PCR_ENTRY_1_10 (32'h1001a658) -`define PV_REG_PCR_ENTRY_1_10 (32'h658) `define CLP_PV_REG_PCR_ENTRY_1_11 (32'h1001a65c) -`define PV_REG_PCR_ENTRY_1_11 (32'h65c) `define CLP_PV_REG_PCR_ENTRY_2_0 (32'h1001a660) -`define PV_REG_PCR_ENTRY_2_0 (32'h660) `define CLP_PV_REG_PCR_ENTRY_2_1 (32'h1001a664) -`define PV_REG_PCR_ENTRY_2_1 (32'h664) `define CLP_PV_REG_PCR_ENTRY_2_2 (32'h1001a668) -`define PV_REG_PCR_ENTRY_2_2 (32'h668) `define CLP_PV_REG_PCR_ENTRY_2_3 (32'h1001a66c) -`define PV_REG_PCR_ENTRY_2_3 (32'h66c) `define CLP_PV_REG_PCR_ENTRY_2_4 (32'h1001a670) -`define PV_REG_PCR_ENTRY_2_4 (32'h670) `define CLP_PV_REG_PCR_ENTRY_2_5 (32'h1001a674) -`define PV_REG_PCR_ENTRY_2_5 (32'h674) `define CLP_PV_REG_PCR_ENTRY_2_6 (32'h1001a678) -`define PV_REG_PCR_ENTRY_2_6 (32'h678) `define CLP_PV_REG_PCR_ENTRY_2_7 (32'h1001a67c) -`define PV_REG_PCR_ENTRY_2_7 (32'h67c) `define CLP_PV_REG_PCR_ENTRY_2_8 (32'h1001a680) -`define PV_REG_PCR_ENTRY_2_8 (32'h680) `define CLP_PV_REG_PCR_ENTRY_2_9 (32'h1001a684) -`define PV_REG_PCR_ENTRY_2_9 (32'h684) `define CLP_PV_REG_PCR_ENTRY_2_10 (32'h1001a688) -`define PV_REG_PCR_ENTRY_2_10 (32'h688) `define CLP_PV_REG_PCR_ENTRY_2_11 (32'h1001a68c) -`define PV_REG_PCR_ENTRY_2_11 (32'h68c) `define CLP_PV_REG_PCR_ENTRY_3_0 (32'h1001a690) -`define PV_REG_PCR_ENTRY_3_0 (32'h690) `define CLP_PV_REG_PCR_ENTRY_3_1 (32'h1001a694) -`define PV_REG_PCR_ENTRY_3_1 (32'h694) `define CLP_PV_REG_PCR_ENTRY_3_2 (32'h1001a698) -`define PV_REG_PCR_ENTRY_3_2 (32'h698) `define CLP_PV_REG_PCR_ENTRY_3_3 (32'h1001a69c) -`define PV_REG_PCR_ENTRY_3_3 (32'h69c) `define CLP_PV_REG_PCR_ENTRY_3_4 (32'h1001a6a0) -`define PV_REG_PCR_ENTRY_3_4 (32'h6a0) `define CLP_PV_REG_PCR_ENTRY_3_5 (32'h1001a6a4) -`define PV_REG_PCR_ENTRY_3_5 (32'h6a4) `define CLP_PV_REG_PCR_ENTRY_3_6 (32'h1001a6a8) -`define PV_REG_PCR_ENTRY_3_6 (32'h6a8) `define CLP_PV_REG_PCR_ENTRY_3_7 (32'h1001a6ac) -`define PV_REG_PCR_ENTRY_3_7 (32'h6ac) `define CLP_PV_REG_PCR_ENTRY_3_8 (32'h1001a6b0) -`define PV_REG_PCR_ENTRY_3_8 (32'h6b0) `define CLP_PV_REG_PCR_ENTRY_3_9 (32'h1001a6b4) -`define PV_REG_PCR_ENTRY_3_9 (32'h6b4) `define CLP_PV_REG_PCR_ENTRY_3_10 (32'h1001a6b8) -`define PV_REG_PCR_ENTRY_3_10 (32'h6b8) `define CLP_PV_REG_PCR_ENTRY_3_11 (32'h1001a6bc) -`define PV_REG_PCR_ENTRY_3_11 (32'h6bc) `define CLP_PV_REG_PCR_ENTRY_4_0 (32'h1001a6c0) -`define PV_REG_PCR_ENTRY_4_0 (32'h6c0) `define CLP_PV_REG_PCR_ENTRY_4_1 (32'h1001a6c4) -`define PV_REG_PCR_ENTRY_4_1 (32'h6c4) `define CLP_PV_REG_PCR_ENTRY_4_2 (32'h1001a6c8) -`define PV_REG_PCR_ENTRY_4_2 (32'h6c8) `define CLP_PV_REG_PCR_ENTRY_4_3 (32'h1001a6cc) -`define PV_REG_PCR_ENTRY_4_3 (32'h6cc) `define CLP_PV_REG_PCR_ENTRY_4_4 (32'h1001a6d0) -`define PV_REG_PCR_ENTRY_4_4 (32'h6d0) `define CLP_PV_REG_PCR_ENTRY_4_5 (32'h1001a6d4) -`define PV_REG_PCR_ENTRY_4_5 (32'h6d4) `define CLP_PV_REG_PCR_ENTRY_4_6 (32'h1001a6d8) -`define PV_REG_PCR_ENTRY_4_6 (32'h6d8) `define CLP_PV_REG_PCR_ENTRY_4_7 (32'h1001a6dc) -`define PV_REG_PCR_ENTRY_4_7 (32'h6dc) `define CLP_PV_REG_PCR_ENTRY_4_8 (32'h1001a6e0) -`define PV_REG_PCR_ENTRY_4_8 (32'h6e0) `define CLP_PV_REG_PCR_ENTRY_4_9 (32'h1001a6e4) -`define PV_REG_PCR_ENTRY_4_9 (32'h6e4) `define CLP_PV_REG_PCR_ENTRY_4_10 (32'h1001a6e8) -`define PV_REG_PCR_ENTRY_4_10 (32'h6e8) `define CLP_PV_REG_PCR_ENTRY_4_11 (32'h1001a6ec) -`define PV_REG_PCR_ENTRY_4_11 (32'h6ec) `define CLP_PV_REG_PCR_ENTRY_5_0 (32'h1001a6f0) -`define PV_REG_PCR_ENTRY_5_0 (32'h6f0) `define CLP_PV_REG_PCR_ENTRY_5_1 (32'h1001a6f4) -`define PV_REG_PCR_ENTRY_5_1 (32'h6f4) `define CLP_PV_REG_PCR_ENTRY_5_2 (32'h1001a6f8) -`define PV_REG_PCR_ENTRY_5_2 (32'h6f8) `define CLP_PV_REG_PCR_ENTRY_5_3 (32'h1001a6fc) -`define PV_REG_PCR_ENTRY_5_3 (32'h6fc) `define CLP_PV_REG_PCR_ENTRY_5_4 (32'h1001a700) -`define PV_REG_PCR_ENTRY_5_4 (32'h700) `define CLP_PV_REG_PCR_ENTRY_5_5 (32'h1001a704) -`define PV_REG_PCR_ENTRY_5_5 (32'h704) `define CLP_PV_REG_PCR_ENTRY_5_6 (32'h1001a708) -`define PV_REG_PCR_ENTRY_5_6 (32'h708) `define CLP_PV_REG_PCR_ENTRY_5_7 (32'h1001a70c) -`define PV_REG_PCR_ENTRY_5_7 (32'h70c) `define CLP_PV_REG_PCR_ENTRY_5_8 (32'h1001a710) -`define PV_REG_PCR_ENTRY_5_8 (32'h710) `define CLP_PV_REG_PCR_ENTRY_5_9 (32'h1001a714) -`define PV_REG_PCR_ENTRY_5_9 (32'h714) `define CLP_PV_REG_PCR_ENTRY_5_10 (32'h1001a718) -`define PV_REG_PCR_ENTRY_5_10 (32'h718) `define CLP_PV_REG_PCR_ENTRY_5_11 (32'h1001a71c) -`define PV_REG_PCR_ENTRY_5_11 (32'h71c) `define CLP_PV_REG_PCR_ENTRY_6_0 (32'h1001a720) -`define PV_REG_PCR_ENTRY_6_0 (32'h720) `define CLP_PV_REG_PCR_ENTRY_6_1 (32'h1001a724) -`define PV_REG_PCR_ENTRY_6_1 (32'h724) `define CLP_PV_REG_PCR_ENTRY_6_2 (32'h1001a728) -`define PV_REG_PCR_ENTRY_6_2 (32'h728) `define CLP_PV_REG_PCR_ENTRY_6_3 (32'h1001a72c) -`define PV_REG_PCR_ENTRY_6_3 (32'h72c) `define CLP_PV_REG_PCR_ENTRY_6_4 (32'h1001a730) -`define PV_REG_PCR_ENTRY_6_4 (32'h730) `define CLP_PV_REG_PCR_ENTRY_6_5 (32'h1001a734) -`define PV_REG_PCR_ENTRY_6_5 (32'h734) `define CLP_PV_REG_PCR_ENTRY_6_6 (32'h1001a738) -`define PV_REG_PCR_ENTRY_6_6 (32'h738) `define CLP_PV_REG_PCR_ENTRY_6_7 (32'h1001a73c) -`define PV_REG_PCR_ENTRY_6_7 (32'h73c) `define CLP_PV_REG_PCR_ENTRY_6_8 (32'h1001a740) -`define PV_REG_PCR_ENTRY_6_8 (32'h740) `define CLP_PV_REG_PCR_ENTRY_6_9 (32'h1001a744) -`define PV_REG_PCR_ENTRY_6_9 (32'h744) `define CLP_PV_REG_PCR_ENTRY_6_10 (32'h1001a748) -`define PV_REG_PCR_ENTRY_6_10 (32'h748) `define CLP_PV_REG_PCR_ENTRY_6_11 (32'h1001a74c) -`define PV_REG_PCR_ENTRY_6_11 (32'h74c) `define CLP_PV_REG_PCR_ENTRY_7_0 (32'h1001a750) -`define PV_REG_PCR_ENTRY_7_0 (32'h750) `define CLP_PV_REG_PCR_ENTRY_7_1 (32'h1001a754) -`define PV_REG_PCR_ENTRY_7_1 (32'h754) `define CLP_PV_REG_PCR_ENTRY_7_2 (32'h1001a758) -`define PV_REG_PCR_ENTRY_7_2 (32'h758) `define CLP_PV_REG_PCR_ENTRY_7_3 (32'h1001a75c) -`define PV_REG_PCR_ENTRY_7_3 (32'h75c) `define CLP_PV_REG_PCR_ENTRY_7_4 (32'h1001a760) -`define PV_REG_PCR_ENTRY_7_4 (32'h760) `define CLP_PV_REG_PCR_ENTRY_7_5 (32'h1001a764) -`define PV_REG_PCR_ENTRY_7_5 (32'h764) `define CLP_PV_REG_PCR_ENTRY_7_6 (32'h1001a768) -`define PV_REG_PCR_ENTRY_7_6 (32'h768) `define CLP_PV_REG_PCR_ENTRY_7_7 (32'h1001a76c) -`define PV_REG_PCR_ENTRY_7_7 (32'h76c) `define CLP_PV_REG_PCR_ENTRY_7_8 (32'h1001a770) -`define PV_REG_PCR_ENTRY_7_8 (32'h770) `define CLP_PV_REG_PCR_ENTRY_7_9 (32'h1001a774) -`define PV_REG_PCR_ENTRY_7_9 (32'h774) `define CLP_PV_REG_PCR_ENTRY_7_10 (32'h1001a778) -`define PV_REG_PCR_ENTRY_7_10 (32'h778) `define CLP_PV_REG_PCR_ENTRY_7_11 (32'h1001a77c) -`define PV_REG_PCR_ENTRY_7_11 (32'h77c) `define CLP_PV_REG_PCR_ENTRY_8_0 (32'h1001a780) -`define PV_REG_PCR_ENTRY_8_0 (32'h780) `define CLP_PV_REG_PCR_ENTRY_8_1 (32'h1001a784) -`define PV_REG_PCR_ENTRY_8_1 (32'h784) `define CLP_PV_REG_PCR_ENTRY_8_2 (32'h1001a788) -`define PV_REG_PCR_ENTRY_8_2 (32'h788) `define CLP_PV_REG_PCR_ENTRY_8_3 (32'h1001a78c) -`define PV_REG_PCR_ENTRY_8_3 (32'h78c) `define CLP_PV_REG_PCR_ENTRY_8_4 (32'h1001a790) -`define PV_REG_PCR_ENTRY_8_4 (32'h790) `define CLP_PV_REG_PCR_ENTRY_8_5 (32'h1001a794) -`define PV_REG_PCR_ENTRY_8_5 (32'h794) `define CLP_PV_REG_PCR_ENTRY_8_6 (32'h1001a798) -`define PV_REG_PCR_ENTRY_8_6 (32'h798) `define CLP_PV_REG_PCR_ENTRY_8_7 (32'h1001a79c) -`define PV_REG_PCR_ENTRY_8_7 (32'h79c) `define CLP_PV_REG_PCR_ENTRY_8_8 (32'h1001a7a0) -`define PV_REG_PCR_ENTRY_8_8 (32'h7a0) `define CLP_PV_REG_PCR_ENTRY_8_9 (32'h1001a7a4) -`define PV_REG_PCR_ENTRY_8_9 (32'h7a4) `define CLP_PV_REG_PCR_ENTRY_8_10 (32'h1001a7a8) -`define PV_REG_PCR_ENTRY_8_10 (32'h7a8) `define CLP_PV_REG_PCR_ENTRY_8_11 (32'h1001a7ac) -`define PV_REG_PCR_ENTRY_8_11 (32'h7ac) `define CLP_PV_REG_PCR_ENTRY_9_0 (32'h1001a7b0) -`define PV_REG_PCR_ENTRY_9_0 (32'h7b0) `define CLP_PV_REG_PCR_ENTRY_9_1 (32'h1001a7b4) -`define PV_REG_PCR_ENTRY_9_1 (32'h7b4) `define CLP_PV_REG_PCR_ENTRY_9_2 (32'h1001a7b8) -`define PV_REG_PCR_ENTRY_9_2 (32'h7b8) `define CLP_PV_REG_PCR_ENTRY_9_3 (32'h1001a7bc) -`define PV_REG_PCR_ENTRY_9_3 (32'h7bc) `define CLP_PV_REG_PCR_ENTRY_9_4 (32'h1001a7c0) -`define PV_REG_PCR_ENTRY_9_4 (32'h7c0) `define CLP_PV_REG_PCR_ENTRY_9_5 (32'h1001a7c4) -`define PV_REG_PCR_ENTRY_9_5 (32'h7c4) `define CLP_PV_REG_PCR_ENTRY_9_6 (32'h1001a7c8) -`define PV_REG_PCR_ENTRY_9_6 (32'h7c8) `define CLP_PV_REG_PCR_ENTRY_9_7 (32'h1001a7cc) -`define PV_REG_PCR_ENTRY_9_7 (32'h7cc) `define CLP_PV_REG_PCR_ENTRY_9_8 (32'h1001a7d0) -`define PV_REG_PCR_ENTRY_9_8 (32'h7d0) `define CLP_PV_REG_PCR_ENTRY_9_9 (32'h1001a7d4) -`define PV_REG_PCR_ENTRY_9_9 (32'h7d4) `define CLP_PV_REG_PCR_ENTRY_9_10 (32'h1001a7d8) -`define PV_REG_PCR_ENTRY_9_10 (32'h7d8) `define CLP_PV_REG_PCR_ENTRY_9_11 (32'h1001a7dc) -`define PV_REG_PCR_ENTRY_9_11 (32'h7dc) `define CLP_PV_REG_PCR_ENTRY_10_0 (32'h1001a7e0) -`define PV_REG_PCR_ENTRY_10_0 (32'h7e0) `define CLP_PV_REG_PCR_ENTRY_10_1 (32'h1001a7e4) -`define PV_REG_PCR_ENTRY_10_1 (32'h7e4) `define CLP_PV_REG_PCR_ENTRY_10_2 (32'h1001a7e8) -`define PV_REG_PCR_ENTRY_10_2 (32'h7e8) `define CLP_PV_REG_PCR_ENTRY_10_3 (32'h1001a7ec) -`define PV_REG_PCR_ENTRY_10_3 (32'h7ec) `define CLP_PV_REG_PCR_ENTRY_10_4 (32'h1001a7f0) -`define PV_REG_PCR_ENTRY_10_4 (32'h7f0) `define CLP_PV_REG_PCR_ENTRY_10_5 (32'h1001a7f4) -`define PV_REG_PCR_ENTRY_10_5 (32'h7f4) `define CLP_PV_REG_PCR_ENTRY_10_6 (32'h1001a7f8) -`define PV_REG_PCR_ENTRY_10_6 (32'h7f8) `define CLP_PV_REG_PCR_ENTRY_10_7 (32'h1001a7fc) -`define PV_REG_PCR_ENTRY_10_7 (32'h7fc) `define CLP_PV_REG_PCR_ENTRY_10_8 (32'h1001a800) -`define PV_REG_PCR_ENTRY_10_8 (32'h800) `define CLP_PV_REG_PCR_ENTRY_10_9 (32'h1001a804) -`define PV_REG_PCR_ENTRY_10_9 (32'h804) `define CLP_PV_REG_PCR_ENTRY_10_10 (32'h1001a808) -`define PV_REG_PCR_ENTRY_10_10 (32'h808) `define CLP_PV_REG_PCR_ENTRY_10_11 (32'h1001a80c) -`define PV_REG_PCR_ENTRY_10_11 (32'h80c) `define CLP_PV_REG_PCR_ENTRY_11_0 (32'h1001a810) -`define PV_REG_PCR_ENTRY_11_0 (32'h810) `define CLP_PV_REG_PCR_ENTRY_11_1 (32'h1001a814) -`define PV_REG_PCR_ENTRY_11_1 (32'h814) `define CLP_PV_REG_PCR_ENTRY_11_2 (32'h1001a818) -`define PV_REG_PCR_ENTRY_11_2 (32'h818) `define CLP_PV_REG_PCR_ENTRY_11_3 (32'h1001a81c) -`define PV_REG_PCR_ENTRY_11_3 (32'h81c) `define CLP_PV_REG_PCR_ENTRY_11_4 (32'h1001a820) -`define PV_REG_PCR_ENTRY_11_4 (32'h820) `define CLP_PV_REG_PCR_ENTRY_11_5 (32'h1001a824) -`define PV_REG_PCR_ENTRY_11_5 (32'h824) `define CLP_PV_REG_PCR_ENTRY_11_6 (32'h1001a828) -`define PV_REG_PCR_ENTRY_11_6 (32'h828) `define CLP_PV_REG_PCR_ENTRY_11_7 (32'h1001a82c) -`define PV_REG_PCR_ENTRY_11_7 (32'h82c) `define CLP_PV_REG_PCR_ENTRY_11_8 (32'h1001a830) -`define PV_REG_PCR_ENTRY_11_8 (32'h830) `define CLP_PV_REG_PCR_ENTRY_11_9 (32'h1001a834) -`define PV_REG_PCR_ENTRY_11_9 (32'h834) `define CLP_PV_REG_PCR_ENTRY_11_10 (32'h1001a838) -`define PV_REG_PCR_ENTRY_11_10 (32'h838) `define CLP_PV_REG_PCR_ENTRY_11_11 (32'h1001a83c) -`define PV_REG_PCR_ENTRY_11_11 (32'h83c) `define CLP_PV_REG_PCR_ENTRY_12_0 (32'h1001a840) -`define PV_REG_PCR_ENTRY_12_0 (32'h840) `define CLP_PV_REG_PCR_ENTRY_12_1 (32'h1001a844) -`define PV_REG_PCR_ENTRY_12_1 (32'h844) `define CLP_PV_REG_PCR_ENTRY_12_2 (32'h1001a848) -`define PV_REG_PCR_ENTRY_12_2 (32'h848) `define CLP_PV_REG_PCR_ENTRY_12_3 (32'h1001a84c) -`define PV_REG_PCR_ENTRY_12_3 (32'h84c) `define CLP_PV_REG_PCR_ENTRY_12_4 (32'h1001a850) -`define PV_REG_PCR_ENTRY_12_4 (32'h850) `define CLP_PV_REG_PCR_ENTRY_12_5 (32'h1001a854) -`define PV_REG_PCR_ENTRY_12_5 (32'h854) `define CLP_PV_REG_PCR_ENTRY_12_6 (32'h1001a858) -`define PV_REG_PCR_ENTRY_12_6 (32'h858) `define CLP_PV_REG_PCR_ENTRY_12_7 (32'h1001a85c) -`define PV_REG_PCR_ENTRY_12_7 (32'h85c) `define CLP_PV_REG_PCR_ENTRY_12_8 (32'h1001a860) -`define PV_REG_PCR_ENTRY_12_8 (32'h860) `define CLP_PV_REG_PCR_ENTRY_12_9 (32'h1001a864) -`define PV_REG_PCR_ENTRY_12_9 (32'h864) `define CLP_PV_REG_PCR_ENTRY_12_10 (32'h1001a868) -`define PV_REG_PCR_ENTRY_12_10 (32'h868) `define CLP_PV_REG_PCR_ENTRY_12_11 (32'h1001a86c) -`define PV_REG_PCR_ENTRY_12_11 (32'h86c) `define CLP_PV_REG_PCR_ENTRY_13_0 (32'h1001a870) -`define PV_REG_PCR_ENTRY_13_0 (32'h870) `define CLP_PV_REG_PCR_ENTRY_13_1 (32'h1001a874) -`define PV_REG_PCR_ENTRY_13_1 (32'h874) `define CLP_PV_REG_PCR_ENTRY_13_2 (32'h1001a878) -`define PV_REG_PCR_ENTRY_13_2 (32'h878) `define CLP_PV_REG_PCR_ENTRY_13_3 (32'h1001a87c) -`define PV_REG_PCR_ENTRY_13_3 (32'h87c) `define CLP_PV_REG_PCR_ENTRY_13_4 (32'h1001a880) -`define PV_REG_PCR_ENTRY_13_4 (32'h880) `define CLP_PV_REG_PCR_ENTRY_13_5 (32'h1001a884) -`define PV_REG_PCR_ENTRY_13_5 (32'h884) `define CLP_PV_REG_PCR_ENTRY_13_6 (32'h1001a888) -`define PV_REG_PCR_ENTRY_13_6 (32'h888) `define CLP_PV_REG_PCR_ENTRY_13_7 (32'h1001a88c) -`define PV_REG_PCR_ENTRY_13_7 (32'h88c) `define CLP_PV_REG_PCR_ENTRY_13_8 (32'h1001a890) -`define PV_REG_PCR_ENTRY_13_8 (32'h890) `define CLP_PV_REG_PCR_ENTRY_13_9 (32'h1001a894) -`define PV_REG_PCR_ENTRY_13_9 (32'h894) `define CLP_PV_REG_PCR_ENTRY_13_10 (32'h1001a898) -`define PV_REG_PCR_ENTRY_13_10 (32'h898) `define CLP_PV_REG_PCR_ENTRY_13_11 (32'h1001a89c) -`define PV_REG_PCR_ENTRY_13_11 (32'h89c) `define CLP_PV_REG_PCR_ENTRY_14_0 (32'h1001a8a0) -`define PV_REG_PCR_ENTRY_14_0 (32'h8a0) `define CLP_PV_REG_PCR_ENTRY_14_1 (32'h1001a8a4) -`define PV_REG_PCR_ENTRY_14_1 (32'h8a4) `define CLP_PV_REG_PCR_ENTRY_14_2 (32'h1001a8a8) -`define PV_REG_PCR_ENTRY_14_2 (32'h8a8) `define CLP_PV_REG_PCR_ENTRY_14_3 (32'h1001a8ac) -`define PV_REG_PCR_ENTRY_14_3 (32'h8ac) `define CLP_PV_REG_PCR_ENTRY_14_4 (32'h1001a8b0) -`define PV_REG_PCR_ENTRY_14_4 (32'h8b0) `define CLP_PV_REG_PCR_ENTRY_14_5 (32'h1001a8b4) -`define PV_REG_PCR_ENTRY_14_5 (32'h8b4) `define CLP_PV_REG_PCR_ENTRY_14_6 (32'h1001a8b8) -`define PV_REG_PCR_ENTRY_14_6 (32'h8b8) `define CLP_PV_REG_PCR_ENTRY_14_7 (32'h1001a8bc) -`define PV_REG_PCR_ENTRY_14_7 (32'h8bc) `define CLP_PV_REG_PCR_ENTRY_14_8 (32'h1001a8c0) -`define PV_REG_PCR_ENTRY_14_8 (32'h8c0) `define CLP_PV_REG_PCR_ENTRY_14_9 (32'h1001a8c4) -`define PV_REG_PCR_ENTRY_14_9 (32'h8c4) `define CLP_PV_REG_PCR_ENTRY_14_10 (32'h1001a8c8) -`define PV_REG_PCR_ENTRY_14_10 (32'h8c8) `define CLP_PV_REG_PCR_ENTRY_14_11 (32'h1001a8cc) -`define PV_REG_PCR_ENTRY_14_11 (32'h8cc) `define CLP_PV_REG_PCR_ENTRY_15_0 (32'h1001a8d0) -`define PV_REG_PCR_ENTRY_15_0 (32'h8d0) `define CLP_PV_REG_PCR_ENTRY_15_1 (32'h1001a8d4) -`define PV_REG_PCR_ENTRY_15_1 (32'h8d4) `define CLP_PV_REG_PCR_ENTRY_15_2 (32'h1001a8d8) -`define PV_REG_PCR_ENTRY_15_2 (32'h8d8) `define CLP_PV_REG_PCR_ENTRY_15_3 (32'h1001a8dc) -`define PV_REG_PCR_ENTRY_15_3 (32'h8dc) `define CLP_PV_REG_PCR_ENTRY_15_4 (32'h1001a8e0) -`define PV_REG_PCR_ENTRY_15_4 (32'h8e0) `define CLP_PV_REG_PCR_ENTRY_15_5 (32'h1001a8e4) -`define PV_REG_PCR_ENTRY_15_5 (32'h8e4) `define CLP_PV_REG_PCR_ENTRY_15_6 (32'h1001a8e8) -`define PV_REG_PCR_ENTRY_15_6 (32'h8e8) `define CLP_PV_REG_PCR_ENTRY_15_7 (32'h1001a8ec) -`define PV_REG_PCR_ENTRY_15_7 (32'h8ec) `define CLP_PV_REG_PCR_ENTRY_15_8 (32'h1001a8f0) -`define PV_REG_PCR_ENTRY_15_8 (32'h8f0) `define CLP_PV_REG_PCR_ENTRY_15_9 (32'h1001a8f4) -`define PV_REG_PCR_ENTRY_15_9 (32'h8f4) `define CLP_PV_REG_PCR_ENTRY_15_10 (32'h1001a8f8) -`define PV_REG_PCR_ENTRY_15_10 (32'h8f8) `define CLP_PV_REG_PCR_ENTRY_15_11 (32'h1001a8fc) -`define PV_REG_PCR_ENTRY_15_11 (32'h8fc) `define CLP_PV_REG_PCR_ENTRY_16_0 (32'h1001a900) -`define PV_REG_PCR_ENTRY_16_0 (32'h900) `define CLP_PV_REG_PCR_ENTRY_16_1 (32'h1001a904) -`define PV_REG_PCR_ENTRY_16_1 (32'h904) `define CLP_PV_REG_PCR_ENTRY_16_2 (32'h1001a908) -`define PV_REG_PCR_ENTRY_16_2 (32'h908) `define CLP_PV_REG_PCR_ENTRY_16_3 (32'h1001a90c) -`define PV_REG_PCR_ENTRY_16_3 (32'h90c) `define CLP_PV_REG_PCR_ENTRY_16_4 (32'h1001a910) -`define PV_REG_PCR_ENTRY_16_4 (32'h910) `define CLP_PV_REG_PCR_ENTRY_16_5 (32'h1001a914) -`define PV_REG_PCR_ENTRY_16_5 (32'h914) `define CLP_PV_REG_PCR_ENTRY_16_6 (32'h1001a918) -`define PV_REG_PCR_ENTRY_16_6 (32'h918) `define CLP_PV_REG_PCR_ENTRY_16_7 (32'h1001a91c) -`define PV_REG_PCR_ENTRY_16_7 (32'h91c) `define CLP_PV_REG_PCR_ENTRY_16_8 (32'h1001a920) -`define PV_REG_PCR_ENTRY_16_8 (32'h920) `define CLP_PV_REG_PCR_ENTRY_16_9 (32'h1001a924) -`define PV_REG_PCR_ENTRY_16_9 (32'h924) `define CLP_PV_REG_PCR_ENTRY_16_10 (32'h1001a928) -`define PV_REG_PCR_ENTRY_16_10 (32'h928) `define CLP_PV_REG_PCR_ENTRY_16_11 (32'h1001a92c) -`define PV_REG_PCR_ENTRY_16_11 (32'h92c) `define CLP_PV_REG_PCR_ENTRY_17_0 (32'h1001a930) -`define PV_REG_PCR_ENTRY_17_0 (32'h930) `define CLP_PV_REG_PCR_ENTRY_17_1 (32'h1001a934) -`define PV_REG_PCR_ENTRY_17_1 (32'h934) `define CLP_PV_REG_PCR_ENTRY_17_2 (32'h1001a938) -`define PV_REG_PCR_ENTRY_17_2 (32'h938) `define CLP_PV_REG_PCR_ENTRY_17_3 (32'h1001a93c) -`define PV_REG_PCR_ENTRY_17_3 (32'h93c) `define CLP_PV_REG_PCR_ENTRY_17_4 (32'h1001a940) -`define PV_REG_PCR_ENTRY_17_4 (32'h940) `define CLP_PV_REG_PCR_ENTRY_17_5 (32'h1001a944) -`define PV_REG_PCR_ENTRY_17_5 (32'h944) `define CLP_PV_REG_PCR_ENTRY_17_6 (32'h1001a948) -`define PV_REG_PCR_ENTRY_17_6 (32'h948) `define CLP_PV_REG_PCR_ENTRY_17_7 (32'h1001a94c) -`define PV_REG_PCR_ENTRY_17_7 (32'h94c) `define CLP_PV_REG_PCR_ENTRY_17_8 (32'h1001a950) -`define PV_REG_PCR_ENTRY_17_8 (32'h950) `define CLP_PV_REG_PCR_ENTRY_17_9 (32'h1001a954) -`define PV_REG_PCR_ENTRY_17_9 (32'h954) `define CLP_PV_REG_PCR_ENTRY_17_10 (32'h1001a958) -`define PV_REG_PCR_ENTRY_17_10 (32'h958) `define CLP_PV_REG_PCR_ENTRY_17_11 (32'h1001a95c) -`define PV_REG_PCR_ENTRY_17_11 (32'h95c) `define CLP_PV_REG_PCR_ENTRY_18_0 (32'h1001a960) -`define PV_REG_PCR_ENTRY_18_0 (32'h960) `define CLP_PV_REG_PCR_ENTRY_18_1 (32'h1001a964) -`define PV_REG_PCR_ENTRY_18_1 (32'h964) `define CLP_PV_REG_PCR_ENTRY_18_2 (32'h1001a968) -`define PV_REG_PCR_ENTRY_18_2 (32'h968) `define CLP_PV_REG_PCR_ENTRY_18_3 (32'h1001a96c) -`define PV_REG_PCR_ENTRY_18_3 (32'h96c) `define CLP_PV_REG_PCR_ENTRY_18_4 (32'h1001a970) -`define PV_REG_PCR_ENTRY_18_4 (32'h970) `define CLP_PV_REG_PCR_ENTRY_18_5 (32'h1001a974) -`define PV_REG_PCR_ENTRY_18_5 (32'h974) `define CLP_PV_REG_PCR_ENTRY_18_6 (32'h1001a978) -`define PV_REG_PCR_ENTRY_18_6 (32'h978) `define CLP_PV_REG_PCR_ENTRY_18_7 (32'h1001a97c) -`define PV_REG_PCR_ENTRY_18_7 (32'h97c) `define CLP_PV_REG_PCR_ENTRY_18_8 (32'h1001a980) -`define PV_REG_PCR_ENTRY_18_8 (32'h980) `define CLP_PV_REG_PCR_ENTRY_18_9 (32'h1001a984) -`define PV_REG_PCR_ENTRY_18_9 (32'h984) `define CLP_PV_REG_PCR_ENTRY_18_10 (32'h1001a988) -`define PV_REG_PCR_ENTRY_18_10 (32'h988) `define CLP_PV_REG_PCR_ENTRY_18_11 (32'h1001a98c) -`define PV_REG_PCR_ENTRY_18_11 (32'h98c) `define CLP_PV_REG_PCR_ENTRY_19_0 (32'h1001a990) -`define PV_REG_PCR_ENTRY_19_0 (32'h990) `define CLP_PV_REG_PCR_ENTRY_19_1 (32'h1001a994) -`define PV_REG_PCR_ENTRY_19_1 (32'h994) `define CLP_PV_REG_PCR_ENTRY_19_2 (32'h1001a998) -`define PV_REG_PCR_ENTRY_19_2 (32'h998) `define CLP_PV_REG_PCR_ENTRY_19_3 (32'h1001a99c) -`define PV_REG_PCR_ENTRY_19_3 (32'h99c) `define CLP_PV_REG_PCR_ENTRY_19_4 (32'h1001a9a0) -`define PV_REG_PCR_ENTRY_19_4 (32'h9a0) `define CLP_PV_REG_PCR_ENTRY_19_5 (32'h1001a9a4) -`define PV_REG_PCR_ENTRY_19_5 (32'h9a4) `define CLP_PV_REG_PCR_ENTRY_19_6 (32'h1001a9a8) -`define PV_REG_PCR_ENTRY_19_6 (32'h9a8) `define CLP_PV_REG_PCR_ENTRY_19_7 (32'h1001a9ac) -`define PV_REG_PCR_ENTRY_19_7 (32'h9ac) `define CLP_PV_REG_PCR_ENTRY_19_8 (32'h1001a9b0) -`define PV_REG_PCR_ENTRY_19_8 (32'h9b0) `define CLP_PV_REG_PCR_ENTRY_19_9 (32'h1001a9b4) -`define PV_REG_PCR_ENTRY_19_9 (32'h9b4) `define CLP_PV_REG_PCR_ENTRY_19_10 (32'h1001a9b8) -`define PV_REG_PCR_ENTRY_19_10 (32'h9b8) `define CLP_PV_REG_PCR_ENTRY_19_11 (32'h1001a9bc) -`define PV_REG_PCR_ENTRY_19_11 (32'h9bc) `define CLP_PV_REG_PCR_ENTRY_20_0 (32'h1001a9c0) -`define PV_REG_PCR_ENTRY_20_0 (32'h9c0) `define CLP_PV_REG_PCR_ENTRY_20_1 (32'h1001a9c4) -`define PV_REG_PCR_ENTRY_20_1 (32'h9c4) `define CLP_PV_REG_PCR_ENTRY_20_2 (32'h1001a9c8) -`define PV_REG_PCR_ENTRY_20_2 (32'h9c8) `define CLP_PV_REG_PCR_ENTRY_20_3 (32'h1001a9cc) -`define PV_REG_PCR_ENTRY_20_3 (32'h9cc) `define CLP_PV_REG_PCR_ENTRY_20_4 (32'h1001a9d0) -`define PV_REG_PCR_ENTRY_20_4 (32'h9d0) `define CLP_PV_REG_PCR_ENTRY_20_5 (32'h1001a9d4) -`define PV_REG_PCR_ENTRY_20_5 (32'h9d4) `define CLP_PV_REG_PCR_ENTRY_20_6 (32'h1001a9d8) -`define PV_REG_PCR_ENTRY_20_6 (32'h9d8) `define CLP_PV_REG_PCR_ENTRY_20_7 (32'h1001a9dc) -`define PV_REG_PCR_ENTRY_20_7 (32'h9dc) `define CLP_PV_REG_PCR_ENTRY_20_8 (32'h1001a9e0) -`define PV_REG_PCR_ENTRY_20_8 (32'h9e0) `define CLP_PV_REG_PCR_ENTRY_20_9 (32'h1001a9e4) -`define PV_REG_PCR_ENTRY_20_9 (32'h9e4) `define CLP_PV_REG_PCR_ENTRY_20_10 (32'h1001a9e8) -`define PV_REG_PCR_ENTRY_20_10 (32'h9e8) `define CLP_PV_REG_PCR_ENTRY_20_11 (32'h1001a9ec) -`define PV_REG_PCR_ENTRY_20_11 (32'h9ec) `define CLP_PV_REG_PCR_ENTRY_21_0 (32'h1001a9f0) -`define PV_REG_PCR_ENTRY_21_0 (32'h9f0) `define CLP_PV_REG_PCR_ENTRY_21_1 (32'h1001a9f4) -`define PV_REG_PCR_ENTRY_21_1 (32'h9f4) `define CLP_PV_REG_PCR_ENTRY_21_2 (32'h1001a9f8) -`define PV_REG_PCR_ENTRY_21_2 (32'h9f8) `define CLP_PV_REG_PCR_ENTRY_21_3 (32'h1001a9fc) -`define PV_REG_PCR_ENTRY_21_3 (32'h9fc) `define CLP_PV_REG_PCR_ENTRY_21_4 (32'h1001aa00) -`define PV_REG_PCR_ENTRY_21_4 (32'ha00) `define CLP_PV_REG_PCR_ENTRY_21_5 (32'h1001aa04) -`define PV_REG_PCR_ENTRY_21_5 (32'ha04) `define CLP_PV_REG_PCR_ENTRY_21_6 (32'h1001aa08) -`define PV_REG_PCR_ENTRY_21_6 (32'ha08) `define CLP_PV_REG_PCR_ENTRY_21_7 (32'h1001aa0c) -`define PV_REG_PCR_ENTRY_21_7 (32'ha0c) `define CLP_PV_REG_PCR_ENTRY_21_8 (32'h1001aa10) -`define PV_REG_PCR_ENTRY_21_8 (32'ha10) `define CLP_PV_REG_PCR_ENTRY_21_9 (32'h1001aa14) -`define PV_REG_PCR_ENTRY_21_9 (32'ha14) `define CLP_PV_REG_PCR_ENTRY_21_10 (32'h1001aa18) -`define PV_REG_PCR_ENTRY_21_10 (32'ha18) `define CLP_PV_REG_PCR_ENTRY_21_11 (32'h1001aa1c) -`define PV_REG_PCR_ENTRY_21_11 (32'ha1c) `define CLP_PV_REG_PCR_ENTRY_22_0 (32'h1001aa20) -`define PV_REG_PCR_ENTRY_22_0 (32'ha20) `define CLP_PV_REG_PCR_ENTRY_22_1 (32'h1001aa24) -`define PV_REG_PCR_ENTRY_22_1 (32'ha24) `define CLP_PV_REG_PCR_ENTRY_22_2 (32'h1001aa28) -`define PV_REG_PCR_ENTRY_22_2 (32'ha28) `define CLP_PV_REG_PCR_ENTRY_22_3 (32'h1001aa2c) -`define PV_REG_PCR_ENTRY_22_3 (32'ha2c) `define CLP_PV_REG_PCR_ENTRY_22_4 (32'h1001aa30) -`define PV_REG_PCR_ENTRY_22_4 (32'ha30) `define CLP_PV_REG_PCR_ENTRY_22_5 (32'h1001aa34) -`define PV_REG_PCR_ENTRY_22_5 (32'ha34) `define CLP_PV_REG_PCR_ENTRY_22_6 (32'h1001aa38) -`define PV_REG_PCR_ENTRY_22_6 (32'ha38) `define CLP_PV_REG_PCR_ENTRY_22_7 (32'h1001aa3c) -`define PV_REG_PCR_ENTRY_22_7 (32'ha3c) `define CLP_PV_REG_PCR_ENTRY_22_8 (32'h1001aa40) -`define PV_REG_PCR_ENTRY_22_8 (32'ha40) `define CLP_PV_REG_PCR_ENTRY_22_9 (32'h1001aa44) -`define PV_REG_PCR_ENTRY_22_9 (32'ha44) `define CLP_PV_REG_PCR_ENTRY_22_10 (32'h1001aa48) -`define PV_REG_PCR_ENTRY_22_10 (32'ha48) `define CLP_PV_REG_PCR_ENTRY_22_11 (32'h1001aa4c) -`define PV_REG_PCR_ENTRY_22_11 (32'ha4c) `define CLP_PV_REG_PCR_ENTRY_23_0 (32'h1001aa50) -`define PV_REG_PCR_ENTRY_23_0 (32'ha50) `define CLP_PV_REG_PCR_ENTRY_23_1 (32'h1001aa54) -`define PV_REG_PCR_ENTRY_23_1 (32'ha54) `define CLP_PV_REG_PCR_ENTRY_23_2 (32'h1001aa58) -`define PV_REG_PCR_ENTRY_23_2 (32'ha58) `define CLP_PV_REG_PCR_ENTRY_23_3 (32'h1001aa5c) -`define PV_REG_PCR_ENTRY_23_3 (32'ha5c) `define CLP_PV_REG_PCR_ENTRY_23_4 (32'h1001aa60) -`define PV_REG_PCR_ENTRY_23_4 (32'ha60) `define CLP_PV_REG_PCR_ENTRY_23_5 (32'h1001aa64) -`define PV_REG_PCR_ENTRY_23_5 (32'ha64) `define CLP_PV_REG_PCR_ENTRY_23_6 (32'h1001aa68) -`define PV_REG_PCR_ENTRY_23_6 (32'ha68) `define CLP_PV_REG_PCR_ENTRY_23_7 (32'h1001aa6c) -`define PV_REG_PCR_ENTRY_23_7 (32'ha6c) `define CLP_PV_REG_PCR_ENTRY_23_8 (32'h1001aa70) -`define PV_REG_PCR_ENTRY_23_8 (32'ha70) `define CLP_PV_REG_PCR_ENTRY_23_9 (32'h1001aa74) -`define PV_REG_PCR_ENTRY_23_9 (32'ha74) `define CLP_PV_REG_PCR_ENTRY_23_10 (32'h1001aa78) -`define PV_REG_PCR_ENTRY_23_10 (32'ha78) `define CLP_PV_REG_PCR_ENTRY_23_11 (32'h1001aa7c) -`define PV_REG_PCR_ENTRY_23_11 (32'ha7c) `define CLP_PV_REG_PCR_ENTRY_24_0 (32'h1001aa80) -`define PV_REG_PCR_ENTRY_24_0 (32'ha80) `define CLP_PV_REG_PCR_ENTRY_24_1 (32'h1001aa84) -`define PV_REG_PCR_ENTRY_24_1 (32'ha84) `define CLP_PV_REG_PCR_ENTRY_24_2 (32'h1001aa88) -`define PV_REG_PCR_ENTRY_24_2 (32'ha88) `define CLP_PV_REG_PCR_ENTRY_24_3 (32'h1001aa8c) -`define PV_REG_PCR_ENTRY_24_3 (32'ha8c) `define CLP_PV_REG_PCR_ENTRY_24_4 (32'h1001aa90) -`define PV_REG_PCR_ENTRY_24_4 (32'ha90) `define CLP_PV_REG_PCR_ENTRY_24_5 (32'h1001aa94) -`define PV_REG_PCR_ENTRY_24_5 (32'ha94) `define CLP_PV_REG_PCR_ENTRY_24_6 (32'h1001aa98) -`define PV_REG_PCR_ENTRY_24_6 (32'ha98) `define CLP_PV_REG_PCR_ENTRY_24_7 (32'h1001aa9c) -`define PV_REG_PCR_ENTRY_24_7 (32'ha9c) `define CLP_PV_REG_PCR_ENTRY_24_8 (32'h1001aaa0) -`define PV_REG_PCR_ENTRY_24_8 (32'haa0) `define CLP_PV_REG_PCR_ENTRY_24_9 (32'h1001aaa4) -`define PV_REG_PCR_ENTRY_24_9 (32'haa4) `define CLP_PV_REG_PCR_ENTRY_24_10 (32'h1001aaa8) -`define PV_REG_PCR_ENTRY_24_10 (32'haa8) `define CLP_PV_REG_PCR_ENTRY_24_11 (32'h1001aaac) -`define PV_REG_PCR_ENTRY_24_11 (32'haac) `define CLP_PV_REG_PCR_ENTRY_25_0 (32'h1001aab0) -`define PV_REG_PCR_ENTRY_25_0 (32'hab0) `define CLP_PV_REG_PCR_ENTRY_25_1 (32'h1001aab4) -`define PV_REG_PCR_ENTRY_25_1 (32'hab4) `define CLP_PV_REG_PCR_ENTRY_25_2 (32'h1001aab8) -`define PV_REG_PCR_ENTRY_25_2 (32'hab8) `define CLP_PV_REG_PCR_ENTRY_25_3 (32'h1001aabc) -`define PV_REG_PCR_ENTRY_25_3 (32'habc) `define CLP_PV_REG_PCR_ENTRY_25_4 (32'h1001aac0) -`define PV_REG_PCR_ENTRY_25_4 (32'hac0) `define CLP_PV_REG_PCR_ENTRY_25_5 (32'h1001aac4) -`define PV_REG_PCR_ENTRY_25_5 (32'hac4) `define CLP_PV_REG_PCR_ENTRY_25_6 (32'h1001aac8) -`define PV_REG_PCR_ENTRY_25_6 (32'hac8) `define CLP_PV_REG_PCR_ENTRY_25_7 (32'h1001aacc) -`define PV_REG_PCR_ENTRY_25_7 (32'hacc) `define CLP_PV_REG_PCR_ENTRY_25_8 (32'h1001aad0) -`define PV_REG_PCR_ENTRY_25_8 (32'had0) `define CLP_PV_REG_PCR_ENTRY_25_9 (32'h1001aad4) -`define PV_REG_PCR_ENTRY_25_9 (32'had4) `define CLP_PV_REG_PCR_ENTRY_25_10 (32'h1001aad8) -`define PV_REG_PCR_ENTRY_25_10 (32'had8) `define CLP_PV_REG_PCR_ENTRY_25_11 (32'h1001aadc) -`define PV_REG_PCR_ENTRY_25_11 (32'hadc) `define CLP_PV_REG_PCR_ENTRY_26_0 (32'h1001aae0) -`define PV_REG_PCR_ENTRY_26_0 (32'hae0) `define CLP_PV_REG_PCR_ENTRY_26_1 (32'h1001aae4) -`define PV_REG_PCR_ENTRY_26_1 (32'hae4) `define CLP_PV_REG_PCR_ENTRY_26_2 (32'h1001aae8) -`define PV_REG_PCR_ENTRY_26_2 (32'hae8) `define CLP_PV_REG_PCR_ENTRY_26_3 (32'h1001aaec) -`define PV_REG_PCR_ENTRY_26_3 (32'haec) `define CLP_PV_REG_PCR_ENTRY_26_4 (32'h1001aaf0) -`define PV_REG_PCR_ENTRY_26_4 (32'haf0) `define CLP_PV_REG_PCR_ENTRY_26_5 (32'h1001aaf4) -`define PV_REG_PCR_ENTRY_26_5 (32'haf4) `define CLP_PV_REG_PCR_ENTRY_26_6 (32'h1001aaf8) -`define PV_REG_PCR_ENTRY_26_6 (32'haf8) `define CLP_PV_REG_PCR_ENTRY_26_7 (32'h1001aafc) -`define PV_REG_PCR_ENTRY_26_7 (32'hafc) `define CLP_PV_REG_PCR_ENTRY_26_8 (32'h1001ab00) -`define PV_REG_PCR_ENTRY_26_8 (32'hb00) `define CLP_PV_REG_PCR_ENTRY_26_9 (32'h1001ab04) -`define PV_REG_PCR_ENTRY_26_9 (32'hb04) `define CLP_PV_REG_PCR_ENTRY_26_10 (32'h1001ab08) -`define PV_REG_PCR_ENTRY_26_10 (32'hb08) `define CLP_PV_REG_PCR_ENTRY_26_11 (32'h1001ab0c) -`define PV_REG_PCR_ENTRY_26_11 (32'hb0c) `define CLP_PV_REG_PCR_ENTRY_27_0 (32'h1001ab10) -`define PV_REG_PCR_ENTRY_27_0 (32'hb10) `define CLP_PV_REG_PCR_ENTRY_27_1 (32'h1001ab14) -`define PV_REG_PCR_ENTRY_27_1 (32'hb14) `define CLP_PV_REG_PCR_ENTRY_27_2 (32'h1001ab18) -`define PV_REG_PCR_ENTRY_27_2 (32'hb18) `define CLP_PV_REG_PCR_ENTRY_27_3 (32'h1001ab1c) -`define PV_REG_PCR_ENTRY_27_3 (32'hb1c) `define CLP_PV_REG_PCR_ENTRY_27_4 (32'h1001ab20) -`define PV_REG_PCR_ENTRY_27_4 (32'hb20) `define CLP_PV_REG_PCR_ENTRY_27_5 (32'h1001ab24) -`define PV_REG_PCR_ENTRY_27_5 (32'hb24) `define CLP_PV_REG_PCR_ENTRY_27_6 (32'h1001ab28) -`define PV_REG_PCR_ENTRY_27_6 (32'hb28) `define CLP_PV_REG_PCR_ENTRY_27_7 (32'h1001ab2c) -`define PV_REG_PCR_ENTRY_27_7 (32'hb2c) `define CLP_PV_REG_PCR_ENTRY_27_8 (32'h1001ab30) -`define PV_REG_PCR_ENTRY_27_8 (32'hb30) `define CLP_PV_REG_PCR_ENTRY_27_9 (32'h1001ab34) -`define PV_REG_PCR_ENTRY_27_9 (32'hb34) `define CLP_PV_REG_PCR_ENTRY_27_10 (32'h1001ab38) -`define PV_REG_PCR_ENTRY_27_10 (32'hb38) `define CLP_PV_REG_PCR_ENTRY_27_11 (32'h1001ab3c) -`define PV_REG_PCR_ENTRY_27_11 (32'hb3c) `define CLP_PV_REG_PCR_ENTRY_28_0 (32'h1001ab40) -`define PV_REG_PCR_ENTRY_28_0 (32'hb40) `define CLP_PV_REG_PCR_ENTRY_28_1 (32'h1001ab44) -`define PV_REG_PCR_ENTRY_28_1 (32'hb44) `define CLP_PV_REG_PCR_ENTRY_28_2 (32'h1001ab48) -`define PV_REG_PCR_ENTRY_28_2 (32'hb48) `define CLP_PV_REG_PCR_ENTRY_28_3 (32'h1001ab4c) -`define PV_REG_PCR_ENTRY_28_3 (32'hb4c) `define CLP_PV_REG_PCR_ENTRY_28_4 (32'h1001ab50) -`define PV_REG_PCR_ENTRY_28_4 (32'hb50) `define CLP_PV_REG_PCR_ENTRY_28_5 (32'h1001ab54) -`define PV_REG_PCR_ENTRY_28_5 (32'hb54) `define CLP_PV_REG_PCR_ENTRY_28_6 (32'h1001ab58) -`define PV_REG_PCR_ENTRY_28_6 (32'hb58) `define CLP_PV_REG_PCR_ENTRY_28_7 (32'h1001ab5c) -`define PV_REG_PCR_ENTRY_28_7 (32'hb5c) `define CLP_PV_REG_PCR_ENTRY_28_8 (32'h1001ab60) -`define PV_REG_PCR_ENTRY_28_8 (32'hb60) `define CLP_PV_REG_PCR_ENTRY_28_9 (32'h1001ab64) -`define PV_REG_PCR_ENTRY_28_9 (32'hb64) `define CLP_PV_REG_PCR_ENTRY_28_10 (32'h1001ab68) -`define PV_REG_PCR_ENTRY_28_10 (32'hb68) `define CLP_PV_REG_PCR_ENTRY_28_11 (32'h1001ab6c) -`define PV_REG_PCR_ENTRY_28_11 (32'hb6c) `define CLP_PV_REG_PCR_ENTRY_29_0 (32'h1001ab70) -`define PV_REG_PCR_ENTRY_29_0 (32'hb70) `define CLP_PV_REG_PCR_ENTRY_29_1 (32'h1001ab74) -`define PV_REG_PCR_ENTRY_29_1 (32'hb74) `define CLP_PV_REG_PCR_ENTRY_29_2 (32'h1001ab78) -`define PV_REG_PCR_ENTRY_29_2 (32'hb78) `define CLP_PV_REG_PCR_ENTRY_29_3 (32'h1001ab7c) -`define PV_REG_PCR_ENTRY_29_3 (32'hb7c) `define CLP_PV_REG_PCR_ENTRY_29_4 (32'h1001ab80) -`define PV_REG_PCR_ENTRY_29_4 (32'hb80) `define CLP_PV_REG_PCR_ENTRY_29_5 (32'h1001ab84) -`define PV_REG_PCR_ENTRY_29_5 (32'hb84) `define CLP_PV_REG_PCR_ENTRY_29_6 (32'h1001ab88) -`define PV_REG_PCR_ENTRY_29_6 (32'hb88) `define CLP_PV_REG_PCR_ENTRY_29_7 (32'h1001ab8c) -`define PV_REG_PCR_ENTRY_29_7 (32'hb8c) `define CLP_PV_REG_PCR_ENTRY_29_8 (32'h1001ab90) -`define PV_REG_PCR_ENTRY_29_8 (32'hb90) `define CLP_PV_REG_PCR_ENTRY_29_9 (32'h1001ab94) -`define PV_REG_PCR_ENTRY_29_9 (32'hb94) `define CLP_PV_REG_PCR_ENTRY_29_10 (32'h1001ab98) -`define PV_REG_PCR_ENTRY_29_10 (32'hb98) `define CLP_PV_REG_PCR_ENTRY_29_11 (32'h1001ab9c) -`define PV_REG_PCR_ENTRY_29_11 (32'hb9c) `define CLP_PV_REG_PCR_ENTRY_30_0 (32'h1001aba0) -`define PV_REG_PCR_ENTRY_30_0 (32'hba0) `define CLP_PV_REG_PCR_ENTRY_30_1 (32'h1001aba4) -`define PV_REG_PCR_ENTRY_30_1 (32'hba4) `define CLP_PV_REG_PCR_ENTRY_30_2 (32'h1001aba8) -`define PV_REG_PCR_ENTRY_30_2 (32'hba8) `define CLP_PV_REG_PCR_ENTRY_30_3 (32'h1001abac) -`define PV_REG_PCR_ENTRY_30_3 (32'hbac) `define CLP_PV_REG_PCR_ENTRY_30_4 (32'h1001abb0) -`define PV_REG_PCR_ENTRY_30_4 (32'hbb0) `define CLP_PV_REG_PCR_ENTRY_30_5 (32'h1001abb4) -`define PV_REG_PCR_ENTRY_30_5 (32'hbb4) `define CLP_PV_REG_PCR_ENTRY_30_6 (32'h1001abb8) -`define PV_REG_PCR_ENTRY_30_6 (32'hbb8) `define CLP_PV_REG_PCR_ENTRY_30_7 (32'h1001abbc) -`define PV_REG_PCR_ENTRY_30_7 (32'hbbc) `define CLP_PV_REG_PCR_ENTRY_30_8 (32'h1001abc0) -`define PV_REG_PCR_ENTRY_30_8 (32'hbc0) `define CLP_PV_REG_PCR_ENTRY_30_9 (32'h1001abc4) -`define PV_REG_PCR_ENTRY_30_9 (32'hbc4) `define CLP_PV_REG_PCR_ENTRY_30_10 (32'h1001abc8) -`define PV_REG_PCR_ENTRY_30_10 (32'hbc8) `define CLP_PV_REG_PCR_ENTRY_30_11 (32'h1001abcc) -`define PV_REG_PCR_ENTRY_30_11 (32'hbcc) `define CLP_PV_REG_PCR_ENTRY_31_0 (32'h1001abd0) -`define PV_REG_PCR_ENTRY_31_0 (32'hbd0) `define CLP_PV_REG_PCR_ENTRY_31_1 (32'h1001abd4) -`define PV_REG_PCR_ENTRY_31_1 (32'hbd4) `define CLP_PV_REG_PCR_ENTRY_31_2 (32'h1001abd8) -`define PV_REG_PCR_ENTRY_31_2 (32'hbd8) `define CLP_PV_REG_PCR_ENTRY_31_3 (32'h1001abdc) -`define PV_REG_PCR_ENTRY_31_3 (32'hbdc) `define CLP_PV_REG_PCR_ENTRY_31_4 (32'h1001abe0) -`define PV_REG_PCR_ENTRY_31_4 (32'hbe0) `define CLP_PV_REG_PCR_ENTRY_31_5 (32'h1001abe4) -`define PV_REG_PCR_ENTRY_31_5 (32'hbe4) `define CLP_PV_REG_PCR_ENTRY_31_6 (32'h1001abe8) -`define PV_REG_PCR_ENTRY_31_6 (32'hbe8) `define CLP_PV_REG_PCR_ENTRY_31_7 (32'h1001abec) -`define PV_REG_PCR_ENTRY_31_7 (32'hbec) `define CLP_PV_REG_PCR_ENTRY_31_8 (32'h1001abf0) -`define PV_REG_PCR_ENTRY_31_8 (32'hbf0) `define CLP_PV_REG_PCR_ENTRY_31_9 (32'h1001abf4) -`define PV_REG_PCR_ENTRY_31_9 (32'hbf4) `define CLP_PV_REG_PCR_ENTRY_31_10 (32'h1001abf8) -`define PV_REG_PCR_ENTRY_31_10 (32'hbf8) `define CLP_PV_REG_PCR_ENTRY_31_11 (32'h1001abfc) -`define PV_REG_PCR_ENTRY_31_11 (32'hbfc) `define CLP_DV_REG_BASE_ADDR (32'h1001c000) `define CLP_DV_REG_STICKYDATAVAULTCTRL_0 (32'h1001c000) -`define DV_REG_STICKYDATAVAULTCTRL_0 (32'h0) -`define DV_REG_STICKYDATAVAULTCTRL_0_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_0_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_1 (32'h1001c004) -`define DV_REG_STICKYDATAVAULTCTRL_1 (32'h4) -`define DV_REG_STICKYDATAVAULTCTRL_1_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_1_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_2 (32'h1001c008) -`define DV_REG_STICKYDATAVAULTCTRL_2 (32'h8) -`define DV_REG_STICKYDATAVAULTCTRL_2_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_2_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_3 (32'h1001c00c) -`define DV_REG_STICKYDATAVAULTCTRL_3 (32'hc) -`define DV_REG_STICKYDATAVAULTCTRL_3_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_3_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_4 (32'h1001c010) -`define DV_REG_STICKYDATAVAULTCTRL_4 (32'h10) -`define DV_REG_STICKYDATAVAULTCTRL_4_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_4_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_5 (32'h1001c014) -`define DV_REG_STICKYDATAVAULTCTRL_5 (32'h14) -`define DV_REG_STICKYDATAVAULTCTRL_5_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_5_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_6 (32'h1001c018) -`define DV_REG_STICKYDATAVAULTCTRL_6 (32'h18) -`define DV_REG_STICKYDATAVAULTCTRL_6_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_6_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_7 (32'h1001c01c) -`define DV_REG_STICKYDATAVAULTCTRL_7 (32'h1c) -`define DV_REG_STICKYDATAVAULTCTRL_7_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_7_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_8 (32'h1001c020) -`define DV_REG_STICKYDATAVAULTCTRL_8 (32'h20) -`define DV_REG_STICKYDATAVAULTCTRL_8_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_8_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYDATAVAULTCTRL_9 (32'h1001c024) -`define DV_REG_STICKYDATAVAULTCTRL_9 (32'h24) -`define DV_REG_STICKYDATAVAULTCTRL_9_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYDATAVAULTCTRL_9_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_0 (32'h1001c028) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_0 (32'h28) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_1 (32'h1001c02c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_1 (32'h2c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_2 (32'h1001c030) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_2 (32'h30) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_3 (32'h1001c034) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_3 (32'h34) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_4 (32'h1001c038) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_4 (32'h38) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_5 (32'h1001c03c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_5 (32'h3c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_6 (32'h1001c040) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_6 (32'h40) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_7 (32'h1001c044) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_7 (32'h44) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_8 (32'h1001c048) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_8 (32'h48) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_9 (32'h1001c04c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_9 (32'h4c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_10 (32'h1001c050) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_10 (32'h50) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_11 (32'h1001c054) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_11 (32'h54) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_0 (32'h1001c058) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_0 (32'h58) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_1 (32'h1001c05c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_1 (32'h5c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_2 (32'h1001c060) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_2 (32'h60) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_3 (32'h1001c064) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_3 (32'h64) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_4 (32'h1001c068) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_4 (32'h68) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_5 (32'h1001c06c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_5 (32'h6c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_6 (32'h1001c070) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_6 (32'h70) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_7 (32'h1001c074) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_7 (32'h74) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_8 (32'h1001c078) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_8 (32'h78) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_9 (32'h1001c07c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_9 (32'h7c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_10 (32'h1001c080) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_10 (32'h80) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_11 (32'h1001c084) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_11 (32'h84) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_0 (32'h1001c088) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_0 (32'h88) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_1 (32'h1001c08c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_1 (32'h8c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_2 (32'h1001c090) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_2 (32'h90) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_3 (32'h1001c094) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_3 (32'h94) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_4 (32'h1001c098) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_4 (32'h98) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_5 (32'h1001c09c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_5 (32'h9c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_6 (32'h1001c0a0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_6 (32'ha0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_7 (32'h1001c0a4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_7 (32'ha4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_8 (32'h1001c0a8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_8 (32'ha8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_9 (32'h1001c0ac) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_9 (32'hac) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_10 (32'h1001c0b0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_10 (32'hb0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_11 (32'h1001c0b4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_11 (32'hb4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_0 (32'h1001c0b8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_0 (32'hb8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_1 (32'h1001c0bc) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_1 (32'hbc) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_2 (32'h1001c0c0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_2 (32'hc0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_3 (32'h1001c0c4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_3 (32'hc4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_4 (32'h1001c0c8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_4 (32'hc8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_5 (32'h1001c0cc) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_5 (32'hcc) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_6 (32'h1001c0d0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_6 (32'hd0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_7 (32'h1001c0d4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_7 (32'hd4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_8 (32'h1001c0d8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_8 (32'hd8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_9 (32'h1001c0dc) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_9 (32'hdc) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_10 (32'h1001c0e0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_10 (32'he0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_11 (32'h1001c0e4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_11 (32'he4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_0 (32'h1001c0e8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_0 (32'he8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_1 (32'h1001c0ec) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_1 (32'hec) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_2 (32'h1001c0f0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_2 (32'hf0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_3 (32'h1001c0f4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_3 (32'hf4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_4 (32'h1001c0f8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_4 (32'hf8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_5 (32'h1001c0fc) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_5 (32'hfc) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_6 (32'h1001c100) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_6 (32'h100) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_7 (32'h1001c104) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_7 (32'h104) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_8 (32'h1001c108) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_8 (32'h108) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_9 (32'h1001c10c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_9 (32'h10c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_10 (32'h1001c110) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_10 (32'h110) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_11 (32'h1001c114) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_11 (32'h114) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_0 (32'h1001c118) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_0 (32'h118) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_1 (32'h1001c11c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_1 (32'h11c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_2 (32'h1001c120) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_2 (32'h120) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_3 (32'h1001c124) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_3 (32'h124) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_4 (32'h1001c128) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_4 (32'h128) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_5 (32'h1001c12c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_5 (32'h12c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_6 (32'h1001c130) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_6 (32'h130) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_7 (32'h1001c134) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_7 (32'h134) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_8 (32'h1001c138) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_8 (32'h138) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_9 (32'h1001c13c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_9 (32'h13c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_10 (32'h1001c140) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_10 (32'h140) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_11 (32'h1001c144) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_11 (32'h144) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_0 (32'h1001c148) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_0 (32'h148) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_1 (32'h1001c14c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_1 (32'h14c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_2 (32'h1001c150) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_2 (32'h150) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_3 (32'h1001c154) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_3 (32'h154) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_4 (32'h1001c158) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_4 (32'h158) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_5 (32'h1001c15c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_5 (32'h15c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_6 (32'h1001c160) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_6 (32'h160) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_7 (32'h1001c164) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_7 (32'h164) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_8 (32'h1001c168) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_8 (32'h168) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_9 (32'h1001c16c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_9 (32'h16c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_10 (32'h1001c170) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_10 (32'h170) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_11 (32'h1001c174) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_11 (32'h174) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_0 (32'h1001c178) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_0 (32'h178) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_1 (32'h1001c17c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_1 (32'h17c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_2 (32'h1001c180) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_2 (32'h180) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_3 (32'h1001c184) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_3 (32'h184) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_4 (32'h1001c188) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_4 (32'h188) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_5 (32'h1001c18c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_5 (32'h18c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_6 (32'h1001c190) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_6 (32'h190) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_7 (32'h1001c194) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_7 (32'h194) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_8 (32'h1001c198) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_8 (32'h198) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_9 (32'h1001c19c) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_9 (32'h19c) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_10 (32'h1001c1a0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_10 (32'h1a0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_11 (32'h1001c1a4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_11 (32'h1a4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_0 (32'h1001c1a8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_0 (32'h1a8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_1 (32'h1001c1ac) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_1 (32'h1ac) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_2 (32'h1001c1b0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_2 (32'h1b0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_3 (32'h1001c1b4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_3 (32'h1b4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_4 (32'h1001c1b8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_4 (32'h1b8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_5 (32'h1001c1bc) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_5 (32'h1bc) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_6 (32'h1001c1c0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_6 (32'h1c0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_7 (32'h1001c1c4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_7 (32'h1c4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_8 (32'h1001c1c8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_8 (32'h1c8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_9 (32'h1001c1cc) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_9 (32'h1cc) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_10 (32'h1001c1d0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_10 (32'h1d0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_11 (32'h1001c1d4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_11 (32'h1d4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_0 (32'h1001c1d8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_0 (32'h1d8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_1 (32'h1001c1dc) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_1 (32'h1dc) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_2 (32'h1001c1e0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_2 (32'h1e0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_3 (32'h1001c1e4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_3 (32'h1e4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_4 (32'h1001c1e8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_4 (32'h1e8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_5 (32'h1001c1ec) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_5 (32'h1ec) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_6 (32'h1001c1f0) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_6 (32'h1f0) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_7 (32'h1001c1f4) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_7 (32'h1f4) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_8 (32'h1001c1f8) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_8 (32'h1f8) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_9 (32'h1001c1fc) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_9 (32'h1fc) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_10 (32'h1001c200) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_10 (32'h200) `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_11 (32'h1001c204) -`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_11 (32'h204) `define CLP_DV_REG_DATAVAULTCTRL_0 (32'h1001c208) -`define DV_REG_DATAVAULTCTRL_0 (32'h208) -`define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_1 (32'h1001c20c) -`define DV_REG_DATAVAULTCTRL_1 (32'h20c) -`define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_2 (32'h1001c210) -`define DV_REG_DATAVAULTCTRL_2 (32'h210) -`define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_3 (32'h1001c214) -`define DV_REG_DATAVAULTCTRL_3 (32'h214) -`define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_4 (32'h1001c218) -`define DV_REG_DATAVAULTCTRL_4 (32'h218) -`define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_5 (32'h1001c21c) -`define DV_REG_DATAVAULTCTRL_5 (32'h21c) -`define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_6 (32'h1001c220) -`define DV_REG_DATAVAULTCTRL_6 (32'h220) -`define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_7 (32'h1001c224) -`define DV_REG_DATAVAULTCTRL_7 (32'h224) -`define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_8 (32'h1001c228) -`define DV_REG_DATAVAULTCTRL_8 (32'h228) -`define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATAVAULTCTRL_9 (32'h1001c22c) -`define DV_REG_DATAVAULTCTRL_9 (32'h22c) -`define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_LOW (0) -`define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_0 (32'h1001c230) -`define DV_REG_DATA_VAULT_ENTRY_0_0 (32'h230) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_1 (32'h1001c234) -`define DV_REG_DATA_VAULT_ENTRY_0_1 (32'h234) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_2 (32'h1001c238) -`define DV_REG_DATA_VAULT_ENTRY_0_2 (32'h238) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_3 (32'h1001c23c) -`define DV_REG_DATA_VAULT_ENTRY_0_3 (32'h23c) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_4 (32'h1001c240) -`define DV_REG_DATA_VAULT_ENTRY_0_4 (32'h240) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_5 (32'h1001c244) -`define DV_REG_DATA_VAULT_ENTRY_0_5 (32'h244) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_6 (32'h1001c248) -`define DV_REG_DATA_VAULT_ENTRY_0_6 (32'h248) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_7 (32'h1001c24c) -`define DV_REG_DATA_VAULT_ENTRY_0_7 (32'h24c) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_8 (32'h1001c250) -`define DV_REG_DATA_VAULT_ENTRY_0_8 (32'h250) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_9 (32'h1001c254) -`define DV_REG_DATA_VAULT_ENTRY_0_9 (32'h254) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_10 (32'h1001c258) -`define DV_REG_DATA_VAULT_ENTRY_0_10 (32'h258) `define CLP_DV_REG_DATA_VAULT_ENTRY_0_11 (32'h1001c25c) -`define DV_REG_DATA_VAULT_ENTRY_0_11 (32'h25c) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_0 (32'h1001c260) -`define DV_REG_DATA_VAULT_ENTRY_1_0 (32'h260) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_1 (32'h1001c264) -`define DV_REG_DATA_VAULT_ENTRY_1_1 (32'h264) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_2 (32'h1001c268) -`define DV_REG_DATA_VAULT_ENTRY_1_2 (32'h268) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_3 (32'h1001c26c) -`define DV_REG_DATA_VAULT_ENTRY_1_3 (32'h26c) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_4 (32'h1001c270) -`define DV_REG_DATA_VAULT_ENTRY_1_4 (32'h270) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_5 (32'h1001c274) -`define DV_REG_DATA_VAULT_ENTRY_1_5 (32'h274) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_6 (32'h1001c278) -`define DV_REG_DATA_VAULT_ENTRY_1_6 (32'h278) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_7 (32'h1001c27c) -`define DV_REG_DATA_VAULT_ENTRY_1_7 (32'h27c) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_8 (32'h1001c280) -`define DV_REG_DATA_VAULT_ENTRY_1_8 (32'h280) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_9 (32'h1001c284) -`define DV_REG_DATA_VAULT_ENTRY_1_9 (32'h284) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_10 (32'h1001c288) -`define DV_REG_DATA_VAULT_ENTRY_1_10 (32'h288) `define CLP_DV_REG_DATA_VAULT_ENTRY_1_11 (32'h1001c28c) -`define DV_REG_DATA_VAULT_ENTRY_1_11 (32'h28c) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_0 (32'h1001c290) -`define DV_REG_DATA_VAULT_ENTRY_2_0 (32'h290) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_1 (32'h1001c294) -`define DV_REG_DATA_VAULT_ENTRY_2_1 (32'h294) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_2 (32'h1001c298) -`define DV_REG_DATA_VAULT_ENTRY_2_2 (32'h298) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_3 (32'h1001c29c) -`define DV_REG_DATA_VAULT_ENTRY_2_3 (32'h29c) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_4 (32'h1001c2a0) -`define DV_REG_DATA_VAULT_ENTRY_2_4 (32'h2a0) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_5 (32'h1001c2a4) -`define DV_REG_DATA_VAULT_ENTRY_2_5 (32'h2a4) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_6 (32'h1001c2a8) -`define DV_REG_DATA_VAULT_ENTRY_2_6 (32'h2a8) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_7 (32'h1001c2ac) -`define DV_REG_DATA_VAULT_ENTRY_2_7 (32'h2ac) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_8 (32'h1001c2b0) -`define DV_REG_DATA_VAULT_ENTRY_2_8 (32'h2b0) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_9 (32'h1001c2b4) -`define DV_REG_DATA_VAULT_ENTRY_2_9 (32'h2b4) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_10 (32'h1001c2b8) -`define DV_REG_DATA_VAULT_ENTRY_2_10 (32'h2b8) `define CLP_DV_REG_DATA_VAULT_ENTRY_2_11 (32'h1001c2bc) -`define DV_REG_DATA_VAULT_ENTRY_2_11 (32'h2bc) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_0 (32'h1001c2c0) -`define DV_REG_DATA_VAULT_ENTRY_3_0 (32'h2c0) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_1 (32'h1001c2c4) -`define DV_REG_DATA_VAULT_ENTRY_3_1 (32'h2c4) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_2 (32'h1001c2c8) -`define DV_REG_DATA_VAULT_ENTRY_3_2 (32'h2c8) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_3 (32'h1001c2cc) -`define DV_REG_DATA_VAULT_ENTRY_3_3 (32'h2cc) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_4 (32'h1001c2d0) -`define DV_REG_DATA_VAULT_ENTRY_3_4 (32'h2d0) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_5 (32'h1001c2d4) -`define DV_REG_DATA_VAULT_ENTRY_3_5 (32'h2d4) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_6 (32'h1001c2d8) -`define DV_REG_DATA_VAULT_ENTRY_3_6 (32'h2d8) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_7 (32'h1001c2dc) -`define DV_REG_DATA_VAULT_ENTRY_3_7 (32'h2dc) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_8 (32'h1001c2e0) -`define DV_REG_DATA_VAULT_ENTRY_3_8 (32'h2e0) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_9 (32'h1001c2e4) -`define DV_REG_DATA_VAULT_ENTRY_3_9 (32'h2e4) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_10 (32'h1001c2e8) -`define DV_REG_DATA_VAULT_ENTRY_3_10 (32'h2e8) `define CLP_DV_REG_DATA_VAULT_ENTRY_3_11 (32'h1001c2ec) -`define DV_REG_DATA_VAULT_ENTRY_3_11 (32'h2ec) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_0 (32'h1001c2f0) -`define DV_REG_DATA_VAULT_ENTRY_4_0 (32'h2f0) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_1 (32'h1001c2f4) -`define DV_REG_DATA_VAULT_ENTRY_4_1 (32'h2f4) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_2 (32'h1001c2f8) -`define DV_REG_DATA_VAULT_ENTRY_4_2 (32'h2f8) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_3 (32'h1001c2fc) -`define DV_REG_DATA_VAULT_ENTRY_4_3 (32'h2fc) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_4 (32'h1001c300) -`define DV_REG_DATA_VAULT_ENTRY_4_4 (32'h300) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_5 (32'h1001c304) -`define DV_REG_DATA_VAULT_ENTRY_4_5 (32'h304) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_6 (32'h1001c308) -`define DV_REG_DATA_VAULT_ENTRY_4_6 (32'h308) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_7 (32'h1001c30c) -`define DV_REG_DATA_VAULT_ENTRY_4_7 (32'h30c) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_8 (32'h1001c310) -`define DV_REG_DATA_VAULT_ENTRY_4_8 (32'h310) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_9 (32'h1001c314) -`define DV_REG_DATA_VAULT_ENTRY_4_9 (32'h314) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_10 (32'h1001c318) -`define DV_REG_DATA_VAULT_ENTRY_4_10 (32'h318) `define CLP_DV_REG_DATA_VAULT_ENTRY_4_11 (32'h1001c31c) -`define DV_REG_DATA_VAULT_ENTRY_4_11 (32'h31c) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_0 (32'h1001c320) -`define DV_REG_DATA_VAULT_ENTRY_5_0 (32'h320) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_1 (32'h1001c324) -`define DV_REG_DATA_VAULT_ENTRY_5_1 (32'h324) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_2 (32'h1001c328) -`define DV_REG_DATA_VAULT_ENTRY_5_2 (32'h328) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_3 (32'h1001c32c) -`define DV_REG_DATA_VAULT_ENTRY_5_3 (32'h32c) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_4 (32'h1001c330) -`define DV_REG_DATA_VAULT_ENTRY_5_4 (32'h330) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_5 (32'h1001c334) -`define DV_REG_DATA_VAULT_ENTRY_5_5 (32'h334) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_6 (32'h1001c338) -`define DV_REG_DATA_VAULT_ENTRY_5_6 (32'h338) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_7 (32'h1001c33c) -`define DV_REG_DATA_VAULT_ENTRY_5_7 (32'h33c) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_8 (32'h1001c340) -`define DV_REG_DATA_VAULT_ENTRY_5_8 (32'h340) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_9 (32'h1001c344) -`define DV_REG_DATA_VAULT_ENTRY_5_9 (32'h344) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_10 (32'h1001c348) -`define DV_REG_DATA_VAULT_ENTRY_5_10 (32'h348) `define CLP_DV_REG_DATA_VAULT_ENTRY_5_11 (32'h1001c34c) -`define DV_REG_DATA_VAULT_ENTRY_5_11 (32'h34c) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_0 (32'h1001c350) -`define DV_REG_DATA_VAULT_ENTRY_6_0 (32'h350) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_1 (32'h1001c354) -`define DV_REG_DATA_VAULT_ENTRY_6_1 (32'h354) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_2 (32'h1001c358) -`define DV_REG_DATA_VAULT_ENTRY_6_2 (32'h358) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_3 (32'h1001c35c) -`define DV_REG_DATA_VAULT_ENTRY_6_3 (32'h35c) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_4 (32'h1001c360) -`define DV_REG_DATA_VAULT_ENTRY_6_4 (32'h360) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_5 (32'h1001c364) -`define DV_REG_DATA_VAULT_ENTRY_6_5 (32'h364) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_6 (32'h1001c368) -`define DV_REG_DATA_VAULT_ENTRY_6_6 (32'h368) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_7 (32'h1001c36c) -`define DV_REG_DATA_VAULT_ENTRY_6_7 (32'h36c) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_8 (32'h1001c370) -`define DV_REG_DATA_VAULT_ENTRY_6_8 (32'h370) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_9 (32'h1001c374) -`define DV_REG_DATA_VAULT_ENTRY_6_9 (32'h374) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_10 (32'h1001c378) -`define DV_REG_DATA_VAULT_ENTRY_6_10 (32'h378) `define CLP_DV_REG_DATA_VAULT_ENTRY_6_11 (32'h1001c37c) -`define DV_REG_DATA_VAULT_ENTRY_6_11 (32'h37c) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_0 (32'h1001c380) -`define DV_REG_DATA_VAULT_ENTRY_7_0 (32'h380) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_1 (32'h1001c384) -`define DV_REG_DATA_VAULT_ENTRY_7_1 (32'h384) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_2 (32'h1001c388) -`define DV_REG_DATA_VAULT_ENTRY_7_2 (32'h388) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_3 (32'h1001c38c) -`define DV_REG_DATA_VAULT_ENTRY_7_3 (32'h38c) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_4 (32'h1001c390) -`define DV_REG_DATA_VAULT_ENTRY_7_4 (32'h390) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_5 (32'h1001c394) -`define DV_REG_DATA_VAULT_ENTRY_7_5 (32'h394) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_6 (32'h1001c398) -`define DV_REG_DATA_VAULT_ENTRY_7_6 (32'h398) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_7 (32'h1001c39c) -`define DV_REG_DATA_VAULT_ENTRY_7_7 (32'h39c) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_8 (32'h1001c3a0) -`define DV_REG_DATA_VAULT_ENTRY_7_8 (32'h3a0) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_9 (32'h1001c3a4) -`define DV_REG_DATA_VAULT_ENTRY_7_9 (32'h3a4) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_10 (32'h1001c3a8) -`define DV_REG_DATA_VAULT_ENTRY_7_10 (32'h3a8) `define CLP_DV_REG_DATA_VAULT_ENTRY_7_11 (32'h1001c3ac) -`define DV_REG_DATA_VAULT_ENTRY_7_11 (32'h3ac) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_0 (32'h1001c3b0) -`define DV_REG_DATA_VAULT_ENTRY_8_0 (32'h3b0) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_1 (32'h1001c3b4) -`define DV_REG_DATA_VAULT_ENTRY_8_1 (32'h3b4) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_2 (32'h1001c3b8) -`define DV_REG_DATA_VAULT_ENTRY_8_2 (32'h3b8) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_3 (32'h1001c3bc) -`define DV_REG_DATA_VAULT_ENTRY_8_3 (32'h3bc) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_4 (32'h1001c3c0) -`define DV_REG_DATA_VAULT_ENTRY_8_4 (32'h3c0) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_5 (32'h1001c3c4) -`define DV_REG_DATA_VAULT_ENTRY_8_5 (32'h3c4) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_6 (32'h1001c3c8) -`define DV_REG_DATA_VAULT_ENTRY_8_6 (32'h3c8) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_7 (32'h1001c3cc) -`define DV_REG_DATA_VAULT_ENTRY_8_7 (32'h3cc) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_8 (32'h1001c3d0) -`define DV_REG_DATA_VAULT_ENTRY_8_8 (32'h3d0) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_9 (32'h1001c3d4) -`define DV_REG_DATA_VAULT_ENTRY_8_9 (32'h3d4) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_10 (32'h1001c3d8) -`define DV_REG_DATA_VAULT_ENTRY_8_10 (32'h3d8) `define CLP_DV_REG_DATA_VAULT_ENTRY_8_11 (32'h1001c3dc) -`define DV_REG_DATA_VAULT_ENTRY_8_11 (32'h3dc) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_0 (32'h1001c3e0) -`define DV_REG_DATA_VAULT_ENTRY_9_0 (32'h3e0) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_1 (32'h1001c3e4) -`define DV_REG_DATA_VAULT_ENTRY_9_1 (32'h3e4) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_2 (32'h1001c3e8) -`define DV_REG_DATA_VAULT_ENTRY_9_2 (32'h3e8) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_3 (32'h1001c3ec) -`define DV_REG_DATA_VAULT_ENTRY_9_3 (32'h3ec) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_4 (32'h1001c3f0) -`define DV_REG_DATA_VAULT_ENTRY_9_4 (32'h3f0) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_5 (32'h1001c3f4) -`define DV_REG_DATA_VAULT_ENTRY_9_5 (32'h3f4) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_6 (32'h1001c3f8) -`define DV_REG_DATA_VAULT_ENTRY_9_6 (32'h3f8) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_7 (32'h1001c3fc) -`define DV_REG_DATA_VAULT_ENTRY_9_7 (32'h3fc) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_8 (32'h1001c400) -`define DV_REG_DATA_VAULT_ENTRY_9_8 (32'h400) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_9 (32'h1001c404) -`define DV_REG_DATA_VAULT_ENTRY_9_9 (32'h404) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_10 (32'h1001c408) -`define DV_REG_DATA_VAULT_ENTRY_9_10 (32'h408) `define CLP_DV_REG_DATA_VAULT_ENTRY_9_11 (32'h1001c40c) -`define DV_REG_DATA_VAULT_ENTRY_9_11 (32'h40c) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_0 (32'h1001c410) -`define DV_REG_LOCKABLESCRATCHREGCTRL_0 (32'h410) -`define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_1 (32'h1001c414) -`define DV_REG_LOCKABLESCRATCHREGCTRL_1 (32'h414) -`define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_2 (32'h1001c418) -`define DV_REG_LOCKABLESCRATCHREGCTRL_2 (32'h418) -`define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_3 (32'h1001c41c) -`define DV_REG_LOCKABLESCRATCHREGCTRL_3 (32'h41c) -`define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_4 (32'h1001c420) -`define DV_REG_LOCKABLESCRATCHREGCTRL_4 (32'h420) -`define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_5 (32'h1001c424) -`define DV_REG_LOCKABLESCRATCHREGCTRL_5 (32'h424) -`define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_6 (32'h1001c428) -`define DV_REG_LOCKABLESCRATCHREGCTRL_6 (32'h428) -`define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_7 (32'h1001c42c) -`define DV_REG_LOCKABLESCRATCHREGCTRL_7 (32'h42c) -`define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_8 (32'h1001c430) -`define DV_REG_LOCKABLESCRATCHREGCTRL_8 (32'h430) -`define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_9 (32'h1001c434) -`define DV_REG_LOCKABLESCRATCHREGCTRL_9 (32'h434) -`define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_LOW (0) -`define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_LOCKABLESCRATCHREG_0 (32'h1001c438) -`define DV_REG_LOCKABLESCRATCHREG_0 (32'h438) `define CLP_DV_REG_LOCKABLESCRATCHREG_1 (32'h1001c43c) -`define DV_REG_LOCKABLESCRATCHREG_1 (32'h43c) `define CLP_DV_REG_LOCKABLESCRATCHREG_2 (32'h1001c440) -`define DV_REG_LOCKABLESCRATCHREG_2 (32'h440) `define CLP_DV_REG_LOCKABLESCRATCHREG_3 (32'h1001c444) -`define DV_REG_LOCKABLESCRATCHREG_3 (32'h444) `define CLP_DV_REG_LOCKABLESCRATCHREG_4 (32'h1001c448) -`define DV_REG_LOCKABLESCRATCHREG_4 (32'h448) `define CLP_DV_REG_LOCKABLESCRATCHREG_5 (32'h1001c44c) -`define DV_REG_LOCKABLESCRATCHREG_5 (32'h44c) `define CLP_DV_REG_LOCKABLESCRATCHREG_6 (32'h1001c450) -`define DV_REG_LOCKABLESCRATCHREG_6 (32'h450) `define CLP_DV_REG_LOCKABLESCRATCHREG_7 (32'h1001c454) -`define DV_REG_LOCKABLESCRATCHREG_7 (32'h454) `define CLP_DV_REG_LOCKABLESCRATCHREG_8 (32'h1001c458) -`define DV_REG_LOCKABLESCRATCHREG_8 (32'h458) `define CLP_DV_REG_LOCKABLESCRATCHREG_9 (32'h1001c45c) -`define DV_REG_LOCKABLESCRATCHREG_9 (32'h45c) `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_0 (32'h1001c460) -`define DV_REG_NONSTICKYGENERICSCRATCHREG_0 (32'h460) `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_1 (32'h1001c464) -`define DV_REG_NONSTICKYGENERICSCRATCHREG_1 (32'h464) `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_2 (32'h1001c468) -`define DV_REG_NONSTICKYGENERICSCRATCHREG_2 (32'h468) `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_3 (32'h1001c46c) -`define DV_REG_NONSTICKYGENERICSCRATCHREG_3 (32'h46c) `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_4 (32'h1001c470) -`define DV_REG_NONSTICKYGENERICSCRATCHREG_4 (32'h470) `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_5 (32'h1001c474) -`define DV_REG_NONSTICKYGENERICSCRATCHREG_5 (32'h474) `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_6 (32'h1001c478) -`define DV_REG_NONSTICKYGENERICSCRATCHREG_6 (32'h478) `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_7 (32'h1001c47c) -`define DV_REG_NONSTICKYGENERICSCRATCHREG_7 (32'h47c) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0 (32'h1001c480) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0 (32'h480) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1 (32'h1001c484) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1 (32'h484) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2 (32'h1001c488) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2 (32'h488) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3 (32'h1001c48c) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3 (32'h48c) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4 (32'h1001c490) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4 (32'h490) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5 (32'h1001c494) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5 (32'h494) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6 (32'h1001c498) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6 (32'h498) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7 (32'h1001c49c) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7 (32'h49c) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW (0) -`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK (32'h1) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_0 (32'h1001c4a0) -`define DV_REG_STICKYLOCKABLESCRATCHREG_0 (32'h4a0) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_1 (32'h1001c4a4) -`define DV_REG_STICKYLOCKABLESCRATCHREG_1 (32'h4a4) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_2 (32'h1001c4a8) -`define DV_REG_STICKYLOCKABLESCRATCHREG_2 (32'h4a8) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_3 (32'h1001c4ac) -`define DV_REG_STICKYLOCKABLESCRATCHREG_3 (32'h4ac) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_4 (32'h1001c4b0) -`define DV_REG_STICKYLOCKABLESCRATCHREG_4 (32'h4b0) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_5 (32'h1001c4b4) -`define DV_REG_STICKYLOCKABLESCRATCHREG_5 (32'h4b4) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_6 (32'h1001c4b8) -`define DV_REG_STICKYLOCKABLESCRATCHREG_6 (32'h4b8) `define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_7 (32'h1001c4bc) -`define DV_REG_STICKYLOCKABLESCRATCHREG_7 (32'h4bc) `define CLP_SHA512_REG_BASE_ADDR (32'h10020000) `define CLP_SHA512_REG_SHA512_NAME_0 (32'h10020000) -`define SHA512_REG_SHA512_NAME_0 (32'h0) `define CLP_SHA512_REG_SHA512_NAME_1 (32'h10020004) -`define SHA512_REG_SHA512_NAME_1 (32'h4) `define CLP_SHA512_REG_SHA512_VERSION_0 (32'h10020008) -`define SHA512_REG_SHA512_VERSION_0 (32'h8) `define CLP_SHA512_REG_SHA512_VERSION_1 (32'h1002000c) -`define SHA512_REG_SHA512_VERSION_1 (32'hc) `define CLP_SHA512_REG_SHA512_CTRL (32'h10020010) -`define SHA512_REG_SHA512_CTRL (32'h10) -`define SHA512_REG_SHA512_CTRL_INIT_LOW (0) -`define SHA512_REG_SHA512_CTRL_INIT_MASK (32'h1) -`define SHA512_REG_SHA512_CTRL_NEXT_LOW (1) -`define SHA512_REG_SHA512_CTRL_NEXT_MASK (32'h2) -`define SHA512_REG_SHA512_CTRL_MODE_LOW (2) -`define SHA512_REG_SHA512_CTRL_MODE_MASK (32'hc) -`define SHA512_REG_SHA512_CTRL_ZEROIZE_LOW (4) -`define SHA512_REG_SHA512_CTRL_ZEROIZE_MASK (32'h10) -`define SHA512_REG_SHA512_CTRL_LAST_LOW (5) -`define SHA512_REG_SHA512_CTRL_LAST_MASK (32'h20) -`define SHA512_REG_SHA512_CTRL_RESTORE_LOW (6) -`define SHA512_REG_SHA512_CTRL_RESTORE_MASK (32'h40) `define CLP_SHA512_REG_SHA512_STATUS (32'h10020018) -`define SHA512_REG_SHA512_STATUS (32'h18) -`define SHA512_REG_SHA512_STATUS_READY_LOW (0) -`define SHA512_REG_SHA512_STATUS_READY_MASK (32'h1) -`define SHA512_REG_SHA512_STATUS_VALID_LOW (1) -`define SHA512_REG_SHA512_STATUS_VALID_MASK (32'h2) `define CLP_SHA512_REG_SHA512_BLOCK_0 (32'h10020080) -`define SHA512_REG_SHA512_BLOCK_0 (32'h80) `define CLP_SHA512_REG_SHA512_BLOCK_1 (32'h10020084) -`define SHA512_REG_SHA512_BLOCK_1 (32'h84) `define CLP_SHA512_REG_SHA512_BLOCK_2 (32'h10020088) -`define SHA512_REG_SHA512_BLOCK_2 (32'h88) `define CLP_SHA512_REG_SHA512_BLOCK_3 (32'h1002008c) -`define SHA512_REG_SHA512_BLOCK_3 (32'h8c) `define CLP_SHA512_REG_SHA512_BLOCK_4 (32'h10020090) -`define SHA512_REG_SHA512_BLOCK_4 (32'h90) `define CLP_SHA512_REG_SHA512_BLOCK_5 (32'h10020094) -`define SHA512_REG_SHA512_BLOCK_5 (32'h94) `define CLP_SHA512_REG_SHA512_BLOCK_6 (32'h10020098) -`define SHA512_REG_SHA512_BLOCK_6 (32'h98) `define CLP_SHA512_REG_SHA512_BLOCK_7 (32'h1002009c) -`define SHA512_REG_SHA512_BLOCK_7 (32'h9c) `define CLP_SHA512_REG_SHA512_BLOCK_8 (32'h100200a0) -`define SHA512_REG_SHA512_BLOCK_8 (32'ha0) `define CLP_SHA512_REG_SHA512_BLOCK_9 (32'h100200a4) -`define SHA512_REG_SHA512_BLOCK_9 (32'ha4) `define CLP_SHA512_REG_SHA512_BLOCK_10 (32'h100200a8) -`define SHA512_REG_SHA512_BLOCK_10 (32'ha8) `define CLP_SHA512_REG_SHA512_BLOCK_11 (32'h100200ac) -`define SHA512_REG_SHA512_BLOCK_11 (32'hac) `define CLP_SHA512_REG_SHA512_BLOCK_12 (32'h100200b0) -`define SHA512_REG_SHA512_BLOCK_12 (32'hb0) `define CLP_SHA512_REG_SHA512_BLOCK_13 (32'h100200b4) -`define SHA512_REG_SHA512_BLOCK_13 (32'hb4) `define CLP_SHA512_REG_SHA512_BLOCK_14 (32'h100200b8) -`define SHA512_REG_SHA512_BLOCK_14 (32'hb8) `define CLP_SHA512_REG_SHA512_BLOCK_15 (32'h100200bc) -`define SHA512_REG_SHA512_BLOCK_15 (32'hbc) `define CLP_SHA512_REG_SHA512_BLOCK_16 (32'h100200c0) -`define SHA512_REG_SHA512_BLOCK_16 (32'hc0) `define CLP_SHA512_REG_SHA512_BLOCK_17 (32'h100200c4) -`define SHA512_REG_SHA512_BLOCK_17 (32'hc4) `define CLP_SHA512_REG_SHA512_BLOCK_18 (32'h100200c8) -`define SHA512_REG_SHA512_BLOCK_18 (32'hc8) `define CLP_SHA512_REG_SHA512_BLOCK_19 (32'h100200cc) -`define SHA512_REG_SHA512_BLOCK_19 (32'hcc) `define CLP_SHA512_REG_SHA512_BLOCK_20 (32'h100200d0) -`define SHA512_REG_SHA512_BLOCK_20 (32'hd0) `define CLP_SHA512_REG_SHA512_BLOCK_21 (32'h100200d4) -`define SHA512_REG_SHA512_BLOCK_21 (32'hd4) `define CLP_SHA512_REG_SHA512_BLOCK_22 (32'h100200d8) -`define SHA512_REG_SHA512_BLOCK_22 (32'hd8) `define CLP_SHA512_REG_SHA512_BLOCK_23 (32'h100200dc) -`define SHA512_REG_SHA512_BLOCK_23 (32'hdc) `define CLP_SHA512_REG_SHA512_BLOCK_24 (32'h100200e0) -`define SHA512_REG_SHA512_BLOCK_24 (32'he0) `define CLP_SHA512_REG_SHA512_BLOCK_25 (32'h100200e4) -`define SHA512_REG_SHA512_BLOCK_25 (32'he4) `define CLP_SHA512_REG_SHA512_BLOCK_26 (32'h100200e8) -`define SHA512_REG_SHA512_BLOCK_26 (32'he8) `define CLP_SHA512_REG_SHA512_BLOCK_27 (32'h100200ec) -`define SHA512_REG_SHA512_BLOCK_27 (32'hec) `define CLP_SHA512_REG_SHA512_BLOCK_28 (32'h100200f0) -`define SHA512_REG_SHA512_BLOCK_28 (32'hf0) `define CLP_SHA512_REG_SHA512_BLOCK_29 (32'h100200f4) -`define SHA512_REG_SHA512_BLOCK_29 (32'hf4) `define CLP_SHA512_REG_SHA512_BLOCK_30 (32'h100200f8) -`define SHA512_REG_SHA512_BLOCK_30 (32'hf8) `define CLP_SHA512_REG_SHA512_BLOCK_31 (32'h100200fc) -`define SHA512_REG_SHA512_BLOCK_31 (32'hfc) `define CLP_SHA512_REG_SHA512_DIGEST_0 (32'h10020100) -`define SHA512_REG_SHA512_DIGEST_0 (32'h100) `define CLP_SHA512_REG_SHA512_DIGEST_1 (32'h10020104) -`define SHA512_REG_SHA512_DIGEST_1 (32'h104) `define CLP_SHA512_REG_SHA512_DIGEST_2 (32'h10020108) -`define SHA512_REG_SHA512_DIGEST_2 (32'h108) `define CLP_SHA512_REG_SHA512_DIGEST_3 (32'h1002010c) -`define SHA512_REG_SHA512_DIGEST_3 (32'h10c) `define CLP_SHA512_REG_SHA512_DIGEST_4 (32'h10020110) -`define SHA512_REG_SHA512_DIGEST_4 (32'h110) `define CLP_SHA512_REG_SHA512_DIGEST_5 (32'h10020114) -`define SHA512_REG_SHA512_DIGEST_5 (32'h114) `define CLP_SHA512_REG_SHA512_DIGEST_6 (32'h10020118) -`define SHA512_REG_SHA512_DIGEST_6 (32'h118) `define CLP_SHA512_REG_SHA512_DIGEST_7 (32'h1002011c) -`define SHA512_REG_SHA512_DIGEST_7 (32'h11c) `define CLP_SHA512_REG_SHA512_DIGEST_8 (32'h10020120) -`define SHA512_REG_SHA512_DIGEST_8 (32'h120) `define CLP_SHA512_REG_SHA512_DIGEST_9 (32'h10020124) -`define SHA512_REG_SHA512_DIGEST_9 (32'h124) `define CLP_SHA512_REG_SHA512_DIGEST_10 (32'h10020128) -`define SHA512_REG_SHA512_DIGEST_10 (32'h128) `define CLP_SHA512_REG_SHA512_DIGEST_11 (32'h1002012c) -`define SHA512_REG_SHA512_DIGEST_11 (32'h12c) `define CLP_SHA512_REG_SHA512_DIGEST_12 (32'h10020130) -`define SHA512_REG_SHA512_DIGEST_12 (32'h130) `define CLP_SHA512_REG_SHA512_DIGEST_13 (32'h10020134) -`define SHA512_REG_SHA512_DIGEST_13 (32'h134) `define CLP_SHA512_REG_SHA512_DIGEST_14 (32'h10020138) -`define SHA512_REG_SHA512_DIGEST_14 (32'h138) `define CLP_SHA512_REG_SHA512_DIGEST_15 (32'h1002013c) -`define SHA512_REG_SHA512_DIGEST_15 (32'h13c) `define CLP_SHA512_REG_SHA512_VAULT_RD_CTRL (32'h10020600) -`define SHA512_REG_SHA512_VAULT_RD_CTRL (32'h600) -`define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_EN_LOW (0) -`define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_EN_MASK (32'h1) -`define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_ENTRY_LOW (1) -`define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_ENTRY_MASK (32'h3e) -`define SHA512_REG_SHA512_VAULT_RD_CTRL_PCR_HASH_EXTEND_LOW (6) -`define SHA512_REG_SHA512_VAULT_RD_CTRL_PCR_HASH_EXTEND_MASK (32'h40) -`define SHA512_REG_SHA512_VAULT_RD_CTRL_RSVD_LOW (7) -`define SHA512_REG_SHA512_VAULT_RD_CTRL_RSVD_MASK (32'hffffff80) `define CLP_SHA512_REG_SHA512_VAULT_RD_STATUS (32'h10020604) -`define SHA512_REG_SHA512_VAULT_RD_STATUS (32'h604) -`define SHA512_REG_SHA512_VAULT_RD_STATUS_READY_LOW (0) -`define SHA512_REG_SHA512_VAULT_RD_STATUS_READY_MASK (32'h1) -`define SHA512_REG_SHA512_VAULT_RD_STATUS_VALID_LOW (1) -`define SHA512_REG_SHA512_VAULT_RD_STATUS_VALID_MASK (32'h2) -`define SHA512_REG_SHA512_VAULT_RD_STATUS_ERROR_LOW (2) -`define SHA512_REG_SHA512_VAULT_RD_STATUS_ERROR_MASK (32'h3fc) `define CLP_SHA512_REG_SHA512_KV_WR_CTRL (32'h10020608) -`define SHA512_REG_SHA512_KV_WR_CTRL (32'h608) -`define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_EN_LOW (0) -`define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_EN_MASK (32'h1) -`define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_ENTRY_LOW (1) -`define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_ENTRY_MASK (32'h3e) -`define SHA512_REG_SHA512_KV_WR_CTRL_HMAC_KEY_DEST_VALID_LOW (6) -`define SHA512_REG_SHA512_KV_WR_CTRL_HMAC_KEY_DEST_VALID_MASK (32'h40) -`define SHA512_REG_SHA512_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_LOW (7) -`define SHA512_REG_SHA512_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_MASK (32'h80) -`define SHA512_REG_SHA512_KV_WR_CTRL_MLDSA_SEED_DEST_VALID_LOW (8) -`define SHA512_REG_SHA512_KV_WR_CTRL_MLDSA_SEED_DEST_VALID_MASK (32'h100) -`define SHA512_REG_SHA512_KV_WR_CTRL_ECC_PKEY_DEST_VALID_LOW (9) -`define SHA512_REG_SHA512_KV_WR_CTRL_ECC_PKEY_DEST_VALID_MASK (32'h200) -`define SHA512_REG_SHA512_KV_WR_CTRL_ECC_SEED_DEST_VALID_LOW (10) -`define SHA512_REG_SHA512_KV_WR_CTRL_ECC_SEED_DEST_VALID_MASK (32'h400) -`define SHA512_REG_SHA512_KV_WR_CTRL_AES_KEY_DEST_VALID_LOW (11) -`define SHA512_REG_SHA512_KV_WR_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) -`define SHA512_REG_SHA512_KV_WR_CTRL_RSVD_LOW (12) -`define SHA512_REG_SHA512_KV_WR_CTRL_RSVD_MASK (32'hfffff000) `define CLP_SHA512_REG_SHA512_KV_WR_STATUS (32'h1002060c) -`define SHA512_REG_SHA512_KV_WR_STATUS (32'h60c) -`define SHA512_REG_SHA512_KV_WR_STATUS_READY_LOW (0) -`define SHA512_REG_SHA512_KV_WR_STATUS_READY_MASK (32'h1) -`define SHA512_REG_SHA512_KV_WR_STATUS_VALID_LOW (1) -`define SHA512_REG_SHA512_KV_WR_STATUS_VALID_MASK (32'h2) -`define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_LOW (2) -`define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_MASK (32'h3fc) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0 (32'h10020610) -`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0 (32'h610) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1 (32'h10020614) -`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1 (32'h614) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2 (32'h10020618) -`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2 (32'h618) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3 (32'h1002061c) -`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3 (32'h61c) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4 (32'h10020620) -`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4 (32'h620) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5 (32'h10020624) -`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5 (32'h624) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6 (32'h10020628) -`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6 (32'h628) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7 (32'h1002062c) -`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7 (32'h62c) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_CTRL (32'h10020630) -`define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL (32'h630) -`define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_LOW (0) -`define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_MASK (32'h1) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_STATUS (32'h10020634) -`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS (32'h634) -`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_LOW (0) -`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_MASK (32'h1) -`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_LOW (1) -`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_MASK (32'h2) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0 (32'h10020638) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0 (32'h638) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1 (32'h1002063c) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1 (32'h63c) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2 (32'h10020640) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2 (32'h640) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3 (32'h10020644) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3 (32'h644) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4 (32'h10020648) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4 (32'h648) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5 (32'h1002064c) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5 (32'h64c) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6 (32'h10020650) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6 (32'h650) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7 (32'h10020654) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7 (32'h654) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8 (32'h10020658) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8 (32'h658) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9 (32'h1002065c) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9 (32'h65c) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10 (32'h10020660) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10 (32'h660) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11 (32'h10020664) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11 (32'h664) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_12 (32'h10020668) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_12 (32'h668) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_13 (32'h1002066c) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_13 (32'h66c) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_14 (32'h10020670) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_14 (32'h670) `define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_15 (32'h10020674) -`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_15 (32'h674) `define CLP_SHA512_REG_INTR_BLOCK_RF_START (32'h10020800) `define CLP_SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h10020800) -`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h10020804) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) `define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h10020808) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h1002080c) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h10020810) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h10020814) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) `define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h10020818) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h1002081c) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) -`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) `define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h10020820) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h10020900) -`define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h10020904) -`define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h10020908) -`define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h1002090c) -`define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) `define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h10020980) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'h10020a00) -`define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) -`define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'h10020a04) -`define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) -`define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'h10020a08) -`define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) -`define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'h10020a0c) -`define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) -`define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h10020a10) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA256_REG_BASE_ADDR (32'h10028000) `define CLP_SHA256_REG_SHA256_NAME_0 (32'h10028000) -`define SHA256_REG_SHA256_NAME_0 (32'h0) `define CLP_SHA256_REG_SHA256_NAME_1 (32'h10028004) -`define SHA256_REG_SHA256_NAME_1 (32'h4) `define CLP_SHA256_REG_SHA256_VERSION_0 (32'h10028008) -`define SHA256_REG_SHA256_VERSION_0 (32'h8) `define CLP_SHA256_REG_SHA256_VERSION_1 (32'h1002800c) -`define SHA256_REG_SHA256_VERSION_1 (32'hc) `define CLP_SHA256_REG_SHA256_CTRL (32'h10028010) -`define SHA256_REG_SHA256_CTRL (32'h10) -`define SHA256_REG_SHA256_CTRL_INIT_LOW (0) -`define SHA256_REG_SHA256_CTRL_INIT_MASK (32'h1) -`define SHA256_REG_SHA256_CTRL_NEXT_LOW (1) -`define SHA256_REG_SHA256_CTRL_NEXT_MASK (32'h2) -`define SHA256_REG_SHA256_CTRL_MODE_LOW (2) -`define SHA256_REG_SHA256_CTRL_MODE_MASK (32'h4) -`define SHA256_REG_SHA256_CTRL_ZEROIZE_LOW (3) -`define SHA256_REG_SHA256_CTRL_ZEROIZE_MASK (32'h8) -`define SHA256_REG_SHA256_CTRL_WNTZ_MODE_LOW (4) -`define SHA256_REG_SHA256_CTRL_WNTZ_MODE_MASK (32'h10) -`define SHA256_REG_SHA256_CTRL_WNTZ_W_LOW (5) -`define SHA256_REG_SHA256_CTRL_WNTZ_W_MASK (32'h1e0) -`define SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_LOW (9) -`define SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_MASK (32'h200) `define CLP_SHA256_REG_SHA256_STATUS (32'h10028018) -`define SHA256_REG_SHA256_STATUS (32'h18) -`define SHA256_REG_SHA256_STATUS_READY_LOW (0) -`define SHA256_REG_SHA256_STATUS_READY_MASK (32'h1) -`define SHA256_REG_SHA256_STATUS_VALID_LOW (1) -`define SHA256_REG_SHA256_STATUS_VALID_MASK (32'h2) -`define SHA256_REG_SHA256_STATUS_WNTZ_BUSY_LOW (2) -`define SHA256_REG_SHA256_STATUS_WNTZ_BUSY_MASK (32'h4) `define CLP_SHA256_REG_SHA256_BLOCK_0 (32'h10028080) -`define SHA256_REG_SHA256_BLOCK_0 (32'h80) `define CLP_SHA256_REG_SHA256_BLOCK_1 (32'h10028084) -`define SHA256_REG_SHA256_BLOCK_1 (32'h84) `define CLP_SHA256_REG_SHA256_BLOCK_2 (32'h10028088) -`define SHA256_REG_SHA256_BLOCK_2 (32'h88) `define CLP_SHA256_REG_SHA256_BLOCK_3 (32'h1002808c) -`define SHA256_REG_SHA256_BLOCK_3 (32'h8c) `define CLP_SHA256_REG_SHA256_BLOCK_4 (32'h10028090) -`define SHA256_REG_SHA256_BLOCK_4 (32'h90) `define CLP_SHA256_REG_SHA256_BLOCK_5 (32'h10028094) -`define SHA256_REG_SHA256_BLOCK_5 (32'h94) `define CLP_SHA256_REG_SHA256_BLOCK_6 (32'h10028098) -`define SHA256_REG_SHA256_BLOCK_6 (32'h98) `define CLP_SHA256_REG_SHA256_BLOCK_7 (32'h1002809c) -`define SHA256_REG_SHA256_BLOCK_7 (32'h9c) `define CLP_SHA256_REG_SHA256_BLOCK_8 (32'h100280a0) -`define SHA256_REG_SHA256_BLOCK_8 (32'ha0) `define CLP_SHA256_REG_SHA256_BLOCK_9 (32'h100280a4) -`define SHA256_REG_SHA256_BLOCK_9 (32'ha4) `define CLP_SHA256_REG_SHA256_BLOCK_10 (32'h100280a8) -`define SHA256_REG_SHA256_BLOCK_10 (32'ha8) `define CLP_SHA256_REG_SHA256_BLOCK_11 (32'h100280ac) -`define SHA256_REG_SHA256_BLOCK_11 (32'hac) `define CLP_SHA256_REG_SHA256_BLOCK_12 (32'h100280b0) -`define SHA256_REG_SHA256_BLOCK_12 (32'hb0) `define CLP_SHA256_REG_SHA256_BLOCK_13 (32'h100280b4) -`define SHA256_REG_SHA256_BLOCK_13 (32'hb4) `define CLP_SHA256_REG_SHA256_BLOCK_14 (32'h100280b8) -`define SHA256_REG_SHA256_BLOCK_14 (32'hb8) `define CLP_SHA256_REG_SHA256_BLOCK_15 (32'h100280bc) -`define SHA256_REG_SHA256_BLOCK_15 (32'hbc) `define CLP_SHA256_REG_SHA256_DIGEST_0 (32'h10028100) -`define SHA256_REG_SHA256_DIGEST_0 (32'h100) `define CLP_SHA256_REG_SHA256_DIGEST_1 (32'h10028104) -`define SHA256_REG_SHA256_DIGEST_1 (32'h104) `define CLP_SHA256_REG_SHA256_DIGEST_2 (32'h10028108) -`define SHA256_REG_SHA256_DIGEST_2 (32'h108) `define CLP_SHA256_REG_SHA256_DIGEST_3 (32'h1002810c) -`define SHA256_REG_SHA256_DIGEST_3 (32'h10c) `define CLP_SHA256_REG_SHA256_DIGEST_4 (32'h10028110) -`define SHA256_REG_SHA256_DIGEST_4 (32'h110) `define CLP_SHA256_REG_SHA256_DIGEST_5 (32'h10028114) -`define SHA256_REG_SHA256_DIGEST_5 (32'h114) `define CLP_SHA256_REG_SHA256_DIGEST_6 (32'h10028118) -`define SHA256_REG_SHA256_DIGEST_6 (32'h118) `define CLP_SHA256_REG_SHA256_DIGEST_7 (32'h1002811c) -`define SHA256_REG_SHA256_DIGEST_7 (32'h11c) `define CLP_SHA256_REG_INTR_BLOCK_RF_START (32'h10028800) `define CLP_SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h10028800) -`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h10028804) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) `define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h10028808) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h1002880c) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h10028810) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h10028814) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) `define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h10028818) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h1002881c) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) -`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) `define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h10028820) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h10028900) -`define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h10028904) -`define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h10028908) -`define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h1002890c) -`define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) `define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h10028980) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'h10028a00) -`define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) -`define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'h10028a04) -`define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) -`define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'h10028a08) -`define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) -`define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'h10028a0c) -`define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) -`define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h10028a10) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_MLDSA_REG_BASE_ADDR (32'h10030000) `define CLP_MLDSA_REG_MLDSA_NAME_0 (32'h10030000) -`define MLDSA_REG_MLDSA_NAME_0 (32'h0) `define CLP_MLDSA_REG_MLDSA_NAME_1 (32'h10030004) -`define MLDSA_REG_MLDSA_NAME_1 (32'h4) `define CLP_MLDSA_REG_MLDSA_VERSION_0 (32'h10030008) -`define MLDSA_REG_MLDSA_VERSION_0 (32'h8) `define CLP_MLDSA_REG_MLDSA_VERSION_1 (32'h1003000c) -`define MLDSA_REG_MLDSA_VERSION_1 (32'hc) `define CLP_MLDSA_REG_MLDSA_CTRL (32'h10030010) -`define MLDSA_REG_MLDSA_CTRL (32'h10) -`define MLDSA_REG_MLDSA_CTRL_CTRL_LOW (0) -`define MLDSA_REG_MLDSA_CTRL_CTRL_MASK (32'h7) -`define MLDSA_REG_MLDSA_CTRL_ZEROIZE_LOW (3) -`define MLDSA_REG_MLDSA_CTRL_ZEROIZE_MASK (32'h8) -`define MLDSA_REG_MLDSA_CTRL_PCR_SIGN_LOW (4) -`define MLDSA_REG_MLDSA_CTRL_PCR_SIGN_MASK (32'h10) `define CLP_MLDSA_REG_MLDSA_STATUS (32'h10030014) -`define MLDSA_REG_MLDSA_STATUS (32'h14) -`define MLDSA_REG_MLDSA_STATUS_READY_LOW (0) -`define MLDSA_REG_MLDSA_STATUS_READY_MASK (32'h1) -`define MLDSA_REG_MLDSA_STATUS_VALID_LOW (1) -`define MLDSA_REG_MLDSA_STATUS_VALID_MASK (32'h2) `define CLP_MLDSA_REG_MLDSA_ENTROPY_0 (32'h10030018) -`define MLDSA_REG_MLDSA_ENTROPY_0 (32'h18) `define CLP_MLDSA_REG_MLDSA_ENTROPY_1 (32'h1003001c) -`define MLDSA_REG_MLDSA_ENTROPY_1 (32'h1c) `define CLP_MLDSA_REG_MLDSA_ENTROPY_2 (32'h10030020) -`define MLDSA_REG_MLDSA_ENTROPY_2 (32'h20) `define CLP_MLDSA_REG_MLDSA_ENTROPY_3 (32'h10030024) -`define MLDSA_REG_MLDSA_ENTROPY_3 (32'h24) `define CLP_MLDSA_REG_MLDSA_ENTROPY_4 (32'h10030028) -`define MLDSA_REG_MLDSA_ENTROPY_4 (32'h28) `define CLP_MLDSA_REG_MLDSA_ENTROPY_5 (32'h1003002c) -`define MLDSA_REG_MLDSA_ENTROPY_5 (32'h2c) `define CLP_MLDSA_REG_MLDSA_ENTROPY_6 (32'h10030030) -`define MLDSA_REG_MLDSA_ENTROPY_6 (32'h30) `define CLP_MLDSA_REG_MLDSA_ENTROPY_7 (32'h10030034) -`define MLDSA_REG_MLDSA_ENTROPY_7 (32'h34) `define CLP_MLDSA_REG_MLDSA_ENTROPY_8 (32'h10030038) -`define MLDSA_REG_MLDSA_ENTROPY_8 (32'h38) `define CLP_MLDSA_REG_MLDSA_ENTROPY_9 (32'h1003003c) -`define MLDSA_REG_MLDSA_ENTROPY_9 (32'h3c) `define CLP_MLDSA_REG_MLDSA_ENTROPY_10 (32'h10030040) -`define MLDSA_REG_MLDSA_ENTROPY_10 (32'h40) `define CLP_MLDSA_REG_MLDSA_ENTROPY_11 (32'h10030044) -`define MLDSA_REG_MLDSA_ENTROPY_11 (32'h44) `define CLP_MLDSA_REG_MLDSA_ENTROPY_12 (32'h10030048) -`define MLDSA_REG_MLDSA_ENTROPY_12 (32'h48) `define CLP_MLDSA_REG_MLDSA_ENTROPY_13 (32'h1003004c) -`define MLDSA_REG_MLDSA_ENTROPY_13 (32'h4c) `define CLP_MLDSA_REG_MLDSA_ENTROPY_14 (32'h10030050) -`define MLDSA_REG_MLDSA_ENTROPY_14 (32'h50) `define CLP_MLDSA_REG_MLDSA_ENTROPY_15 (32'h10030054) -`define MLDSA_REG_MLDSA_ENTROPY_15 (32'h54) `define CLP_MLDSA_REG_MLDSA_SEED_0 (32'h10030058) -`define MLDSA_REG_MLDSA_SEED_0 (32'h58) `define CLP_MLDSA_REG_MLDSA_SEED_1 (32'h1003005c) -`define MLDSA_REG_MLDSA_SEED_1 (32'h5c) `define CLP_MLDSA_REG_MLDSA_SEED_2 (32'h10030060) -`define MLDSA_REG_MLDSA_SEED_2 (32'h60) `define CLP_MLDSA_REG_MLDSA_SEED_3 (32'h10030064) -`define MLDSA_REG_MLDSA_SEED_3 (32'h64) `define CLP_MLDSA_REG_MLDSA_SEED_4 (32'h10030068) -`define MLDSA_REG_MLDSA_SEED_4 (32'h68) `define CLP_MLDSA_REG_MLDSA_SEED_5 (32'h1003006c) -`define MLDSA_REG_MLDSA_SEED_5 (32'h6c) `define CLP_MLDSA_REG_MLDSA_SEED_6 (32'h10030070) -`define MLDSA_REG_MLDSA_SEED_6 (32'h70) `define CLP_MLDSA_REG_MLDSA_SEED_7 (32'h10030074) -`define MLDSA_REG_MLDSA_SEED_7 (32'h74) `define CLP_MLDSA_REG_MLDSA_SIGN_RND_0 (32'h10030078) -`define MLDSA_REG_MLDSA_SIGN_RND_0 (32'h78) `define CLP_MLDSA_REG_MLDSA_SIGN_RND_1 (32'h1003007c) -`define MLDSA_REG_MLDSA_SIGN_RND_1 (32'h7c) `define CLP_MLDSA_REG_MLDSA_SIGN_RND_2 (32'h10030080) -`define MLDSA_REG_MLDSA_SIGN_RND_2 (32'h80) `define CLP_MLDSA_REG_MLDSA_SIGN_RND_3 (32'h10030084) -`define MLDSA_REG_MLDSA_SIGN_RND_3 (32'h84) `define CLP_MLDSA_REG_MLDSA_SIGN_RND_4 (32'h10030088) -`define MLDSA_REG_MLDSA_SIGN_RND_4 (32'h88) `define CLP_MLDSA_REG_MLDSA_SIGN_RND_5 (32'h1003008c) -`define MLDSA_REG_MLDSA_SIGN_RND_5 (32'h8c) `define CLP_MLDSA_REG_MLDSA_SIGN_RND_6 (32'h10030090) -`define MLDSA_REG_MLDSA_SIGN_RND_6 (32'h90) `define CLP_MLDSA_REG_MLDSA_SIGN_RND_7 (32'h10030094) -`define MLDSA_REG_MLDSA_SIGN_RND_7 (32'h94) `define CLP_MLDSA_REG_MLDSA_MSG_0 (32'h10030098) -`define MLDSA_REG_MLDSA_MSG_0 (32'h98) `define CLP_MLDSA_REG_MLDSA_MSG_1 (32'h1003009c) -`define MLDSA_REG_MLDSA_MSG_1 (32'h9c) `define CLP_MLDSA_REG_MLDSA_MSG_2 (32'h100300a0) -`define MLDSA_REG_MLDSA_MSG_2 (32'ha0) `define CLP_MLDSA_REG_MLDSA_MSG_3 (32'h100300a4) -`define MLDSA_REG_MLDSA_MSG_3 (32'ha4) `define CLP_MLDSA_REG_MLDSA_MSG_4 (32'h100300a8) -`define MLDSA_REG_MLDSA_MSG_4 (32'ha8) `define CLP_MLDSA_REG_MLDSA_MSG_5 (32'h100300ac) -`define MLDSA_REG_MLDSA_MSG_5 (32'hac) `define CLP_MLDSA_REG_MLDSA_MSG_6 (32'h100300b0) -`define MLDSA_REG_MLDSA_MSG_6 (32'hb0) `define CLP_MLDSA_REG_MLDSA_MSG_7 (32'h100300b4) -`define MLDSA_REG_MLDSA_MSG_7 (32'hb4) `define CLP_MLDSA_REG_MLDSA_MSG_8 (32'h100300b8) -`define MLDSA_REG_MLDSA_MSG_8 (32'hb8) `define CLP_MLDSA_REG_MLDSA_MSG_9 (32'h100300bc) -`define MLDSA_REG_MLDSA_MSG_9 (32'hbc) `define CLP_MLDSA_REG_MLDSA_MSG_10 (32'h100300c0) -`define MLDSA_REG_MLDSA_MSG_10 (32'hc0) `define CLP_MLDSA_REG_MLDSA_MSG_11 (32'h100300c4) -`define MLDSA_REG_MLDSA_MSG_11 (32'hc4) `define CLP_MLDSA_REG_MLDSA_MSG_12 (32'h100300c8) -`define MLDSA_REG_MLDSA_MSG_12 (32'hc8) `define CLP_MLDSA_REG_MLDSA_MSG_13 (32'h100300cc) -`define MLDSA_REG_MLDSA_MSG_13 (32'hcc) `define CLP_MLDSA_REG_MLDSA_MSG_14 (32'h100300d0) -`define MLDSA_REG_MLDSA_MSG_14 (32'hd0) `define CLP_MLDSA_REG_MLDSA_MSG_15 (32'h100300d4) -`define MLDSA_REG_MLDSA_MSG_15 (32'hd4) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_0 (32'h100300d8) -`define MLDSA_REG_MLDSA_VERIFY_RES_0 (32'hd8) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_1 (32'h100300dc) -`define MLDSA_REG_MLDSA_VERIFY_RES_1 (32'hdc) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_2 (32'h100300e0) -`define MLDSA_REG_MLDSA_VERIFY_RES_2 (32'he0) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_3 (32'h100300e4) -`define MLDSA_REG_MLDSA_VERIFY_RES_3 (32'he4) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_4 (32'h100300e8) -`define MLDSA_REG_MLDSA_VERIFY_RES_4 (32'he8) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_5 (32'h100300ec) -`define MLDSA_REG_MLDSA_VERIFY_RES_5 (32'hec) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_6 (32'h100300f0) -`define MLDSA_REG_MLDSA_VERIFY_RES_6 (32'hf0) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_7 (32'h100300f4) -`define MLDSA_REG_MLDSA_VERIFY_RES_7 (32'hf4) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_8 (32'h100300f8) -`define MLDSA_REG_MLDSA_VERIFY_RES_8 (32'hf8) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_9 (32'h100300fc) -`define MLDSA_REG_MLDSA_VERIFY_RES_9 (32'hfc) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_10 (32'h10030100) -`define MLDSA_REG_MLDSA_VERIFY_RES_10 (32'h100) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_11 (32'h10030104) -`define MLDSA_REG_MLDSA_VERIFY_RES_11 (32'h104) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_12 (32'h10030108) -`define MLDSA_REG_MLDSA_VERIFY_RES_12 (32'h108) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_13 (32'h1003010c) -`define MLDSA_REG_MLDSA_VERIFY_RES_13 (32'h10c) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_14 (32'h10030110) -`define MLDSA_REG_MLDSA_VERIFY_RES_14 (32'h110) `define CLP_MLDSA_REG_MLDSA_VERIFY_RES_15 (32'h10030114) -`define MLDSA_REG_MLDSA_VERIFY_RES_15 (32'h114) `define CLP_MLDSA_REG_MLDSA_PUBKEY_BASE_ADDR (32'h10031000) `define CLP_MLDSA_REG_MLDSA_PUBKEY_END_ADDR (32'h10031a1f) `define CLP_MLDSA_REG_MLDSA_SIGNATURE_BASE_ADDR (32'h10032000) @@ -4695,1829 +1754,460 @@ `define CLP_MLDSA_REG_MLDSA_PRIVKEY_IN_BASE_ADDR (32'h10036000) `define CLP_MLDSA_REG_MLDSA_PRIVKEY_IN_END_ADDR (32'h1003731f) `define CLP_MLDSA_REG_MLDSA_KV_RD_SEED_CTRL (32'h10038000) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL (32'h8000) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_EN_LOW (0) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_EN_MASK (32'h1) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_ENTRY_LOW (1) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_ENTRY_MASK (32'h3e) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_LOW (6) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (32'h40) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_RSVD_LOW (7) -`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_RSVD_MASK (32'hffffff80) `define CLP_MLDSA_REG_MLDSA_KV_RD_SEED_STATUS (32'h10038004) -`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS (32'h8004) -`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_READY_LOW (0) -`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_READY_MASK (32'h1) -`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_VALID_LOW (1) -`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_VALID_MASK (32'h2) -`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_ERROR_LOW (2) -`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_ERROR_MASK (32'h3fc) `define CLP_MLDSA_REG_INTR_BLOCK_RF_START (32'h10038100) `define CLP_MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h10038100) -`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h8100) -`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h10038104) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h8104) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h10038108) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h8108) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h1003810c) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h810c) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h10038110) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h8110) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h10038114) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h8114) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h10038118) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h8118) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h1003811c) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h811c) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h10038120) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h8120) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h10038200) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h8200) `define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h10038280) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h8280) `define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'h10038300) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'h8300) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h10038304) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h8304) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_CSRNG_REG_BASE_ADDR (32'h20002000) `define CLP_CSRNG_REG_INTERRUPT_STATE (32'h20002000) -`define CSRNG_REG_INTERRUPT_STATE (32'h0) -`define CSRNG_REG_INTERRUPT_STATE_CS_CMD_REQ_DONE_LOW (0) -`define CSRNG_REG_INTERRUPT_STATE_CS_CMD_REQ_DONE_MASK (32'h1) -`define CSRNG_REG_INTERRUPT_STATE_CS_ENTROPY_REQ_LOW (1) -`define CSRNG_REG_INTERRUPT_STATE_CS_ENTROPY_REQ_MASK (32'h2) -`define CSRNG_REG_INTERRUPT_STATE_CS_HW_INST_EXC_LOW (2) -`define CSRNG_REG_INTERRUPT_STATE_CS_HW_INST_EXC_MASK (32'h4) -`define CSRNG_REG_INTERRUPT_STATE_CS_FATAL_ERR_LOW (3) -`define CSRNG_REG_INTERRUPT_STATE_CS_FATAL_ERR_MASK (32'h8) `define CLP_CSRNG_REG_INTERRUPT_ENABLE (32'h20002004) -`define CSRNG_REG_INTERRUPT_ENABLE (32'h4) -`define CSRNG_REG_INTERRUPT_ENABLE_CS_CMD_REQ_DONE_LOW (0) -`define CSRNG_REG_INTERRUPT_ENABLE_CS_CMD_REQ_DONE_MASK (32'h1) -`define CSRNG_REG_INTERRUPT_ENABLE_CS_ENTROPY_REQ_LOW (1) -`define CSRNG_REG_INTERRUPT_ENABLE_CS_ENTROPY_REQ_MASK (32'h2) -`define CSRNG_REG_INTERRUPT_ENABLE_CS_HW_INST_EXC_LOW (2) -`define CSRNG_REG_INTERRUPT_ENABLE_CS_HW_INST_EXC_MASK (32'h4) -`define CSRNG_REG_INTERRUPT_ENABLE_CS_FATAL_ERR_LOW (3) -`define CSRNG_REG_INTERRUPT_ENABLE_CS_FATAL_ERR_MASK (32'h8) `define CLP_CSRNG_REG_INTERRUPT_TEST (32'h20002008) -`define CSRNG_REG_INTERRUPT_TEST (32'h8) -`define CSRNG_REG_INTERRUPT_TEST_CS_CMD_REQ_DONE_LOW (0) -`define CSRNG_REG_INTERRUPT_TEST_CS_CMD_REQ_DONE_MASK (32'h1) -`define CSRNG_REG_INTERRUPT_TEST_CS_ENTROPY_REQ_LOW (1) -`define CSRNG_REG_INTERRUPT_TEST_CS_ENTROPY_REQ_MASK (32'h2) -`define CSRNG_REG_INTERRUPT_TEST_CS_HW_INST_EXC_LOW (2) -`define CSRNG_REG_INTERRUPT_TEST_CS_HW_INST_EXC_MASK (32'h4) -`define CSRNG_REG_INTERRUPT_TEST_CS_FATAL_ERR_LOW (3) -`define CSRNG_REG_INTERRUPT_TEST_CS_FATAL_ERR_MASK (32'h8) `define CLP_CSRNG_REG_ALERT_TEST (32'h2000200c) -`define CSRNG_REG_ALERT_TEST (32'hc) -`define CSRNG_REG_ALERT_TEST_RECOV_ALERT_LOW (0) -`define CSRNG_REG_ALERT_TEST_RECOV_ALERT_MASK (32'h1) -`define CSRNG_REG_ALERT_TEST_FATAL_ALERT_LOW (1) -`define CSRNG_REG_ALERT_TEST_FATAL_ALERT_MASK (32'h2) `define CLP_CSRNG_REG_REGWEN (32'h20002010) -`define CSRNG_REG_REGWEN (32'h10) -`define CSRNG_REG_REGWEN_REGWEN_LOW (0) -`define CSRNG_REG_REGWEN_REGWEN_MASK (32'h1) `define CLP_CSRNG_REG_CTRL (32'h20002014) -`define CSRNG_REG_CTRL (32'h14) -`define CSRNG_REG_CTRL_ENABLE_LOW (0) -`define CSRNG_REG_CTRL_ENABLE_MASK (32'hf) -`define CSRNG_REG_CTRL_SW_APP_ENABLE_LOW (4) -`define CSRNG_REG_CTRL_SW_APP_ENABLE_MASK (32'hf0) -`define CSRNG_REG_CTRL_READ_INT_STATE_LOW (8) -`define CSRNG_REG_CTRL_READ_INT_STATE_MASK (32'hf00) `define CLP_CSRNG_REG_CMD_REQ (32'h20002018) -`define CSRNG_REG_CMD_REQ (32'h18) -`define CSRNG_REG_CMD_REQ_ACMD_LOW (0) -`define CSRNG_REG_CMD_REQ_ACMD_MASK (32'hf) -`define CSRNG_REG_CMD_REQ_CLEN_LOW (4) -`define CSRNG_REG_CMD_REQ_CLEN_MASK (32'hf0) -`define CSRNG_REG_CMD_REQ_FLAG0_LOW (8) -`define CSRNG_REG_CMD_REQ_FLAG0_MASK (32'hf00) -`define CSRNG_REG_CMD_REQ_GLEN_LOW (12) -`define CSRNG_REG_CMD_REQ_GLEN_MASK (32'h1fff000) `define CLP_CSRNG_REG_SW_CMD_STS (32'h2000201c) -`define CSRNG_REG_SW_CMD_STS (32'h1c) -`define CSRNG_REG_SW_CMD_STS_CMD_RDY_LOW (0) -`define CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK (32'h1) -`define CSRNG_REG_SW_CMD_STS_CMD_STS_LOW (1) -`define CSRNG_REG_SW_CMD_STS_CMD_STS_MASK (32'h2) `define CLP_CSRNG_REG_GENBITS_VLD (32'h20002020) -`define CSRNG_REG_GENBITS_VLD (32'h20) -`define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_LOW (0) -`define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_MASK (32'h1) -`define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_LOW (1) -`define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_MASK (32'h2) `define CLP_CSRNG_REG_GENBITS (32'h20002024) -`define CSRNG_REG_GENBITS (32'h24) `define CLP_CSRNG_REG_INT_STATE_NUM (32'h20002028) -`define CSRNG_REG_INT_STATE_NUM (32'h28) -`define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_LOW (0) -`define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_MASK (32'hf) `define CLP_CSRNG_REG_INT_STATE_VAL (32'h2000202c) -`define CSRNG_REG_INT_STATE_VAL (32'h2c) `define CLP_CSRNG_REG_HW_EXC_STS (32'h20002030) -`define CSRNG_REG_HW_EXC_STS (32'h30) -`define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_LOW (0) -`define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_MASK (32'hffff) `define CLP_CSRNG_REG_RECOV_ALERT_STS (32'h20002034) -`define CSRNG_REG_RECOV_ALERT_STS (32'h34) -`define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_LOW (0) -`define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_MASK (32'h1) -`define CSRNG_REG_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_LOW (1) -`define CSRNG_REG_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_MASK (32'h2) -`define CSRNG_REG_RECOV_ALERT_STS_READ_INT_STATE_FIELD_ALERT_LOW (2) -`define CSRNG_REG_RECOV_ALERT_STS_READ_INT_STATE_FIELD_ALERT_MASK (32'h4) -`define CSRNG_REG_RECOV_ALERT_STS_ACMD_FLAG0_FIELD_ALERT_LOW (3) -`define CSRNG_REG_RECOV_ALERT_STS_ACMD_FLAG0_FIELD_ALERT_MASK (32'h8) -`define CSRNG_REG_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_LOW (12) -`define CSRNG_REG_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_MASK (32'h1000) -`define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_LOW (13) -`define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_MASK (32'h2000) `define CLP_CSRNG_REG_ERR_CODE (32'h20002038) -`define CSRNG_REG_ERR_CODE (32'h38) -`define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_LOW (0) -`define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_MASK (32'h1) -`define CSRNG_REG_ERR_CODE_SFIFO_GENBITS_ERR_LOW (1) -`define CSRNG_REG_ERR_CODE_SFIFO_GENBITS_ERR_MASK (32'h2) -`define CSRNG_REG_ERR_CODE_SFIFO_CMDREQ_ERR_LOW (2) -`define CSRNG_REG_ERR_CODE_SFIFO_CMDREQ_ERR_MASK (32'h4) -`define CSRNG_REG_ERR_CODE_SFIFO_RCSTAGE_ERR_LOW (3) -`define CSRNG_REG_ERR_CODE_SFIFO_RCSTAGE_ERR_MASK (32'h8) -`define CSRNG_REG_ERR_CODE_SFIFO_KEYVRC_ERR_LOW (4) -`define CSRNG_REG_ERR_CODE_SFIFO_KEYVRC_ERR_MASK (32'h10) -`define CSRNG_REG_ERR_CODE_SFIFO_UPDREQ_ERR_LOW (5) -`define CSRNG_REG_ERR_CODE_SFIFO_UPDREQ_ERR_MASK (32'h20) -`define CSRNG_REG_ERR_CODE_SFIFO_BENCREQ_ERR_LOW (6) -`define CSRNG_REG_ERR_CODE_SFIFO_BENCREQ_ERR_MASK (32'h40) -`define CSRNG_REG_ERR_CODE_SFIFO_BENCACK_ERR_LOW (7) -`define CSRNG_REG_ERR_CODE_SFIFO_BENCACK_ERR_MASK (32'h80) -`define CSRNG_REG_ERR_CODE_SFIFO_PDATA_ERR_LOW (8) -`define CSRNG_REG_ERR_CODE_SFIFO_PDATA_ERR_MASK (32'h100) -`define CSRNG_REG_ERR_CODE_SFIFO_FINAL_ERR_LOW (9) -`define CSRNG_REG_ERR_CODE_SFIFO_FINAL_ERR_MASK (32'h200) -`define CSRNG_REG_ERR_CODE_SFIFO_GBENCACK_ERR_LOW (10) -`define CSRNG_REG_ERR_CODE_SFIFO_GBENCACK_ERR_MASK (32'h400) -`define CSRNG_REG_ERR_CODE_SFIFO_GRCSTAGE_ERR_LOW (11) -`define CSRNG_REG_ERR_CODE_SFIFO_GRCSTAGE_ERR_MASK (32'h800) -`define CSRNG_REG_ERR_CODE_SFIFO_GGENREQ_ERR_LOW (12) -`define CSRNG_REG_ERR_CODE_SFIFO_GGENREQ_ERR_MASK (32'h1000) -`define CSRNG_REG_ERR_CODE_SFIFO_GADSTAGE_ERR_LOW (13) -`define CSRNG_REG_ERR_CODE_SFIFO_GADSTAGE_ERR_MASK (32'h2000) -`define CSRNG_REG_ERR_CODE_SFIFO_GGENBITS_ERR_LOW (14) -`define CSRNG_REG_ERR_CODE_SFIFO_GGENBITS_ERR_MASK (32'h4000) -`define CSRNG_REG_ERR_CODE_SFIFO_BLKENC_ERR_LOW (15) -`define CSRNG_REG_ERR_CODE_SFIFO_BLKENC_ERR_MASK (32'h8000) -`define CSRNG_REG_ERR_CODE_CMD_STAGE_SM_ERR_LOW (20) -`define CSRNG_REG_ERR_CODE_CMD_STAGE_SM_ERR_MASK (32'h100000) -`define CSRNG_REG_ERR_CODE_MAIN_SM_ERR_LOW (21) -`define CSRNG_REG_ERR_CODE_MAIN_SM_ERR_MASK (32'h200000) -`define CSRNG_REG_ERR_CODE_DRBG_GEN_SM_ERR_LOW (22) -`define CSRNG_REG_ERR_CODE_DRBG_GEN_SM_ERR_MASK (32'h400000) -`define CSRNG_REG_ERR_CODE_DRBG_UPDBE_SM_ERR_LOW (23) -`define CSRNG_REG_ERR_CODE_DRBG_UPDBE_SM_ERR_MASK (32'h800000) -`define CSRNG_REG_ERR_CODE_DRBG_UPDOB_SM_ERR_LOW (24) -`define CSRNG_REG_ERR_CODE_DRBG_UPDOB_SM_ERR_MASK (32'h1000000) -`define CSRNG_REG_ERR_CODE_AES_CIPHER_SM_ERR_LOW (25) -`define CSRNG_REG_ERR_CODE_AES_CIPHER_SM_ERR_MASK (32'h2000000) -`define CSRNG_REG_ERR_CODE_CMD_GEN_CNT_ERR_LOW (26) -`define CSRNG_REG_ERR_CODE_CMD_GEN_CNT_ERR_MASK (32'h4000000) -`define CSRNG_REG_ERR_CODE_FIFO_WRITE_ERR_LOW (28) -`define CSRNG_REG_ERR_CODE_FIFO_WRITE_ERR_MASK (32'h10000000) -`define CSRNG_REG_ERR_CODE_FIFO_READ_ERR_LOW (29) -`define CSRNG_REG_ERR_CODE_FIFO_READ_ERR_MASK (32'h20000000) -`define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30) -`define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_MASK (32'h40000000) `define CLP_CSRNG_REG_ERR_CODE_TEST (32'h2000203c) -`define CSRNG_REG_ERR_CODE_TEST (32'h3c) -`define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0) -`define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (32'h1f) `define CLP_CSRNG_REG_MAIN_SM_STATE (32'h20002040) -`define CSRNG_REG_MAIN_SM_STATE (32'h40) -`define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) -`define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (32'hff) `define CLP_ENTROPY_SRC_REG_BASE_ADDR (32'h20003000) `define CLP_ENTROPY_SRC_REG_INTERRUPT_STATE (32'h20003000) -`define ENTROPY_SRC_REG_INTERRUPT_STATE (32'h0) -`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_ENTROPY_VALID_LOW (0) -`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_ENTROPY_VALID_MASK (32'h1) -`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_HEALTH_TEST_FAILED_LOW (1) -`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_HEALTH_TEST_FAILED_MASK (32'h2) -`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_OBSERVE_FIFO_READY_LOW (2) -`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_OBSERVE_FIFO_READY_MASK (32'h4) -`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_FATAL_ERR_LOW (3) -`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_FATAL_ERR_MASK (32'h8) `define CLP_ENTROPY_SRC_REG_INTERRUPT_ENABLE (32'h20003004) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE (32'h4) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_ENTROPY_VALID_LOW (0) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_ENTROPY_VALID_MASK (32'h1) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_HEALTH_TEST_FAILED_LOW (1) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_HEALTH_TEST_FAILED_MASK (32'h2) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_OBSERVE_FIFO_READY_LOW (2) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_OBSERVE_FIFO_READY_MASK (32'h4) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_FATAL_ERR_LOW (3) -`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_FATAL_ERR_MASK (32'h8) `define CLP_ENTROPY_SRC_REG_INTERRUPT_TEST (32'h20003008) -`define ENTROPY_SRC_REG_INTERRUPT_TEST (32'h8) -`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_ENTROPY_VALID_LOW (0) -`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_ENTROPY_VALID_MASK (32'h1) -`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_HEALTH_TEST_FAILED_LOW (1) -`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_HEALTH_TEST_FAILED_MASK (32'h2) -`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_OBSERVE_FIFO_READY_LOW (2) -`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_OBSERVE_FIFO_READY_MASK (32'h4) -`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_FATAL_ERR_LOW (3) -`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_FATAL_ERR_MASK (32'h8) `define CLP_ENTROPY_SRC_REG_ALERT_TEST (32'h2000300c) -`define ENTROPY_SRC_REG_ALERT_TEST (32'hc) -`define ENTROPY_SRC_REG_ALERT_TEST_RECOV_ALERT_LOW (0) -`define ENTROPY_SRC_REG_ALERT_TEST_RECOV_ALERT_MASK (32'h1) -`define ENTROPY_SRC_REG_ALERT_TEST_FATAL_ALERT_LOW (1) -`define ENTROPY_SRC_REG_ALERT_TEST_FATAL_ALERT_MASK (32'h2) `define CLP_ENTROPY_SRC_REG_ME_REGWEN (32'h20003010) -`define ENTROPY_SRC_REG_ME_REGWEN (32'h10) -`define ENTROPY_SRC_REG_ME_REGWEN_ME_REGWEN_LOW (0) -`define ENTROPY_SRC_REG_ME_REGWEN_ME_REGWEN_MASK (32'h1) `define CLP_ENTROPY_SRC_REG_SW_REGUPD (32'h20003014) -`define ENTROPY_SRC_REG_SW_REGUPD (32'h14) -`define ENTROPY_SRC_REG_SW_REGUPD_SW_REGUPD_LOW (0) -`define ENTROPY_SRC_REG_SW_REGUPD_SW_REGUPD_MASK (32'h1) `define CLP_ENTROPY_SRC_REG_REGWEN (32'h20003018) -`define ENTROPY_SRC_REG_REGWEN (32'h18) -`define ENTROPY_SRC_REG_REGWEN_REGWEN_LOW (0) -`define ENTROPY_SRC_REG_REGWEN_REGWEN_MASK (32'h1) `define CLP_ENTROPY_SRC_REG_REV (32'h2000301c) -`define ENTROPY_SRC_REG_REV (32'h1c) -`define ENTROPY_SRC_REG_REV_ABI_REVISION_LOW (0) -`define ENTROPY_SRC_REG_REV_ABI_REVISION_MASK (32'hff) -`define ENTROPY_SRC_REG_REV_HW_REVISION_LOW (8) -`define ENTROPY_SRC_REG_REV_HW_REVISION_MASK (32'hff00) -`define ENTROPY_SRC_REG_REV_CHIP_TYPE_LOW (16) -`define ENTROPY_SRC_REG_REV_CHIP_TYPE_MASK (32'hff0000) `define CLP_ENTROPY_SRC_REG_MODULE_ENABLE (32'h20003020) -`define ENTROPY_SRC_REG_MODULE_ENABLE (32'h20) -`define ENTROPY_SRC_REG_MODULE_ENABLE_MODULE_ENABLE_LOW (0) -`define ENTROPY_SRC_REG_MODULE_ENABLE_MODULE_ENABLE_MASK (32'hf) `define CLP_ENTROPY_SRC_REG_CONF (32'h20003024) -`define ENTROPY_SRC_REG_CONF (32'h24) -`define ENTROPY_SRC_REG_CONF_FIPS_ENABLE_LOW (0) -`define ENTROPY_SRC_REG_CONF_FIPS_ENABLE_MASK (32'hf) -`define ENTROPY_SRC_REG_CONF_ENTROPY_DATA_REG_ENABLE_LOW (4) -`define ENTROPY_SRC_REG_CONF_ENTROPY_DATA_REG_ENABLE_MASK (32'hf0) -`define ENTROPY_SRC_REG_CONF_THRESHOLD_SCOPE_LOW (12) -`define ENTROPY_SRC_REG_CONF_THRESHOLD_SCOPE_MASK (32'hf000) -`define ENTROPY_SRC_REG_CONF_RNG_BIT_ENABLE_LOW (20) -`define ENTROPY_SRC_REG_CONF_RNG_BIT_ENABLE_MASK (32'hf00000) -`define ENTROPY_SRC_REG_CONF_RNG_BIT_SEL_LOW (24) -`define ENTROPY_SRC_REG_CONF_RNG_BIT_SEL_MASK (32'h3000000) `define CLP_ENTROPY_SRC_REG_ENTROPY_CONTROL (32'h20003028) -`define ENTROPY_SRC_REG_ENTROPY_CONTROL (32'h28) -`define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_ROUTE_LOW (0) -`define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_ROUTE_MASK (32'hf) -`define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_TYPE_LOW (4) -`define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_TYPE_MASK (32'hf0) `define CLP_ENTROPY_SRC_REG_ENTROPY_DATA (32'h2000302c) -`define ENTROPY_SRC_REG_ENTROPY_DATA (32'h2c) `define CLP_ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS (32'h20003030) -`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS (32'h30) -`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_FIPS_WINDOW_LOW (0) -`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_FIPS_WINDOW_MASK (32'hffff) -`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_LOW (16) -`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_REPCNT_THRESHOLDS (32'h20003034) -`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS (32'h34) -`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_REPCNTS_THRESHOLDS (32'h20003038) -`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS (32'h38) -`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS (32'h2000303c) -`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS (32'h3c) -`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS (32'h20003040) -`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS (32'h40) -`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_BUCKET_THRESHOLDS (32'h20003044) -`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS (32'h44) -`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS (32'h20003048) -`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS (32'h48) -`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS (32'h2000304c) -`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS (32'h4c) -`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS (32'h20003050) -`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS (32'h50) -`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS (32'h20003054) -`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS (32'h54) -`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_FIPS_THRESH_LOW (0) -`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) -`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) -`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS (32'h20003058) -`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS (32'h58) -`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS (32'h2000305c) -`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS (32'h5c) -`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS (32'h20003060) -`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS (32'h60) -`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS (32'h20003064) -`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS (32'h64) -`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS (32'h20003068) -`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS (32'h68) -`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS (32'h2000306c) -`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS (32'h6c) -`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS (32'h20003070) -`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS (32'h70) -`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS (32'h20003074) -`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS (32'h74) -`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS (32'h20003078) -`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS (32'h78) -`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) -`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) -`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) -`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_REPCNT_TOTAL_FAILS (32'h2000307c) -`define ENTROPY_SRC_REG_REPCNT_TOTAL_FAILS (32'h7c) `define CLP_ENTROPY_SRC_REG_REPCNTS_TOTAL_FAILS (32'h20003080) -`define ENTROPY_SRC_REG_REPCNTS_TOTAL_FAILS (32'h80) `define CLP_ENTROPY_SRC_REG_ADAPTP_HI_TOTAL_FAILS (32'h20003084) -`define ENTROPY_SRC_REG_ADAPTP_HI_TOTAL_FAILS (32'h84) `define CLP_ENTROPY_SRC_REG_ADAPTP_LO_TOTAL_FAILS (32'h20003088) -`define ENTROPY_SRC_REG_ADAPTP_LO_TOTAL_FAILS (32'h88) `define CLP_ENTROPY_SRC_REG_BUCKET_TOTAL_FAILS (32'h2000308c) -`define ENTROPY_SRC_REG_BUCKET_TOTAL_FAILS (32'h8c) `define CLP_ENTROPY_SRC_REG_MARKOV_HI_TOTAL_FAILS (32'h20003090) -`define ENTROPY_SRC_REG_MARKOV_HI_TOTAL_FAILS (32'h90) `define CLP_ENTROPY_SRC_REG_MARKOV_LO_TOTAL_FAILS (32'h20003094) -`define ENTROPY_SRC_REG_MARKOV_LO_TOTAL_FAILS (32'h94) `define CLP_ENTROPY_SRC_REG_EXTHT_HI_TOTAL_FAILS (32'h20003098) -`define ENTROPY_SRC_REG_EXTHT_HI_TOTAL_FAILS (32'h98) `define CLP_ENTROPY_SRC_REG_EXTHT_LO_TOTAL_FAILS (32'h2000309c) -`define ENTROPY_SRC_REG_EXTHT_LO_TOTAL_FAILS (32'h9c) `define CLP_ENTROPY_SRC_REG_ALERT_THRESHOLD (32'h200030a0) -`define ENTROPY_SRC_REG_ALERT_THRESHOLD (32'ha0) -`define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_LOW (0) -`define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_MASK (32'hffff) -`define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_LOW (16) -`define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_MASK (32'hffff0000) `define CLP_ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS (32'h200030a4) -`define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS (32'ha4) -`define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_LOW (0) -`define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_MASK (32'hffff) `define CLP_ENTROPY_SRC_REG_ALERT_FAIL_COUNTS (32'h200030a8) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS (32'ha8) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_LOW (4) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_MASK (32'hf0) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_LOW (8) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_MASK (32'hf00) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_LOW (12) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_MASK (32'hf000) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_LOW (16) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_MASK (32'hf0000) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_LOW (20) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_MASK (32'hf00000) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_LOW (24) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_MASK (32'hf000000) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_LOW (28) -`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_MASK (32'hf0000000) `define CLP_ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS (32'h200030ac) -`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS (32'hac) -`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_LOW (0) -`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_MASK (32'hf) -`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_LOW (4) -`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_MASK (32'hf0) `define CLP_ENTROPY_SRC_REG_FW_OV_CONTROL (32'h200030b0) -`define ENTROPY_SRC_REG_FW_OV_CONTROL (32'hb0) -`define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_MODE_LOW (0) -`define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_MODE_MASK (32'hf) -`define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_LOW (4) -`define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK (32'hf0) `define CLP_ENTROPY_SRC_REG_FW_OV_SHA3_START (32'h200030b4) -`define ENTROPY_SRC_REG_FW_OV_SHA3_START (32'hb4) -`define ENTROPY_SRC_REG_FW_OV_SHA3_START_FW_OV_INSERT_START_LOW (0) -`define ENTROPY_SRC_REG_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK (32'hf) `define CLP_ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL (32'h200030b8) -`define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL (32'hb8) -`define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_LOW (0) -`define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_MASK (32'h1) `define CLP_ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW (32'h200030bc) -`define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW (32'hbc) -`define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_LOW (0) -`define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_MASK (32'h1) `define CLP_ENTROPY_SRC_REG_FW_OV_RD_DATA (32'h200030c0) -`define ENTROPY_SRC_REG_FW_OV_RD_DATA (32'hc0) `define CLP_ENTROPY_SRC_REG_FW_OV_WR_DATA (32'h200030c4) -`define ENTROPY_SRC_REG_FW_OV_WR_DATA (32'hc4) `define CLP_ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH (32'h200030c8) -`define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH (32'hc8) -`define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_LOW (0) -`define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK (32'h7f) `define CLP_ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH (32'h200030cc) -`define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH (32'hcc) -`define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_LOW (0) -`define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_MASK (32'h7f) `define CLP_ENTROPY_SRC_REG_DEBUG_STATUS (32'h200030d0) -`define ENTROPY_SRC_REG_DEBUG_STATUS (32'hd0) -`define ENTROPY_SRC_REG_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_LOW (0) -`define ENTROPY_SRC_REG_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_MASK (32'h7) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_FSM_LOW (3) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_FSM_MASK (32'h38) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_BLOCK_PR_LOW (6) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_BLOCK_PR_MASK (32'h40) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_SQUEEZING_LOW (7) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_SQUEEZING_MASK (32'h80) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_ABSORBED_LOW (8) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_ABSORBED_MASK (32'h100) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_ERR_LOW (9) -`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_ERR_MASK (32'h200) -`define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_IDLE_LOW (16) -`define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_IDLE_MASK (32'h10000) -`define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_BOOT_DONE_LOW (17) -`define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_BOOT_DONE_MASK (32'h20000) `define CLP_ENTROPY_SRC_REG_RECOV_ALERT_STS (32'h200030d4) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS (32'hd4) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_LOW (0) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_MASK (32'h1) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ENTROPY_DATA_REG_EN_FIELD_ALERT_LOW (1) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ENTROPY_DATA_REG_EN_FIELD_ALERT_MASK (32'h2) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_MODULE_ENABLE_FIELD_ALERT_LOW (2) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_MODULE_ENABLE_FIELD_ALERT_MASK (32'h4) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_THRESHOLD_SCOPE_FIELD_ALERT_LOW (3) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_THRESHOLD_SCOPE_FIELD_ALERT_MASK (32'h8) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_RNG_BIT_ENABLE_FIELD_ALERT_LOW (5) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_RNG_BIT_ENABLE_FIELD_ALERT_MASK (32'h20) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_SHA3_START_FIELD_ALERT_LOW (7) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_SHA3_START_FIELD_ALERT_MASK (32'h80) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_MODE_FIELD_ALERT_LOW (8) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_MODE_FIELD_ALERT_MASK (32'h100) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_ENTROPY_INSERT_FIELD_ALERT_LOW (9) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_ENTROPY_INSERT_FIELD_ALERT_MASK (32'h200) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_ROUTE_FIELD_ALERT_LOW (10) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_ROUTE_FIELD_ALERT_MASK (32'h400) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_TYPE_FIELD_ALERT_LOW (11) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_TYPE_FIELD_ALERT_MASK (32'h800) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_MAIN_SM_ALERT_LOW (12) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_MAIN_SM_ALERT_MASK (32'h1000) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_BUS_CMP_ALERT_LOW (13) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_BUS_CMP_ALERT_MASK (32'h2000) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_THRESH_CFG_ALERT_LOW (14) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_THRESH_CFG_ALERT_MASK (32'h4000) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_LOW (15) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_MASK (32'h8000) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_LOW (16) -`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_MASK (32'h10000) `define CLP_ENTROPY_SRC_REG_ERR_CODE (32'h200030d8) -`define ENTROPY_SRC_REG_ERR_CODE (32'hd8) -`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESRNG_ERR_LOW (0) -`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESRNG_ERR_MASK (32'h1) -`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_OBSERVE_ERR_LOW (1) -`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_OBSERVE_ERR_MASK (32'h2) -`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESFINAL_ERR_LOW (2) -`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESFINAL_ERR_MASK (32'h4) -`define ENTROPY_SRC_REG_ERR_CODE_ES_ACK_SM_ERR_LOW (20) -`define ENTROPY_SRC_REG_ERR_CODE_ES_ACK_SM_ERR_MASK (32'h100000) -`define ENTROPY_SRC_REG_ERR_CODE_ES_MAIN_SM_ERR_LOW (21) -`define ENTROPY_SRC_REG_ERR_CODE_ES_MAIN_SM_ERR_MASK (32'h200000) -`define ENTROPY_SRC_REG_ERR_CODE_ES_CNTR_ERR_LOW (22) -`define ENTROPY_SRC_REG_ERR_CODE_ES_CNTR_ERR_MASK (32'h400000) -`define ENTROPY_SRC_REG_ERR_CODE_SHA3_STATE_ERR_LOW (23) -`define ENTROPY_SRC_REG_ERR_CODE_SHA3_STATE_ERR_MASK (32'h800000) -`define ENTROPY_SRC_REG_ERR_CODE_SHA3_RST_STORAGE_ERR_LOW (24) -`define ENTROPY_SRC_REG_ERR_CODE_SHA3_RST_STORAGE_ERR_MASK (32'h1000000) -`define ENTROPY_SRC_REG_ERR_CODE_FIFO_WRITE_ERR_LOW (28) -`define ENTROPY_SRC_REG_ERR_CODE_FIFO_WRITE_ERR_MASK (32'h10000000) -`define ENTROPY_SRC_REG_ERR_CODE_FIFO_READ_ERR_LOW (29) -`define ENTROPY_SRC_REG_ERR_CODE_FIFO_READ_ERR_MASK (32'h20000000) -`define ENTROPY_SRC_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30) -`define ENTROPY_SRC_REG_ERR_CODE_FIFO_STATE_ERR_MASK (32'h40000000) `define CLP_ENTROPY_SRC_REG_ERR_CODE_TEST (32'h200030dc) -`define ENTROPY_SRC_REG_ERR_CODE_TEST (32'hdc) -`define ENTROPY_SRC_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0) -`define ENTROPY_SRC_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (32'h1f) `define CLP_ENTROPY_SRC_REG_MAIN_SM_STATE (32'h200030e0) -`define ENTROPY_SRC_REG_MAIN_SM_STATE (32'he0) -`define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) -`define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (32'h1ff) `define CLP_MBOX_CSR_BASE_ADDR (32'h30020000) `define CLP_MBOX_CSR_MBOX_LOCK (32'h30020000) -`define MBOX_CSR_MBOX_LOCK (32'h0) -`define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) -`define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) `define CLP_MBOX_CSR_MBOX_USER (32'h30020004) -`define MBOX_CSR_MBOX_USER (32'h4) `define CLP_MBOX_CSR_MBOX_CMD (32'h30020008) -`define MBOX_CSR_MBOX_CMD (32'h8) `define CLP_MBOX_CSR_MBOX_DLEN (32'h3002000c) -`define MBOX_CSR_MBOX_DLEN (32'hc) `define CLP_MBOX_CSR_MBOX_DATAIN (32'h30020010) -`define MBOX_CSR_MBOX_DATAIN (32'h10) `define CLP_MBOX_CSR_MBOX_DATAOUT (32'h30020014) -`define MBOX_CSR_MBOX_DATAOUT (32'h14) `define CLP_MBOX_CSR_MBOX_EXECUTE (32'h30020018) -`define MBOX_CSR_MBOX_EXECUTE (32'h18) -`define MBOX_CSR_MBOX_EXECUTE_EXECUTE_LOW (0) -`define MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK (32'h1) `define CLP_MBOX_CSR_MBOX_STATUS (32'h3002001c) -`define MBOX_CSR_MBOX_STATUS (32'h1c) -`define MBOX_CSR_MBOX_STATUS_STATUS_LOW (0) -`define MBOX_CSR_MBOX_STATUS_STATUS_MASK (32'hf) -`define MBOX_CSR_MBOX_STATUS_ECC_SINGLE_ERROR_LOW (4) -`define MBOX_CSR_MBOX_STATUS_ECC_SINGLE_ERROR_MASK (32'h10) -`define MBOX_CSR_MBOX_STATUS_ECC_DOUBLE_ERROR_LOW (5) -`define MBOX_CSR_MBOX_STATUS_ECC_DOUBLE_ERROR_MASK (32'h20) -`define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW (6) -`define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK (32'h1c0) -`define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW (9) -`define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (32'h200) -`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) -`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h3fffc00) `define CLP_MBOX_CSR_MBOX_UNLOCK (32'h30020020) -`define MBOX_CSR_MBOX_UNLOCK (32'h20) -`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) -`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (32'h1) `define CLP_MBOX_CSR_TAP_MODE (32'h30020024) -`define MBOX_CSR_TAP_MODE (32'h24) -`define MBOX_CSR_TAP_MODE_ENABLED_LOW (0) -`define MBOX_CSR_TAP_MODE_ENABLED_MASK (32'h1) `define CLP_SHA512_ACC_CSR_BASE_ADDR (32'h30021000) `define CLP_SHA512_ACC_CSR_LOCK (32'h30021000) -`define SHA512_ACC_CSR_LOCK (32'h0) -`define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) -`define SHA512_ACC_CSR_LOCK_LOCK_MASK (32'h1) `define CLP_SHA512_ACC_CSR_USER (32'h30021004) -`define SHA512_ACC_CSR_USER (32'h4) `define CLP_SHA512_ACC_CSR_MODE (32'h30021008) -`define SHA512_ACC_CSR_MODE (32'h8) -`define SHA512_ACC_CSR_MODE_MODE_LOW (0) -`define SHA512_ACC_CSR_MODE_MODE_MASK (32'h3) -`define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_LOW (2) -`define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_MASK (32'h4) `define CLP_SHA512_ACC_CSR_START_ADDRESS (32'h3002100c) -`define SHA512_ACC_CSR_START_ADDRESS (32'hc) `define CLP_SHA512_ACC_CSR_DLEN (32'h30021010) -`define SHA512_ACC_CSR_DLEN (32'h10) `define CLP_SHA512_ACC_CSR_DATAIN (32'h30021014) -`define SHA512_ACC_CSR_DATAIN (32'h14) `define CLP_SHA512_ACC_CSR_EXECUTE (32'h30021018) -`define SHA512_ACC_CSR_EXECUTE (32'h18) -`define SHA512_ACC_CSR_EXECUTE_EXECUTE_LOW (0) -`define SHA512_ACC_CSR_EXECUTE_EXECUTE_MASK (32'h1) `define CLP_SHA512_ACC_CSR_STATUS (32'h3002101c) -`define SHA512_ACC_CSR_STATUS (32'h1c) -`define SHA512_ACC_CSR_STATUS_VALID_LOW (0) -`define SHA512_ACC_CSR_STATUS_VALID_MASK (32'h1) -`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW (1) -`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK (32'h2) `define CLP_SHA512_ACC_CSR_DIGEST_0 (32'h30021020) -`define SHA512_ACC_CSR_DIGEST_0 (32'h20) `define CLP_SHA512_ACC_CSR_DIGEST_1 (32'h30021024) -`define SHA512_ACC_CSR_DIGEST_1 (32'h24) `define CLP_SHA512_ACC_CSR_DIGEST_2 (32'h30021028) -`define SHA512_ACC_CSR_DIGEST_2 (32'h28) `define CLP_SHA512_ACC_CSR_DIGEST_3 (32'h3002102c) -`define SHA512_ACC_CSR_DIGEST_3 (32'h2c) `define CLP_SHA512_ACC_CSR_DIGEST_4 (32'h30021030) -`define SHA512_ACC_CSR_DIGEST_4 (32'h30) `define CLP_SHA512_ACC_CSR_DIGEST_5 (32'h30021034) -`define SHA512_ACC_CSR_DIGEST_5 (32'h34) `define CLP_SHA512_ACC_CSR_DIGEST_6 (32'h30021038) -`define SHA512_ACC_CSR_DIGEST_6 (32'h38) `define CLP_SHA512_ACC_CSR_DIGEST_7 (32'h3002103c) -`define SHA512_ACC_CSR_DIGEST_7 (32'h3c) `define CLP_SHA512_ACC_CSR_DIGEST_8 (32'h30021040) -`define SHA512_ACC_CSR_DIGEST_8 (32'h40) `define CLP_SHA512_ACC_CSR_DIGEST_9 (32'h30021044) -`define SHA512_ACC_CSR_DIGEST_9 (32'h44) `define CLP_SHA512_ACC_CSR_DIGEST_10 (32'h30021048) -`define SHA512_ACC_CSR_DIGEST_10 (32'h48) `define CLP_SHA512_ACC_CSR_DIGEST_11 (32'h3002104c) -`define SHA512_ACC_CSR_DIGEST_11 (32'h4c) `define CLP_SHA512_ACC_CSR_DIGEST_12 (32'h30021050) -`define SHA512_ACC_CSR_DIGEST_12 (32'h50) `define CLP_SHA512_ACC_CSR_DIGEST_13 (32'h30021054) -`define SHA512_ACC_CSR_DIGEST_13 (32'h54) `define CLP_SHA512_ACC_CSR_DIGEST_14 (32'h30021058) -`define SHA512_ACC_CSR_DIGEST_14 (32'h58) `define CLP_SHA512_ACC_CSR_DIGEST_15 (32'h3002105c) -`define SHA512_ACC_CSR_DIGEST_15 (32'h5c) `define CLP_SHA512_ACC_CSR_CONTROL (32'h30021060) -`define SHA512_ACC_CSR_CONTROL (32'h60) -`define SHA512_ACC_CSR_CONTROL_ZEROIZE_LOW (0) -`define SHA512_ACC_CSR_CONTROL_ZEROIZE_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_START (32'h30021800) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h30021800) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h30021804) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h30021808) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h3002180c) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h30021810) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h30021814) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h30021818) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h3002181c) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h30021820) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h30021900) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h30021904) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h30021908) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h3002190c) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h30021980) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'h30021a00) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'h30021a04) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'h30021a08) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'h30021a0c) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h30021a10) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_BASE_ADDR (32'h30022000) `define CLP_AXI_DMA_REG_ID (32'h30022000) -`define AXI_DMA_REG_ID (32'h0) `define CLP_AXI_DMA_REG_CAP (32'h30022004) -`define AXI_DMA_REG_CAP (32'h4) -`define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW (0) -`define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK (32'hfff) -`define AXI_DMA_REG_CAP_RSVD_LOW (12) -`define AXI_DMA_REG_CAP_RSVD_MASK (32'hfffff000) `define CLP_AXI_DMA_REG_CTRL (32'h30022008) -`define AXI_DMA_REG_CTRL (32'h8) -`define AXI_DMA_REG_CTRL_GO_LOW (0) -`define AXI_DMA_REG_CTRL_GO_MASK (32'h1) -`define AXI_DMA_REG_CTRL_FLUSH_LOW (1) -`define AXI_DMA_REG_CTRL_FLUSH_MASK (32'h2) -`define AXI_DMA_REG_CTRL_RSVD0_LOW (2) -`define AXI_DMA_REG_CTRL_RSVD0_MASK (32'hfffc) -`define AXI_DMA_REG_CTRL_RD_ROUTE_LOW (16) -`define AXI_DMA_REG_CTRL_RD_ROUTE_MASK (32'h30000) -`define AXI_DMA_REG_CTRL_RSVD1_LOW (18) -`define AXI_DMA_REG_CTRL_RSVD1_MASK (32'hc0000) -`define AXI_DMA_REG_CTRL_RD_FIXED_LOW (20) -`define AXI_DMA_REG_CTRL_RD_FIXED_MASK (32'h100000) -`define AXI_DMA_REG_CTRL_RSVD2_LOW (21) -`define AXI_DMA_REG_CTRL_RSVD2_MASK (32'he00000) -`define AXI_DMA_REG_CTRL_WR_ROUTE_LOW (24) -`define AXI_DMA_REG_CTRL_WR_ROUTE_MASK (32'h3000000) -`define AXI_DMA_REG_CTRL_RSVD3_LOW (26) -`define AXI_DMA_REG_CTRL_RSVD3_MASK (32'hc000000) -`define AXI_DMA_REG_CTRL_WR_FIXED_LOW (28) -`define AXI_DMA_REG_CTRL_WR_FIXED_MASK (32'h10000000) -`define AXI_DMA_REG_CTRL_RSVD4_LOW (29) -`define AXI_DMA_REG_CTRL_RSVD4_MASK (32'he0000000) `define CLP_AXI_DMA_REG_STATUS0 (32'h3002200c) -`define AXI_DMA_REG_STATUS0 (32'hc) -`define AXI_DMA_REG_STATUS0_BUSY_LOW (0) -`define AXI_DMA_REG_STATUS0_BUSY_MASK (32'h1) -`define AXI_DMA_REG_STATUS0_ERROR_LOW (1) -`define AXI_DMA_REG_STATUS0_ERROR_MASK (32'h2) -`define AXI_DMA_REG_STATUS0_RSVD0_LOW (2) -`define AXI_DMA_REG_STATUS0_RSVD0_MASK (32'hc) -`define AXI_DMA_REG_STATUS0_FIFO_DEPTH_LOW (4) -`define AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK (32'hfff0) -`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW (16) -`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK (32'h30000) -`define AXI_DMA_REG_STATUS0_PAYLOAD_AVAILABLE_LOW (18) -`define AXI_DMA_REG_STATUS0_PAYLOAD_AVAILABLE_MASK (32'h40000) -`define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_LOW (19) -`define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_MASK (32'h80000) -`define AXI_DMA_REG_STATUS0_RSVD1_LOW (20) -`define AXI_DMA_REG_STATUS0_RSVD1_MASK (32'hfff00000) `define CLP_AXI_DMA_REG_STATUS1 (32'h30022010) -`define AXI_DMA_REG_STATUS1 (32'h10) `define CLP_AXI_DMA_REG_SRC_ADDR_L (32'h30022014) -`define AXI_DMA_REG_SRC_ADDR_L (32'h14) `define CLP_AXI_DMA_REG_SRC_ADDR_H (32'h30022018) -`define AXI_DMA_REG_SRC_ADDR_H (32'h18) `define CLP_AXI_DMA_REG_DST_ADDR_L (32'h3002201c) -`define AXI_DMA_REG_DST_ADDR_L (32'h1c) `define CLP_AXI_DMA_REG_DST_ADDR_H (32'h30022020) -`define AXI_DMA_REG_DST_ADDR_H (32'h20) `define CLP_AXI_DMA_REG_BYTE_COUNT (32'h30022024) -`define AXI_DMA_REG_BYTE_COUNT (32'h24) `define CLP_AXI_DMA_REG_BLOCK_SIZE (32'h30022028) -`define AXI_DMA_REG_BLOCK_SIZE (32'h28) -`define AXI_DMA_REG_BLOCK_SIZE_SIZE_LOW (0) -`define AXI_DMA_REG_BLOCK_SIZE_SIZE_MASK (32'hfff) -`define AXI_DMA_REG_BLOCK_SIZE_RSVD_LOW (12) -`define AXI_DMA_REG_BLOCK_SIZE_RSVD_MASK (32'hfffff000) `define CLP_AXI_DMA_REG_WRITE_DATA (32'h3002202c) -`define AXI_DMA_REG_WRITE_DATA (32'h2c) `define CLP_AXI_DMA_REG_READ_DATA (32'h30022030) -`define AXI_DMA_REG_READ_DATA (32'h30) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_START (32'h30022800) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h30022800) -`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h30022804) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK (32'h1) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_LOW (1) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_MASK (32'h2) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_LOW (2) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_MASK (32'h4) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_LOW (3) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_MASK (32'h8) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_LOW (4) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_MASK (32'h10) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_LOW (5) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK (32'h20) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_LOW (6) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK (32'h40) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h30022808) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK (32'h1) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_LOW (1) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_MASK (32'h2) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_LOW (2) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_MASK (32'h4) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_LOW (3) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK (32'h8) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_LOW (4) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK (32'h10) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h3002280c) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h30022810) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h30022814) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK (32'h1) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_LOW (1) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK (32'h2) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_LOW (2) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK (32'h4) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_LOW (3) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK (32'h8) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_LOW (4) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK (32'h10) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_LOW (5) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK (32'h20) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_LOW (6) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK (32'h40) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h30022818) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK (32'h1) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_LOW (1) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK (32'h2) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_LOW (2) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK (32'h4) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_LOW (3) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK (32'h8) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_LOW (4) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK (32'h10) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h3002281c) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_MASK (32'h1) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_LOW (1) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_MASK (32'h2) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_LOW (2) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_MASK (32'h4) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_LOW (3) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_MASK (32'h8) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_LOW (4) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_MASK (32'h10) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_LOW (5) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_MASK (32'h20) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_LOW (6) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_MASK (32'h40) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h30022820) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_MASK (32'h1) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_LOW (1) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_MASK (32'h2) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_LOW (2) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_MASK (32'h4) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_LOW (3) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_MASK (32'h8) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_LOW (4) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_MASK (32'h10) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (32'h30022900) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (32'h900) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (32'h30022904) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (32'h904) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (32'h30022908) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (32'h908) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (32'h3002290c) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (32'h90c) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (32'h30022910) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (32'h910) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (32'h30022914) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (32'h914) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (32'h30022918) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (32'h918) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (32'h30022980) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (32'h980) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (32'h30022984) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (32'h984) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (32'h30022988) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (32'h988) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (32'h3002298c) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (32'h98c) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (32'h30022990) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (32'h990) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (32'h30022a00) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (32'ha00) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (32'h30022a04) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (32'ha04) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (32'h30022a08) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (32'ha08) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (32'h30022a0c) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (32'ha0c) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (32'h30022a10) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (32'ha10) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (32'h30022a14) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (32'ha14) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (32'h30022a18) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (32'ha18) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (32'h30022a1c) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (32'ha1c) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (32'h30022a20) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (32'ha20) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (32'h30022a24) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (32'ha24) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (32'h30022a28) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (32'ha28) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (32'h30022a2c) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (32'ha2c) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_BASE_ADDR (32'h30030000) `define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (32'h30030000) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (32'h0) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW (0) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK (32'h1) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW (1) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK (32'h2) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW (2) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (32'h4) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4) -`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0) `define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (32'h30030004) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK (32'h1) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW (1) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK (32'h2) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW (2) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (32'h4) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3) -`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (32'hfffffff8) `define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (32'h30030008) -`define SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (32'h8) `define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL (32'h3003000c) -`define SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL (32'hc) `define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_ENC (32'h30030010) -`define SOC_IFC_REG_CPTRA_HW_ERROR_ENC (32'h10) `define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_ENC (32'h30030014) -`define SOC_IFC_REG_CPTRA_FW_ERROR_ENC (32'h14) `define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (32'h30030018) -`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (32'h18) `define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (32'h3003001c) -`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (32'h1c) `define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (32'h30030020) -`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (32'h20) `define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (32'h30030024) -`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (32'h24) `define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (32'h30030028) -`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (32'h28) `define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (32'h3003002c) -`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (32'h2c) `define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (32'h30030030) -`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (32'h30) `define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (32'h30030034) -`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (32'h34) `define CLP_SOC_IFC_REG_CPTRA_BOOT_STATUS (32'h30030038) -`define SOC_IFC_REG_CPTRA_BOOT_STATUS (32'h38) `define CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS (32'h3003003c) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS (32'h3c) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_LOW (0) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK (32'hffffff) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_LOW (24) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (32'h1000000) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (32'he000000) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (32'h10000000) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (32'h20000000) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK (32'h40000000) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_LOW (31) -`define SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK (32'h80000000) `define CLP_SOC_IFC_REG_CPTRA_RESET_REASON (32'h30030040) -`define SOC_IFC_REG_CPTRA_RESET_REASON (32'h40) -`define SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_LOW (0) -`define SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK (32'h1) -`define SOC_IFC_REG_CPTRA_RESET_REASON_WARM_RESET_LOW (1) -`define SOC_IFC_REG_CPTRA_RESET_REASON_WARM_RESET_MASK (32'h2) `define CLP_SOC_IFC_REG_CPTRA_SECURITY_STATE (32'h30030044) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE (32'h44) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_LOW (0) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_MASK (32'h3) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEBUG_LOCKED_LOW (2) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEBUG_LOCKED_MASK (32'h4) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_LOW (3) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) -`define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) `define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h30030048) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h48) `define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h3003004c) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h4c) `define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h30030050) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h50) `define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h30030054) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h54) `define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h30030058) -`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h58) `define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h3003005c) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h5c) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h30030060) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h60) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h30030064) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h64) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h30030068) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h68) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h3003006c) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h6c) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (32'h30030070) -`define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (32'h70) `define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h30030074) -`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h74) -`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h30030078) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h78) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (32'h3003007c) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_1 (32'h7c) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_2 (32'h30030080) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_2 (32'h80) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_3 (32'h30030084) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_3 (32'h84) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_4 (32'h30030088) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_4 (32'h88) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_5 (32'h3003008c) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_5 (32'h8c) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_6 (32'h30030090) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_6 (32'h90) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_7 (32'h30030094) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_7 (32'h94) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_8 (32'h30030098) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_8 (32'h98) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_9 (32'h3003009c) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_9 (32'h9c) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_10 (32'h300300a0) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_10 (32'ha0) `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_11 (32'h300300a4) -`define SOC_IFC_REG_CPTRA_TRNG_DATA_11 (32'ha4) `define CLP_SOC_IFC_REG_CPTRA_TRNG_CTRL (32'h300300a8) -`define SOC_IFC_REG_CPTRA_TRNG_CTRL (32'ha8) -`define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_LOW (0) -`define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS (32'h300300ac) -`define SOC_IFC_REG_CPTRA_TRNG_STATUS (32'hac) -`define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW (0) -`define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK (32'h1) -`define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW (1) -`define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK (32'h2) `define CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE (32'h300300b0) -`define SOC_IFC_REG_CPTRA_FUSE_WR_DONE (32'hb0) -`define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_LOW (0) -`define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_TIMER_CONFIG (32'h300300b4) -`define SOC_IFC_REG_CPTRA_TIMER_CONFIG (32'hb4) `define CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO (32'h300300b8) -`define SOC_IFC_REG_CPTRA_BOOTFSM_GO (32'hb8) -`define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_LOW (0) -`define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG (32'h300300bc) -`define SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG (32'hbc) `define CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN (32'h300300c0) -`define SOC_IFC_REG_CPTRA_CLK_GATING_EN (32'hc0) -`define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW (0) -`define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0 (32'h300300c4) -`define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0 (32'hc4) `define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1 (32'h300300c8) -`define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1 (32'hc8) `define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (32'h300300cc) -`define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (32'hcc) `define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (32'h300300d0) -`define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (32'hd0) `define CLP_SOC_IFC_REG_CPTRA_HW_REV_ID (32'h300300d4) -`define SOC_IFC_REG_CPTRA_HW_REV_ID (32'hd4) -`define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW (0) -`define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK (32'hffff) -`define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW (16) -`define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK (32'hffff0000) `define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_0 (32'h300300d8) -`define SOC_IFC_REG_CPTRA_FW_REV_ID_0 (32'hd8) `define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_1 (32'h300300dc) -`define SOC_IFC_REG_CPTRA_FW_REV_ID_1 (32'hdc) `define CLP_SOC_IFC_REG_CPTRA_HW_CONFIG (32'h300300e0) -`define SOC_IFC_REG_CPTRA_HW_CONFIG (32'he0) -`define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0) -`define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (32'h1) -`define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1) -`define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (32'he) -`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) -`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) -`define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5) -`define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (32'h20) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'h300300e4) -`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'he4) -`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) -`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL (32'h300300e8) -`define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL (32'he8) -`define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW (0) -`define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'h300300ec) -`define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'hec) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'h300300f0) -`define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'hf0) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN (32'h300300f4) -`define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN (32'hf4) -`define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW (0) -`define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL (32'h300300f8) -`define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL (32'hf8) -`define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW (0) -`define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'h300300fc) -`define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'hfc) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h30030100) -`define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h100) `define CLP_SOC_IFC_REG_CPTRA_WDT_STATUS (32'h30030104) -`define SOC_IFC_REG_CPTRA_WDT_STATUS (32'h104) -`define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW (0) -`define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) -`define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) -`define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) `define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (32'h30030108) -`define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (32'h108) `define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h3003010c) -`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h10c) -`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h30030110) -`define SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h110) `define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (32'h30030114) -`define SOC_IFC_REG_CPTRA_WDT_CFG_1 (32'h114) `define CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (32'h30030118) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (32'h118) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW (0) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK (32'hffff) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW (16) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK (32'hffff0000) `define CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (32'h3003011c) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (32'h11c) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW (0) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK (32'hffff) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW (16) -`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK (32'hffff0000) `define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_0 (32'h30030120) -`define SOC_IFC_REG_CPTRA_RSVD_REG_0 (32'h120) `define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1 (32'h30030124) -`define SOC_IFC_REG_CPTRA_RSVD_REG_1 (32'h124) `define CLP_SOC_IFC_REG_CPTRA_HW_CAPABILITIES (32'h30030128) -`define SOC_IFC_REG_CPTRA_HW_CAPABILITIES (32'h128) `define CLP_SOC_IFC_REG_CPTRA_FW_CAPABILITIES (32'h3003012c) -`define SOC_IFC_REG_CPTRA_FW_CAPABILITIES (32'h12c) `define CLP_SOC_IFC_REG_CPTRA_CAP_LOCK (32'h30030130) -`define SOC_IFC_REG_CPTRA_CAP_LOCK (32'h130) -`define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (32'h30030140) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (32'h140) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (32'h30030144) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (32'h144) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (32'h30030148) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (32'h148) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (32'h3003014c) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (32'h14c) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (32'h30030150) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (32'h150) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (32'h30030154) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (32'h154) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (32'h30030158) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (32'h158) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (32'h3003015c) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (32'h15c) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (32'h30030160) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (32'h160) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (32'h30030164) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (32'h164) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (32'h30030168) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (32'h168) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (32'h3003016c) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (32'h16c) `define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h30030170) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h170) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_0 (32'h30030200) -`define SOC_IFC_REG_FUSE_UDS_SEED_0 (32'h200) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_1 (32'h30030204) -`define SOC_IFC_REG_FUSE_UDS_SEED_1 (32'h204) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_2 (32'h30030208) -`define SOC_IFC_REG_FUSE_UDS_SEED_2 (32'h208) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_3 (32'h3003020c) -`define SOC_IFC_REG_FUSE_UDS_SEED_3 (32'h20c) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_4 (32'h30030210) -`define SOC_IFC_REG_FUSE_UDS_SEED_4 (32'h210) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_5 (32'h30030214) -`define SOC_IFC_REG_FUSE_UDS_SEED_5 (32'h214) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_6 (32'h30030218) -`define SOC_IFC_REG_FUSE_UDS_SEED_6 (32'h218) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_7 (32'h3003021c) -`define SOC_IFC_REG_FUSE_UDS_SEED_7 (32'h21c) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_8 (32'h30030220) -`define SOC_IFC_REG_FUSE_UDS_SEED_8 (32'h220) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_9 (32'h30030224) -`define SOC_IFC_REG_FUSE_UDS_SEED_9 (32'h224) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_10 (32'h30030228) -`define SOC_IFC_REG_FUSE_UDS_SEED_10 (32'h228) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_11 (32'h3003022c) -`define SOC_IFC_REG_FUSE_UDS_SEED_11 (32'h22c) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_12 (32'h30030230) -`define SOC_IFC_REG_FUSE_UDS_SEED_12 (32'h230) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_13 (32'h30030234) -`define SOC_IFC_REG_FUSE_UDS_SEED_13 (32'h234) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_14 (32'h30030238) -`define SOC_IFC_REG_FUSE_UDS_SEED_14 (32'h238) `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_15 (32'h3003023c) -`define SOC_IFC_REG_FUSE_UDS_SEED_15 (32'h23c) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 (32'h30030240) -`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 (32'h240) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_1 (32'h30030244) -`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_1 (32'h244) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_2 (32'h30030248) -`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_2 (32'h248) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_3 (32'h3003024c) -`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_3 (32'h24c) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_4 (32'h30030250) -`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_4 (32'h250) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_5 (32'h30030254) -`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_5 (32'h254) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 (32'h30030258) -`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 (32'h258) `define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (32'h3003025c) -`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (32'h25c) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (32'h30030260) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (32'h260) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (32'h30030264) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (32'h264) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (32'h30030268) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (32'h268) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (32'h3003026c) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (32'h26c) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (32'h30030270) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (32'h270) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (32'h30030274) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (32'h274) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (32'h30030278) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (32'h278) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (32'h3003027c) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (32'h27c) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (32'h30030280) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (32'h280) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (32'h30030284) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (32'h284) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (32'h30030288) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (32'h288) `define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (32'h3003028c) -`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (32'h28c) `define CLP_SOC_IFC_REG_FUSE_ECC_REVOCATION (32'h30030290) -`define SOC_IFC_REG_FUSE_ECC_REVOCATION (32'h290) -`define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) -`define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (32'hf) `define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h300302b4) -`define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) `define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h300302b8) -`define SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h2b8) `define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (32'h300302bc) -`define SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (32'h2bc) `define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (32'h300302c0) -`define SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (32'h2c0) `define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (32'h300302c4) -`define SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (32'h2c4) `define CLP_SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h300302c8) -`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2c8) -`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0) -`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (32'h1) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h300302cc) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2cc) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h300302d0) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2d0) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h300302d4) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2d4) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h300302d8) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2d8) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h300302dc) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2dc) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h300302e0) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2e0) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h300302e4) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2e4) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h300302e8) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2e8) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h300302ec) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2ec) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h300302f0) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h2f0) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h300302f4) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h2f4) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h300302f8) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h2f8) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h300302fc) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h2fc) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h30030300) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h300) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h30030304) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h304) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h30030308) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h308) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h3003030c) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h30c) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h30030310) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h310) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h30030314) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h314) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h30030318) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h318) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h3003031c) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h31c) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h30030320) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h320) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h30030324) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h324) `define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h30030328) -`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h328) `define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h3003032c) -`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h32c) `define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h30030330) -`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h330) `define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h30030334) -`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h334) `define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h30030338) -`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h338) `define CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION (32'h30030340) -`define SOC_IFC_REG_FUSE_LMS_REVOCATION (32'h340) `define CLP_SOC_IFC_REG_FUSE_MLDSA_REVOCATION (32'h30030344) -`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION (32'h344) -`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0) -`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (32'hf) `define CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID (32'h30030348) -`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID (32'h348) -`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0) -`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) `define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h3003034c) -`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h34c) `define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h30030350) -`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h350) `define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h30030354) -`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354) `define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h30030358) -`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358) `define CLP_SOC_IFC_REG_FUSE_PQC_KEY_TYPE (32'h3003035c) -`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE (32'h35c) -`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) -`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (32'h3) `define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h30030360) -`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h360) `define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h30030364) -`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h364) `define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h30030368) -`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h368) `define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h3003036c) -`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h36c) `define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h30030370) -`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h370) -`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) -`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (32'hff) `define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (32'h30030500) -`define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500) `define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (32'h30030504) -`define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (32'h504) `define CLP_SOC_IFC_REG_SS_MCI_BASE_ADDR_L (32'h30030508) -`define SOC_IFC_REG_SS_MCI_BASE_ADDR_L (32'h508) `define CLP_SOC_IFC_REG_SS_MCI_BASE_ADDR_H (32'h3003050c) -`define SOC_IFC_REG_SS_MCI_BASE_ADDR_H (32'h50c) `define CLP_SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h30030510) -`define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h510) `define CLP_SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h30030514) -`define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h514) `define CLP_SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (32'h30030518) -`define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (32'h518) `define CLP_SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (32'h3003051c) -`define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (32'h51c) `define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (32'h30030520) -`define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (32'h520) `define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (32'h30030524) -`define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (32'h524) `define CLP_SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h30030528) -`define SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h528) `define CLP_SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h3003052c) -`define SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h52c) `define CLP_SOC_IFC_REG_SS_DEBUG_INTENT (32'h30030530) -`define SOC_IFC_REG_SS_DEBUG_INTENT (32'h530) -`define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0) -`define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (32'h1) `define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_0 (32'h300305a0) -`define SOC_IFC_REG_SS_STRAP_GENERIC_0 (32'h5a0) `define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_1 (32'h300305a4) -`define SOC_IFC_REG_SS_STRAP_GENERIC_1 (32'h5a4) `define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_2 (32'h300305a8) -`define SOC_IFC_REG_SS_STRAP_GENERIC_2 (32'h5a8) `define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_3 (32'h300305ac) -`define SOC_IFC_REG_SS_STRAP_GENERIC_3 (32'h5ac) `define CLP_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h300305c0) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h5c0) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (32'h1) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_LOW (1) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_MASK (32'h2) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_LOW (2) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (32'h4) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (32'hfffffff8) `define CLP_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h300305c4) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h5c4) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (32'h1) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_LOW (1) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_MASK (32'h2) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_LOW (2) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_MASK (32'h4) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_LOW (3) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_MASK (32'h8) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_LOW (4) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_MASK (32'h10) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_LOW (5) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_MASK (32'h20) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_LOW (6) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK (32'h40) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_LOW (7) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (32'h80) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (32'h100) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9) -`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (32'hfffffe00) `define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h300305c8) -`define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h5c8) `define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h300305cc) -`define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h5cc) `define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h300305d0) -`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h5d0) `define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h300305d4) -`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h5d4) `define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h300305d8) -`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h5d8) `define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h300305dc) -`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h5dc) `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0 (32'h30030600) -`define SOC_IFC_REG_INTERNAL_OBF_KEY_0 (32'h600) `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_1 (32'h30030604) -`define SOC_IFC_REG_INTERNAL_OBF_KEY_1 (32'h604) `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_2 (32'h30030608) -`define SOC_IFC_REG_INTERNAL_OBF_KEY_2 (32'h608) `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_3 (32'h3003060c) -`define SOC_IFC_REG_INTERNAL_OBF_KEY_3 (32'h60c) `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_4 (32'h30030610) -`define SOC_IFC_REG_INTERNAL_OBF_KEY_4 (32'h610) `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_5 (32'h30030614) -`define SOC_IFC_REG_INTERNAL_OBF_KEY_5 (32'h614) `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_6 (32'h30030618) -`define SOC_IFC_REG_INTERNAL_OBF_KEY_6 (32'h618) `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_7 (32'h3003061c) -`define SOC_IFC_REG_INTERNAL_OBF_KEY_7 (32'h61c) `define CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK (32'h30030620) -`define SOC_IFC_REG_INTERNAL_ICCM_LOCK (32'h620) -`define SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_LOW (0) -`define SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK (32'h1) `define CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET (32'h30030624) -`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET (32'h624) -`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_LOW (0) -`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK (32'h1) `define CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES (32'h30030628) -`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES (32'h628) -`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_LOW (0) -`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_MASK (32'hff) `define CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR (32'h3003062c) -`define SOC_IFC_REG_INTERNAL_NMI_VECTOR (32'h62c) `define CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK (32'h30030630) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK (32'h630) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_LOW (0) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK (32'h1) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_LOW (1) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_MASK (32'h2) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_LOW (2) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK (32'h4) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_CRYPTO_ERR_LOW (3) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_CRYPTO_ERR_MASK (32'h8) `define CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK (32'h30030634) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK (32'h634) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_LOW (0) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_MASK (32'h1) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_LOW (1) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_MASK (32'h2) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_LOW (2) -`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK (32'h4) `define CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK (32'h30030638) -`define SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK (32'h638) `define CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK (32'h3003063c) -`define SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK (32'h63c) `define CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L (32'h30030640) -`define SOC_IFC_REG_INTERNAL_RV_MTIME_L (32'h640) `define CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H (32'h30030644) -`define SOC_IFC_REG_INTERNAL_RV_MTIME_H (32'h644) `define CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L (32'h30030648) -`define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L (32'h648) `define CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H (32'h3003064c) -`define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H (32'h64c) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_START (32'h30030800) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h30030800) -`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) -`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) -`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) -`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h30030804) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INV_DEV_EN_LOW (1) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INV_DEV_EN_MASK (32'h2) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_FAIL_EN_LOW (2) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_FAIL_EN_MASK (32'h4) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_BAD_FUSE_EN_LOW (3) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_BAD_FUSE_EN_MASK (32'h8) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_ICCM_BLOCKED_EN_LOW (4) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_ICCM_BLOCKED_EN_MASK (32'h10) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_ECC_UNC_EN_LOW (5) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_ECC_UNC_EN_MASK (32'h20) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_LOW (6) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK (32'h40) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_LOW (7) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK (32'h80) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h30030808) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_MASK (32'h1) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_LOW (1) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_MASK (32'h2) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_LOW (2) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_MASK (32'h4) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_LOW (3) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_MASK (32'h8) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_LOW (4) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK (32'h10) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_LOW (5) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK (32'h20) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h3003080c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h30030810) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h30030814) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_LOW (1) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK (32'h2) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_LOW (2) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK (32'h4) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_LOW (3) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK (32'h8) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_LOW (4) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK (32'h10) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_LOW (5) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK (32'h20) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_LOW (6) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK (32'h40) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_LOW (7) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK (32'h80) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h30030818) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK (32'h1) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_LOW (1) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK (32'h2) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_LOW (2) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK (32'h4) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_LOW (3) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK (32'h8) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_LOW (4) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK (32'h10) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_LOW (5) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK (32'h20) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h3003081c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INV_DEV_TRIG_LOW (1) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INV_DEV_TRIG_MASK (32'h2) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_FAIL_TRIG_LOW (2) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_FAIL_TRIG_MASK (32'h4) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_BAD_FUSE_TRIG_LOW (3) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_BAD_FUSE_TRIG_MASK (32'h8) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_ICCM_BLOCKED_TRIG_LOW (4) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_ICCM_BLOCKED_TRIG_MASK (32'h10) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_ECC_UNC_TRIG_LOW (5) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_ECC_UNC_TRIG_MASK (32'h20) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER1_TIMEOUT_TRIG_LOW (6) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER1_TIMEOUT_TRIG_MASK (32'h40) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_LOW (7) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_MASK (32'h80) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h30030820) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_MASK (32'h1) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_MBOX_ECC_COR_TRIG_LOW (1) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_MBOX_ECC_COR_TRIG_MASK (32'h2) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_LOW (2) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_MASK (32'h4) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_LOW (3) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_MASK (32'h8) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_LOW (4) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK (32'h10) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_LOW (5) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_MASK (32'h20) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h30030900) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h900) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R (32'h30030904) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R (32'h904) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R (32'h30030908) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R (32'h908) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R (32'h3003090c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R (32'h90c) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R (32'h30030910) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R (32'h910) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R (32'h30030914) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R (32'h914) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R (32'h30030918) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R (32'h918) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R (32'h3003091c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R (32'h91c) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R (32'h30030980) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R (32'h980) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R (32'h30030984) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R (32'h984) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R (32'h30030988) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R (32'h988) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R (32'h3003098c) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R (32'h98c) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R (32'h30030990) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R (32'h990) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R (32'h30030994) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R (32'h994) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'h30030a00) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'ha00) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R (32'h30030a04) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R (32'ha04) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R (32'h30030a08) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R (32'ha08) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R (32'h30030a0c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R (32'ha0c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R (32'h30030a10) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R (32'ha10) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R (32'h30030a14) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R (32'ha14) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R (32'h30030a18) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R (32'ha18) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R (32'h30030a1c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R (32'ha1c) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R (32'h30030a20) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R (32'ha20) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R (32'h30030a24) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R (32'ha24) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R (32'h30030a28) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R (32'ha28) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R (32'h30030a2c) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R (32'ha2c) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R (32'h30030a30) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R (32'ha30) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R (32'h30030a34) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R (32'ha34) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW (0) -`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) `define CLP_MBOX_SRAM_BASE_ADDR (32'h30040000) `define CLP_MBOX_SRAM_END_ADDR (32'h3007ffff) diff --git a/src/integration/rtl/caliptra_reg_field_defines.svh b/src/integration/rtl/caliptra_reg_field_defines.svh new file mode 100644 index 000000000..d5f799bd1 --- /dev/null +++ b/src/integration/rtl/caliptra_reg_field_defines.svh @@ -0,0 +1,4331 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +`ifndef CALIPTRA_REG_FIELD_DEFINES_HEADER +`define CALIPTRA_REG_FIELD_DEFINES_HEADER + + +`define DOE_REG_DOE_IV_0 (32'h0) +`define DOE_REG_DOE_IV_1 (32'h4) +`define DOE_REG_DOE_IV_2 (32'h8) +`define DOE_REG_DOE_IV_3 (32'hc) +`define DOE_REG_DOE_CTRL (32'h10) +`define DOE_REG_DOE_CTRL_CMD_LOW (0) +`define DOE_REG_DOE_CTRL_CMD_MASK (32'h3) +`define DOE_REG_DOE_CTRL_DEST_LOW (2) +`define DOE_REG_DOE_CTRL_DEST_MASK (32'h7c) +`define DOE_REG_DOE_STATUS (32'h14) +`define DOE_REG_DOE_STATUS_READY_LOW (0) +`define DOE_REG_DOE_STATUS_READY_MASK (32'h1) +`define DOE_REG_DOE_STATUS_VALID_LOW (1) +`define DOE_REG_DOE_STATUS_VALID_MASK (32'h2) +`define DOE_REG_DOE_STATUS_UDS_FLOW_DONE_LOW (2) +`define DOE_REG_DOE_STATUS_UDS_FLOW_DONE_MASK (32'h4) +`define DOE_REG_DOE_STATUS_FE_FLOW_DONE_LOW (3) +`define DOE_REG_DOE_STATUS_FE_FLOW_DONE_MASK (32'h8) +`define DOE_REG_DOE_STATUS_DEOBF_SECRETS_CLEARED_LOW (4) +`define DOE_REG_DOE_STATUS_DEOBF_SECRETS_CLEARED_MASK (32'h10) +`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) +`define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) +`define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) +`define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) +`define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) +`define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define ECC_REG_ECC_NAME_0 (32'h0) +`define ECC_REG_ECC_NAME_1 (32'h4) +`define ECC_REG_ECC_VERSION_0 (32'h8) +`define ECC_REG_ECC_VERSION_1 (32'hc) +`define ECC_REG_ECC_CTRL (32'h10) +`define ECC_REG_ECC_CTRL_CTRL_LOW (0) +`define ECC_REG_ECC_CTRL_CTRL_MASK (32'h3) +`define ECC_REG_ECC_CTRL_ZEROIZE_LOW (2) +`define ECC_REG_ECC_CTRL_ZEROIZE_MASK (32'h4) +`define ECC_REG_ECC_CTRL_PCR_SIGN_LOW (3) +`define ECC_REG_ECC_CTRL_PCR_SIGN_MASK (32'h8) +`define ECC_REG_ECC_CTRL_DH_SHAREDKEY_LOW (4) +`define ECC_REG_ECC_CTRL_DH_SHAREDKEY_MASK (32'h10) +`define ECC_REG_ECC_STATUS (32'h18) +`define ECC_REG_ECC_STATUS_READY_LOW (0) +`define ECC_REG_ECC_STATUS_READY_MASK (32'h1) +`define ECC_REG_ECC_STATUS_VALID_LOW (1) +`define ECC_REG_ECC_STATUS_VALID_MASK (32'h2) +`define ECC_REG_ECC_SEED_0 (32'h80) +`define ECC_REG_ECC_SEED_1 (32'h84) +`define ECC_REG_ECC_SEED_2 (32'h88) +`define ECC_REG_ECC_SEED_3 (32'h8c) +`define ECC_REG_ECC_SEED_4 (32'h90) +`define ECC_REG_ECC_SEED_5 (32'h94) +`define ECC_REG_ECC_SEED_6 (32'h98) +`define ECC_REG_ECC_SEED_7 (32'h9c) +`define ECC_REG_ECC_SEED_8 (32'ha0) +`define ECC_REG_ECC_SEED_9 (32'ha4) +`define ECC_REG_ECC_SEED_10 (32'ha8) +`define ECC_REG_ECC_SEED_11 (32'hac) +`define ECC_REG_ECC_MSG_0 (32'h100) +`define ECC_REG_ECC_MSG_1 (32'h104) +`define ECC_REG_ECC_MSG_2 (32'h108) +`define ECC_REG_ECC_MSG_3 (32'h10c) +`define ECC_REG_ECC_MSG_4 (32'h110) +`define ECC_REG_ECC_MSG_5 (32'h114) +`define ECC_REG_ECC_MSG_6 (32'h118) +`define ECC_REG_ECC_MSG_7 (32'h11c) +`define ECC_REG_ECC_MSG_8 (32'h120) +`define ECC_REG_ECC_MSG_9 (32'h124) +`define ECC_REG_ECC_MSG_10 (32'h128) +`define ECC_REG_ECC_MSG_11 (32'h12c) +`define ECC_REG_ECC_PRIVKEY_OUT_0 (32'h180) +`define ECC_REG_ECC_PRIVKEY_OUT_1 (32'h184) +`define ECC_REG_ECC_PRIVKEY_OUT_2 (32'h188) +`define ECC_REG_ECC_PRIVKEY_OUT_3 (32'h18c) +`define ECC_REG_ECC_PRIVKEY_OUT_4 (32'h190) +`define ECC_REG_ECC_PRIVKEY_OUT_5 (32'h194) +`define ECC_REG_ECC_PRIVKEY_OUT_6 (32'h198) +`define ECC_REG_ECC_PRIVKEY_OUT_7 (32'h19c) +`define ECC_REG_ECC_PRIVKEY_OUT_8 (32'h1a0) +`define ECC_REG_ECC_PRIVKEY_OUT_9 (32'h1a4) +`define ECC_REG_ECC_PRIVKEY_OUT_10 (32'h1a8) +`define ECC_REG_ECC_PRIVKEY_OUT_11 (32'h1ac) +`define ECC_REG_ECC_PUBKEY_X_0 (32'h200) +`define ECC_REG_ECC_PUBKEY_X_1 (32'h204) +`define ECC_REG_ECC_PUBKEY_X_2 (32'h208) +`define ECC_REG_ECC_PUBKEY_X_3 (32'h20c) +`define ECC_REG_ECC_PUBKEY_X_4 (32'h210) +`define ECC_REG_ECC_PUBKEY_X_5 (32'h214) +`define ECC_REG_ECC_PUBKEY_X_6 (32'h218) +`define ECC_REG_ECC_PUBKEY_X_7 (32'h21c) +`define ECC_REG_ECC_PUBKEY_X_8 (32'h220) +`define ECC_REG_ECC_PUBKEY_X_9 (32'h224) +`define ECC_REG_ECC_PUBKEY_X_10 (32'h228) +`define ECC_REG_ECC_PUBKEY_X_11 (32'h22c) +`define ECC_REG_ECC_PUBKEY_Y_0 (32'h280) +`define ECC_REG_ECC_PUBKEY_Y_1 (32'h284) +`define ECC_REG_ECC_PUBKEY_Y_2 (32'h288) +`define ECC_REG_ECC_PUBKEY_Y_3 (32'h28c) +`define ECC_REG_ECC_PUBKEY_Y_4 (32'h290) +`define ECC_REG_ECC_PUBKEY_Y_5 (32'h294) +`define ECC_REG_ECC_PUBKEY_Y_6 (32'h298) +`define ECC_REG_ECC_PUBKEY_Y_7 (32'h29c) +`define ECC_REG_ECC_PUBKEY_Y_8 (32'h2a0) +`define ECC_REG_ECC_PUBKEY_Y_9 (32'h2a4) +`define ECC_REG_ECC_PUBKEY_Y_10 (32'h2a8) +`define ECC_REG_ECC_PUBKEY_Y_11 (32'h2ac) +`define ECC_REG_ECC_SIGN_R_0 (32'h300) +`define ECC_REG_ECC_SIGN_R_1 (32'h304) +`define ECC_REG_ECC_SIGN_R_2 (32'h308) +`define ECC_REG_ECC_SIGN_R_3 (32'h30c) +`define ECC_REG_ECC_SIGN_R_4 (32'h310) +`define ECC_REG_ECC_SIGN_R_5 (32'h314) +`define ECC_REG_ECC_SIGN_R_6 (32'h318) +`define ECC_REG_ECC_SIGN_R_7 (32'h31c) +`define ECC_REG_ECC_SIGN_R_8 (32'h320) +`define ECC_REG_ECC_SIGN_R_9 (32'h324) +`define ECC_REG_ECC_SIGN_R_10 (32'h328) +`define ECC_REG_ECC_SIGN_R_11 (32'h32c) +`define ECC_REG_ECC_SIGN_S_0 (32'h380) +`define ECC_REG_ECC_SIGN_S_1 (32'h384) +`define ECC_REG_ECC_SIGN_S_2 (32'h388) +`define ECC_REG_ECC_SIGN_S_3 (32'h38c) +`define ECC_REG_ECC_SIGN_S_4 (32'h390) +`define ECC_REG_ECC_SIGN_S_5 (32'h394) +`define ECC_REG_ECC_SIGN_S_6 (32'h398) +`define ECC_REG_ECC_SIGN_S_7 (32'h39c) +`define ECC_REG_ECC_SIGN_S_8 (32'h3a0) +`define ECC_REG_ECC_SIGN_S_9 (32'h3a4) +`define ECC_REG_ECC_SIGN_S_10 (32'h3a8) +`define ECC_REG_ECC_SIGN_S_11 (32'h3ac) +`define ECC_REG_ECC_VERIFY_R_0 (32'h400) +`define ECC_REG_ECC_VERIFY_R_1 (32'h404) +`define ECC_REG_ECC_VERIFY_R_2 (32'h408) +`define ECC_REG_ECC_VERIFY_R_3 (32'h40c) +`define ECC_REG_ECC_VERIFY_R_4 (32'h410) +`define ECC_REG_ECC_VERIFY_R_5 (32'h414) +`define ECC_REG_ECC_VERIFY_R_6 (32'h418) +`define ECC_REG_ECC_VERIFY_R_7 (32'h41c) +`define ECC_REG_ECC_VERIFY_R_8 (32'h420) +`define ECC_REG_ECC_VERIFY_R_9 (32'h424) +`define ECC_REG_ECC_VERIFY_R_10 (32'h428) +`define ECC_REG_ECC_VERIFY_R_11 (32'h42c) +`define ECC_REG_ECC_IV_0 (32'h480) +`define ECC_REG_ECC_IV_1 (32'h484) +`define ECC_REG_ECC_IV_2 (32'h488) +`define ECC_REG_ECC_IV_3 (32'h48c) +`define ECC_REG_ECC_IV_4 (32'h490) +`define ECC_REG_ECC_IV_5 (32'h494) +`define ECC_REG_ECC_IV_6 (32'h498) +`define ECC_REG_ECC_IV_7 (32'h49c) +`define ECC_REG_ECC_IV_8 (32'h4a0) +`define ECC_REG_ECC_IV_9 (32'h4a4) +`define ECC_REG_ECC_IV_10 (32'h4a8) +`define ECC_REG_ECC_IV_11 (32'h4ac) +`define ECC_REG_ECC_NONCE_0 (32'h500) +`define ECC_REG_ECC_NONCE_1 (32'h504) +`define ECC_REG_ECC_NONCE_2 (32'h508) +`define ECC_REG_ECC_NONCE_3 (32'h50c) +`define ECC_REG_ECC_NONCE_4 (32'h510) +`define ECC_REG_ECC_NONCE_5 (32'h514) +`define ECC_REG_ECC_NONCE_6 (32'h518) +`define ECC_REG_ECC_NONCE_7 (32'h51c) +`define ECC_REG_ECC_NONCE_8 (32'h520) +`define ECC_REG_ECC_NONCE_9 (32'h524) +`define ECC_REG_ECC_NONCE_10 (32'h528) +`define ECC_REG_ECC_NONCE_11 (32'h52c) +`define ECC_REG_ECC_PRIVKEY_IN_0 (32'h580) +`define ECC_REG_ECC_PRIVKEY_IN_1 (32'h584) +`define ECC_REG_ECC_PRIVKEY_IN_2 (32'h588) +`define ECC_REG_ECC_PRIVKEY_IN_3 (32'h58c) +`define ECC_REG_ECC_PRIVKEY_IN_4 (32'h590) +`define ECC_REG_ECC_PRIVKEY_IN_5 (32'h594) +`define ECC_REG_ECC_PRIVKEY_IN_6 (32'h598) +`define ECC_REG_ECC_PRIVKEY_IN_7 (32'h59c) +`define ECC_REG_ECC_PRIVKEY_IN_8 (32'h5a0) +`define ECC_REG_ECC_PRIVKEY_IN_9 (32'h5a4) +`define ECC_REG_ECC_PRIVKEY_IN_10 (32'h5a8) +`define ECC_REG_ECC_PRIVKEY_IN_11 (32'h5ac) +`define ECC_REG_ECC_DH_SHARED_KEY_0 (32'h5c0) +`define ECC_REG_ECC_DH_SHARED_KEY_1 (32'h5c4) +`define ECC_REG_ECC_DH_SHARED_KEY_2 (32'h5c8) +`define ECC_REG_ECC_DH_SHARED_KEY_3 (32'h5cc) +`define ECC_REG_ECC_DH_SHARED_KEY_4 (32'h5d0) +`define ECC_REG_ECC_DH_SHARED_KEY_5 (32'h5d4) +`define ECC_REG_ECC_DH_SHARED_KEY_6 (32'h5d8) +`define ECC_REG_ECC_DH_SHARED_KEY_7 (32'h5dc) +`define ECC_REG_ECC_DH_SHARED_KEY_8 (32'h5e0) +`define ECC_REG_ECC_DH_SHARED_KEY_9 (32'h5e4) +`define ECC_REG_ECC_DH_SHARED_KEY_10 (32'h5e8) +`define ECC_REG_ECC_DH_SHARED_KEY_11 (32'h5ec) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL (32'h600) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_LOW (0) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_MASK (32'h1) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_ENTRY_LOW (1) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_ENTRY_MASK (32'h3e) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL_PCR_HASH_EXTEND_LOW (6) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_LOW (7) +`define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_MASK (32'hffffff80) +`define ECC_REG_ECC_KV_RD_PKEY_STATUS (32'h604) +`define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_LOW (0) +`define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_MASK (32'h1) +`define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_LOW (1) +`define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_MASK (32'h2) +`define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_LOW (2) +`define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_MASK (32'h3fc) +`define ECC_REG_ECC_KV_RD_SEED_CTRL (32'h608) +`define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_LOW (0) +`define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_MASK (32'h1) +`define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_ENTRY_LOW (1) +`define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_ENTRY_MASK (32'h3e) +`define ECC_REG_ECC_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_LOW (6) +`define ECC_REG_ECC_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (32'h40) +`define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_LOW (7) +`define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_MASK (32'hffffff80) +`define ECC_REG_ECC_KV_RD_SEED_STATUS (32'h60c) +`define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_LOW (0) +`define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_MASK (32'h1) +`define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_LOW (1) +`define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_MASK (32'h2) +`define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_LOW (2) +`define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_MASK (32'h3fc) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL (32'h610) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_LOW (0) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_MASK (32'h1) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_ENTRY_LOW (1) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_ENTRY_MASK (32'h3e) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_HMAC_KEY_DEST_VALID_LOW (6) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_HMAC_KEY_DEST_VALID_MASK (32'h40) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_HMAC_BLOCK_DEST_VALID_LOW (7) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_HMAC_BLOCK_DEST_VALID_MASK (32'h80) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_MLDSA_SEED_DEST_VALID_LOW (8) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_MLDSA_SEED_DEST_VALID_MASK (32'h100) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_PKEY_DEST_VALID_LOW (9) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_PKEY_DEST_VALID_MASK (32'h200) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_SEED_DEST_VALID_LOW (10) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_ECC_SEED_DEST_VALID_MASK (32'h400) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_AES_KEY_DEST_VALID_LOW (11) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_LOW (12) +`define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_MASK (32'hfffff000) +`define ECC_REG_ECC_KV_WR_PKEY_STATUS (32'h614) +`define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_LOW (0) +`define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_MASK (32'h1) +`define ECC_REG_ECC_KV_WR_PKEY_STATUS_VALID_LOW (1) +`define ECC_REG_ECC_KV_WR_PKEY_STATUS_VALID_MASK (32'h2) +`define ECC_REG_ECC_KV_WR_PKEY_STATUS_ERROR_LOW (2) +`define ECC_REG_ECC_KV_WR_PKEY_STATUS_ERROR_MASK (32'h3fc) +`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h900) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'ha00) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha04) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define HMAC_REG_HMAC512_NAME_0 (32'h0) +`define HMAC_REG_HMAC512_NAME_1 (32'h4) +`define HMAC_REG_HMAC512_VERSION_0 (32'h8) +`define HMAC_REG_HMAC512_VERSION_1 (32'hc) +`define HMAC_REG_HMAC512_CTRL (32'h10) +`define HMAC_REG_HMAC512_CTRL_INIT_LOW (0) +`define HMAC_REG_HMAC512_CTRL_INIT_MASK (32'h1) +`define HMAC_REG_HMAC512_CTRL_NEXT_LOW (1) +`define HMAC_REG_HMAC512_CTRL_NEXT_MASK (32'h2) +`define HMAC_REG_HMAC512_CTRL_ZEROIZE_LOW (2) +`define HMAC_REG_HMAC512_CTRL_ZEROIZE_MASK (32'h4) +`define HMAC_REG_HMAC512_CTRL_MODE_LOW (3) +`define HMAC_REG_HMAC512_CTRL_MODE_MASK (32'h8) +`define HMAC_REG_HMAC512_CTRL_CSR_MODE_LOW (4) +`define HMAC_REG_HMAC512_CTRL_CSR_MODE_MASK (32'h10) +`define HMAC_REG_HMAC512_CTRL_RESERVED_LOW (5) +`define HMAC_REG_HMAC512_CTRL_RESERVED_MASK (32'h20) +`define HMAC_REG_HMAC512_STATUS (32'h18) +`define HMAC_REG_HMAC512_STATUS_READY_LOW (0) +`define HMAC_REG_HMAC512_STATUS_READY_MASK (32'h1) +`define HMAC_REG_HMAC512_STATUS_VALID_LOW (1) +`define HMAC_REG_HMAC512_STATUS_VALID_MASK (32'h2) +`define HMAC_REG_HMAC512_KEY_0 (32'h40) +`define HMAC_REG_HMAC512_KEY_1 (32'h44) +`define HMAC_REG_HMAC512_KEY_2 (32'h48) +`define HMAC_REG_HMAC512_KEY_3 (32'h4c) +`define HMAC_REG_HMAC512_KEY_4 (32'h50) +`define HMAC_REG_HMAC512_KEY_5 (32'h54) +`define HMAC_REG_HMAC512_KEY_6 (32'h58) +`define HMAC_REG_HMAC512_KEY_7 (32'h5c) +`define HMAC_REG_HMAC512_KEY_8 (32'h60) +`define HMAC_REG_HMAC512_KEY_9 (32'h64) +`define HMAC_REG_HMAC512_KEY_10 (32'h68) +`define HMAC_REG_HMAC512_KEY_11 (32'h6c) +`define HMAC_REG_HMAC512_KEY_12 (32'h70) +`define HMAC_REG_HMAC512_KEY_13 (32'h74) +`define HMAC_REG_HMAC512_KEY_14 (32'h78) +`define HMAC_REG_HMAC512_KEY_15 (32'h7c) +`define HMAC_REG_HMAC512_BLOCK_0 (32'h80) +`define HMAC_REG_HMAC512_BLOCK_1 (32'h84) +`define HMAC_REG_HMAC512_BLOCK_2 (32'h88) +`define HMAC_REG_HMAC512_BLOCK_3 (32'h8c) +`define HMAC_REG_HMAC512_BLOCK_4 (32'h90) +`define HMAC_REG_HMAC512_BLOCK_5 (32'h94) +`define HMAC_REG_HMAC512_BLOCK_6 (32'h98) +`define HMAC_REG_HMAC512_BLOCK_7 (32'h9c) +`define HMAC_REG_HMAC512_BLOCK_8 (32'ha0) +`define HMAC_REG_HMAC512_BLOCK_9 (32'ha4) +`define HMAC_REG_HMAC512_BLOCK_10 (32'ha8) +`define HMAC_REG_HMAC512_BLOCK_11 (32'hac) +`define HMAC_REG_HMAC512_BLOCK_12 (32'hb0) +`define HMAC_REG_HMAC512_BLOCK_13 (32'hb4) +`define HMAC_REG_HMAC512_BLOCK_14 (32'hb8) +`define HMAC_REG_HMAC512_BLOCK_15 (32'hbc) +`define HMAC_REG_HMAC512_BLOCK_16 (32'hc0) +`define HMAC_REG_HMAC512_BLOCK_17 (32'hc4) +`define HMAC_REG_HMAC512_BLOCK_18 (32'hc8) +`define HMAC_REG_HMAC512_BLOCK_19 (32'hcc) +`define HMAC_REG_HMAC512_BLOCK_20 (32'hd0) +`define HMAC_REG_HMAC512_BLOCK_21 (32'hd4) +`define HMAC_REG_HMAC512_BLOCK_22 (32'hd8) +`define HMAC_REG_HMAC512_BLOCK_23 (32'hdc) +`define HMAC_REG_HMAC512_BLOCK_24 (32'he0) +`define HMAC_REG_HMAC512_BLOCK_25 (32'he4) +`define HMAC_REG_HMAC512_BLOCK_26 (32'he8) +`define HMAC_REG_HMAC512_BLOCK_27 (32'hec) +`define HMAC_REG_HMAC512_BLOCK_28 (32'hf0) +`define HMAC_REG_HMAC512_BLOCK_29 (32'hf4) +`define HMAC_REG_HMAC512_BLOCK_30 (32'hf8) +`define HMAC_REG_HMAC512_BLOCK_31 (32'hfc) +`define HMAC_REG_HMAC512_TAG_0 (32'h100) +`define HMAC_REG_HMAC512_TAG_1 (32'h104) +`define HMAC_REG_HMAC512_TAG_2 (32'h108) +`define HMAC_REG_HMAC512_TAG_3 (32'h10c) +`define HMAC_REG_HMAC512_TAG_4 (32'h110) +`define HMAC_REG_HMAC512_TAG_5 (32'h114) +`define HMAC_REG_HMAC512_TAG_6 (32'h118) +`define HMAC_REG_HMAC512_TAG_7 (32'h11c) +`define HMAC_REG_HMAC512_TAG_8 (32'h120) +`define HMAC_REG_HMAC512_TAG_9 (32'h124) +`define HMAC_REG_HMAC512_TAG_10 (32'h128) +`define HMAC_REG_HMAC512_TAG_11 (32'h12c) +`define HMAC_REG_HMAC512_TAG_12 (32'h130) +`define HMAC_REG_HMAC512_TAG_13 (32'h134) +`define HMAC_REG_HMAC512_TAG_14 (32'h138) +`define HMAC_REG_HMAC512_TAG_15 (32'h13c) +`define HMAC_REG_HMAC512_LFSR_SEED_0 (32'h140) +`define HMAC_REG_HMAC512_LFSR_SEED_1 (32'h144) +`define HMAC_REG_HMAC512_LFSR_SEED_2 (32'h148) +`define HMAC_REG_HMAC512_LFSR_SEED_3 (32'h14c) +`define HMAC_REG_HMAC512_LFSR_SEED_4 (32'h150) +`define HMAC_REG_HMAC512_LFSR_SEED_5 (32'h154) +`define HMAC_REG_HMAC512_LFSR_SEED_6 (32'h158) +`define HMAC_REG_HMAC512_LFSR_SEED_7 (32'h15c) +`define HMAC_REG_HMAC512_LFSR_SEED_8 (32'h160) +`define HMAC_REG_HMAC512_LFSR_SEED_9 (32'h164) +`define HMAC_REG_HMAC512_LFSR_SEED_10 (32'h168) +`define HMAC_REG_HMAC512_LFSR_SEED_11 (32'h16c) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL (32'h600) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_LOW (0) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_MASK (32'h1) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_ENTRY_LOW (1) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_ENTRY_MASK (32'h3e) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_LOW (6) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_RSVD_LOW (7) +`define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_RSVD_MASK (32'hffffff80) +`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS (32'h604) +`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_READY_LOW (0) +`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_READY_MASK (32'h1) +`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_VALID_LOW (1) +`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_VALID_MASK (32'h2) +`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_ERROR_LOW (2) +`define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_ERROR_MASK (32'h3fc) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL (32'h608) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_EN_LOW (0) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_EN_MASK (32'h1) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_ENTRY_LOW (1) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_ENTRY_MASK (32'h3e) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_PCR_HASH_EXTEND_LOW (6) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_PCR_HASH_EXTEND_MASK (32'h40) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_RSVD_LOW (7) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_RSVD_MASK (32'hffffff80) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS (32'h60c) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_READY_LOW (0) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_READY_MASK (32'h1) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_VALID_LOW (1) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_VALID_MASK (32'h2) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_ERROR_LOW (2) +`define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_ERROR_MASK (32'h3fc) +`define HMAC_REG_HMAC512_KV_WR_CTRL (32'h610) +`define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_EN_LOW (0) +`define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_EN_MASK (32'h1) +`define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_ENTRY_LOW (1) +`define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_ENTRY_MASK (32'h3e) +`define HMAC_REG_HMAC512_KV_WR_CTRL_HMAC_KEY_DEST_VALID_LOW (6) +`define HMAC_REG_HMAC512_KV_WR_CTRL_HMAC_KEY_DEST_VALID_MASK (32'h40) +`define HMAC_REG_HMAC512_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_LOW (7) +`define HMAC_REG_HMAC512_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_MASK (32'h80) +`define HMAC_REG_HMAC512_KV_WR_CTRL_MLDSA_SEED_DEST_VALID_LOW (8) +`define HMAC_REG_HMAC512_KV_WR_CTRL_MLDSA_SEED_DEST_VALID_MASK (32'h100) +`define HMAC_REG_HMAC512_KV_WR_CTRL_ECC_PKEY_DEST_VALID_LOW (9) +`define HMAC_REG_HMAC512_KV_WR_CTRL_ECC_PKEY_DEST_VALID_MASK (32'h200) +`define HMAC_REG_HMAC512_KV_WR_CTRL_ECC_SEED_DEST_VALID_LOW (10) +`define HMAC_REG_HMAC512_KV_WR_CTRL_ECC_SEED_DEST_VALID_MASK (32'h400) +`define HMAC_REG_HMAC512_KV_WR_CTRL_AES_KEY_DEST_VALID_LOW (11) +`define HMAC_REG_HMAC512_KV_WR_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) +`define HMAC_REG_HMAC512_KV_WR_CTRL_RSVD_LOW (12) +`define HMAC_REG_HMAC512_KV_WR_CTRL_RSVD_MASK (32'hfffff000) +`define HMAC_REG_HMAC512_KV_WR_STATUS (32'h614) +`define HMAC_REG_HMAC512_KV_WR_STATUS_READY_LOW (0) +`define HMAC_REG_HMAC512_KV_WR_STATUS_READY_MASK (32'h1) +`define HMAC_REG_HMAC512_KV_WR_STATUS_VALID_LOW (1) +`define HMAC_REG_HMAC512_KV_WR_STATUS_VALID_MASK (32'h2) +`define HMAC_REG_HMAC512_KV_WR_STATUS_ERROR_LOW (2) +`define HMAC_REG_HMAC512_KV_WR_STATUS_ERROR_MASK (32'h3fc) +`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_MODE_ERROR_EN_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_MODE_ERROR_EN_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_ZERO_ERROR_EN_LOW (1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_ZERO_ERROR_EN_MASK (32'h2) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_MODE_ERROR_STS_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_MODE_ERROR_STS_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_ZERO_ERROR_STS_LOW (1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_ZERO_ERROR_STS_MASK (32'h2) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_MODE_ERROR_TRIG_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_MODE_ERROR_TRIG_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_ZERO_ERROR_TRIG_LOW (1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_ZERO_ERROR_TRIG_MASK (32'h2) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) +`define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_R (32'h900) +`define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_R (32'h904) +`define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R (32'ha00) +`define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R (32'ha04) +`define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) +`define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) +`define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AES_REG_KEY_SHARE0_0 (32'h4) +`define AES_REG_KEY_SHARE0_1 (32'h8) +`define AES_REG_KEY_SHARE0_2 (32'hc) +`define AES_REG_KEY_SHARE0_3 (32'h10) +`define AES_REG_KEY_SHARE0_4 (32'h14) +`define AES_REG_KEY_SHARE0_5 (32'h18) +`define AES_REG_KEY_SHARE0_6 (32'h1c) +`define AES_REG_KEY_SHARE0_7 (32'h20) +`define AES_REG_KEY_SHARE1_0 (32'h24) +`define AES_REG_KEY_SHARE1_1 (32'h28) +`define AES_REG_KEY_SHARE1_2 (32'h2c) +`define AES_REG_KEY_SHARE1_3 (32'h30) +`define AES_REG_KEY_SHARE1_4 (32'h34) +`define AES_REG_KEY_SHARE1_5 (32'h38) +`define AES_REG_KEY_SHARE1_6 (32'h3c) +`define AES_REG_KEY_SHARE1_7 (32'h40) +`define AES_REG_IV_0 (32'h44) +`define AES_REG_IV_1 (32'h48) +`define AES_REG_IV_2 (32'h4c) +`define AES_REG_IV_3 (32'h50) +`define AES_REG_DATA_IN_0 (32'h54) +`define AES_REG_DATA_IN_1 (32'h58) +`define AES_REG_DATA_IN_2 (32'h5c) +`define AES_REG_DATA_IN_3 (32'h60) +`define AES_REG_DATA_OUT_0 (32'h64) +`define AES_REG_DATA_OUT_1 (32'h68) +`define AES_REG_DATA_OUT_2 (32'h6c) +`define AES_REG_DATA_OUT_3 (32'h70) +`define AES_REG_CTRL_SHADOWED (32'h74) +`define AES_REG_CTRL_SHADOWED_OPERATION_LOW (0) +`define AES_REG_CTRL_SHADOWED_OPERATION_MASK (32'h3) +`define AES_REG_CTRL_SHADOWED_MODE_LOW (2) +`define AES_REG_CTRL_SHADOWED_MODE_MASK (32'hfc) +`define AES_REG_CTRL_SHADOWED_KEY_LEN_LOW (8) +`define AES_REG_CTRL_SHADOWED_KEY_LEN_MASK (32'h700) +`define AES_REG_CTRL_SHADOWED_SIDELOAD_LOW (11) +`define AES_REG_CTRL_SHADOWED_SIDELOAD_MASK (32'h800) +`define AES_REG_CTRL_SHADOWED_PRNG_RESEED_RATE_LOW (12) +`define AES_REG_CTRL_SHADOWED_PRNG_RESEED_RATE_MASK (32'h7000) +`define AES_REG_CTRL_SHADOWED_MANUAL_OPERATION_LOW (15) +`define AES_REG_CTRL_SHADOWED_MANUAL_OPERATION_MASK (32'h8000) +`define AES_REG_CTRL_AUX_SHADOWED (32'h78) +`define AES_REG_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_LOW (0) +`define AES_REG_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_MASK (32'h1) +`define AES_REG_CTRL_AUX_SHADOWED_FORCE_MASKS_LOW (1) +`define AES_REG_CTRL_AUX_SHADOWED_FORCE_MASKS_MASK (32'h2) +`define AES_REG_CTRL_AUX_REGWEN (32'h7c) +`define AES_REG_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_LOW (0) +`define AES_REG_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_MASK (32'h1) +`define AES_REG_TRIGGER (32'h80) +`define AES_REG_TRIGGER_START_LOW (0) +`define AES_REG_TRIGGER_START_MASK (32'h1) +`define AES_REG_TRIGGER_KEY_IV_DATA_IN_CLEAR_LOW (1) +`define AES_REG_TRIGGER_KEY_IV_DATA_IN_CLEAR_MASK (32'h2) +`define AES_REG_TRIGGER_DATA_OUT_CLEAR_LOW (2) +`define AES_REG_TRIGGER_DATA_OUT_CLEAR_MASK (32'h4) +`define AES_REG_TRIGGER_PRNG_RESEED_LOW (3) +`define AES_REG_TRIGGER_PRNG_RESEED_MASK (32'h8) +`define AES_REG_STATUS (32'h84) +`define AES_REG_STATUS_IDLE_LOW (0) +`define AES_REG_STATUS_IDLE_MASK (32'h1) +`define AES_REG_STATUS_STALL_LOW (1) +`define AES_REG_STATUS_STALL_MASK (32'h2) +`define AES_REG_STATUS_OUTPUT_LOST_LOW (2) +`define AES_REG_STATUS_OUTPUT_LOST_MASK (32'h4) +`define AES_REG_STATUS_OUTPUT_VALID_LOW (3) +`define AES_REG_STATUS_OUTPUT_VALID_MASK (32'h8) +`define AES_REG_STATUS_INPUT_READY_LOW (4) +`define AES_REG_STATUS_INPUT_READY_MASK (32'h10) +`define AES_REG_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_LOW (5) +`define AES_REG_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK (32'h20) +`define AES_REG_STATUS_ALERT_FATAL_FAULT_LOW (6) +`define AES_REG_STATUS_ALERT_FATAL_FAULT_MASK (32'h40) +`define AES_REG_CTRL_GCM_SHADOWED (32'h88) +`define AES_REG_CTRL_GCM_SHADOWED_PHASE_LOW (0) +`define AES_REG_CTRL_GCM_SHADOWED_PHASE_MASK (32'h3f) +`define AES_REG_CTRL_GCM_SHADOWED_NUM_VALID_BYTES_LOW (6) +`define AES_REG_CTRL_GCM_SHADOWED_NUM_VALID_BYTES_MASK (32'h7c0) +`define AES_CLP_REG_AES_NAME_0 (32'h100) +`define AES_CLP_REG_AES_NAME_1 (32'h104) +`define AES_CLP_REG_AES_VERSION_0 (32'h108) +`define AES_CLP_REG_AES_VERSION_1 (32'h10c) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL (32'h600) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_EN_LOW (0) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_EN_MASK (32'h1) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_ENTRY_LOW (1) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_ENTRY_MASK (32'h3e) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_LOW (6) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_RSVD_LOW (7) +`define AES_CLP_REG_AES_KV_RD_KEY_CTRL_RSVD_MASK (32'hffffff80) +`define AES_CLP_REG_AES_KV_RD_KEY_STATUS (32'h604) +`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_READY_LOW (0) +`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_READY_MASK (32'h1) +`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_VALID_LOW (1) +`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_VALID_MASK (32'h2) +`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_ERROR_LOW (2) +`define AES_CLP_REG_AES_KV_RD_KEY_STATUS_ERROR_MASK (32'h3fc) +`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define KV_REG_KEY_CTRL_0 (32'h0) +`define KV_REG_KEY_CTRL_0_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_0_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_0_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_0_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_0_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_0_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_0_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_0_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_0_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_0_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_0_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_0_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_0_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_0_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_1 (32'h4) +`define KV_REG_KEY_CTRL_1_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_1_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_1_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_1_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_1_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_1_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_1_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_1_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_1_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_1_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_1_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_1_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_1_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_1_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_2 (32'h8) +`define KV_REG_KEY_CTRL_2_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_2_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_2_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_2_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_2_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_2_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_2_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_2_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_2_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_2_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_2_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_2_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_2_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_2_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_3 (32'hc) +`define KV_REG_KEY_CTRL_3_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_3_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_3_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_3_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_3_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_3_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_3_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_3_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_3_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_3_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_3_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_3_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_3_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_3_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_4 (32'h10) +`define KV_REG_KEY_CTRL_4_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_4_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_4_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_4_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_4_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_4_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_4_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_4_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_4_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_4_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_4_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_4_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_4_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_4_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_5 (32'h14) +`define KV_REG_KEY_CTRL_5_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_5_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_5_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_5_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_5_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_5_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_5_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_5_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_5_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_5_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_5_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_5_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_5_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_5_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_6 (32'h18) +`define KV_REG_KEY_CTRL_6_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_6_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_6_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_6_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_6_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_6_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_6_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_6_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_6_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_6_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_6_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_6_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_6_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_6_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_7 (32'h1c) +`define KV_REG_KEY_CTRL_7_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_7_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_7_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_7_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_7_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_7_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_7_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_7_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_7_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_7_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_7_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_7_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_7_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_7_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_8 (32'h20) +`define KV_REG_KEY_CTRL_8_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_8_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_8_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_8_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_8_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_8_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_8_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_8_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_8_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_8_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_8_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_8_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_8_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_8_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_9 (32'h24) +`define KV_REG_KEY_CTRL_9_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_9_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_9_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_9_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_9_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_9_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_9_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_9_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_9_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_9_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_9_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_9_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_9_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_9_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_10 (32'h28) +`define KV_REG_KEY_CTRL_10_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_10_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_10_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_10_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_10_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_10_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_10_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_10_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_10_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_10_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_10_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_10_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_10_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_10_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_11 (32'h2c) +`define KV_REG_KEY_CTRL_11_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_11_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_11_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_11_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_11_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_11_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_11_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_11_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_11_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_11_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_11_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_11_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_11_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_11_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_12 (32'h30) +`define KV_REG_KEY_CTRL_12_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_12_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_12_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_12_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_12_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_12_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_12_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_12_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_12_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_12_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_12_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_12_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_12_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_12_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_13 (32'h34) +`define KV_REG_KEY_CTRL_13_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_13_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_13_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_13_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_13_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_13_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_13_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_13_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_13_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_13_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_13_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_13_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_13_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_13_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_14 (32'h38) +`define KV_REG_KEY_CTRL_14_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_14_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_14_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_14_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_14_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_14_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_14_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_14_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_14_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_14_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_14_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_14_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_14_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_14_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_15 (32'h3c) +`define KV_REG_KEY_CTRL_15_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_15_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_15_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_15_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_15_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_15_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_15_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_15_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_15_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_15_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_15_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_15_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_15_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_15_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_16 (32'h40) +`define KV_REG_KEY_CTRL_16_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_16_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_16_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_16_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_16_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_16_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_16_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_16_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_16_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_16_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_16_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_16_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_16_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_16_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_17 (32'h44) +`define KV_REG_KEY_CTRL_17_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_17_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_17_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_17_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_17_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_17_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_17_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_17_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_17_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_17_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_17_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_17_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_17_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_17_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_18 (32'h48) +`define KV_REG_KEY_CTRL_18_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_18_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_18_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_18_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_18_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_18_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_18_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_18_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_18_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_18_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_18_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_18_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_18_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_18_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_19 (32'h4c) +`define KV_REG_KEY_CTRL_19_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_19_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_19_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_19_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_19_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_19_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_19_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_19_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_19_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_19_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_19_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_19_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_19_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_19_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_20 (32'h50) +`define KV_REG_KEY_CTRL_20_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_20_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_20_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_20_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_20_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_20_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_20_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_20_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_20_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_20_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_20_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_20_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_20_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_20_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_21 (32'h54) +`define KV_REG_KEY_CTRL_21_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_21_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_21_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_21_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_21_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_21_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_21_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_21_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_21_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_21_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_21_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_21_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_21_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_21_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_22 (32'h58) +`define KV_REG_KEY_CTRL_22_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_22_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_22_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_22_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_22_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_22_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_22_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_22_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_22_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_22_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_22_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_22_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_22_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_22_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_CTRL_23 (32'h5c) +`define KV_REG_KEY_CTRL_23_LOCK_WR_LOW (0) +`define KV_REG_KEY_CTRL_23_LOCK_WR_MASK (32'h1) +`define KV_REG_KEY_CTRL_23_LOCK_USE_LOW (1) +`define KV_REG_KEY_CTRL_23_LOCK_USE_MASK (32'h2) +`define KV_REG_KEY_CTRL_23_CLEAR_LOW (2) +`define KV_REG_KEY_CTRL_23_CLEAR_MASK (32'h4) +`define KV_REG_KEY_CTRL_23_RSVD0_LOW (3) +`define KV_REG_KEY_CTRL_23_RSVD0_MASK (32'h8) +`define KV_REG_KEY_CTRL_23_RSVD1_LOW (4) +`define KV_REG_KEY_CTRL_23_RSVD1_MASK (32'h1f0) +`define KV_REG_KEY_CTRL_23_DEST_VALID_LOW (9) +`define KV_REG_KEY_CTRL_23_DEST_VALID_MASK (32'h1fe00) +`define KV_REG_KEY_CTRL_23_LAST_DWORD_LOW (17) +`define KV_REG_KEY_CTRL_23_LAST_DWORD_MASK (32'h1e0000) +`define KV_REG_KEY_ENTRY_0_0 (32'h600) +`define KV_REG_KEY_ENTRY_0_1 (32'h604) +`define KV_REG_KEY_ENTRY_0_2 (32'h608) +`define KV_REG_KEY_ENTRY_0_3 (32'h60c) +`define KV_REG_KEY_ENTRY_0_4 (32'h610) +`define KV_REG_KEY_ENTRY_0_5 (32'h614) +`define KV_REG_KEY_ENTRY_0_6 (32'h618) +`define KV_REG_KEY_ENTRY_0_7 (32'h61c) +`define KV_REG_KEY_ENTRY_0_8 (32'h620) +`define KV_REG_KEY_ENTRY_0_9 (32'h624) +`define KV_REG_KEY_ENTRY_0_10 (32'h628) +`define KV_REG_KEY_ENTRY_0_11 (32'h62c) +`define KV_REG_KEY_ENTRY_0_12 (32'h630) +`define KV_REG_KEY_ENTRY_0_13 (32'h634) +`define KV_REG_KEY_ENTRY_0_14 (32'h638) +`define KV_REG_KEY_ENTRY_0_15 (32'h63c) +`define KV_REG_KEY_ENTRY_1_0 (32'h640) +`define KV_REG_KEY_ENTRY_1_1 (32'h644) +`define KV_REG_KEY_ENTRY_1_2 (32'h648) +`define KV_REG_KEY_ENTRY_1_3 (32'h64c) +`define KV_REG_KEY_ENTRY_1_4 (32'h650) +`define KV_REG_KEY_ENTRY_1_5 (32'h654) +`define KV_REG_KEY_ENTRY_1_6 (32'h658) +`define KV_REG_KEY_ENTRY_1_7 (32'h65c) +`define KV_REG_KEY_ENTRY_1_8 (32'h660) +`define KV_REG_KEY_ENTRY_1_9 (32'h664) +`define KV_REG_KEY_ENTRY_1_10 (32'h668) +`define KV_REG_KEY_ENTRY_1_11 (32'h66c) +`define KV_REG_KEY_ENTRY_1_12 (32'h670) +`define KV_REG_KEY_ENTRY_1_13 (32'h674) +`define KV_REG_KEY_ENTRY_1_14 (32'h678) +`define KV_REG_KEY_ENTRY_1_15 (32'h67c) +`define KV_REG_KEY_ENTRY_2_0 (32'h680) +`define KV_REG_KEY_ENTRY_2_1 (32'h684) +`define KV_REG_KEY_ENTRY_2_2 (32'h688) +`define KV_REG_KEY_ENTRY_2_3 (32'h68c) +`define KV_REG_KEY_ENTRY_2_4 (32'h690) +`define KV_REG_KEY_ENTRY_2_5 (32'h694) +`define KV_REG_KEY_ENTRY_2_6 (32'h698) +`define KV_REG_KEY_ENTRY_2_7 (32'h69c) +`define KV_REG_KEY_ENTRY_2_8 (32'h6a0) +`define KV_REG_KEY_ENTRY_2_9 (32'h6a4) +`define KV_REG_KEY_ENTRY_2_10 (32'h6a8) +`define KV_REG_KEY_ENTRY_2_11 (32'h6ac) +`define KV_REG_KEY_ENTRY_2_12 (32'h6b0) +`define KV_REG_KEY_ENTRY_2_13 (32'h6b4) +`define KV_REG_KEY_ENTRY_2_14 (32'h6b8) +`define KV_REG_KEY_ENTRY_2_15 (32'h6bc) +`define KV_REG_KEY_ENTRY_3_0 (32'h6c0) +`define KV_REG_KEY_ENTRY_3_1 (32'h6c4) +`define KV_REG_KEY_ENTRY_3_2 (32'h6c8) +`define KV_REG_KEY_ENTRY_3_3 (32'h6cc) +`define KV_REG_KEY_ENTRY_3_4 (32'h6d0) +`define KV_REG_KEY_ENTRY_3_5 (32'h6d4) +`define KV_REG_KEY_ENTRY_3_6 (32'h6d8) +`define KV_REG_KEY_ENTRY_3_7 (32'h6dc) +`define KV_REG_KEY_ENTRY_3_8 (32'h6e0) +`define KV_REG_KEY_ENTRY_3_9 (32'h6e4) +`define KV_REG_KEY_ENTRY_3_10 (32'h6e8) +`define KV_REG_KEY_ENTRY_3_11 (32'h6ec) +`define KV_REG_KEY_ENTRY_3_12 (32'h6f0) +`define KV_REG_KEY_ENTRY_3_13 (32'h6f4) +`define KV_REG_KEY_ENTRY_3_14 (32'h6f8) +`define KV_REG_KEY_ENTRY_3_15 (32'h6fc) +`define KV_REG_KEY_ENTRY_4_0 (32'h700) +`define KV_REG_KEY_ENTRY_4_1 (32'h704) +`define KV_REG_KEY_ENTRY_4_2 (32'h708) +`define KV_REG_KEY_ENTRY_4_3 (32'h70c) +`define KV_REG_KEY_ENTRY_4_4 (32'h710) +`define KV_REG_KEY_ENTRY_4_5 (32'h714) +`define KV_REG_KEY_ENTRY_4_6 (32'h718) +`define KV_REG_KEY_ENTRY_4_7 (32'h71c) +`define KV_REG_KEY_ENTRY_4_8 (32'h720) +`define KV_REG_KEY_ENTRY_4_9 (32'h724) +`define KV_REG_KEY_ENTRY_4_10 (32'h728) +`define KV_REG_KEY_ENTRY_4_11 (32'h72c) +`define KV_REG_KEY_ENTRY_4_12 (32'h730) +`define KV_REG_KEY_ENTRY_4_13 (32'h734) +`define KV_REG_KEY_ENTRY_4_14 (32'h738) +`define KV_REG_KEY_ENTRY_4_15 (32'h73c) +`define KV_REG_KEY_ENTRY_5_0 (32'h740) +`define KV_REG_KEY_ENTRY_5_1 (32'h744) +`define KV_REG_KEY_ENTRY_5_2 (32'h748) +`define KV_REG_KEY_ENTRY_5_3 (32'h74c) +`define KV_REG_KEY_ENTRY_5_4 (32'h750) +`define KV_REG_KEY_ENTRY_5_5 (32'h754) +`define KV_REG_KEY_ENTRY_5_6 (32'h758) +`define KV_REG_KEY_ENTRY_5_7 (32'h75c) +`define KV_REG_KEY_ENTRY_5_8 (32'h760) +`define KV_REG_KEY_ENTRY_5_9 (32'h764) +`define KV_REG_KEY_ENTRY_5_10 (32'h768) +`define KV_REG_KEY_ENTRY_5_11 (32'h76c) +`define KV_REG_KEY_ENTRY_5_12 (32'h770) +`define KV_REG_KEY_ENTRY_5_13 (32'h774) +`define KV_REG_KEY_ENTRY_5_14 (32'h778) +`define KV_REG_KEY_ENTRY_5_15 (32'h77c) +`define KV_REG_KEY_ENTRY_6_0 (32'h780) +`define KV_REG_KEY_ENTRY_6_1 (32'h784) +`define KV_REG_KEY_ENTRY_6_2 (32'h788) +`define KV_REG_KEY_ENTRY_6_3 (32'h78c) +`define KV_REG_KEY_ENTRY_6_4 (32'h790) +`define KV_REG_KEY_ENTRY_6_5 (32'h794) +`define KV_REG_KEY_ENTRY_6_6 (32'h798) +`define KV_REG_KEY_ENTRY_6_7 (32'h79c) +`define KV_REG_KEY_ENTRY_6_8 (32'h7a0) +`define KV_REG_KEY_ENTRY_6_9 (32'h7a4) +`define KV_REG_KEY_ENTRY_6_10 (32'h7a8) +`define KV_REG_KEY_ENTRY_6_11 (32'h7ac) +`define KV_REG_KEY_ENTRY_6_12 (32'h7b0) +`define KV_REG_KEY_ENTRY_6_13 (32'h7b4) +`define KV_REG_KEY_ENTRY_6_14 (32'h7b8) +`define KV_REG_KEY_ENTRY_6_15 (32'h7bc) +`define KV_REG_KEY_ENTRY_7_0 (32'h7c0) +`define KV_REG_KEY_ENTRY_7_1 (32'h7c4) +`define KV_REG_KEY_ENTRY_7_2 (32'h7c8) +`define KV_REG_KEY_ENTRY_7_3 (32'h7cc) +`define KV_REG_KEY_ENTRY_7_4 (32'h7d0) +`define KV_REG_KEY_ENTRY_7_5 (32'h7d4) +`define KV_REG_KEY_ENTRY_7_6 (32'h7d8) +`define KV_REG_KEY_ENTRY_7_7 (32'h7dc) +`define KV_REG_KEY_ENTRY_7_8 (32'h7e0) +`define KV_REG_KEY_ENTRY_7_9 (32'h7e4) +`define KV_REG_KEY_ENTRY_7_10 (32'h7e8) +`define KV_REG_KEY_ENTRY_7_11 (32'h7ec) +`define KV_REG_KEY_ENTRY_7_12 (32'h7f0) +`define KV_REG_KEY_ENTRY_7_13 (32'h7f4) +`define KV_REG_KEY_ENTRY_7_14 (32'h7f8) +`define KV_REG_KEY_ENTRY_7_15 (32'h7fc) +`define KV_REG_KEY_ENTRY_8_0 (32'h800) +`define KV_REG_KEY_ENTRY_8_1 (32'h804) +`define KV_REG_KEY_ENTRY_8_2 (32'h808) +`define KV_REG_KEY_ENTRY_8_3 (32'h80c) +`define KV_REG_KEY_ENTRY_8_4 (32'h810) +`define KV_REG_KEY_ENTRY_8_5 (32'h814) +`define KV_REG_KEY_ENTRY_8_6 (32'h818) +`define KV_REG_KEY_ENTRY_8_7 (32'h81c) +`define KV_REG_KEY_ENTRY_8_8 (32'h820) +`define KV_REG_KEY_ENTRY_8_9 (32'h824) +`define KV_REG_KEY_ENTRY_8_10 (32'h828) +`define KV_REG_KEY_ENTRY_8_11 (32'h82c) +`define KV_REG_KEY_ENTRY_8_12 (32'h830) +`define KV_REG_KEY_ENTRY_8_13 (32'h834) +`define KV_REG_KEY_ENTRY_8_14 (32'h838) +`define KV_REG_KEY_ENTRY_8_15 (32'h83c) +`define KV_REG_KEY_ENTRY_9_0 (32'h840) +`define KV_REG_KEY_ENTRY_9_1 (32'h844) +`define KV_REG_KEY_ENTRY_9_2 (32'h848) +`define KV_REG_KEY_ENTRY_9_3 (32'h84c) +`define KV_REG_KEY_ENTRY_9_4 (32'h850) +`define KV_REG_KEY_ENTRY_9_5 (32'h854) +`define KV_REG_KEY_ENTRY_9_6 (32'h858) +`define KV_REG_KEY_ENTRY_9_7 (32'h85c) +`define KV_REG_KEY_ENTRY_9_8 (32'h860) +`define KV_REG_KEY_ENTRY_9_9 (32'h864) +`define KV_REG_KEY_ENTRY_9_10 (32'h868) +`define KV_REG_KEY_ENTRY_9_11 (32'h86c) +`define KV_REG_KEY_ENTRY_9_12 (32'h870) +`define KV_REG_KEY_ENTRY_9_13 (32'h874) +`define KV_REG_KEY_ENTRY_9_14 (32'h878) +`define KV_REG_KEY_ENTRY_9_15 (32'h87c) +`define KV_REG_KEY_ENTRY_10_0 (32'h880) +`define KV_REG_KEY_ENTRY_10_1 (32'h884) +`define KV_REG_KEY_ENTRY_10_2 (32'h888) +`define KV_REG_KEY_ENTRY_10_3 (32'h88c) +`define KV_REG_KEY_ENTRY_10_4 (32'h890) +`define KV_REG_KEY_ENTRY_10_5 (32'h894) +`define KV_REG_KEY_ENTRY_10_6 (32'h898) +`define KV_REG_KEY_ENTRY_10_7 (32'h89c) +`define KV_REG_KEY_ENTRY_10_8 (32'h8a0) +`define KV_REG_KEY_ENTRY_10_9 (32'h8a4) +`define KV_REG_KEY_ENTRY_10_10 (32'h8a8) +`define KV_REG_KEY_ENTRY_10_11 (32'h8ac) +`define KV_REG_KEY_ENTRY_10_12 (32'h8b0) +`define KV_REG_KEY_ENTRY_10_13 (32'h8b4) +`define KV_REG_KEY_ENTRY_10_14 (32'h8b8) +`define KV_REG_KEY_ENTRY_10_15 (32'h8bc) +`define KV_REG_KEY_ENTRY_11_0 (32'h8c0) +`define KV_REG_KEY_ENTRY_11_1 (32'h8c4) +`define KV_REG_KEY_ENTRY_11_2 (32'h8c8) +`define KV_REG_KEY_ENTRY_11_3 (32'h8cc) +`define KV_REG_KEY_ENTRY_11_4 (32'h8d0) +`define KV_REG_KEY_ENTRY_11_5 (32'h8d4) +`define KV_REG_KEY_ENTRY_11_6 (32'h8d8) +`define KV_REG_KEY_ENTRY_11_7 (32'h8dc) +`define KV_REG_KEY_ENTRY_11_8 (32'h8e0) +`define KV_REG_KEY_ENTRY_11_9 (32'h8e4) +`define KV_REG_KEY_ENTRY_11_10 (32'h8e8) +`define KV_REG_KEY_ENTRY_11_11 (32'h8ec) +`define KV_REG_KEY_ENTRY_11_12 (32'h8f0) +`define KV_REG_KEY_ENTRY_11_13 (32'h8f4) +`define KV_REG_KEY_ENTRY_11_14 (32'h8f8) +`define KV_REG_KEY_ENTRY_11_15 (32'h8fc) +`define KV_REG_KEY_ENTRY_12_0 (32'h900) +`define KV_REG_KEY_ENTRY_12_1 (32'h904) +`define KV_REG_KEY_ENTRY_12_2 (32'h908) +`define KV_REG_KEY_ENTRY_12_3 (32'h90c) +`define KV_REG_KEY_ENTRY_12_4 (32'h910) +`define KV_REG_KEY_ENTRY_12_5 (32'h914) +`define KV_REG_KEY_ENTRY_12_6 (32'h918) +`define KV_REG_KEY_ENTRY_12_7 (32'h91c) +`define KV_REG_KEY_ENTRY_12_8 (32'h920) +`define KV_REG_KEY_ENTRY_12_9 (32'h924) +`define KV_REG_KEY_ENTRY_12_10 (32'h928) +`define KV_REG_KEY_ENTRY_12_11 (32'h92c) +`define KV_REG_KEY_ENTRY_12_12 (32'h930) +`define KV_REG_KEY_ENTRY_12_13 (32'h934) +`define KV_REG_KEY_ENTRY_12_14 (32'h938) +`define KV_REG_KEY_ENTRY_12_15 (32'h93c) +`define KV_REG_KEY_ENTRY_13_0 (32'h940) +`define KV_REG_KEY_ENTRY_13_1 (32'h944) +`define KV_REG_KEY_ENTRY_13_2 (32'h948) +`define KV_REG_KEY_ENTRY_13_3 (32'h94c) +`define KV_REG_KEY_ENTRY_13_4 (32'h950) +`define KV_REG_KEY_ENTRY_13_5 (32'h954) +`define KV_REG_KEY_ENTRY_13_6 (32'h958) +`define KV_REG_KEY_ENTRY_13_7 (32'h95c) +`define KV_REG_KEY_ENTRY_13_8 (32'h960) +`define KV_REG_KEY_ENTRY_13_9 (32'h964) +`define KV_REG_KEY_ENTRY_13_10 (32'h968) +`define KV_REG_KEY_ENTRY_13_11 (32'h96c) +`define KV_REG_KEY_ENTRY_13_12 (32'h970) +`define KV_REG_KEY_ENTRY_13_13 (32'h974) +`define KV_REG_KEY_ENTRY_13_14 (32'h978) +`define KV_REG_KEY_ENTRY_13_15 (32'h97c) +`define KV_REG_KEY_ENTRY_14_0 (32'h980) +`define KV_REG_KEY_ENTRY_14_1 (32'h984) +`define KV_REG_KEY_ENTRY_14_2 (32'h988) +`define KV_REG_KEY_ENTRY_14_3 (32'h98c) +`define KV_REG_KEY_ENTRY_14_4 (32'h990) +`define KV_REG_KEY_ENTRY_14_5 (32'h994) +`define KV_REG_KEY_ENTRY_14_6 (32'h998) +`define KV_REG_KEY_ENTRY_14_7 (32'h99c) +`define KV_REG_KEY_ENTRY_14_8 (32'h9a0) +`define KV_REG_KEY_ENTRY_14_9 (32'h9a4) +`define KV_REG_KEY_ENTRY_14_10 (32'h9a8) +`define KV_REG_KEY_ENTRY_14_11 (32'h9ac) +`define KV_REG_KEY_ENTRY_14_12 (32'h9b0) +`define KV_REG_KEY_ENTRY_14_13 (32'h9b4) +`define KV_REG_KEY_ENTRY_14_14 (32'h9b8) +`define KV_REG_KEY_ENTRY_14_15 (32'h9bc) +`define KV_REG_KEY_ENTRY_15_0 (32'h9c0) +`define KV_REG_KEY_ENTRY_15_1 (32'h9c4) +`define KV_REG_KEY_ENTRY_15_2 (32'h9c8) +`define KV_REG_KEY_ENTRY_15_3 (32'h9cc) +`define KV_REG_KEY_ENTRY_15_4 (32'h9d0) +`define KV_REG_KEY_ENTRY_15_5 (32'h9d4) +`define KV_REG_KEY_ENTRY_15_6 (32'h9d8) +`define KV_REG_KEY_ENTRY_15_7 (32'h9dc) +`define KV_REG_KEY_ENTRY_15_8 (32'h9e0) +`define KV_REG_KEY_ENTRY_15_9 (32'h9e4) +`define KV_REG_KEY_ENTRY_15_10 (32'h9e8) +`define KV_REG_KEY_ENTRY_15_11 (32'h9ec) +`define KV_REG_KEY_ENTRY_15_12 (32'h9f0) +`define KV_REG_KEY_ENTRY_15_13 (32'h9f4) +`define KV_REG_KEY_ENTRY_15_14 (32'h9f8) +`define KV_REG_KEY_ENTRY_15_15 (32'h9fc) +`define KV_REG_KEY_ENTRY_16_0 (32'ha00) +`define KV_REG_KEY_ENTRY_16_1 (32'ha04) +`define KV_REG_KEY_ENTRY_16_2 (32'ha08) +`define KV_REG_KEY_ENTRY_16_3 (32'ha0c) +`define KV_REG_KEY_ENTRY_16_4 (32'ha10) +`define KV_REG_KEY_ENTRY_16_5 (32'ha14) +`define KV_REG_KEY_ENTRY_16_6 (32'ha18) +`define KV_REG_KEY_ENTRY_16_7 (32'ha1c) +`define KV_REG_KEY_ENTRY_16_8 (32'ha20) +`define KV_REG_KEY_ENTRY_16_9 (32'ha24) +`define KV_REG_KEY_ENTRY_16_10 (32'ha28) +`define KV_REG_KEY_ENTRY_16_11 (32'ha2c) +`define KV_REG_KEY_ENTRY_16_12 (32'ha30) +`define KV_REG_KEY_ENTRY_16_13 (32'ha34) +`define KV_REG_KEY_ENTRY_16_14 (32'ha38) +`define KV_REG_KEY_ENTRY_16_15 (32'ha3c) +`define KV_REG_KEY_ENTRY_17_0 (32'ha40) +`define KV_REG_KEY_ENTRY_17_1 (32'ha44) +`define KV_REG_KEY_ENTRY_17_2 (32'ha48) +`define KV_REG_KEY_ENTRY_17_3 (32'ha4c) +`define KV_REG_KEY_ENTRY_17_4 (32'ha50) +`define KV_REG_KEY_ENTRY_17_5 (32'ha54) +`define KV_REG_KEY_ENTRY_17_6 (32'ha58) +`define KV_REG_KEY_ENTRY_17_7 (32'ha5c) +`define KV_REG_KEY_ENTRY_17_8 (32'ha60) +`define KV_REG_KEY_ENTRY_17_9 (32'ha64) +`define KV_REG_KEY_ENTRY_17_10 (32'ha68) +`define KV_REG_KEY_ENTRY_17_11 (32'ha6c) +`define KV_REG_KEY_ENTRY_17_12 (32'ha70) +`define KV_REG_KEY_ENTRY_17_13 (32'ha74) +`define KV_REG_KEY_ENTRY_17_14 (32'ha78) +`define KV_REG_KEY_ENTRY_17_15 (32'ha7c) +`define KV_REG_KEY_ENTRY_18_0 (32'ha80) +`define KV_REG_KEY_ENTRY_18_1 (32'ha84) +`define KV_REG_KEY_ENTRY_18_2 (32'ha88) +`define KV_REG_KEY_ENTRY_18_3 (32'ha8c) +`define KV_REG_KEY_ENTRY_18_4 (32'ha90) +`define KV_REG_KEY_ENTRY_18_5 (32'ha94) +`define KV_REG_KEY_ENTRY_18_6 (32'ha98) +`define KV_REG_KEY_ENTRY_18_7 (32'ha9c) +`define KV_REG_KEY_ENTRY_18_8 (32'haa0) +`define KV_REG_KEY_ENTRY_18_9 (32'haa4) +`define KV_REG_KEY_ENTRY_18_10 (32'haa8) +`define KV_REG_KEY_ENTRY_18_11 (32'haac) +`define KV_REG_KEY_ENTRY_18_12 (32'hab0) +`define KV_REG_KEY_ENTRY_18_13 (32'hab4) +`define KV_REG_KEY_ENTRY_18_14 (32'hab8) +`define KV_REG_KEY_ENTRY_18_15 (32'habc) +`define KV_REG_KEY_ENTRY_19_0 (32'hac0) +`define KV_REG_KEY_ENTRY_19_1 (32'hac4) +`define KV_REG_KEY_ENTRY_19_2 (32'hac8) +`define KV_REG_KEY_ENTRY_19_3 (32'hacc) +`define KV_REG_KEY_ENTRY_19_4 (32'had0) +`define KV_REG_KEY_ENTRY_19_5 (32'had4) +`define KV_REG_KEY_ENTRY_19_6 (32'had8) +`define KV_REG_KEY_ENTRY_19_7 (32'hadc) +`define KV_REG_KEY_ENTRY_19_8 (32'hae0) +`define KV_REG_KEY_ENTRY_19_9 (32'hae4) +`define KV_REG_KEY_ENTRY_19_10 (32'hae8) +`define KV_REG_KEY_ENTRY_19_11 (32'haec) +`define KV_REG_KEY_ENTRY_19_12 (32'haf0) +`define KV_REG_KEY_ENTRY_19_13 (32'haf4) +`define KV_REG_KEY_ENTRY_19_14 (32'haf8) +`define KV_REG_KEY_ENTRY_19_15 (32'hafc) +`define KV_REG_KEY_ENTRY_20_0 (32'hb00) +`define KV_REG_KEY_ENTRY_20_1 (32'hb04) +`define KV_REG_KEY_ENTRY_20_2 (32'hb08) +`define KV_REG_KEY_ENTRY_20_3 (32'hb0c) +`define KV_REG_KEY_ENTRY_20_4 (32'hb10) +`define KV_REG_KEY_ENTRY_20_5 (32'hb14) +`define KV_REG_KEY_ENTRY_20_6 (32'hb18) +`define KV_REG_KEY_ENTRY_20_7 (32'hb1c) +`define KV_REG_KEY_ENTRY_20_8 (32'hb20) +`define KV_REG_KEY_ENTRY_20_9 (32'hb24) +`define KV_REG_KEY_ENTRY_20_10 (32'hb28) +`define KV_REG_KEY_ENTRY_20_11 (32'hb2c) +`define KV_REG_KEY_ENTRY_20_12 (32'hb30) +`define KV_REG_KEY_ENTRY_20_13 (32'hb34) +`define KV_REG_KEY_ENTRY_20_14 (32'hb38) +`define KV_REG_KEY_ENTRY_20_15 (32'hb3c) +`define KV_REG_KEY_ENTRY_21_0 (32'hb40) +`define KV_REG_KEY_ENTRY_21_1 (32'hb44) +`define KV_REG_KEY_ENTRY_21_2 (32'hb48) +`define KV_REG_KEY_ENTRY_21_3 (32'hb4c) +`define KV_REG_KEY_ENTRY_21_4 (32'hb50) +`define KV_REG_KEY_ENTRY_21_5 (32'hb54) +`define KV_REG_KEY_ENTRY_21_6 (32'hb58) +`define KV_REG_KEY_ENTRY_21_7 (32'hb5c) +`define KV_REG_KEY_ENTRY_21_8 (32'hb60) +`define KV_REG_KEY_ENTRY_21_9 (32'hb64) +`define KV_REG_KEY_ENTRY_21_10 (32'hb68) +`define KV_REG_KEY_ENTRY_21_11 (32'hb6c) +`define KV_REG_KEY_ENTRY_21_12 (32'hb70) +`define KV_REG_KEY_ENTRY_21_13 (32'hb74) +`define KV_REG_KEY_ENTRY_21_14 (32'hb78) +`define KV_REG_KEY_ENTRY_21_15 (32'hb7c) +`define KV_REG_KEY_ENTRY_22_0 (32'hb80) +`define KV_REG_KEY_ENTRY_22_1 (32'hb84) +`define KV_REG_KEY_ENTRY_22_2 (32'hb88) +`define KV_REG_KEY_ENTRY_22_3 (32'hb8c) +`define KV_REG_KEY_ENTRY_22_4 (32'hb90) +`define KV_REG_KEY_ENTRY_22_5 (32'hb94) +`define KV_REG_KEY_ENTRY_22_6 (32'hb98) +`define KV_REG_KEY_ENTRY_22_7 (32'hb9c) +`define KV_REG_KEY_ENTRY_22_8 (32'hba0) +`define KV_REG_KEY_ENTRY_22_9 (32'hba4) +`define KV_REG_KEY_ENTRY_22_10 (32'hba8) +`define KV_REG_KEY_ENTRY_22_11 (32'hbac) +`define KV_REG_KEY_ENTRY_22_12 (32'hbb0) +`define KV_REG_KEY_ENTRY_22_13 (32'hbb4) +`define KV_REG_KEY_ENTRY_22_14 (32'hbb8) +`define KV_REG_KEY_ENTRY_22_15 (32'hbbc) +`define KV_REG_KEY_ENTRY_23_0 (32'hbc0) +`define KV_REG_KEY_ENTRY_23_1 (32'hbc4) +`define KV_REG_KEY_ENTRY_23_2 (32'hbc8) +`define KV_REG_KEY_ENTRY_23_3 (32'hbcc) +`define KV_REG_KEY_ENTRY_23_4 (32'hbd0) +`define KV_REG_KEY_ENTRY_23_5 (32'hbd4) +`define KV_REG_KEY_ENTRY_23_6 (32'hbd8) +`define KV_REG_KEY_ENTRY_23_7 (32'hbdc) +`define KV_REG_KEY_ENTRY_23_8 (32'hbe0) +`define KV_REG_KEY_ENTRY_23_9 (32'hbe4) +`define KV_REG_KEY_ENTRY_23_10 (32'hbe8) +`define KV_REG_KEY_ENTRY_23_11 (32'hbec) +`define KV_REG_KEY_ENTRY_23_12 (32'hbf0) +`define KV_REG_KEY_ENTRY_23_13 (32'hbf4) +`define KV_REG_KEY_ENTRY_23_14 (32'hbf8) +`define KV_REG_KEY_ENTRY_23_15 (32'hbfc) +`define KV_REG_CLEAR_SECRETS (32'hc00) +`define KV_REG_CLEAR_SECRETS_WR_DEBUG_VALUES_LOW (0) +`define KV_REG_CLEAR_SECRETS_WR_DEBUG_VALUES_MASK (32'h1) +`define KV_REG_CLEAR_SECRETS_SEL_DEBUG_VALUE_LOW (1) +`define KV_REG_CLEAR_SECRETS_SEL_DEBUG_VALUE_MASK (32'h2) +`define PV_REG_PCR_CTRL_0 (32'h0) +`define PV_REG_PCR_CTRL_0_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_0_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_0_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_0_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_0_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_0_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_0_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_0_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_1 (32'h4) +`define PV_REG_PCR_CTRL_1_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_1_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_1_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_1_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_1_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_1_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_1_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_1_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_2 (32'h8) +`define PV_REG_PCR_CTRL_2_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_2_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_2_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_2_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_2_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_2_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_2_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_2_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_3 (32'hc) +`define PV_REG_PCR_CTRL_3_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_3_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_3_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_3_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_3_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_3_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_3_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_3_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_4 (32'h10) +`define PV_REG_PCR_CTRL_4_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_4_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_4_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_4_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_4_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_4_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_4_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_4_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_5 (32'h14) +`define PV_REG_PCR_CTRL_5_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_5_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_5_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_5_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_5_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_5_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_5_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_5_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_6 (32'h18) +`define PV_REG_PCR_CTRL_6_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_6_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_6_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_6_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_6_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_6_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_6_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_6_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_7 (32'h1c) +`define PV_REG_PCR_CTRL_7_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_7_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_7_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_7_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_7_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_7_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_7_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_7_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_8 (32'h20) +`define PV_REG_PCR_CTRL_8_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_8_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_8_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_8_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_8_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_8_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_8_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_8_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_9 (32'h24) +`define PV_REG_PCR_CTRL_9_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_9_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_9_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_9_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_9_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_9_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_9_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_9_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_10 (32'h28) +`define PV_REG_PCR_CTRL_10_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_10_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_10_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_10_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_10_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_10_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_10_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_10_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_11 (32'h2c) +`define PV_REG_PCR_CTRL_11_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_11_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_11_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_11_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_11_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_11_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_11_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_11_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_12 (32'h30) +`define PV_REG_PCR_CTRL_12_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_12_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_12_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_12_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_12_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_12_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_12_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_12_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_13 (32'h34) +`define PV_REG_PCR_CTRL_13_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_13_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_13_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_13_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_13_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_13_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_13_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_13_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_14 (32'h38) +`define PV_REG_PCR_CTRL_14_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_14_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_14_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_14_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_14_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_14_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_14_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_14_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_15 (32'h3c) +`define PV_REG_PCR_CTRL_15_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_15_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_15_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_15_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_15_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_15_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_15_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_15_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_16 (32'h40) +`define PV_REG_PCR_CTRL_16_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_16_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_16_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_16_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_16_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_16_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_16_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_16_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_17 (32'h44) +`define PV_REG_PCR_CTRL_17_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_17_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_17_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_17_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_17_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_17_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_17_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_17_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_18 (32'h48) +`define PV_REG_PCR_CTRL_18_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_18_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_18_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_18_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_18_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_18_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_18_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_18_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_19 (32'h4c) +`define PV_REG_PCR_CTRL_19_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_19_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_19_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_19_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_19_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_19_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_19_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_19_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_20 (32'h50) +`define PV_REG_PCR_CTRL_20_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_20_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_20_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_20_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_20_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_20_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_20_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_20_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_21 (32'h54) +`define PV_REG_PCR_CTRL_21_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_21_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_21_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_21_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_21_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_21_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_21_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_21_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_22 (32'h58) +`define PV_REG_PCR_CTRL_22_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_22_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_22_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_22_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_22_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_22_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_22_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_22_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_23 (32'h5c) +`define PV_REG_PCR_CTRL_23_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_23_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_23_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_23_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_23_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_23_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_23_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_23_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_24 (32'h60) +`define PV_REG_PCR_CTRL_24_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_24_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_24_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_24_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_24_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_24_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_24_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_24_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_25 (32'h64) +`define PV_REG_PCR_CTRL_25_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_25_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_25_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_25_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_25_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_25_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_25_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_25_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_26 (32'h68) +`define PV_REG_PCR_CTRL_26_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_26_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_26_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_26_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_26_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_26_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_26_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_26_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_27 (32'h6c) +`define PV_REG_PCR_CTRL_27_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_27_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_27_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_27_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_27_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_27_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_27_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_27_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_28 (32'h70) +`define PV_REG_PCR_CTRL_28_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_28_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_28_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_28_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_28_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_28_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_28_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_28_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_29 (32'h74) +`define PV_REG_PCR_CTRL_29_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_29_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_29_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_29_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_29_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_29_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_29_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_29_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_30 (32'h78) +`define PV_REG_PCR_CTRL_30_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_30_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_30_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_30_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_30_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_30_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_30_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_30_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_CTRL_31 (32'h7c) +`define PV_REG_PCR_CTRL_31_LOCK_LOW (0) +`define PV_REG_PCR_CTRL_31_LOCK_MASK (32'h1) +`define PV_REG_PCR_CTRL_31_CLEAR_LOW (1) +`define PV_REG_PCR_CTRL_31_CLEAR_MASK (32'h2) +`define PV_REG_PCR_CTRL_31_RSVD0_LOW (2) +`define PV_REG_PCR_CTRL_31_RSVD0_MASK (32'h4) +`define PV_REG_PCR_CTRL_31_RSVD1_LOW (3) +`define PV_REG_PCR_CTRL_31_RSVD1_MASK (32'hf8) +`define PV_REG_PCR_ENTRY_0_0 (32'h600) +`define PV_REG_PCR_ENTRY_0_1 (32'h604) +`define PV_REG_PCR_ENTRY_0_2 (32'h608) +`define PV_REG_PCR_ENTRY_0_3 (32'h60c) +`define PV_REG_PCR_ENTRY_0_4 (32'h610) +`define PV_REG_PCR_ENTRY_0_5 (32'h614) +`define PV_REG_PCR_ENTRY_0_6 (32'h618) +`define PV_REG_PCR_ENTRY_0_7 (32'h61c) +`define PV_REG_PCR_ENTRY_0_8 (32'h620) +`define PV_REG_PCR_ENTRY_0_9 (32'h624) +`define PV_REG_PCR_ENTRY_0_10 (32'h628) +`define PV_REG_PCR_ENTRY_0_11 (32'h62c) +`define PV_REG_PCR_ENTRY_1_0 (32'h630) +`define PV_REG_PCR_ENTRY_1_1 (32'h634) +`define PV_REG_PCR_ENTRY_1_2 (32'h638) +`define PV_REG_PCR_ENTRY_1_3 (32'h63c) +`define PV_REG_PCR_ENTRY_1_4 (32'h640) +`define PV_REG_PCR_ENTRY_1_5 (32'h644) +`define PV_REG_PCR_ENTRY_1_6 (32'h648) +`define PV_REG_PCR_ENTRY_1_7 (32'h64c) +`define PV_REG_PCR_ENTRY_1_8 (32'h650) +`define PV_REG_PCR_ENTRY_1_9 (32'h654) +`define PV_REG_PCR_ENTRY_1_10 (32'h658) +`define PV_REG_PCR_ENTRY_1_11 (32'h65c) +`define PV_REG_PCR_ENTRY_2_0 (32'h660) +`define PV_REG_PCR_ENTRY_2_1 (32'h664) +`define PV_REG_PCR_ENTRY_2_2 (32'h668) +`define PV_REG_PCR_ENTRY_2_3 (32'h66c) +`define PV_REG_PCR_ENTRY_2_4 (32'h670) +`define PV_REG_PCR_ENTRY_2_5 (32'h674) +`define PV_REG_PCR_ENTRY_2_6 (32'h678) +`define PV_REG_PCR_ENTRY_2_7 (32'h67c) +`define PV_REG_PCR_ENTRY_2_8 (32'h680) +`define PV_REG_PCR_ENTRY_2_9 (32'h684) +`define PV_REG_PCR_ENTRY_2_10 (32'h688) +`define PV_REG_PCR_ENTRY_2_11 (32'h68c) +`define PV_REG_PCR_ENTRY_3_0 (32'h690) +`define PV_REG_PCR_ENTRY_3_1 (32'h694) +`define PV_REG_PCR_ENTRY_3_2 (32'h698) +`define PV_REG_PCR_ENTRY_3_3 (32'h69c) +`define PV_REG_PCR_ENTRY_3_4 (32'h6a0) +`define PV_REG_PCR_ENTRY_3_5 (32'h6a4) +`define PV_REG_PCR_ENTRY_3_6 (32'h6a8) +`define PV_REG_PCR_ENTRY_3_7 (32'h6ac) +`define PV_REG_PCR_ENTRY_3_8 (32'h6b0) +`define PV_REG_PCR_ENTRY_3_9 (32'h6b4) +`define PV_REG_PCR_ENTRY_3_10 (32'h6b8) +`define PV_REG_PCR_ENTRY_3_11 (32'h6bc) +`define PV_REG_PCR_ENTRY_4_0 (32'h6c0) +`define PV_REG_PCR_ENTRY_4_1 (32'h6c4) +`define PV_REG_PCR_ENTRY_4_2 (32'h6c8) +`define PV_REG_PCR_ENTRY_4_3 (32'h6cc) +`define PV_REG_PCR_ENTRY_4_4 (32'h6d0) +`define PV_REG_PCR_ENTRY_4_5 (32'h6d4) +`define PV_REG_PCR_ENTRY_4_6 (32'h6d8) +`define PV_REG_PCR_ENTRY_4_7 (32'h6dc) +`define PV_REG_PCR_ENTRY_4_8 (32'h6e0) +`define PV_REG_PCR_ENTRY_4_9 (32'h6e4) +`define PV_REG_PCR_ENTRY_4_10 (32'h6e8) +`define PV_REG_PCR_ENTRY_4_11 (32'h6ec) +`define PV_REG_PCR_ENTRY_5_0 (32'h6f0) +`define PV_REG_PCR_ENTRY_5_1 (32'h6f4) +`define PV_REG_PCR_ENTRY_5_2 (32'h6f8) +`define PV_REG_PCR_ENTRY_5_3 (32'h6fc) +`define PV_REG_PCR_ENTRY_5_4 (32'h700) +`define PV_REG_PCR_ENTRY_5_5 (32'h704) +`define PV_REG_PCR_ENTRY_5_6 (32'h708) +`define PV_REG_PCR_ENTRY_5_7 (32'h70c) +`define PV_REG_PCR_ENTRY_5_8 (32'h710) +`define PV_REG_PCR_ENTRY_5_9 (32'h714) +`define PV_REG_PCR_ENTRY_5_10 (32'h718) +`define PV_REG_PCR_ENTRY_5_11 (32'h71c) +`define PV_REG_PCR_ENTRY_6_0 (32'h720) +`define PV_REG_PCR_ENTRY_6_1 (32'h724) +`define PV_REG_PCR_ENTRY_6_2 (32'h728) +`define PV_REG_PCR_ENTRY_6_3 (32'h72c) +`define PV_REG_PCR_ENTRY_6_4 (32'h730) +`define PV_REG_PCR_ENTRY_6_5 (32'h734) +`define PV_REG_PCR_ENTRY_6_6 (32'h738) +`define PV_REG_PCR_ENTRY_6_7 (32'h73c) +`define PV_REG_PCR_ENTRY_6_8 (32'h740) +`define PV_REG_PCR_ENTRY_6_9 (32'h744) +`define PV_REG_PCR_ENTRY_6_10 (32'h748) +`define PV_REG_PCR_ENTRY_6_11 (32'h74c) +`define PV_REG_PCR_ENTRY_7_0 (32'h750) +`define PV_REG_PCR_ENTRY_7_1 (32'h754) +`define PV_REG_PCR_ENTRY_7_2 (32'h758) +`define PV_REG_PCR_ENTRY_7_3 (32'h75c) +`define PV_REG_PCR_ENTRY_7_4 (32'h760) +`define PV_REG_PCR_ENTRY_7_5 (32'h764) +`define PV_REG_PCR_ENTRY_7_6 (32'h768) +`define PV_REG_PCR_ENTRY_7_7 (32'h76c) +`define PV_REG_PCR_ENTRY_7_8 (32'h770) +`define PV_REG_PCR_ENTRY_7_9 (32'h774) +`define PV_REG_PCR_ENTRY_7_10 (32'h778) +`define PV_REG_PCR_ENTRY_7_11 (32'h77c) +`define PV_REG_PCR_ENTRY_8_0 (32'h780) +`define PV_REG_PCR_ENTRY_8_1 (32'h784) +`define PV_REG_PCR_ENTRY_8_2 (32'h788) +`define PV_REG_PCR_ENTRY_8_3 (32'h78c) +`define PV_REG_PCR_ENTRY_8_4 (32'h790) +`define PV_REG_PCR_ENTRY_8_5 (32'h794) +`define PV_REG_PCR_ENTRY_8_6 (32'h798) +`define PV_REG_PCR_ENTRY_8_7 (32'h79c) +`define PV_REG_PCR_ENTRY_8_8 (32'h7a0) +`define PV_REG_PCR_ENTRY_8_9 (32'h7a4) +`define PV_REG_PCR_ENTRY_8_10 (32'h7a8) +`define PV_REG_PCR_ENTRY_8_11 (32'h7ac) +`define PV_REG_PCR_ENTRY_9_0 (32'h7b0) +`define PV_REG_PCR_ENTRY_9_1 (32'h7b4) +`define PV_REG_PCR_ENTRY_9_2 (32'h7b8) +`define PV_REG_PCR_ENTRY_9_3 (32'h7bc) +`define PV_REG_PCR_ENTRY_9_4 (32'h7c0) +`define PV_REG_PCR_ENTRY_9_5 (32'h7c4) +`define PV_REG_PCR_ENTRY_9_6 (32'h7c8) +`define PV_REG_PCR_ENTRY_9_7 (32'h7cc) +`define PV_REG_PCR_ENTRY_9_8 (32'h7d0) +`define PV_REG_PCR_ENTRY_9_9 (32'h7d4) +`define PV_REG_PCR_ENTRY_9_10 (32'h7d8) +`define PV_REG_PCR_ENTRY_9_11 (32'h7dc) +`define PV_REG_PCR_ENTRY_10_0 (32'h7e0) +`define PV_REG_PCR_ENTRY_10_1 (32'h7e4) +`define PV_REG_PCR_ENTRY_10_2 (32'h7e8) +`define PV_REG_PCR_ENTRY_10_3 (32'h7ec) +`define PV_REG_PCR_ENTRY_10_4 (32'h7f0) +`define PV_REG_PCR_ENTRY_10_5 (32'h7f4) +`define PV_REG_PCR_ENTRY_10_6 (32'h7f8) +`define PV_REG_PCR_ENTRY_10_7 (32'h7fc) +`define PV_REG_PCR_ENTRY_10_8 (32'h800) +`define PV_REG_PCR_ENTRY_10_9 (32'h804) +`define PV_REG_PCR_ENTRY_10_10 (32'h808) +`define PV_REG_PCR_ENTRY_10_11 (32'h80c) +`define PV_REG_PCR_ENTRY_11_0 (32'h810) +`define PV_REG_PCR_ENTRY_11_1 (32'h814) +`define PV_REG_PCR_ENTRY_11_2 (32'h818) +`define PV_REG_PCR_ENTRY_11_3 (32'h81c) +`define PV_REG_PCR_ENTRY_11_4 (32'h820) +`define PV_REG_PCR_ENTRY_11_5 (32'h824) +`define PV_REG_PCR_ENTRY_11_6 (32'h828) +`define PV_REG_PCR_ENTRY_11_7 (32'h82c) +`define PV_REG_PCR_ENTRY_11_8 (32'h830) +`define PV_REG_PCR_ENTRY_11_9 (32'h834) +`define PV_REG_PCR_ENTRY_11_10 (32'h838) +`define PV_REG_PCR_ENTRY_11_11 (32'h83c) +`define PV_REG_PCR_ENTRY_12_0 (32'h840) +`define PV_REG_PCR_ENTRY_12_1 (32'h844) +`define PV_REG_PCR_ENTRY_12_2 (32'h848) +`define PV_REG_PCR_ENTRY_12_3 (32'h84c) +`define PV_REG_PCR_ENTRY_12_4 (32'h850) +`define PV_REG_PCR_ENTRY_12_5 (32'h854) +`define PV_REG_PCR_ENTRY_12_6 (32'h858) +`define PV_REG_PCR_ENTRY_12_7 (32'h85c) +`define PV_REG_PCR_ENTRY_12_8 (32'h860) +`define PV_REG_PCR_ENTRY_12_9 (32'h864) +`define PV_REG_PCR_ENTRY_12_10 (32'h868) +`define PV_REG_PCR_ENTRY_12_11 (32'h86c) +`define PV_REG_PCR_ENTRY_13_0 (32'h870) +`define PV_REG_PCR_ENTRY_13_1 (32'h874) +`define PV_REG_PCR_ENTRY_13_2 (32'h878) +`define PV_REG_PCR_ENTRY_13_3 (32'h87c) +`define PV_REG_PCR_ENTRY_13_4 (32'h880) +`define PV_REG_PCR_ENTRY_13_5 (32'h884) +`define PV_REG_PCR_ENTRY_13_6 (32'h888) +`define PV_REG_PCR_ENTRY_13_7 (32'h88c) +`define PV_REG_PCR_ENTRY_13_8 (32'h890) +`define PV_REG_PCR_ENTRY_13_9 (32'h894) +`define PV_REG_PCR_ENTRY_13_10 (32'h898) +`define PV_REG_PCR_ENTRY_13_11 (32'h89c) +`define PV_REG_PCR_ENTRY_14_0 (32'h8a0) +`define PV_REG_PCR_ENTRY_14_1 (32'h8a4) +`define PV_REG_PCR_ENTRY_14_2 (32'h8a8) +`define PV_REG_PCR_ENTRY_14_3 (32'h8ac) +`define PV_REG_PCR_ENTRY_14_4 (32'h8b0) +`define PV_REG_PCR_ENTRY_14_5 (32'h8b4) +`define PV_REG_PCR_ENTRY_14_6 (32'h8b8) +`define PV_REG_PCR_ENTRY_14_7 (32'h8bc) +`define PV_REG_PCR_ENTRY_14_8 (32'h8c0) +`define PV_REG_PCR_ENTRY_14_9 (32'h8c4) +`define PV_REG_PCR_ENTRY_14_10 (32'h8c8) +`define PV_REG_PCR_ENTRY_14_11 (32'h8cc) +`define PV_REG_PCR_ENTRY_15_0 (32'h8d0) +`define PV_REG_PCR_ENTRY_15_1 (32'h8d4) +`define PV_REG_PCR_ENTRY_15_2 (32'h8d8) +`define PV_REG_PCR_ENTRY_15_3 (32'h8dc) +`define PV_REG_PCR_ENTRY_15_4 (32'h8e0) +`define PV_REG_PCR_ENTRY_15_5 (32'h8e4) +`define PV_REG_PCR_ENTRY_15_6 (32'h8e8) +`define PV_REG_PCR_ENTRY_15_7 (32'h8ec) +`define PV_REG_PCR_ENTRY_15_8 (32'h8f0) +`define PV_REG_PCR_ENTRY_15_9 (32'h8f4) +`define PV_REG_PCR_ENTRY_15_10 (32'h8f8) +`define PV_REG_PCR_ENTRY_15_11 (32'h8fc) +`define PV_REG_PCR_ENTRY_16_0 (32'h900) +`define PV_REG_PCR_ENTRY_16_1 (32'h904) +`define PV_REG_PCR_ENTRY_16_2 (32'h908) +`define PV_REG_PCR_ENTRY_16_3 (32'h90c) +`define PV_REG_PCR_ENTRY_16_4 (32'h910) +`define PV_REG_PCR_ENTRY_16_5 (32'h914) +`define PV_REG_PCR_ENTRY_16_6 (32'h918) +`define PV_REG_PCR_ENTRY_16_7 (32'h91c) +`define PV_REG_PCR_ENTRY_16_8 (32'h920) +`define PV_REG_PCR_ENTRY_16_9 (32'h924) +`define PV_REG_PCR_ENTRY_16_10 (32'h928) +`define PV_REG_PCR_ENTRY_16_11 (32'h92c) +`define PV_REG_PCR_ENTRY_17_0 (32'h930) +`define PV_REG_PCR_ENTRY_17_1 (32'h934) +`define PV_REG_PCR_ENTRY_17_2 (32'h938) +`define PV_REG_PCR_ENTRY_17_3 (32'h93c) +`define PV_REG_PCR_ENTRY_17_4 (32'h940) +`define PV_REG_PCR_ENTRY_17_5 (32'h944) +`define PV_REG_PCR_ENTRY_17_6 (32'h948) +`define PV_REG_PCR_ENTRY_17_7 (32'h94c) +`define PV_REG_PCR_ENTRY_17_8 (32'h950) +`define PV_REG_PCR_ENTRY_17_9 (32'h954) +`define PV_REG_PCR_ENTRY_17_10 (32'h958) +`define PV_REG_PCR_ENTRY_17_11 (32'h95c) +`define PV_REG_PCR_ENTRY_18_0 (32'h960) +`define PV_REG_PCR_ENTRY_18_1 (32'h964) +`define PV_REG_PCR_ENTRY_18_2 (32'h968) +`define PV_REG_PCR_ENTRY_18_3 (32'h96c) +`define PV_REG_PCR_ENTRY_18_4 (32'h970) +`define PV_REG_PCR_ENTRY_18_5 (32'h974) +`define PV_REG_PCR_ENTRY_18_6 (32'h978) +`define PV_REG_PCR_ENTRY_18_7 (32'h97c) +`define PV_REG_PCR_ENTRY_18_8 (32'h980) +`define PV_REG_PCR_ENTRY_18_9 (32'h984) +`define PV_REG_PCR_ENTRY_18_10 (32'h988) +`define PV_REG_PCR_ENTRY_18_11 (32'h98c) +`define PV_REG_PCR_ENTRY_19_0 (32'h990) +`define PV_REG_PCR_ENTRY_19_1 (32'h994) +`define PV_REG_PCR_ENTRY_19_2 (32'h998) +`define PV_REG_PCR_ENTRY_19_3 (32'h99c) +`define PV_REG_PCR_ENTRY_19_4 (32'h9a0) +`define PV_REG_PCR_ENTRY_19_5 (32'h9a4) +`define PV_REG_PCR_ENTRY_19_6 (32'h9a8) +`define PV_REG_PCR_ENTRY_19_7 (32'h9ac) +`define PV_REG_PCR_ENTRY_19_8 (32'h9b0) +`define PV_REG_PCR_ENTRY_19_9 (32'h9b4) +`define PV_REG_PCR_ENTRY_19_10 (32'h9b8) +`define PV_REG_PCR_ENTRY_19_11 (32'h9bc) +`define PV_REG_PCR_ENTRY_20_0 (32'h9c0) +`define PV_REG_PCR_ENTRY_20_1 (32'h9c4) +`define PV_REG_PCR_ENTRY_20_2 (32'h9c8) +`define PV_REG_PCR_ENTRY_20_3 (32'h9cc) +`define PV_REG_PCR_ENTRY_20_4 (32'h9d0) +`define PV_REG_PCR_ENTRY_20_5 (32'h9d4) +`define PV_REG_PCR_ENTRY_20_6 (32'h9d8) +`define PV_REG_PCR_ENTRY_20_7 (32'h9dc) +`define PV_REG_PCR_ENTRY_20_8 (32'h9e0) +`define PV_REG_PCR_ENTRY_20_9 (32'h9e4) +`define PV_REG_PCR_ENTRY_20_10 (32'h9e8) +`define PV_REG_PCR_ENTRY_20_11 (32'h9ec) +`define PV_REG_PCR_ENTRY_21_0 (32'h9f0) +`define PV_REG_PCR_ENTRY_21_1 (32'h9f4) +`define PV_REG_PCR_ENTRY_21_2 (32'h9f8) +`define PV_REG_PCR_ENTRY_21_3 (32'h9fc) +`define PV_REG_PCR_ENTRY_21_4 (32'ha00) +`define PV_REG_PCR_ENTRY_21_5 (32'ha04) +`define PV_REG_PCR_ENTRY_21_6 (32'ha08) +`define PV_REG_PCR_ENTRY_21_7 (32'ha0c) +`define PV_REG_PCR_ENTRY_21_8 (32'ha10) +`define PV_REG_PCR_ENTRY_21_9 (32'ha14) +`define PV_REG_PCR_ENTRY_21_10 (32'ha18) +`define PV_REG_PCR_ENTRY_21_11 (32'ha1c) +`define PV_REG_PCR_ENTRY_22_0 (32'ha20) +`define PV_REG_PCR_ENTRY_22_1 (32'ha24) +`define PV_REG_PCR_ENTRY_22_2 (32'ha28) +`define PV_REG_PCR_ENTRY_22_3 (32'ha2c) +`define PV_REG_PCR_ENTRY_22_4 (32'ha30) +`define PV_REG_PCR_ENTRY_22_5 (32'ha34) +`define PV_REG_PCR_ENTRY_22_6 (32'ha38) +`define PV_REG_PCR_ENTRY_22_7 (32'ha3c) +`define PV_REG_PCR_ENTRY_22_8 (32'ha40) +`define PV_REG_PCR_ENTRY_22_9 (32'ha44) +`define PV_REG_PCR_ENTRY_22_10 (32'ha48) +`define PV_REG_PCR_ENTRY_22_11 (32'ha4c) +`define PV_REG_PCR_ENTRY_23_0 (32'ha50) +`define PV_REG_PCR_ENTRY_23_1 (32'ha54) +`define PV_REG_PCR_ENTRY_23_2 (32'ha58) +`define PV_REG_PCR_ENTRY_23_3 (32'ha5c) +`define PV_REG_PCR_ENTRY_23_4 (32'ha60) +`define PV_REG_PCR_ENTRY_23_5 (32'ha64) +`define PV_REG_PCR_ENTRY_23_6 (32'ha68) +`define PV_REG_PCR_ENTRY_23_7 (32'ha6c) +`define PV_REG_PCR_ENTRY_23_8 (32'ha70) +`define PV_REG_PCR_ENTRY_23_9 (32'ha74) +`define PV_REG_PCR_ENTRY_23_10 (32'ha78) +`define PV_REG_PCR_ENTRY_23_11 (32'ha7c) +`define PV_REG_PCR_ENTRY_24_0 (32'ha80) +`define PV_REG_PCR_ENTRY_24_1 (32'ha84) +`define PV_REG_PCR_ENTRY_24_2 (32'ha88) +`define PV_REG_PCR_ENTRY_24_3 (32'ha8c) +`define PV_REG_PCR_ENTRY_24_4 (32'ha90) +`define PV_REG_PCR_ENTRY_24_5 (32'ha94) +`define PV_REG_PCR_ENTRY_24_6 (32'ha98) +`define PV_REG_PCR_ENTRY_24_7 (32'ha9c) +`define PV_REG_PCR_ENTRY_24_8 (32'haa0) +`define PV_REG_PCR_ENTRY_24_9 (32'haa4) +`define PV_REG_PCR_ENTRY_24_10 (32'haa8) +`define PV_REG_PCR_ENTRY_24_11 (32'haac) +`define PV_REG_PCR_ENTRY_25_0 (32'hab0) +`define PV_REG_PCR_ENTRY_25_1 (32'hab4) +`define PV_REG_PCR_ENTRY_25_2 (32'hab8) +`define PV_REG_PCR_ENTRY_25_3 (32'habc) +`define PV_REG_PCR_ENTRY_25_4 (32'hac0) +`define PV_REG_PCR_ENTRY_25_5 (32'hac4) +`define PV_REG_PCR_ENTRY_25_6 (32'hac8) +`define PV_REG_PCR_ENTRY_25_7 (32'hacc) +`define PV_REG_PCR_ENTRY_25_8 (32'had0) +`define PV_REG_PCR_ENTRY_25_9 (32'had4) +`define PV_REG_PCR_ENTRY_25_10 (32'had8) +`define PV_REG_PCR_ENTRY_25_11 (32'hadc) +`define PV_REG_PCR_ENTRY_26_0 (32'hae0) +`define PV_REG_PCR_ENTRY_26_1 (32'hae4) +`define PV_REG_PCR_ENTRY_26_2 (32'hae8) +`define PV_REG_PCR_ENTRY_26_3 (32'haec) +`define PV_REG_PCR_ENTRY_26_4 (32'haf0) +`define PV_REG_PCR_ENTRY_26_5 (32'haf4) +`define PV_REG_PCR_ENTRY_26_6 (32'haf8) +`define PV_REG_PCR_ENTRY_26_7 (32'hafc) +`define PV_REG_PCR_ENTRY_26_8 (32'hb00) +`define PV_REG_PCR_ENTRY_26_9 (32'hb04) +`define PV_REG_PCR_ENTRY_26_10 (32'hb08) +`define PV_REG_PCR_ENTRY_26_11 (32'hb0c) +`define PV_REG_PCR_ENTRY_27_0 (32'hb10) +`define PV_REG_PCR_ENTRY_27_1 (32'hb14) +`define PV_REG_PCR_ENTRY_27_2 (32'hb18) +`define PV_REG_PCR_ENTRY_27_3 (32'hb1c) +`define PV_REG_PCR_ENTRY_27_4 (32'hb20) +`define PV_REG_PCR_ENTRY_27_5 (32'hb24) +`define PV_REG_PCR_ENTRY_27_6 (32'hb28) +`define PV_REG_PCR_ENTRY_27_7 (32'hb2c) +`define PV_REG_PCR_ENTRY_27_8 (32'hb30) +`define PV_REG_PCR_ENTRY_27_9 (32'hb34) +`define PV_REG_PCR_ENTRY_27_10 (32'hb38) +`define PV_REG_PCR_ENTRY_27_11 (32'hb3c) +`define PV_REG_PCR_ENTRY_28_0 (32'hb40) +`define PV_REG_PCR_ENTRY_28_1 (32'hb44) +`define PV_REG_PCR_ENTRY_28_2 (32'hb48) +`define PV_REG_PCR_ENTRY_28_3 (32'hb4c) +`define PV_REG_PCR_ENTRY_28_4 (32'hb50) +`define PV_REG_PCR_ENTRY_28_5 (32'hb54) +`define PV_REG_PCR_ENTRY_28_6 (32'hb58) +`define PV_REG_PCR_ENTRY_28_7 (32'hb5c) +`define PV_REG_PCR_ENTRY_28_8 (32'hb60) +`define PV_REG_PCR_ENTRY_28_9 (32'hb64) +`define PV_REG_PCR_ENTRY_28_10 (32'hb68) +`define PV_REG_PCR_ENTRY_28_11 (32'hb6c) +`define PV_REG_PCR_ENTRY_29_0 (32'hb70) +`define PV_REG_PCR_ENTRY_29_1 (32'hb74) +`define PV_REG_PCR_ENTRY_29_2 (32'hb78) +`define PV_REG_PCR_ENTRY_29_3 (32'hb7c) +`define PV_REG_PCR_ENTRY_29_4 (32'hb80) +`define PV_REG_PCR_ENTRY_29_5 (32'hb84) +`define PV_REG_PCR_ENTRY_29_6 (32'hb88) +`define PV_REG_PCR_ENTRY_29_7 (32'hb8c) +`define PV_REG_PCR_ENTRY_29_8 (32'hb90) +`define PV_REG_PCR_ENTRY_29_9 (32'hb94) +`define PV_REG_PCR_ENTRY_29_10 (32'hb98) +`define PV_REG_PCR_ENTRY_29_11 (32'hb9c) +`define PV_REG_PCR_ENTRY_30_0 (32'hba0) +`define PV_REG_PCR_ENTRY_30_1 (32'hba4) +`define PV_REG_PCR_ENTRY_30_2 (32'hba8) +`define PV_REG_PCR_ENTRY_30_3 (32'hbac) +`define PV_REG_PCR_ENTRY_30_4 (32'hbb0) +`define PV_REG_PCR_ENTRY_30_5 (32'hbb4) +`define PV_REG_PCR_ENTRY_30_6 (32'hbb8) +`define PV_REG_PCR_ENTRY_30_7 (32'hbbc) +`define PV_REG_PCR_ENTRY_30_8 (32'hbc0) +`define PV_REG_PCR_ENTRY_30_9 (32'hbc4) +`define PV_REG_PCR_ENTRY_30_10 (32'hbc8) +`define PV_REG_PCR_ENTRY_30_11 (32'hbcc) +`define PV_REG_PCR_ENTRY_31_0 (32'hbd0) +`define PV_REG_PCR_ENTRY_31_1 (32'hbd4) +`define PV_REG_PCR_ENTRY_31_2 (32'hbd8) +`define PV_REG_PCR_ENTRY_31_3 (32'hbdc) +`define PV_REG_PCR_ENTRY_31_4 (32'hbe0) +`define PV_REG_PCR_ENTRY_31_5 (32'hbe4) +`define PV_REG_PCR_ENTRY_31_6 (32'hbe8) +`define PV_REG_PCR_ENTRY_31_7 (32'hbec) +`define PV_REG_PCR_ENTRY_31_8 (32'hbf0) +`define PV_REG_PCR_ENTRY_31_9 (32'hbf4) +`define PV_REG_PCR_ENTRY_31_10 (32'hbf8) +`define PV_REG_PCR_ENTRY_31_11 (32'hbfc) +`define DV_REG_STICKYDATAVAULTCTRL_0 (32'h0) +`define DV_REG_STICKYDATAVAULTCTRL_0_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_0_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_1 (32'h4) +`define DV_REG_STICKYDATAVAULTCTRL_1_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_1_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_2 (32'h8) +`define DV_REG_STICKYDATAVAULTCTRL_2_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_2_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_3 (32'hc) +`define DV_REG_STICKYDATAVAULTCTRL_3_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_3_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_4 (32'h10) +`define DV_REG_STICKYDATAVAULTCTRL_4_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_4_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_5 (32'h14) +`define DV_REG_STICKYDATAVAULTCTRL_5_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_5_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_6 (32'h18) +`define DV_REG_STICKYDATAVAULTCTRL_6_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_6_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_7 (32'h1c) +`define DV_REG_STICKYDATAVAULTCTRL_7_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_7_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_8 (32'h20) +`define DV_REG_STICKYDATAVAULTCTRL_8_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_8_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYDATAVAULTCTRL_9 (32'h24) +`define DV_REG_STICKYDATAVAULTCTRL_9_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYDATAVAULTCTRL_9_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_0 (32'h28) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_1 (32'h2c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_2 (32'h30) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_3 (32'h34) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_4 (32'h38) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_5 (32'h3c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_6 (32'h40) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_7 (32'h44) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_8 (32'h48) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_9 (32'h4c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_10 (32'h50) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_0_11 (32'h54) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_0 (32'h58) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_1 (32'h5c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_2 (32'h60) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_3 (32'h64) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_4 (32'h68) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_5 (32'h6c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_6 (32'h70) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_7 (32'h74) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_8 (32'h78) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_9 (32'h7c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_10 (32'h80) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_1_11 (32'h84) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_0 (32'h88) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_1 (32'h8c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_2 (32'h90) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_3 (32'h94) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_4 (32'h98) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_5 (32'h9c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_6 (32'ha0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_7 (32'ha4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_8 (32'ha8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_9 (32'hac) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_10 (32'hb0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_2_11 (32'hb4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_0 (32'hb8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_1 (32'hbc) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_2 (32'hc0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_3 (32'hc4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_4 (32'hc8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_5 (32'hcc) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_6 (32'hd0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_7 (32'hd4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_8 (32'hd8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_9 (32'hdc) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_10 (32'he0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_3_11 (32'he4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_0 (32'he8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_1 (32'hec) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_2 (32'hf0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_3 (32'hf4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_4 (32'hf8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_5 (32'hfc) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_6 (32'h100) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_7 (32'h104) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_8 (32'h108) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_9 (32'h10c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_10 (32'h110) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_4_11 (32'h114) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_0 (32'h118) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_1 (32'h11c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_2 (32'h120) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_3 (32'h124) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_4 (32'h128) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_5 (32'h12c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_6 (32'h130) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_7 (32'h134) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_8 (32'h138) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_9 (32'h13c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_10 (32'h140) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_5_11 (32'h144) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_0 (32'h148) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_1 (32'h14c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_2 (32'h150) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_3 (32'h154) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_4 (32'h158) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_5 (32'h15c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_6 (32'h160) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_7 (32'h164) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_8 (32'h168) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_9 (32'h16c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_10 (32'h170) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_6_11 (32'h174) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_0 (32'h178) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_1 (32'h17c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_2 (32'h180) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_3 (32'h184) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_4 (32'h188) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_5 (32'h18c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_6 (32'h190) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_7 (32'h194) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_8 (32'h198) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_9 (32'h19c) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_10 (32'h1a0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_7_11 (32'h1a4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_0 (32'h1a8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_1 (32'h1ac) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_2 (32'h1b0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_3 (32'h1b4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_4 (32'h1b8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_5 (32'h1bc) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_6 (32'h1c0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_7 (32'h1c4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_8 (32'h1c8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_9 (32'h1cc) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_10 (32'h1d0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_8_11 (32'h1d4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_0 (32'h1d8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_1 (32'h1dc) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_2 (32'h1e0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_3 (32'h1e4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_4 (32'h1e8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_5 (32'h1ec) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_6 (32'h1f0) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_7 (32'h1f4) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_8 (32'h1f8) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_9 (32'h1fc) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_10 (32'h200) +`define DV_REG_STICKY_DATA_VAULT_ENTRY_9_11 (32'h204) +`define DV_REG_DATAVAULTCTRL_0 (32'h208) +`define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_1 (32'h20c) +`define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_2 (32'h210) +`define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_3 (32'h214) +`define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_4 (32'h218) +`define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_5 (32'h21c) +`define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_6 (32'h220) +`define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_7 (32'h224) +`define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_8 (32'h228) +`define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATAVAULTCTRL_9 (32'h22c) +`define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_LOW (0) +`define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_DATA_VAULT_ENTRY_0_0 (32'h230) +`define DV_REG_DATA_VAULT_ENTRY_0_1 (32'h234) +`define DV_REG_DATA_VAULT_ENTRY_0_2 (32'h238) +`define DV_REG_DATA_VAULT_ENTRY_0_3 (32'h23c) +`define DV_REG_DATA_VAULT_ENTRY_0_4 (32'h240) +`define DV_REG_DATA_VAULT_ENTRY_0_5 (32'h244) +`define DV_REG_DATA_VAULT_ENTRY_0_6 (32'h248) +`define DV_REG_DATA_VAULT_ENTRY_0_7 (32'h24c) +`define DV_REG_DATA_VAULT_ENTRY_0_8 (32'h250) +`define DV_REG_DATA_VAULT_ENTRY_0_9 (32'h254) +`define DV_REG_DATA_VAULT_ENTRY_0_10 (32'h258) +`define DV_REG_DATA_VAULT_ENTRY_0_11 (32'h25c) +`define DV_REG_DATA_VAULT_ENTRY_1_0 (32'h260) +`define DV_REG_DATA_VAULT_ENTRY_1_1 (32'h264) +`define DV_REG_DATA_VAULT_ENTRY_1_2 (32'h268) +`define DV_REG_DATA_VAULT_ENTRY_1_3 (32'h26c) +`define DV_REG_DATA_VAULT_ENTRY_1_4 (32'h270) +`define DV_REG_DATA_VAULT_ENTRY_1_5 (32'h274) +`define DV_REG_DATA_VAULT_ENTRY_1_6 (32'h278) +`define DV_REG_DATA_VAULT_ENTRY_1_7 (32'h27c) +`define DV_REG_DATA_VAULT_ENTRY_1_8 (32'h280) +`define DV_REG_DATA_VAULT_ENTRY_1_9 (32'h284) +`define DV_REG_DATA_VAULT_ENTRY_1_10 (32'h288) +`define DV_REG_DATA_VAULT_ENTRY_1_11 (32'h28c) +`define DV_REG_DATA_VAULT_ENTRY_2_0 (32'h290) +`define DV_REG_DATA_VAULT_ENTRY_2_1 (32'h294) +`define DV_REG_DATA_VAULT_ENTRY_2_2 (32'h298) +`define DV_REG_DATA_VAULT_ENTRY_2_3 (32'h29c) +`define DV_REG_DATA_VAULT_ENTRY_2_4 (32'h2a0) +`define DV_REG_DATA_VAULT_ENTRY_2_5 (32'h2a4) +`define DV_REG_DATA_VAULT_ENTRY_2_6 (32'h2a8) +`define DV_REG_DATA_VAULT_ENTRY_2_7 (32'h2ac) +`define DV_REG_DATA_VAULT_ENTRY_2_8 (32'h2b0) +`define DV_REG_DATA_VAULT_ENTRY_2_9 (32'h2b4) +`define DV_REG_DATA_VAULT_ENTRY_2_10 (32'h2b8) +`define DV_REG_DATA_VAULT_ENTRY_2_11 (32'h2bc) +`define DV_REG_DATA_VAULT_ENTRY_3_0 (32'h2c0) +`define DV_REG_DATA_VAULT_ENTRY_3_1 (32'h2c4) +`define DV_REG_DATA_VAULT_ENTRY_3_2 (32'h2c8) +`define DV_REG_DATA_VAULT_ENTRY_3_3 (32'h2cc) +`define DV_REG_DATA_VAULT_ENTRY_3_4 (32'h2d0) +`define DV_REG_DATA_VAULT_ENTRY_3_5 (32'h2d4) +`define DV_REG_DATA_VAULT_ENTRY_3_6 (32'h2d8) +`define DV_REG_DATA_VAULT_ENTRY_3_7 (32'h2dc) +`define DV_REG_DATA_VAULT_ENTRY_3_8 (32'h2e0) +`define DV_REG_DATA_VAULT_ENTRY_3_9 (32'h2e4) +`define DV_REG_DATA_VAULT_ENTRY_3_10 (32'h2e8) +`define DV_REG_DATA_VAULT_ENTRY_3_11 (32'h2ec) +`define DV_REG_DATA_VAULT_ENTRY_4_0 (32'h2f0) +`define DV_REG_DATA_VAULT_ENTRY_4_1 (32'h2f4) +`define DV_REG_DATA_VAULT_ENTRY_4_2 (32'h2f8) +`define DV_REG_DATA_VAULT_ENTRY_4_3 (32'h2fc) +`define DV_REG_DATA_VAULT_ENTRY_4_4 (32'h300) +`define DV_REG_DATA_VAULT_ENTRY_4_5 (32'h304) +`define DV_REG_DATA_VAULT_ENTRY_4_6 (32'h308) +`define DV_REG_DATA_VAULT_ENTRY_4_7 (32'h30c) +`define DV_REG_DATA_VAULT_ENTRY_4_8 (32'h310) +`define DV_REG_DATA_VAULT_ENTRY_4_9 (32'h314) +`define DV_REG_DATA_VAULT_ENTRY_4_10 (32'h318) +`define DV_REG_DATA_VAULT_ENTRY_4_11 (32'h31c) +`define DV_REG_DATA_VAULT_ENTRY_5_0 (32'h320) +`define DV_REG_DATA_VAULT_ENTRY_5_1 (32'h324) +`define DV_REG_DATA_VAULT_ENTRY_5_2 (32'h328) +`define DV_REG_DATA_VAULT_ENTRY_5_3 (32'h32c) +`define DV_REG_DATA_VAULT_ENTRY_5_4 (32'h330) +`define DV_REG_DATA_VAULT_ENTRY_5_5 (32'h334) +`define DV_REG_DATA_VAULT_ENTRY_5_6 (32'h338) +`define DV_REG_DATA_VAULT_ENTRY_5_7 (32'h33c) +`define DV_REG_DATA_VAULT_ENTRY_5_8 (32'h340) +`define DV_REG_DATA_VAULT_ENTRY_5_9 (32'h344) +`define DV_REG_DATA_VAULT_ENTRY_5_10 (32'h348) +`define DV_REG_DATA_VAULT_ENTRY_5_11 (32'h34c) +`define DV_REG_DATA_VAULT_ENTRY_6_0 (32'h350) +`define DV_REG_DATA_VAULT_ENTRY_6_1 (32'h354) +`define DV_REG_DATA_VAULT_ENTRY_6_2 (32'h358) +`define DV_REG_DATA_VAULT_ENTRY_6_3 (32'h35c) +`define DV_REG_DATA_VAULT_ENTRY_6_4 (32'h360) +`define DV_REG_DATA_VAULT_ENTRY_6_5 (32'h364) +`define DV_REG_DATA_VAULT_ENTRY_6_6 (32'h368) +`define DV_REG_DATA_VAULT_ENTRY_6_7 (32'h36c) +`define DV_REG_DATA_VAULT_ENTRY_6_8 (32'h370) +`define DV_REG_DATA_VAULT_ENTRY_6_9 (32'h374) +`define DV_REG_DATA_VAULT_ENTRY_6_10 (32'h378) +`define DV_REG_DATA_VAULT_ENTRY_6_11 (32'h37c) +`define DV_REG_DATA_VAULT_ENTRY_7_0 (32'h380) +`define DV_REG_DATA_VAULT_ENTRY_7_1 (32'h384) +`define DV_REG_DATA_VAULT_ENTRY_7_2 (32'h388) +`define DV_REG_DATA_VAULT_ENTRY_7_3 (32'h38c) +`define DV_REG_DATA_VAULT_ENTRY_7_4 (32'h390) +`define DV_REG_DATA_VAULT_ENTRY_7_5 (32'h394) +`define DV_REG_DATA_VAULT_ENTRY_7_6 (32'h398) +`define DV_REG_DATA_VAULT_ENTRY_7_7 (32'h39c) +`define DV_REG_DATA_VAULT_ENTRY_7_8 (32'h3a0) +`define DV_REG_DATA_VAULT_ENTRY_7_9 (32'h3a4) +`define DV_REG_DATA_VAULT_ENTRY_7_10 (32'h3a8) +`define DV_REG_DATA_VAULT_ENTRY_7_11 (32'h3ac) +`define DV_REG_DATA_VAULT_ENTRY_8_0 (32'h3b0) +`define DV_REG_DATA_VAULT_ENTRY_8_1 (32'h3b4) +`define DV_REG_DATA_VAULT_ENTRY_8_2 (32'h3b8) +`define DV_REG_DATA_VAULT_ENTRY_8_3 (32'h3bc) +`define DV_REG_DATA_VAULT_ENTRY_8_4 (32'h3c0) +`define DV_REG_DATA_VAULT_ENTRY_8_5 (32'h3c4) +`define DV_REG_DATA_VAULT_ENTRY_8_6 (32'h3c8) +`define DV_REG_DATA_VAULT_ENTRY_8_7 (32'h3cc) +`define DV_REG_DATA_VAULT_ENTRY_8_8 (32'h3d0) +`define DV_REG_DATA_VAULT_ENTRY_8_9 (32'h3d4) +`define DV_REG_DATA_VAULT_ENTRY_8_10 (32'h3d8) +`define DV_REG_DATA_VAULT_ENTRY_8_11 (32'h3dc) +`define DV_REG_DATA_VAULT_ENTRY_9_0 (32'h3e0) +`define DV_REG_DATA_VAULT_ENTRY_9_1 (32'h3e4) +`define DV_REG_DATA_VAULT_ENTRY_9_2 (32'h3e8) +`define DV_REG_DATA_VAULT_ENTRY_9_3 (32'h3ec) +`define DV_REG_DATA_VAULT_ENTRY_9_4 (32'h3f0) +`define DV_REG_DATA_VAULT_ENTRY_9_5 (32'h3f4) +`define DV_REG_DATA_VAULT_ENTRY_9_6 (32'h3f8) +`define DV_REG_DATA_VAULT_ENTRY_9_7 (32'h3fc) +`define DV_REG_DATA_VAULT_ENTRY_9_8 (32'h400) +`define DV_REG_DATA_VAULT_ENTRY_9_9 (32'h404) +`define DV_REG_DATA_VAULT_ENTRY_9_10 (32'h408) +`define DV_REG_DATA_VAULT_ENTRY_9_11 (32'h40c) +`define DV_REG_LOCKABLESCRATCHREGCTRL_0 (32'h410) +`define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_1 (32'h414) +`define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_2 (32'h418) +`define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_3 (32'h41c) +`define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_4 (32'h420) +`define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_5 (32'h424) +`define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_6 (32'h428) +`define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_7 (32'h42c) +`define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_8 (32'h430) +`define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREGCTRL_9 (32'h434) +`define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_LOW (0) +`define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_LOCKABLESCRATCHREG_0 (32'h438) +`define DV_REG_LOCKABLESCRATCHREG_1 (32'h43c) +`define DV_REG_LOCKABLESCRATCHREG_2 (32'h440) +`define DV_REG_LOCKABLESCRATCHREG_3 (32'h444) +`define DV_REG_LOCKABLESCRATCHREG_4 (32'h448) +`define DV_REG_LOCKABLESCRATCHREG_5 (32'h44c) +`define DV_REG_LOCKABLESCRATCHREG_6 (32'h450) +`define DV_REG_LOCKABLESCRATCHREG_7 (32'h454) +`define DV_REG_LOCKABLESCRATCHREG_8 (32'h458) +`define DV_REG_LOCKABLESCRATCHREG_9 (32'h45c) +`define DV_REG_NONSTICKYGENERICSCRATCHREG_0 (32'h460) +`define DV_REG_NONSTICKYGENERICSCRATCHREG_1 (32'h464) +`define DV_REG_NONSTICKYGENERICSCRATCHREG_2 (32'h468) +`define DV_REG_NONSTICKYGENERICSCRATCHREG_3 (32'h46c) +`define DV_REG_NONSTICKYGENERICSCRATCHREG_4 (32'h470) +`define DV_REG_NONSTICKYGENERICSCRATCHREG_5 (32'h474) +`define DV_REG_NONSTICKYGENERICSCRATCHREG_6 (32'h478) +`define DV_REG_NONSTICKYGENERICSCRATCHREG_7 (32'h47c) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0 (32'h480) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1 (32'h484) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2 (32'h488) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3 (32'h48c) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4 (32'h490) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5 (32'h494) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6 (32'h498) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7 (32'h49c) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW (0) +`define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK (32'h1) +`define DV_REG_STICKYLOCKABLESCRATCHREG_0 (32'h4a0) +`define DV_REG_STICKYLOCKABLESCRATCHREG_1 (32'h4a4) +`define DV_REG_STICKYLOCKABLESCRATCHREG_2 (32'h4a8) +`define DV_REG_STICKYLOCKABLESCRATCHREG_3 (32'h4ac) +`define DV_REG_STICKYLOCKABLESCRATCHREG_4 (32'h4b0) +`define DV_REG_STICKYLOCKABLESCRATCHREG_5 (32'h4b4) +`define DV_REG_STICKYLOCKABLESCRATCHREG_6 (32'h4b8) +`define DV_REG_STICKYLOCKABLESCRATCHREG_7 (32'h4bc) +`define SHA512_REG_SHA512_NAME_0 (32'h0) +`define SHA512_REG_SHA512_NAME_1 (32'h4) +`define SHA512_REG_SHA512_VERSION_0 (32'h8) +`define SHA512_REG_SHA512_VERSION_1 (32'hc) +`define SHA512_REG_SHA512_CTRL (32'h10) +`define SHA512_REG_SHA512_CTRL_INIT_LOW (0) +`define SHA512_REG_SHA512_CTRL_INIT_MASK (32'h1) +`define SHA512_REG_SHA512_CTRL_NEXT_LOW (1) +`define SHA512_REG_SHA512_CTRL_NEXT_MASK (32'h2) +`define SHA512_REG_SHA512_CTRL_MODE_LOW (2) +`define SHA512_REG_SHA512_CTRL_MODE_MASK (32'hc) +`define SHA512_REG_SHA512_CTRL_ZEROIZE_LOW (4) +`define SHA512_REG_SHA512_CTRL_ZEROIZE_MASK (32'h10) +`define SHA512_REG_SHA512_CTRL_LAST_LOW (5) +`define SHA512_REG_SHA512_CTRL_LAST_MASK (32'h20) +`define SHA512_REG_SHA512_CTRL_RESTORE_LOW (6) +`define SHA512_REG_SHA512_CTRL_RESTORE_MASK (32'h40) +`define SHA512_REG_SHA512_STATUS (32'h18) +`define SHA512_REG_SHA512_STATUS_READY_LOW (0) +`define SHA512_REG_SHA512_STATUS_READY_MASK (32'h1) +`define SHA512_REG_SHA512_STATUS_VALID_LOW (1) +`define SHA512_REG_SHA512_STATUS_VALID_MASK (32'h2) +`define SHA512_REG_SHA512_BLOCK_0 (32'h80) +`define SHA512_REG_SHA512_BLOCK_1 (32'h84) +`define SHA512_REG_SHA512_BLOCK_2 (32'h88) +`define SHA512_REG_SHA512_BLOCK_3 (32'h8c) +`define SHA512_REG_SHA512_BLOCK_4 (32'h90) +`define SHA512_REG_SHA512_BLOCK_5 (32'h94) +`define SHA512_REG_SHA512_BLOCK_6 (32'h98) +`define SHA512_REG_SHA512_BLOCK_7 (32'h9c) +`define SHA512_REG_SHA512_BLOCK_8 (32'ha0) +`define SHA512_REG_SHA512_BLOCK_9 (32'ha4) +`define SHA512_REG_SHA512_BLOCK_10 (32'ha8) +`define SHA512_REG_SHA512_BLOCK_11 (32'hac) +`define SHA512_REG_SHA512_BLOCK_12 (32'hb0) +`define SHA512_REG_SHA512_BLOCK_13 (32'hb4) +`define SHA512_REG_SHA512_BLOCK_14 (32'hb8) +`define SHA512_REG_SHA512_BLOCK_15 (32'hbc) +`define SHA512_REG_SHA512_BLOCK_16 (32'hc0) +`define SHA512_REG_SHA512_BLOCK_17 (32'hc4) +`define SHA512_REG_SHA512_BLOCK_18 (32'hc8) +`define SHA512_REG_SHA512_BLOCK_19 (32'hcc) +`define SHA512_REG_SHA512_BLOCK_20 (32'hd0) +`define SHA512_REG_SHA512_BLOCK_21 (32'hd4) +`define SHA512_REG_SHA512_BLOCK_22 (32'hd8) +`define SHA512_REG_SHA512_BLOCK_23 (32'hdc) +`define SHA512_REG_SHA512_BLOCK_24 (32'he0) +`define SHA512_REG_SHA512_BLOCK_25 (32'he4) +`define SHA512_REG_SHA512_BLOCK_26 (32'he8) +`define SHA512_REG_SHA512_BLOCK_27 (32'hec) +`define SHA512_REG_SHA512_BLOCK_28 (32'hf0) +`define SHA512_REG_SHA512_BLOCK_29 (32'hf4) +`define SHA512_REG_SHA512_BLOCK_30 (32'hf8) +`define SHA512_REG_SHA512_BLOCK_31 (32'hfc) +`define SHA512_REG_SHA512_DIGEST_0 (32'h100) +`define SHA512_REG_SHA512_DIGEST_1 (32'h104) +`define SHA512_REG_SHA512_DIGEST_2 (32'h108) +`define SHA512_REG_SHA512_DIGEST_3 (32'h10c) +`define SHA512_REG_SHA512_DIGEST_4 (32'h110) +`define SHA512_REG_SHA512_DIGEST_5 (32'h114) +`define SHA512_REG_SHA512_DIGEST_6 (32'h118) +`define SHA512_REG_SHA512_DIGEST_7 (32'h11c) +`define SHA512_REG_SHA512_DIGEST_8 (32'h120) +`define SHA512_REG_SHA512_DIGEST_9 (32'h124) +`define SHA512_REG_SHA512_DIGEST_10 (32'h128) +`define SHA512_REG_SHA512_DIGEST_11 (32'h12c) +`define SHA512_REG_SHA512_DIGEST_12 (32'h130) +`define SHA512_REG_SHA512_DIGEST_13 (32'h134) +`define SHA512_REG_SHA512_DIGEST_14 (32'h138) +`define SHA512_REG_SHA512_DIGEST_15 (32'h13c) +`define SHA512_REG_SHA512_VAULT_RD_CTRL (32'h600) +`define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_EN_LOW (0) +`define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_EN_MASK (32'h1) +`define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_ENTRY_LOW (1) +`define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_ENTRY_MASK (32'h3e) +`define SHA512_REG_SHA512_VAULT_RD_CTRL_PCR_HASH_EXTEND_LOW (6) +`define SHA512_REG_SHA512_VAULT_RD_CTRL_PCR_HASH_EXTEND_MASK (32'h40) +`define SHA512_REG_SHA512_VAULT_RD_CTRL_RSVD_LOW (7) +`define SHA512_REG_SHA512_VAULT_RD_CTRL_RSVD_MASK (32'hffffff80) +`define SHA512_REG_SHA512_VAULT_RD_STATUS (32'h604) +`define SHA512_REG_SHA512_VAULT_RD_STATUS_READY_LOW (0) +`define SHA512_REG_SHA512_VAULT_RD_STATUS_READY_MASK (32'h1) +`define SHA512_REG_SHA512_VAULT_RD_STATUS_VALID_LOW (1) +`define SHA512_REG_SHA512_VAULT_RD_STATUS_VALID_MASK (32'h2) +`define SHA512_REG_SHA512_VAULT_RD_STATUS_ERROR_LOW (2) +`define SHA512_REG_SHA512_VAULT_RD_STATUS_ERROR_MASK (32'h3fc) +`define SHA512_REG_SHA512_KV_WR_CTRL (32'h608) +`define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_EN_LOW (0) +`define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_EN_MASK (32'h1) +`define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_ENTRY_LOW (1) +`define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_ENTRY_MASK (32'h3e) +`define SHA512_REG_SHA512_KV_WR_CTRL_HMAC_KEY_DEST_VALID_LOW (6) +`define SHA512_REG_SHA512_KV_WR_CTRL_HMAC_KEY_DEST_VALID_MASK (32'h40) +`define SHA512_REG_SHA512_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_LOW (7) +`define SHA512_REG_SHA512_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_MASK (32'h80) +`define SHA512_REG_SHA512_KV_WR_CTRL_MLDSA_SEED_DEST_VALID_LOW (8) +`define SHA512_REG_SHA512_KV_WR_CTRL_MLDSA_SEED_DEST_VALID_MASK (32'h100) +`define SHA512_REG_SHA512_KV_WR_CTRL_ECC_PKEY_DEST_VALID_LOW (9) +`define SHA512_REG_SHA512_KV_WR_CTRL_ECC_PKEY_DEST_VALID_MASK (32'h200) +`define SHA512_REG_SHA512_KV_WR_CTRL_ECC_SEED_DEST_VALID_LOW (10) +`define SHA512_REG_SHA512_KV_WR_CTRL_ECC_SEED_DEST_VALID_MASK (32'h400) +`define SHA512_REG_SHA512_KV_WR_CTRL_AES_KEY_DEST_VALID_LOW (11) +`define SHA512_REG_SHA512_KV_WR_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) +`define SHA512_REG_SHA512_KV_WR_CTRL_RSVD_LOW (12) +`define SHA512_REG_SHA512_KV_WR_CTRL_RSVD_MASK (32'hfffff000) +`define SHA512_REG_SHA512_KV_WR_STATUS (32'h60c) +`define SHA512_REG_SHA512_KV_WR_STATUS_READY_LOW (0) +`define SHA512_REG_SHA512_KV_WR_STATUS_READY_MASK (32'h1) +`define SHA512_REG_SHA512_KV_WR_STATUS_VALID_LOW (1) +`define SHA512_REG_SHA512_KV_WR_STATUS_VALID_MASK (32'h2) +`define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_LOW (2) +`define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_MASK (32'h3fc) +`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0 (32'h610) +`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1 (32'h614) +`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2 (32'h618) +`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3 (32'h61c) +`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4 (32'h620) +`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5 (32'h624) +`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6 (32'h628) +`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7 (32'h62c) +`define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL (32'h630) +`define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_LOW (0) +`define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_MASK (32'h1) +`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS (32'h634) +`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_LOW (0) +`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_MASK (32'h1) +`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_LOW (1) +`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_MASK (32'h2) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0 (32'h638) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1 (32'h63c) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2 (32'h640) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3 (32'h644) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4 (32'h648) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5 (32'h64c) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6 (32'h650) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7 (32'h654) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8 (32'h658) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9 (32'h65c) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10 (32'h660) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11 (32'h664) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_12 (32'h668) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_13 (32'h66c) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_14 (32'h670) +`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_15 (32'h674) +`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) +`define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) +`define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) +`define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) +`define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) +`define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA256_REG_SHA256_NAME_0 (32'h0) +`define SHA256_REG_SHA256_NAME_1 (32'h4) +`define SHA256_REG_SHA256_VERSION_0 (32'h8) +`define SHA256_REG_SHA256_VERSION_1 (32'hc) +`define SHA256_REG_SHA256_CTRL (32'h10) +`define SHA256_REG_SHA256_CTRL_INIT_LOW (0) +`define SHA256_REG_SHA256_CTRL_INIT_MASK (32'h1) +`define SHA256_REG_SHA256_CTRL_NEXT_LOW (1) +`define SHA256_REG_SHA256_CTRL_NEXT_MASK (32'h2) +`define SHA256_REG_SHA256_CTRL_MODE_LOW (2) +`define SHA256_REG_SHA256_CTRL_MODE_MASK (32'h4) +`define SHA256_REG_SHA256_CTRL_ZEROIZE_LOW (3) +`define SHA256_REG_SHA256_CTRL_ZEROIZE_MASK (32'h8) +`define SHA256_REG_SHA256_CTRL_WNTZ_MODE_LOW (4) +`define SHA256_REG_SHA256_CTRL_WNTZ_MODE_MASK (32'h10) +`define SHA256_REG_SHA256_CTRL_WNTZ_W_LOW (5) +`define SHA256_REG_SHA256_CTRL_WNTZ_W_MASK (32'h1e0) +`define SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_LOW (9) +`define SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_MASK (32'h200) +`define SHA256_REG_SHA256_STATUS (32'h18) +`define SHA256_REG_SHA256_STATUS_READY_LOW (0) +`define SHA256_REG_SHA256_STATUS_READY_MASK (32'h1) +`define SHA256_REG_SHA256_STATUS_VALID_LOW (1) +`define SHA256_REG_SHA256_STATUS_VALID_MASK (32'h2) +`define SHA256_REG_SHA256_STATUS_WNTZ_BUSY_LOW (2) +`define SHA256_REG_SHA256_STATUS_WNTZ_BUSY_MASK (32'h4) +`define SHA256_REG_SHA256_BLOCK_0 (32'h80) +`define SHA256_REG_SHA256_BLOCK_1 (32'h84) +`define SHA256_REG_SHA256_BLOCK_2 (32'h88) +`define SHA256_REG_SHA256_BLOCK_3 (32'h8c) +`define SHA256_REG_SHA256_BLOCK_4 (32'h90) +`define SHA256_REG_SHA256_BLOCK_5 (32'h94) +`define SHA256_REG_SHA256_BLOCK_6 (32'h98) +`define SHA256_REG_SHA256_BLOCK_7 (32'h9c) +`define SHA256_REG_SHA256_BLOCK_8 (32'ha0) +`define SHA256_REG_SHA256_BLOCK_9 (32'ha4) +`define SHA256_REG_SHA256_BLOCK_10 (32'ha8) +`define SHA256_REG_SHA256_BLOCK_11 (32'hac) +`define SHA256_REG_SHA256_BLOCK_12 (32'hb0) +`define SHA256_REG_SHA256_BLOCK_13 (32'hb4) +`define SHA256_REG_SHA256_BLOCK_14 (32'hb8) +`define SHA256_REG_SHA256_BLOCK_15 (32'hbc) +`define SHA256_REG_SHA256_DIGEST_0 (32'h100) +`define SHA256_REG_SHA256_DIGEST_1 (32'h104) +`define SHA256_REG_SHA256_DIGEST_2 (32'h108) +`define SHA256_REG_SHA256_DIGEST_3 (32'h10c) +`define SHA256_REG_SHA256_DIGEST_4 (32'h110) +`define SHA256_REG_SHA256_DIGEST_5 (32'h114) +`define SHA256_REG_SHA256_DIGEST_6 (32'h118) +`define SHA256_REG_SHA256_DIGEST_7 (32'h11c) +`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) +`define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) +`define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) +`define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) +`define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) +`define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define MLDSA_REG_MLDSA_NAME_0 (32'h0) +`define MLDSA_REG_MLDSA_NAME_1 (32'h4) +`define MLDSA_REG_MLDSA_VERSION_0 (32'h8) +`define MLDSA_REG_MLDSA_VERSION_1 (32'hc) +`define MLDSA_REG_MLDSA_CTRL (32'h10) +`define MLDSA_REG_MLDSA_CTRL_CTRL_LOW (0) +`define MLDSA_REG_MLDSA_CTRL_CTRL_MASK (32'h7) +`define MLDSA_REG_MLDSA_CTRL_ZEROIZE_LOW (3) +`define MLDSA_REG_MLDSA_CTRL_ZEROIZE_MASK (32'h8) +`define MLDSA_REG_MLDSA_CTRL_PCR_SIGN_LOW (4) +`define MLDSA_REG_MLDSA_CTRL_PCR_SIGN_MASK (32'h10) +`define MLDSA_REG_MLDSA_STATUS (32'h14) +`define MLDSA_REG_MLDSA_STATUS_READY_LOW (0) +`define MLDSA_REG_MLDSA_STATUS_READY_MASK (32'h1) +`define MLDSA_REG_MLDSA_STATUS_VALID_LOW (1) +`define MLDSA_REG_MLDSA_STATUS_VALID_MASK (32'h2) +`define MLDSA_REG_MLDSA_ENTROPY_0 (32'h18) +`define MLDSA_REG_MLDSA_ENTROPY_1 (32'h1c) +`define MLDSA_REG_MLDSA_ENTROPY_2 (32'h20) +`define MLDSA_REG_MLDSA_ENTROPY_3 (32'h24) +`define MLDSA_REG_MLDSA_ENTROPY_4 (32'h28) +`define MLDSA_REG_MLDSA_ENTROPY_5 (32'h2c) +`define MLDSA_REG_MLDSA_ENTROPY_6 (32'h30) +`define MLDSA_REG_MLDSA_ENTROPY_7 (32'h34) +`define MLDSA_REG_MLDSA_ENTROPY_8 (32'h38) +`define MLDSA_REG_MLDSA_ENTROPY_9 (32'h3c) +`define MLDSA_REG_MLDSA_ENTROPY_10 (32'h40) +`define MLDSA_REG_MLDSA_ENTROPY_11 (32'h44) +`define MLDSA_REG_MLDSA_ENTROPY_12 (32'h48) +`define MLDSA_REG_MLDSA_ENTROPY_13 (32'h4c) +`define MLDSA_REG_MLDSA_ENTROPY_14 (32'h50) +`define MLDSA_REG_MLDSA_ENTROPY_15 (32'h54) +`define MLDSA_REG_MLDSA_SEED_0 (32'h58) +`define MLDSA_REG_MLDSA_SEED_1 (32'h5c) +`define MLDSA_REG_MLDSA_SEED_2 (32'h60) +`define MLDSA_REG_MLDSA_SEED_3 (32'h64) +`define MLDSA_REG_MLDSA_SEED_4 (32'h68) +`define MLDSA_REG_MLDSA_SEED_5 (32'h6c) +`define MLDSA_REG_MLDSA_SEED_6 (32'h70) +`define MLDSA_REG_MLDSA_SEED_7 (32'h74) +`define MLDSA_REG_MLDSA_SIGN_RND_0 (32'h78) +`define MLDSA_REG_MLDSA_SIGN_RND_1 (32'h7c) +`define MLDSA_REG_MLDSA_SIGN_RND_2 (32'h80) +`define MLDSA_REG_MLDSA_SIGN_RND_3 (32'h84) +`define MLDSA_REG_MLDSA_SIGN_RND_4 (32'h88) +`define MLDSA_REG_MLDSA_SIGN_RND_5 (32'h8c) +`define MLDSA_REG_MLDSA_SIGN_RND_6 (32'h90) +`define MLDSA_REG_MLDSA_SIGN_RND_7 (32'h94) +`define MLDSA_REG_MLDSA_MSG_0 (32'h98) +`define MLDSA_REG_MLDSA_MSG_1 (32'h9c) +`define MLDSA_REG_MLDSA_MSG_2 (32'ha0) +`define MLDSA_REG_MLDSA_MSG_3 (32'ha4) +`define MLDSA_REG_MLDSA_MSG_4 (32'ha8) +`define MLDSA_REG_MLDSA_MSG_5 (32'hac) +`define MLDSA_REG_MLDSA_MSG_6 (32'hb0) +`define MLDSA_REG_MLDSA_MSG_7 (32'hb4) +`define MLDSA_REG_MLDSA_MSG_8 (32'hb8) +`define MLDSA_REG_MLDSA_MSG_9 (32'hbc) +`define MLDSA_REG_MLDSA_MSG_10 (32'hc0) +`define MLDSA_REG_MLDSA_MSG_11 (32'hc4) +`define MLDSA_REG_MLDSA_MSG_12 (32'hc8) +`define MLDSA_REG_MLDSA_MSG_13 (32'hcc) +`define MLDSA_REG_MLDSA_MSG_14 (32'hd0) +`define MLDSA_REG_MLDSA_MSG_15 (32'hd4) +`define MLDSA_REG_MLDSA_VERIFY_RES_0 (32'hd8) +`define MLDSA_REG_MLDSA_VERIFY_RES_1 (32'hdc) +`define MLDSA_REG_MLDSA_VERIFY_RES_2 (32'he0) +`define MLDSA_REG_MLDSA_VERIFY_RES_3 (32'he4) +`define MLDSA_REG_MLDSA_VERIFY_RES_4 (32'he8) +`define MLDSA_REG_MLDSA_VERIFY_RES_5 (32'hec) +`define MLDSA_REG_MLDSA_VERIFY_RES_6 (32'hf0) +`define MLDSA_REG_MLDSA_VERIFY_RES_7 (32'hf4) +`define MLDSA_REG_MLDSA_VERIFY_RES_8 (32'hf8) +`define MLDSA_REG_MLDSA_VERIFY_RES_9 (32'hfc) +`define MLDSA_REG_MLDSA_VERIFY_RES_10 (32'h100) +`define MLDSA_REG_MLDSA_VERIFY_RES_11 (32'h104) +`define MLDSA_REG_MLDSA_VERIFY_RES_12 (32'h108) +`define MLDSA_REG_MLDSA_VERIFY_RES_13 (32'h10c) +`define MLDSA_REG_MLDSA_VERIFY_RES_14 (32'h110) +`define MLDSA_REG_MLDSA_VERIFY_RES_15 (32'h114) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL (32'h8000) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_EN_LOW (0) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_EN_MASK (32'h1) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_ENTRY_LOW (1) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_ENTRY_MASK (32'h3e) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_LOW (6) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (32'h40) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_RSVD_LOW (7) +`define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_RSVD_MASK (32'hffffff80) +`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS (32'h8004) +`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_READY_LOW (0) +`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_READY_MASK (32'h1) +`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_VALID_LOW (1) +`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_VALID_MASK (32'h2) +`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_ERROR_LOW (2) +`define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_ERROR_MASK (32'h3fc) +`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h8100) +`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h8104) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h8108) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h810c) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h8110) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h8114) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h8118) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h811c) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h8120) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h8200) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h8280) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'h8300) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h8304) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define CSRNG_REG_INTERRUPT_STATE (32'h0) +`define CSRNG_REG_INTERRUPT_STATE_CS_CMD_REQ_DONE_LOW (0) +`define CSRNG_REG_INTERRUPT_STATE_CS_CMD_REQ_DONE_MASK (32'h1) +`define CSRNG_REG_INTERRUPT_STATE_CS_ENTROPY_REQ_LOW (1) +`define CSRNG_REG_INTERRUPT_STATE_CS_ENTROPY_REQ_MASK (32'h2) +`define CSRNG_REG_INTERRUPT_STATE_CS_HW_INST_EXC_LOW (2) +`define CSRNG_REG_INTERRUPT_STATE_CS_HW_INST_EXC_MASK (32'h4) +`define CSRNG_REG_INTERRUPT_STATE_CS_FATAL_ERR_LOW (3) +`define CSRNG_REG_INTERRUPT_STATE_CS_FATAL_ERR_MASK (32'h8) +`define CSRNG_REG_INTERRUPT_ENABLE (32'h4) +`define CSRNG_REG_INTERRUPT_ENABLE_CS_CMD_REQ_DONE_LOW (0) +`define CSRNG_REG_INTERRUPT_ENABLE_CS_CMD_REQ_DONE_MASK (32'h1) +`define CSRNG_REG_INTERRUPT_ENABLE_CS_ENTROPY_REQ_LOW (1) +`define CSRNG_REG_INTERRUPT_ENABLE_CS_ENTROPY_REQ_MASK (32'h2) +`define CSRNG_REG_INTERRUPT_ENABLE_CS_HW_INST_EXC_LOW (2) +`define CSRNG_REG_INTERRUPT_ENABLE_CS_HW_INST_EXC_MASK (32'h4) +`define CSRNG_REG_INTERRUPT_ENABLE_CS_FATAL_ERR_LOW (3) +`define CSRNG_REG_INTERRUPT_ENABLE_CS_FATAL_ERR_MASK (32'h8) +`define CSRNG_REG_INTERRUPT_TEST (32'h8) +`define CSRNG_REG_INTERRUPT_TEST_CS_CMD_REQ_DONE_LOW (0) +`define CSRNG_REG_INTERRUPT_TEST_CS_CMD_REQ_DONE_MASK (32'h1) +`define CSRNG_REG_INTERRUPT_TEST_CS_ENTROPY_REQ_LOW (1) +`define CSRNG_REG_INTERRUPT_TEST_CS_ENTROPY_REQ_MASK (32'h2) +`define CSRNG_REG_INTERRUPT_TEST_CS_HW_INST_EXC_LOW (2) +`define CSRNG_REG_INTERRUPT_TEST_CS_HW_INST_EXC_MASK (32'h4) +`define CSRNG_REG_INTERRUPT_TEST_CS_FATAL_ERR_LOW (3) +`define CSRNG_REG_INTERRUPT_TEST_CS_FATAL_ERR_MASK (32'h8) +`define CSRNG_REG_ALERT_TEST (32'hc) +`define CSRNG_REG_ALERT_TEST_RECOV_ALERT_LOW (0) +`define CSRNG_REG_ALERT_TEST_RECOV_ALERT_MASK (32'h1) +`define CSRNG_REG_ALERT_TEST_FATAL_ALERT_LOW (1) +`define CSRNG_REG_ALERT_TEST_FATAL_ALERT_MASK (32'h2) +`define CSRNG_REG_REGWEN (32'h10) +`define CSRNG_REG_REGWEN_REGWEN_LOW (0) +`define CSRNG_REG_REGWEN_REGWEN_MASK (32'h1) +`define CSRNG_REG_CTRL (32'h14) +`define CSRNG_REG_CTRL_ENABLE_LOW (0) +`define CSRNG_REG_CTRL_ENABLE_MASK (32'hf) +`define CSRNG_REG_CTRL_SW_APP_ENABLE_LOW (4) +`define CSRNG_REG_CTRL_SW_APP_ENABLE_MASK (32'hf0) +`define CSRNG_REG_CTRL_READ_INT_STATE_LOW (8) +`define CSRNG_REG_CTRL_READ_INT_STATE_MASK (32'hf00) +`define CSRNG_REG_CMD_REQ (32'h18) +`define CSRNG_REG_CMD_REQ_ACMD_LOW (0) +`define CSRNG_REG_CMD_REQ_ACMD_MASK (32'hf) +`define CSRNG_REG_CMD_REQ_CLEN_LOW (4) +`define CSRNG_REG_CMD_REQ_CLEN_MASK (32'hf0) +`define CSRNG_REG_CMD_REQ_FLAG0_LOW (8) +`define CSRNG_REG_CMD_REQ_FLAG0_MASK (32'hf00) +`define CSRNG_REG_CMD_REQ_GLEN_LOW (12) +`define CSRNG_REG_CMD_REQ_GLEN_MASK (32'h1fff000) +`define CSRNG_REG_SW_CMD_STS (32'h1c) +`define CSRNG_REG_SW_CMD_STS_CMD_RDY_LOW (0) +`define CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK (32'h1) +`define CSRNG_REG_SW_CMD_STS_CMD_STS_LOW (1) +`define CSRNG_REG_SW_CMD_STS_CMD_STS_MASK (32'h2) +`define CSRNG_REG_GENBITS_VLD (32'h20) +`define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_LOW (0) +`define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_MASK (32'h1) +`define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_LOW (1) +`define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_MASK (32'h2) +`define CSRNG_REG_GENBITS (32'h24) +`define CSRNG_REG_INT_STATE_NUM (32'h28) +`define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_LOW (0) +`define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_MASK (32'hf) +`define CSRNG_REG_INT_STATE_VAL (32'h2c) +`define CSRNG_REG_HW_EXC_STS (32'h30) +`define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_LOW (0) +`define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_MASK (32'hffff) +`define CSRNG_REG_RECOV_ALERT_STS (32'h34) +`define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_LOW (0) +`define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_MASK (32'h1) +`define CSRNG_REG_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_LOW (1) +`define CSRNG_REG_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_MASK (32'h2) +`define CSRNG_REG_RECOV_ALERT_STS_READ_INT_STATE_FIELD_ALERT_LOW (2) +`define CSRNG_REG_RECOV_ALERT_STS_READ_INT_STATE_FIELD_ALERT_MASK (32'h4) +`define CSRNG_REG_RECOV_ALERT_STS_ACMD_FLAG0_FIELD_ALERT_LOW (3) +`define CSRNG_REG_RECOV_ALERT_STS_ACMD_FLAG0_FIELD_ALERT_MASK (32'h8) +`define CSRNG_REG_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_LOW (12) +`define CSRNG_REG_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_MASK (32'h1000) +`define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_LOW (13) +`define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_MASK (32'h2000) +`define CSRNG_REG_ERR_CODE (32'h38) +`define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_LOW (0) +`define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_MASK (32'h1) +`define CSRNG_REG_ERR_CODE_SFIFO_GENBITS_ERR_LOW (1) +`define CSRNG_REG_ERR_CODE_SFIFO_GENBITS_ERR_MASK (32'h2) +`define CSRNG_REG_ERR_CODE_SFIFO_CMDREQ_ERR_LOW (2) +`define CSRNG_REG_ERR_CODE_SFIFO_CMDREQ_ERR_MASK (32'h4) +`define CSRNG_REG_ERR_CODE_SFIFO_RCSTAGE_ERR_LOW (3) +`define CSRNG_REG_ERR_CODE_SFIFO_RCSTAGE_ERR_MASK (32'h8) +`define CSRNG_REG_ERR_CODE_SFIFO_KEYVRC_ERR_LOW (4) +`define CSRNG_REG_ERR_CODE_SFIFO_KEYVRC_ERR_MASK (32'h10) +`define CSRNG_REG_ERR_CODE_SFIFO_UPDREQ_ERR_LOW (5) +`define CSRNG_REG_ERR_CODE_SFIFO_UPDREQ_ERR_MASK (32'h20) +`define CSRNG_REG_ERR_CODE_SFIFO_BENCREQ_ERR_LOW (6) +`define CSRNG_REG_ERR_CODE_SFIFO_BENCREQ_ERR_MASK (32'h40) +`define CSRNG_REG_ERR_CODE_SFIFO_BENCACK_ERR_LOW (7) +`define CSRNG_REG_ERR_CODE_SFIFO_BENCACK_ERR_MASK (32'h80) +`define CSRNG_REG_ERR_CODE_SFIFO_PDATA_ERR_LOW (8) +`define CSRNG_REG_ERR_CODE_SFIFO_PDATA_ERR_MASK (32'h100) +`define CSRNG_REG_ERR_CODE_SFIFO_FINAL_ERR_LOW (9) +`define CSRNG_REG_ERR_CODE_SFIFO_FINAL_ERR_MASK (32'h200) +`define CSRNG_REG_ERR_CODE_SFIFO_GBENCACK_ERR_LOW (10) +`define CSRNG_REG_ERR_CODE_SFIFO_GBENCACK_ERR_MASK (32'h400) +`define CSRNG_REG_ERR_CODE_SFIFO_GRCSTAGE_ERR_LOW (11) +`define CSRNG_REG_ERR_CODE_SFIFO_GRCSTAGE_ERR_MASK (32'h800) +`define CSRNG_REG_ERR_CODE_SFIFO_GGENREQ_ERR_LOW (12) +`define CSRNG_REG_ERR_CODE_SFIFO_GGENREQ_ERR_MASK (32'h1000) +`define CSRNG_REG_ERR_CODE_SFIFO_GADSTAGE_ERR_LOW (13) +`define CSRNG_REG_ERR_CODE_SFIFO_GADSTAGE_ERR_MASK (32'h2000) +`define CSRNG_REG_ERR_CODE_SFIFO_GGENBITS_ERR_LOW (14) +`define CSRNG_REG_ERR_CODE_SFIFO_GGENBITS_ERR_MASK (32'h4000) +`define CSRNG_REG_ERR_CODE_SFIFO_BLKENC_ERR_LOW (15) +`define CSRNG_REG_ERR_CODE_SFIFO_BLKENC_ERR_MASK (32'h8000) +`define CSRNG_REG_ERR_CODE_CMD_STAGE_SM_ERR_LOW (20) +`define CSRNG_REG_ERR_CODE_CMD_STAGE_SM_ERR_MASK (32'h100000) +`define CSRNG_REG_ERR_CODE_MAIN_SM_ERR_LOW (21) +`define CSRNG_REG_ERR_CODE_MAIN_SM_ERR_MASK (32'h200000) +`define CSRNG_REG_ERR_CODE_DRBG_GEN_SM_ERR_LOW (22) +`define CSRNG_REG_ERR_CODE_DRBG_GEN_SM_ERR_MASK (32'h400000) +`define CSRNG_REG_ERR_CODE_DRBG_UPDBE_SM_ERR_LOW (23) +`define CSRNG_REG_ERR_CODE_DRBG_UPDBE_SM_ERR_MASK (32'h800000) +`define CSRNG_REG_ERR_CODE_DRBG_UPDOB_SM_ERR_LOW (24) +`define CSRNG_REG_ERR_CODE_DRBG_UPDOB_SM_ERR_MASK (32'h1000000) +`define CSRNG_REG_ERR_CODE_AES_CIPHER_SM_ERR_LOW (25) +`define CSRNG_REG_ERR_CODE_AES_CIPHER_SM_ERR_MASK (32'h2000000) +`define CSRNG_REG_ERR_CODE_CMD_GEN_CNT_ERR_LOW (26) +`define CSRNG_REG_ERR_CODE_CMD_GEN_CNT_ERR_MASK (32'h4000000) +`define CSRNG_REG_ERR_CODE_FIFO_WRITE_ERR_LOW (28) +`define CSRNG_REG_ERR_CODE_FIFO_WRITE_ERR_MASK (32'h10000000) +`define CSRNG_REG_ERR_CODE_FIFO_READ_ERR_LOW (29) +`define CSRNG_REG_ERR_CODE_FIFO_READ_ERR_MASK (32'h20000000) +`define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30) +`define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_MASK (32'h40000000) +`define CSRNG_REG_ERR_CODE_TEST (32'h3c) +`define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0) +`define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (32'h1f) +`define CSRNG_REG_MAIN_SM_STATE (32'h40) +`define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) +`define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (32'hff) +`define ENTROPY_SRC_REG_INTERRUPT_STATE (32'h0) +`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_ENTROPY_VALID_LOW (0) +`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_ENTROPY_VALID_MASK (32'h1) +`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_HEALTH_TEST_FAILED_LOW (1) +`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_HEALTH_TEST_FAILED_MASK (32'h2) +`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_OBSERVE_FIFO_READY_LOW (2) +`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_OBSERVE_FIFO_READY_MASK (32'h4) +`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_FATAL_ERR_LOW (3) +`define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_FATAL_ERR_MASK (32'h8) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE (32'h4) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_ENTROPY_VALID_LOW (0) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_ENTROPY_VALID_MASK (32'h1) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_HEALTH_TEST_FAILED_LOW (1) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_HEALTH_TEST_FAILED_MASK (32'h2) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_OBSERVE_FIFO_READY_LOW (2) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_OBSERVE_FIFO_READY_MASK (32'h4) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_FATAL_ERR_LOW (3) +`define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_FATAL_ERR_MASK (32'h8) +`define ENTROPY_SRC_REG_INTERRUPT_TEST (32'h8) +`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_ENTROPY_VALID_LOW (0) +`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_ENTROPY_VALID_MASK (32'h1) +`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_HEALTH_TEST_FAILED_LOW (1) +`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_HEALTH_TEST_FAILED_MASK (32'h2) +`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_OBSERVE_FIFO_READY_LOW (2) +`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_OBSERVE_FIFO_READY_MASK (32'h4) +`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_FATAL_ERR_LOW (3) +`define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_FATAL_ERR_MASK (32'h8) +`define ENTROPY_SRC_REG_ALERT_TEST (32'hc) +`define ENTROPY_SRC_REG_ALERT_TEST_RECOV_ALERT_LOW (0) +`define ENTROPY_SRC_REG_ALERT_TEST_RECOV_ALERT_MASK (32'h1) +`define ENTROPY_SRC_REG_ALERT_TEST_FATAL_ALERT_LOW (1) +`define ENTROPY_SRC_REG_ALERT_TEST_FATAL_ALERT_MASK (32'h2) +`define ENTROPY_SRC_REG_ME_REGWEN (32'h10) +`define ENTROPY_SRC_REG_ME_REGWEN_ME_REGWEN_LOW (0) +`define ENTROPY_SRC_REG_ME_REGWEN_ME_REGWEN_MASK (32'h1) +`define ENTROPY_SRC_REG_SW_REGUPD (32'h14) +`define ENTROPY_SRC_REG_SW_REGUPD_SW_REGUPD_LOW (0) +`define ENTROPY_SRC_REG_SW_REGUPD_SW_REGUPD_MASK (32'h1) +`define ENTROPY_SRC_REG_REGWEN (32'h18) +`define ENTROPY_SRC_REG_REGWEN_REGWEN_LOW (0) +`define ENTROPY_SRC_REG_REGWEN_REGWEN_MASK (32'h1) +`define ENTROPY_SRC_REG_REV (32'h1c) +`define ENTROPY_SRC_REG_REV_ABI_REVISION_LOW (0) +`define ENTROPY_SRC_REG_REV_ABI_REVISION_MASK (32'hff) +`define ENTROPY_SRC_REG_REV_HW_REVISION_LOW (8) +`define ENTROPY_SRC_REG_REV_HW_REVISION_MASK (32'hff00) +`define ENTROPY_SRC_REG_REV_CHIP_TYPE_LOW (16) +`define ENTROPY_SRC_REG_REV_CHIP_TYPE_MASK (32'hff0000) +`define ENTROPY_SRC_REG_MODULE_ENABLE (32'h20) +`define ENTROPY_SRC_REG_MODULE_ENABLE_MODULE_ENABLE_LOW (0) +`define ENTROPY_SRC_REG_MODULE_ENABLE_MODULE_ENABLE_MASK (32'hf) +`define ENTROPY_SRC_REG_CONF (32'h24) +`define ENTROPY_SRC_REG_CONF_FIPS_ENABLE_LOW (0) +`define ENTROPY_SRC_REG_CONF_FIPS_ENABLE_MASK (32'hf) +`define ENTROPY_SRC_REG_CONF_ENTROPY_DATA_REG_ENABLE_LOW (4) +`define ENTROPY_SRC_REG_CONF_ENTROPY_DATA_REG_ENABLE_MASK (32'hf0) +`define ENTROPY_SRC_REG_CONF_THRESHOLD_SCOPE_LOW (12) +`define ENTROPY_SRC_REG_CONF_THRESHOLD_SCOPE_MASK (32'hf000) +`define ENTROPY_SRC_REG_CONF_RNG_BIT_ENABLE_LOW (20) +`define ENTROPY_SRC_REG_CONF_RNG_BIT_ENABLE_MASK (32'hf00000) +`define ENTROPY_SRC_REG_CONF_RNG_BIT_SEL_LOW (24) +`define ENTROPY_SRC_REG_CONF_RNG_BIT_SEL_MASK (32'h3000000) +`define ENTROPY_SRC_REG_ENTROPY_CONTROL (32'h28) +`define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_ROUTE_LOW (0) +`define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_ROUTE_MASK (32'hf) +`define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_TYPE_LOW (4) +`define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_TYPE_MASK (32'hf0) +`define ENTROPY_SRC_REG_ENTROPY_DATA (32'h2c) +`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS (32'h30) +`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_FIPS_WINDOW_LOW (0) +`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_FIPS_WINDOW_MASK (32'hffff) +`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_LOW (16) +`define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS (32'h34) +`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS (32'h38) +`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS (32'h3c) +`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS (32'h40) +`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS (32'h44) +`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS (32'h48) +`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS (32'h4c) +`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS (32'h50) +`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS (32'h54) +`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_FIPS_THRESH_LOW (0) +`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) +`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) +`define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS (32'h58) +`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS (32'h5c) +`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS (32'h60) +`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS (32'h64) +`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS (32'h68) +`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS (32'h6c) +`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS (32'h70) +`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS (32'h74) +`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS (32'h78) +`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) +`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) +`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) +`define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_REPCNT_TOTAL_FAILS (32'h7c) +`define ENTROPY_SRC_REG_REPCNTS_TOTAL_FAILS (32'h80) +`define ENTROPY_SRC_REG_ADAPTP_HI_TOTAL_FAILS (32'h84) +`define ENTROPY_SRC_REG_ADAPTP_LO_TOTAL_FAILS (32'h88) +`define ENTROPY_SRC_REG_BUCKET_TOTAL_FAILS (32'h8c) +`define ENTROPY_SRC_REG_MARKOV_HI_TOTAL_FAILS (32'h90) +`define ENTROPY_SRC_REG_MARKOV_LO_TOTAL_FAILS (32'h94) +`define ENTROPY_SRC_REG_EXTHT_HI_TOTAL_FAILS (32'h98) +`define ENTROPY_SRC_REG_EXTHT_LO_TOTAL_FAILS (32'h9c) +`define ENTROPY_SRC_REG_ALERT_THRESHOLD (32'ha0) +`define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_LOW (0) +`define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_MASK (32'hffff) +`define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_LOW (16) +`define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_MASK (32'hffff0000) +`define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS (32'ha4) +`define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_LOW (0) +`define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_MASK (32'hffff) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS (32'ha8) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_LOW (4) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_MASK (32'hf0) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_LOW (8) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_MASK (32'hf00) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_LOW (12) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_MASK (32'hf000) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_LOW (16) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_MASK (32'hf0000) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_LOW (20) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_MASK (32'hf00000) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_LOW (24) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_MASK (32'hf000000) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_LOW (28) +`define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_MASK (32'hf0000000) +`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS (32'hac) +`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_LOW (0) +`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_MASK (32'hf) +`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_LOW (4) +`define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_MASK (32'hf0) +`define ENTROPY_SRC_REG_FW_OV_CONTROL (32'hb0) +`define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_MODE_LOW (0) +`define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_MODE_MASK (32'hf) +`define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_LOW (4) +`define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK (32'hf0) +`define ENTROPY_SRC_REG_FW_OV_SHA3_START (32'hb4) +`define ENTROPY_SRC_REG_FW_OV_SHA3_START_FW_OV_INSERT_START_LOW (0) +`define ENTROPY_SRC_REG_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK (32'hf) +`define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL (32'hb8) +`define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_LOW (0) +`define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_MASK (32'h1) +`define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW (32'hbc) +`define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_LOW (0) +`define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_MASK (32'h1) +`define ENTROPY_SRC_REG_FW_OV_RD_DATA (32'hc0) +`define ENTROPY_SRC_REG_FW_OV_WR_DATA (32'hc4) +`define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH (32'hc8) +`define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_LOW (0) +`define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK (32'h7f) +`define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH (32'hcc) +`define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_LOW (0) +`define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_MASK (32'h7f) +`define ENTROPY_SRC_REG_DEBUG_STATUS (32'hd0) +`define ENTROPY_SRC_REG_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_LOW (0) +`define ENTROPY_SRC_REG_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_MASK (32'h7) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_FSM_LOW (3) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_FSM_MASK (32'h38) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_BLOCK_PR_LOW (6) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_BLOCK_PR_MASK (32'h40) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_SQUEEZING_LOW (7) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_SQUEEZING_MASK (32'h80) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_ABSORBED_LOW (8) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_ABSORBED_MASK (32'h100) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_ERR_LOW (9) +`define ENTROPY_SRC_REG_DEBUG_STATUS_SHA3_ERR_MASK (32'h200) +`define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_IDLE_LOW (16) +`define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_IDLE_MASK (32'h10000) +`define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_BOOT_DONE_LOW (17) +`define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_BOOT_DONE_MASK (32'h20000) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS (32'hd4) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_LOW (0) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_MASK (32'h1) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ENTROPY_DATA_REG_EN_FIELD_ALERT_LOW (1) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ENTROPY_DATA_REG_EN_FIELD_ALERT_MASK (32'h2) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_MODULE_ENABLE_FIELD_ALERT_LOW (2) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_MODULE_ENABLE_FIELD_ALERT_MASK (32'h4) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_THRESHOLD_SCOPE_FIELD_ALERT_LOW (3) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_THRESHOLD_SCOPE_FIELD_ALERT_MASK (32'h8) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_RNG_BIT_ENABLE_FIELD_ALERT_LOW (5) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_RNG_BIT_ENABLE_FIELD_ALERT_MASK (32'h20) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_SHA3_START_FIELD_ALERT_LOW (7) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_SHA3_START_FIELD_ALERT_MASK (32'h80) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_MODE_FIELD_ALERT_LOW (8) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_MODE_FIELD_ALERT_MASK (32'h100) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_ENTROPY_INSERT_FIELD_ALERT_LOW (9) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_FW_OV_ENTROPY_INSERT_FIELD_ALERT_MASK (32'h200) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_ROUTE_FIELD_ALERT_LOW (10) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_ROUTE_FIELD_ALERT_MASK (32'h400) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_TYPE_FIELD_ALERT_LOW (11) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_TYPE_FIELD_ALERT_MASK (32'h800) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_MAIN_SM_ALERT_LOW (12) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_MAIN_SM_ALERT_MASK (32'h1000) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_BUS_CMP_ALERT_LOW (13) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_BUS_CMP_ALERT_MASK (32'h2000) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_THRESH_CFG_ALERT_LOW (14) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_THRESH_CFG_ALERT_MASK (32'h4000) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_LOW (15) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_MASK (32'h8000) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_LOW (16) +`define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_MASK (32'h10000) +`define ENTROPY_SRC_REG_ERR_CODE (32'hd8) +`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESRNG_ERR_LOW (0) +`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESRNG_ERR_MASK (32'h1) +`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_OBSERVE_ERR_LOW (1) +`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_OBSERVE_ERR_MASK (32'h2) +`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESFINAL_ERR_LOW (2) +`define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESFINAL_ERR_MASK (32'h4) +`define ENTROPY_SRC_REG_ERR_CODE_ES_ACK_SM_ERR_LOW (20) +`define ENTROPY_SRC_REG_ERR_CODE_ES_ACK_SM_ERR_MASK (32'h100000) +`define ENTROPY_SRC_REG_ERR_CODE_ES_MAIN_SM_ERR_LOW (21) +`define ENTROPY_SRC_REG_ERR_CODE_ES_MAIN_SM_ERR_MASK (32'h200000) +`define ENTROPY_SRC_REG_ERR_CODE_ES_CNTR_ERR_LOW (22) +`define ENTROPY_SRC_REG_ERR_CODE_ES_CNTR_ERR_MASK (32'h400000) +`define ENTROPY_SRC_REG_ERR_CODE_SHA3_STATE_ERR_LOW (23) +`define ENTROPY_SRC_REG_ERR_CODE_SHA3_STATE_ERR_MASK (32'h800000) +`define ENTROPY_SRC_REG_ERR_CODE_SHA3_RST_STORAGE_ERR_LOW (24) +`define ENTROPY_SRC_REG_ERR_CODE_SHA3_RST_STORAGE_ERR_MASK (32'h1000000) +`define ENTROPY_SRC_REG_ERR_CODE_FIFO_WRITE_ERR_LOW (28) +`define ENTROPY_SRC_REG_ERR_CODE_FIFO_WRITE_ERR_MASK (32'h10000000) +`define ENTROPY_SRC_REG_ERR_CODE_FIFO_READ_ERR_LOW (29) +`define ENTROPY_SRC_REG_ERR_CODE_FIFO_READ_ERR_MASK (32'h20000000) +`define ENTROPY_SRC_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30) +`define ENTROPY_SRC_REG_ERR_CODE_FIFO_STATE_ERR_MASK (32'h40000000) +`define ENTROPY_SRC_REG_ERR_CODE_TEST (32'hdc) +`define ENTROPY_SRC_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0) +`define ENTROPY_SRC_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (32'h1f) +`define ENTROPY_SRC_REG_MAIN_SM_STATE (32'he0) +`define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) +`define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (32'h1ff) +`define MBOX_CSR_MBOX_LOCK (32'h0) +`define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) +`define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) +`define MBOX_CSR_MBOX_USER (32'h4) +`define MBOX_CSR_MBOX_CMD (32'h8) +`define MBOX_CSR_MBOX_DLEN (32'hc) +`define MBOX_CSR_MBOX_DATAIN (32'h10) +`define MBOX_CSR_MBOX_DATAOUT (32'h14) +`define MBOX_CSR_MBOX_EXECUTE (32'h18) +`define MBOX_CSR_MBOX_EXECUTE_EXECUTE_LOW (0) +`define MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK (32'h1) +`define MBOX_CSR_MBOX_STATUS (32'h1c) +`define MBOX_CSR_MBOX_STATUS_STATUS_LOW (0) +`define MBOX_CSR_MBOX_STATUS_STATUS_MASK (32'hf) +`define MBOX_CSR_MBOX_STATUS_ECC_SINGLE_ERROR_LOW (4) +`define MBOX_CSR_MBOX_STATUS_ECC_SINGLE_ERROR_MASK (32'h10) +`define MBOX_CSR_MBOX_STATUS_ECC_DOUBLE_ERROR_LOW (5) +`define MBOX_CSR_MBOX_STATUS_ECC_DOUBLE_ERROR_MASK (32'h20) +`define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW (6) +`define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK (32'h1c0) +`define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW (9) +`define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (32'h200) +`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) +`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h3fffc00) +`define MBOX_CSR_MBOX_UNLOCK (32'h20) +`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) +`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (32'h1) +`define MBOX_CSR_TAP_MODE (32'h24) +`define MBOX_CSR_TAP_MODE_ENABLED_LOW (0) +`define MBOX_CSR_TAP_MODE_ENABLED_MASK (32'h1) +`define SHA512_ACC_CSR_LOCK (32'h0) +`define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) +`define SHA512_ACC_CSR_LOCK_LOCK_MASK (32'h1) +`define SHA512_ACC_CSR_USER (32'h4) +`define SHA512_ACC_CSR_MODE (32'h8) +`define SHA512_ACC_CSR_MODE_MODE_LOW (0) +`define SHA512_ACC_CSR_MODE_MODE_MASK (32'h3) +`define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_LOW (2) +`define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_MASK (32'h4) +`define SHA512_ACC_CSR_START_ADDRESS (32'hc) +`define SHA512_ACC_CSR_DLEN (32'h10) +`define SHA512_ACC_CSR_DATAIN (32'h14) +`define SHA512_ACC_CSR_EXECUTE (32'h18) +`define SHA512_ACC_CSR_EXECUTE_EXECUTE_LOW (0) +`define SHA512_ACC_CSR_EXECUTE_EXECUTE_MASK (32'h1) +`define SHA512_ACC_CSR_STATUS (32'h1c) +`define SHA512_ACC_CSR_STATUS_VALID_LOW (0) +`define SHA512_ACC_CSR_STATUS_VALID_MASK (32'h1) +`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW (1) +`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK (32'h2) +`define SHA512_ACC_CSR_DIGEST_0 (32'h20) +`define SHA512_ACC_CSR_DIGEST_1 (32'h24) +`define SHA512_ACC_CSR_DIGEST_2 (32'h28) +`define SHA512_ACC_CSR_DIGEST_3 (32'h2c) +`define SHA512_ACC_CSR_DIGEST_4 (32'h30) +`define SHA512_ACC_CSR_DIGEST_5 (32'h34) +`define SHA512_ACC_CSR_DIGEST_6 (32'h38) +`define SHA512_ACC_CSR_DIGEST_7 (32'h3c) +`define SHA512_ACC_CSR_DIGEST_8 (32'h40) +`define SHA512_ACC_CSR_DIGEST_9 (32'h44) +`define SHA512_ACC_CSR_DIGEST_10 (32'h48) +`define SHA512_ACC_CSR_DIGEST_11 (32'h4c) +`define SHA512_ACC_CSR_DIGEST_12 (32'h50) +`define SHA512_ACC_CSR_DIGEST_13 (32'h54) +`define SHA512_ACC_CSR_DIGEST_14 (32'h58) +`define SHA512_ACC_CSR_DIGEST_15 (32'h5c) +`define SHA512_ACC_CSR_CONTROL (32'h60) +`define SHA512_ACC_CSR_CONTROL_ZEROIZE_LOW (0) +`define SHA512_ACC_CSR_CONTROL_ZEROIZE_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_LOW (1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK (32'h2) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_LOW (2) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_LOW (1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK (32'h2) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_LOW (2) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_LOW (1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK (32'h2) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_LOW (2) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_ID (32'h0) +`define AXI_DMA_REG_CAP (32'h4) +`define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW (0) +`define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK (32'hfff) +`define AXI_DMA_REG_CAP_RSVD_LOW (12) +`define AXI_DMA_REG_CAP_RSVD_MASK (32'hfffff000) +`define AXI_DMA_REG_CTRL (32'h8) +`define AXI_DMA_REG_CTRL_GO_LOW (0) +`define AXI_DMA_REG_CTRL_GO_MASK (32'h1) +`define AXI_DMA_REG_CTRL_FLUSH_LOW (1) +`define AXI_DMA_REG_CTRL_FLUSH_MASK (32'h2) +`define AXI_DMA_REG_CTRL_RSVD0_LOW (2) +`define AXI_DMA_REG_CTRL_RSVD0_MASK (32'hfffc) +`define AXI_DMA_REG_CTRL_RD_ROUTE_LOW (16) +`define AXI_DMA_REG_CTRL_RD_ROUTE_MASK (32'h30000) +`define AXI_DMA_REG_CTRL_RSVD1_LOW (18) +`define AXI_DMA_REG_CTRL_RSVD1_MASK (32'hc0000) +`define AXI_DMA_REG_CTRL_RD_FIXED_LOW (20) +`define AXI_DMA_REG_CTRL_RD_FIXED_MASK (32'h100000) +`define AXI_DMA_REG_CTRL_RSVD2_LOW (21) +`define AXI_DMA_REG_CTRL_RSVD2_MASK (32'he00000) +`define AXI_DMA_REG_CTRL_WR_ROUTE_LOW (24) +`define AXI_DMA_REG_CTRL_WR_ROUTE_MASK (32'h3000000) +`define AXI_DMA_REG_CTRL_RSVD3_LOW (26) +`define AXI_DMA_REG_CTRL_RSVD3_MASK (32'hc000000) +`define AXI_DMA_REG_CTRL_WR_FIXED_LOW (28) +`define AXI_DMA_REG_CTRL_WR_FIXED_MASK (32'h10000000) +`define AXI_DMA_REG_CTRL_RSVD4_LOW (29) +`define AXI_DMA_REG_CTRL_RSVD4_MASK (32'he0000000) +`define AXI_DMA_REG_STATUS0 (32'hc) +`define AXI_DMA_REG_STATUS0_BUSY_LOW (0) +`define AXI_DMA_REG_STATUS0_BUSY_MASK (32'h1) +`define AXI_DMA_REG_STATUS0_ERROR_LOW (1) +`define AXI_DMA_REG_STATUS0_ERROR_MASK (32'h2) +`define AXI_DMA_REG_STATUS0_RSVD0_LOW (2) +`define AXI_DMA_REG_STATUS0_RSVD0_MASK (32'hc) +`define AXI_DMA_REG_STATUS0_FIFO_DEPTH_LOW (4) +`define AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK (32'hfff0) +`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW (16) +`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK (32'h30000) +`define AXI_DMA_REG_STATUS0_PAYLOAD_AVAILABLE_LOW (18) +`define AXI_DMA_REG_STATUS0_PAYLOAD_AVAILABLE_MASK (32'h40000) +`define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_LOW (19) +`define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_MASK (32'h80000) +`define AXI_DMA_REG_STATUS0_RSVD1_LOW (20) +`define AXI_DMA_REG_STATUS0_RSVD1_MASK (32'hfff00000) +`define AXI_DMA_REG_STATUS1 (32'h10) +`define AXI_DMA_REG_SRC_ADDR_L (32'h14) +`define AXI_DMA_REG_SRC_ADDR_H (32'h18) +`define AXI_DMA_REG_DST_ADDR_L (32'h1c) +`define AXI_DMA_REG_DST_ADDR_H (32'h20) +`define AXI_DMA_REG_BYTE_COUNT (32'h24) +`define AXI_DMA_REG_BLOCK_SIZE (32'h28) +`define AXI_DMA_REG_BLOCK_SIZE_SIZE_LOW (0) +`define AXI_DMA_REG_BLOCK_SIZE_SIZE_MASK (32'hfff) +`define AXI_DMA_REG_BLOCK_SIZE_RSVD_LOW (12) +`define AXI_DMA_REG_BLOCK_SIZE_RSVD_MASK (32'hfffff000) +`define AXI_DMA_REG_WRITE_DATA (32'h2c) +`define AXI_DMA_REG_READ_DATA (32'h30) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_RD_EN_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_AXI_WR_EN_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_LOCK_EN_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_SHA_LOCK_EN_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK (32'h40) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_EMPTY_EN_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_EMPTY_EN_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_RD_STS_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_AXI_WR_STS_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_LOCK_STS_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_SHA_LOCK_STS_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK (32'h40) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_EMPTY_STS_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_EMPTY_STS_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_RD_TRIG_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_AXI_WR_TRIG_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_LOCK_TRIG_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_SHA_LOCK_TRIG_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_LOW (5) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_MASK (32'h20) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_LOW (6) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_MASK (32'h40) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_LOW (1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_EMPTY_TRIG_MASK (32'h2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_LOW (2) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_EMPTY_TRIG_MASK (32'h4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_LOW (3) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_MASK (32'h8) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_LOW (4) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_MASK (32'h10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (32'h900) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (32'h904) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (32'h908) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (32'h90c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (32'h910) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (32'h914) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (32'h918) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (32'h980) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (32'h984) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (32'h988) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (32'h98c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (32'h990) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (32'ha00) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (32'ha04) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (32'ha08) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (32'ha0c) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (32'ha10) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (32'ha14) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (32'ha18) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (32'ha1c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (32'ha20) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (32'ha24) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (32'ha28) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (32'ha2c) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (32'h0) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW (0) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW (1) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK (32'h2) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW (2) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (32'h4) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4) +`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW (1) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK (32'h2) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW (2) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (32'h4) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3) +`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (32'hfffffff8) +`define SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (32'h8) +`define SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL (32'hc) +`define SOC_IFC_REG_CPTRA_HW_ERROR_ENC (32'h10) +`define SOC_IFC_REG_CPTRA_FW_ERROR_ENC (32'h14) +`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (32'h18) +`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (32'h1c) +`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (32'h20) +`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (32'h24) +`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (32'h28) +`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (32'h2c) +`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (32'h30) +`define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (32'h34) +`define SOC_IFC_REG_CPTRA_BOOT_STATUS (32'h38) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS (32'h3c) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_LOW (0) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK (32'hffffff) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_LOW (24) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (32'h1000000) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (32'he000000) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (32'h10000000) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (32'h20000000) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK (32'h40000000) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_LOW (31) +`define SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK (32'h80000000) +`define SOC_IFC_REG_CPTRA_RESET_REASON (32'h40) +`define SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_LOW (0) +`define SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_RESET_REASON_WARM_RESET_LOW (1) +`define SOC_IFC_REG_CPTRA_RESET_REASON_WARM_RESET_MASK (32'h2) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE (32'h44) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_LOW (0) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_MASK (32'h3) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEBUG_LOCKED_LOW (2) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEBUG_LOCKED_MASK (32'h4) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_LOW (3) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) +`define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h48) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h4c) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h50) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h54) +`define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h58) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h5c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h60) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h64) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h68) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h6c) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (32'h70) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h74) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h78) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_1 (32'h7c) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_2 (32'h80) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_3 (32'h84) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_4 (32'h88) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_5 (32'h8c) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_6 (32'h90) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_7 (32'h94) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_8 (32'h98) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_9 (32'h9c) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_10 (32'ha0) +`define SOC_IFC_REG_CPTRA_TRNG_DATA_11 (32'ha4) +`define SOC_IFC_REG_CPTRA_TRNG_CTRL (32'ha8) +`define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_LOW (0) +`define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_TRNG_STATUS (32'hac) +`define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW (0) +`define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW (1) +`define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK (32'h2) +`define SOC_IFC_REG_CPTRA_FUSE_WR_DONE (32'hb0) +`define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_LOW (0) +`define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_TIMER_CONFIG (32'hb4) +`define SOC_IFC_REG_CPTRA_BOOTFSM_GO (32'hb8) +`define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_LOW (0) +`define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG (32'hbc) +`define SOC_IFC_REG_CPTRA_CLK_GATING_EN (32'hc0) +`define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW (0) +`define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0 (32'hc4) +`define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1 (32'hc8) +`define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (32'hcc) +`define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (32'hd0) +`define SOC_IFC_REG_CPTRA_HW_REV_ID (32'hd4) +`define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW (0) +`define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK (32'hffff) +`define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW (16) +`define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK (32'hffff0000) +`define SOC_IFC_REG_CPTRA_FW_REV_ID_0 (32'hd8) +`define SOC_IFC_REG_CPTRA_FW_REV_ID_1 (32'hdc) +`define SOC_IFC_REG_CPTRA_HW_CONFIG (32'he0) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (32'he) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (32'h20) +`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'he4) +`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) +`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL (32'he8) +`define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW (0) +`define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'hec) +`define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'hf0) +`define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN (32'hf4) +`define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW (0) +`define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL (32'hf8) +`define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW (0) +`define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'hfc) +`define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h100) +`define SOC_IFC_REG_CPTRA_WDT_STATUS (32'h104) +`define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW (0) +`define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) +`define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) +`define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (32'h108) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h10c) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h110) +`define SOC_IFC_REG_CPTRA_WDT_CFG_1 (32'h114) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (32'h118) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW (0) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK (32'hffff) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW (16) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK (32'hffff0000) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (32'h11c) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW (0) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK (32'hffff) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW (16) +`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK (32'hffff0000) +`define SOC_IFC_REG_CPTRA_RSVD_REG_0 (32'h120) +`define SOC_IFC_REG_CPTRA_RSVD_REG_1 (32'h124) +`define SOC_IFC_REG_CPTRA_HW_CAPABILITIES (32'h128) +`define SOC_IFC_REG_CPTRA_FW_CAPABILITIES (32'h12c) +`define SOC_IFC_REG_CPTRA_CAP_LOCK (32'h130) +`define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_MASK (32'h1) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (32'h140) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (32'h144) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (32'h148) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (32'h14c) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (32'h150) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (32'h154) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (32'h158) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (32'h15c) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (32'h160) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (32'h164) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (32'h168) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (32'h16c) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h170) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (32'h1) +`define SOC_IFC_REG_FUSE_UDS_SEED_0 (32'h200) +`define SOC_IFC_REG_FUSE_UDS_SEED_1 (32'h204) +`define SOC_IFC_REG_FUSE_UDS_SEED_2 (32'h208) +`define SOC_IFC_REG_FUSE_UDS_SEED_3 (32'h20c) +`define SOC_IFC_REG_FUSE_UDS_SEED_4 (32'h210) +`define SOC_IFC_REG_FUSE_UDS_SEED_5 (32'h214) +`define SOC_IFC_REG_FUSE_UDS_SEED_6 (32'h218) +`define SOC_IFC_REG_FUSE_UDS_SEED_7 (32'h21c) +`define SOC_IFC_REG_FUSE_UDS_SEED_8 (32'h220) +`define SOC_IFC_REG_FUSE_UDS_SEED_9 (32'h224) +`define SOC_IFC_REG_FUSE_UDS_SEED_10 (32'h228) +`define SOC_IFC_REG_FUSE_UDS_SEED_11 (32'h22c) +`define SOC_IFC_REG_FUSE_UDS_SEED_12 (32'h230) +`define SOC_IFC_REG_FUSE_UDS_SEED_13 (32'h234) +`define SOC_IFC_REG_FUSE_UDS_SEED_14 (32'h238) +`define SOC_IFC_REG_FUSE_UDS_SEED_15 (32'h23c) +`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 (32'h240) +`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_1 (32'h244) +`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_2 (32'h248) +`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_3 (32'h24c) +`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_4 (32'h250) +`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_5 (32'h254) +`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 (32'h258) +`define SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (32'h25c) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (32'h260) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (32'h264) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (32'h268) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (32'h26c) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (32'h270) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (32'h274) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (32'h278) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (32'h27c) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (32'h280) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (32'h284) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (32'h288) +`define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (32'h28c) +`define SOC_IFC_REG_FUSE_ECC_REVOCATION (32'h290) +`define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) +`define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (32'hf) +`define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) +`define SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h2b8) +`define SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (32'h2bc) +`define SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (32'h2c0) +`define SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (32'h2c4) +`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2c8) +`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0) +`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (32'h1) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2cc) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2d0) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2d4) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2d8) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2dc) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2e0) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2e4) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2e8) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2ec) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h2f0) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h2f4) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h2f8) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h2fc) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h300) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h304) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h308) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h30c) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h310) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h314) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h318) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h31c) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h320) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h324) +`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h328) +`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h32c) +`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h330) +`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h334) +`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h338) +`define SOC_IFC_REG_FUSE_LMS_REVOCATION (32'h340) +`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION (32'h344) +`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0) +`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (32'hf) +`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID (32'h348) +`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0) +`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) +`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h34c) +`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h350) +`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354) +`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358) +`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE (32'h35c) +`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) +`define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (32'h3) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h360) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h364) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h368) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h36c) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h370) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) +`define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (32'hff) +`define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500) +`define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (32'h504) +`define SOC_IFC_REG_SS_MCI_BASE_ADDR_L (32'h508) +`define SOC_IFC_REG_SS_MCI_BASE_ADDR_H (32'h50c) +`define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h510) +`define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h514) +`define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (32'h518) +`define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (32'h51c) +`define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (32'h520) +`define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (32'h524) +`define SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h528) +`define SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h52c) +`define SOC_IFC_REG_SS_DEBUG_INTENT (32'h530) +`define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0) +`define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (32'h1) +`define SOC_IFC_REG_SS_STRAP_GENERIC_0 (32'h5a0) +`define SOC_IFC_REG_SS_STRAP_GENERIC_1 (32'h5a4) +`define SOC_IFC_REG_SS_STRAP_GENERIC_2 (32'h5a8) +`define SOC_IFC_REG_SS_STRAP_GENERIC_3 (32'h5ac) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h5c0) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (32'h1) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_LOW (1) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_MASK (32'h2) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_LOW (2) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (32'h4) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (32'hfffffff8) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h5c4) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (32'h1) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_LOW (1) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_MASK (32'h2) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_LOW (2) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_MASK (32'h4) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_LOW (3) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_MASK (32'h8) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_LOW (4) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_MASK (32'h10) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_LOW (5) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_MASK (32'h20) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_LOW (6) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK (32'h40) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_LOW (7) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (32'h80) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (32'h100) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9) +`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (32'hfffffe00) +`define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h5c8) +`define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h5cc) +`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h5d0) +`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h5d4) +`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h5d8) +`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h5dc) +`define SOC_IFC_REG_INTERNAL_OBF_KEY_0 (32'h600) +`define SOC_IFC_REG_INTERNAL_OBF_KEY_1 (32'h604) +`define SOC_IFC_REG_INTERNAL_OBF_KEY_2 (32'h608) +`define SOC_IFC_REG_INTERNAL_OBF_KEY_3 (32'h60c) +`define SOC_IFC_REG_INTERNAL_OBF_KEY_4 (32'h610) +`define SOC_IFC_REG_INTERNAL_OBF_KEY_5 (32'h614) +`define SOC_IFC_REG_INTERNAL_OBF_KEY_6 (32'h618) +`define SOC_IFC_REG_INTERNAL_OBF_KEY_7 (32'h61c) +`define SOC_IFC_REG_INTERNAL_ICCM_LOCK (32'h620) +`define SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_LOW (0) +`define SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK (32'h1) +`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET (32'h624) +`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_LOW (0) +`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK (32'h1) +`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES (32'h628) +`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_LOW (0) +`define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_MASK (32'hff) +`define SOC_IFC_REG_INTERNAL_NMI_VECTOR (32'h62c) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK (32'h630) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_LOW (0) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK (32'h1) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_LOW (1) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_MASK (32'h2) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_LOW (2) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK (32'h4) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_CRYPTO_ERR_LOW (3) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_CRYPTO_ERR_MASK (32'h8) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK (32'h634) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_LOW (0) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_MASK (32'h1) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_LOW (1) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_MASK (32'h2) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_LOW (2) +`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK (32'h4) +`define SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK (32'h638) +`define SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK (32'h63c) +`define SOC_IFC_REG_INTERNAL_RV_MTIME_L (32'h640) +`define SOC_IFC_REG_INTERNAL_RV_MTIME_H (32'h644) +`define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L (32'h648) +`define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H (32'h64c) +`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) +`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) +`define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INV_DEV_EN_LOW (1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INV_DEV_EN_MASK (32'h2) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_FAIL_EN_LOW (2) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_FAIL_EN_MASK (32'h4) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_BAD_FUSE_EN_LOW (3) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_BAD_FUSE_EN_MASK (32'h8) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_ICCM_BLOCKED_EN_LOW (4) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_ICCM_BLOCKED_EN_MASK (32'h10) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_ECC_UNC_EN_LOW (5) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_ECC_UNC_EN_MASK (32'h20) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_LOW (6) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK (32'h40) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_LOW (7) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK (32'h80) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_LOW (1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_MASK (32'h2) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_LOW (2) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_MASK (32'h4) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_LOW (3) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_MASK (32'h8) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_LOW (4) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK (32'h10) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_LOW (5) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK (32'h20) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_LOW (1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK (32'h2) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_LOW (2) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK (32'h4) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_LOW (3) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK (32'h8) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_LOW (4) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK (32'h10) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_LOW (5) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK (32'h20) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_LOW (6) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK (32'h40) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_LOW (7) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK (32'h80) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_LOW (1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK (32'h2) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_LOW (2) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK (32'h4) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_LOW (3) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK (32'h8) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_LOW (4) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK (32'h10) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_LOW (5) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK (32'h20) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INV_DEV_TRIG_LOW (1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INV_DEV_TRIG_MASK (32'h2) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_FAIL_TRIG_LOW (2) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_FAIL_TRIG_MASK (32'h4) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_BAD_FUSE_TRIG_LOW (3) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_BAD_FUSE_TRIG_MASK (32'h8) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_ICCM_BLOCKED_TRIG_LOW (4) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_ICCM_BLOCKED_TRIG_MASK (32'h10) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_ECC_UNC_TRIG_LOW (5) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_ECC_UNC_TRIG_MASK (32'h20) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER1_TIMEOUT_TRIG_LOW (6) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER1_TIMEOUT_TRIG_MASK (32'h40) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_LOW (7) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_MASK (32'h80) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_MBOX_ECC_COR_TRIG_LOW (1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_MBOX_ECC_COR_TRIG_MASK (32'h2) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_LOW (2) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_MASK (32'h4) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_LOW (3) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_MASK (32'h8) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_LOW (4) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK (32'h10) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_LOW (5) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_MASK (32'h20) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h900) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R (32'h904) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R (32'h908) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R (32'h90c) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R (32'h910) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R (32'h914) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R (32'h918) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R (32'h91c) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R (32'h980) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R (32'h984) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R (32'h988) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R (32'h98c) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R (32'h990) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R (32'h994) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'ha00) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R (32'ha04) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R (32'ha08) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R (32'ha0c) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R (32'ha10) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R (32'ha14) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R (32'ha18) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R (32'ha1c) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R (32'ha20) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R (32'ha24) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R (32'ha28) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R (32'ha2c) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R (32'ha30) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R (32'ha34) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW (0) +`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) + + +`endif \ No newline at end of file diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv index 7e8d32ee1..009f18d24 100755 --- a/src/integration/tb/caliptra_top_tb.sv +++ b/src/integration/tb/caliptra_top_tb.sv @@ -17,6 +17,7 @@ `include "common_defines.sv" `include "config_defines.svh" `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" `include "caliptra_macros.svh" `ifndef VERILATOR diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv index 5581934c6..b0a2ca8c0 100644 --- a/src/integration/tb/caliptra_top_tb_services.sv +++ b/src/integration/tb/caliptra_top_tb_services.sv @@ -31,6 +31,7 @@ `include "common_defines.sv" `include "config_defines.svh" `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" module caliptra_top_tb_services diff --git a/src/integration/tb/caliptra_top_tb_soc_bfm.sv b/src/integration/tb/caliptra_top_tb_soc_bfm.sv index cb6140801..ec53ec4e6 100644 --- a/src/integration/tb/caliptra_top_tb_soc_bfm.sv +++ b/src/integration/tb/caliptra_top_tb_soc_bfm.sv @@ -16,6 +16,7 @@ `include "common_defines.sv" `include "config_defines.svh" `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" `include "caliptra_macros.svh" module caliptra_top_tb_soc_bfm diff --git a/src/sha256/tb/sha256_random_test.sv b/src/sha256/tb/sha256_random_test.sv index b391bfe9f..7edaf5596 100644 --- a/src/sha256/tb/sha256_random_test.sv +++ b/src/sha256/tb/sha256_random_test.sv @@ -23,6 +23,7 @@ `default_nettype none `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" module sha256_random_test(); diff --git a/src/sha512/tb/sha512_ctrl_32bit_tb.sv b/src/sha512/tb/sha512_ctrl_32bit_tb.sv index b62bbb224..839848bd4 100644 --- a/src/sha512/tb/sha512_ctrl_32bit_tb.sv +++ b/src/sha512/tb/sha512_ctrl_32bit_tb.sv @@ -22,6 +22,7 @@ //====================================================================== `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" module sha512_ctrl_32bit_tb import kv_defines_pkg::*; diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index da059b043..83f2e4abc 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -19,592 +19,215 @@ `define CALIPTRA_TOP_REG_BASE_ADDR (32'h0) `define CALIPTRA_TOP_REG_MBOX_CSR_BASE_ADDR (32'h20000) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_LOCK (32'h20000) -`define MBOX_CSR_MBOX_LOCK (32'h0) -`define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) -`define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_USER (32'h20004) -`define MBOX_CSR_MBOX_USER (32'h4) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_CMD (32'h20008) -`define MBOX_CSR_MBOX_CMD (32'h8) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DLEN (32'h2000c) -`define MBOX_CSR_MBOX_DLEN (32'hc) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DATAIN (32'h20010) -`define MBOX_CSR_MBOX_DATAIN (32'h10) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DATAOUT (32'h20014) -`define MBOX_CSR_MBOX_DATAOUT (32'h14) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_EXECUTE (32'h20018) -`define MBOX_CSR_MBOX_EXECUTE (32'h18) -`define MBOX_CSR_MBOX_EXECUTE_EXECUTE_LOW (0) -`define MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK (32'h1) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_STATUS (32'h2001c) -`define MBOX_CSR_MBOX_STATUS (32'h1c) -`define MBOX_CSR_MBOX_STATUS_STATUS_LOW (0) -`define MBOX_CSR_MBOX_STATUS_STATUS_MASK (32'hf) -`define MBOX_CSR_MBOX_STATUS_ECC_SINGLE_ERROR_LOW (4) -`define MBOX_CSR_MBOX_STATUS_ECC_SINGLE_ERROR_MASK (32'h10) -`define MBOX_CSR_MBOX_STATUS_ECC_DOUBLE_ERROR_LOW (5) -`define MBOX_CSR_MBOX_STATUS_ECC_DOUBLE_ERROR_MASK (32'h20) -`define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW (6) -`define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK (32'h1c0) -`define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW (9) -`define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (32'h200) -`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) -`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h3fffc00) `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_UNLOCK (32'h20020) -`define MBOX_CSR_MBOX_UNLOCK (32'h20) -`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) -`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_MBOX_CSR_TAP_MODE (32'h20024) -`define MBOX_CSR_TAP_MODE (32'h24) -`define MBOX_CSR_TAP_MODE_ENABLED_LOW (0) -`define MBOX_CSR_TAP_MODE_ENABLED_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_BASE_ADDR (32'h30000) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (32'h30000) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (32'h0) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK (32'h1) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW (1) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK (32'h2) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW (2) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (32'h4) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (32'h30004) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK (32'h1) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW (1) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK (32'h2) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW (2) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (32'h4) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (32'hfffffff8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (32'h30008) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (32'h8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL (32'h3000c) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL (32'hc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_ENC (32'h30010) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_ENC (32'h10) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_ENC (32'h30014) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_ENC (32'h14) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (32'h30018) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (32'h18) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (32'h3001c) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (32'h1c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (32'h30020) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (32'h20) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (32'h30024) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (32'h24) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (32'h30028) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (32'h28) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (32'h3002c) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (32'h2c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (32'h30030) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (32'h30) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (32'h30034) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (32'h34) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_BOOT_STATUS (32'h30038) -`define GENERIC_AND_FUSE_REG_CPTRA_BOOT_STATUS (32'h38) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS (32'h3003c) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS (32'h3c) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_MASK (32'hffffff) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_LOW (24) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (32'h1000000) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (32'he000000) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (32'h10000000) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (32'h20000000) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK (32'h40000000) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_LOW (31) -`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK (32'h80000000) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON (32'h30040) -`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON (32'h40) -`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_FW_UPD_RESET_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK (32'h1) -`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_WARM_RESET_LOW (1) -`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_WARM_RESET_MASK (32'h2) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE (32'h30044) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE (32'h44) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_MASK (32'h3) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEBUG_LOCKED_LOW (2) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEBUG_LOCKED_MASK (32'h4) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_LOW (3) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) -`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h30048) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h48) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h3004c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h4c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h30050) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h50) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h30054) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h54) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h30058) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h58) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h3005c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h5c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h30060) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h60) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h30064) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h64) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h30068) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h68) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h3006c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h6c) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (32'h30070) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (32'h70) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h30074) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h74) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (32'h30078) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (32'h78) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (32'h3007c) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (32'h7c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_2 (32'h30080) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_2 (32'h80) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_3 (32'h30084) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_3 (32'h84) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_4 (32'h30088) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_4 (32'h88) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_5 (32'h3008c) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_5 (32'h8c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_6 (32'h30090) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_6 (32'h90) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_7 (32'h30094) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_7 (32'h94) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_8 (32'h30098) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_8 (32'h98) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_9 (32'h3009c) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_9 (32'h9c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10 (32'h300a0) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10 (32'ha0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11 (32'h300a4) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11 (32'ha4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL (32'h300a8) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL (32'ha8) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS (32'h300ac) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS (32'hac) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK (32'h1) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW (1) -`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK (32'h2) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE (32'h300b0) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE (32'hb0) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG (32'h300b4) -`define GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG (32'hb4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO (32'h300b8) -`define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO (32'hb8) -`define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG (32'h300bc) -`define GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG (32'hbc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN (32'h300c0) -`define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN (32'hc0) -`define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0 (32'h300c4) -`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0 (32'hc4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1 (32'h300c8) -`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1 (32'hc8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (32'h300cc) -`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (32'hcc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (32'h300d0) -`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (32'hd0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID (32'h300d4) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID (32'hd4) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK (32'hffff) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW (16) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK (32'hffff0000) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0 (32'h300d8) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0 (32'hd8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1 (32'h300dc) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1 (32'hdc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG (32'h300e0) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG (32'he0) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (32'h1) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (32'he) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (32'h20) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'h300e4) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'he4) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL (32'h300e8) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL (32'he8) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'h300ec) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'hec) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'h300f0) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'hf0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN (32'h300f4) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN (32'hf4) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL (32'h300f8) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL (32'hf8) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'h300fc) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'hfc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h30100) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h100) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS (32'h30104) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS (32'h104) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (32'h30108) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (32'h108) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h3010c) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h10c) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (32'h30110) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (32'h110) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (32'h30114) -`define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (32'h114) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (32'h30118) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (32'h118) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK (32'hffff) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW (16) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK (32'hffff0000) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (32'h3011c) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (32'h11c) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK (32'hffff) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW (16) -`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK (32'hffff0000) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 (32'h30120) -`define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 (32'h120) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (32'h30124) -`define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (32'h124) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (32'h30128) -`define GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (32'h128) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (32'h3012c) -`define GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (32'h12c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (32'h30130) -`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (32'h130) -`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (32'h30140) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (32'h140) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (32'h30144) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (32'h144) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (32'h30148) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (32'h148) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (32'h3014c) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (32'h14c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (32'h30150) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (32'h150) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (32'h30154) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (32'h154) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (32'h30158) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (32'h158) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (32'h3015c) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (32'h15c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (32'h30160) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (32'h160) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (32'h30164) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (32'h164) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (32'h30168) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (32'h168) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (32'h3016c) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (32'h16c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h30170) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h170) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0) -`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (32'h30200) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (32'h200) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 (32'h30204) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 (32'h204) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_2 (32'h30208) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_2 (32'h208) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_3 (32'h3020c) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_3 (32'h20c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_4 (32'h30210) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_4 (32'h210) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_5 (32'h30214) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_5 (32'h214) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_6 (32'h30218) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_6 (32'h218) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_7 (32'h3021c) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_7 (32'h21c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_8 (32'h30220) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_8 (32'h220) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_9 (32'h30224) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_9 (32'h224) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_10 (32'h30228) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_10 (32'h228) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_11 (32'h3022c) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_11 (32'h22c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_12 (32'h30230) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_12 (32'h230) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_13 (32'h30234) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_13 (32'h234) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_14 (32'h30238) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_14 (32'h238) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_15 (32'h3023c) -`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_15 (32'h23c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_0 (32'h30240) -`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_0 (32'h240) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_1 (32'h30244) -`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_1 (32'h244) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_2 (32'h30248) -`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_2 (32'h248) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_3 (32'h3024c) -`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_3 (32'h24c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_4 (32'h30250) -`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_4 (32'h250) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_5 (32'h30254) -`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_5 (32'h254) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 (32'h30258) -`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 (32'h258) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (32'h3025c) -`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (32'h25c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (32'h30260) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (32'h260) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (32'h30264) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (32'h264) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (32'h30268) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (32'h268) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (32'h3026c) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (32'h26c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (32'h30270) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (32'h270) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (32'h30274) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (32'h274) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (32'h30278) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (32'h278) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (32'h3027c) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (32'h27c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (32'h30280) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (32'h280) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (32'h30284) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (32'h284) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (32'h30288) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (32'h288) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (32'h3028c) -`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (32'h28c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (32'h30290) -`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (32'h290) -`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) -`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (32'hf) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h302b4) -`define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h302b8) -`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h2b8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (32'h302bc) -`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (32'h2bc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (32'h302c0) -`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (32'h2c0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (32'h302c4) -`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (32'h2c4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h302c8) -`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2c8) -`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0) -`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h302cc) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2cc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h302d0) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2d0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h302d4) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2d4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h302d8) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2d8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h302dc) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2dc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h302e0) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2e0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h302e4) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2e4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h302e8) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2e8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h302ec) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2ec) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h302f0) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h2f0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h302f4) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h2f4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h302f8) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h2f8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h302fc) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h2fc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h30300) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h300) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h30304) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h304) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h30308) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h308) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h3030c) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h30c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h30310) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h310) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h30314) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h314) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h30318) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h318) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h3031c) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h31c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h30320) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h320) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h30324) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h324) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h30328) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h328) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h3032c) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h32c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h30330) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h330) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h30334) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h334) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h30338) -`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h338) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (32'h30340) -`define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (32'h340) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (32'h30344) -`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (32'h344) -`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0) -`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (32'hf) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (32'h30348) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (32'h348) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h3034c) -`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h34c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h30350) -`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h350) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h30354) -`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h30358) -`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (32'h3035c) -`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (32'h35c) -`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) -`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (32'h3) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h30360) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h360) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h30364) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h364) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h30368) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h368) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h3036c) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h36c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h30370) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h370) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) -`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (32'hff) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (32'h30500) -`define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (32'h30504) -`define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (32'h504) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (32'h30508) -`define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (32'h508) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (32'h3050c) -`define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (32'h50c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h30510) -`define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h510) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h30514) -`define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h514) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (32'h30518) -`define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (32'h518) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (32'h3051c) -`define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (32'h51c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (32'h30520) -`define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (32'h520) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (32'h30524) -`define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (32'h524) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h30528) -`define GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h528) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h3052c) -`define GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h52c) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (32'h30530) -`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (32'h530) -`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0) -`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (32'h1) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (32'h305a0) -`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (32'h5a0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (32'h305a4) -`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (32'h5a4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (32'h305a8) -`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (32'h5a8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (32'h305ac) -`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (32'h5ac) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h305c0) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h5c0) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (32'h1) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_LOW (1) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_MASK (32'h2) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_LOW (2) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (32'h4) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (32'hfffffff8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h305c4) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h5c4) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (32'h1) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_LOW (1) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_MASK (32'h2) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_LOW (2) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_MASK (32'h4) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_LOW (3) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_MASK (32'h8) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_LOW (4) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_MASK (32'h10) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_LOW (5) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_MASK (32'h20) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_LOW (6) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK (32'h40) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_LOW (7) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (32'h80) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (32'h100) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9) -`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (32'hfffffe00) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h305c8) -`define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h5c8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h305cc) -`define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h5cc) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h305d0) -`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h5d0) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h305d4) -`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h5d4) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h305d8) -`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h5d8) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h305dc) -`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h5dc) `endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/caliptra_top_reg_field_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_field_defines.svh new file mode 100644 index 000000000..d53601ca4 --- /dev/null +++ b/src/soc_ifc/rtl/caliptra_top_reg_field_defines.svh @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +`ifndef CALIPTRA_TOP_REG_FIELD_DEFINES_HEADER +`define CALIPTRA_TOP_REG_FIELD_DEFINES_HEADER + + +`define MBOX_CSR_MBOX_LOCK (32'h0) +`define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) +`define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) +`define MBOX_CSR_MBOX_USER (32'h4) +`define MBOX_CSR_MBOX_CMD (32'h8) +`define MBOX_CSR_MBOX_DLEN (32'hc) +`define MBOX_CSR_MBOX_DATAIN (32'h10) +`define MBOX_CSR_MBOX_DATAOUT (32'h14) +`define MBOX_CSR_MBOX_EXECUTE (32'h18) +`define MBOX_CSR_MBOX_EXECUTE_EXECUTE_LOW (0) +`define MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK (32'h1) +`define MBOX_CSR_MBOX_STATUS (32'h1c) +`define MBOX_CSR_MBOX_STATUS_STATUS_LOW (0) +`define MBOX_CSR_MBOX_STATUS_STATUS_MASK (32'hf) +`define MBOX_CSR_MBOX_STATUS_ECC_SINGLE_ERROR_LOW (4) +`define MBOX_CSR_MBOX_STATUS_ECC_SINGLE_ERROR_MASK (32'h10) +`define MBOX_CSR_MBOX_STATUS_ECC_DOUBLE_ERROR_LOW (5) +`define MBOX_CSR_MBOX_STATUS_ECC_DOUBLE_ERROR_MASK (32'h20) +`define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW (6) +`define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK (32'h1c0) +`define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW (9) +`define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (32'h200) +`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) +`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h3fffc00) +`define MBOX_CSR_MBOX_UNLOCK (32'h20) +`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) +`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (32'h1) +`define MBOX_CSR_TAP_MODE (32'h24) +`define MBOX_CSR_TAP_MODE_ENABLED_LOW (0) +`define MBOX_CSR_TAP_MODE_ENABLED_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (32'h0) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW (1) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK (32'h2) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW (2) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (32'h4) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW (1) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK (32'h2) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW (2) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (32'h4) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (32'hfffffff8) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (32'h8) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL (32'hc) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_ENC (32'h10) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_ENC (32'h14) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (32'h18) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (32'h1c) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (32'h20) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (32'h24) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (32'h28) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (32'h2c) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (32'h30) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (32'h34) +`define GENERIC_AND_FUSE_REG_CPTRA_BOOT_STATUS (32'h38) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS (32'h3c) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_MASK (32'hffffff) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_LOW (24) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (32'h1000000) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (32'he000000) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (32'h10000000) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (32'h20000000) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK (32'h40000000) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_LOW (31) +`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK (32'h80000000) +`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON (32'h40) +`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_FW_UPD_RESET_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_WARM_RESET_LOW (1) +`define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_WARM_RESET_MASK (32'h2) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE (32'h44) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_MASK (32'h3) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEBUG_LOCKED_LOW (2) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEBUG_LOCKED_MASK (32'h4) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_LOW (3) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) +`define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h48) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h4c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h50) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h54) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h58) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h5c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h60) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h64) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h68) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h6c) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (32'h70) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h74) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (32'h78) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (32'h7c) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_2 (32'h80) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_3 (32'h84) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_4 (32'h88) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_5 (32'h8c) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_6 (32'h90) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_7 (32'h94) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_8 (32'h98) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_9 (32'h9c) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10 (32'ha0) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11 (32'ha4) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL (32'ha8) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS (32'hac) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW (1) +`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK (32'h2) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE (32'hb0) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG (32'hb4) +`define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO (32'hb8) +`define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG (32'hbc) +`define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN (32'hc0) +`define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0 (32'hc4) +`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1 (32'hc8) +`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (32'hcc) +`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (32'hd0) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID (32'hd4) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK (32'hffff) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW (16) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK (32'hffff0000) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0 (32'hd8) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1 (32'hdc) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG (32'he0) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (32'he) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (32'h20) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'he4) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL (32'he8) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'hec) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'hf0) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN (32'hf4) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL (32'hf8) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'hfc) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h100) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS (32'h104) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (32'h108) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h10c) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (32'h110) +`define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (32'h114) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (32'h118) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK (32'hffff) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW (16) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK (32'hffff0000) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (32'h11c) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK (32'hffff) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW (16) +`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK (32'hffff0000) +`define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 (32'h120) +`define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (32'h124) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (32'h128) +`define GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (32'h12c) +`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (32'h130) +`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (32'h140) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (32'h144) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (32'h148) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (32'h14c) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (32'h150) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (32'h154) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (32'h158) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (32'h15c) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (32'h160) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (32'h164) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (32'h168) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (32'h16c) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h170) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0) +`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (32'h200) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 (32'h204) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_2 (32'h208) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_3 (32'h20c) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_4 (32'h210) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_5 (32'h214) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_6 (32'h218) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_7 (32'h21c) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_8 (32'h220) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_9 (32'h224) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_10 (32'h228) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_11 (32'h22c) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_12 (32'h230) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_13 (32'h234) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_14 (32'h238) +`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_15 (32'h23c) +`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_0 (32'h240) +`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_1 (32'h244) +`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_2 (32'h248) +`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_3 (32'h24c) +`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_4 (32'h250) +`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_5 (32'h254) +`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 (32'h258) +`define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (32'h25c) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (32'h260) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (32'h264) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (32'h268) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (32'h26c) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (32'h270) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (32'h274) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (32'h278) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (32'h27c) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (32'h280) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (32'h284) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (32'h288) +`define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (32'h28c) +`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (32'h290) +`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (32'hf) +`define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) +`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h2b8) +`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (32'h2bc) +`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (32'h2c0) +`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (32'h2c4) +`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2c8) +`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2cc) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2d0) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2d4) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2d8) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2dc) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2e0) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2e4) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2e8) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2ec) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h2f0) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h2f4) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h2f8) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h2fc) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h300) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h304) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h308) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h30c) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h310) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h314) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h318) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h31c) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h320) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h324) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h328) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h32c) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h330) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h334) +`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h338) +`define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (32'h340) +`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (32'h344) +`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (32'hf) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (32'h348) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) +`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h34c) +`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h350) +`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354) +`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358) +`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (32'h35c) +`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (32'h3) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h360) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h364) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h368) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h36c) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h370) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) +`define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (32'hff) +`define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500) +`define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (32'h504) +`define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (32'h508) +`define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (32'h50c) +`define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h510) +`define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h514) +`define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (32'h518) +`define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (32'h51c) +`define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (32'h520) +`define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (32'h524) +`define GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h528) +`define GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h52c) +`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (32'h530) +`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0) +`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (32'h5a0) +`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (32'h5a4) +`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (32'h5a8) +`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (32'h5ac) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h5c0) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_LOW (1) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_MASK (32'h2) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_LOW (2) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (32'h4) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (32'hfffffff8) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h5c4) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (32'h1) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_LOW (1) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_MASK (32'h2) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_LOW (2) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_MASK (32'h4) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_LOW (3) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_MASK (32'h8) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_LOW (4) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_MASK (32'h10) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_LOW (5) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_MASK (32'h20) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_LOW (6) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK (32'h40) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_LOW (7) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (32'h80) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (32'h100) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9) +`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (32'hfffffe00) +`define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h5c8) +`define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h5cc) +`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h5d0) +`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h5d4) +`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h5d8) +`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h5dc) + + +`endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv index 0f9c25e77..a1cff81e4 100644 --- a/src/soc_ifc/rtl/soc_ifc_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_pkg.sv @@ -17,6 +17,7 @@ `include "config_defines.svh" `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" package soc_ifc_pkg; diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index ac2ab17a8..e4fac191f 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -15,6 +15,7 @@ `include "caliptra_sva.svh" `include "caliptra_macros.svh" `include "caliptra_reg_defines.svh" +`include "caliptra_reg_field_defines.svh" module soc_ifc_top import soc_ifc_pkg::*; diff --git a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv index bf1e83ff6..6c7116bb3 100644 --- a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv +++ b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv @@ -22,6 +22,7 @@ package soc_ifc_tb_pkg; `include "caliptra_reg_defines.svh" // This is from integration/rtl level + `include "caliptra_reg_field_defines.svh" localparam SOCIFC_BASE = `CLP_SOC_IFC_REG_BASE_ADDR; localparam SHAACC_BASE = `CLP_SHA512_ACC_CSR_BASE_ADDR; diff --git a/tools/scripts/reg_doc_gen.py b/tools/scripts/reg_doc_gen.py index 8e2fe58c3..314b09dfa 100644 --- a/tools/scripts/reg_doc_gen.py +++ b/tools/scripts/reg_doc_gen.py @@ -34,9 +34,11 @@ # Listener block will print register name and address into C Header file class HeaderPrintingListener(RDLListener): - def __init__(self, file_path, filename, ext, tick): + def __init__(self, file_path, filename, ext, tick, do_global=1, do_rel=1): self.regfile_offset = 0 self.tick = tick + self.do_global = do_global + self.do_rel = do_rel self.file_path = file_path header_file_path = os.path.join(self.file_path, filename + ext) self.file = open(header_file_path, 'w') @@ -64,14 +66,16 @@ def enter_Addrmap(self, node): if self.tick == "`": address = address.replace("0x", "32'h", 1) #print the base address of each address map - self.file.write((self.tick + "define " + register_name.upper() + "_BASE_ADDR" + "\t(" + address + ")\n").expandtabs(100)) + if self.do_global == 1: + self.file.write((self.tick + "define " + register_name.upper() + "_BASE_ADDR" + "\t(" + address + ")\n").expandtabs(100)) def enter_Regfile(self, node): self.regfile_offset = node.address_offset register_name = node.get_path("_",'_{index:d}') address = hex(node.absolute_address) if self.tick == "`": address = address.replace("0x", "32'h", 1) - self.file.write((self.tick + "define " + register_name.upper() + "_START" + "\t(" + address + ")\n").expandtabs(100)) + if self.do_global == 1: + self.file.write((self.tick + "define " + register_name.upper() + "_START" + "\t(" + address + ")\n").expandtabs(100)) def exit_Regfile(self, node): self.regfile_offset = 0 def enter_Reg(self, node): @@ -80,39 +84,45 @@ def enter_Reg(self, node): address = hex(node.absolute_address) if self.tick == "`": address = address.replace("0x", "32'h", 1) - self.file.write((self.tick + "define " + register_name.upper() + "\t(" + address + ")\n").expandtabs(100)) + if self.do_global == 1: + self.file.write((self.tick + "define " + register_name.upper() + "\t(" + address + ")\n").expandtabs(100)) #getting and printing the relative address and path for each register (relative to the addr map it belongs to) register_name = node.get_rel_path(self.top_node.parent,"^","_",'_{index:d}') address = hex(node.address_offset + self.regfile_offset) if self.tick == "`": address = address.replace("0x", "32'h", 1) - self.file.write((self.tick + "define " + register_name.upper() + "\t(" + address + ")\n").expandtabs(100)) + if self.do_rel == 1: + self.file.write((self.tick + "define " + register_name.upper() + "\t(" + address + ")\n").expandtabs(100)) def enter_Field(self, node): field_name = node.get_rel_path(self.top_node.parent,"^","_",'_{index:d}') if node.width == 1: field_mask = hex(1 << node.low) if self.tick == "`": field_mask = field_mask.replace("0x", "32'h", 1) - self.file.write((self.tick + "define " + field_name.upper() + "_LOW" + "\t(" + str(node.low) + ")\n").expandtabs(100)) - self.file.write((self.tick + "define " + field_name.upper() + "_MASK" + "\t(" + field_mask + ")\n").expandtabs(100)) + if self.do_rel == 1: + self.file.write((self.tick + "define " + field_name.upper() + "_LOW" + "\t(" + str(node.low) + ")\n").expandtabs(100)) + self.file.write((self.tick + "define " + field_name.upper() + "_MASK" + "\t(" + field_mask + ")\n").expandtabs(100)) elif node.low != 0 or node.high != 31: field_mask = hex(((2 << node.high) - 1) & ~((1 << node.low) -1)) if self.tick == "`": field_mask = field_mask.replace("0x", "32'h", 1) - self.file.write((self.tick + "define " + field_name.upper() + "_LOW" + "\t(" + str(node.low) + ")\n").expandtabs(100)) - self.file.write((self.tick + "define " + field_name.upper() + "_MASK" + "\t(" + field_mask + ")\n").expandtabs(100)) + if self.do_rel == 1: + self.file.write((self.tick + "define " + field_name.upper() + "_LOW" + "\t(" + str(node.low) + ")\n").expandtabs(100)) + self.file.write((self.tick + "define " + field_name.upper() + "_MASK" + "\t(" + field_mask + ")\n").expandtabs(100)) def enter_Mem(self, node): #getting and printing the absolute address and path for each register mem_name = node.get_path("_",'_{index:d}') address = hex(node.absolute_address) if self.tick == "`": address = address.replace("0x", "32'h", 1) - self.file.write((self.tick + "define " + mem_name.upper() + "_BASE_ADDR" + "\t(" + address + ")\n").expandtabs(100)) + if self.do_global == 1: + self.file.write((self.tick + "define " + mem_name.upper() + "_BASE_ADDR" + "\t(" + address + ")\n").expandtabs(100)) #getting and printing the end address for the memory address = hex(node.absolute_address + node.size - 1) if self.tick == "`": address = address.replace("0x", "32'h", 1) - self.file.write((self.tick + "define " + mem_name.upper() + "_END_ADDR" + "\t(" + address + ")\n").expandtabs(100)) + if self.do_global == 1: + self.file.write((self.tick + "define " + mem_name.upper() + "_END_ADDR" + "\t(" + address + ")\n").expandtabs(100)) #list of address map files to compile @@ -153,7 +163,11 @@ def enter_Mem(self, node): walker.walk(root, listener) listener.file.write("\n\n#endif") listener.file.close() - listener = HeaderPrintingListener(rtl_output_dir, filename + "_defines", ".svh", "`") + listener = HeaderPrintingListener(rtl_output_dir, filename + "_defines", ".svh", "`", 1, 0) + walker.walk(root, listener) + listener.file.write("\n\n`endif") + listener.file.close() + listener = HeaderPrintingListener(rtl_output_dir, filename + "_field_defines", ".svh", "`", 0, 1) walker.walk(root, listener) listener.file.write("\n\n`endif") listener.file.close() From 17444a34012ec04fd119c0ceef0f44fcfc7f5843 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 17 Jan 2025 09:44:50 -0800 Subject: [PATCH 6/9] Protect relative reg offset macros with ifndef/endif --- src/integration/rtl/caliptra_reg.h | 4312 +++++++++++++++++ .../rtl/caliptra_reg_field_defines.svh | 4312 +++++++++++++++++ src/soc_ifc/rtl/caliptra_top_reg.h | 418 ++ .../rtl/caliptra_top_reg_field_defines.svh | 418 ++ tools/scripts/reg_doc_gen.py | 4 + 5 files changed, 9464 insertions(+) diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index f2e26ec37..baed881b0 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -19,20 +19,31 @@ #define CLP_BASE_ADDR (0x0) #define CLP_DOE_REG_BASE_ADDR (0x10000000) #define CLP_DOE_REG_DOE_IV_0 (0x10000000) +#ifndef DOE_REG_DOE_IV_0 #define DOE_REG_DOE_IV_0 (0x0) +#endif #define CLP_DOE_REG_DOE_IV_1 (0x10000004) +#ifndef DOE_REG_DOE_IV_1 #define DOE_REG_DOE_IV_1 (0x4) +#endif #define CLP_DOE_REG_DOE_IV_2 (0x10000008) +#ifndef DOE_REG_DOE_IV_2 #define DOE_REG_DOE_IV_2 (0x8) +#endif #define CLP_DOE_REG_DOE_IV_3 (0x1000000c) +#ifndef DOE_REG_DOE_IV_3 #define DOE_REG_DOE_IV_3 (0xc) +#endif #define CLP_DOE_REG_DOE_CTRL (0x10000010) +#ifndef DOE_REG_DOE_CTRL #define DOE_REG_DOE_CTRL (0x10) #define DOE_REG_DOE_CTRL_CMD_LOW (0) #define DOE_REG_DOE_CTRL_CMD_MASK (0x3) #define DOE_REG_DOE_CTRL_DEST_LOW (2) #define DOE_REG_DOE_CTRL_DEST_MASK (0x7c) +#endif #define CLP_DOE_REG_DOE_STATUS (0x10000014) +#ifndef DOE_REG_DOE_STATUS #define DOE_REG_DOE_STATUS (0x14) #define DOE_REG_DOE_STATUS_READY_LOW (0) #define DOE_REG_DOE_STATUS_READY_MASK (0x1) @@ -44,14 +55,18 @@ #define DOE_REG_DOE_STATUS_FE_FLOW_DONE_MASK (0x8) #define DOE_REG_DOE_STATUS_DEOBF_SECRETS_CLEARED_LOW (4) #define DOE_REG_DOE_STATUS_DEOBF_SECRETS_CLEARED_MASK (0x10) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_START (0x10000800) #define CLP_DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x10000800) +#ifndef DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x10000804) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (0x1) @@ -61,19 +76,27 @@ #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (0x4) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (0x8) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x10000808) +#ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x1000080c) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x10000810) +#ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x10000814) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (0x1) @@ -83,11 +106,15 @@ #define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (0x4) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (0x8) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x10000818) +#ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x1000081c) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (0x1) @@ -97,50 +124,82 @@ #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (0x4) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) #define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (0x8) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x10000820) +#ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) #define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x10000900) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R #define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x900) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x10000904) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R #define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x904) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x10000908) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R #define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x908) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x1000090c) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R #define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x90c) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x10000980) +#ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R #define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x980) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0x10000a00) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R #define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0xa00) #define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) #define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0x10000a04) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R #define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0xa04) #define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) #define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0x10000a08) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R #define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0xa08) #define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) #define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0x10000a0c) +#ifndef DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R #define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0xa0c) #define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) #define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x10000a10) +#ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R #define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa10) #define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_ECC_REG_BASE_ADDR (0x10008000) #define CLP_ECC_REG_ECC_NAME_0 (0x10008000) +#ifndef ECC_REG_ECC_NAME_0 #define ECC_REG_ECC_NAME_0 (0x0) +#endif #define CLP_ECC_REG_ECC_NAME_1 (0x10008004) +#ifndef ECC_REG_ECC_NAME_1 #define ECC_REG_ECC_NAME_1 (0x4) +#endif #define CLP_ECC_REG_ECC_VERSION_0 (0x10008008) +#ifndef ECC_REG_ECC_VERSION_0 #define ECC_REG_ECC_VERSION_0 (0x8) +#endif #define CLP_ECC_REG_ECC_VERSION_1 (0x1000800c) +#ifndef ECC_REG_ECC_VERSION_1 #define ECC_REG_ECC_VERSION_1 (0xc) +#endif #define CLP_ECC_REG_ECC_CTRL (0x10008010) +#ifndef ECC_REG_ECC_CTRL #define ECC_REG_ECC_CTRL (0x10) #define ECC_REG_ECC_CTRL_CTRL_LOW (0) #define ECC_REG_ECC_CTRL_CTRL_MASK (0x3) @@ -150,301 +209,593 @@ #define ECC_REG_ECC_CTRL_PCR_SIGN_MASK (0x8) #define ECC_REG_ECC_CTRL_DH_SHAREDKEY_LOW (4) #define ECC_REG_ECC_CTRL_DH_SHAREDKEY_MASK (0x10) +#endif #define CLP_ECC_REG_ECC_STATUS (0x10008018) +#ifndef ECC_REG_ECC_STATUS #define ECC_REG_ECC_STATUS (0x18) #define ECC_REG_ECC_STATUS_READY_LOW (0) #define ECC_REG_ECC_STATUS_READY_MASK (0x1) #define ECC_REG_ECC_STATUS_VALID_LOW (1) #define ECC_REG_ECC_STATUS_VALID_MASK (0x2) +#endif #define CLP_ECC_REG_ECC_SEED_0 (0x10008080) +#ifndef ECC_REG_ECC_SEED_0 #define ECC_REG_ECC_SEED_0 (0x80) +#endif #define CLP_ECC_REG_ECC_SEED_1 (0x10008084) +#ifndef ECC_REG_ECC_SEED_1 #define ECC_REG_ECC_SEED_1 (0x84) +#endif #define CLP_ECC_REG_ECC_SEED_2 (0x10008088) +#ifndef ECC_REG_ECC_SEED_2 #define ECC_REG_ECC_SEED_2 (0x88) +#endif #define CLP_ECC_REG_ECC_SEED_3 (0x1000808c) +#ifndef ECC_REG_ECC_SEED_3 #define ECC_REG_ECC_SEED_3 (0x8c) +#endif #define CLP_ECC_REG_ECC_SEED_4 (0x10008090) +#ifndef ECC_REG_ECC_SEED_4 #define ECC_REG_ECC_SEED_4 (0x90) +#endif #define CLP_ECC_REG_ECC_SEED_5 (0x10008094) +#ifndef ECC_REG_ECC_SEED_5 #define ECC_REG_ECC_SEED_5 (0x94) +#endif #define CLP_ECC_REG_ECC_SEED_6 (0x10008098) +#ifndef ECC_REG_ECC_SEED_6 #define ECC_REG_ECC_SEED_6 (0x98) +#endif #define CLP_ECC_REG_ECC_SEED_7 (0x1000809c) +#ifndef ECC_REG_ECC_SEED_7 #define ECC_REG_ECC_SEED_7 (0x9c) +#endif #define CLP_ECC_REG_ECC_SEED_8 (0x100080a0) +#ifndef ECC_REG_ECC_SEED_8 #define ECC_REG_ECC_SEED_8 (0xa0) +#endif #define CLP_ECC_REG_ECC_SEED_9 (0x100080a4) +#ifndef ECC_REG_ECC_SEED_9 #define ECC_REG_ECC_SEED_9 (0xa4) +#endif #define CLP_ECC_REG_ECC_SEED_10 (0x100080a8) +#ifndef ECC_REG_ECC_SEED_10 #define ECC_REG_ECC_SEED_10 (0xa8) +#endif #define CLP_ECC_REG_ECC_SEED_11 (0x100080ac) +#ifndef ECC_REG_ECC_SEED_11 #define ECC_REG_ECC_SEED_11 (0xac) +#endif #define CLP_ECC_REG_ECC_MSG_0 (0x10008100) +#ifndef ECC_REG_ECC_MSG_0 #define ECC_REG_ECC_MSG_0 (0x100) +#endif #define CLP_ECC_REG_ECC_MSG_1 (0x10008104) +#ifndef ECC_REG_ECC_MSG_1 #define ECC_REG_ECC_MSG_1 (0x104) +#endif #define CLP_ECC_REG_ECC_MSG_2 (0x10008108) +#ifndef ECC_REG_ECC_MSG_2 #define ECC_REG_ECC_MSG_2 (0x108) +#endif #define CLP_ECC_REG_ECC_MSG_3 (0x1000810c) +#ifndef ECC_REG_ECC_MSG_3 #define ECC_REG_ECC_MSG_3 (0x10c) +#endif #define CLP_ECC_REG_ECC_MSG_4 (0x10008110) +#ifndef ECC_REG_ECC_MSG_4 #define ECC_REG_ECC_MSG_4 (0x110) +#endif #define CLP_ECC_REG_ECC_MSG_5 (0x10008114) +#ifndef ECC_REG_ECC_MSG_5 #define ECC_REG_ECC_MSG_5 (0x114) +#endif #define CLP_ECC_REG_ECC_MSG_6 (0x10008118) +#ifndef ECC_REG_ECC_MSG_6 #define ECC_REG_ECC_MSG_6 (0x118) +#endif #define CLP_ECC_REG_ECC_MSG_7 (0x1000811c) +#ifndef ECC_REG_ECC_MSG_7 #define ECC_REG_ECC_MSG_7 (0x11c) +#endif #define CLP_ECC_REG_ECC_MSG_8 (0x10008120) +#ifndef ECC_REG_ECC_MSG_8 #define ECC_REG_ECC_MSG_8 (0x120) +#endif #define CLP_ECC_REG_ECC_MSG_9 (0x10008124) +#ifndef ECC_REG_ECC_MSG_9 #define ECC_REG_ECC_MSG_9 (0x124) +#endif #define CLP_ECC_REG_ECC_MSG_10 (0x10008128) +#ifndef ECC_REG_ECC_MSG_10 #define ECC_REG_ECC_MSG_10 (0x128) +#endif #define CLP_ECC_REG_ECC_MSG_11 (0x1000812c) +#ifndef ECC_REG_ECC_MSG_11 #define ECC_REG_ECC_MSG_11 (0x12c) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_0 (0x10008180) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_0 #define ECC_REG_ECC_PRIVKEY_OUT_0 (0x180) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_1 (0x10008184) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_1 #define ECC_REG_ECC_PRIVKEY_OUT_1 (0x184) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_2 (0x10008188) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_2 #define ECC_REG_ECC_PRIVKEY_OUT_2 (0x188) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_3 (0x1000818c) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_3 #define ECC_REG_ECC_PRIVKEY_OUT_3 (0x18c) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_4 (0x10008190) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_4 #define ECC_REG_ECC_PRIVKEY_OUT_4 (0x190) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_5 (0x10008194) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_5 #define ECC_REG_ECC_PRIVKEY_OUT_5 (0x194) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_6 (0x10008198) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_6 #define ECC_REG_ECC_PRIVKEY_OUT_6 (0x198) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_7 (0x1000819c) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_7 #define ECC_REG_ECC_PRIVKEY_OUT_7 (0x19c) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_8 (0x100081a0) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_8 #define ECC_REG_ECC_PRIVKEY_OUT_8 (0x1a0) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_9 (0x100081a4) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_9 #define ECC_REG_ECC_PRIVKEY_OUT_9 (0x1a4) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_10 (0x100081a8) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_10 #define ECC_REG_ECC_PRIVKEY_OUT_10 (0x1a8) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_OUT_11 (0x100081ac) +#ifndef ECC_REG_ECC_PRIVKEY_OUT_11 #define ECC_REG_ECC_PRIVKEY_OUT_11 (0x1ac) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_0 (0x10008200) +#ifndef ECC_REG_ECC_PUBKEY_X_0 #define ECC_REG_ECC_PUBKEY_X_0 (0x200) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_1 (0x10008204) +#ifndef ECC_REG_ECC_PUBKEY_X_1 #define ECC_REG_ECC_PUBKEY_X_1 (0x204) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_2 (0x10008208) +#ifndef ECC_REG_ECC_PUBKEY_X_2 #define ECC_REG_ECC_PUBKEY_X_2 (0x208) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_3 (0x1000820c) +#ifndef ECC_REG_ECC_PUBKEY_X_3 #define ECC_REG_ECC_PUBKEY_X_3 (0x20c) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_4 (0x10008210) +#ifndef ECC_REG_ECC_PUBKEY_X_4 #define ECC_REG_ECC_PUBKEY_X_4 (0x210) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_5 (0x10008214) +#ifndef ECC_REG_ECC_PUBKEY_X_5 #define ECC_REG_ECC_PUBKEY_X_5 (0x214) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_6 (0x10008218) +#ifndef ECC_REG_ECC_PUBKEY_X_6 #define ECC_REG_ECC_PUBKEY_X_6 (0x218) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_7 (0x1000821c) +#ifndef ECC_REG_ECC_PUBKEY_X_7 #define ECC_REG_ECC_PUBKEY_X_7 (0x21c) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_8 (0x10008220) +#ifndef ECC_REG_ECC_PUBKEY_X_8 #define ECC_REG_ECC_PUBKEY_X_8 (0x220) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_9 (0x10008224) +#ifndef ECC_REG_ECC_PUBKEY_X_9 #define ECC_REG_ECC_PUBKEY_X_9 (0x224) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_10 (0x10008228) +#ifndef ECC_REG_ECC_PUBKEY_X_10 #define ECC_REG_ECC_PUBKEY_X_10 (0x228) +#endif #define CLP_ECC_REG_ECC_PUBKEY_X_11 (0x1000822c) +#ifndef ECC_REG_ECC_PUBKEY_X_11 #define ECC_REG_ECC_PUBKEY_X_11 (0x22c) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_0 (0x10008280) +#ifndef ECC_REG_ECC_PUBKEY_Y_0 #define ECC_REG_ECC_PUBKEY_Y_0 (0x280) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_1 (0x10008284) +#ifndef ECC_REG_ECC_PUBKEY_Y_1 #define ECC_REG_ECC_PUBKEY_Y_1 (0x284) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_2 (0x10008288) +#ifndef ECC_REG_ECC_PUBKEY_Y_2 #define ECC_REG_ECC_PUBKEY_Y_2 (0x288) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_3 (0x1000828c) +#ifndef ECC_REG_ECC_PUBKEY_Y_3 #define ECC_REG_ECC_PUBKEY_Y_3 (0x28c) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_4 (0x10008290) +#ifndef ECC_REG_ECC_PUBKEY_Y_4 #define ECC_REG_ECC_PUBKEY_Y_4 (0x290) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_5 (0x10008294) +#ifndef ECC_REG_ECC_PUBKEY_Y_5 #define ECC_REG_ECC_PUBKEY_Y_5 (0x294) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_6 (0x10008298) +#ifndef ECC_REG_ECC_PUBKEY_Y_6 #define ECC_REG_ECC_PUBKEY_Y_6 (0x298) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_7 (0x1000829c) +#ifndef ECC_REG_ECC_PUBKEY_Y_7 #define ECC_REG_ECC_PUBKEY_Y_7 (0x29c) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_8 (0x100082a0) +#ifndef ECC_REG_ECC_PUBKEY_Y_8 #define ECC_REG_ECC_PUBKEY_Y_8 (0x2a0) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_9 (0x100082a4) +#ifndef ECC_REG_ECC_PUBKEY_Y_9 #define ECC_REG_ECC_PUBKEY_Y_9 (0x2a4) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_10 (0x100082a8) +#ifndef ECC_REG_ECC_PUBKEY_Y_10 #define ECC_REG_ECC_PUBKEY_Y_10 (0x2a8) +#endif #define CLP_ECC_REG_ECC_PUBKEY_Y_11 (0x100082ac) +#ifndef ECC_REG_ECC_PUBKEY_Y_11 #define ECC_REG_ECC_PUBKEY_Y_11 (0x2ac) +#endif #define CLP_ECC_REG_ECC_SIGN_R_0 (0x10008300) +#ifndef ECC_REG_ECC_SIGN_R_0 #define ECC_REG_ECC_SIGN_R_0 (0x300) +#endif #define CLP_ECC_REG_ECC_SIGN_R_1 (0x10008304) +#ifndef ECC_REG_ECC_SIGN_R_1 #define ECC_REG_ECC_SIGN_R_1 (0x304) +#endif #define CLP_ECC_REG_ECC_SIGN_R_2 (0x10008308) +#ifndef ECC_REG_ECC_SIGN_R_2 #define ECC_REG_ECC_SIGN_R_2 (0x308) +#endif #define CLP_ECC_REG_ECC_SIGN_R_3 (0x1000830c) +#ifndef ECC_REG_ECC_SIGN_R_3 #define ECC_REG_ECC_SIGN_R_3 (0x30c) +#endif #define CLP_ECC_REG_ECC_SIGN_R_4 (0x10008310) +#ifndef ECC_REG_ECC_SIGN_R_4 #define ECC_REG_ECC_SIGN_R_4 (0x310) +#endif #define CLP_ECC_REG_ECC_SIGN_R_5 (0x10008314) +#ifndef ECC_REG_ECC_SIGN_R_5 #define ECC_REG_ECC_SIGN_R_5 (0x314) +#endif #define CLP_ECC_REG_ECC_SIGN_R_6 (0x10008318) +#ifndef ECC_REG_ECC_SIGN_R_6 #define ECC_REG_ECC_SIGN_R_6 (0x318) +#endif #define CLP_ECC_REG_ECC_SIGN_R_7 (0x1000831c) +#ifndef ECC_REG_ECC_SIGN_R_7 #define ECC_REG_ECC_SIGN_R_7 (0x31c) +#endif #define CLP_ECC_REG_ECC_SIGN_R_8 (0x10008320) +#ifndef ECC_REG_ECC_SIGN_R_8 #define ECC_REG_ECC_SIGN_R_8 (0x320) +#endif #define CLP_ECC_REG_ECC_SIGN_R_9 (0x10008324) +#ifndef ECC_REG_ECC_SIGN_R_9 #define ECC_REG_ECC_SIGN_R_9 (0x324) +#endif #define CLP_ECC_REG_ECC_SIGN_R_10 (0x10008328) +#ifndef ECC_REG_ECC_SIGN_R_10 #define ECC_REG_ECC_SIGN_R_10 (0x328) +#endif #define CLP_ECC_REG_ECC_SIGN_R_11 (0x1000832c) +#ifndef ECC_REG_ECC_SIGN_R_11 #define ECC_REG_ECC_SIGN_R_11 (0x32c) +#endif #define CLP_ECC_REG_ECC_SIGN_S_0 (0x10008380) +#ifndef ECC_REG_ECC_SIGN_S_0 #define ECC_REG_ECC_SIGN_S_0 (0x380) +#endif #define CLP_ECC_REG_ECC_SIGN_S_1 (0x10008384) +#ifndef ECC_REG_ECC_SIGN_S_1 #define ECC_REG_ECC_SIGN_S_1 (0x384) +#endif #define CLP_ECC_REG_ECC_SIGN_S_2 (0x10008388) +#ifndef ECC_REG_ECC_SIGN_S_2 #define ECC_REG_ECC_SIGN_S_2 (0x388) +#endif #define CLP_ECC_REG_ECC_SIGN_S_3 (0x1000838c) +#ifndef ECC_REG_ECC_SIGN_S_3 #define ECC_REG_ECC_SIGN_S_3 (0x38c) +#endif #define CLP_ECC_REG_ECC_SIGN_S_4 (0x10008390) +#ifndef ECC_REG_ECC_SIGN_S_4 #define ECC_REG_ECC_SIGN_S_4 (0x390) +#endif #define CLP_ECC_REG_ECC_SIGN_S_5 (0x10008394) +#ifndef ECC_REG_ECC_SIGN_S_5 #define ECC_REG_ECC_SIGN_S_5 (0x394) +#endif #define CLP_ECC_REG_ECC_SIGN_S_6 (0x10008398) +#ifndef ECC_REG_ECC_SIGN_S_6 #define ECC_REG_ECC_SIGN_S_6 (0x398) +#endif #define CLP_ECC_REG_ECC_SIGN_S_7 (0x1000839c) +#ifndef ECC_REG_ECC_SIGN_S_7 #define ECC_REG_ECC_SIGN_S_7 (0x39c) +#endif #define CLP_ECC_REG_ECC_SIGN_S_8 (0x100083a0) +#ifndef ECC_REG_ECC_SIGN_S_8 #define ECC_REG_ECC_SIGN_S_8 (0x3a0) +#endif #define CLP_ECC_REG_ECC_SIGN_S_9 (0x100083a4) +#ifndef ECC_REG_ECC_SIGN_S_9 #define ECC_REG_ECC_SIGN_S_9 (0x3a4) +#endif #define CLP_ECC_REG_ECC_SIGN_S_10 (0x100083a8) +#ifndef ECC_REG_ECC_SIGN_S_10 #define ECC_REG_ECC_SIGN_S_10 (0x3a8) +#endif #define CLP_ECC_REG_ECC_SIGN_S_11 (0x100083ac) +#ifndef ECC_REG_ECC_SIGN_S_11 #define ECC_REG_ECC_SIGN_S_11 (0x3ac) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_0 (0x10008400) +#ifndef ECC_REG_ECC_VERIFY_R_0 #define ECC_REG_ECC_VERIFY_R_0 (0x400) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_1 (0x10008404) +#ifndef ECC_REG_ECC_VERIFY_R_1 #define ECC_REG_ECC_VERIFY_R_1 (0x404) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_2 (0x10008408) +#ifndef ECC_REG_ECC_VERIFY_R_2 #define ECC_REG_ECC_VERIFY_R_2 (0x408) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_3 (0x1000840c) +#ifndef ECC_REG_ECC_VERIFY_R_3 #define ECC_REG_ECC_VERIFY_R_3 (0x40c) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_4 (0x10008410) +#ifndef ECC_REG_ECC_VERIFY_R_4 #define ECC_REG_ECC_VERIFY_R_4 (0x410) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_5 (0x10008414) +#ifndef ECC_REG_ECC_VERIFY_R_5 #define ECC_REG_ECC_VERIFY_R_5 (0x414) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_6 (0x10008418) +#ifndef ECC_REG_ECC_VERIFY_R_6 #define ECC_REG_ECC_VERIFY_R_6 (0x418) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_7 (0x1000841c) +#ifndef ECC_REG_ECC_VERIFY_R_7 #define ECC_REG_ECC_VERIFY_R_7 (0x41c) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_8 (0x10008420) +#ifndef ECC_REG_ECC_VERIFY_R_8 #define ECC_REG_ECC_VERIFY_R_8 (0x420) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_9 (0x10008424) +#ifndef ECC_REG_ECC_VERIFY_R_9 #define ECC_REG_ECC_VERIFY_R_9 (0x424) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_10 (0x10008428) +#ifndef ECC_REG_ECC_VERIFY_R_10 #define ECC_REG_ECC_VERIFY_R_10 (0x428) +#endif #define CLP_ECC_REG_ECC_VERIFY_R_11 (0x1000842c) +#ifndef ECC_REG_ECC_VERIFY_R_11 #define ECC_REG_ECC_VERIFY_R_11 (0x42c) +#endif #define CLP_ECC_REG_ECC_IV_0 (0x10008480) +#ifndef ECC_REG_ECC_IV_0 #define ECC_REG_ECC_IV_0 (0x480) +#endif #define CLP_ECC_REG_ECC_IV_1 (0x10008484) +#ifndef ECC_REG_ECC_IV_1 #define ECC_REG_ECC_IV_1 (0x484) +#endif #define CLP_ECC_REG_ECC_IV_2 (0x10008488) +#ifndef ECC_REG_ECC_IV_2 #define ECC_REG_ECC_IV_2 (0x488) +#endif #define CLP_ECC_REG_ECC_IV_3 (0x1000848c) +#ifndef ECC_REG_ECC_IV_3 #define ECC_REG_ECC_IV_3 (0x48c) +#endif #define CLP_ECC_REG_ECC_IV_4 (0x10008490) +#ifndef ECC_REG_ECC_IV_4 #define ECC_REG_ECC_IV_4 (0x490) +#endif #define CLP_ECC_REG_ECC_IV_5 (0x10008494) +#ifndef ECC_REG_ECC_IV_5 #define ECC_REG_ECC_IV_5 (0x494) +#endif #define CLP_ECC_REG_ECC_IV_6 (0x10008498) +#ifndef ECC_REG_ECC_IV_6 #define ECC_REG_ECC_IV_6 (0x498) +#endif #define CLP_ECC_REG_ECC_IV_7 (0x1000849c) +#ifndef ECC_REG_ECC_IV_7 #define ECC_REG_ECC_IV_7 (0x49c) +#endif #define CLP_ECC_REG_ECC_IV_8 (0x100084a0) +#ifndef ECC_REG_ECC_IV_8 #define ECC_REG_ECC_IV_8 (0x4a0) +#endif #define CLP_ECC_REG_ECC_IV_9 (0x100084a4) +#ifndef ECC_REG_ECC_IV_9 #define ECC_REG_ECC_IV_9 (0x4a4) +#endif #define CLP_ECC_REG_ECC_IV_10 (0x100084a8) +#ifndef ECC_REG_ECC_IV_10 #define ECC_REG_ECC_IV_10 (0x4a8) +#endif #define CLP_ECC_REG_ECC_IV_11 (0x100084ac) +#ifndef ECC_REG_ECC_IV_11 #define ECC_REG_ECC_IV_11 (0x4ac) +#endif #define CLP_ECC_REG_ECC_NONCE_0 (0x10008500) +#ifndef ECC_REG_ECC_NONCE_0 #define ECC_REG_ECC_NONCE_0 (0x500) +#endif #define CLP_ECC_REG_ECC_NONCE_1 (0x10008504) +#ifndef ECC_REG_ECC_NONCE_1 #define ECC_REG_ECC_NONCE_1 (0x504) +#endif #define CLP_ECC_REG_ECC_NONCE_2 (0x10008508) +#ifndef ECC_REG_ECC_NONCE_2 #define ECC_REG_ECC_NONCE_2 (0x508) +#endif #define CLP_ECC_REG_ECC_NONCE_3 (0x1000850c) +#ifndef ECC_REG_ECC_NONCE_3 #define ECC_REG_ECC_NONCE_3 (0x50c) +#endif #define CLP_ECC_REG_ECC_NONCE_4 (0x10008510) +#ifndef ECC_REG_ECC_NONCE_4 #define ECC_REG_ECC_NONCE_4 (0x510) +#endif #define CLP_ECC_REG_ECC_NONCE_5 (0x10008514) +#ifndef ECC_REG_ECC_NONCE_5 #define ECC_REG_ECC_NONCE_5 (0x514) +#endif #define CLP_ECC_REG_ECC_NONCE_6 (0x10008518) +#ifndef ECC_REG_ECC_NONCE_6 #define ECC_REG_ECC_NONCE_6 (0x518) +#endif #define CLP_ECC_REG_ECC_NONCE_7 (0x1000851c) +#ifndef ECC_REG_ECC_NONCE_7 #define ECC_REG_ECC_NONCE_7 (0x51c) +#endif #define CLP_ECC_REG_ECC_NONCE_8 (0x10008520) +#ifndef ECC_REG_ECC_NONCE_8 #define ECC_REG_ECC_NONCE_8 (0x520) +#endif #define CLP_ECC_REG_ECC_NONCE_9 (0x10008524) +#ifndef ECC_REG_ECC_NONCE_9 #define ECC_REG_ECC_NONCE_9 (0x524) +#endif #define CLP_ECC_REG_ECC_NONCE_10 (0x10008528) +#ifndef ECC_REG_ECC_NONCE_10 #define ECC_REG_ECC_NONCE_10 (0x528) +#endif #define CLP_ECC_REG_ECC_NONCE_11 (0x1000852c) +#ifndef ECC_REG_ECC_NONCE_11 #define ECC_REG_ECC_NONCE_11 (0x52c) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_0 (0x10008580) +#ifndef ECC_REG_ECC_PRIVKEY_IN_0 #define ECC_REG_ECC_PRIVKEY_IN_0 (0x580) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_1 (0x10008584) +#ifndef ECC_REG_ECC_PRIVKEY_IN_1 #define ECC_REG_ECC_PRIVKEY_IN_1 (0x584) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_2 (0x10008588) +#ifndef ECC_REG_ECC_PRIVKEY_IN_2 #define ECC_REG_ECC_PRIVKEY_IN_2 (0x588) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_3 (0x1000858c) +#ifndef ECC_REG_ECC_PRIVKEY_IN_3 #define ECC_REG_ECC_PRIVKEY_IN_3 (0x58c) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_4 (0x10008590) +#ifndef ECC_REG_ECC_PRIVKEY_IN_4 #define ECC_REG_ECC_PRIVKEY_IN_4 (0x590) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_5 (0x10008594) +#ifndef ECC_REG_ECC_PRIVKEY_IN_5 #define ECC_REG_ECC_PRIVKEY_IN_5 (0x594) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_6 (0x10008598) +#ifndef ECC_REG_ECC_PRIVKEY_IN_6 #define ECC_REG_ECC_PRIVKEY_IN_6 (0x598) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_7 (0x1000859c) +#ifndef ECC_REG_ECC_PRIVKEY_IN_7 #define ECC_REG_ECC_PRIVKEY_IN_7 (0x59c) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_8 (0x100085a0) +#ifndef ECC_REG_ECC_PRIVKEY_IN_8 #define ECC_REG_ECC_PRIVKEY_IN_8 (0x5a0) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_9 (0x100085a4) +#ifndef ECC_REG_ECC_PRIVKEY_IN_9 #define ECC_REG_ECC_PRIVKEY_IN_9 (0x5a4) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_10 (0x100085a8) +#ifndef ECC_REG_ECC_PRIVKEY_IN_10 #define ECC_REG_ECC_PRIVKEY_IN_10 (0x5a8) +#endif #define CLP_ECC_REG_ECC_PRIVKEY_IN_11 (0x100085ac) +#ifndef ECC_REG_ECC_PRIVKEY_IN_11 #define ECC_REG_ECC_PRIVKEY_IN_11 (0x5ac) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_0 (0x100085c0) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_0 #define ECC_REG_ECC_DH_SHARED_KEY_0 (0x5c0) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_1 (0x100085c4) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_1 #define ECC_REG_ECC_DH_SHARED_KEY_1 (0x5c4) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_2 (0x100085c8) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_2 #define ECC_REG_ECC_DH_SHARED_KEY_2 (0x5c8) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_3 (0x100085cc) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_3 #define ECC_REG_ECC_DH_SHARED_KEY_3 (0x5cc) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_4 (0x100085d0) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_4 #define ECC_REG_ECC_DH_SHARED_KEY_4 (0x5d0) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_5 (0x100085d4) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_5 #define ECC_REG_ECC_DH_SHARED_KEY_5 (0x5d4) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_6 (0x100085d8) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_6 #define ECC_REG_ECC_DH_SHARED_KEY_6 (0x5d8) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_7 (0x100085dc) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_7 #define ECC_REG_ECC_DH_SHARED_KEY_7 (0x5dc) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_8 (0x100085e0) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_8 #define ECC_REG_ECC_DH_SHARED_KEY_8 (0x5e0) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_9 (0x100085e4) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_9 #define ECC_REG_ECC_DH_SHARED_KEY_9 (0x5e4) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_10 (0x100085e8) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_10 #define ECC_REG_ECC_DH_SHARED_KEY_10 (0x5e8) +#endif #define CLP_ECC_REG_ECC_DH_SHARED_KEY_11 (0x100085ec) +#ifndef ECC_REG_ECC_DH_SHARED_KEY_11 #define ECC_REG_ECC_DH_SHARED_KEY_11 (0x5ec) +#endif #define CLP_ECC_REG_ECC_KV_RD_PKEY_CTRL (0x10008600) +#ifndef ECC_REG_ECC_KV_RD_PKEY_CTRL #define ECC_REG_ECC_KV_RD_PKEY_CTRL (0x600) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_LOW (0) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_MASK (0x1) @@ -454,7 +805,9 @@ #define ECC_REG_ECC_KV_RD_PKEY_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_LOW (7) #define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_MASK (0xffffff80) +#endif #define CLP_ECC_REG_ECC_KV_RD_PKEY_STATUS (0x10008604) +#ifndef ECC_REG_ECC_KV_RD_PKEY_STATUS #define ECC_REG_ECC_KV_RD_PKEY_STATUS (0x604) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_LOW (0) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_MASK (0x1) @@ -462,7 +815,9 @@ #define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_MASK (0x2) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_LOW (2) #define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_ECC_REG_ECC_KV_RD_SEED_CTRL (0x10008608) +#ifndef ECC_REG_ECC_KV_RD_SEED_CTRL #define ECC_REG_ECC_KV_RD_SEED_CTRL (0x608) #define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_LOW (0) #define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_MASK (0x1) @@ -472,7 +827,9 @@ #define ECC_REG_ECC_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_LOW (7) #define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_MASK (0xffffff80) +#endif #define CLP_ECC_REG_ECC_KV_RD_SEED_STATUS (0x1000860c) +#ifndef ECC_REG_ECC_KV_RD_SEED_STATUS #define ECC_REG_ECC_KV_RD_SEED_STATUS (0x60c) #define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_LOW (0) #define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_MASK (0x1) @@ -480,7 +837,9 @@ #define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_MASK (0x2) #define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_LOW (2) #define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_ECC_REG_ECC_KV_WR_PKEY_CTRL (0x10008610) +#ifndef ECC_REG_ECC_KV_WR_PKEY_CTRL #define ECC_REG_ECC_KV_WR_PKEY_CTRL (0x610) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_LOW (0) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_MASK (0x1) @@ -500,7 +859,9 @@ #define ECC_REG_ECC_KV_WR_PKEY_CTRL_AES_KEY_DEST_VALID_MASK (0x800) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_LOW (12) #define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_MASK (0xfffff000) +#endif #define CLP_ECC_REG_ECC_KV_WR_PKEY_STATUS (0x10008614) +#ifndef ECC_REG_ECC_KV_WR_PKEY_STATUS #define ECC_REG_ECC_KV_WR_PKEY_STATUS (0x614) #define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_LOW (0) #define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_MASK (0x1) @@ -508,67 +869,103 @@ #define ECC_REG_ECC_KV_WR_PKEY_STATUS_VALID_MASK (0x2) #define ECC_REG_ECC_KV_WR_PKEY_STATUS_ERROR_LOW (2) #define ECC_REG_ECC_KV_WR_PKEY_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_START (0x10008800) #define CLP_ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x10008800) +#ifndef ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x10008804) +#ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) #define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x10008808) +#ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x1000880c) +#ifndef ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x10008810) +#ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x10008814) +#ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) #define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x10008818) +#ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x1000881c) +#ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) #define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x10008820) +#ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) #define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (0x10008900) +#ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R #define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (0x900) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x10008980) +#ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R #define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x980) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (0x10008a00) +#ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R #define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (0xa00) #define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) #define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x10008a04) +#ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R #define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa04) #define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_HMAC_REG_BASE_ADDR (0x10010000) #define CLP_HMAC_REG_HMAC512_NAME_0 (0x10010000) +#ifndef HMAC_REG_HMAC512_NAME_0 #define HMAC_REG_HMAC512_NAME_0 (0x0) +#endif #define CLP_HMAC_REG_HMAC512_NAME_1 (0x10010004) +#ifndef HMAC_REG_HMAC512_NAME_1 #define HMAC_REG_HMAC512_NAME_1 (0x4) +#endif #define CLP_HMAC_REG_HMAC512_VERSION_0 (0x10010008) +#ifndef HMAC_REG_HMAC512_VERSION_0 #define HMAC_REG_HMAC512_VERSION_0 (0x8) +#endif #define CLP_HMAC_REG_HMAC512_VERSION_1 (0x1001000c) +#ifndef HMAC_REG_HMAC512_VERSION_1 #define HMAC_REG_HMAC512_VERSION_1 (0xc) +#endif #define CLP_HMAC_REG_HMAC512_CTRL (0x10010010) +#ifndef HMAC_REG_HMAC512_CTRL #define HMAC_REG_HMAC512_CTRL (0x10) #define HMAC_REG_HMAC512_CTRL_INIT_LOW (0) #define HMAC_REG_HMAC512_CTRL_INIT_MASK (0x1) @@ -582,165 +979,321 @@ #define HMAC_REG_HMAC512_CTRL_CSR_MODE_MASK (0x10) #define HMAC_REG_HMAC512_CTRL_RESERVED_LOW (5) #define HMAC_REG_HMAC512_CTRL_RESERVED_MASK (0x20) +#endif #define CLP_HMAC_REG_HMAC512_STATUS (0x10010018) +#ifndef HMAC_REG_HMAC512_STATUS #define HMAC_REG_HMAC512_STATUS (0x18) #define HMAC_REG_HMAC512_STATUS_READY_LOW (0) #define HMAC_REG_HMAC512_STATUS_READY_MASK (0x1) #define HMAC_REG_HMAC512_STATUS_VALID_LOW (1) #define HMAC_REG_HMAC512_STATUS_VALID_MASK (0x2) +#endif #define CLP_HMAC_REG_HMAC512_KEY_0 (0x10010040) +#ifndef HMAC_REG_HMAC512_KEY_0 #define HMAC_REG_HMAC512_KEY_0 (0x40) +#endif #define CLP_HMAC_REG_HMAC512_KEY_1 (0x10010044) +#ifndef HMAC_REG_HMAC512_KEY_1 #define HMAC_REG_HMAC512_KEY_1 (0x44) +#endif #define CLP_HMAC_REG_HMAC512_KEY_2 (0x10010048) +#ifndef HMAC_REG_HMAC512_KEY_2 #define HMAC_REG_HMAC512_KEY_2 (0x48) +#endif #define CLP_HMAC_REG_HMAC512_KEY_3 (0x1001004c) +#ifndef HMAC_REG_HMAC512_KEY_3 #define HMAC_REG_HMAC512_KEY_3 (0x4c) +#endif #define CLP_HMAC_REG_HMAC512_KEY_4 (0x10010050) +#ifndef HMAC_REG_HMAC512_KEY_4 #define HMAC_REG_HMAC512_KEY_4 (0x50) +#endif #define CLP_HMAC_REG_HMAC512_KEY_5 (0x10010054) +#ifndef HMAC_REG_HMAC512_KEY_5 #define HMAC_REG_HMAC512_KEY_5 (0x54) +#endif #define CLP_HMAC_REG_HMAC512_KEY_6 (0x10010058) +#ifndef HMAC_REG_HMAC512_KEY_6 #define HMAC_REG_HMAC512_KEY_6 (0x58) +#endif #define CLP_HMAC_REG_HMAC512_KEY_7 (0x1001005c) +#ifndef HMAC_REG_HMAC512_KEY_7 #define HMAC_REG_HMAC512_KEY_7 (0x5c) +#endif #define CLP_HMAC_REG_HMAC512_KEY_8 (0x10010060) +#ifndef HMAC_REG_HMAC512_KEY_8 #define HMAC_REG_HMAC512_KEY_8 (0x60) +#endif #define CLP_HMAC_REG_HMAC512_KEY_9 (0x10010064) +#ifndef HMAC_REG_HMAC512_KEY_9 #define HMAC_REG_HMAC512_KEY_9 (0x64) +#endif #define CLP_HMAC_REG_HMAC512_KEY_10 (0x10010068) +#ifndef HMAC_REG_HMAC512_KEY_10 #define HMAC_REG_HMAC512_KEY_10 (0x68) +#endif #define CLP_HMAC_REG_HMAC512_KEY_11 (0x1001006c) +#ifndef HMAC_REG_HMAC512_KEY_11 #define HMAC_REG_HMAC512_KEY_11 (0x6c) +#endif #define CLP_HMAC_REG_HMAC512_KEY_12 (0x10010070) +#ifndef HMAC_REG_HMAC512_KEY_12 #define HMAC_REG_HMAC512_KEY_12 (0x70) +#endif #define CLP_HMAC_REG_HMAC512_KEY_13 (0x10010074) +#ifndef HMAC_REG_HMAC512_KEY_13 #define HMAC_REG_HMAC512_KEY_13 (0x74) +#endif #define CLP_HMAC_REG_HMAC512_KEY_14 (0x10010078) +#ifndef HMAC_REG_HMAC512_KEY_14 #define HMAC_REG_HMAC512_KEY_14 (0x78) +#endif #define CLP_HMAC_REG_HMAC512_KEY_15 (0x1001007c) +#ifndef HMAC_REG_HMAC512_KEY_15 #define HMAC_REG_HMAC512_KEY_15 (0x7c) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_0 (0x10010080) +#ifndef HMAC_REG_HMAC512_BLOCK_0 #define HMAC_REG_HMAC512_BLOCK_0 (0x80) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_1 (0x10010084) +#ifndef HMAC_REG_HMAC512_BLOCK_1 #define HMAC_REG_HMAC512_BLOCK_1 (0x84) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_2 (0x10010088) +#ifndef HMAC_REG_HMAC512_BLOCK_2 #define HMAC_REG_HMAC512_BLOCK_2 (0x88) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_3 (0x1001008c) +#ifndef HMAC_REG_HMAC512_BLOCK_3 #define HMAC_REG_HMAC512_BLOCK_3 (0x8c) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_4 (0x10010090) +#ifndef HMAC_REG_HMAC512_BLOCK_4 #define HMAC_REG_HMAC512_BLOCK_4 (0x90) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_5 (0x10010094) +#ifndef HMAC_REG_HMAC512_BLOCK_5 #define HMAC_REG_HMAC512_BLOCK_5 (0x94) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_6 (0x10010098) +#ifndef HMAC_REG_HMAC512_BLOCK_6 #define HMAC_REG_HMAC512_BLOCK_6 (0x98) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_7 (0x1001009c) +#ifndef HMAC_REG_HMAC512_BLOCK_7 #define HMAC_REG_HMAC512_BLOCK_7 (0x9c) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_8 (0x100100a0) +#ifndef HMAC_REG_HMAC512_BLOCK_8 #define HMAC_REG_HMAC512_BLOCK_8 (0xa0) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_9 (0x100100a4) +#ifndef HMAC_REG_HMAC512_BLOCK_9 #define HMAC_REG_HMAC512_BLOCK_9 (0xa4) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_10 (0x100100a8) +#ifndef HMAC_REG_HMAC512_BLOCK_10 #define HMAC_REG_HMAC512_BLOCK_10 (0xa8) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_11 (0x100100ac) +#ifndef HMAC_REG_HMAC512_BLOCK_11 #define HMAC_REG_HMAC512_BLOCK_11 (0xac) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_12 (0x100100b0) +#ifndef HMAC_REG_HMAC512_BLOCK_12 #define HMAC_REG_HMAC512_BLOCK_12 (0xb0) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_13 (0x100100b4) +#ifndef HMAC_REG_HMAC512_BLOCK_13 #define HMAC_REG_HMAC512_BLOCK_13 (0xb4) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_14 (0x100100b8) +#ifndef HMAC_REG_HMAC512_BLOCK_14 #define HMAC_REG_HMAC512_BLOCK_14 (0xb8) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_15 (0x100100bc) +#ifndef HMAC_REG_HMAC512_BLOCK_15 #define HMAC_REG_HMAC512_BLOCK_15 (0xbc) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_16 (0x100100c0) +#ifndef HMAC_REG_HMAC512_BLOCK_16 #define HMAC_REG_HMAC512_BLOCK_16 (0xc0) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_17 (0x100100c4) +#ifndef HMAC_REG_HMAC512_BLOCK_17 #define HMAC_REG_HMAC512_BLOCK_17 (0xc4) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_18 (0x100100c8) +#ifndef HMAC_REG_HMAC512_BLOCK_18 #define HMAC_REG_HMAC512_BLOCK_18 (0xc8) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_19 (0x100100cc) +#ifndef HMAC_REG_HMAC512_BLOCK_19 #define HMAC_REG_HMAC512_BLOCK_19 (0xcc) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_20 (0x100100d0) +#ifndef HMAC_REG_HMAC512_BLOCK_20 #define HMAC_REG_HMAC512_BLOCK_20 (0xd0) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_21 (0x100100d4) +#ifndef HMAC_REG_HMAC512_BLOCK_21 #define HMAC_REG_HMAC512_BLOCK_21 (0xd4) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_22 (0x100100d8) +#ifndef HMAC_REG_HMAC512_BLOCK_22 #define HMAC_REG_HMAC512_BLOCK_22 (0xd8) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_23 (0x100100dc) +#ifndef HMAC_REG_HMAC512_BLOCK_23 #define HMAC_REG_HMAC512_BLOCK_23 (0xdc) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_24 (0x100100e0) +#ifndef HMAC_REG_HMAC512_BLOCK_24 #define HMAC_REG_HMAC512_BLOCK_24 (0xe0) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_25 (0x100100e4) +#ifndef HMAC_REG_HMAC512_BLOCK_25 #define HMAC_REG_HMAC512_BLOCK_25 (0xe4) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_26 (0x100100e8) +#ifndef HMAC_REG_HMAC512_BLOCK_26 #define HMAC_REG_HMAC512_BLOCK_26 (0xe8) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_27 (0x100100ec) +#ifndef HMAC_REG_HMAC512_BLOCK_27 #define HMAC_REG_HMAC512_BLOCK_27 (0xec) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_28 (0x100100f0) +#ifndef HMAC_REG_HMAC512_BLOCK_28 #define HMAC_REG_HMAC512_BLOCK_28 (0xf0) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_29 (0x100100f4) +#ifndef HMAC_REG_HMAC512_BLOCK_29 #define HMAC_REG_HMAC512_BLOCK_29 (0xf4) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_30 (0x100100f8) +#ifndef HMAC_REG_HMAC512_BLOCK_30 #define HMAC_REG_HMAC512_BLOCK_30 (0xf8) +#endif #define CLP_HMAC_REG_HMAC512_BLOCK_31 (0x100100fc) +#ifndef HMAC_REG_HMAC512_BLOCK_31 #define HMAC_REG_HMAC512_BLOCK_31 (0xfc) +#endif #define CLP_HMAC_REG_HMAC512_TAG_0 (0x10010100) +#ifndef HMAC_REG_HMAC512_TAG_0 #define HMAC_REG_HMAC512_TAG_0 (0x100) +#endif #define CLP_HMAC_REG_HMAC512_TAG_1 (0x10010104) +#ifndef HMAC_REG_HMAC512_TAG_1 #define HMAC_REG_HMAC512_TAG_1 (0x104) +#endif #define CLP_HMAC_REG_HMAC512_TAG_2 (0x10010108) +#ifndef HMAC_REG_HMAC512_TAG_2 #define HMAC_REG_HMAC512_TAG_2 (0x108) +#endif #define CLP_HMAC_REG_HMAC512_TAG_3 (0x1001010c) +#ifndef HMAC_REG_HMAC512_TAG_3 #define HMAC_REG_HMAC512_TAG_3 (0x10c) +#endif #define CLP_HMAC_REG_HMAC512_TAG_4 (0x10010110) +#ifndef HMAC_REG_HMAC512_TAG_4 #define HMAC_REG_HMAC512_TAG_4 (0x110) +#endif #define CLP_HMAC_REG_HMAC512_TAG_5 (0x10010114) +#ifndef HMAC_REG_HMAC512_TAG_5 #define HMAC_REG_HMAC512_TAG_5 (0x114) +#endif #define CLP_HMAC_REG_HMAC512_TAG_6 (0x10010118) +#ifndef HMAC_REG_HMAC512_TAG_6 #define HMAC_REG_HMAC512_TAG_6 (0x118) +#endif #define CLP_HMAC_REG_HMAC512_TAG_7 (0x1001011c) +#ifndef HMAC_REG_HMAC512_TAG_7 #define HMAC_REG_HMAC512_TAG_7 (0x11c) +#endif #define CLP_HMAC_REG_HMAC512_TAG_8 (0x10010120) +#ifndef HMAC_REG_HMAC512_TAG_8 #define HMAC_REG_HMAC512_TAG_8 (0x120) +#endif #define CLP_HMAC_REG_HMAC512_TAG_9 (0x10010124) +#ifndef HMAC_REG_HMAC512_TAG_9 #define HMAC_REG_HMAC512_TAG_9 (0x124) +#endif #define CLP_HMAC_REG_HMAC512_TAG_10 (0x10010128) +#ifndef HMAC_REG_HMAC512_TAG_10 #define HMAC_REG_HMAC512_TAG_10 (0x128) +#endif #define CLP_HMAC_REG_HMAC512_TAG_11 (0x1001012c) +#ifndef HMAC_REG_HMAC512_TAG_11 #define HMAC_REG_HMAC512_TAG_11 (0x12c) +#endif #define CLP_HMAC_REG_HMAC512_TAG_12 (0x10010130) +#ifndef HMAC_REG_HMAC512_TAG_12 #define HMAC_REG_HMAC512_TAG_12 (0x130) +#endif #define CLP_HMAC_REG_HMAC512_TAG_13 (0x10010134) +#ifndef HMAC_REG_HMAC512_TAG_13 #define HMAC_REG_HMAC512_TAG_13 (0x134) +#endif #define CLP_HMAC_REG_HMAC512_TAG_14 (0x10010138) +#ifndef HMAC_REG_HMAC512_TAG_14 #define HMAC_REG_HMAC512_TAG_14 (0x138) +#endif #define CLP_HMAC_REG_HMAC512_TAG_15 (0x1001013c) +#ifndef HMAC_REG_HMAC512_TAG_15 #define HMAC_REG_HMAC512_TAG_15 (0x13c) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_0 (0x10010140) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_0 #define HMAC_REG_HMAC512_LFSR_SEED_0 (0x140) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_1 (0x10010144) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_1 #define HMAC_REG_HMAC512_LFSR_SEED_1 (0x144) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_2 (0x10010148) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_2 #define HMAC_REG_HMAC512_LFSR_SEED_2 (0x148) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_3 (0x1001014c) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_3 #define HMAC_REG_HMAC512_LFSR_SEED_3 (0x14c) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_4 (0x10010150) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_4 #define HMAC_REG_HMAC512_LFSR_SEED_4 (0x150) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_5 (0x10010154) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_5 #define HMAC_REG_HMAC512_LFSR_SEED_5 (0x154) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_6 (0x10010158) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_6 #define HMAC_REG_HMAC512_LFSR_SEED_6 (0x158) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_7 (0x1001015c) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_7 #define HMAC_REG_HMAC512_LFSR_SEED_7 (0x15c) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_8 (0x10010160) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_8 #define HMAC_REG_HMAC512_LFSR_SEED_8 (0x160) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_9 (0x10010164) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_9 #define HMAC_REG_HMAC512_LFSR_SEED_9 (0x164) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_10 (0x10010168) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_10 #define HMAC_REG_HMAC512_LFSR_SEED_10 (0x168) +#endif #define CLP_HMAC_REG_HMAC512_LFSR_SEED_11 (0x1001016c) +#ifndef HMAC_REG_HMAC512_LFSR_SEED_11 #define HMAC_REG_HMAC512_LFSR_SEED_11 (0x16c) +#endif #define CLP_HMAC_REG_HMAC512_KV_RD_KEY_CTRL (0x10010600) +#ifndef HMAC_REG_HMAC512_KV_RD_KEY_CTRL #define HMAC_REG_HMAC512_KV_RD_KEY_CTRL (0x600) #define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_LOW (0) #define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_MASK (0x1) @@ -750,7 +1303,9 @@ #define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_RSVD_LOW (7) #define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_RSVD_MASK (0xffffff80) +#endif #define CLP_HMAC_REG_HMAC512_KV_RD_KEY_STATUS (0x10010604) +#ifndef HMAC_REG_HMAC512_KV_RD_KEY_STATUS #define HMAC_REG_HMAC512_KV_RD_KEY_STATUS (0x604) #define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_READY_LOW (0) #define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_READY_MASK (0x1) @@ -758,7 +1313,9 @@ #define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_VALID_MASK (0x2) #define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_ERROR_LOW (2) #define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL (0x10010608) +#ifndef HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL #define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL (0x608) #define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_EN_LOW (0) #define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_EN_MASK (0x1) @@ -768,7 +1325,9 @@ #define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_RSVD_LOW (7) #define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_RSVD_MASK (0xffffff80) +#endif #define CLP_HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS (0x1001060c) +#ifndef HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS #define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS (0x60c) #define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_READY_LOW (0) #define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_READY_MASK (0x1) @@ -776,7 +1335,9 @@ #define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_VALID_MASK (0x2) #define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_ERROR_LOW (2) #define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_HMAC_REG_HMAC512_KV_WR_CTRL (0x10010610) +#ifndef HMAC_REG_HMAC512_KV_WR_CTRL #define HMAC_REG_HMAC512_KV_WR_CTRL (0x610) #define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_EN_LOW (0) #define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_EN_MASK (0x1) @@ -796,7 +1357,9 @@ #define HMAC_REG_HMAC512_KV_WR_CTRL_AES_KEY_DEST_VALID_MASK (0x800) #define HMAC_REG_HMAC512_KV_WR_CTRL_RSVD_LOW (12) #define HMAC_REG_HMAC512_KV_WR_CTRL_RSVD_MASK (0xfffff000) +#endif #define CLP_HMAC_REG_HMAC512_KV_WR_STATUS (0x10010614) +#ifndef HMAC_REG_HMAC512_KV_WR_STATUS #define HMAC_REG_HMAC512_KV_WR_STATUS (0x614) #define HMAC_REG_HMAC512_KV_WR_STATUS_READY_LOW (0) #define HMAC_REG_HMAC512_KV_WR_STATUS_READY_MASK (0x1) @@ -804,14 +1367,18 @@ #define HMAC_REG_HMAC512_KV_WR_STATUS_VALID_MASK (0x2) #define HMAC_REG_HMAC512_KV_WR_STATUS_ERROR_LOW (2) #define HMAC_REG_HMAC512_KV_WR_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_START (0x10010800) #define CLP_HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x10010800) +#ifndef HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x10010804) +#ifndef HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_MODE_ERROR_EN_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_MODE_ERROR_EN_MASK (0x1) @@ -821,19 +1388,27 @@ #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (0x4) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (0x8) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x10010808) +#ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x1001080c) +#ifndef HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x10010810) +#ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x10010814) +#ifndef HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_MODE_ERROR_STS_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_MODE_ERROR_STS_MASK (0x1) @@ -843,11 +1418,15 @@ #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (0x4) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (0x8) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x10010818) +#ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x1001081c) +#ifndef HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_MODE_ERROR_TRIG_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_MODE_ERROR_TRIG_MASK (0x1) @@ -857,98 +1436,178 @@ #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (0x4) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) #define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (0x8) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x10010820) +#ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_R (0x10010900) +#ifndef HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_R #define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_R (0x900) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_R (0x10010904) +#ifndef HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_R #define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_R (0x904) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x10010908) +#ifndef HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R #define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x908) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x1001090c) +#ifndef HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R #define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x90c) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x10010980) +#ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R #define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x980) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R (0x10010a00) +#ifndef HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R #define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R (0xa00) #define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R_PULSE_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R (0x10010a04) +#ifndef HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R #define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R (0xa04) #define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R_PULSE_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0x10010a08) +#ifndef HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R #define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0xa08) #define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0x10010a0c) +#ifndef HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R #define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0xa0c) #define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x10010a10) +#ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R #define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa10) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AES_REG_BASE_ADDR (0x10011000) #define CLP_AES_REG_KEY_SHARE0_0 (0x10011004) +#ifndef AES_REG_KEY_SHARE0_0 #define AES_REG_KEY_SHARE0_0 (0x4) +#endif #define CLP_AES_REG_KEY_SHARE0_1 (0x10011008) +#ifndef AES_REG_KEY_SHARE0_1 #define AES_REG_KEY_SHARE0_1 (0x8) +#endif #define CLP_AES_REG_KEY_SHARE0_2 (0x1001100c) +#ifndef AES_REG_KEY_SHARE0_2 #define AES_REG_KEY_SHARE0_2 (0xc) +#endif #define CLP_AES_REG_KEY_SHARE0_3 (0x10011010) +#ifndef AES_REG_KEY_SHARE0_3 #define AES_REG_KEY_SHARE0_3 (0x10) +#endif #define CLP_AES_REG_KEY_SHARE0_4 (0x10011014) +#ifndef AES_REG_KEY_SHARE0_4 #define AES_REG_KEY_SHARE0_4 (0x14) +#endif #define CLP_AES_REG_KEY_SHARE0_5 (0x10011018) +#ifndef AES_REG_KEY_SHARE0_5 #define AES_REG_KEY_SHARE0_5 (0x18) +#endif #define CLP_AES_REG_KEY_SHARE0_6 (0x1001101c) +#ifndef AES_REG_KEY_SHARE0_6 #define AES_REG_KEY_SHARE0_6 (0x1c) +#endif #define CLP_AES_REG_KEY_SHARE0_7 (0x10011020) +#ifndef AES_REG_KEY_SHARE0_7 #define AES_REG_KEY_SHARE0_7 (0x20) +#endif #define CLP_AES_REG_KEY_SHARE1_0 (0x10011024) +#ifndef AES_REG_KEY_SHARE1_0 #define AES_REG_KEY_SHARE1_0 (0x24) +#endif #define CLP_AES_REG_KEY_SHARE1_1 (0x10011028) +#ifndef AES_REG_KEY_SHARE1_1 #define AES_REG_KEY_SHARE1_1 (0x28) +#endif #define CLP_AES_REG_KEY_SHARE1_2 (0x1001102c) +#ifndef AES_REG_KEY_SHARE1_2 #define AES_REG_KEY_SHARE1_2 (0x2c) +#endif #define CLP_AES_REG_KEY_SHARE1_3 (0x10011030) +#ifndef AES_REG_KEY_SHARE1_3 #define AES_REG_KEY_SHARE1_3 (0x30) +#endif #define CLP_AES_REG_KEY_SHARE1_4 (0x10011034) +#ifndef AES_REG_KEY_SHARE1_4 #define AES_REG_KEY_SHARE1_4 (0x34) +#endif #define CLP_AES_REG_KEY_SHARE1_5 (0x10011038) +#ifndef AES_REG_KEY_SHARE1_5 #define AES_REG_KEY_SHARE1_5 (0x38) +#endif #define CLP_AES_REG_KEY_SHARE1_6 (0x1001103c) +#ifndef AES_REG_KEY_SHARE1_6 #define AES_REG_KEY_SHARE1_6 (0x3c) +#endif #define CLP_AES_REG_KEY_SHARE1_7 (0x10011040) +#ifndef AES_REG_KEY_SHARE1_7 #define AES_REG_KEY_SHARE1_7 (0x40) +#endif #define CLP_AES_REG_IV_0 (0x10011044) +#ifndef AES_REG_IV_0 #define AES_REG_IV_0 (0x44) +#endif #define CLP_AES_REG_IV_1 (0x10011048) +#ifndef AES_REG_IV_1 #define AES_REG_IV_1 (0x48) +#endif #define CLP_AES_REG_IV_2 (0x1001104c) +#ifndef AES_REG_IV_2 #define AES_REG_IV_2 (0x4c) +#endif #define CLP_AES_REG_IV_3 (0x10011050) +#ifndef AES_REG_IV_3 #define AES_REG_IV_3 (0x50) +#endif #define CLP_AES_REG_DATA_IN_0 (0x10011054) +#ifndef AES_REG_DATA_IN_0 #define AES_REG_DATA_IN_0 (0x54) +#endif #define CLP_AES_REG_DATA_IN_1 (0x10011058) +#ifndef AES_REG_DATA_IN_1 #define AES_REG_DATA_IN_1 (0x58) +#endif #define CLP_AES_REG_DATA_IN_2 (0x1001105c) +#ifndef AES_REG_DATA_IN_2 #define AES_REG_DATA_IN_2 (0x5c) +#endif #define CLP_AES_REG_DATA_IN_3 (0x10011060) +#ifndef AES_REG_DATA_IN_3 #define AES_REG_DATA_IN_3 (0x60) +#endif #define CLP_AES_REG_DATA_OUT_0 (0x10011064) +#ifndef AES_REG_DATA_OUT_0 #define AES_REG_DATA_OUT_0 (0x64) +#endif #define CLP_AES_REG_DATA_OUT_1 (0x10011068) +#ifndef AES_REG_DATA_OUT_1 #define AES_REG_DATA_OUT_1 (0x68) +#endif #define CLP_AES_REG_DATA_OUT_2 (0x1001106c) +#ifndef AES_REG_DATA_OUT_2 #define AES_REG_DATA_OUT_2 (0x6c) +#endif #define CLP_AES_REG_DATA_OUT_3 (0x10011070) +#ifndef AES_REG_DATA_OUT_3 #define AES_REG_DATA_OUT_3 (0x70) +#endif #define CLP_AES_REG_CTRL_SHADOWED (0x10011074) +#ifndef AES_REG_CTRL_SHADOWED #define AES_REG_CTRL_SHADOWED (0x74) #define AES_REG_CTRL_SHADOWED_OPERATION_LOW (0) #define AES_REG_CTRL_SHADOWED_OPERATION_MASK (0x3) @@ -962,17 +1621,23 @@ #define AES_REG_CTRL_SHADOWED_PRNG_RESEED_RATE_MASK (0x7000) #define AES_REG_CTRL_SHADOWED_MANUAL_OPERATION_LOW (15) #define AES_REG_CTRL_SHADOWED_MANUAL_OPERATION_MASK (0x8000) +#endif #define CLP_AES_REG_CTRL_AUX_SHADOWED (0x10011078) +#ifndef AES_REG_CTRL_AUX_SHADOWED #define AES_REG_CTRL_AUX_SHADOWED (0x78) #define AES_REG_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_LOW (0) #define AES_REG_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_MASK (0x1) #define AES_REG_CTRL_AUX_SHADOWED_FORCE_MASKS_LOW (1) #define AES_REG_CTRL_AUX_SHADOWED_FORCE_MASKS_MASK (0x2) +#endif #define CLP_AES_REG_CTRL_AUX_REGWEN (0x1001107c) +#ifndef AES_REG_CTRL_AUX_REGWEN #define AES_REG_CTRL_AUX_REGWEN (0x7c) #define AES_REG_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_LOW (0) #define AES_REG_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_MASK (0x1) +#endif #define CLP_AES_REG_TRIGGER (0x10011080) +#ifndef AES_REG_TRIGGER #define AES_REG_TRIGGER (0x80) #define AES_REG_TRIGGER_START_LOW (0) #define AES_REG_TRIGGER_START_MASK (0x1) @@ -982,7 +1647,9 @@ #define AES_REG_TRIGGER_DATA_OUT_CLEAR_MASK (0x4) #define AES_REG_TRIGGER_PRNG_RESEED_LOW (3) #define AES_REG_TRIGGER_PRNG_RESEED_MASK (0x8) +#endif #define CLP_AES_REG_STATUS (0x10011084) +#ifndef AES_REG_STATUS #define AES_REG_STATUS (0x84) #define AES_REG_STATUS_IDLE_LOW (0) #define AES_REG_STATUS_IDLE_MASK (0x1) @@ -998,22 +1665,34 @@ #define AES_REG_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK (0x20) #define AES_REG_STATUS_ALERT_FATAL_FAULT_LOW (6) #define AES_REG_STATUS_ALERT_FATAL_FAULT_MASK (0x40) +#endif #define CLP_AES_REG_CTRL_GCM_SHADOWED (0x10011088) +#ifndef AES_REG_CTRL_GCM_SHADOWED #define AES_REG_CTRL_GCM_SHADOWED (0x88) #define AES_REG_CTRL_GCM_SHADOWED_PHASE_LOW (0) #define AES_REG_CTRL_GCM_SHADOWED_PHASE_MASK (0x3f) #define AES_REG_CTRL_GCM_SHADOWED_NUM_VALID_BYTES_LOW (6) #define AES_REG_CTRL_GCM_SHADOWED_NUM_VALID_BYTES_MASK (0x7c0) +#endif #define CLP_AES_CLP_REG_BASE_ADDR (0x10011100) #define CLP_AES_CLP_REG_AES_NAME_0 (0x10011200) +#ifndef AES_CLP_REG_AES_NAME_0 #define AES_CLP_REG_AES_NAME_0 (0x100) +#endif #define CLP_AES_CLP_REG_AES_NAME_1 (0x10011204) +#ifndef AES_CLP_REG_AES_NAME_1 #define AES_CLP_REG_AES_NAME_1 (0x104) +#endif #define CLP_AES_CLP_REG_AES_VERSION_0 (0x10011208) +#ifndef AES_CLP_REG_AES_VERSION_0 #define AES_CLP_REG_AES_VERSION_0 (0x108) +#endif #define CLP_AES_CLP_REG_AES_VERSION_1 (0x1001120c) +#ifndef AES_CLP_REG_AES_VERSION_1 #define AES_CLP_REG_AES_VERSION_1 (0x10c) +#endif #define CLP_AES_CLP_REG_AES_KV_RD_KEY_CTRL (0x10011700) +#ifndef AES_CLP_REG_AES_KV_RD_KEY_CTRL #define AES_CLP_REG_AES_KV_RD_KEY_CTRL (0x600) #define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_EN_LOW (0) #define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_EN_MASK (0x1) @@ -1023,7 +1702,9 @@ #define AES_CLP_REG_AES_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define AES_CLP_REG_AES_KV_RD_KEY_CTRL_RSVD_LOW (7) #define AES_CLP_REG_AES_KV_RD_KEY_CTRL_RSVD_MASK (0xffffff80) +#endif #define CLP_AES_CLP_REG_AES_KV_RD_KEY_STATUS (0x10011704) +#ifndef AES_CLP_REG_AES_KV_RD_KEY_STATUS #define AES_CLP_REG_AES_KV_RD_KEY_STATUS (0x604) #define AES_CLP_REG_AES_KV_RD_KEY_STATUS_READY_LOW (0) #define AES_CLP_REG_AES_KV_RD_KEY_STATUS_READY_MASK (0x1) @@ -1031,14 +1712,18 @@ #define AES_CLP_REG_AES_KV_RD_KEY_STATUS_VALID_MASK (0x2) #define AES_CLP_REG_AES_KV_RD_KEY_STATUS_ERROR_LOW (2) #define AES_CLP_REG_AES_KV_RD_KEY_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_START (0x10011900) #define CLP_AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x10011900) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x10011904) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (0x1) @@ -1048,19 +1733,27 @@ #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (0x4) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (0x8) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x10011908) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x1001190c) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x10011910) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x10011914) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (0x1) @@ -1070,11 +1763,15 @@ #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (0x4) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (0x8) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x10011918) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x1001191c) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (0x1) @@ -1084,42 +1781,66 @@ #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (0x4) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (0x8) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x10011920) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x10011a00) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x900) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x10011a04) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x904) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x10011a08) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x908) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x10011a0c) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x90c) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x10011a80) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x980) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0x10011b00) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0xa00) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0x10011b04) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0xa04) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0x10011b08) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0xa08) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0x10011b0c) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R #define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0xa0c) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x10011b10) +#ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa10) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_KV_REG_BASE_ADDR (0x10018000) #define CLP_KV_REG_KEY_CTRL_0 (0x10018000) +#ifndef KV_REG_KEY_CTRL_0 #define KV_REG_KEY_CTRL_0 (0x0) #define KV_REG_KEY_CTRL_0_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_0_LOCK_WR_MASK (0x1) @@ -1135,7 +1856,9 @@ #define KV_REG_KEY_CTRL_0_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_0_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_0_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_1 (0x10018004) +#ifndef KV_REG_KEY_CTRL_1 #define KV_REG_KEY_CTRL_1 (0x4) #define KV_REG_KEY_CTRL_1_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_1_LOCK_WR_MASK (0x1) @@ -1151,7 +1874,9 @@ #define KV_REG_KEY_CTRL_1_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_1_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_1_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_2 (0x10018008) +#ifndef KV_REG_KEY_CTRL_2 #define KV_REG_KEY_CTRL_2 (0x8) #define KV_REG_KEY_CTRL_2_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_2_LOCK_WR_MASK (0x1) @@ -1167,7 +1892,9 @@ #define KV_REG_KEY_CTRL_2_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_2_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_2_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_3 (0x1001800c) +#ifndef KV_REG_KEY_CTRL_3 #define KV_REG_KEY_CTRL_3 (0xc) #define KV_REG_KEY_CTRL_3_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_3_LOCK_WR_MASK (0x1) @@ -1183,7 +1910,9 @@ #define KV_REG_KEY_CTRL_3_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_3_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_3_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_4 (0x10018010) +#ifndef KV_REG_KEY_CTRL_4 #define KV_REG_KEY_CTRL_4 (0x10) #define KV_REG_KEY_CTRL_4_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_4_LOCK_WR_MASK (0x1) @@ -1199,7 +1928,9 @@ #define KV_REG_KEY_CTRL_4_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_4_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_4_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_5 (0x10018014) +#ifndef KV_REG_KEY_CTRL_5 #define KV_REG_KEY_CTRL_5 (0x14) #define KV_REG_KEY_CTRL_5_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_5_LOCK_WR_MASK (0x1) @@ -1215,7 +1946,9 @@ #define KV_REG_KEY_CTRL_5_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_5_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_5_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_6 (0x10018018) +#ifndef KV_REG_KEY_CTRL_6 #define KV_REG_KEY_CTRL_6 (0x18) #define KV_REG_KEY_CTRL_6_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_6_LOCK_WR_MASK (0x1) @@ -1231,7 +1964,9 @@ #define KV_REG_KEY_CTRL_6_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_6_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_6_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_7 (0x1001801c) +#ifndef KV_REG_KEY_CTRL_7 #define KV_REG_KEY_CTRL_7 (0x1c) #define KV_REG_KEY_CTRL_7_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_7_LOCK_WR_MASK (0x1) @@ -1247,7 +1982,9 @@ #define KV_REG_KEY_CTRL_7_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_7_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_7_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_8 (0x10018020) +#ifndef KV_REG_KEY_CTRL_8 #define KV_REG_KEY_CTRL_8 (0x20) #define KV_REG_KEY_CTRL_8_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_8_LOCK_WR_MASK (0x1) @@ -1263,7 +2000,9 @@ #define KV_REG_KEY_CTRL_8_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_8_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_8_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_9 (0x10018024) +#ifndef KV_REG_KEY_CTRL_9 #define KV_REG_KEY_CTRL_9 (0x24) #define KV_REG_KEY_CTRL_9_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_9_LOCK_WR_MASK (0x1) @@ -1279,7 +2018,9 @@ #define KV_REG_KEY_CTRL_9_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_9_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_9_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_10 (0x10018028) +#ifndef KV_REG_KEY_CTRL_10 #define KV_REG_KEY_CTRL_10 (0x28) #define KV_REG_KEY_CTRL_10_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_10_LOCK_WR_MASK (0x1) @@ -1295,7 +2036,9 @@ #define KV_REG_KEY_CTRL_10_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_10_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_10_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_11 (0x1001802c) +#ifndef KV_REG_KEY_CTRL_11 #define KV_REG_KEY_CTRL_11 (0x2c) #define KV_REG_KEY_CTRL_11_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_11_LOCK_WR_MASK (0x1) @@ -1311,7 +2054,9 @@ #define KV_REG_KEY_CTRL_11_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_11_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_11_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_12 (0x10018030) +#ifndef KV_REG_KEY_CTRL_12 #define KV_REG_KEY_CTRL_12 (0x30) #define KV_REG_KEY_CTRL_12_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_12_LOCK_WR_MASK (0x1) @@ -1327,7 +2072,9 @@ #define KV_REG_KEY_CTRL_12_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_12_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_12_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_13 (0x10018034) +#ifndef KV_REG_KEY_CTRL_13 #define KV_REG_KEY_CTRL_13 (0x34) #define KV_REG_KEY_CTRL_13_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_13_LOCK_WR_MASK (0x1) @@ -1343,7 +2090,9 @@ #define KV_REG_KEY_CTRL_13_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_13_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_13_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_14 (0x10018038) +#ifndef KV_REG_KEY_CTRL_14 #define KV_REG_KEY_CTRL_14 (0x38) #define KV_REG_KEY_CTRL_14_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_14_LOCK_WR_MASK (0x1) @@ -1359,7 +2108,9 @@ #define KV_REG_KEY_CTRL_14_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_14_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_14_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_15 (0x1001803c) +#ifndef KV_REG_KEY_CTRL_15 #define KV_REG_KEY_CTRL_15 (0x3c) #define KV_REG_KEY_CTRL_15_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_15_LOCK_WR_MASK (0x1) @@ -1375,7 +2126,9 @@ #define KV_REG_KEY_CTRL_15_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_15_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_15_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_16 (0x10018040) +#ifndef KV_REG_KEY_CTRL_16 #define KV_REG_KEY_CTRL_16 (0x40) #define KV_REG_KEY_CTRL_16_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_16_LOCK_WR_MASK (0x1) @@ -1391,7 +2144,9 @@ #define KV_REG_KEY_CTRL_16_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_16_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_16_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_17 (0x10018044) +#ifndef KV_REG_KEY_CTRL_17 #define KV_REG_KEY_CTRL_17 (0x44) #define KV_REG_KEY_CTRL_17_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_17_LOCK_WR_MASK (0x1) @@ -1407,7 +2162,9 @@ #define KV_REG_KEY_CTRL_17_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_17_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_17_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_18 (0x10018048) +#ifndef KV_REG_KEY_CTRL_18 #define KV_REG_KEY_CTRL_18 (0x48) #define KV_REG_KEY_CTRL_18_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_18_LOCK_WR_MASK (0x1) @@ -1423,7 +2180,9 @@ #define KV_REG_KEY_CTRL_18_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_18_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_18_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_19 (0x1001804c) +#ifndef KV_REG_KEY_CTRL_19 #define KV_REG_KEY_CTRL_19 (0x4c) #define KV_REG_KEY_CTRL_19_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_19_LOCK_WR_MASK (0x1) @@ -1439,7 +2198,9 @@ #define KV_REG_KEY_CTRL_19_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_19_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_19_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_20 (0x10018050) +#ifndef KV_REG_KEY_CTRL_20 #define KV_REG_KEY_CTRL_20 (0x50) #define KV_REG_KEY_CTRL_20_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_20_LOCK_WR_MASK (0x1) @@ -1455,7 +2216,9 @@ #define KV_REG_KEY_CTRL_20_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_20_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_20_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_21 (0x10018054) +#ifndef KV_REG_KEY_CTRL_21 #define KV_REG_KEY_CTRL_21 (0x54) #define KV_REG_KEY_CTRL_21_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_21_LOCK_WR_MASK (0x1) @@ -1471,7 +2234,9 @@ #define KV_REG_KEY_CTRL_21_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_21_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_21_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_22 (0x10018058) +#ifndef KV_REG_KEY_CTRL_22 #define KV_REG_KEY_CTRL_22 (0x58) #define KV_REG_KEY_CTRL_22_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_22_LOCK_WR_MASK (0x1) @@ -1487,7 +2252,9 @@ #define KV_REG_KEY_CTRL_22_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_22_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_22_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_CTRL_23 (0x1001805c) +#ifndef KV_REG_KEY_CTRL_23 #define KV_REG_KEY_CTRL_23 (0x5c) #define KV_REG_KEY_CTRL_23_LOCK_WR_LOW (0) #define KV_REG_KEY_CTRL_23_LOCK_WR_MASK (0x1) @@ -1503,782 +2270,1554 @@ #define KV_REG_KEY_CTRL_23_DEST_VALID_MASK (0x1fe00) #define KV_REG_KEY_CTRL_23_LAST_DWORD_LOW (17) #define KV_REG_KEY_CTRL_23_LAST_DWORD_MASK (0x1e0000) +#endif #define CLP_KV_REG_KEY_ENTRY_0_0 (0x10018600) +#ifndef KV_REG_KEY_ENTRY_0_0 #define KV_REG_KEY_ENTRY_0_0 (0x600) +#endif #define CLP_KV_REG_KEY_ENTRY_0_1 (0x10018604) +#ifndef KV_REG_KEY_ENTRY_0_1 #define KV_REG_KEY_ENTRY_0_1 (0x604) +#endif #define CLP_KV_REG_KEY_ENTRY_0_2 (0x10018608) +#ifndef KV_REG_KEY_ENTRY_0_2 #define KV_REG_KEY_ENTRY_0_2 (0x608) +#endif #define CLP_KV_REG_KEY_ENTRY_0_3 (0x1001860c) +#ifndef KV_REG_KEY_ENTRY_0_3 #define KV_REG_KEY_ENTRY_0_3 (0x60c) +#endif #define CLP_KV_REG_KEY_ENTRY_0_4 (0x10018610) +#ifndef KV_REG_KEY_ENTRY_0_4 #define KV_REG_KEY_ENTRY_0_4 (0x610) +#endif #define CLP_KV_REG_KEY_ENTRY_0_5 (0x10018614) +#ifndef KV_REG_KEY_ENTRY_0_5 #define KV_REG_KEY_ENTRY_0_5 (0x614) +#endif #define CLP_KV_REG_KEY_ENTRY_0_6 (0x10018618) +#ifndef KV_REG_KEY_ENTRY_0_6 #define KV_REG_KEY_ENTRY_0_6 (0x618) +#endif #define CLP_KV_REG_KEY_ENTRY_0_7 (0x1001861c) +#ifndef KV_REG_KEY_ENTRY_0_7 #define KV_REG_KEY_ENTRY_0_7 (0x61c) +#endif #define CLP_KV_REG_KEY_ENTRY_0_8 (0x10018620) +#ifndef KV_REG_KEY_ENTRY_0_8 #define KV_REG_KEY_ENTRY_0_8 (0x620) +#endif #define CLP_KV_REG_KEY_ENTRY_0_9 (0x10018624) +#ifndef KV_REG_KEY_ENTRY_0_9 #define KV_REG_KEY_ENTRY_0_9 (0x624) +#endif #define CLP_KV_REG_KEY_ENTRY_0_10 (0x10018628) +#ifndef KV_REG_KEY_ENTRY_0_10 #define KV_REG_KEY_ENTRY_0_10 (0x628) +#endif #define CLP_KV_REG_KEY_ENTRY_0_11 (0x1001862c) +#ifndef KV_REG_KEY_ENTRY_0_11 #define KV_REG_KEY_ENTRY_0_11 (0x62c) +#endif #define CLP_KV_REG_KEY_ENTRY_0_12 (0x10018630) +#ifndef KV_REG_KEY_ENTRY_0_12 #define KV_REG_KEY_ENTRY_0_12 (0x630) +#endif #define CLP_KV_REG_KEY_ENTRY_0_13 (0x10018634) +#ifndef KV_REG_KEY_ENTRY_0_13 #define KV_REG_KEY_ENTRY_0_13 (0x634) +#endif #define CLP_KV_REG_KEY_ENTRY_0_14 (0x10018638) +#ifndef KV_REG_KEY_ENTRY_0_14 #define KV_REG_KEY_ENTRY_0_14 (0x638) +#endif #define CLP_KV_REG_KEY_ENTRY_0_15 (0x1001863c) +#ifndef KV_REG_KEY_ENTRY_0_15 #define KV_REG_KEY_ENTRY_0_15 (0x63c) +#endif #define CLP_KV_REG_KEY_ENTRY_1_0 (0x10018640) +#ifndef KV_REG_KEY_ENTRY_1_0 #define KV_REG_KEY_ENTRY_1_0 (0x640) +#endif #define CLP_KV_REG_KEY_ENTRY_1_1 (0x10018644) +#ifndef KV_REG_KEY_ENTRY_1_1 #define KV_REG_KEY_ENTRY_1_1 (0x644) +#endif #define CLP_KV_REG_KEY_ENTRY_1_2 (0x10018648) +#ifndef KV_REG_KEY_ENTRY_1_2 #define KV_REG_KEY_ENTRY_1_2 (0x648) +#endif #define CLP_KV_REG_KEY_ENTRY_1_3 (0x1001864c) +#ifndef KV_REG_KEY_ENTRY_1_3 #define KV_REG_KEY_ENTRY_1_3 (0x64c) +#endif #define CLP_KV_REG_KEY_ENTRY_1_4 (0x10018650) +#ifndef KV_REG_KEY_ENTRY_1_4 #define KV_REG_KEY_ENTRY_1_4 (0x650) +#endif #define CLP_KV_REG_KEY_ENTRY_1_5 (0x10018654) +#ifndef KV_REG_KEY_ENTRY_1_5 #define KV_REG_KEY_ENTRY_1_5 (0x654) +#endif #define CLP_KV_REG_KEY_ENTRY_1_6 (0x10018658) +#ifndef KV_REG_KEY_ENTRY_1_6 #define KV_REG_KEY_ENTRY_1_6 (0x658) +#endif #define CLP_KV_REG_KEY_ENTRY_1_7 (0x1001865c) +#ifndef KV_REG_KEY_ENTRY_1_7 #define KV_REG_KEY_ENTRY_1_7 (0x65c) +#endif #define CLP_KV_REG_KEY_ENTRY_1_8 (0x10018660) +#ifndef KV_REG_KEY_ENTRY_1_8 #define KV_REG_KEY_ENTRY_1_8 (0x660) +#endif #define CLP_KV_REG_KEY_ENTRY_1_9 (0x10018664) +#ifndef KV_REG_KEY_ENTRY_1_9 #define KV_REG_KEY_ENTRY_1_9 (0x664) +#endif #define CLP_KV_REG_KEY_ENTRY_1_10 (0x10018668) +#ifndef KV_REG_KEY_ENTRY_1_10 #define KV_REG_KEY_ENTRY_1_10 (0x668) +#endif #define CLP_KV_REG_KEY_ENTRY_1_11 (0x1001866c) +#ifndef KV_REG_KEY_ENTRY_1_11 #define KV_REG_KEY_ENTRY_1_11 (0x66c) +#endif #define CLP_KV_REG_KEY_ENTRY_1_12 (0x10018670) +#ifndef KV_REG_KEY_ENTRY_1_12 #define KV_REG_KEY_ENTRY_1_12 (0x670) +#endif #define CLP_KV_REG_KEY_ENTRY_1_13 (0x10018674) +#ifndef KV_REG_KEY_ENTRY_1_13 #define KV_REG_KEY_ENTRY_1_13 (0x674) +#endif #define CLP_KV_REG_KEY_ENTRY_1_14 (0x10018678) +#ifndef KV_REG_KEY_ENTRY_1_14 #define KV_REG_KEY_ENTRY_1_14 (0x678) +#endif #define CLP_KV_REG_KEY_ENTRY_1_15 (0x1001867c) +#ifndef KV_REG_KEY_ENTRY_1_15 #define KV_REG_KEY_ENTRY_1_15 (0x67c) +#endif #define CLP_KV_REG_KEY_ENTRY_2_0 (0x10018680) +#ifndef KV_REG_KEY_ENTRY_2_0 #define KV_REG_KEY_ENTRY_2_0 (0x680) +#endif #define CLP_KV_REG_KEY_ENTRY_2_1 (0x10018684) +#ifndef KV_REG_KEY_ENTRY_2_1 #define KV_REG_KEY_ENTRY_2_1 (0x684) +#endif #define CLP_KV_REG_KEY_ENTRY_2_2 (0x10018688) +#ifndef KV_REG_KEY_ENTRY_2_2 #define KV_REG_KEY_ENTRY_2_2 (0x688) +#endif #define CLP_KV_REG_KEY_ENTRY_2_3 (0x1001868c) +#ifndef KV_REG_KEY_ENTRY_2_3 #define KV_REG_KEY_ENTRY_2_3 (0x68c) +#endif #define CLP_KV_REG_KEY_ENTRY_2_4 (0x10018690) +#ifndef KV_REG_KEY_ENTRY_2_4 #define KV_REG_KEY_ENTRY_2_4 (0x690) +#endif #define CLP_KV_REG_KEY_ENTRY_2_5 (0x10018694) +#ifndef KV_REG_KEY_ENTRY_2_5 #define KV_REG_KEY_ENTRY_2_5 (0x694) +#endif #define CLP_KV_REG_KEY_ENTRY_2_6 (0x10018698) +#ifndef KV_REG_KEY_ENTRY_2_6 #define KV_REG_KEY_ENTRY_2_6 (0x698) +#endif #define CLP_KV_REG_KEY_ENTRY_2_7 (0x1001869c) +#ifndef KV_REG_KEY_ENTRY_2_7 #define KV_REG_KEY_ENTRY_2_7 (0x69c) +#endif #define CLP_KV_REG_KEY_ENTRY_2_8 (0x100186a0) +#ifndef KV_REG_KEY_ENTRY_2_8 #define KV_REG_KEY_ENTRY_2_8 (0x6a0) +#endif #define CLP_KV_REG_KEY_ENTRY_2_9 (0x100186a4) +#ifndef KV_REG_KEY_ENTRY_2_9 #define KV_REG_KEY_ENTRY_2_9 (0x6a4) +#endif #define CLP_KV_REG_KEY_ENTRY_2_10 (0x100186a8) +#ifndef KV_REG_KEY_ENTRY_2_10 #define KV_REG_KEY_ENTRY_2_10 (0x6a8) +#endif #define CLP_KV_REG_KEY_ENTRY_2_11 (0x100186ac) +#ifndef KV_REG_KEY_ENTRY_2_11 #define KV_REG_KEY_ENTRY_2_11 (0x6ac) +#endif #define CLP_KV_REG_KEY_ENTRY_2_12 (0x100186b0) +#ifndef KV_REG_KEY_ENTRY_2_12 #define KV_REG_KEY_ENTRY_2_12 (0x6b0) +#endif #define CLP_KV_REG_KEY_ENTRY_2_13 (0x100186b4) +#ifndef KV_REG_KEY_ENTRY_2_13 #define KV_REG_KEY_ENTRY_2_13 (0x6b4) +#endif #define CLP_KV_REG_KEY_ENTRY_2_14 (0x100186b8) +#ifndef KV_REG_KEY_ENTRY_2_14 #define KV_REG_KEY_ENTRY_2_14 (0x6b8) +#endif #define CLP_KV_REG_KEY_ENTRY_2_15 (0x100186bc) +#ifndef KV_REG_KEY_ENTRY_2_15 #define KV_REG_KEY_ENTRY_2_15 (0x6bc) +#endif #define CLP_KV_REG_KEY_ENTRY_3_0 (0x100186c0) +#ifndef KV_REG_KEY_ENTRY_3_0 #define KV_REG_KEY_ENTRY_3_0 (0x6c0) +#endif #define CLP_KV_REG_KEY_ENTRY_3_1 (0x100186c4) +#ifndef KV_REG_KEY_ENTRY_3_1 #define KV_REG_KEY_ENTRY_3_1 (0x6c4) +#endif #define CLP_KV_REG_KEY_ENTRY_3_2 (0x100186c8) +#ifndef KV_REG_KEY_ENTRY_3_2 #define KV_REG_KEY_ENTRY_3_2 (0x6c8) +#endif #define CLP_KV_REG_KEY_ENTRY_3_3 (0x100186cc) +#ifndef KV_REG_KEY_ENTRY_3_3 #define KV_REG_KEY_ENTRY_3_3 (0x6cc) +#endif #define CLP_KV_REG_KEY_ENTRY_3_4 (0x100186d0) +#ifndef KV_REG_KEY_ENTRY_3_4 #define KV_REG_KEY_ENTRY_3_4 (0x6d0) +#endif #define CLP_KV_REG_KEY_ENTRY_3_5 (0x100186d4) +#ifndef KV_REG_KEY_ENTRY_3_5 #define KV_REG_KEY_ENTRY_3_5 (0x6d4) +#endif #define CLP_KV_REG_KEY_ENTRY_3_6 (0x100186d8) +#ifndef KV_REG_KEY_ENTRY_3_6 #define KV_REG_KEY_ENTRY_3_6 (0x6d8) +#endif #define CLP_KV_REG_KEY_ENTRY_3_7 (0x100186dc) +#ifndef KV_REG_KEY_ENTRY_3_7 #define KV_REG_KEY_ENTRY_3_7 (0x6dc) +#endif #define CLP_KV_REG_KEY_ENTRY_3_8 (0x100186e0) +#ifndef KV_REG_KEY_ENTRY_3_8 #define KV_REG_KEY_ENTRY_3_8 (0x6e0) +#endif #define CLP_KV_REG_KEY_ENTRY_3_9 (0x100186e4) +#ifndef KV_REG_KEY_ENTRY_3_9 #define KV_REG_KEY_ENTRY_3_9 (0x6e4) +#endif #define CLP_KV_REG_KEY_ENTRY_3_10 (0x100186e8) +#ifndef KV_REG_KEY_ENTRY_3_10 #define KV_REG_KEY_ENTRY_3_10 (0x6e8) +#endif #define CLP_KV_REG_KEY_ENTRY_3_11 (0x100186ec) +#ifndef KV_REG_KEY_ENTRY_3_11 #define KV_REG_KEY_ENTRY_3_11 (0x6ec) +#endif #define CLP_KV_REG_KEY_ENTRY_3_12 (0x100186f0) +#ifndef KV_REG_KEY_ENTRY_3_12 #define KV_REG_KEY_ENTRY_3_12 (0x6f0) +#endif #define CLP_KV_REG_KEY_ENTRY_3_13 (0x100186f4) +#ifndef KV_REG_KEY_ENTRY_3_13 #define KV_REG_KEY_ENTRY_3_13 (0x6f4) +#endif #define CLP_KV_REG_KEY_ENTRY_3_14 (0x100186f8) +#ifndef KV_REG_KEY_ENTRY_3_14 #define KV_REG_KEY_ENTRY_3_14 (0x6f8) +#endif #define CLP_KV_REG_KEY_ENTRY_3_15 (0x100186fc) +#ifndef KV_REG_KEY_ENTRY_3_15 #define KV_REG_KEY_ENTRY_3_15 (0x6fc) +#endif #define CLP_KV_REG_KEY_ENTRY_4_0 (0x10018700) +#ifndef KV_REG_KEY_ENTRY_4_0 #define KV_REG_KEY_ENTRY_4_0 (0x700) +#endif #define CLP_KV_REG_KEY_ENTRY_4_1 (0x10018704) +#ifndef KV_REG_KEY_ENTRY_4_1 #define KV_REG_KEY_ENTRY_4_1 (0x704) +#endif #define CLP_KV_REG_KEY_ENTRY_4_2 (0x10018708) +#ifndef KV_REG_KEY_ENTRY_4_2 #define KV_REG_KEY_ENTRY_4_2 (0x708) +#endif #define CLP_KV_REG_KEY_ENTRY_4_3 (0x1001870c) +#ifndef KV_REG_KEY_ENTRY_4_3 #define KV_REG_KEY_ENTRY_4_3 (0x70c) +#endif #define CLP_KV_REG_KEY_ENTRY_4_4 (0x10018710) +#ifndef KV_REG_KEY_ENTRY_4_4 #define KV_REG_KEY_ENTRY_4_4 (0x710) +#endif #define CLP_KV_REG_KEY_ENTRY_4_5 (0x10018714) +#ifndef KV_REG_KEY_ENTRY_4_5 #define KV_REG_KEY_ENTRY_4_5 (0x714) +#endif #define CLP_KV_REG_KEY_ENTRY_4_6 (0x10018718) +#ifndef KV_REG_KEY_ENTRY_4_6 #define KV_REG_KEY_ENTRY_4_6 (0x718) +#endif #define CLP_KV_REG_KEY_ENTRY_4_7 (0x1001871c) +#ifndef KV_REG_KEY_ENTRY_4_7 #define KV_REG_KEY_ENTRY_4_7 (0x71c) +#endif #define CLP_KV_REG_KEY_ENTRY_4_8 (0x10018720) +#ifndef KV_REG_KEY_ENTRY_4_8 #define KV_REG_KEY_ENTRY_4_8 (0x720) +#endif #define CLP_KV_REG_KEY_ENTRY_4_9 (0x10018724) +#ifndef KV_REG_KEY_ENTRY_4_9 #define KV_REG_KEY_ENTRY_4_9 (0x724) +#endif #define CLP_KV_REG_KEY_ENTRY_4_10 (0x10018728) +#ifndef KV_REG_KEY_ENTRY_4_10 #define KV_REG_KEY_ENTRY_4_10 (0x728) +#endif #define CLP_KV_REG_KEY_ENTRY_4_11 (0x1001872c) +#ifndef KV_REG_KEY_ENTRY_4_11 #define KV_REG_KEY_ENTRY_4_11 (0x72c) +#endif #define CLP_KV_REG_KEY_ENTRY_4_12 (0x10018730) +#ifndef KV_REG_KEY_ENTRY_4_12 #define KV_REG_KEY_ENTRY_4_12 (0x730) +#endif #define CLP_KV_REG_KEY_ENTRY_4_13 (0x10018734) +#ifndef KV_REG_KEY_ENTRY_4_13 #define KV_REG_KEY_ENTRY_4_13 (0x734) +#endif #define CLP_KV_REG_KEY_ENTRY_4_14 (0x10018738) +#ifndef KV_REG_KEY_ENTRY_4_14 #define KV_REG_KEY_ENTRY_4_14 (0x738) +#endif #define CLP_KV_REG_KEY_ENTRY_4_15 (0x1001873c) +#ifndef KV_REG_KEY_ENTRY_4_15 #define KV_REG_KEY_ENTRY_4_15 (0x73c) +#endif #define CLP_KV_REG_KEY_ENTRY_5_0 (0x10018740) +#ifndef KV_REG_KEY_ENTRY_5_0 #define KV_REG_KEY_ENTRY_5_0 (0x740) +#endif #define CLP_KV_REG_KEY_ENTRY_5_1 (0x10018744) +#ifndef KV_REG_KEY_ENTRY_5_1 #define KV_REG_KEY_ENTRY_5_1 (0x744) +#endif #define CLP_KV_REG_KEY_ENTRY_5_2 (0x10018748) +#ifndef KV_REG_KEY_ENTRY_5_2 #define KV_REG_KEY_ENTRY_5_2 (0x748) +#endif #define CLP_KV_REG_KEY_ENTRY_5_3 (0x1001874c) +#ifndef KV_REG_KEY_ENTRY_5_3 #define KV_REG_KEY_ENTRY_5_3 (0x74c) +#endif #define CLP_KV_REG_KEY_ENTRY_5_4 (0x10018750) +#ifndef KV_REG_KEY_ENTRY_5_4 #define KV_REG_KEY_ENTRY_5_4 (0x750) +#endif #define CLP_KV_REG_KEY_ENTRY_5_5 (0x10018754) +#ifndef KV_REG_KEY_ENTRY_5_5 #define KV_REG_KEY_ENTRY_5_5 (0x754) +#endif #define CLP_KV_REG_KEY_ENTRY_5_6 (0x10018758) +#ifndef KV_REG_KEY_ENTRY_5_6 #define KV_REG_KEY_ENTRY_5_6 (0x758) +#endif #define CLP_KV_REG_KEY_ENTRY_5_7 (0x1001875c) +#ifndef KV_REG_KEY_ENTRY_5_7 #define KV_REG_KEY_ENTRY_5_7 (0x75c) +#endif #define CLP_KV_REG_KEY_ENTRY_5_8 (0x10018760) +#ifndef KV_REG_KEY_ENTRY_5_8 #define KV_REG_KEY_ENTRY_5_8 (0x760) +#endif #define CLP_KV_REG_KEY_ENTRY_5_9 (0x10018764) +#ifndef KV_REG_KEY_ENTRY_5_9 #define KV_REG_KEY_ENTRY_5_9 (0x764) +#endif #define CLP_KV_REG_KEY_ENTRY_5_10 (0x10018768) +#ifndef KV_REG_KEY_ENTRY_5_10 #define KV_REG_KEY_ENTRY_5_10 (0x768) +#endif #define CLP_KV_REG_KEY_ENTRY_5_11 (0x1001876c) +#ifndef KV_REG_KEY_ENTRY_5_11 #define KV_REG_KEY_ENTRY_5_11 (0x76c) +#endif #define CLP_KV_REG_KEY_ENTRY_5_12 (0x10018770) +#ifndef KV_REG_KEY_ENTRY_5_12 #define KV_REG_KEY_ENTRY_5_12 (0x770) +#endif #define CLP_KV_REG_KEY_ENTRY_5_13 (0x10018774) +#ifndef KV_REG_KEY_ENTRY_5_13 #define KV_REG_KEY_ENTRY_5_13 (0x774) +#endif #define CLP_KV_REG_KEY_ENTRY_5_14 (0x10018778) +#ifndef KV_REG_KEY_ENTRY_5_14 #define KV_REG_KEY_ENTRY_5_14 (0x778) +#endif #define CLP_KV_REG_KEY_ENTRY_5_15 (0x1001877c) +#ifndef KV_REG_KEY_ENTRY_5_15 #define KV_REG_KEY_ENTRY_5_15 (0x77c) +#endif #define CLP_KV_REG_KEY_ENTRY_6_0 (0x10018780) +#ifndef KV_REG_KEY_ENTRY_6_0 #define KV_REG_KEY_ENTRY_6_0 (0x780) +#endif #define CLP_KV_REG_KEY_ENTRY_6_1 (0x10018784) +#ifndef KV_REG_KEY_ENTRY_6_1 #define KV_REG_KEY_ENTRY_6_1 (0x784) +#endif #define CLP_KV_REG_KEY_ENTRY_6_2 (0x10018788) +#ifndef KV_REG_KEY_ENTRY_6_2 #define KV_REG_KEY_ENTRY_6_2 (0x788) +#endif #define CLP_KV_REG_KEY_ENTRY_6_3 (0x1001878c) +#ifndef KV_REG_KEY_ENTRY_6_3 #define KV_REG_KEY_ENTRY_6_3 (0x78c) +#endif #define CLP_KV_REG_KEY_ENTRY_6_4 (0x10018790) +#ifndef KV_REG_KEY_ENTRY_6_4 #define KV_REG_KEY_ENTRY_6_4 (0x790) +#endif #define CLP_KV_REG_KEY_ENTRY_6_5 (0x10018794) +#ifndef KV_REG_KEY_ENTRY_6_5 #define KV_REG_KEY_ENTRY_6_5 (0x794) +#endif #define CLP_KV_REG_KEY_ENTRY_6_6 (0x10018798) +#ifndef KV_REG_KEY_ENTRY_6_6 #define KV_REG_KEY_ENTRY_6_6 (0x798) +#endif #define CLP_KV_REG_KEY_ENTRY_6_7 (0x1001879c) +#ifndef KV_REG_KEY_ENTRY_6_7 #define KV_REG_KEY_ENTRY_6_7 (0x79c) +#endif #define CLP_KV_REG_KEY_ENTRY_6_8 (0x100187a0) +#ifndef KV_REG_KEY_ENTRY_6_8 #define KV_REG_KEY_ENTRY_6_8 (0x7a0) +#endif #define CLP_KV_REG_KEY_ENTRY_6_9 (0x100187a4) +#ifndef KV_REG_KEY_ENTRY_6_9 #define KV_REG_KEY_ENTRY_6_9 (0x7a4) +#endif #define CLP_KV_REG_KEY_ENTRY_6_10 (0x100187a8) +#ifndef KV_REG_KEY_ENTRY_6_10 #define KV_REG_KEY_ENTRY_6_10 (0x7a8) +#endif #define CLP_KV_REG_KEY_ENTRY_6_11 (0x100187ac) +#ifndef KV_REG_KEY_ENTRY_6_11 #define KV_REG_KEY_ENTRY_6_11 (0x7ac) +#endif #define CLP_KV_REG_KEY_ENTRY_6_12 (0x100187b0) +#ifndef KV_REG_KEY_ENTRY_6_12 #define KV_REG_KEY_ENTRY_6_12 (0x7b0) +#endif #define CLP_KV_REG_KEY_ENTRY_6_13 (0x100187b4) +#ifndef KV_REG_KEY_ENTRY_6_13 #define KV_REG_KEY_ENTRY_6_13 (0x7b4) +#endif #define CLP_KV_REG_KEY_ENTRY_6_14 (0x100187b8) +#ifndef KV_REG_KEY_ENTRY_6_14 #define KV_REG_KEY_ENTRY_6_14 (0x7b8) +#endif #define CLP_KV_REG_KEY_ENTRY_6_15 (0x100187bc) +#ifndef KV_REG_KEY_ENTRY_6_15 #define KV_REG_KEY_ENTRY_6_15 (0x7bc) +#endif #define CLP_KV_REG_KEY_ENTRY_7_0 (0x100187c0) +#ifndef KV_REG_KEY_ENTRY_7_0 #define KV_REG_KEY_ENTRY_7_0 (0x7c0) +#endif #define CLP_KV_REG_KEY_ENTRY_7_1 (0x100187c4) +#ifndef KV_REG_KEY_ENTRY_7_1 #define KV_REG_KEY_ENTRY_7_1 (0x7c4) +#endif #define CLP_KV_REG_KEY_ENTRY_7_2 (0x100187c8) +#ifndef KV_REG_KEY_ENTRY_7_2 #define KV_REG_KEY_ENTRY_7_2 (0x7c8) +#endif #define CLP_KV_REG_KEY_ENTRY_7_3 (0x100187cc) +#ifndef KV_REG_KEY_ENTRY_7_3 #define KV_REG_KEY_ENTRY_7_3 (0x7cc) +#endif #define CLP_KV_REG_KEY_ENTRY_7_4 (0x100187d0) +#ifndef KV_REG_KEY_ENTRY_7_4 #define KV_REG_KEY_ENTRY_7_4 (0x7d0) +#endif #define CLP_KV_REG_KEY_ENTRY_7_5 (0x100187d4) +#ifndef KV_REG_KEY_ENTRY_7_5 #define KV_REG_KEY_ENTRY_7_5 (0x7d4) +#endif #define CLP_KV_REG_KEY_ENTRY_7_6 (0x100187d8) +#ifndef KV_REG_KEY_ENTRY_7_6 #define KV_REG_KEY_ENTRY_7_6 (0x7d8) +#endif #define CLP_KV_REG_KEY_ENTRY_7_7 (0x100187dc) +#ifndef KV_REG_KEY_ENTRY_7_7 #define KV_REG_KEY_ENTRY_7_7 (0x7dc) +#endif #define CLP_KV_REG_KEY_ENTRY_7_8 (0x100187e0) +#ifndef KV_REG_KEY_ENTRY_7_8 #define KV_REG_KEY_ENTRY_7_8 (0x7e0) +#endif #define CLP_KV_REG_KEY_ENTRY_7_9 (0x100187e4) +#ifndef KV_REG_KEY_ENTRY_7_9 #define KV_REG_KEY_ENTRY_7_9 (0x7e4) +#endif #define CLP_KV_REG_KEY_ENTRY_7_10 (0x100187e8) +#ifndef KV_REG_KEY_ENTRY_7_10 #define KV_REG_KEY_ENTRY_7_10 (0x7e8) +#endif #define CLP_KV_REG_KEY_ENTRY_7_11 (0x100187ec) +#ifndef KV_REG_KEY_ENTRY_7_11 #define KV_REG_KEY_ENTRY_7_11 (0x7ec) +#endif #define CLP_KV_REG_KEY_ENTRY_7_12 (0x100187f0) +#ifndef KV_REG_KEY_ENTRY_7_12 #define KV_REG_KEY_ENTRY_7_12 (0x7f0) +#endif #define CLP_KV_REG_KEY_ENTRY_7_13 (0x100187f4) +#ifndef KV_REG_KEY_ENTRY_7_13 #define KV_REG_KEY_ENTRY_7_13 (0x7f4) +#endif #define CLP_KV_REG_KEY_ENTRY_7_14 (0x100187f8) +#ifndef KV_REG_KEY_ENTRY_7_14 #define KV_REG_KEY_ENTRY_7_14 (0x7f8) +#endif #define CLP_KV_REG_KEY_ENTRY_7_15 (0x100187fc) +#ifndef KV_REG_KEY_ENTRY_7_15 #define KV_REG_KEY_ENTRY_7_15 (0x7fc) +#endif #define CLP_KV_REG_KEY_ENTRY_8_0 (0x10018800) +#ifndef KV_REG_KEY_ENTRY_8_0 #define KV_REG_KEY_ENTRY_8_0 (0x800) +#endif #define CLP_KV_REG_KEY_ENTRY_8_1 (0x10018804) +#ifndef KV_REG_KEY_ENTRY_8_1 #define KV_REG_KEY_ENTRY_8_1 (0x804) +#endif #define CLP_KV_REG_KEY_ENTRY_8_2 (0x10018808) +#ifndef KV_REG_KEY_ENTRY_8_2 #define KV_REG_KEY_ENTRY_8_2 (0x808) +#endif #define CLP_KV_REG_KEY_ENTRY_8_3 (0x1001880c) +#ifndef KV_REG_KEY_ENTRY_8_3 #define KV_REG_KEY_ENTRY_8_3 (0x80c) +#endif #define CLP_KV_REG_KEY_ENTRY_8_4 (0x10018810) +#ifndef KV_REG_KEY_ENTRY_8_4 #define KV_REG_KEY_ENTRY_8_4 (0x810) +#endif #define CLP_KV_REG_KEY_ENTRY_8_5 (0x10018814) +#ifndef KV_REG_KEY_ENTRY_8_5 #define KV_REG_KEY_ENTRY_8_5 (0x814) +#endif #define CLP_KV_REG_KEY_ENTRY_8_6 (0x10018818) +#ifndef KV_REG_KEY_ENTRY_8_6 #define KV_REG_KEY_ENTRY_8_6 (0x818) +#endif #define CLP_KV_REG_KEY_ENTRY_8_7 (0x1001881c) +#ifndef KV_REG_KEY_ENTRY_8_7 #define KV_REG_KEY_ENTRY_8_7 (0x81c) +#endif #define CLP_KV_REG_KEY_ENTRY_8_8 (0x10018820) +#ifndef KV_REG_KEY_ENTRY_8_8 #define KV_REG_KEY_ENTRY_8_8 (0x820) +#endif #define CLP_KV_REG_KEY_ENTRY_8_9 (0x10018824) +#ifndef KV_REG_KEY_ENTRY_8_9 #define KV_REG_KEY_ENTRY_8_9 (0x824) +#endif #define CLP_KV_REG_KEY_ENTRY_8_10 (0x10018828) +#ifndef KV_REG_KEY_ENTRY_8_10 #define KV_REG_KEY_ENTRY_8_10 (0x828) +#endif #define CLP_KV_REG_KEY_ENTRY_8_11 (0x1001882c) +#ifndef KV_REG_KEY_ENTRY_8_11 #define KV_REG_KEY_ENTRY_8_11 (0x82c) +#endif #define CLP_KV_REG_KEY_ENTRY_8_12 (0x10018830) +#ifndef KV_REG_KEY_ENTRY_8_12 #define KV_REG_KEY_ENTRY_8_12 (0x830) +#endif #define CLP_KV_REG_KEY_ENTRY_8_13 (0x10018834) +#ifndef KV_REG_KEY_ENTRY_8_13 #define KV_REG_KEY_ENTRY_8_13 (0x834) +#endif #define CLP_KV_REG_KEY_ENTRY_8_14 (0x10018838) +#ifndef KV_REG_KEY_ENTRY_8_14 #define KV_REG_KEY_ENTRY_8_14 (0x838) +#endif #define CLP_KV_REG_KEY_ENTRY_8_15 (0x1001883c) +#ifndef KV_REG_KEY_ENTRY_8_15 #define KV_REG_KEY_ENTRY_8_15 (0x83c) +#endif #define CLP_KV_REG_KEY_ENTRY_9_0 (0x10018840) +#ifndef KV_REG_KEY_ENTRY_9_0 #define KV_REG_KEY_ENTRY_9_0 (0x840) +#endif #define CLP_KV_REG_KEY_ENTRY_9_1 (0x10018844) +#ifndef KV_REG_KEY_ENTRY_9_1 #define KV_REG_KEY_ENTRY_9_1 (0x844) +#endif #define CLP_KV_REG_KEY_ENTRY_9_2 (0x10018848) +#ifndef KV_REG_KEY_ENTRY_9_2 #define KV_REG_KEY_ENTRY_9_2 (0x848) +#endif #define CLP_KV_REG_KEY_ENTRY_9_3 (0x1001884c) +#ifndef KV_REG_KEY_ENTRY_9_3 #define KV_REG_KEY_ENTRY_9_3 (0x84c) +#endif #define CLP_KV_REG_KEY_ENTRY_9_4 (0x10018850) +#ifndef KV_REG_KEY_ENTRY_9_4 #define KV_REG_KEY_ENTRY_9_4 (0x850) +#endif #define CLP_KV_REG_KEY_ENTRY_9_5 (0x10018854) +#ifndef KV_REG_KEY_ENTRY_9_5 #define KV_REG_KEY_ENTRY_9_5 (0x854) +#endif #define CLP_KV_REG_KEY_ENTRY_9_6 (0x10018858) +#ifndef KV_REG_KEY_ENTRY_9_6 #define KV_REG_KEY_ENTRY_9_6 (0x858) +#endif #define CLP_KV_REG_KEY_ENTRY_9_7 (0x1001885c) +#ifndef KV_REG_KEY_ENTRY_9_7 #define KV_REG_KEY_ENTRY_9_7 (0x85c) +#endif #define CLP_KV_REG_KEY_ENTRY_9_8 (0x10018860) +#ifndef KV_REG_KEY_ENTRY_9_8 #define KV_REG_KEY_ENTRY_9_8 (0x860) +#endif #define CLP_KV_REG_KEY_ENTRY_9_9 (0x10018864) +#ifndef KV_REG_KEY_ENTRY_9_9 #define KV_REG_KEY_ENTRY_9_9 (0x864) +#endif #define CLP_KV_REG_KEY_ENTRY_9_10 (0x10018868) +#ifndef KV_REG_KEY_ENTRY_9_10 #define KV_REG_KEY_ENTRY_9_10 (0x868) +#endif #define CLP_KV_REG_KEY_ENTRY_9_11 (0x1001886c) +#ifndef KV_REG_KEY_ENTRY_9_11 #define KV_REG_KEY_ENTRY_9_11 (0x86c) +#endif #define CLP_KV_REG_KEY_ENTRY_9_12 (0x10018870) +#ifndef KV_REG_KEY_ENTRY_9_12 #define KV_REG_KEY_ENTRY_9_12 (0x870) +#endif #define CLP_KV_REG_KEY_ENTRY_9_13 (0x10018874) +#ifndef KV_REG_KEY_ENTRY_9_13 #define KV_REG_KEY_ENTRY_9_13 (0x874) +#endif #define CLP_KV_REG_KEY_ENTRY_9_14 (0x10018878) +#ifndef KV_REG_KEY_ENTRY_9_14 #define KV_REG_KEY_ENTRY_9_14 (0x878) +#endif #define CLP_KV_REG_KEY_ENTRY_9_15 (0x1001887c) +#ifndef KV_REG_KEY_ENTRY_9_15 #define KV_REG_KEY_ENTRY_9_15 (0x87c) +#endif #define CLP_KV_REG_KEY_ENTRY_10_0 (0x10018880) +#ifndef KV_REG_KEY_ENTRY_10_0 #define KV_REG_KEY_ENTRY_10_0 (0x880) +#endif #define CLP_KV_REG_KEY_ENTRY_10_1 (0x10018884) +#ifndef KV_REG_KEY_ENTRY_10_1 #define KV_REG_KEY_ENTRY_10_1 (0x884) +#endif #define CLP_KV_REG_KEY_ENTRY_10_2 (0x10018888) +#ifndef KV_REG_KEY_ENTRY_10_2 #define KV_REG_KEY_ENTRY_10_2 (0x888) +#endif #define CLP_KV_REG_KEY_ENTRY_10_3 (0x1001888c) +#ifndef KV_REG_KEY_ENTRY_10_3 #define KV_REG_KEY_ENTRY_10_3 (0x88c) +#endif #define CLP_KV_REG_KEY_ENTRY_10_4 (0x10018890) +#ifndef KV_REG_KEY_ENTRY_10_4 #define KV_REG_KEY_ENTRY_10_4 (0x890) +#endif #define CLP_KV_REG_KEY_ENTRY_10_5 (0x10018894) +#ifndef KV_REG_KEY_ENTRY_10_5 #define KV_REG_KEY_ENTRY_10_5 (0x894) +#endif #define CLP_KV_REG_KEY_ENTRY_10_6 (0x10018898) +#ifndef KV_REG_KEY_ENTRY_10_6 #define KV_REG_KEY_ENTRY_10_6 (0x898) +#endif #define CLP_KV_REG_KEY_ENTRY_10_7 (0x1001889c) +#ifndef KV_REG_KEY_ENTRY_10_7 #define KV_REG_KEY_ENTRY_10_7 (0x89c) +#endif #define CLP_KV_REG_KEY_ENTRY_10_8 (0x100188a0) +#ifndef KV_REG_KEY_ENTRY_10_8 #define KV_REG_KEY_ENTRY_10_8 (0x8a0) +#endif #define CLP_KV_REG_KEY_ENTRY_10_9 (0x100188a4) +#ifndef KV_REG_KEY_ENTRY_10_9 #define KV_REG_KEY_ENTRY_10_9 (0x8a4) +#endif #define CLP_KV_REG_KEY_ENTRY_10_10 (0x100188a8) +#ifndef KV_REG_KEY_ENTRY_10_10 #define KV_REG_KEY_ENTRY_10_10 (0x8a8) +#endif #define CLP_KV_REG_KEY_ENTRY_10_11 (0x100188ac) +#ifndef KV_REG_KEY_ENTRY_10_11 #define KV_REG_KEY_ENTRY_10_11 (0x8ac) +#endif #define CLP_KV_REG_KEY_ENTRY_10_12 (0x100188b0) +#ifndef KV_REG_KEY_ENTRY_10_12 #define KV_REG_KEY_ENTRY_10_12 (0x8b0) +#endif #define CLP_KV_REG_KEY_ENTRY_10_13 (0x100188b4) +#ifndef KV_REG_KEY_ENTRY_10_13 #define KV_REG_KEY_ENTRY_10_13 (0x8b4) +#endif #define CLP_KV_REG_KEY_ENTRY_10_14 (0x100188b8) +#ifndef KV_REG_KEY_ENTRY_10_14 #define KV_REG_KEY_ENTRY_10_14 (0x8b8) +#endif #define CLP_KV_REG_KEY_ENTRY_10_15 (0x100188bc) +#ifndef KV_REG_KEY_ENTRY_10_15 #define KV_REG_KEY_ENTRY_10_15 (0x8bc) +#endif #define CLP_KV_REG_KEY_ENTRY_11_0 (0x100188c0) +#ifndef KV_REG_KEY_ENTRY_11_0 #define KV_REG_KEY_ENTRY_11_0 (0x8c0) +#endif #define CLP_KV_REG_KEY_ENTRY_11_1 (0x100188c4) +#ifndef KV_REG_KEY_ENTRY_11_1 #define KV_REG_KEY_ENTRY_11_1 (0x8c4) +#endif #define CLP_KV_REG_KEY_ENTRY_11_2 (0x100188c8) +#ifndef KV_REG_KEY_ENTRY_11_2 #define KV_REG_KEY_ENTRY_11_2 (0x8c8) +#endif #define CLP_KV_REG_KEY_ENTRY_11_3 (0x100188cc) +#ifndef KV_REG_KEY_ENTRY_11_3 #define KV_REG_KEY_ENTRY_11_3 (0x8cc) +#endif #define CLP_KV_REG_KEY_ENTRY_11_4 (0x100188d0) +#ifndef KV_REG_KEY_ENTRY_11_4 #define KV_REG_KEY_ENTRY_11_4 (0x8d0) +#endif #define CLP_KV_REG_KEY_ENTRY_11_5 (0x100188d4) +#ifndef KV_REG_KEY_ENTRY_11_5 #define KV_REG_KEY_ENTRY_11_5 (0x8d4) +#endif #define CLP_KV_REG_KEY_ENTRY_11_6 (0x100188d8) +#ifndef KV_REG_KEY_ENTRY_11_6 #define KV_REG_KEY_ENTRY_11_6 (0x8d8) +#endif #define CLP_KV_REG_KEY_ENTRY_11_7 (0x100188dc) +#ifndef KV_REG_KEY_ENTRY_11_7 #define KV_REG_KEY_ENTRY_11_7 (0x8dc) +#endif #define CLP_KV_REG_KEY_ENTRY_11_8 (0x100188e0) +#ifndef KV_REG_KEY_ENTRY_11_8 #define KV_REG_KEY_ENTRY_11_8 (0x8e0) +#endif #define CLP_KV_REG_KEY_ENTRY_11_9 (0x100188e4) +#ifndef KV_REG_KEY_ENTRY_11_9 #define KV_REG_KEY_ENTRY_11_9 (0x8e4) +#endif #define CLP_KV_REG_KEY_ENTRY_11_10 (0x100188e8) +#ifndef KV_REG_KEY_ENTRY_11_10 #define KV_REG_KEY_ENTRY_11_10 (0x8e8) +#endif #define CLP_KV_REG_KEY_ENTRY_11_11 (0x100188ec) +#ifndef KV_REG_KEY_ENTRY_11_11 #define KV_REG_KEY_ENTRY_11_11 (0x8ec) +#endif #define CLP_KV_REG_KEY_ENTRY_11_12 (0x100188f0) +#ifndef KV_REG_KEY_ENTRY_11_12 #define KV_REG_KEY_ENTRY_11_12 (0x8f0) +#endif #define CLP_KV_REG_KEY_ENTRY_11_13 (0x100188f4) +#ifndef KV_REG_KEY_ENTRY_11_13 #define KV_REG_KEY_ENTRY_11_13 (0x8f4) +#endif #define CLP_KV_REG_KEY_ENTRY_11_14 (0x100188f8) +#ifndef KV_REG_KEY_ENTRY_11_14 #define KV_REG_KEY_ENTRY_11_14 (0x8f8) +#endif #define CLP_KV_REG_KEY_ENTRY_11_15 (0x100188fc) +#ifndef KV_REG_KEY_ENTRY_11_15 #define KV_REG_KEY_ENTRY_11_15 (0x8fc) +#endif #define CLP_KV_REG_KEY_ENTRY_12_0 (0x10018900) +#ifndef KV_REG_KEY_ENTRY_12_0 #define KV_REG_KEY_ENTRY_12_0 (0x900) +#endif #define CLP_KV_REG_KEY_ENTRY_12_1 (0x10018904) +#ifndef KV_REG_KEY_ENTRY_12_1 #define KV_REG_KEY_ENTRY_12_1 (0x904) +#endif #define CLP_KV_REG_KEY_ENTRY_12_2 (0x10018908) +#ifndef KV_REG_KEY_ENTRY_12_2 #define KV_REG_KEY_ENTRY_12_2 (0x908) +#endif #define CLP_KV_REG_KEY_ENTRY_12_3 (0x1001890c) +#ifndef KV_REG_KEY_ENTRY_12_3 #define KV_REG_KEY_ENTRY_12_3 (0x90c) +#endif #define CLP_KV_REG_KEY_ENTRY_12_4 (0x10018910) +#ifndef KV_REG_KEY_ENTRY_12_4 #define KV_REG_KEY_ENTRY_12_4 (0x910) +#endif #define CLP_KV_REG_KEY_ENTRY_12_5 (0x10018914) +#ifndef KV_REG_KEY_ENTRY_12_5 #define KV_REG_KEY_ENTRY_12_5 (0x914) +#endif #define CLP_KV_REG_KEY_ENTRY_12_6 (0x10018918) +#ifndef KV_REG_KEY_ENTRY_12_6 #define KV_REG_KEY_ENTRY_12_6 (0x918) +#endif #define CLP_KV_REG_KEY_ENTRY_12_7 (0x1001891c) +#ifndef KV_REG_KEY_ENTRY_12_7 #define KV_REG_KEY_ENTRY_12_7 (0x91c) +#endif #define CLP_KV_REG_KEY_ENTRY_12_8 (0x10018920) +#ifndef KV_REG_KEY_ENTRY_12_8 #define KV_REG_KEY_ENTRY_12_8 (0x920) +#endif #define CLP_KV_REG_KEY_ENTRY_12_9 (0x10018924) +#ifndef KV_REG_KEY_ENTRY_12_9 #define KV_REG_KEY_ENTRY_12_9 (0x924) +#endif #define CLP_KV_REG_KEY_ENTRY_12_10 (0x10018928) +#ifndef KV_REG_KEY_ENTRY_12_10 #define KV_REG_KEY_ENTRY_12_10 (0x928) +#endif #define CLP_KV_REG_KEY_ENTRY_12_11 (0x1001892c) +#ifndef KV_REG_KEY_ENTRY_12_11 #define KV_REG_KEY_ENTRY_12_11 (0x92c) +#endif #define CLP_KV_REG_KEY_ENTRY_12_12 (0x10018930) +#ifndef KV_REG_KEY_ENTRY_12_12 #define KV_REG_KEY_ENTRY_12_12 (0x930) +#endif #define CLP_KV_REG_KEY_ENTRY_12_13 (0x10018934) +#ifndef KV_REG_KEY_ENTRY_12_13 #define KV_REG_KEY_ENTRY_12_13 (0x934) +#endif #define CLP_KV_REG_KEY_ENTRY_12_14 (0x10018938) +#ifndef KV_REG_KEY_ENTRY_12_14 #define KV_REG_KEY_ENTRY_12_14 (0x938) +#endif #define CLP_KV_REG_KEY_ENTRY_12_15 (0x1001893c) +#ifndef KV_REG_KEY_ENTRY_12_15 #define KV_REG_KEY_ENTRY_12_15 (0x93c) +#endif #define CLP_KV_REG_KEY_ENTRY_13_0 (0x10018940) +#ifndef KV_REG_KEY_ENTRY_13_0 #define KV_REG_KEY_ENTRY_13_0 (0x940) +#endif #define CLP_KV_REG_KEY_ENTRY_13_1 (0x10018944) +#ifndef KV_REG_KEY_ENTRY_13_1 #define KV_REG_KEY_ENTRY_13_1 (0x944) +#endif #define CLP_KV_REG_KEY_ENTRY_13_2 (0x10018948) +#ifndef KV_REG_KEY_ENTRY_13_2 #define KV_REG_KEY_ENTRY_13_2 (0x948) +#endif #define CLP_KV_REG_KEY_ENTRY_13_3 (0x1001894c) +#ifndef KV_REG_KEY_ENTRY_13_3 #define KV_REG_KEY_ENTRY_13_3 (0x94c) +#endif #define CLP_KV_REG_KEY_ENTRY_13_4 (0x10018950) +#ifndef KV_REG_KEY_ENTRY_13_4 #define KV_REG_KEY_ENTRY_13_4 (0x950) +#endif #define CLP_KV_REG_KEY_ENTRY_13_5 (0x10018954) +#ifndef KV_REG_KEY_ENTRY_13_5 #define KV_REG_KEY_ENTRY_13_5 (0x954) +#endif #define CLP_KV_REG_KEY_ENTRY_13_6 (0x10018958) +#ifndef KV_REG_KEY_ENTRY_13_6 #define KV_REG_KEY_ENTRY_13_6 (0x958) +#endif #define CLP_KV_REG_KEY_ENTRY_13_7 (0x1001895c) +#ifndef KV_REG_KEY_ENTRY_13_7 #define KV_REG_KEY_ENTRY_13_7 (0x95c) +#endif #define CLP_KV_REG_KEY_ENTRY_13_8 (0x10018960) +#ifndef KV_REG_KEY_ENTRY_13_8 #define KV_REG_KEY_ENTRY_13_8 (0x960) +#endif #define CLP_KV_REG_KEY_ENTRY_13_9 (0x10018964) +#ifndef KV_REG_KEY_ENTRY_13_9 #define KV_REG_KEY_ENTRY_13_9 (0x964) +#endif #define CLP_KV_REG_KEY_ENTRY_13_10 (0x10018968) +#ifndef KV_REG_KEY_ENTRY_13_10 #define KV_REG_KEY_ENTRY_13_10 (0x968) +#endif #define CLP_KV_REG_KEY_ENTRY_13_11 (0x1001896c) +#ifndef KV_REG_KEY_ENTRY_13_11 #define KV_REG_KEY_ENTRY_13_11 (0x96c) +#endif #define CLP_KV_REG_KEY_ENTRY_13_12 (0x10018970) +#ifndef KV_REG_KEY_ENTRY_13_12 #define KV_REG_KEY_ENTRY_13_12 (0x970) +#endif #define CLP_KV_REG_KEY_ENTRY_13_13 (0x10018974) +#ifndef KV_REG_KEY_ENTRY_13_13 #define KV_REG_KEY_ENTRY_13_13 (0x974) +#endif #define CLP_KV_REG_KEY_ENTRY_13_14 (0x10018978) +#ifndef KV_REG_KEY_ENTRY_13_14 #define KV_REG_KEY_ENTRY_13_14 (0x978) +#endif #define CLP_KV_REG_KEY_ENTRY_13_15 (0x1001897c) +#ifndef KV_REG_KEY_ENTRY_13_15 #define KV_REG_KEY_ENTRY_13_15 (0x97c) +#endif #define CLP_KV_REG_KEY_ENTRY_14_0 (0x10018980) +#ifndef KV_REG_KEY_ENTRY_14_0 #define KV_REG_KEY_ENTRY_14_0 (0x980) +#endif #define CLP_KV_REG_KEY_ENTRY_14_1 (0x10018984) +#ifndef KV_REG_KEY_ENTRY_14_1 #define KV_REG_KEY_ENTRY_14_1 (0x984) +#endif #define CLP_KV_REG_KEY_ENTRY_14_2 (0x10018988) +#ifndef KV_REG_KEY_ENTRY_14_2 #define KV_REG_KEY_ENTRY_14_2 (0x988) +#endif #define CLP_KV_REG_KEY_ENTRY_14_3 (0x1001898c) +#ifndef KV_REG_KEY_ENTRY_14_3 #define KV_REG_KEY_ENTRY_14_3 (0x98c) +#endif #define CLP_KV_REG_KEY_ENTRY_14_4 (0x10018990) +#ifndef KV_REG_KEY_ENTRY_14_4 #define KV_REG_KEY_ENTRY_14_4 (0x990) +#endif #define CLP_KV_REG_KEY_ENTRY_14_5 (0x10018994) +#ifndef KV_REG_KEY_ENTRY_14_5 #define KV_REG_KEY_ENTRY_14_5 (0x994) +#endif #define CLP_KV_REG_KEY_ENTRY_14_6 (0x10018998) +#ifndef KV_REG_KEY_ENTRY_14_6 #define KV_REG_KEY_ENTRY_14_6 (0x998) +#endif #define CLP_KV_REG_KEY_ENTRY_14_7 (0x1001899c) +#ifndef KV_REG_KEY_ENTRY_14_7 #define KV_REG_KEY_ENTRY_14_7 (0x99c) +#endif #define CLP_KV_REG_KEY_ENTRY_14_8 (0x100189a0) +#ifndef KV_REG_KEY_ENTRY_14_8 #define KV_REG_KEY_ENTRY_14_8 (0x9a0) +#endif #define CLP_KV_REG_KEY_ENTRY_14_9 (0x100189a4) +#ifndef KV_REG_KEY_ENTRY_14_9 #define KV_REG_KEY_ENTRY_14_9 (0x9a4) +#endif #define CLP_KV_REG_KEY_ENTRY_14_10 (0x100189a8) +#ifndef KV_REG_KEY_ENTRY_14_10 #define KV_REG_KEY_ENTRY_14_10 (0x9a8) +#endif #define CLP_KV_REG_KEY_ENTRY_14_11 (0x100189ac) +#ifndef KV_REG_KEY_ENTRY_14_11 #define KV_REG_KEY_ENTRY_14_11 (0x9ac) +#endif #define CLP_KV_REG_KEY_ENTRY_14_12 (0x100189b0) +#ifndef KV_REG_KEY_ENTRY_14_12 #define KV_REG_KEY_ENTRY_14_12 (0x9b0) +#endif #define CLP_KV_REG_KEY_ENTRY_14_13 (0x100189b4) +#ifndef KV_REG_KEY_ENTRY_14_13 #define KV_REG_KEY_ENTRY_14_13 (0x9b4) +#endif #define CLP_KV_REG_KEY_ENTRY_14_14 (0x100189b8) +#ifndef KV_REG_KEY_ENTRY_14_14 #define KV_REG_KEY_ENTRY_14_14 (0x9b8) +#endif #define CLP_KV_REG_KEY_ENTRY_14_15 (0x100189bc) +#ifndef KV_REG_KEY_ENTRY_14_15 #define KV_REG_KEY_ENTRY_14_15 (0x9bc) +#endif #define CLP_KV_REG_KEY_ENTRY_15_0 (0x100189c0) +#ifndef KV_REG_KEY_ENTRY_15_0 #define KV_REG_KEY_ENTRY_15_0 (0x9c0) +#endif #define CLP_KV_REG_KEY_ENTRY_15_1 (0x100189c4) +#ifndef KV_REG_KEY_ENTRY_15_1 #define KV_REG_KEY_ENTRY_15_1 (0x9c4) +#endif #define CLP_KV_REG_KEY_ENTRY_15_2 (0x100189c8) +#ifndef KV_REG_KEY_ENTRY_15_2 #define KV_REG_KEY_ENTRY_15_2 (0x9c8) +#endif #define CLP_KV_REG_KEY_ENTRY_15_3 (0x100189cc) +#ifndef KV_REG_KEY_ENTRY_15_3 #define KV_REG_KEY_ENTRY_15_3 (0x9cc) +#endif #define CLP_KV_REG_KEY_ENTRY_15_4 (0x100189d0) +#ifndef KV_REG_KEY_ENTRY_15_4 #define KV_REG_KEY_ENTRY_15_4 (0x9d0) +#endif #define CLP_KV_REG_KEY_ENTRY_15_5 (0x100189d4) +#ifndef KV_REG_KEY_ENTRY_15_5 #define KV_REG_KEY_ENTRY_15_5 (0x9d4) +#endif #define CLP_KV_REG_KEY_ENTRY_15_6 (0x100189d8) +#ifndef KV_REG_KEY_ENTRY_15_6 #define KV_REG_KEY_ENTRY_15_6 (0x9d8) +#endif #define CLP_KV_REG_KEY_ENTRY_15_7 (0x100189dc) +#ifndef KV_REG_KEY_ENTRY_15_7 #define KV_REG_KEY_ENTRY_15_7 (0x9dc) +#endif #define CLP_KV_REG_KEY_ENTRY_15_8 (0x100189e0) +#ifndef KV_REG_KEY_ENTRY_15_8 #define KV_REG_KEY_ENTRY_15_8 (0x9e0) +#endif #define CLP_KV_REG_KEY_ENTRY_15_9 (0x100189e4) +#ifndef KV_REG_KEY_ENTRY_15_9 #define KV_REG_KEY_ENTRY_15_9 (0x9e4) +#endif #define CLP_KV_REG_KEY_ENTRY_15_10 (0x100189e8) +#ifndef KV_REG_KEY_ENTRY_15_10 #define KV_REG_KEY_ENTRY_15_10 (0x9e8) +#endif #define CLP_KV_REG_KEY_ENTRY_15_11 (0x100189ec) +#ifndef KV_REG_KEY_ENTRY_15_11 #define KV_REG_KEY_ENTRY_15_11 (0x9ec) +#endif #define CLP_KV_REG_KEY_ENTRY_15_12 (0x100189f0) +#ifndef KV_REG_KEY_ENTRY_15_12 #define KV_REG_KEY_ENTRY_15_12 (0x9f0) +#endif #define CLP_KV_REG_KEY_ENTRY_15_13 (0x100189f4) +#ifndef KV_REG_KEY_ENTRY_15_13 #define KV_REG_KEY_ENTRY_15_13 (0x9f4) +#endif #define CLP_KV_REG_KEY_ENTRY_15_14 (0x100189f8) +#ifndef KV_REG_KEY_ENTRY_15_14 #define KV_REG_KEY_ENTRY_15_14 (0x9f8) +#endif #define CLP_KV_REG_KEY_ENTRY_15_15 (0x100189fc) +#ifndef KV_REG_KEY_ENTRY_15_15 #define KV_REG_KEY_ENTRY_15_15 (0x9fc) +#endif #define CLP_KV_REG_KEY_ENTRY_16_0 (0x10018a00) +#ifndef KV_REG_KEY_ENTRY_16_0 #define KV_REG_KEY_ENTRY_16_0 (0xa00) +#endif #define CLP_KV_REG_KEY_ENTRY_16_1 (0x10018a04) +#ifndef KV_REG_KEY_ENTRY_16_1 #define KV_REG_KEY_ENTRY_16_1 (0xa04) +#endif #define CLP_KV_REG_KEY_ENTRY_16_2 (0x10018a08) +#ifndef KV_REG_KEY_ENTRY_16_2 #define KV_REG_KEY_ENTRY_16_2 (0xa08) +#endif #define CLP_KV_REG_KEY_ENTRY_16_3 (0x10018a0c) +#ifndef KV_REG_KEY_ENTRY_16_3 #define KV_REG_KEY_ENTRY_16_3 (0xa0c) +#endif #define CLP_KV_REG_KEY_ENTRY_16_4 (0x10018a10) +#ifndef KV_REG_KEY_ENTRY_16_4 #define KV_REG_KEY_ENTRY_16_4 (0xa10) +#endif #define CLP_KV_REG_KEY_ENTRY_16_5 (0x10018a14) +#ifndef KV_REG_KEY_ENTRY_16_5 #define KV_REG_KEY_ENTRY_16_5 (0xa14) +#endif #define CLP_KV_REG_KEY_ENTRY_16_6 (0x10018a18) +#ifndef KV_REG_KEY_ENTRY_16_6 #define KV_REG_KEY_ENTRY_16_6 (0xa18) +#endif #define CLP_KV_REG_KEY_ENTRY_16_7 (0x10018a1c) +#ifndef KV_REG_KEY_ENTRY_16_7 #define KV_REG_KEY_ENTRY_16_7 (0xa1c) +#endif #define CLP_KV_REG_KEY_ENTRY_16_8 (0x10018a20) +#ifndef KV_REG_KEY_ENTRY_16_8 #define KV_REG_KEY_ENTRY_16_8 (0xa20) +#endif #define CLP_KV_REG_KEY_ENTRY_16_9 (0x10018a24) +#ifndef KV_REG_KEY_ENTRY_16_9 #define KV_REG_KEY_ENTRY_16_9 (0xa24) +#endif #define CLP_KV_REG_KEY_ENTRY_16_10 (0x10018a28) +#ifndef KV_REG_KEY_ENTRY_16_10 #define KV_REG_KEY_ENTRY_16_10 (0xa28) +#endif #define CLP_KV_REG_KEY_ENTRY_16_11 (0x10018a2c) +#ifndef KV_REG_KEY_ENTRY_16_11 #define KV_REG_KEY_ENTRY_16_11 (0xa2c) +#endif #define CLP_KV_REG_KEY_ENTRY_16_12 (0x10018a30) +#ifndef KV_REG_KEY_ENTRY_16_12 #define KV_REG_KEY_ENTRY_16_12 (0xa30) +#endif #define CLP_KV_REG_KEY_ENTRY_16_13 (0x10018a34) +#ifndef KV_REG_KEY_ENTRY_16_13 #define KV_REG_KEY_ENTRY_16_13 (0xa34) +#endif #define CLP_KV_REG_KEY_ENTRY_16_14 (0x10018a38) +#ifndef KV_REG_KEY_ENTRY_16_14 #define KV_REG_KEY_ENTRY_16_14 (0xa38) +#endif #define CLP_KV_REG_KEY_ENTRY_16_15 (0x10018a3c) +#ifndef KV_REG_KEY_ENTRY_16_15 #define KV_REG_KEY_ENTRY_16_15 (0xa3c) +#endif #define CLP_KV_REG_KEY_ENTRY_17_0 (0x10018a40) +#ifndef KV_REG_KEY_ENTRY_17_0 #define KV_REG_KEY_ENTRY_17_0 (0xa40) +#endif #define CLP_KV_REG_KEY_ENTRY_17_1 (0x10018a44) +#ifndef KV_REG_KEY_ENTRY_17_1 #define KV_REG_KEY_ENTRY_17_1 (0xa44) +#endif #define CLP_KV_REG_KEY_ENTRY_17_2 (0x10018a48) +#ifndef KV_REG_KEY_ENTRY_17_2 #define KV_REG_KEY_ENTRY_17_2 (0xa48) +#endif #define CLP_KV_REG_KEY_ENTRY_17_3 (0x10018a4c) +#ifndef KV_REG_KEY_ENTRY_17_3 #define KV_REG_KEY_ENTRY_17_3 (0xa4c) +#endif #define CLP_KV_REG_KEY_ENTRY_17_4 (0x10018a50) +#ifndef KV_REG_KEY_ENTRY_17_4 #define KV_REG_KEY_ENTRY_17_4 (0xa50) +#endif #define CLP_KV_REG_KEY_ENTRY_17_5 (0x10018a54) +#ifndef KV_REG_KEY_ENTRY_17_5 #define KV_REG_KEY_ENTRY_17_5 (0xa54) +#endif #define CLP_KV_REG_KEY_ENTRY_17_6 (0x10018a58) +#ifndef KV_REG_KEY_ENTRY_17_6 #define KV_REG_KEY_ENTRY_17_6 (0xa58) +#endif #define CLP_KV_REG_KEY_ENTRY_17_7 (0x10018a5c) +#ifndef KV_REG_KEY_ENTRY_17_7 #define KV_REG_KEY_ENTRY_17_7 (0xa5c) +#endif #define CLP_KV_REG_KEY_ENTRY_17_8 (0x10018a60) +#ifndef KV_REG_KEY_ENTRY_17_8 #define KV_REG_KEY_ENTRY_17_8 (0xa60) +#endif #define CLP_KV_REG_KEY_ENTRY_17_9 (0x10018a64) +#ifndef KV_REG_KEY_ENTRY_17_9 #define KV_REG_KEY_ENTRY_17_9 (0xa64) +#endif #define CLP_KV_REG_KEY_ENTRY_17_10 (0x10018a68) +#ifndef KV_REG_KEY_ENTRY_17_10 #define KV_REG_KEY_ENTRY_17_10 (0xa68) +#endif #define CLP_KV_REG_KEY_ENTRY_17_11 (0x10018a6c) +#ifndef KV_REG_KEY_ENTRY_17_11 #define KV_REG_KEY_ENTRY_17_11 (0xa6c) +#endif #define CLP_KV_REG_KEY_ENTRY_17_12 (0x10018a70) +#ifndef KV_REG_KEY_ENTRY_17_12 #define KV_REG_KEY_ENTRY_17_12 (0xa70) +#endif #define CLP_KV_REG_KEY_ENTRY_17_13 (0x10018a74) +#ifndef KV_REG_KEY_ENTRY_17_13 #define KV_REG_KEY_ENTRY_17_13 (0xa74) +#endif #define CLP_KV_REG_KEY_ENTRY_17_14 (0x10018a78) +#ifndef KV_REG_KEY_ENTRY_17_14 #define KV_REG_KEY_ENTRY_17_14 (0xa78) +#endif #define CLP_KV_REG_KEY_ENTRY_17_15 (0x10018a7c) +#ifndef KV_REG_KEY_ENTRY_17_15 #define KV_REG_KEY_ENTRY_17_15 (0xa7c) +#endif #define CLP_KV_REG_KEY_ENTRY_18_0 (0x10018a80) +#ifndef KV_REG_KEY_ENTRY_18_0 #define KV_REG_KEY_ENTRY_18_0 (0xa80) +#endif #define CLP_KV_REG_KEY_ENTRY_18_1 (0x10018a84) +#ifndef KV_REG_KEY_ENTRY_18_1 #define KV_REG_KEY_ENTRY_18_1 (0xa84) +#endif #define CLP_KV_REG_KEY_ENTRY_18_2 (0x10018a88) +#ifndef KV_REG_KEY_ENTRY_18_2 #define KV_REG_KEY_ENTRY_18_2 (0xa88) +#endif #define CLP_KV_REG_KEY_ENTRY_18_3 (0x10018a8c) +#ifndef KV_REG_KEY_ENTRY_18_3 #define KV_REG_KEY_ENTRY_18_3 (0xa8c) +#endif #define CLP_KV_REG_KEY_ENTRY_18_4 (0x10018a90) +#ifndef KV_REG_KEY_ENTRY_18_4 #define KV_REG_KEY_ENTRY_18_4 (0xa90) +#endif #define CLP_KV_REG_KEY_ENTRY_18_5 (0x10018a94) +#ifndef KV_REG_KEY_ENTRY_18_5 #define KV_REG_KEY_ENTRY_18_5 (0xa94) +#endif #define CLP_KV_REG_KEY_ENTRY_18_6 (0x10018a98) +#ifndef KV_REG_KEY_ENTRY_18_6 #define KV_REG_KEY_ENTRY_18_6 (0xa98) +#endif #define CLP_KV_REG_KEY_ENTRY_18_7 (0x10018a9c) +#ifndef KV_REG_KEY_ENTRY_18_7 #define KV_REG_KEY_ENTRY_18_7 (0xa9c) +#endif #define CLP_KV_REG_KEY_ENTRY_18_8 (0x10018aa0) +#ifndef KV_REG_KEY_ENTRY_18_8 #define KV_REG_KEY_ENTRY_18_8 (0xaa0) +#endif #define CLP_KV_REG_KEY_ENTRY_18_9 (0x10018aa4) +#ifndef KV_REG_KEY_ENTRY_18_9 #define KV_REG_KEY_ENTRY_18_9 (0xaa4) +#endif #define CLP_KV_REG_KEY_ENTRY_18_10 (0x10018aa8) +#ifndef KV_REG_KEY_ENTRY_18_10 #define KV_REG_KEY_ENTRY_18_10 (0xaa8) +#endif #define CLP_KV_REG_KEY_ENTRY_18_11 (0x10018aac) +#ifndef KV_REG_KEY_ENTRY_18_11 #define KV_REG_KEY_ENTRY_18_11 (0xaac) +#endif #define CLP_KV_REG_KEY_ENTRY_18_12 (0x10018ab0) +#ifndef KV_REG_KEY_ENTRY_18_12 #define KV_REG_KEY_ENTRY_18_12 (0xab0) +#endif #define CLP_KV_REG_KEY_ENTRY_18_13 (0x10018ab4) +#ifndef KV_REG_KEY_ENTRY_18_13 #define KV_REG_KEY_ENTRY_18_13 (0xab4) +#endif #define CLP_KV_REG_KEY_ENTRY_18_14 (0x10018ab8) +#ifndef KV_REG_KEY_ENTRY_18_14 #define KV_REG_KEY_ENTRY_18_14 (0xab8) +#endif #define CLP_KV_REG_KEY_ENTRY_18_15 (0x10018abc) +#ifndef KV_REG_KEY_ENTRY_18_15 #define KV_REG_KEY_ENTRY_18_15 (0xabc) +#endif #define CLP_KV_REG_KEY_ENTRY_19_0 (0x10018ac0) +#ifndef KV_REG_KEY_ENTRY_19_0 #define KV_REG_KEY_ENTRY_19_0 (0xac0) +#endif #define CLP_KV_REG_KEY_ENTRY_19_1 (0x10018ac4) +#ifndef KV_REG_KEY_ENTRY_19_1 #define KV_REG_KEY_ENTRY_19_1 (0xac4) +#endif #define CLP_KV_REG_KEY_ENTRY_19_2 (0x10018ac8) +#ifndef KV_REG_KEY_ENTRY_19_2 #define KV_REG_KEY_ENTRY_19_2 (0xac8) +#endif #define CLP_KV_REG_KEY_ENTRY_19_3 (0x10018acc) +#ifndef KV_REG_KEY_ENTRY_19_3 #define KV_REG_KEY_ENTRY_19_3 (0xacc) +#endif #define CLP_KV_REG_KEY_ENTRY_19_4 (0x10018ad0) +#ifndef KV_REG_KEY_ENTRY_19_4 #define KV_REG_KEY_ENTRY_19_4 (0xad0) +#endif #define CLP_KV_REG_KEY_ENTRY_19_5 (0x10018ad4) +#ifndef KV_REG_KEY_ENTRY_19_5 #define KV_REG_KEY_ENTRY_19_5 (0xad4) +#endif #define CLP_KV_REG_KEY_ENTRY_19_6 (0x10018ad8) +#ifndef KV_REG_KEY_ENTRY_19_6 #define KV_REG_KEY_ENTRY_19_6 (0xad8) +#endif #define CLP_KV_REG_KEY_ENTRY_19_7 (0x10018adc) +#ifndef KV_REG_KEY_ENTRY_19_7 #define KV_REG_KEY_ENTRY_19_7 (0xadc) +#endif #define CLP_KV_REG_KEY_ENTRY_19_8 (0x10018ae0) +#ifndef KV_REG_KEY_ENTRY_19_8 #define KV_REG_KEY_ENTRY_19_8 (0xae0) +#endif #define CLP_KV_REG_KEY_ENTRY_19_9 (0x10018ae4) +#ifndef KV_REG_KEY_ENTRY_19_9 #define KV_REG_KEY_ENTRY_19_9 (0xae4) +#endif #define CLP_KV_REG_KEY_ENTRY_19_10 (0x10018ae8) +#ifndef KV_REG_KEY_ENTRY_19_10 #define KV_REG_KEY_ENTRY_19_10 (0xae8) +#endif #define CLP_KV_REG_KEY_ENTRY_19_11 (0x10018aec) +#ifndef KV_REG_KEY_ENTRY_19_11 #define KV_REG_KEY_ENTRY_19_11 (0xaec) +#endif #define CLP_KV_REG_KEY_ENTRY_19_12 (0x10018af0) +#ifndef KV_REG_KEY_ENTRY_19_12 #define KV_REG_KEY_ENTRY_19_12 (0xaf0) +#endif #define CLP_KV_REG_KEY_ENTRY_19_13 (0x10018af4) +#ifndef KV_REG_KEY_ENTRY_19_13 #define KV_REG_KEY_ENTRY_19_13 (0xaf4) +#endif #define CLP_KV_REG_KEY_ENTRY_19_14 (0x10018af8) +#ifndef KV_REG_KEY_ENTRY_19_14 #define KV_REG_KEY_ENTRY_19_14 (0xaf8) +#endif #define CLP_KV_REG_KEY_ENTRY_19_15 (0x10018afc) +#ifndef KV_REG_KEY_ENTRY_19_15 #define KV_REG_KEY_ENTRY_19_15 (0xafc) +#endif #define CLP_KV_REG_KEY_ENTRY_20_0 (0x10018b00) +#ifndef KV_REG_KEY_ENTRY_20_0 #define KV_REG_KEY_ENTRY_20_0 (0xb00) +#endif #define CLP_KV_REG_KEY_ENTRY_20_1 (0x10018b04) +#ifndef KV_REG_KEY_ENTRY_20_1 #define KV_REG_KEY_ENTRY_20_1 (0xb04) +#endif #define CLP_KV_REG_KEY_ENTRY_20_2 (0x10018b08) +#ifndef KV_REG_KEY_ENTRY_20_2 #define KV_REG_KEY_ENTRY_20_2 (0xb08) +#endif #define CLP_KV_REG_KEY_ENTRY_20_3 (0x10018b0c) +#ifndef KV_REG_KEY_ENTRY_20_3 #define KV_REG_KEY_ENTRY_20_3 (0xb0c) +#endif #define CLP_KV_REG_KEY_ENTRY_20_4 (0x10018b10) +#ifndef KV_REG_KEY_ENTRY_20_4 #define KV_REG_KEY_ENTRY_20_4 (0xb10) +#endif #define CLP_KV_REG_KEY_ENTRY_20_5 (0x10018b14) +#ifndef KV_REG_KEY_ENTRY_20_5 #define KV_REG_KEY_ENTRY_20_5 (0xb14) +#endif #define CLP_KV_REG_KEY_ENTRY_20_6 (0x10018b18) +#ifndef KV_REG_KEY_ENTRY_20_6 #define KV_REG_KEY_ENTRY_20_6 (0xb18) +#endif #define CLP_KV_REG_KEY_ENTRY_20_7 (0x10018b1c) +#ifndef KV_REG_KEY_ENTRY_20_7 #define KV_REG_KEY_ENTRY_20_7 (0xb1c) +#endif #define CLP_KV_REG_KEY_ENTRY_20_8 (0x10018b20) +#ifndef KV_REG_KEY_ENTRY_20_8 #define KV_REG_KEY_ENTRY_20_8 (0xb20) +#endif #define CLP_KV_REG_KEY_ENTRY_20_9 (0x10018b24) +#ifndef KV_REG_KEY_ENTRY_20_9 #define KV_REG_KEY_ENTRY_20_9 (0xb24) +#endif #define CLP_KV_REG_KEY_ENTRY_20_10 (0x10018b28) +#ifndef KV_REG_KEY_ENTRY_20_10 #define KV_REG_KEY_ENTRY_20_10 (0xb28) +#endif #define CLP_KV_REG_KEY_ENTRY_20_11 (0x10018b2c) +#ifndef KV_REG_KEY_ENTRY_20_11 #define KV_REG_KEY_ENTRY_20_11 (0xb2c) +#endif #define CLP_KV_REG_KEY_ENTRY_20_12 (0x10018b30) +#ifndef KV_REG_KEY_ENTRY_20_12 #define KV_REG_KEY_ENTRY_20_12 (0xb30) +#endif #define CLP_KV_REG_KEY_ENTRY_20_13 (0x10018b34) +#ifndef KV_REG_KEY_ENTRY_20_13 #define KV_REG_KEY_ENTRY_20_13 (0xb34) +#endif #define CLP_KV_REG_KEY_ENTRY_20_14 (0x10018b38) +#ifndef KV_REG_KEY_ENTRY_20_14 #define KV_REG_KEY_ENTRY_20_14 (0xb38) +#endif #define CLP_KV_REG_KEY_ENTRY_20_15 (0x10018b3c) +#ifndef KV_REG_KEY_ENTRY_20_15 #define KV_REG_KEY_ENTRY_20_15 (0xb3c) +#endif #define CLP_KV_REG_KEY_ENTRY_21_0 (0x10018b40) +#ifndef KV_REG_KEY_ENTRY_21_0 #define KV_REG_KEY_ENTRY_21_0 (0xb40) +#endif #define CLP_KV_REG_KEY_ENTRY_21_1 (0x10018b44) +#ifndef KV_REG_KEY_ENTRY_21_1 #define KV_REG_KEY_ENTRY_21_1 (0xb44) +#endif #define CLP_KV_REG_KEY_ENTRY_21_2 (0x10018b48) +#ifndef KV_REG_KEY_ENTRY_21_2 #define KV_REG_KEY_ENTRY_21_2 (0xb48) +#endif #define CLP_KV_REG_KEY_ENTRY_21_3 (0x10018b4c) +#ifndef KV_REG_KEY_ENTRY_21_3 #define KV_REG_KEY_ENTRY_21_3 (0xb4c) +#endif #define CLP_KV_REG_KEY_ENTRY_21_4 (0x10018b50) +#ifndef KV_REG_KEY_ENTRY_21_4 #define KV_REG_KEY_ENTRY_21_4 (0xb50) +#endif #define CLP_KV_REG_KEY_ENTRY_21_5 (0x10018b54) +#ifndef KV_REG_KEY_ENTRY_21_5 #define KV_REG_KEY_ENTRY_21_5 (0xb54) +#endif #define CLP_KV_REG_KEY_ENTRY_21_6 (0x10018b58) +#ifndef KV_REG_KEY_ENTRY_21_6 #define KV_REG_KEY_ENTRY_21_6 (0xb58) +#endif #define CLP_KV_REG_KEY_ENTRY_21_7 (0x10018b5c) +#ifndef KV_REG_KEY_ENTRY_21_7 #define KV_REG_KEY_ENTRY_21_7 (0xb5c) +#endif #define CLP_KV_REG_KEY_ENTRY_21_8 (0x10018b60) +#ifndef KV_REG_KEY_ENTRY_21_8 #define KV_REG_KEY_ENTRY_21_8 (0xb60) +#endif #define CLP_KV_REG_KEY_ENTRY_21_9 (0x10018b64) +#ifndef KV_REG_KEY_ENTRY_21_9 #define KV_REG_KEY_ENTRY_21_9 (0xb64) +#endif #define CLP_KV_REG_KEY_ENTRY_21_10 (0x10018b68) +#ifndef KV_REG_KEY_ENTRY_21_10 #define KV_REG_KEY_ENTRY_21_10 (0xb68) +#endif #define CLP_KV_REG_KEY_ENTRY_21_11 (0x10018b6c) +#ifndef KV_REG_KEY_ENTRY_21_11 #define KV_REG_KEY_ENTRY_21_11 (0xb6c) +#endif #define CLP_KV_REG_KEY_ENTRY_21_12 (0x10018b70) +#ifndef KV_REG_KEY_ENTRY_21_12 #define KV_REG_KEY_ENTRY_21_12 (0xb70) +#endif #define CLP_KV_REG_KEY_ENTRY_21_13 (0x10018b74) +#ifndef KV_REG_KEY_ENTRY_21_13 #define KV_REG_KEY_ENTRY_21_13 (0xb74) +#endif #define CLP_KV_REG_KEY_ENTRY_21_14 (0x10018b78) +#ifndef KV_REG_KEY_ENTRY_21_14 #define KV_REG_KEY_ENTRY_21_14 (0xb78) +#endif #define CLP_KV_REG_KEY_ENTRY_21_15 (0x10018b7c) +#ifndef KV_REG_KEY_ENTRY_21_15 #define KV_REG_KEY_ENTRY_21_15 (0xb7c) +#endif #define CLP_KV_REG_KEY_ENTRY_22_0 (0x10018b80) +#ifndef KV_REG_KEY_ENTRY_22_0 #define KV_REG_KEY_ENTRY_22_0 (0xb80) +#endif #define CLP_KV_REG_KEY_ENTRY_22_1 (0x10018b84) +#ifndef KV_REG_KEY_ENTRY_22_1 #define KV_REG_KEY_ENTRY_22_1 (0xb84) +#endif #define CLP_KV_REG_KEY_ENTRY_22_2 (0x10018b88) +#ifndef KV_REG_KEY_ENTRY_22_2 #define KV_REG_KEY_ENTRY_22_2 (0xb88) +#endif #define CLP_KV_REG_KEY_ENTRY_22_3 (0x10018b8c) +#ifndef KV_REG_KEY_ENTRY_22_3 #define KV_REG_KEY_ENTRY_22_3 (0xb8c) +#endif #define CLP_KV_REG_KEY_ENTRY_22_4 (0x10018b90) +#ifndef KV_REG_KEY_ENTRY_22_4 #define KV_REG_KEY_ENTRY_22_4 (0xb90) +#endif #define CLP_KV_REG_KEY_ENTRY_22_5 (0x10018b94) +#ifndef KV_REG_KEY_ENTRY_22_5 #define KV_REG_KEY_ENTRY_22_5 (0xb94) +#endif #define CLP_KV_REG_KEY_ENTRY_22_6 (0x10018b98) +#ifndef KV_REG_KEY_ENTRY_22_6 #define KV_REG_KEY_ENTRY_22_6 (0xb98) +#endif #define CLP_KV_REG_KEY_ENTRY_22_7 (0x10018b9c) +#ifndef KV_REG_KEY_ENTRY_22_7 #define KV_REG_KEY_ENTRY_22_7 (0xb9c) +#endif #define CLP_KV_REG_KEY_ENTRY_22_8 (0x10018ba0) +#ifndef KV_REG_KEY_ENTRY_22_8 #define KV_REG_KEY_ENTRY_22_8 (0xba0) +#endif #define CLP_KV_REG_KEY_ENTRY_22_9 (0x10018ba4) +#ifndef KV_REG_KEY_ENTRY_22_9 #define KV_REG_KEY_ENTRY_22_9 (0xba4) +#endif #define CLP_KV_REG_KEY_ENTRY_22_10 (0x10018ba8) +#ifndef KV_REG_KEY_ENTRY_22_10 #define KV_REG_KEY_ENTRY_22_10 (0xba8) +#endif #define CLP_KV_REG_KEY_ENTRY_22_11 (0x10018bac) +#ifndef KV_REG_KEY_ENTRY_22_11 #define KV_REG_KEY_ENTRY_22_11 (0xbac) +#endif #define CLP_KV_REG_KEY_ENTRY_22_12 (0x10018bb0) +#ifndef KV_REG_KEY_ENTRY_22_12 #define KV_REG_KEY_ENTRY_22_12 (0xbb0) +#endif #define CLP_KV_REG_KEY_ENTRY_22_13 (0x10018bb4) +#ifndef KV_REG_KEY_ENTRY_22_13 #define KV_REG_KEY_ENTRY_22_13 (0xbb4) +#endif #define CLP_KV_REG_KEY_ENTRY_22_14 (0x10018bb8) +#ifndef KV_REG_KEY_ENTRY_22_14 #define KV_REG_KEY_ENTRY_22_14 (0xbb8) +#endif #define CLP_KV_REG_KEY_ENTRY_22_15 (0x10018bbc) +#ifndef KV_REG_KEY_ENTRY_22_15 #define KV_REG_KEY_ENTRY_22_15 (0xbbc) +#endif #define CLP_KV_REG_KEY_ENTRY_23_0 (0x10018bc0) +#ifndef KV_REG_KEY_ENTRY_23_0 #define KV_REG_KEY_ENTRY_23_0 (0xbc0) +#endif #define CLP_KV_REG_KEY_ENTRY_23_1 (0x10018bc4) +#ifndef KV_REG_KEY_ENTRY_23_1 #define KV_REG_KEY_ENTRY_23_1 (0xbc4) +#endif #define CLP_KV_REG_KEY_ENTRY_23_2 (0x10018bc8) +#ifndef KV_REG_KEY_ENTRY_23_2 #define KV_REG_KEY_ENTRY_23_2 (0xbc8) +#endif #define CLP_KV_REG_KEY_ENTRY_23_3 (0x10018bcc) +#ifndef KV_REG_KEY_ENTRY_23_3 #define KV_REG_KEY_ENTRY_23_3 (0xbcc) +#endif #define CLP_KV_REG_KEY_ENTRY_23_4 (0x10018bd0) +#ifndef KV_REG_KEY_ENTRY_23_4 #define KV_REG_KEY_ENTRY_23_4 (0xbd0) +#endif #define CLP_KV_REG_KEY_ENTRY_23_5 (0x10018bd4) +#ifndef KV_REG_KEY_ENTRY_23_5 #define KV_REG_KEY_ENTRY_23_5 (0xbd4) +#endif #define CLP_KV_REG_KEY_ENTRY_23_6 (0x10018bd8) +#ifndef KV_REG_KEY_ENTRY_23_6 #define KV_REG_KEY_ENTRY_23_6 (0xbd8) +#endif #define CLP_KV_REG_KEY_ENTRY_23_7 (0x10018bdc) +#ifndef KV_REG_KEY_ENTRY_23_7 #define KV_REG_KEY_ENTRY_23_7 (0xbdc) +#endif #define CLP_KV_REG_KEY_ENTRY_23_8 (0x10018be0) +#ifndef KV_REG_KEY_ENTRY_23_8 #define KV_REG_KEY_ENTRY_23_8 (0xbe0) +#endif #define CLP_KV_REG_KEY_ENTRY_23_9 (0x10018be4) +#ifndef KV_REG_KEY_ENTRY_23_9 #define KV_REG_KEY_ENTRY_23_9 (0xbe4) +#endif #define CLP_KV_REG_KEY_ENTRY_23_10 (0x10018be8) +#ifndef KV_REG_KEY_ENTRY_23_10 #define KV_REG_KEY_ENTRY_23_10 (0xbe8) +#endif #define CLP_KV_REG_KEY_ENTRY_23_11 (0x10018bec) +#ifndef KV_REG_KEY_ENTRY_23_11 #define KV_REG_KEY_ENTRY_23_11 (0xbec) +#endif #define CLP_KV_REG_KEY_ENTRY_23_12 (0x10018bf0) +#ifndef KV_REG_KEY_ENTRY_23_12 #define KV_REG_KEY_ENTRY_23_12 (0xbf0) +#endif #define CLP_KV_REG_KEY_ENTRY_23_13 (0x10018bf4) +#ifndef KV_REG_KEY_ENTRY_23_13 #define KV_REG_KEY_ENTRY_23_13 (0xbf4) +#endif #define CLP_KV_REG_KEY_ENTRY_23_14 (0x10018bf8) +#ifndef KV_REG_KEY_ENTRY_23_14 #define KV_REG_KEY_ENTRY_23_14 (0xbf8) +#endif #define CLP_KV_REG_KEY_ENTRY_23_15 (0x10018bfc) +#ifndef KV_REG_KEY_ENTRY_23_15 #define KV_REG_KEY_ENTRY_23_15 (0xbfc) +#endif #define CLP_KV_REG_CLEAR_SECRETS (0x10018c00) +#ifndef KV_REG_CLEAR_SECRETS #define KV_REG_CLEAR_SECRETS (0xc00) #define KV_REG_CLEAR_SECRETS_WR_DEBUG_VALUES_LOW (0) #define KV_REG_CLEAR_SECRETS_WR_DEBUG_VALUES_MASK (0x1) #define KV_REG_CLEAR_SECRETS_SEL_DEBUG_VALUE_LOW (1) #define KV_REG_CLEAR_SECRETS_SEL_DEBUG_VALUE_MASK (0x2) +#endif #define CLP_PV_REG_BASE_ADDR (0x1001a000) #define CLP_PV_REG_PCR_CTRL_0 (0x1001a000) +#ifndef PV_REG_PCR_CTRL_0 #define PV_REG_PCR_CTRL_0 (0x0) #define PV_REG_PCR_CTRL_0_LOCK_LOW (0) #define PV_REG_PCR_CTRL_0_LOCK_MASK (0x1) @@ -2288,7 +3827,9 @@ #define PV_REG_PCR_CTRL_0_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_0_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_0_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_1 (0x1001a004) +#ifndef PV_REG_PCR_CTRL_1 #define PV_REG_PCR_CTRL_1 (0x4) #define PV_REG_PCR_CTRL_1_LOCK_LOW (0) #define PV_REG_PCR_CTRL_1_LOCK_MASK (0x1) @@ -2298,7 +3839,9 @@ #define PV_REG_PCR_CTRL_1_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_1_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_1_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_2 (0x1001a008) +#ifndef PV_REG_PCR_CTRL_2 #define PV_REG_PCR_CTRL_2 (0x8) #define PV_REG_PCR_CTRL_2_LOCK_LOW (0) #define PV_REG_PCR_CTRL_2_LOCK_MASK (0x1) @@ -2308,7 +3851,9 @@ #define PV_REG_PCR_CTRL_2_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_2_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_2_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_3 (0x1001a00c) +#ifndef PV_REG_PCR_CTRL_3 #define PV_REG_PCR_CTRL_3 (0xc) #define PV_REG_PCR_CTRL_3_LOCK_LOW (0) #define PV_REG_PCR_CTRL_3_LOCK_MASK (0x1) @@ -2318,7 +3863,9 @@ #define PV_REG_PCR_CTRL_3_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_3_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_3_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_4 (0x1001a010) +#ifndef PV_REG_PCR_CTRL_4 #define PV_REG_PCR_CTRL_4 (0x10) #define PV_REG_PCR_CTRL_4_LOCK_LOW (0) #define PV_REG_PCR_CTRL_4_LOCK_MASK (0x1) @@ -2328,7 +3875,9 @@ #define PV_REG_PCR_CTRL_4_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_4_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_4_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_5 (0x1001a014) +#ifndef PV_REG_PCR_CTRL_5 #define PV_REG_PCR_CTRL_5 (0x14) #define PV_REG_PCR_CTRL_5_LOCK_LOW (0) #define PV_REG_PCR_CTRL_5_LOCK_MASK (0x1) @@ -2338,7 +3887,9 @@ #define PV_REG_PCR_CTRL_5_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_5_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_5_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_6 (0x1001a018) +#ifndef PV_REG_PCR_CTRL_6 #define PV_REG_PCR_CTRL_6 (0x18) #define PV_REG_PCR_CTRL_6_LOCK_LOW (0) #define PV_REG_PCR_CTRL_6_LOCK_MASK (0x1) @@ -2348,7 +3899,9 @@ #define PV_REG_PCR_CTRL_6_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_6_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_6_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_7 (0x1001a01c) +#ifndef PV_REG_PCR_CTRL_7 #define PV_REG_PCR_CTRL_7 (0x1c) #define PV_REG_PCR_CTRL_7_LOCK_LOW (0) #define PV_REG_PCR_CTRL_7_LOCK_MASK (0x1) @@ -2358,7 +3911,9 @@ #define PV_REG_PCR_CTRL_7_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_7_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_7_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_8 (0x1001a020) +#ifndef PV_REG_PCR_CTRL_8 #define PV_REG_PCR_CTRL_8 (0x20) #define PV_REG_PCR_CTRL_8_LOCK_LOW (0) #define PV_REG_PCR_CTRL_8_LOCK_MASK (0x1) @@ -2368,7 +3923,9 @@ #define PV_REG_PCR_CTRL_8_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_8_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_8_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_9 (0x1001a024) +#ifndef PV_REG_PCR_CTRL_9 #define PV_REG_PCR_CTRL_9 (0x24) #define PV_REG_PCR_CTRL_9_LOCK_LOW (0) #define PV_REG_PCR_CTRL_9_LOCK_MASK (0x1) @@ -2378,7 +3935,9 @@ #define PV_REG_PCR_CTRL_9_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_9_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_9_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_10 (0x1001a028) +#ifndef PV_REG_PCR_CTRL_10 #define PV_REG_PCR_CTRL_10 (0x28) #define PV_REG_PCR_CTRL_10_LOCK_LOW (0) #define PV_REG_PCR_CTRL_10_LOCK_MASK (0x1) @@ -2388,7 +3947,9 @@ #define PV_REG_PCR_CTRL_10_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_10_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_10_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_11 (0x1001a02c) +#ifndef PV_REG_PCR_CTRL_11 #define PV_REG_PCR_CTRL_11 (0x2c) #define PV_REG_PCR_CTRL_11_LOCK_LOW (0) #define PV_REG_PCR_CTRL_11_LOCK_MASK (0x1) @@ -2398,7 +3959,9 @@ #define PV_REG_PCR_CTRL_11_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_11_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_11_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_12 (0x1001a030) +#ifndef PV_REG_PCR_CTRL_12 #define PV_REG_PCR_CTRL_12 (0x30) #define PV_REG_PCR_CTRL_12_LOCK_LOW (0) #define PV_REG_PCR_CTRL_12_LOCK_MASK (0x1) @@ -2408,7 +3971,9 @@ #define PV_REG_PCR_CTRL_12_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_12_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_12_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_13 (0x1001a034) +#ifndef PV_REG_PCR_CTRL_13 #define PV_REG_PCR_CTRL_13 (0x34) #define PV_REG_PCR_CTRL_13_LOCK_LOW (0) #define PV_REG_PCR_CTRL_13_LOCK_MASK (0x1) @@ -2418,7 +3983,9 @@ #define PV_REG_PCR_CTRL_13_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_13_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_13_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_14 (0x1001a038) +#ifndef PV_REG_PCR_CTRL_14 #define PV_REG_PCR_CTRL_14 (0x38) #define PV_REG_PCR_CTRL_14_LOCK_LOW (0) #define PV_REG_PCR_CTRL_14_LOCK_MASK (0x1) @@ -2428,7 +3995,9 @@ #define PV_REG_PCR_CTRL_14_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_14_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_14_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_15 (0x1001a03c) +#ifndef PV_REG_PCR_CTRL_15 #define PV_REG_PCR_CTRL_15 (0x3c) #define PV_REG_PCR_CTRL_15_LOCK_LOW (0) #define PV_REG_PCR_CTRL_15_LOCK_MASK (0x1) @@ -2438,7 +4007,9 @@ #define PV_REG_PCR_CTRL_15_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_15_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_15_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_16 (0x1001a040) +#ifndef PV_REG_PCR_CTRL_16 #define PV_REG_PCR_CTRL_16 (0x40) #define PV_REG_PCR_CTRL_16_LOCK_LOW (0) #define PV_REG_PCR_CTRL_16_LOCK_MASK (0x1) @@ -2448,7 +4019,9 @@ #define PV_REG_PCR_CTRL_16_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_16_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_16_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_17 (0x1001a044) +#ifndef PV_REG_PCR_CTRL_17 #define PV_REG_PCR_CTRL_17 (0x44) #define PV_REG_PCR_CTRL_17_LOCK_LOW (0) #define PV_REG_PCR_CTRL_17_LOCK_MASK (0x1) @@ -2458,7 +4031,9 @@ #define PV_REG_PCR_CTRL_17_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_17_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_17_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_18 (0x1001a048) +#ifndef PV_REG_PCR_CTRL_18 #define PV_REG_PCR_CTRL_18 (0x48) #define PV_REG_PCR_CTRL_18_LOCK_LOW (0) #define PV_REG_PCR_CTRL_18_LOCK_MASK (0x1) @@ -2468,7 +4043,9 @@ #define PV_REG_PCR_CTRL_18_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_18_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_18_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_19 (0x1001a04c) +#ifndef PV_REG_PCR_CTRL_19 #define PV_REG_PCR_CTRL_19 (0x4c) #define PV_REG_PCR_CTRL_19_LOCK_LOW (0) #define PV_REG_PCR_CTRL_19_LOCK_MASK (0x1) @@ -2478,7 +4055,9 @@ #define PV_REG_PCR_CTRL_19_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_19_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_19_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_20 (0x1001a050) +#ifndef PV_REG_PCR_CTRL_20 #define PV_REG_PCR_CTRL_20 (0x50) #define PV_REG_PCR_CTRL_20_LOCK_LOW (0) #define PV_REG_PCR_CTRL_20_LOCK_MASK (0x1) @@ -2488,7 +4067,9 @@ #define PV_REG_PCR_CTRL_20_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_20_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_20_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_21 (0x1001a054) +#ifndef PV_REG_PCR_CTRL_21 #define PV_REG_PCR_CTRL_21 (0x54) #define PV_REG_PCR_CTRL_21_LOCK_LOW (0) #define PV_REG_PCR_CTRL_21_LOCK_MASK (0x1) @@ -2498,7 +4079,9 @@ #define PV_REG_PCR_CTRL_21_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_21_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_21_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_22 (0x1001a058) +#ifndef PV_REG_PCR_CTRL_22 #define PV_REG_PCR_CTRL_22 (0x58) #define PV_REG_PCR_CTRL_22_LOCK_LOW (0) #define PV_REG_PCR_CTRL_22_LOCK_MASK (0x1) @@ -2508,7 +4091,9 @@ #define PV_REG_PCR_CTRL_22_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_22_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_22_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_23 (0x1001a05c) +#ifndef PV_REG_PCR_CTRL_23 #define PV_REG_PCR_CTRL_23 (0x5c) #define PV_REG_PCR_CTRL_23_LOCK_LOW (0) #define PV_REG_PCR_CTRL_23_LOCK_MASK (0x1) @@ -2518,7 +4103,9 @@ #define PV_REG_PCR_CTRL_23_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_23_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_23_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_24 (0x1001a060) +#ifndef PV_REG_PCR_CTRL_24 #define PV_REG_PCR_CTRL_24 (0x60) #define PV_REG_PCR_CTRL_24_LOCK_LOW (0) #define PV_REG_PCR_CTRL_24_LOCK_MASK (0x1) @@ -2528,7 +4115,9 @@ #define PV_REG_PCR_CTRL_24_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_24_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_24_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_25 (0x1001a064) +#ifndef PV_REG_PCR_CTRL_25 #define PV_REG_PCR_CTRL_25 (0x64) #define PV_REG_PCR_CTRL_25_LOCK_LOW (0) #define PV_REG_PCR_CTRL_25_LOCK_MASK (0x1) @@ -2538,7 +4127,9 @@ #define PV_REG_PCR_CTRL_25_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_25_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_25_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_26 (0x1001a068) +#ifndef PV_REG_PCR_CTRL_26 #define PV_REG_PCR_CTRL_26 (0x68) #define PV_REG_PCR_CTRL_26_LOCK_LOW (0) #define PV_REG_PCR_CTRL_26_LOCK_MASK (0x1) @@ -2548,7 +4139,9 @@ #define PV_REG_PCR_CTRL_26_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_26_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_26_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_27 (0x1001a06c) +#ifndef PV_REG_PCR_CTRL_27 #define PV_REG_PCR_CTRL_27 (0x6c) #define PV_REG_PCR_CTRL_27_LOCK_LOW (0) #define PV_REG_PCR_CTRL_27_LOCK_MASK (0x1) @@ -2558,7 +4151,9 @@ #define PV_REG_PCR_CTRL_27_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_27_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_27_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_28 (0x1001a070) +#ifndef PV_REG_PCR_CTRL_28 #define PV_REG_PCR_CTRL_28 (0x70) #define PV_REG_PCR_CTRL_28_LOCK_LOW (0) #define PV_REG_PCR_CTRL_28_LOCK_MASK (0x1) @@ -2568,7 +4163,9 @@ #define PV_REG_PCR_CTRL_28_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_28_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_28_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_29 (0x1001a074) +#ifndef PV_REG_PCR_CTRL_29 #define PV_REG_PCR_CTRL_29 (0x74) #define PV_REG_PCR_CTRL_29_LOCK_LOW (0) #define PV_REG_PCR_CTRL_29_LOCK_MASK (0x1) @@ -2578,7 +4175,9 @@ #define PV_REG_PCR_CTRL_29_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_29_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_29_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_30 (0x1001a078) +#ifndef PV_REG_PCR_CTRL_30 #define PV_REG_PCR_CTRL_30 (0x78) #define PV_REG_PCR_CTRL_30_LOCK_LOW (0) #define PV_REG_PCR_CTRL_30_LOCK_MASK (0x1) @@ -2588,7 +4187,9 @@ #define PV_REG_PCR_CTRL_30_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_30_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_30_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_CTRL_31 (0x1001a07c) +#ifndef PV_REG_PCR_CTRL_31 #define PV_REG_PCR_CTRL_31 (0x7c) #define PV_REG_PCR_CTRL_31_LOCK_LOW (0) #define PV_REG_PCR_CTRL_31_LOCK_MASK (0x1) @@ -2598,1469 +4199,2855 @@ #define PV_REG_PCR_CTRL_31_RSVD0_MASK (0x4) #define PV_REG_PCR_CTRL_31_RSVD1_LOW (3) #define PV_REG_PCR_CTRL_31_RSVD1_MASK (0xf8) +#endif #define CLP_PV_REG_PCR_ENTRY_0_0 (0x1001a600) +#ifndef PV_REG_PCR_ENTRY_0_0 #define PV_REG_PCR_ENTRY_0_0 (0x600) +#endif #define CLP_PV_REG_PCR_ENTRY_0_1 (0x1001a604) +#ifndef PV_REG_PCR_ENTRY_0_1 #define PV_REG_PCR_ENTRY_0_1 (0x604) +#endif #define CLP_PV_REG_PCR_ENTRY_0_2 (0x1001a608) +#ifndef PV_REG_PCR_ENTRY_0_2 #define PV_REG_PCR_ENTRY_0_2 (0x608) +#endif #define CLP_PV_REG_PCR_ENTRY_0_3 (0x1001a60c) +#ifndef PV_REG_PCR_ENTRY_0_3 #define PV_REG_PCR_ENTRY_0_3 (0x60c) +#endif #define CLP_PV_REG_PCR_ENTRY_0_4 (0x1001a610) +#ifndef PV_REG_PCR_ENTRY_0_4 #define PV_REG_PCR_ENTRY_0_4 (0x610) +#endif #define CLP_PV_REG_PCR_ENTRY_0_5 (0x1001a614) +#ifndef PV_REG_PCR_ENTRY_0_5 #define PV_REG_PCR_ENTRY_0_5 (0x614) +#endif #define CLP_PV_REG_PCR_ENTRY_0_6 (0x1001a618) +#ifndef PV_REG_PCR_ENTRY_0_6 #define PV_REG_PCR_ENTRY_0_6 (0x618) +#endif #define CLP_PV_REG_PCR_ENTRY_0_7 (0x1001a61c) +#ifndef PV_REG_PCR_ENTRY_0_7 #define PV_REG_PCR_ENTRY_0_7 (0x61c) +#endif #define CLP_PV_REG_PCR_ENTRY_0_8 (0x1001a620) +#ifndef PV_REG_PCR_ENTRY_0_8 #define PV_REG_PCR_ENTRY_0_8 (0x620) +#endif #define CLP_PV_REG_PCR_ENTRY_0_9 (0x1001a624) +#ifndef PV_REG_PCR_ENTRY_0_9 #define PV_REG_PCR_ENTRY_0_9 (0x624) +#endif #define CLP_PV_REG_PCR_ENTRY_0_10 (0x1001a628) +#ifndef PV_REG_PCR_ENTRY_0_10 #define PV_REG_PCR_ENTRY_0_10 (0x628) +#endif #define CLP_PV_REG_PCR_ENTRY_0_11 (0x1001a62c) +#ifndef PV_REG_PCR_ENTRY_0_11 #define PV_REG_PCR_ENTRY_0_11 (0x62c) +#endif #define CLP_PV_REG_PCR_ENTRY_1_0 (0x1001a630) +#ifndef PV_REG_PCR_ENTRY_1_0 #define PV_REG_PCR_ENTRY_1_0 (0x630) +#endif #define CLP_PV_REG_PCR_ENTRY_1_1 (0x1001a634) +#ifndef PV_REG_PCR_ENTRY_1_1 #define PV_REG_PCR_ENTRY_1_1 (0x634) +#endif #define CLP_PV_REG_PCR_ENTRY_1_2 (0x1001a638) +#ifndef PV_REG_PCR_ENTRY_1_2 #define PV_REG_PCR_ENTRY_1_2 (0x638) +#endif #define CLP_PV_REG_PCR_ENTRY_1_3 (0x1001a63c) +#ifndef PV_REG_PCR_ENTRY_1_3 #define PV_REG_PCR_ENTRY_1_3 (0x63c) +#endif #define CLP_PV_REG_PCR_ENTRY_1_4 (0x1001a640) +#ifndef PV_REG_PCR_ENTRY_1_4 #define PV_REG_PCR_ENTRY_1_4 (0x640) +#endif #define CLP_PV_REG_PCR_ENTRY_1_5 (0x1001a644) +#ifndef PV_REG_PCR_ENTRY_1_5 #define PV_REG_PCR_ENTRY_1_5 (0x644) +#endif #define CLP_PV_REG_PCR_ENTRY_1_6 (0x1001a648) +#ifndef PV_REG_PCR_ENTRY_1_6 #define PV_REG_PCR_ENTRY_1_6 (0x648) +#endif #define CLP_PV_REG_PCR_ENTRY_1_7 (0x1001a64c) +#ifndef PV_REG_PCR_ENTRY_1_7 #define PV_REG_PCR_ENTRY_1_7 (0x64c) +#endif #define CLP_PV_REG_PCR_ENTRY_1_8 (0x1001a650) +#ifndef PV_REG_PCR_ENTRY_1_8 #define PV_REG_PCR_ENTRY_1_8 (0x650) +#endif #define CLP_PV_REG_PCR_ENTRY_1_9 (0x1001a654) +#ifndef PV_REG_PCR_ENTRY_1_9 #define PV_REG_PCR_ENTRY_1_9 (0x654) +#endif #define CLP_PV_REG_PCR_ENTRY_1_10 (0x1001a658) +#ifndef PV_REG_PCR_ENTRY_1_10 #define PV_REG_PCR_ENTRY_1_10 (0x658) +#endif #define CLP_PV_REG_PCR_ENTRY_1_11 (0x1001a65c) +#ifndef PV_REG_PCR_ENTRY_1_11 #define PV_REG_PCR_ENTRY_1_11 (0x65c) +#endif #define CLP_PV_REG_PCR_ENTRY_2_0 (0x1001a660) +#ifndef PV_REG_PCR_ENTRY_2_0 #define PV_REG_PCR_ENTRY_2_0 (0x660) +#endif #define CLP_PV_REG_PCR_ENTRY_2_1 (0x1001a664) +#ifndef PV_REG_PCR_ENTRY_2_1 #define PV_REG_PCR_ENTRY_2_1 (0x664) +#endif #define CLP_PV_REG_PCR_ENTRY_2_2 (0x1001a668) +#ifndef PV_REG_PCR_ENTRY_2_2 #define PV_REG_PCR_ENTRY_2_2 (0x668) +#endif #define CLP_PV_REG_PCR_ENTRY_2_3 (0x1001a66c) +#ifndef PV_REG_PCR_ENTRY_2_3 #define PV_REG_PCR_ENTRY_2_3 (0x66c) +#endif #define CLP_PV_REG_PCR_ENTRY_2_4 (0x1001a670) +#ifndef PV_REG_PCR_ENTRY_2_4 #define PV_REG_PCR_ENTRY_2_4 (0x670) +#endif #define CLP_PV_REG_PCR_ENTRY_2_5 (0x1001a674) +#ifndef PV_REG_PCR_ENTRY_2_5 #define PV_REG_PCR_ENTRY_2_5 (0x674) +#endif #define CLP_PV_REG_PCR_ENTRY_2_6 (0x1001a678) +#ifndef PV_REG_PCR_ENTRY_2_6 #define PV_REG_PCR_ENTRY_2_6 (0x678) +#endif #define CLP_PV_REG_PCR_ENTRY_2_7 (0x1001a67c) +#ifndef PV_REG_PCR_ENTRY_2_7 #define PV_REG_PCR_ENTRY_2_7 (0x67c) +#endif #define CLP_PV_REG_PCR_ENTRY_2_8 (0x1001a680) +#ifndef PV_REG_PCR_ENTRY_2_8 #define PV_REG_PCR_ENTRY_2_8 (0x680) +#endif #define CLP_PV_REG_PCR_ENTRY_2_9 (0x1001a684) +#ifndef PV_REG_PCR_ENTRY_2_9 #define PV_REG_PCR_ENTRY_2_9 (0x684) +#endif #define CLP_PV_REG_PCR_ENTRY_2_10 (0x1001a688) +#ifndef PV_REG_PCR_ENTRY_2_10 #define PV_REG_PCR_ENTRY_2_10 (0x688) +#endif #define CLP_PV_REG_PCR_ENTRY_2_11 (0x1001a68c) +#ifndef PV_REG_PCR_ENTRY_2_11 #define PV_REG_PCR_ENTRY_2_11 (0x68c) +#endif #define CLP_PV_REG_PCR_ENTRY_3_0 (0x1001a690) +#ifndef PV_REG_PCR_ENTRY_3_0 #define PV_REG_PCR_ENTRY_3_0 (0x690) +#endif #define CLP_PV_REG_PCR_ENTRY_3_1 (0x1001a694) +#ifndef PV_REG_PCR_ENTRY_3_1 #define PV_REG_PCR_ENTRY_3_1 (0x694) +#endif #define CLP_PV_REG_PCR_ENTRY_3_2 (0x1001a698) +#ifndef PV_REG_PCR_ENTRY_3_2 #define PV_REG_PCR_ENTRY_3_2 (0x698) +#endif #define CLP_PV_REG_PCR_ENTRY_3_3 (0x1001a69c) +#ifndef PV_REG_PCR_ENTRY_3_3 #define PV_REG_PCR_ENTRY_3_3 (0x69c) +#endif #define CLP_PV_REG_PCR_ENTRY_3_4 (0x1001a6a0) +#ifndef PV_REG_PCR_ENTRY_3_4 #define PV_REG_PCR_ENTRY_3_4 (0x6a0) +#endif #define CLP_PV_REG_PCR_ENTRY_3_5 (0x1001a6a4) +#ifndef PV_REG_PCR_ENTRY_3_5 #define PV_REG_PCR_ENTRY_3_5 (0x6a4) +#endif #define CLP_PV_REG_PCR_ENTRY_3_6 (0x1001a6a8) +#ifndef PV_REG_PCR_ENTRY_3_6 #define PV_REG_PCR_ENTRY_3_6 (0x6a8) +#endif #define CLP_PV_REG_PCR_ENTRY_3_7 (0x1001a6ac) +#ifndef PV_REG_PCR_ENTRY_3_7 #define PV_REG_PCR_ENTRY_3_7 (0x6ac) +#endif #define CLP_PV_REG_PCR_ENTRY_3_8 (0x1001a6b0) +#ifndef PV_REG_PCR_ENTRY_3_8 #define PV_REG_PCR_ENTRY_3_8 (0x6b0) +#endif #define CLP_PV_REG_PCR_ENTRY_3_9 (0x1001a6b4) +#ifndef PV_REG_PCR_ENTRY_3_9 #define PV_REG_PCR_ENTRY_3_9 (0x6b4) +#endif #define CLP_PV_REG_PCR_ENTRY_3_10 (0x1001a6b8) +#ifndef PV_REG_PCR_ENTRY_3_10 #define PV_REG_PCR_ENTRY_3_10 (0x6b8) +#endif #define CLP_PV_REG_PCR_ENTRY_3_11 (0x1001a6bc) +#ifndef PV_REG_PCR_ENTRY_3_11 #define PV_REG_PCR_ENTRY_3_11 (0x6bc) +#endif #define CLP_PV_REG_PCR_ENTRY_4_0 (0x1001a6c0) +#ifndef PV_REG_PCR_ENTRY_4_0 #define PV_REG_PCR_ENTRY_4_0 (0x6c0) +#endif #define CLP_PV_REG_PCR_ENTRY_4_1 (0x1001a6c4) +#ifndef PV_REG_PCR_ENTRY_4_1 #define PV_REG_PCR_ENTRY_4_1 (0x6c4) +#endif #define CLP_PV_REG_PCR_ENTRY_4_2 (0x1001a6c8) +#ifndef PV_REG_PCR_ENTRY_4_2 #define PV_REG_PCR_ENTRY_4_2 (0x6c8) +#endif #define CLP_PV_REG_PCR_ENTRY_4_3 (0x1001a6cc) +#ifndef PV_REG_PCR_ENTRY_4_3 #define PV_REG_PCR_ENTRY_4_3 (0x6cc) +#endif #define CLP_PV_REG_PCR_ENTRY_4_4 (0x1001a6d0) +#ifndef PV_REG_PCR_ENTRY_4_4 #define PV_REG_PCR_ENTRY_4_4 (0x6d0) +#endif #define CLP_PV_REG_PCR_ENTRY_4_5 (0x1001a6d4) +#ifndef PV_REG_PCR_ENTRY_4_5 #define PV_REG_PCR_ENTRY_4_5 (0x6d4) +#endif #define CLP_PV_REG_PCR_ENTRY_4_6 (0x1001a6d8) +#ifndef PV_REG_PCR_ENTRY_4_6 #define PV_REG_PCR_ENTRY_4_6 (0x6d8) +#endif #define CLP_PV_REG_PCR_ENTRY_4_7 (0x1001a6dc) +#ifndef PV_REG_PCR_ENTRY_4_7 #define PV_REG_PCR_ENTRY_4_7 (0x6dc) +#endif #define CLP_PV_REG_PCR_ENTRY_4_8 (0x1001a6e0) +#ifndef PV_REG_PCR_ENTRY_4_8 #define PV_REG_PCR_ENTRY_4_8 (0x6e0) +#endif #define CLP_PV_REG_PCR_ENTRY_4_9 (0x1001a6e4) +#ifndef PV_REG_PCR_ENTRY_4_9 #define PV_REG_PCR_ENTRY_4_9 (0x6e4) +#endif #define CLP_PV_REG_PCR_ENTRY_4_10 (0x1001a6e8) +#ifndef PV_REG_PCR_ENTRY_4_10 #define PV_REG_PCR_ENTRY_4_10 (0x6e8) +#endif #define CLP_PV_REG_PCR_ENTRY_4_11 (0x1001a6ec) +#ifndef PV_REG_PCR_ENTRY_4_11 #define PV_REG_PCR_ENTRY_4_11 (0x6ec) +#endif #define CLP_PV_REG_PCR_ENTRY_5_0 (0x1001a6f0) +#ifndef PV_REG_PCR_ENTRY_5_0 #define PV_REG_PCR_ENTRY_5_0 (0x6f0) +#endif #define CLP_PV_REG_PCR_ENTRY_5_1 (0x1001a6f4) +#ifndef PV_REG_PCR_ENTRY_5_1 #define PV_REG_PCR_ENTRY_5_1 (0x6f4) +#endif #define CLP_PV_REG_PCR_ENTRY_5_2 (0x1001a6f8) +#ifndef PV_REG_PCR_ENTRY_5_2 #define PV_REG_PCR_ENTRY_5_2 (0x6f8) +#endif #define CLP_PV_REG_PCR_ENTRY_5_3 (0x1001a6fc) +#ifndef PV_REG_PCR_ENTRY_5_3 #define PV_REG_PCR_ENTRY_5_3 (0x6fc) +#endif #define CLP_PV_REG_PCR_ENTRY_5_4 (0x1001a700) +#ifndef PV_REG_PCR_ENTRY_5_4 #define PV_REG_PCR_ENTRY_5_4 (0x700) +#endif #define CLP_PV_REG_PCR_ENTRY_5_5 (0x1001a704) +#ifndef PV_REG_PCR_ENTRY_5_5 #define PV_REG_PCR_ENTRY_5_5 (0x704) +#endif #define CLP_PV_REG_PCR_ENTRY_5_6 (0x1001a708) +#ifndef PV_REG_PCR_ENTRY_5_6 #define PV_REG_PCR_ENTRY_5_6 (0x708) +#endif #define CLP_PV_REG_PCR_ENTRY_5_7 (0x1001a70c) +#ifndef PV_REG_PCR_ENTRY_5_7 #define PV_REG_PCR_ENTRY_5_7 (0x70c) +#endif #define CLP_PV_REG_PCR_ENTRY_5_8 (0x1001a710) +#ifndef PV_REG_PCR_ENTRY_5_8 #define PV_REG_PCR_ENTRY_5_8 (0x710) +#endif #define CLP_PV_REG_PCR_ENTRY_5_9 (0x1001a714) +#ifndef PV_REG_PCR_ENTRY_5_9 #define PV_REG_PCR_ENTRY_5_9 (0x714) +#endif #define CLP_PV_REG_PCR_ENTRY_5_10 (0x1001a718) +#ifndef PV_REG_PCR_ENTRY_5_10 #define PV_REG_PCR_ENTRY_5_10 (0x718) +#endif #define CLP_PV_REG_PCR_ENTRY_5_11 (0x1001a71c) +#ifndef PV_REG_PCR_ENTRY_5_11 #define PV_REG_PCR_ENTRY_5_11 (0x71c) +#endif #define CLP_PV_REG_PCR_ENTRY_6_0 (0x1001a720) +#ifndef PV_REG_PCR_ENTRY_6_0 #define PV_REG_PCR_ENTRY_6_0 (0x720) +#endif #define CLP_PV_REG_PCR_ENTRY_6_1 (0x1001a724) +#ifndef PV_REG_PCR_ENTRY_6_1 #define PV_REG_PCR_ENTRY_6_1 (0x724) +#endif #define CLP_PV_REG_PCR_ENTRY_6_2 (0x1001a728) +#ifndef PV_REG_PCR_ENTRY_6_2 #define PV_REG_PCR_ENTRY_6_2 (0x728) +#endif #define CLP_PV_REG_PCR_ENTRY_6_3 (0x1001a72c) +#ifndef PV_REG_PCR_ENTRY_6_3 #define PV_REG_PCR_ENTRY_6_3 (0x72c) +#endif #define CLP_PV_REG_PCR_ENTRY_6_4 (0x1001a730) +#ifndef PV_REG_PCR_ENTRY_6_4 #define PV_REG_PCR_ENTRY_6_4 (0x730) +#endif #define CLP_PV_REG_PCR_ENTRY_6_5 (0x1001a734) +#ifndef PV_REG_PCR_ENTRY_6_5 #define PV_REG_PCR_ENTRY_6_5 (0x734) +#endif #define CLP_PV_REG_PCR_ENTRY_6_6 (0x1001a738) +#ifndef PV_REG_PCR_ENTRY_6_6 #define PV_REG_PCR_ENTRY_6_6 (0x738) +#endif #define CLP_PV_REG_PCR_ENTRY_6_7 (0x1001a73c) +#ifndef PV_REG_PCR_ENTRY_6_7 #define PV_REG_PCR_ENTRY_6_7 (0x73c) +#endif #define CLP_PV_REG_PCR_ENTRY_6_8 (0x1001a740) +#ifndef PV_REG_PCR_ENTRY_6_8 #define PV_REG_PCR_ENTRY_6_8 (0x740) +#endif #define CLP_PV_REG_PCR_ENTRY_6_9 (0x1001a744) +#ifndef PV_REG_PCR_ENTRY_6_9 #define PV_REG_PCR_ENTRY_6_9 (0x744) +#endif #define CLP_PV_REG_PCR_ENTRY_6_10 (0x1001a748) +#ifndef PV_REG_PCR_ENTRY_6_10 #define PV_REG_PCR_ENTRY_6_10 (0x748) +#endif #define CLP_PV_REG_PCR_ENTRY_6_11 (0x1001a74c) +#ifndef PV_REG_PCR_ENTRY_6_11 #define PV_REG_PCR_ENTRY_6_11 (0x74c) +#endif #define CLP_PV_REG_PCR_ENTRY_7_0 (0x1001a750) +#ifndef PV_REG_PCR_ENTRY_7_0 #define PV_REG_PCR_ENTRY_7_0 (0x750) +#endif #define CLP_PV_REG_PCR_ENTRY_7_1 (0x1001a754) +#ifndef PV_REG_PCR_ENTRY_7_1 #define PV_REG_PCR_ENTRY_7_1 (0x754) +#endif #define CLP_PV_REG_PCR_ENTRY_7_2 (0x1001a758) +#ifndef PV_REG_PCR_ENTRY_7_2 #define PV_REG_PCR_ENTRY_7_2 (0x758) +#endif #define CLP_PV_REG_PCR_ENTRY_7_3 (0x1001a75c) +#ifndef PV_REG_PCR_ENTRY_7_3 #define PV_REG_PCR_ENTRY_7_3 (0x75c) +#endif #define CLP_PV_REG_PCR_ENTRY_7_4 (0x1001a760) +#ifndef PV_REG_PCR_ENTRY_7_4 #define PV_REG_PCR_ENTRY_7_4 (0x760) +#endif #define CLP_PV_REG_PCR_ENTRY_7_5 (0x1001a764) +#ifndef PV_REG_PCR_ENTRY_7_5 #define PV_REG_PCR_ENTRY_7_5 (0x764) +#endif #define CLP_PV_REG_PCR_ENTRY_7_6 (0x1001a768) +#ifndef PV_REG_PCR_ENTRY_7_6 #define PV_REG_PCR_ENTRY_7_6 (0x768) +#endif #define CLP_PV_REG_PCR_ENTRY_7_7 (0x1001a76c) +#ifndef PV_REG_PCR_ENTRY_7_7 #define PV_REG_PCR_ENTRY_7_7 (0x76c) +#endif #define CLP_PV_REG_PCR_ENTRY_7_8 (0x1001a770) +#ifndef PV_REG_PCR_ENTRY_7_8 #define PV_REG_PCR_ENTRY_7_8 (0x770) +#endif #define CLP_PV_REG_PCR_ENTRY_7_9 (0x1001a774) +#ifndef PV_REG_PCR_ENTRY_7_9 #define PV_REG_PCR_ENTRY_7_9 (0x774) +#endif #define CLP_PV_REG_PCR_ENTRY_7_10 (0x1001a778) +#ifndef PV_REG_PCR_ENTRY_7_10 #define PV_REG_PCR_ENTRY_7_10 (0x778) +#endif #define CLP_PV_REG_PCR_ENTRY_7_11 (0x1001a77c) +#ifndef PV_REG_PCR_ENTRY_7_11 #define PV_REG_PCR_ENTRY_7_11 (0x77c) +#endif #define CLP_PV_REG_PCR_ENTRY_8_0 (0x1001a780) +#ifndef PV_REG_PCR_ENTRY_8_0 #define PV_REG_PCR_ENTRY_8_0 (0x780) +#endif #define CLP_PV_REG_PCR_ENTRY_8_1 (0x1001a784) +#ifndef PV_REG_PCR_ENTRY_8_1 #define PV_REG_PCR_ENTRY_8_1 (0x784) +#endif #define CLP_PV_REG_PCR_ENTRY_8_2 (0x1001a788) +#ifndef PV_REG_PCR_ENTRY_8_2 #define PV_REG_PCR_ENTRY_8_2 (0x788) +#endif #define CLP_PV_REG_PCR_ENTRY_8_3 (0x1001a78c) +#ifndef PV_REG_PCR_ENTRY_8_3 #define PV_REG_PCR_ENTRY_8_3 (0x78c) +#endif #define CLP_PV_REG_PCR_ENTRY_8_4 (0x1001a790) +#ifndef PV_REG_PCR_ENTRY_8_4 #define PV_REG_PCR_ENTRY_8_4 (0x790) +#endif #define CLP_PV_REG_PCR_ENTRY_8_5 (0x1001a794) +#ifndef PV_REG_PCR_ENTRY_8_5 #define PV_REG_PCR_ENTRY_8_5 (0x794) +#endif #define CLP_PV_REG_PCR_ENTRY_8_6 (0x1001a798) +#ifndef PV_REG_PCR_ENTRY_8_6 #define PV_REG_PCR_ENTRY_8_6 (0x798) +#endif #define CLP_PV_REG_PCR_ENTRY_8_7 (0x1001a79c) +#ifndef PV_REG_PCR_ENTRY_8_7 #define PV_REG_PCR_ENTRY_8_7 (0x79c) +#endif #define CLP_PV_REG_PCR_ENTRY_8_8 (0x1001a7a0) +#ifndef PV_REG_PCR_ENTRY_8_8 #define PV_REG_PCR_ENTRY_8_8 (0x7a0) +#endif #define CLP_PV_REG_PCR_ENTRY_8_9 (0x1001a7a4) +#ifndef PV_REG_PCR_ENTRY_8_9 #define PV_REG_PCR_ENTRY_8_9 (0x7a4) +#endif #define CLP_PV_REG_PCR_ENTRY_8_10 (0x1001a7a8) +#ifndef PV_REG_PCR_ENTRY_8_10 #define PV_REG_PCR_ENTRY_8_10 (0x7a8) +#endif #define CLP_PV_REG_PCR_ENTRY_8_11 (0x1001a7ac) +#ifndef PV_REG_PCR_ENTRY_8_11 #define PV_REG_PCR_ENTRY_8_11 (0x7ac) +#endif #define CLP_PV_REG_PCR_ENTRY_9_0 (0x1001a7b0) +#ifndef PV_REG_PCR_ENTRY_9_0 #define PV_REG_PCR_ENTRY_9_0 (0x7b0) +#endif #define CLP_PV_REG_PCR_ENTRY_9_1 (0x1001a7b4) +#ifndef PV_REG_PCR_ENTRY_9_1 #define PV_REG_PCR_ENTRY_9_1 (0x7b4) +#endif #define CLP_PV_REG_PCR_ENTRY_9_2 (0x1001a7b8) +#ifndef PV_REG_PCR_ENTRY_9_2 #define PV_REG_PCR_ENTRY_9_2 (0x7b8) +#endif #define CLP_PV_REG_PCR_ENTRY_9_3 (0x1001a7bc) +#ifndef PV_REG_PCR_ENTRY_9_3 #define PV_REG_PCR_ENTRY_9_3 (0x7bc) +#endif #define CLP_PV_REG_PCR_ENTRY_9_4 (0x1001a7c0) +#ifndef PV_REG_PCR_ENTRY_9_4 #define PV_REG_PCR_ENTRY_9_4 (0x7c0) +#endif #define CLP_PV_REG_PCR_ENTRY_9_5 (0x1001a7c4) +#ifndef PV_REG_PCR_ENTRY_9_5 #define PV_REG_PCR_ENTRY_9_5 (0x7c4) +#endif #define CLP_PV_REG_PCR_ENTRY_9_6 (0x1001a7c8) +#ifndef PV_REG_PCR_ENTRY_9_6 #define PV_REG_PCR_ENTRY_9_6 (0x7c8) +#endif #define CLP_PV_REG_PCR_ENTRY_9_7 (0x1001a7cc) +#ifndef PV_REG_PCR_ENTRY_9_7 #define PV_REG_PCR_ENTRY_9_7 (0x7cc) +#endif #define CLP_PV_REG_PCR_ENTRY_9_8 (0x1001a7d0) +#ifndef PV_REG_PCR_ENTRY_9_8 #define PV_REG_PCR_ENTRY_9_8 (0x7d0) +#endif #define CLP_PV_REG_PCR_ENTRY_9_9 (0x1001a7d4) +#ifndef PV_REG_PCR_ENTRY_9_9 #define PV_REG_PCR_ENTRY_9_9 (0x7d4) +#endif #define CLP_PV_REG_PCR_ENTRY_9_10 (0x1001a7d8) +#ifndef PV_REG_PCR_ENTRY_9_10 #define PV_REG_PCR_ENTRY_9_10 (0x7d8) +#endif #define CLP_PV_REG_PCR_ENTRY_9_11 (0x1001a7dc) +#ifndef PV_REG_PCR_ENTRY_9_11 #define PV_REG_PCR_ENTRY_9_11 (0x7dc) +#endif #define CLP_PV_REG_PCR_ENTRY_10_0 (0x1001a7e0) +#ifndef PV_REG_PCR_ENTRY_10_0 #define PV_REG_PCR_ENTRY_10_0 (0x7e0) +#endif #define CLP_PV_REG_PCR_ENTRY_10_1 (0x1001a7e4) +#ifndef PV_REG_PCR_ENTRY_10_1 #define PV_REG_PCR_ENTRY_10_1 (0x7e4) +#endif #define CLP_PV_REG_PCR_ENTRY_10_2 (0x1001a7e8) +#ifndef PV_REG_PCR_ENTRY_10_2 #define PV_REG_PCR_ENTRY_10_2 (0x7e8) +#endif #define CLP_PV_REG_PCR_ENTRY_10_3 (0x1001a7ec) +#ifndef PV_REG_PCR_ENTRY_10_3 #define PV_REG_PCR_ENTRY_10_3 (0x7ec) +#endif #define CLP_PV_REG_PCR_ENTRY_10_4 (0x1001a7f0) +#ifndef PV_REG_PCR_ENTRY_10_4 #define PV_REG_PCR_ENTRY_10_4 (0x7f0) +#endif #define CLP_PV_REG_PCR_ENTRY_10_5 (0x1001a7f4) +#ifndef PV_REG_PCR_ENTRY_10_5 #define PV_REG_PCR_ENTRY_10_5 (0x7f4) +#endif #define CLP_PV_REG_PCR_ENTRY_10_6 (0x1001a7f8) +#ifndef PV_REG_PCR_ENTRY_10_6 #define PV_REG_PCR_ENTRY_10_6 (0x7f8) +#endif #define CLP_PV_REG_PCR_ENTRY_10_7 (0x1001a7fc) +#ifndef PV_REG_PCR_ENTRY_10_7 #define PV_REG_PCR_ENTRY_10_7 (0x7fc) +#endif #define CLP_PV_REG_PCR_ENTRY_10_8 (0x1001a800) +#ifndef PV_REG_PCR_ENTRY_10_8 #define PV_REG_PCR_ENTRY_10_8 (0x800) +#endif #define CLP_PV_REG_PCR_ENTRY_10_9 (0x1001a804) +#ifndef PV_REG_PCR_ENTRY_10_9 #define PV_REG_PCR_ENTRY_10_9 (0x804) +#endif #define CLP_PV_REG_PCR_ENTRY_10_10 (0x1001a808) +#ifndef PV_REG_PCR_ENTRY_10_10 #define PV_REG_PCR_ENTRY_10_10 (0x808) +#endif #define CLP_PV_REG_PCR_ENTRY_10_11 (0x1001a80c) +#ifndef PV_REG_PCR_ENTRY_10_11 #define PV_REG_PCR_ENTRY_10_11 (0x80c) +#endif #define CLP_PV_REG_PCR_ENTRY_11_0 (0x1001a810) +#ifndef PV_REG_PCR_ENTRY_11_0 #define PV_REG_PCR_ENTRY_11_0 (0x810) +#endif #define CLP_PV_REG_PCR_ENTRY_11_1 (0x1001a814) +#ifndef PV_REG_PCR_ENTRY_11_1 #define PV_REG_PCR_ENTRY_11_1 (0x814) +#endif #define CLP_PV_REG_PCR_ENTRY_11_2 (0x1001a818) +#ifndef PV_REG_PCR_ENTRY_11_2 #define PV_REG_PCR_ENTRY_11_2 (0x818) +#endif #define CLP_PV_REG_PCR_ENTRY_11_3 (0x1001a81c) +#ifndef PV_REG_PCR_ENTRY_11_3 #define PV_REG_PCR_ENTRY_11_3 (0x81c) +#endif #define CLP_PV_REG_PCR_ENTRY_11_4 (0x1001a820) +#ifndef PV_REG_PCR_ENTRY_11_4 #define PV_REG_PCR_ENTRY_11_4 (0x820) +#endif #define CLP_PV_REG_PCR_ENTRY_11_5 (0x1001a824) +#ifndef PV_REG_PCR_ENTRY_11_5 #define PV_REG_PCR_ENTRY_11_5 (0x824) +#endif #define CLP_PV_REG_PCR_ENTRY_11_6 (0x1001a828) +#ifndef PV_REG_PCR_ENTRY_11_6 #define PV_REG_PCR_ENTRY_11_6 (0x828) +#endif #define CLP_PV_REG_PCR_ENTRY_11_7 (0x1001a82c) +#ifndef PV_REG_PCR_ENTRY_11_7 #define PV_REG_PCR_ENTRY_11_7 (0x82c) +#endif #define CLP_PV_REG_PCR_ENTRY_11_8 (0x1001a830) +#ifndef PV_REG_PCR_ENTRY_11_8 #define PV_REG_PCR_ENTRY_11_8 (0x830) +#endif #define CLP_PV_REG_PCR_ENTRY_11_9 (0x1001a834) +#ifndef PV_REG_PCR_ENTRY_11_9 #define PV_REG_PCR_ENTRY_11_9 (0x834) +#endif #define CLP_PV_REG_PCR_ENTRY_11_10 (0x1001a838) +#ifndef PV_REG_PCR_ENTRY_11_10 #define PV_REG_PCR_ENTRY_11_10 (0x838) +#endif #define CLP_PV_REG_PCR_ENTRY_11_11 (0x1001a83c) +#ifndef PV_REG_PCR_ENTRY_11_11 #define PV_REG_PCR_ENTRY_11_11 (0x83c) +#endif #define CLP_PV_REG_PCR_ENTRY_12_0 (0x1001a840) +#ifndef PV_REG_PCR_ENTRY_12_0 #define PV_REG_PCR_ENTRY_12_0 (0x840) +#endif #define CLP_PV_REG_PCR_ENTRY_12_1 (0x1001a844) +#ifndef PV_REG_PCR_ENTRY_12_1 #define PV_REG_PCR_ENTRY_12_1 (0x844) +#endif #define CLP_PV_REG_PCR_ENTRY_12_2 (0x1001a848) +#ifndef PV_REG_PCR_ENTRY_12_2 #define PV_REG_PCR_ENTRY_12_2 (0x848) +#endif #define CLP_PV_REG_PCR_ENTRY_12_3 (0x1001a84c) +#ifndef PV_REG_PCR_ENTRY_12_3 #define PV_REG_PCR_ENTRY_12_3 (0x84c) +#endif #define CLP_PV_REG_PCR_ENTRY_12_4 (0x1001a850) +#ifndef PV_REG_PCR_ENTRY_12_4 #define PV_REG_PCR_ENTRY_12_4 (0x850) +#endif #define CLP_PV_REG_PCR_ENTRY_12_5 (0x1001a854) +#ifndef PV_REG_PCR_ENTRY_12_5 #define PV_REG_PCR_ENTRY_12_5 (0x854) +#endif #define CLP_PV_REG_PCR_ENTRY_12_6 (0x1001a858) +#ifndef PV_REG_PCR_ENTRY_12_6 #define PV_REG_PCR_ENTRY_12_6 (0x858) +#endif #define CLP_PV_REG_PCR_ENTRY_12_7 (0x1001a85c) +#ifndef PV_REG_PCR_ENTRY_12_7 #define PV_REG_PCR_ENTRY_12_7 (0x85c) +#endif #define CLP_PV_REG_PCR_ENTRY_12_8 (0x1001a860) +#ifndef PV_REG_PCR_ENTRY_12_8 #define PV_REG_PCR_ENTRY_12_8 (0x860) +#endif #define CLP_PV_REG_PCR_ENTRY_12_9 (0x1001a864) +#ifndef PV_REG_PCR_ENTRY_12_9 #define PV_REG_PCR_ENTRY_12_9 (0x864) +#endif #define CLP_PV_REG_PCR_ENTRY_12_10 (0x1001a868) +#ifndef PV_REG_PCR_ENTRY_12_10 #define PV_REG_PCR_ENTRY_12_10 (0x868) +#endif #define CLP_PV_REG_PCR_ENTRY_12_11 (0x1001a86c) +#ifndef PV_REG_PCR_ENTRY_12_11 #define PV_REG_PCR_ENTRY_12_11 (0x86c) +#endif #define CLP_PV_REG_PCR_ENTRY_13_0 (0x1001a870) +#ifndef PV_REG_PCR_ENTRY_13_0 #define PV_REG_PCR_ENTRY_13_0 (0x870) +#endif #define CLP_PV_REG_PCR_ENTRY_13_1 (0x1001a874) +#ifndef PV_REG_PCR_ENTRY_13_1 #define PV_REG_PCR_ENTRY_13_1 (0x874) +#endif #define CLP_PV_REG_PCR_ENTRY_13_2 (0x1001a878) +#ifndef PV_REG_PCR_ENTRY_13_2 #define PV_REG_PCR_ENTRY_13_2 (0x878) +#endif #define CLP_PV_REG_PCR_ENTRY_13_3 (0x1001a87c) +#ifndef PV_REG_PCR_ENTRY_13_3 #define PV_REG_PCR_ENTRY_13_3 (0x87c) +#endif #define CLP_PV_REG_PCR_ENTRY_13_4 (0x1001a880) +#ifndef PV_REG_PCR_ENTRY_13_4 #define PV_REG_PCR_ENTRY_13_4 (0x880) +#endif #define CLP_PV_REG_PCR_ENTRY_13_5 (0x1001a884) +#ifndef PV_REG_PCR_ENTRY_13_5 #define PV_REG_PCR_ENTRY_13_5 (0x884) +#endif #define CLP_PV_REG_PCR_ENTRY_13_6 (0x1001a888) +#ifndef PV_REG_PCR_ENTRY_13_6 #define PV_REG_PCR_ENTRY_13_6 (0x888) +#endif #define CLP_PV_REG_PCR_ENTRY_13_7 (0x1001a88c) +#ifndef PV_REG_PCR_ENTRY_13_7 #define PV_REG_PCR_ENTRY_13_7 (0x88c) +#endif #define CLP_PV_REG_PCR_ENTRY_13_8 (0x1001a890) +#ifndef PV_REG_PCR_ENTRY_13_8 #define PV_REG_PCR_ENTRY_13_8 (0x890) +#endif #define CLP_PV_REG_PCR_ENTRY_13_9 (0x1001a894) +#ifndef PV_REG_PCR_ENTRY_13_9 #define PV_REG_PCR_ENTRY_13_9 (0x894) +#endif #define CLP_PV_REG_PCR_ENTRY_13_10 (0x1001a898) +#ifndef PV_REG_PCR_ENTRY_13_10 #define PV_REG_PCR_ENTRY_13_10 (0x898) +#endif #define CLP_PV_REG_PCR_ENTRY_13_11 (0x1001a89c) +#ifndef PV_REG_PCR_ENTRY_13_11 #define PV_REG_PCR_ENTRY_13_11 (0x89c) +#endif #define CLP_PV_REG_PCR_ENTRY_14_0 (0x1001a8a0) +#ifndef PV_REG_PCR_ENTRY_14_0 #define PV_REG_PCR_ENTRY_14_0 (0x8a0) +#endif #define CLP_PV_REG_PCR_ENTRY_14_1 (0x1001a8a4) +#ifndef PV_REG_PCR_ENTRY_14_1 #define PV_REG_PCR_ENTRY_14_1 (0x8a4) +#endif #define CLP_PV_REG_PCR_ENTRY_14_2 (0x1001a8a8) +#ifndef PV_REG_PCR_ENTRY_14_2 #define PV_REG_PCR_ENTRY_14_2 (0x8a8) +#endif #define CLP_PV_REG_PCR_ENTRY_14_3 (0x1001a8ac) +#ifndef PV_REG_PCR_ENTRY_14_3 #define PV_REG_PCR_ENTRY_14_3 (0x8ac) +#endif #define CLP_PV_REG_PCR_ENTRY_14_4 (0x1001a8b0) +#ifndef PV_REG_PCR_ENTRY_14_4 #define PV_REG_PCR_ENTRY_14_4 (0x8b0) +#endif #define CLP_PV_REG_PCR_ENTRY_14_5 (0x1001a8b4) +#ifndef PV_REG_PCR_ENTRY_14_5 #define PV_REG_PCR_ENTRY_14_5 (0x8b4) +#endif #define CLP_PV_REG_PCR_ENTRY_14_6 (0x1001a8b8) +#ifndef PV_REG_PCR_ENTRY_14_6 #define PV_REG_PCR_ENTRY_14_6 (0x8b8) +#endif #define CLP_PV_REG_PCR_ENTRY_14_7 (0x1001a8bc) +#ifndef PV_REG_PCR_ENTRY_14_7 #define PV_REG_PCR_ENTRY_14_7 (0x8bc) +#endif #define CLP_PV_REG_PCR_ENTRY_14_8 (0x1001a8c0) +#ifndef PV_REG_PCR_ENTRY_14_8 #define PV_REG_PCR_ENTRY_14_8 (0x8c0) +#endif #define CLP_PV_REG_PCR_ENTRY_14_9 (0x1001a8c4) +#ifndef PV_REG_PCR_ENTRY_14_9 #define PV_REG_PCR_ENTRY_14_9 (0x8c4) +#endif #define CLP_PV_REG_PCR_ENTRY_14_10 (0x1001a8c8) +#ifndef PV_REG_PCR_ENTRY_14_10 #define PV_REG_PCR_ENTRY_14_10 (0x8c8) +#endif #define CLP_PV_REG_PCR_ENTRY_14_11 (0x1001a8cc) +#ifndef PV_REG_PCR_ENTRY_14_11 #define PV_REG_PCR_ENTRY_14_11 (0x8cc) +#endif #define CLP_PV_REG_PCR_ENTRY_15_0 (0x1001a8d0) +#ifndef PV_REG_PCR_ENTRY_15_0 #define PV_REG_PCR_ENTRY_15_0 (0x8d0) +#endif #define CLP_PV_REG_PCR_ENTRY_15_1 (0x1001a8d4) +#ifndef PV_REG_PCR_ENTRY_15_1 #define PV_REG_PCR_ENTRY_15_1 (0x8d4) +#endif #define CLP_PV_REG_PCR_ENTRY_15_2 (0x1001a8d8) +#ifndef PV_REG_PCR_ENTRY_15_2 #define PV_REG_PCR_ENTRY_15_2 (0x8d8) +#endif #define CLP_PV_REG_PCR_ENTRY_15_3 (0x1001a8dc) +#ifndef PV_REG_PCR_ENTRY_15_3 #define PV_REG_PCR_ENTRY_15_3 (0x8dc) +#endif #define CLP_PV_REG_PCR_ENTRY_15_4 (0x1001a8e0) +#ifndef PV_REG_PCR_ENTRY_15_4 #define PV_REG_PCR_ENTRY_15_4 (0x8e0) +#endif #define CLP_PV_REG_PCR_ENTRY_15_5 (0x1001a8e4) +#ifndef PV_REG_PCR_ENTRY_15_5 #define PV_REG_PCR_ENTRY_15_5 (0x8e4) +#endif #define CLP_PV_REG_PCR_ENTRY_15_6 (0x1001a8e8) +#ifndef PV_REG_PCR_ENTRY_15_6 #define PV_REG_PCR_ENTRY_15_6 (0x8e8) +#endif #define CLP_PV_REG_PCR_ENTRY_15_7 (0x1001a8ec) +#ifndef PV_REG_PCR_ENTRY_15_7 #define PV_REG_PCR_ENTRY_15_7 (0x8ec) +#endif #define CLP_PV_REG_PCR_ENTRY_15_8 (0x1001a8f0) +#ifndef PV_REG_PCR_ENTRY_15_8 #define PV_REG_PCR_ENTRY_15_8 (0x8f0) +#endif #define CLP_PV_REG_PCR_ENTRY_15_9 (0x1001a8f4) +#ifndef PV_REG_PCR_ENTRY_15_9 #define PV_REG_PCR_ENTRY_15_9 (0x8f4) +#endif #define CLP_PV_REG_PCR_ENTRY_15_10 (0x1001a8f8) +#ifndef PV_REG_PCR_ENTRY_15_10 #define PV_REG_PCR_ENTRY_15_10 (0x8f8) +#endif #define CLP_PV_REG_PCR_ENTRY_15_11 (0x1001a8fc) +#ifndef PV_REG_PCR_ENTRY_15_11 #define PV_REG_PCR_ENTRY_15_11 (0x8fc) +#endif #define CLP_PV_REG_PCR_ENTRY_16_0 (0x1001a900) +#ifndef PV_REG_PCR_ENTRY_16_0 #define PV_REG_PCR_ENTRY_16_0 (0x900) +#endif #define CLP_PV_REG_PCR_ENTRY_16_1 (0x1001a904) +#ifndef PV_REG_PCR_ENTRY_16_1 #define PV_REG_PCR_ENTRY_16_1 (0x904) +#endif #define CLP_PV_REG_PCR_ENTRY_16_2 (0x1001a908) +#ifndef PV_REG_PCR_ENTRY_16_2 #define PV_REG_PCR_ENTRY_16_2 (0x908) +#endif #define CLP_PV_REG_PCR_ENTRY_16_3 (0x1001a90c) +#ifndef PV_REG_PCR_ENTRY_16_3 #define PV_REG_PCR_ENTRY_16_3 (0x90c) +#endif #define CLP_PV_REG_PCR_ENTRY_16_4 (0x1001a910) +#ifndef PV_REG_PCR_ENTRY_16_4 #define PV_REG_PCR_ENTRY_16_4 (0x910) +#endif #define CLP_PV_REG_PCR_ENTRY_16_5 (0x1001a914) +#ifndef PV_REG_PCR_ENTRY_16_5 #define PV_REG_PCR_ENTRY_16_5 (0x914) +#endif #define CLP_PV_REG_PCR_ENTRY_16_6 (0x1001a918) +#ifndef PV_REG_PCR_ENTRY_16_6 #define PV_REG_PCR_ENTRY_16_6 (0x918) +#endif #define CLP_PV_REG_PCR_ENTRY_16_7 (0x1001a91c) +#ifndef PV_REG_PCR_ENTRY_16_7 #define PV_REG_PCR_ENTRY_16_7 (0x91c) +#endif #define CLP_PV_REG_PCR_ENTRY_16_8 (0x1001a920) +#ifndef PV_REG_PCR_ENTRY_16_8 #define PV_REG_PCR_ENTRY_16_8 (0x920) +#endif #define CLP_PV_REG_PCR_ENTRY_16_9 (0x1001a924) +#ifndef PV_REG_PCR_ENTRY_16_9 #define PV_REG_PCR_ENTRY_16_9 (0x924) +#endif #define CLP_PV_REG_PCR_ENTRY_16_10 (0x1001a928) +#ifndef PV_REG_PCR_ENTRY_16_10 #define PV_REG_PCR_ENTRY_16_10 (0x928) +#endif #define CLP_PV_REG_PCR_ENTRY_16_11 (0x1001a92c) +#ifndef PV_REG_PCR_ENTRY_16_11 #define PV_REG_PCR_ENTRY_16_11 (0x92c) +#endif #define CLP_PV_REG_PCR_ENTRY_17_0 (0x1001a930) +#ifndef PV_REG_PCR_ENTRY_17_0 #define PV_REG_PCR_ENTRY_17_0 (0x930) +#endif #define CLP_PV_REG_PCR_ENTRY_17_1 (0x1001a934) +#ifndef PV_REG_PCR_ENTRY_17_1 #define PV_REG_PCR_ENTRY_17_1 (0x934) +#endif #define CLP_PV_REG_PCR_ENTRY_17_2 (0x1001a938) +#ifndef PV_REG_PCR_ENTRY_17_2 #define PV_REG_PCR_ENTRY_17_2 (0x938) +#endif #define CLP_PV_REG_PCR_ENTRY_17_3 (0x1001a93c) +#ifndef PV_REG_PCR_ENTRY_17_3 #define PV_REG_PCR_ENTRY_17_3 (0x93c) +#endif #define CLP_PV_REG_PCR_ENTRY_17_4 (0x1001a940) +#ifndef PV_REG_PCR_ENTRY_17_4 #define PV_REG_PCR_ENTRY_17_4 (0x940) +#endif #define CLP_PV_REG_PCR_ENTRY_17_5 (0x1001a944) +#ifndef PV_REG_PCR_ENTRY_17_5 #define PV_REG_PCR_ENTRY_17_5 (0x944) +#endif #define CLP_PV_REG_PCR_ENTRY_17_6 (0x1001a948) +#ifndef PV_REG_PCR_ENTRY_17_6 #define PV_REG_PCR_ENTRY_17_6 (0x948) +#endif #define CLP_PV_REG_PCR_ENTRY_17_7 (0x1001a94c) +#ifndef PV_REG_PCR_ENTRY_17_7 #define PV_REG_PCR_ENTRY_17_7 (0x94c) +#endif #define CLP_PV_REG_PCR_ENTRY_17_8 (0x1001a950) +#ifndef PV_REG_PCR_ENTRY_17_8 #define PV_REG_PCR_ENTRY_17_8 (0x950) +#endif #define CLP_PV_REG_PCR_ENTRY_17_9 (0x1001a954) +#ifndef PV_REG_PCR_ENTRY_17_9 #define PV_REG_PCR_ENTRY_17_9 (0x954) +#endif #define CLP_PV_REG_PCR_ENTRY_17_10 (0x1001a958) +#ifndef PV_REG_PCR_ENTRY_17_10 #define PV_REG_PCR_ENTRY_17_10 (0x958) +#endif #define CLP_PV_REG_PCR_ENTRY_17_11 (0x1001a95c) +#ifndef PV_REG_PCR_ENTRY_17_11 #define PV_REG_PCR_ENTRY_17_11 (0x95c) +#endif #define CLP_PV_REG_PCR_ENTRY_18_0 (0x1001a960) +#ifndef PV_REG_PCR_ENTRY_18_0 #define PV_REG_PCR_ENTRY_18_0 (0x960) +#endif #define CLP_PV_REG_PCR_ENTRY_18_1 (0x1001a964) +#ifndef PV_REG_PCR_ENTRY_18_1 #define PV_REG_PCR_ENTRY_18_1 (0x964) +#endif #define CLP_PV_REG_PCR_ENTRY_18_2 (0x1001a968) +#ifndef PV_REG_PCR_ENTRY_18_2 #define PV_REG_PCR_ENTRY_18_2 (0x968) +#endif #define CLP_PV_REG_PCR_ENTRY_18_3 (0x1001a96c) +#ifndef PV_REG_PCR_ENTRY_18_3 #define PV_REG_PCR_ENTRY_18_3 (0x96c) +#endif #define CLP_PV_REG_PCR_ENTRY_18_4 (0x1001a970) +#ifndef PV_REG_PCR_ENTRY_18_4 #define PV_REG_PCR_ENTRY_18_4 (0x970) +#endif #define CLP_PV_REG_PCR_ENTRY_18_5 (0x1001a974) +#ifndef PV_REG_PCR_ENTRY_18_5 #define PV_REG_PCR_ENTRY_18_5 (0x974) +#endif #define CLP_PV_REG_PCR_ENTRY_18_6 (0x1001a978) +#ifndef PV_REG_PCR_ENTRY_18_6 #define PV_REG_PCR_ENTRY_18_6 (0x978) +#endif #define CLP_PV_REG_PCR_ENTRY_18_7 (0x1001a97c) +#ifndef PV_REG_PCR_ENTRY_18_7 #define PV_REG_PCR_ENTRY_18_7 (0x97c) +#endif #define CLP_PV_REG_PCR_ENTRY_18_8 (0x1001a980) +#ifndef PV_REG_PCR_ENTRY_18_8 #define PV_REG_PCR_ENTRY_18_8 (0x980) +#endif #define CLP_PV_REG_PCR_ENTRY_18_9 (0x1001a984) +#ifndef PV_REG_PCR_ENTRY_18_9 #define PV_REG_PCR_ENTRY_18_9 (0x984) +#endif #define CLP_PV_REG_PCR_ENTRY_18_10 (0x1001a988) +#ifndef PV_REG_PCR_ENTRY_18_10 #define PV_REG_PCR_ENTRY_18_10 (0x988) +#endif #define CLP_PV_REG_PCR_ENTRY_18_11 (0x1001a98c) +#ifndef PV_REG_PCR_ENTRY_18_11 #define PV_REG_PCR_ENTRY_18_11 (0x98c) +#endif #define CLP_PV_REG_PCR_ENTRY_19_0 (0x1001a990) +#ifndef PV_REG_PCR_ENTRY_19_0 #define PV_REG_PCR_ENTRY_19_0 (0x990) +#endif #define CLP_PV_REG_PCR_ENTRY_19_1 (0x1001a994) +#ifndef PV_REG_PCR_ENTRY_19_1 #define PV_REG_PCR_ENTRY_19_1 (0x994) +#endif #define CLP_PV_REG_PCR_ENTRY_19_2 (0x1001a998) +#ifndef PV_REG_PCR_ENTRY_19_2 #define PV_REG_PCR_ENTRY_19_2 (0x998) +#endif #define CLP_PV_REG_PCR_ENTRY_19_3 (0x1001a99c) +#ifndef PV_REG_PCR_ENTRY_19_3 #define PV_REG_PCR_ENTRY_19_3 (0x99c) +#endif #define CLP_PV_REG_PCR_ENTRY_19_4 (0x1001a9a0) +#ifndef PV_REG_PCR_ENTRY_19_4 #define PV_REG_PCR_ENTRY_19_4 (0x9a0) +#endif #define CLP_PV_REG_PCR_ENTRY_19_5 (0x1001a9a4) +#ifndef PV_REG_PCR_ENTRY_19_5 #define PV_REG_PCR_ENTRY_19_5 (0x9a4) +#endif #define CLP_PV_REG_PCR_ENTRY_19_6 (0x1001a9a8) +#ifndef PV_REG_PCR_ENTRY_19_6 #define PV_REG_PCR_ENTRY_19_6 (0x9a8) +#endif #define CLP_PV_REG_PCR_ENTRY_19_7 (0x1001a9ac) +#ifndef PV_REG_PCR_ENTRY_19_7 #define PV_REG_PCR_ENTRY_19_7 (0x9ac) +#endif #define CLP_PV_REG_PCR_ENTRY_19_8 (0x1001a9b0) +#ifndef PV_REG_PCR_ENTRY_19_8 #define PV_REG_PCR_ENTRY_19_8 (0x9b0) +#endif #define CLP_PV_REG_PCR_ENTRY_19_9 (0x1001a9b4) +#ifndef PV_REG_PCR_ENTRY_19_9 #define PV_REG_PCR_ENTRY_19_9 (0x9b4) +#endif #define CLP_PV_REG_PCR_ENTRY_19_10 (0x1001a9b8) +#ifndef PV_REG_PCR_ENTRY_19_10 #define PV_REG_PCR_ENTRY_19_10 (0x9b8) +#endif #define CLP_PV_REG_PCR_ENTRY_19_11 (0x1001a9bc) +#ifndef PV_REG_PCR_ENTRY_19_11 #define PV_REG_PCR_ENTRY_19_11 (0x9bc) +#endif #define CLP_PV_REG_PCR_ENTRY_20_0 (0x1001a9c0) +#ifndef PV_REG_PCR_ENTRY_20_0 #define PV_REG_PCR_ENTRY_20_0 (0x9c0) +#endif #define CLP_PV_REG_PCR_ENTRY_20_1 (0x1001a9c4) +#ifndef PV_REG_PCR_ENTRY_20_1 #define PV_REG_PCR_ENTRY_20_1 (0x9c4) +#endif #define CLP_PV_REG_PCR_ENTRY_20_2 (0x1001a9c8) +#ifndef PV_REG_PCR_ENTRY_20_2 #define PV_REG_PCR_ENTRY_20_2 (0x9c8) +#endif #define CLP_PV_REG_PCR_ENTRY_20_3 (0x1001a9cc) +#ifndef PV_REG_PCR_ENTRY_20_3 #define PV_REG_PCR_ENTRY_20_3 (0x9cc) +#endif #define CLP_PV_REG_PCR_ENTRY_20_4 (0x1001a9d0) +#ifndef PV_REG_PCR_ENTRY_20_4 #define PV_REG_PCR_ENTRY_20_4 (0x9d0) +#endif #define CLP_PV_REG_PCR_ENTRY_20_5 (0x1001a9d4) +#ifndef PV_REG_PCR_ENTRY_20_5 #define PV_REG_PCR_ENTRY_20_5 (0x9d4) +#endif #define CLP_PV_REG_PCR_ENTRY_20_6 (0x1001a9d8) +#ifndef PV_REG_PCR_ENTRY_20_6 #define PV_REG_PCR_ENTRY_20_6 (0x9d8) +#endif #define CLP_PV_REG_PCR_ENTRY_20_7 (0x1001a9dc) +#ifndef PV_REG_PCR_ENTRY_20_7 #define PV_REG_PCR_ENTRY_20_7 (0x9dc) +#endif #define CLP_PV_REG_PCR_ENTRY_20_8 (0x1001a9e0) +#ifndef PV_REG_PCR_ENTRY_20_8 #define PV_REG_PCR_ENTRY_20_8 (0x9e0) +#endif #define CLP_PV_REG_PCR_ENTRY_20_9 (0x1001a9e4) +#ifndef PV_REG_PCR_ENTRY_20_9 #define PV_REG_PCR_ENTRY_20_9 (0x9e4) +#endif #define CLP_PV_REG_PCR_ENTRY_20_10 (0x1001a9e8) +#ifndef PV_REG_PCR_ENTRY_20_10 #define PV_REG_PCR_ENTRY_20_10 (0x9e8) +#endif #define CLP_PV_REG_PCR_ENTRY_20_11 (0x1001a9ec) +#ifndef PV_REG_PCR_ENTRY_20_11 #define PV_REG_PCR_ENTRY_20_11 (0x9ec) +#endif #define CLP_PV_REG_PCR_ENTRY_21_0 (0x1001a9f0) +#ifndef PV_REG_PCR_ENTRY_21_0 #define PV_REG_PCR_ENTRY_21_0 (0x9f0) +#endif #define CLP_PV_REG_PCR_ENTRY_21_1 (0x1001a9f4) +#ifndef PV_REG_PCR_ENTRY_21_1 #define PV_REG_PCR_ENTRY_21_1 (0x9f4) +#endif #define CLP_PV_REG_PCR_ENTRY_21_2 (0x1001a9f8) +#ifndef PV_REG_PCR_ENTRY_21_2 #define PV_REG_PCR_ENTRY_21_2 (0x9f8) +#endif #define CLP_PV_REG_PCR_ENTRY_21_3 (0x1001a9fc) +#ifndef PV_REG_PCR_ENTRY_21_3 #define PV_REG_PCR_ENTRY_21_3 (0x9fc) +#endif #define CLP_PV_REG_PCR_ENTRY_21_4 (0x1001aa00) +#ifndef PV_REG_PCR_ENTRY_21_4 #define PV_REG_PCR_ENTRY_21_4 (0xa00) +#endif #define CLP_PV_REG_PCR_ENTRY_21_5 (0x1001aa04) +#ifndef PV_REG_PCR_ENTRY_21_5 #define PV_REG_PCR_ENTRY_21_5 (0xa04) +#endif #define CLP_PV_REG_PCR_ENTRY_21_6 (0x1001aa08) +#ifndef PV_REG_PCR_ENTRY_21_6 #define PV_REG_PCR_ENTRY_21_6 (0xa08) +#endif #define CLP_PV_REG_PCR_ENTRY_21_7 (0x1001aa0c) +#ifndef PV_REG_PCR_ENTRY_21_7 #define PV_REG_PCR_ENTRY_21_7 (0xa0c) +#endif #define CLP_PV_REG_PCR_ENTRY_21_8 (0x1001aa10) +#ifndef PV_REG_PCR_ENTRY_21_8 #define PV_REG_PCR_ENTRY_21_8 (0xa10) +#endif #define CLP_PV_REG_PCR_ENTRY_21_9 (0x1001aa14) +#ifndef PV_REG_PCR_ENTRY_21_9 #define PV_REG_PCR_ENTRY_21_9 (0xa14) +#endif #define CLP_PV_REG_PCR_ENTRY_21_10 (0x1001aa18) +#ifndef PV_REG_PCR_ENTRY_21_10 #define PV_REG_PCR_ENTRY_21_10 (0xa18) +#endif #define CLP_PV_REG_PCR_ENTRY_21_11 (0x1001aa1c) +#ifndef PV_REG_PCR_ENTRY_21_11 #define PV_REG_PCR_ENTRY_21_11 (0xa1c) +#endif #define CLP_PV_REG_PCR_ENTRY_22_0 (0x1001aa20) +#ifndef PV_REG_PCR_ENTRY_22_0 #define PV_REG_PCR_ENTRY_22_0 (0xa20) +#endif #define CLP_PV_REG_PCR_ENTRY_22_1 (0x1001aa24) +#ifndef PV_REG_PCR_ENTRY_22_1 #define PV_REG_PCR_ENTRY_22_1 (0xa24) +#endif #define CLP_PV_REG_PCR_ENTRY_22_2 (0x1001aa28) +#ifndef PV_REG_PCR_ENTRY_22_2 #define PV_REG_PCR_ENTRY_22_2 (0xa28) +#endif #define CLP_PV_REG_PCR_ENTRY_22_3 (0x1001aa2c) +#ifndef PV_REG_PCR_ENTRY_22_3 #define PV_REG_PCR_ENTRY_22_3 (0xa2c) +#endif #define CLP_PV_REG_PCR_ENTRY_22_4 (0x1001aa30) +#ifndef PV_REG_PCR_ENTRY_22_4 #define PV_REG_PCR_ENTRY_22_4 (0xa30) +#endif #define CLP_PV_REG_PCR_ENTRY_22_5 (0x1001aa34) +#ifndef PV_REG_PCR_ENTRY_22_5 #define PV_REG_PCR_ENTRY_22_5 (0xa34) +#endif #define CLP_PV_REG_PCR_ENTRY_22_6 (0x1001aa38) +#ifndef PV_REG_PCR_ENTRY_22_6 #define PV_REG_PCR_ENTRY_22_6 (0xa38) +#endif #define CLP_PV_REG_PCR_ENTRY_22_7 (0x1001aa3c) +#ifndef PV_REG_PCR_ENTRY_22_7 #define PV_REG_PCR_ENTRY_22_7 (0xa3c) +#endif #define CLP_PV_REG_PCR_ENTRY_22_8 (0x1001aa40) +#ifndef PV_REG_PCR_ENTRY_22_8 #define PV_REG_PCR_ENTRY_22_8 (0xa40) +#endif #define CLP_PV_REG_PCR_ENTRY_22_9 (0x1001aa44) +#ifndef PV_REG_PCR_ENTRY_22_9 #define PV_REG_PCR_ENTRY_22_9 (0xa44) +#endif #define CLP_PV_REG_PCR_ENTRY_22_10 (0x1001aa48) +#ifndef PV_REG_PCR_ENTRY_22_10 #define PV_REG_PCR_ENTRY_22_10 (0xa48) +#endif #define CLP_PV_REG_PCR_ENTRY_22_11 (0x1001aa4c) +#ifndef PV_REG_PCR_ENTRY_22_11 #define PV_REG_PCR_ENTRY_22_11 (0xa4c) +#endif #define CLP_PV_REG_PCR_ENTRY_23_0 (0x1001aa50) +#ifndef PV_REG_PCR_ENTRY_23_0 #define PV_REG_PCR_ENTRY_23_0 (0xa50) +#endif #define CLP_PV_REG_PCR_ENTRY_23_1 (0x1001aa54) +#ifndef PV_REG_PCR_ENTRY_23_1 #define PV_REG_PCR_ENTRY_23_1 (0xa54) +#endif #define CLP_PV_REG_PCR_ENTRY_23_2 (0x1001aa58) +#ifndef PV_REG_PCR_ENTRY_23_2 #define PV_REG_PCR_ENTRY_23_2 (0xa58) +#endif #define CLP_PV_REG_PCR_ENTRY_23_3 (0x1001aa5c) +#ifndef PV_REG_PCR_ENTRY_23_3 #define PV_REG_PCR_ENTRY_23_3 (0xa5c) +#endif #define CLP_PV_REG_PCR_ENTRY_23_4 (0x1001aa60) +#ifndef PV_REG_PCR_ENTRY_23_4 #define PV_REG_PCR_ENTRY_23_4 (0xa60) +#endif #define CLP_PV_REG_PCR_ENTRY_23_5 (0x1001aa64) +#ifndef PV_REG_PCR_ENTRY_23_5 #define PV_REG_PCR_ENTRY_23_5 (0xa64) +#endif #define CLP_PV_REG_PCR_ENTRY_23_6 (0x1001aa68) +#ifndef PV_REG_PCR_ENTRY_23_6 #define PV_REG_PCR_ENTRY_23_6 (0xa68) +#endif #define CLP_PV_REG_PCR_ENTRY_23_7 (0x1001aa6c) +#ifndef PV_REG_PCR_ENTRY_23_7 #define PV_REG_PCR_ENTRY_23_7 (0xa6c) +#endif #define CLP_PV_REG_PCR_ENTRY_23_8 (0x1001aa70) +#ifndef PV_REG_PCR_ENTRY_23_8 #define PV_REG_PCR_ENTRY_23_8 (0xa70) +#endif #define CLP_PV_REG_PCR_ENTRY_23_9 (0x1001aa74) +#ifndef PV_REG_PCR_ENTRY_23_9 #define PV_REG_PCR_ENTRY_23_9 (0xa74) +#endif #define CLP_PV_REG_PCR_ENTRY_23_10 (0x1001aa78) +#ifndef PV_REG_PCR_ENTRY_23_10 #define PV_REG_PCR_ENTRY_23_10 (0xa78) +#endif #define CLP_PV_REG_PCR_ENTRY_23_11 (0x1001aa7c) +#ifndef PV_REG_PCR_ENTRY_23_11 #define PV_REG_PCR_ENTRY_23_11 (0xa7c) +#endif #define CLP_PV_REG_PCR_ENTRY_24_0 (0x1001aa80) +#ifndef PV_REG_PCR_ENTRY_24_0 #define PV_REG_PCR_ENTRY_24_0 (0xa80) +#endif #define CLP_PV_REG_PCR_ENTRY_24_1 (0x1001aa84) +#ifndef PV_REG_PCR_ENTRY_24_1 #define PV_REG_PCR_ENTRY_24_1 (0xa84) +#endif #define CLP_PV_REG_PCR_ENTRY_24_2 (0x1001aa88) +#ifndef PV_REG_PCR_ENTRY_24_2 #define PV_REG_PCR_ENTRY_24_2 (0xa88) +#endif #define CLP_PV_REG_PCR_ENTRY_24_3 (0x1001aa8c) +#ifndef PV_REG_PCR_ENTRY_24_3 #define PV_REG_PCR_ENTRY_24_3 (0xa8c) +#endif #define CLP_PV_REG_PCR_ENTRY_24_4 (0x1001aa90) +#ifndef PV_REG_PCR_ENTRY_24_4 #define PV_REG_PCR_ENTRY_24_4 (0xa90) +#endif #define CLP_PV_REG_PCR_ENTRY_24_5 (0x1001aa94) +#ifndef PV_REG_PCR_ENTRY_24_5 #define PV_REG_PCR_ENTRY_24_5 (0xa94) +#endif #define CLP_PV_REG_PCR_ENTRY_24_6 (0x1001aa98) +#ifndef PV_REG_PCR_ENTRY_24_6 #define PV_REG_PCR_ENTRY_24_6 (0xa98) +#endif #define CLP_PV_REG_PCR_ENTRY_24_7 (0x1001aa9c) +#ifndef PV_REG_PCR_ENTRY_24_7 #define PV_REG_PCR_ENTRY_24_7 (0xa9c) +#endif #define CLP_PV_REG_PCR_ENTRY_24_8 (0x1001aaa0) +#ifndef PV_REG_PCR_ENTRY_24_8 #define PV_REG_PCR_ENTRY_24_8 (0xaa0) +#endif #define CLP_PV_REG_PCR_ENTRY_24_9 (0x1001aaa4) +#ifndef PV_REG_PCR_ENTRY_24_9 #define PV_REG_PCR_ENTRY_24_9 (0xaa4) +#endif #define CLP_PV_REG_PCR_ENTRY_24_10 (0x1001aaa8) +#ifndef PV_REG_PCR_ENTRY_24_10 #define PV_REG_PCR_ENTRY_24_10 (0xaa8) +#endif #define CLP_PV_REG_PCR_ENTRY_24_11 (0x1001aaac) +#ifndef PV_REG_PCR_ENTRY_24_11 #define PV_REG_PCR_ENTRY_24_11 (0xaac) +#endif #define CLP_PV_REG_PCR_ENTRY_25_0 (0x1001aab0) +#ifndef PV_REG_PCR_ENTRY_25_0 #define PV_REG_PCR_ENTRY_25_0 (0xab0) +#endif #define CLP_PV_REG_PCR_ENTRY_25_1 (0x1001aab4) +#ifndef PV_REG_PCR_ENTRY_25_1 #define PV_REG_PCR_ENTRY_25_1 (0xab4) +#endif #define CLP_PV_REG_PCR_ENTRY_25_2 (0x1001aab8) +#ifndef PV_REG_PCR_ENTRY_25_2 #define PV_REG_PCR_ENTRY_25_2 (0xab8) +#endif #define CLP_PV_REG_PCR_ENTRY_25_3 (0x1001aabc) +#ifndef PV_REG_PCR_ENTRY_25_3 #define PV_REG_PCR_ENTRY_25_3 (0xabc) +#endif #define CLP_PV_REG_PCR_ENTRY_25_4 (0x1001aac0) +#ifndef PV_REG_PCR_ENTRY_25_4 #define PV_REG_PCR_ENTRY_25_4 (0xac0) +#endif #define CLP_PV_REG_PCR_ENTRY_25_5 (0x1001aac4) +#ifndef PV_REG_PCR_ENTRY_25_5 #define PV_REG_PCR_ENTRY_25_5 (0xac4) +#endif #define CLP_PV_REG_PCR_ENTRY_25_6 (0x1001aac8) +#ifndef PV_REG_PCR_ENTRY_25_6 #define PV_REG_PCR_ENTRY_25_6 (0xac8) +#endif #define CLP_PV_REG_PCR_ENTRY_25_7 (0x1001aacc) +#ifndef PV_REG_PCR_ENTRY_25_7 #define PV_REG_PCR_ENTRY_25_7 (0xacc) +#endif #define CLP_PV_REG_PCR_ENTRY_25_8 (0x1001aad0) +#ifndef PV_REG_PCR_ENTRY_25_8 #define PV_REG_PCR_ENTRY_25_8 (0xad0) +#endif #define CLP_PV_REG_PCR_ENTRY_25_9 (0x1001aad4) +#ifndef PV_REG_PCR_ENTRY_25_9 #define PV_REG_PCR_ENTRY_25_9 (0xad4) +#endif #define CLP_PV_REG_PCR_ENTRY_25_10 (0x1001aad8) +#ifndef PV_REG_PCR_ENTRY_25_10 #define PV_REG_PCR_ENTRY_25_10 (0xad8) +#endif #define CLP_PV_REG_PCR_ENTRY_25_11 (0x1001aadc) +#ifndef PV_REG_PCR_ENTRY_25_11 #define PV_REG_PCR_ENTRY_25_11 (0xadc) +#endif #define CLP_PV_REG_PCR_ENTRY_26_0 (0x1001aae0) +#ifndef PV_REG_PCR_ENTRY_26_0 #define PV_REG_PCR_ENTRY_26_0 (0xae0) +#endif #define CLP_PV_REG_PCR_ENTRY_26_1 (0x1001aae4) +#ifndef PV_REG_PCR_ENTRY_26_1 #define PV_REG_PCR_ENTRY_26_1 (0xae4) +#endif #define CLP_PV_REG_PCR_ENTRY_26_2 (0x1001aae8) +#ifndef PV_REG_PCR_ENTRY_26_2 #define PV_REG_PCR_ENTRY_26_2 (0xae8) +#endif #define CLP_PV_REG_PCR_ENTRY_26_3 (0x1001aaec) +#ifndef PV_REG_PCR_ENTRY_26_3 #define PV_REG_PCR_ENTRY_26_3 (0xaec) +#endif #define CLP_PV_REG_PCR_ENTRY_26_4 (0x1001aaf0) +#ifndef PV_REG_PCR_ENTRY_26_4 #define PV_REG_PCR_ENTRY_26_4 (0xaf0) +#endif #define CLP_PV_REG_PCR_ENTRY_26_5 (0x1001aaf4) +#ifndef PV_REG_PCR_ENTRY_26_5 #define PV_REG_PCR_ENTRY_26_5 (0xaf4) +#endif #define CLP_PV_REG_PCR_ENTRY_26_6 (0x1001aaf8) +#ifndef PV_REG_PCR_ENTRY_26_6 #define PV_REG_PCR_ENTRY_26_6 (0xaf8) +#endif #define CLP_PV_REG_PCR_ENTRY_26_7 (0x1001aafc) +#ifndef PV_REG_PCR_ENTRY_26_7 #define PV_REG_PCR_ENTRY_26_7 (0xafc) +#endif #define CLP_PV_REG_PCR_ENTRY_26_8 (0x1001ab00) +#ifndef PV_REG_PCR_ENTRY_26_8 #define PV_REG_PCR_ENTRY_26_8 (0xb00) +#endif #define CLP_PV_REG_PCR_ENTRY_26_9 (0x1001ab04) +#ifndef PV_REG_PCR_ENTRY_26_9 #define PV_REG_PCR_ENTRY_26_9 (0xb04) +#endif #define CLP_PV_REG_PCR_ENTRY_26_10 (0x1001ab08) +#ifndef PV_REG_PCR_ENTRY_26_10 #define PV_REG_PCR_ENTRY_26_10 (0xb08) +#endif #define CLP_PV_REG_PCR_ENTRY_26_11 (0x1001ab0c) +#ifndef PV_REG_PCR_ENTRY_26_11 #define PV_REG_PCR_ENTRY_26_11 (0xb0c) +#endif #define CLP_PV_REG_PCR_ENTRY_27_0 (0x1001ab10) +#ifndef PV_REG_PCR_ENTRY_27_0 #define PV_REG_PCR_ENTRY_27_0 (0xb10) +#endif #define CLP_PV_REG_PCR_ENTRY_27_1 (0x1001ab14) +#ifndef PV_REG_PCR_ENTRY_27_1 #define PV_REG_PCR_ENTRY_27_1 (0xb14) +#endif #define CLP_PV_REG_PCR_ENTRY_27_2 (0x1001ab18) +#ifndef PV_REG_PCR_ENTRY_27_2 #define PV_REG_PCR_ENTRY_27_2 (0xb18) +#endif #define CLP_PV_REG_PCR_ENTRY_27_3 (0x1001ab1c) +#ifndef PV_REG_PCR_ENTRY_27_3 #define PV_REG_PCR_ENTRY_27_3 (0xb1c) +#endif #define CLP_PV_REG_PCR_ENTRY_27_4 (0x1001ab20) +#ifndef PV_REG_PCR_ENTRY_27_4 #define PV_REG_PCR_ENTRY_27_4 (0xb20) +#endif #define CLP_PV_REG_PCR_ENTRY_27_5 (0x1001ab24) +#ifndef PV_REG_PCR_ENTRY_27_5 #define PV_REG_PCR_ENTRY_27_5 (0xb24) +#endif #define CLP_PV_REG_PCR_ENTRY_27_6 (0x1001ab28) +#ifndef PV_REG_PCR_ENTRY_27_6 #define PV_REG_PCR_ENTRY_27_6 (0xb28) +#endif #define CLP_PV_REG_PCR_ENTRY_27_7 (0x1001ab2c) +#ifndef PV_REG_PCR_ENTRY_27_7 #define PV_REG_PCR_ENTRY_27_7 (0xb2c) +#endif #define CLP_PV_REG_PCR_ENTRY_27_8 (0x1001ab30) +#ifndef PV_REG_PCR_ENTRY_27_8 #define PV_REG_PCR_ENTRY_27_8 (0xb30) +#endif #define CLP_PV_REG_PCR_ENTRY_27_9 (0x1001ab34) +#ifndef PV_REG_PCR_ENTRY_27_9 #define PV_REG_PCR_ENTRY_27_9 (0xb34) +#endif #define CLP_PV_REG_PCR_ENTRY_27_10 (0x1001ab38) +#ifndef PV_REG_PCR_ENTRY_27_10 #define PV_REG_PCR_ENTRY_27_10 (0xb38) +#endif #define CLP_PV_REG_PCR_ENTRY_27_11 (0x1001ab3c) +#ifndef PV_REG_PCR_ENTRY_27_11 #define PV_REG_PCR_ENTRY_27_11 (0xb3c) +#endif #define CLP_PV_REG_PCR_ENTRY_28_0 (0x1001ab40) +#ifndef PV_REG_PCR_ENTRY_28_0 #define PV_REG_PCR_ENTRY_28_0 (0xb40) +#endif #define CLP_PV_REG_PCR_ENTRY_28_1 (0x1001ab44) +#ifndef PV_REG_PCR_ENTRY_28_1 #define PV_REG_PCR_ENTRY_28_1 (0xb44) +#endif #define CLP_PV_REG_PCR_ENTRY_28_2 (0x1001ab48) +#ifndef PV_REG_PCR_ENTRY_28_2 #define PV_REG_PCR_ENTRY_28_2 (0xb48) +#endif #define CLP_PV_REG_PCR_ENTRY_28_3 (0x1001ab4c) +#ifndef PV_REG_PCR_ENTRY_28_3 #define PV_REG_PCR_ENTRY_28_3 (0xb4c) +#endif #define CLP_PV_REG_PCR_ENTRY_28_4 (0x1001ab50) +#ifndef PV_REG_PCR_ENTRY_28_4 #define PV_REG_PCR_ENTRY_28_4 (0xb50) +#endif #define CLP_PV_REG_PCR_ENTRY_28_5 (0x1001ab54) +#ifndef PV_REG_PCR_ENTRY_28_5 #define PV_REG_PCR_ENTRY_28_5 (0xb54) +#endif #define CLP_PV_REG_PCR_ENTRY_28_6 (0x1001ab58) +#ifndef PV_REG_PCR_ENTRY_28_6 #define PV_REG_PCR_ENTRY_28_6 (0xb58) +#endif #define CLP_PV_REG_PCR_ENTRY_28_7 (0x1001ab5c) +#ifndef PV_REG_PCR_ENTRY_28_7 #define PV_REG_PCR_ENTRY_28_7 (0xb5c) +#endif #define CLP_PV_REG_PCR_ENTRY_28_8 (0x1001ab60) +#ifndef PV_REG_PCR_ENTRY_28_8 #define PV_REG_PCR_ENTRY_28_8 (0xb60) +#endif #define CLP_PV_REG_PCR_ENTRY_28_9 (0x1001ab64) +#ifndef PV_REG_PCR_ENTRY_28_9 #define PV_REG_PCR_ENTRY_28_9 (0xb64) +#endif #define CLP_PV_REG_PCR_ENTRY_28_10 (0x1001ab68) +#ifndef PV_REG_PCR_ENTRY_28_10 #define PV_REG_PCR_ENTRY_28_10 (0xb68) +#endif #define CLP_PV_REG_PCR_ENTRY_28_11 (0x1001ab6c) +#ifndef PV_REG_PCR_ENTRY_28_11 #define PV_REG_PCR_ENTRY_28_11 (0xb6c) +#endif #define CLP_PV_REG_PCR_ENTRY_29_0 (0x1001ab70) +#ifndef PV_REG_PCR_ENTRY_29_0 #define PV_REG_PCR_ENTRY_29_0 (0xb70) +#endif #define CLP_PV_REG_PCR_ENTRY_29_1 (0x1001ab74) +#ifndef PV_REG_PCR_ENTRY_29_1 #define PV_REG_PCR_ENTRY_29_1 (0xb74) +#endif #define CLP_PV_REG_PCR_ENTRY_29_2 (0x1001ab78) +#ifndef PV_REG_PCR_ENTRY_29_2 #define PV_REG_PCR_ENTRY_29_2 (0xb78) +#endif #define CLP_PV_REG_PCR_ENTRY_29_3 (0x1001ab7c) +#ifndef PV_REG_PCR_ENTRY_29_3 #define PV_REG_PCR_ENTRY_29_3 (0xb7c) +#endif #define CLP_PV_REG_PCR_ENTRY_29_4 (0x1001ab80) +#ifndef PV_REG_PCR_ENTRY_29_4 #define PV_REG_PCR_ENTRY_29_4 (0xb80) +#endif #define CLP_PV_REG_PCR_ENTRY_29_5 (0x1001ab84) +#ifndef PV_REG_PCR_ENTRY_29_5 #define PV_REG_PCR_ENTRY_29_5 (0xb84) +#endif #define CLP_PV_REG_PCR_ENTRY_29_6 (0x1001ab88) +#ifndef PV_REG_PCR_ENTRY_29_6 #define PV_REG_PCR_ENTRY_29_6 (0xb88) +#endif #define CLP_PV_REG_PCR_ENTRY_29_7 (0x1001ab8c) +#ifndef PV_REG_PCR_ENTRY_29_7 #define PV_REG_PCR_ENTRY_29_7 (0xb8c) +#endif #define CLP_PV_REG_PCR_ENTRY_29_8 (0x1001ab90) +#ifndef PV_REG_PCR_ENTRY_29_8 #define PV_REG_PCR_ENTRY_29_8 (0xb90) +#endif #define CLP_PV_REG_PCR_ENTRY_29_9 (0x1001ab94) +#ifndef PV_REG_PCR_ENTRY_29_9 #define PV_REG_PCR_ENTRY_29_9 (0xb94) +#endif #define CLP_PV_REG_PCR_ENTRY_29_10 (0x1001ab98) +#ifndef PV_REG_PCR_ENTRY_29_10 #define PV_REG_PCR_ENTRY_29_10 (0xb98) +#endif #define CLP_PV_REG_PCR_ENTRY_29_11 (0x1001ab9c) +#ifndef PV_REG_PCR_ENTRY_29_11 #define PV_REG_PCR_ENTRY_29_11 (0xb9c) +#endif #define CLP_PV_REG_PCR_ENTRY_30_0 (0x1001aba0) +#ifndef PV_REG_PCR_ENTRY_30_0 #define PV_REG_PCR_ENTRY_30_0 (0xba0) +#endif #define CLP_PV_REG_PCR_ENTRY_30_1 (0x1001aba4) +#ifndef PV_REG_PCR_ENTRY_30_1 #define PV_REG_PCR_ENTRY_30_1 (0xba4) +#endif #define CLP_PV_REG_PCR_ENTRY_30_2 (0x1001aba8) +#ifndef PV_REG_PCR_ENTRY_30_2 #define PV_REG_PCR_ENTRY_30_2 (0xba8) +#endif #define CLP_PV_REG_PCR_ENTRY_30_3 (0x1001abac) +#ifndef PV_REG_PCR_ENTRY_30_3 #define PV_REG_PCR_ENTRY_30_3 (0xbac) +#endif #define CLP_PV_REG_PCR_ENTRY_30_4 (0x1001abb0) +#ifndef PV_REG_PCR_ENTRY_30_4 #define PV_REG_PCR_ENTRY_30_4 (0xbb0) +#endif #define CLP_PV_REG_PCR_ENTRY_30_5 (0x1001abb4) +#ifndef PV_REG_PCR_ENTRY_30_5 #define PV_REG_PCR_ENTRY_30_5 (0xbb4) +#endif #define CLP_PV_REG_PCR_ENTRY_30_6 (0x1001abb8) +#ifndef PV_REG_PCR_ENTRY_30_6 #define PV_REG_PCR_ENTRY_30_6 (0xbb8) +#endif #define CLP_PV_REG_PCR_ENTRY_30_7 (0x1001abbc) +#ifndef PV_REG_PCR_ENTRY_30_7 #define PV_REG_PCR_ENTRY_30_7 (0xbbc) +#endif #define CLP_PV_REG_PCR_ENTRY_30_8 (0x1001abc0) +#ifndef PV_REG_PCR_ENTRY_30_8 #define PV_REG_PCR_ENTRY_30_8 (0xbc0) +#endif #define CLP_PV_REG_PCR_ENTRY_30_9 (0x1001abc4) +#ifndef PV_REG_PCR_ENTRY_30_9 #define PV_REG_PCR_ENTRY_30_9 (0xbc4) +#endif #define CLP_PV_REG_PCR_ENTRY_30_10 (0x1001abc8) +#ifndef PV_REG_PCR_ENTRY_30_10 #define PV_REG_PCR_ENTRY_30_10 (0xbc8) +#endif #define CLP_PV_REG_PCR_ENTRY_30_11 (0x1001abcc) +#ifndef PV_REG_PCR_ENTRY_30_11 #define PV_REG_PCR_ENTRY_30_11 (0xbcc) +#endif #define CLP_PV_REG_PCR_ENTRY_31_0 (0x1001abd0) +#ifndef PV_REG_PCR_ENTRY_31_0 #define PV_REG_PCR_ENTRY_31_0 (0xbd0) +#endif #define CLP_PV_REG_PCR_ENTRY_31_1 (0x1001abd4) +#ifndef PV_REG_PCR_ENTRY_31_1 #define PV_REG_PCR_ENTRY_31_1 (0xbd4) +#endif #define CLP_PV_REG_PCR_ENTRY_31_2 (0x1001abd8) +#ifndef PV_REG_PCR_ENTRY_31_2 #define PV_REG_PCR_ENTRY_31_2 (0xbd8) +#endif #define CLP_PV_REG_PCR_ENTRY_31_3 (0x1001abdc) +#ifndef PV_REG_PCR_ENTRY_31_3 #define PV_REG_PCR_ENTRY_31_3 (0xbdc) +#endif #define CLP_PV_REG_PCR_ENTRY_31_4 (0x1001abe0) +#ifndef PV_REG_PCR_ENTRY_31_4 #define PV_REG_PCR_ENTRY_31_4 (0xbe0) +#endif #define CLP_PV_REG_PCR_ENTRY_31_5 (0x1001abe4) +#ifndef PV_REG_PCR_ENTRY_31_5 #define PV_REG_PCR_ENTRY_31_5 (0xbe4) +#endif #define CLP_PV_REG_PCR_ENTRY_31_6 (0x1001abe8) +#ifndef PV_REG_PCR_ENTRY_31_6 #define PV_REG_PCR_ENTRY_31_6 (0xbe8) +#endif #define CLP_PV_REG_PCR_ENTRY_31_7 (0x1001abec) +#ifndef PV_REG_PCR_ENTRY_31_7 #define PV_REG_PCR_ENTRY_31_7 (0xbec) +#endif #define CLP_PV_REG_PCR_ENTRY_31_8 (0x1001abf0) +#ifndef PV_REG_PCR_ENTRY_31_8 #define PV_REG_PCR_ENTRY_31_8 (0xbf0) +#endif #define CLP_PV_REG_PCR_ENTRY_31_9 (0x1001abf4) +#ifndef PV_REG_PCR_ENTRY_31_9 #define PV_REG_PCR_ENTRY_31_9 (0xbf4) +#endif #define CLP_PV_REG_PCR_ENTRY_31_10 (0x1001abf8) +#ifndef PV_REG_PCR_ENTRY_31_10 #define PV_REG_PCR_ENTRY_31_10 (0xbf8) +#endif #define CLP_PV_REG_PCR_ENTRY_31_11 (0x1001abfc) +#ifndef PV_REG_PCR_ENTRY_31_11 #define PV_REG_PCR_ENTRY_31_11 (0xbfc) +#endif #define CLP_DV_REG_BASE_ADDR (0x1001c000) #define CLP_DV_REG_STICKYDATAVAULTCTRL_0 (0x1001c000) +#ifndef DV_REG_STICKYDATAVAULTCTRL_0 #define DV_REG_STICKYDATAVAULTCTRL_0 (0x0) #define DV_REG_STICKYDATAVAULTCTRL_0_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_0_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_1 (0x1001c004) +#ifndef DV_REG_STICKYDATAVAULTCTRL_1 #define DV_REG_STICKYDATAVAULTCTRL_1 (0x4) #define DV_REG_STICKYDATAVAULTCTRL_1_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_1_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_2 (0x1001c008) +#ifndef DV_REG_STICKYDATAVAULTCTRL_2 #define DV_REG_STICKYDATAVAULTCTRL_2 (0x8) #define DV_REG_STICKYDATAVAULTCTRL_2_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_2_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_3 (0x1001c00c) +#ifndef DV_REG_STICKYDATAVAULTCTRL_3 #define DV_REG_STICKYDATAVAULTCTRL_3 (0xc) #define DV_REG_STICKYDATAVAULTCTRL_3_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_3_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_4 (0x1001c010) +#ifndef DV_REG_STICKYDATAVAULTCTRL_4 #define DV_REG_STICKYDATAVAULTCTRL_4 (0x10) #define DV_REG_STICKYDATAVAULTCTRL_4_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_4_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_5 (0x1001c014) +#ifndef DV_REG_STICKYDATAVAULTCTRL_5 #define DV_REG_STICKYDATAVAULTCTRL_5 (0x14) #define DV_REG_STICKYDATAVAULTCTRL_5_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_5_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_6 (0x1001c018) +#ifndef DV_REG_STICKYDATAVAULTCTRL_6 #define DV_REG_STICKYDATAVAULTCTRL_6 (0x18) #define DV_REG_STICKYDATAVAULTCTRL_6_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_6_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_7 (0x1001c01c) +#ifndef DV_REG_STICKYDATAVAULTCTRL_7 #define DV_REG_STICKYDATAVAULTCTRL_7 (0x1c) #define DV_REG_STICKYDATAVAULTCTRL_7_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_7_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_8 (0x1001c020) +#ifndef DV_REG_STICKYDATAVAULTCTRL_8 #define DV_REG_STICKYDATAVAULTCTRL_8 (0x20) #define DV_REG_STICKYDATAVAULTCTRL_8_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_8_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYDATAVAULTCTRL_9 (0x1001c024) +#ifndef DV_REG_STICKYDATAVAULTCTRL_9 #define DV_REG_STICKYDATAVAULTCTRL_9 (0x24) #define DV_REG_STICKYDATAVAULTCTRL_9_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYDATAVAULTCTRL_9_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_0 (0x1001c028) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_0 (0x28) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_1 (0x1001c02c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_1 (0x2c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_2 (0x1001c030) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_2 (0x30) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_3 (0x1001c034) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_3 (0x34) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_4 (0x1001c038) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_4 (0x38) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_5 (0x1001c03c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_5 (0x3c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_6 (0x1001c040) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_6 (0x40) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_7 (0x1001c044) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_7 (0x44) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_8 (0x1001c048) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_8 (0x48) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_9 (0x1001c04c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_9 (0x4c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_10 (0x1001c050) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_10 (0x50) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_11 (0x1001c054) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_0_11 (0x54) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_0 (0x1001c058) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_0 (0x58) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_1 (0x1001c05c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_1 (0x5c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_2 (0x1001c060) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_2 (0x60) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_3 (0x1001c064) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_3 (0x64) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_4 (0x1001c068) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_4 (0x68) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_5 (0x1001c06c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_5 (0x6c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_6 (0x1001c070) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_6 (0x70) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_7 (0x1001c074) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_7 (0x74) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_8 (0x1001c078) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_8 (0x78) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_9 (0x1001c07c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_9 (0x7c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_10 (0x1001c080) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_10 (0x80) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_11 (0x1001c084) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_1_11 (0x84) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_0 (0x1001c088) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_0 (0x88) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_1 (0x1001c08c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_1 (0x8c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_2 (0x1001c090) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_2 (0x90) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_3 (0x1001c094) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_3 (0x94) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_4 (0x1001c098) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_4 (0x98) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_5 (0x1001c09c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_5 (0x9c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_6 (0x1001c0a0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_6 (0xa0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_7 (0x1001c0a4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_7 (0xa4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_8 (0x1001c0a8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_8 (0xa8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_9 (0x1001c0ac) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_9 (0xac) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_10 (0x1001c0b0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_10 (0xb0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_2_11 (0x1001c0b4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_2_11 (0xb4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_0 (0x1001c0b8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_0 (0xb8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_1 (0x1001c0bc) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_1 (0xbc) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_2 (0x1001c0c0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_2 (0xc0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_3 (0x1001c0c4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_3 (0xc4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_4 (0x1001c0c8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_4 (0xc8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_5 (0x1001c0cc) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_5 (0xcc) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_6 (0x1001c0d0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_6 (0xd0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_7 (0x1001c0d4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_7 (0xd4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_8 (0x1001c0d8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_8 (0xd8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_9 (0x1001c0dc) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_9 (0xdc) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_10 (0x1001c0e0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_10 (0xe0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_3_11 (0x1001c0e4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_3_11 (0xe4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_0 (0x1001c0e8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_0 (0xe8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_1 (0x1001c0ec) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_1 (0xec) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_2 (0x1001c0f0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_2 (0xf0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_3 (0x1001c0f4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_3 (0xf4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_4 (0x1001c0f8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_4 (0xf8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_5 (0x1001c0fc) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_5 (0xfc) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_6 (0x1001c100) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_6 (0x100) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_7 (0x1001c104) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_7 (0x104) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_8 (0x1001c108) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_8 (0x108) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_9 (0x1001c10c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_9 (0x10c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_10 (0x1001c110) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_10 (0x110) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_4_11 (0x1001c114) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_4_11 (0x114) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_0 (0x1001c118) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_0 (0x118) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_1 (0x1001c11c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_1 (0x11c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_2 (0x1001c120) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_2 (0x120) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_3 (0x1001c124) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_3 (0x124) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_4 (0x1001c128) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_4 (0x128) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_5 (0x1001c12c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_5 (0x12c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_6 (0x1001c130) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_6 (0x130) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_7 (0x1001c134) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_7 (0x134) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_8 (0x1001c138) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_8 (0x138) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_9 (0x1001c13c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_9 (0x13c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_10 (0x1001c140) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_10 (0x140) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_5_11 (0x1001c144) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_5_11 (0x144) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_0 (0x1001c148) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_0 (0x148) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_1 (0x1001c14c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_1 (0x14c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_2 (0x1001c150) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_2 (0x150) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_3 (0x1001c154) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_3 (0x154) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_4 (0x1001c158) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_4 (0x158) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_5 (0x1001c15c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_5 (0x15c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_6 (0x1001c160) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_6 (0x160) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_7 (0x1001c164) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_7 (0x164) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_8 (0x1001c168) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_8 (0x168) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_9 (0x1001c16c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_9 (0x16c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_10 (0x1001c170) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_10 (0x170) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_6_11 (0x1001c174) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_6_11 (0x174) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_0 (0x1001c178) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_0 (0x178) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_1 (0x1001c17c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_1 (0x17c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_2 (0x1001c180) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_2 (0x180) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_3 (0x1001c184) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_3 (0x184) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_4 (0x1001c188) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_4 (0x188) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_5 (0x1001c18c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_5 (0x18c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_6 (0x1001c190) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_6 (0x190) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_7 (0x1001c194) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_7 (0x194) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_8 (0x1001c198) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_8 (0x198) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_9 (0x1001c19c) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_9 (0x19c) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_10 (0x1001c1a0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_10 (0x1a0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_11 (0x1001c1a4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_7_11 (0x1a4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_0 (0x1001c1a8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_0 (0x1a8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_1 (0x1001c1ac) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_1 (0x1ac) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_2 (0x1001c1b0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_2 (0x1b0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_3 (0x1001c1b4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_3 (0x1b4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_4 (0x1001c1b8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_4 (0x1b8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_5 (0x1001c1bc) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_5 (0x1bc) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_6 (0x1001c1c0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_6 (0x1c0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_7 (0x1001c1c4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_7 (0x1c4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_8 (0x1001c1c8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_8 (0x1c8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_9 (0x1001c1cc) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_9 (0x1cc) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_10 (0x1001c1d0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_10 (0x1d0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_11 (0x1001c1d4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_8_11 (0x1d4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_0 (0x1001c1d8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_0 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_0 (0x1d8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_1 (0x1001c1dc) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_1 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_1 (0x1dc) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_2 (0x1001c1e0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_2 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_2 (0x1e0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_3 (0x1001c1e4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_3 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_3 (0x1e4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_4 (0x1001c1e8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_4 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_4 (0x1e8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_5 (0x1001c1ec) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_5 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_5 (0x1ec) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_6 (0x1001c1f0) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_6 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_6 (0x1f0) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_7 (0x1001c1f4) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_7 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_7 (0x1f4) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_8 (0x1001c1f8) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_8 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_8 (0x1f8) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_9 (0x1001c1fc) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_9 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_9 (0x1fc) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_10 (0x1001c200) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_10 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_10 (0x200) +#endif #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_11 (0x1001c204) +#ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_11 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_11 (0x204) +#endif #define CLP_DV_REG_DATAVAULTCTRL_0 (0x1001c208) +#ifndef DV_REG_DATAVAULTCTRL_0 #define DV_REG_DATAVAULTCTRL_0 (0x208) #define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_1 (0x1001c20c) +#ifndef DV_REG_DATAVAULTCTRL_1 #define DV_REG_DATAVAULTCTRL_1 (0x20c) #define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_2 (0x1001c210) +#ifndef DV_REG_DATAVAULTCTRL_2 #define DV_REG_DATAVAULTCTRL_2 (0x210) #define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_3 (0x1001c214) +#ifndef DV_REG_DATAVAULTCTRL_3 #define DV_REG_DATAVAULTCTRL_3 (0x214) #define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_4 (0x1001c218) +#ifndef DV_REG_DATAVAULTCTRL_4 #define DV_REG_DATAVAULTCTRL_4 (0x218) #define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_5 (0x1001c21c) +#ifndef DV_REG_DATAVAULTCTRL_5 #define DV_REG_DATAVAULTCTRL_5 (0x21c) #define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_6 (0x1001c220) +#ifndef DV_REG_DATAVAULTCTRL_6 #define DV_REG_DATAVAULTCTRL_6 (0x220) #define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_7 (0x1001c224) +#ifndef DV_REG_DATAVAULTCTRL_7 #define DV_REG_DATAVAULTCTRL_7 (0x224) #define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_8 (0x1001c228) +#ifndef DV_REG_DATAVAULTCTRL_8 #define DV_REG_DATAVAULTCTRL_8 (0x228) #define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATAVAULTCTRL_9 (0x1001c22c) +#ifndef DV_REG_DATAVAULTCTRL_9 #define DV_REG_DATAVAULTCTRL_9 (0x22c) #define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_LOW (0) #define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_0 (0x1001c230) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_0 #define DV_REG_DATA_VAULT_ENTRY_0_0 (0x230) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_1 (0x1001c234) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_1 #define DV_REG_DATA_VAULT_ENTRY_0_1 (0x234) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_2 (0x1001c238) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_2 #define DV_REG_DATA_VAULT_ENTRY_0_2 (0x238) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_3 (0x1001c23c) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_3 #define DV_REG_DATA_VAULT_ENTRY_0_3 (0x23c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_4 (0x1001c240) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_4 #define DV_REG_DATA_VAULT_ENTRY_0_4 (0x240) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_5 (0x1001c244) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_5 #define DV_REG_DATA_VAULT_ENTRY_0_5 (0x244) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_6 (0x1001c248) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_6 #define DV_REG_DATA_VAULT_ENTRY_0_6 (0x248) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_7 (0x1001c24c) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_7 #define DV_REG_DATA_VAULT_ENTRY_0_7 (0x24c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_8 (0x1001c250) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_8 #define DV_REG_DATA_VAULT_ENTRY_0_8 (0x250) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_9 (0x1001c254) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_9 #define DV_REG_DATA_VAULT_ENTRY_0_9 (0x254) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_10 (0x1001c258) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_10 #define DV_REG_DATA_VAULT_ENTRY_0_10 (0x258) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_0_11 (0x1001c25c) +#ifndef DV_REG_DATA_VAULT_ENTRY_0_11 #define DV_REG_DATA_VAULT_ENTRY_0_11 (0x25c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_0 (0x1001c260) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_0 #define DV_REG_DATA_VAULT_ENTRY_1_0 (0x260) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_1 (0x1001c264) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_1 #define DV_REG_DATA_VAULT_ENTRY_1_1 (0x264) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_2 (0x1001c268) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_2 #define DV_REG_DATA_VAULT_ENTRY_1_2 (0x268) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_3 (0x1001c26c) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_3 #define DV_REG_DATA_VAULT_ENTRY_1_3 (0x26c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_4 (0x1001c270) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_4 #define DV_REG_DATA_VAULT_ENTRY_1_4 (0x270) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_5 (0x1001c274) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_5 #define DV_REG_DATA_VAULT_ENTRY_1_5 (0x274) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_6 (0x1001c278) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_6 #define DV_REG_DATA_VAULT_ENTRY_1_6 (0x278) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_7 (0x1001c27c) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_7 #define DV_REG_DATA_VAULT_ENTRY_1_7 (0x27c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_8 (0x1001c280) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_8 #define DV_REG_DATA_VAULT_ENTRY_1_8 (0x280) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_9 (0x1001c284) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_9 #define DV_REG_DATA_VAULT_ENTRY_1_9 (0x284) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_10 (0x1001c288) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_10 #define DV_REG_DATA_VAULT_ENTRY_1_10 (0x288) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_1_11 (0x1001c28c) +#ifndef DV_REG_DATA_VAULT_ENTRY_1_11 #define DV_REG_DATA_VAULT_ENTRY_1_11 (0x28c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_0 (0x1001c290) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_0 #define DV_REG_DATA_VAULT_ENTRY_2_0 (0x290) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_1 (0x1001c294) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_1 #define DV_REG_DATA_VAULT_ENTRY_2_1 (0x294) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_2 (0x1001c298) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_2 #define DV_REG_DATA_VAULT_ENTRY_2_2 (0x298) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_3 (0x1001c29c) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_3 #define DV_REG_DATA_VAULT_ENTRY_2_3 (0x29c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_4 (0x1001c2a0) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_4 #define DV_REG_DATA_VAULT_ENTRY_2_4 (0x2a0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_5 (0x1001c2a4) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_5 #define DV_REG_DATA_VAULT_ENTRY_2_5 (0x2a4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_6 (0x1001c2a8) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_6 #define DV_REG_DATA_VAULT_ENTRY_2_6 (0x2a8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_7 (0x1001c2ac) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_7 #define DV_REG_DATA_VAULT_ENTRY_2_7 (0x2ac) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_8 (0x1001c2b0) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_8 #define DV_REG_DATA_VAULT_ENTRY_2_8 (0x2b0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_9 (0x1001c2b4) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_9 #define DV_REG_DATA_VAULT_ENTRY_2_9 (0x2b4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_10 (0x1001c2b8) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_10 #define DV_REG_DATA_VAULT_ENTRY_2_10 (0x2b8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_2_11 (0x1001c2bc) +#ifndef DV_REG_DATA_VAULT_ENTRY_2_11 #define DV_REG_DATA_VAULT_ENTRY_2_11 (0x2bc) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_0 (0x1001c2c0) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_0 #define DV_REG_DATA_VAULT_ENTRY_3_0 (0x2c0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_1 (0x1001c2c4) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_1 #define DV_REG_DATA_VAULT_ENTRY_3_1 (0x2c4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_2 (0x1001c2c8) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_2 #define DV_REG_DATA_VAULT_ENTRY_3_2 (0x2c8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_3 (0x1001c2cc) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_3 #define DV_REG_DATA_VAULT_ENTRY_3_3 (0x2cc) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_4 (0x1001c2d0) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_4 #define DV_REG_DATA_VAULT_ENTRY_3_4 (0x2d0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_5 (0x1001c2d4) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_5 #define DV_REG_DATA_VAULT_ENTRY_3_5 (0x2d4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_6 (0x1001c2d8) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_6 #define DV_REG_DATA_VAULT_ENTRY_3_6 (0x2d8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_7 (0x1001c2dc) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_7 #define DV_REG_DATA_VAULT_ENTRY_3_7 (0x2dc) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_8 (0x1001c2e0) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_8 #define DV_REG_DATA_VAULT_ENTRY_3_8 (0x2e0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_9 (0x1001c2e4) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_9 #define DV_REG_DATA_VAULT_ENTRY_3_9 (0x2e4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_10 (0x1001c2e8) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_10 #define DV_REG_DATA_VAULT_ENTRY_3_10 (0x2e8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_3_11 (0x1001c2ec) +#ifndef DV_REG_DATA_VAULT_ENTRY_3_11 #define DV_REG_DATA_VAULT_ENTRY_3_11 (0x2ec) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_0 (0x1001c2f0) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_0 #define DV_REG_DATA_VAULT_ENTRY_4_0 (0x2f0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_1 (0x1001c2f4) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_1 #define DV_REG_DATA_VAULT_ENTRY_4_1 (0x2f4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_2 (0x1001c2f8) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_2 #define DV_REG_DATA_VAULT_ENTRY_4_2 (0x2f8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_3 (0x1001c2fc) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_3 #define DV_REG_DATA_VAULT_ENTRY_4_3 (0x2fc) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_4 (0x1001c300) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_4 #define DV_REG_DATA_VAULT_ENTRY_4_4 (0x300) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_5 (0x1001c304) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_5 #define DV_REG_DATA_VAULT_ENTRY_4_5 (0x304) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_6 (0x1001c308) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_6 #define DV_REG_DATA_VAULT_ENTRY_4_6 (0x308) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_7 (0x1001c30c) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_7 #define DV_REG_DATA_VAULT_ENTRY_4_7 (0x30c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_8 (0x1001c310) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_8 #define DV_REG_DATA_VAULT_ENTRY_4_8 (0x310) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_9 (0x1001c314) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_9 #define DV_REG_DATA_VAULT_ENTRY_4_9 (0x314) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_10 (0x1001c318) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_10 #define DV_REG_DATA_VAULT_ENTRY_4_10 (0x318) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_4_11 (0x1001c31c) +#ifndef DV_REG_DATA_VAULT_ENTRY_4_11 #define DV_REG_DATA_VAULT_ENTRY_4_11 (0x31c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_0 (0x1001c320) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_0 #define DV_REG_DATA_VAULT_ENTRY_5_0 (0x320) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_1 (0x1001c324) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_1 #define DV_REG_DATA_VAULT_ENTRY_5_1 (0x324) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_2 (0x1001c328) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_2 #define DV_REG_DATA_VAULT_ENTRY_5_2 (0x328) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_3 (0x1001c32c) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_3 #define DV_REG_DATA_VAULT_ENTRY_5_3 (0x32c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_4 (0x1001c330) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_4 #define DV_REG_DATA_VAULT_ENTRY_5_4 (0x330) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_5 (0x1001c334) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_5 #define DV_REG_DATA_VAULT_ENTRY_5_5 (0x334) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_6 (0x1001c338) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_6 #define DV_REG_DATA_VAULT_ENTRY_5_6 (0x338) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_7 (0x1001c33c) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_7 #define DV_REG_DATA_VAULT_ENTRY_5_7 (0x33c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_8 (0x1001c340) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_8 #define DV_REG_DATA_VAULT_ENTRY_5_8 (0x340) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_9 (0x1001c344) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_9 #define DV_REG_DATA_VAULT_ENTRY_5_9 (0x344) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_10 (0x1001c348) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_10 #define DV_REG_DATA_VAULT_ENTRY_5_10 (0x348) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_5_11 (0x1001c34c) +#ifndef DV_REG_DATA_VAULT_ENTRY_5_11 #define DV_REG_DATA_VAULT_ENTRY_5_11 (0x34c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_0 (0x1001c350) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_0 #define DV_REG_DATA_VAULT_ENTRY_6_0 (0x350) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_1 (0x1001c354) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_1 #define DV_REG_DATA_VAULT_ENTRY_6_1 (0x354) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_2 (0x1001c358) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_2 #define DV_REG_DATA_VAULT_ENTRY_6_2 (0x358) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_3 (0x1001c35c) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_3 #define DV_REG_DATA_VAULT_ENTRY_6_3 (0x35c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_4 (0x1001c360) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_4 #define DV_REG_DATA_VAULT_ENTRY_6_4 (0x360) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_5 (0x1001c364) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_5 #define DV_REG_DATA_VAULT_ENTRY_6_5 (0x364) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_6 (0x1001c368) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_6 #define DV_REG_DATA_VAULT_ENTRY_6_6 (0x368) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_7 (0x1001c36c) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_7 #define DV_REG_DATA_VAULT_ENTRY_6_7 (0x36c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_8 (0x1001c370) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_8 #define DV_REG_DATA_VAULT_ENTRY_6_8 (0x370) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_9 (0x1001c374) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_9 #define DV_REG_DATA_VAULT_ENTRY_6_9 (0x374) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_10 (0x1001c378) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_10 #define DV_REG_DATA_VAULT_ENTRY_6_10 (0x378) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_6_11 (0x1001c37c) +#ifndef DV_REG_DATA_VAULT_ENTRY_6_11 #define DV_REG_DATA_VAULT_ENTRY_6_11 (0x37c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_0 (0x1001c380) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_0 #define DV_REG_DATA_VAULT_ENTRY_7_0 (0x380) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_1 (0x1001c384) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_1 #define DV_REG_DATA_VAULT_ENTRY_7_1 (0x384) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_2 (0x1001c388) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_2 #define DV_REG_DATA_VAULT_ENTRY_7_2 (0x388) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_3 (0x1001c38c) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_3 #define DV_REG_DATA_VAULT_ENTRY_7_3 (0x38c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_4 (0x1001c390) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_4 #define DV_REG_DATA_VAULT_ENTRY_7_4 (0x390) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_5 (0x1001c394) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_5 #define DV_REG_DATA_VAULT_ENTRY_7_5 (0x394) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_6 (0x1001c398) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_6 #define DV_REG_DATA_VAULT_ENTRY_7_6 (0x398) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_7 (0x1001c39c) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_7 #define DV_REG_DATA_VAULT_ENTRY_7_7 (0x39c) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_8 (0x1001c3a0) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_8 #define DV_REG_DATA_VAULT_ENTRY_7_8 (0x3a0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_9 (0x1001c3a4) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_9 #define DV_REG_DATA_VAULT_ENTRY_7_9 (0x3a4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_10 (0x1001c3a8) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_10 #define DV_REG_DATA_VAULT_ENTRY_7_10 (0x3a8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_7_11 (0x1001c3ac) +#ifndef DV_REG_DATA_VAULT_ENTRY_7_11 #define DV_REG_DATA_VAULT_ENTRY_7_11 (0x3ac) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_0 (0x1001c3b0) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_0 #define DV_REG_DATA_VAULT_ENTRY_8_0 (0x3b0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_1 (0x1001c3b4) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_1 #define DV_REG_DATA_VAULT_ENTRY_8_1 (0x3b4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_2 (0x1001c3b8) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_2 #define DV_REG_DATA_VAULT_ENTRY_8_2 (0x3b8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_3 (0x1001c3bc) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_3 #define DV_REG_DATA_VAULT_ENTRY_8_3 (0x3bc) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_4 (0x1001c3c0) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_4 #define DV_REG_DATA_VAULT_ENTRY_8_4 (0x3c0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_5 (0x1001c3c4) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_5 #define DV_REG_DATA_VAULT_ENTRY_8_5 (0x3c4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_6 (0x1001c3c8) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_6 #define DV_REG_DATA_VAULT_ENTRY_8_6 (0x3c8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_7 (0x1001c3cc) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_7 #define DV_REG_DATA_VAULT_ENTRY_8_7 (0x3cc) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_8 (0x1001c3d0) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_8 #define DV_REG_DATA_VAULT_ENTRY_8_8 (0x3d0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_9 (0x1001c3d4) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_9 #define DV_REG_DATA_VAULT_ENTRY_8_9 (0x3d4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_10 (0x1001c3d8) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_10 #define DV_REG_DATA_VAULT_ENTRY_8_10 (0x3d8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_8_11 (0x1001c3dc) +#ifndef DV_REG_DATA_VAULT_ENTRY_8_11 #define DV_REG_DATA_VAULT_ENTRY_8_11 (0x3dc) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_0 (0x1001c3e0) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_0 #define DV_REG_DATA_VAULT_ENTRY_9_0 (0x3e0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_1 (0x1001c3e4) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_1 #define DV_REG_DATA_VAULT_ENTRY_9_1 (0x3e4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_2 (0x1001c3e8) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_2 #define DV_REG_DATA_VAULT_ENTRY_9_2 (0x3e8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_3 (0x1001c3ec) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_3 #define DV_REG_DATA_VAULT_ENTRY_9_3 (0x3ec) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_4 (0x1001c3f0) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_4 #define DV_REG_DATA_VAULT_ENTRY_9_4 (0x3f0) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_5 (0x1001c3f4) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_5 #define DV_REG_DATA_VAULT_ENTRY_9_5 (0x3f4) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_6 (0x1001c3f8) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_6 #define DV_REG_DATA_VAULT_ENTRY_9_6 (0x3f8) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_7 (0x1001c3fc) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_7 #define DV_REG_DATA_VAULT_ENTRY_9_7 (0x3fc) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_8 (0x1001c400) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_8 #define DV_REG_DATA_VAULT_ENTRY_9_8 (0x400) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_9 (0x1001c404) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_9 #define DV_REG_DATA_VAULT_ENTRY_9_9 (0x404) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_10 (0x1001c408) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_10 #define DV_REG_DATA_VAULT_ENTRY_9_10 (0x408) +#endif #define CLP_DV_REG_DATA_VAULT_ENTRY_9_11 (0x1001c40c) +#ifndef DV_REG_DATA_VAULT_ENTRY_9_11 #define DV_REG_DATA_VAULT_ENTRY_9_11 (0x40c) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_0 (0x1001c410) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_0 #define DV_REG_LOCKABLESCRATCHREGCTRL_0 (0x410) #define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_1 (0x1001c414) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_1 #define DV_REG_LOCKABLESCRATCHREGCTRL_1 (0x414) #define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_2 (0x1001c418) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_2 #define DV_REG_LOCKABLESCRATCHREGCTRL_2 (0x418) #define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_3 (0x1001c41c) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_3 #define DV_REG_LOCKABLESCRATCHREGCTRL_3 (0x41c) #define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_4 (0x1001c420) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_4 #define DV_REG_LOCKABLESCRATCHREGCTRL_4 (0x420) #define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_5 (0x1001c424) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_5 #define DV_REG_LOCKABLESCRATCHREGCTRL_5 (0x424) #define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_6 (0x1001c428) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_6 #define DV_REG_LOCKABLESCRATCHREGCTRL_6 (0x428) #define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_7 (0x1001c42c) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_7 #define DV_REG_LOCKABLESCRATCHREGCTRL_7 (0x42c) #define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_8 (0x1001c430) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_8 #define DV_REG_LOCKABLESCRATCHREGCTRL_8 (0x430) #define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_9 (0x1001c434) +#ifndef DV_REG_LOCKABLESCRATCHREGCTRL_9 #define DV_REG_LOCKABLESCRATCHREGCTRL_9 (0x434) #define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_LOW (0) #define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_0 (0x1001c438) +#ifndef DV_REG_LOCKABLESCRATCHREG_0 #define DV_REG_LOCKABLESCRATCHREG_0 (0x438) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_1 (0x1001c43c) +#ifndef DV_REG_LOCKABLESCRATCHREG_1 #define DV_REG_LOCKABLESCRATCHREG_1 (0x43c) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_2 (0x1001c440) +#ifndef DV_REG_LOCKABLESCRATCHREG_2 #define DV_REG_LOCKABLESCRATCHREG_2 (0x440) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_3 (0x1001c444) +#ifndef DV_REG_LOCKABLESCRATCHREG_3 #define DV_REG_LOCKABLESCRATCHREG_3 (0x444) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_4 (0x1001c448) +#ifndef DV_REG_LOCKABLESCRATCHREG_4 #define DV_REG_LOCKABLESCRATCHREG_4 (0x448) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_5 (0x1001c44c) +#ifndef DV_REG_LOCKABLESCRATCHREG_5 #define DV_REG_LOCKABLESCRATCHREG_5 (0x44c) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_6 (0x1001c450) +#ifndef DV_REG_LOCKABLESCRATCHREG_6 #define DV_REG_LOCKABLESCRATCHREG_6 (0x450) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_7 (0x1001c454) +#ifndef DV_REG_LOCKABLESCRATCHREG_7 #define DV_REG_LOCKABLESCRATCHREG_7 (0x454) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_8 (0x1001c458) +#ifndef DV_REG_LOCKABLESCRATCHREG_8 #define DV_REG_LOCKABLESCRATCHREG_8 (0x458) +#endif #define CLP_DV_REG_LOCKABLESCRATCHREG_9 (0x1001c45c) +#ifndef DV_REG_LOCKABLESCRATCHREG_9 #define DV_REG_LOCKABLESCRATCHREG_9 (0x45c) +#endif #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_0 (0x1001c460) +#ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_0 #define DV_REG_NONSTICKYGENERICSCRATCHREG_0 (0x460) +#endif #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_1 (0x1001c464) +#ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_1 #define DV_REG_NONSTICKYGENERICSCRATCHREG_1 (0x464) +#endif #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_2 (0x1001c468) +#ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_2 #define DV_REG_NONSTICKYGENERICSCRATCHREG_2 (0x468) +#endif #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_3 (0x1001c46c) +#ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_3 #define DV_REG_NONSTICKYGENERICSCRATCHREG_3 (0x46c) +#endif #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_4 (0x1001c470) +#ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_4 #define DV_REG_NONSTICKYGENERICSCRATCHREG_4 (0x470) +#endif #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_5 (0x1001c474) +#ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_5 #define DV_REG_NONSTICKYGENERICSCRATCHREG_5 (0x474) +#endif #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_6 (0x1001c478) +#ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_6 #define DV_REG_NONSTICKYGENERICSCRATCHREG_6 (0x478) +#endif #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_7 (0x1001c47c) +#ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_7 #define DV_REG_NONSTICKYGENERICSCRATCHREG_7 (0x47c) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0 (0x1001c480) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0 #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0 (0x480) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1 (0x1001c484) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1 #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1 (0x484) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2 (0x1001c488) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2 #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2 (0x488) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3 (0x1001c48c) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3 #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3 (0x48c) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4 (0x1001c490) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4 #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4 (0x490) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5 (0x1001c494) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5 #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5 (0x494) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6 (0x1001c498) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6 #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6 (0x498) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7 (0x1001c49c) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7 #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7 (0x49c) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW (0) #define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK (0x1) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_0 (0x1001c4a0) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREG_0 #define DV_REG_STICKYLOCKABLESCRATCHREG_0 (0x4a0) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_1 (0x1001c4a4) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREG_1 #define DV_REG_STICKYLOCKABLESCRATCHREG_1 (0x4a4) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_2 (0x1001c4a8) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREG_2 #define DV_REG_STICKYLOCKABLESCRATCHREG_2 (0x4a8) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_3 (0x1001c4ac) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREG_3 #define DV_REG_STICKYLOCKABLESCRATCHREG_3 (0x4ac) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_4 (0x1001c4b0) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREG_4 #define DV_REG_STICKYLOCKABLESCRATCHREG_4 (0x4b0) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_5 (0x1001c4b4) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREG_5 #define DV_REG_STICKYLOCKABLESCRATCHREG_5 (0x4b4) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_6 (0x1001c4b8) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREG_6 #define DV_REG_STICKYLOCKABLESCRATCHREG_6 (0x4b8) +#endif #define CLP_DV_REG_STICKYLOCKABLESCRATCHREG_7 (0x1001c4bc) +#ifndef DV_REG_STICKYLOCKABLESCRATCHREG_7 #define DV_REG_STICKYLOCKABLESCRATCHREG_7 (0x4bc) +#endif #define CLP_SHA512_REG_BASE_ADDR (0x10020000) #define CLP_SHA512_REG_SHA512_NAME_0 (0x10020000) +#ifndef SHA512_REG_SHA512_NAME_0 #define SHA512_REG_SHA512_NAME_0 (0x0) +#endif #define CLP_SHA512_REG_SHA512_NAME_1 (0x10020004) +#ifndef SHA512_REG_SHA512_NAME_1 #define SHA512_REG_SHA512_NAME_1 (0x4) +#endif #define CLP_SHA512_REG_SHA512_VERSION_0 (0x10020008) +#ifndef SHA512_REG_SHA512_VERSION_0 #define SHA512_REG_SHA512_VERSION_0 (0x8) +#endif #define CLP_SHA512_REG_SHA512_VERSION_1 (0x1002000c) +#ifndef SHA512_REG_SHA512_VERSION_1 #define SHA512_REG_SHA512_VERSION_1 (0xc) +#endif #define CLP_SHA512_REG_SHA512_CTRL (0x10020010) +#ifndef SHA512_REG_SHA512_CTRL #define SHA512_REG_SHA512_CTRL (0x10) #define SHA512_REG_SHA512_CTRL_INIT_LOW (0) #define SHA512_REG_SHA512_CTRL_INIT_MASK (0x1) @@ -4074,109 +7061,209 @@ #define SHA512_REG_SHA512_CTRL_LAST_MASK (0x20) #define SHA512_REG_SHA512_CTRL_RESTORE_LOW (6) #define SHA512_REG_SHA512_CTRL_RESTORE_MASK (0x40) +#endif #define CLP_SHA512_REG_SHA512_STATUS (0x10020018) +#ifndef SHA512_REG_SHA512_STATUS #define SHA512_REG_SHA512_STATUS (0x18) #define SHA512_REG_SHA512_STATUS_READY_LOW (0) #define SHA512_REG_SHA512_STATUS_READY_MASK (0x1) #define SHA512_REG_SHA512_STATUS_VALID_LOW (1) #define SHA512_REG_SHA512_STATUS_VALID_MASK (0x2) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_0 (0x10020080) +#ifndef SHA512_REG_SHA512_BLOCK_0 #define SHA512_REG_SHA512_BLOCK_0 (0x80) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_1 (0x10020084) +#ifndef SHA512_REG_SHA512_BLOCK_1 #define SHA512_REG_SHA512_BLOCK_1 (0x84) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_2 (0x10020088) +#ifndef SHA512_REG_SHA512_BLOCK_2 #define SHA512_REG_SHA512_BLOCK_2 (0x88) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_3 (0x1002008c) +#ifndef SHA512_REG_SHA512_BLOCK_3 #define SHA512_REG_SHA512_BLOCK_3 (0x8c) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_4 (0x10020090) +#ifndef SHA512_REG_SHA512_BLOCK_4 #define SHA512_REG_SHA512_BLOCK_4 (0x90) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_5 (0x10020094) +#ifndef SHA512_REG_SHA512_BLOCK_5 #define SHA512_REG_SHA512_BLOCK_5 (0x94) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_6 (0x10020098) +#ifndef SHA512_REG_SHA512_BLOCK_6 #define SHA512_REG_SHA512_BLOCK_6 (0x98) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_7 (0x1002009c) +#ifndef SHA512_REG_SHA512_BLOCK_7 #define SHA512_REG_SHA512_BLOCK_7 (0x9c) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_8 (0x100200a0) +#ifndef SHA512_REG_SHA512_BLOCK_8 #define SHA512_REG_SHA512_BLOCK_8 (0xa0) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_9 (0x100200a4) +#ifndef SHA512_REG_SHA512_BLOCK_9 #define SHA512_REG_SHA512_BLOCK_9 (0xa4) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_10 (0x100200a8) +#ifndef SHA512_REG_SHA512_BLOCK_10 #define SHA512_REG_SHA512_BLOCK_10 (0xa8) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_11 (0x100200ac) +#ifndef SHA512_REG_SHA512_BLOCK_11 #define SHA512_REG_SHA512_BLOCK_11 (0xac) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_12 (0x100200b0) +#ifndef SHA512_REG_SHA512_BLOCK_12 #define SHA512_REG_SHA512_BLOCK_12 (0xb0) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_13 (0x100200b4) +#ifndef SHA512_REG_SHA512_BLOCK_13 #define SHA512_REG_SHA512_BLOCK_13 (0xb4) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_14 (0x100200b8) +#ifndef SHA512_REG_SHA512_BLOCK_14 #define SHA512_REG_SHA512_BLOCK_14 (0xb8) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_15 (0x100200bc) +#ifndef SHA512_REG_SHA512_BLOCK_15 #define SHA512_REG_SHA512_BLOCK_15 (0xbc) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_16 (0x100200c0) +#ifndef SHA512_REG_SHA512_BLOCK_16 #define SHA512_REG_SHA512_BLOCK_16 (0xc0) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_17 (0x100200c4) +#ifndef SHA512_REG_SHA512_BLOCK_17 #define SHA512_REG_SHA512_BLOCK_17 (0xc4) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_18 (0x100200c8) +#ifndef SHA512_REG_SHA512_BLOCK_18 #define SHA512_REG_SHA512_BLOCK_18 (0xc8) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_19 (0x100200cc) +#ifndef SHA512_REG_SHA512_BLOCK_19 #define SHA512_REG_SHA512_BLOCK_19 (0xcc) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_20 (0x100200d0) +#ifndef SHA512_REG_SHA512_BLOCK_20 #define SHA512_REG_SHA512_BLOCK_20 (0xd0) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_21 (0x100200d4) +#ifndef SHA512_REG_SHA512_BLOCK_21 #define SHA512_REG_SHA512_BLOCK_21 (0xd4) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_22 (0x100200d8) +#ifndef SHA512_REG_SHA512_BLOCK_22 #define SHA512_REG_SHA512_BLOCK_22 (0xd8) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_23 (0x100200dc) +#ifndef SHA512_REG_SHA512_BLOCK_23 #define SHA512_REG_SHA512_BLOCK_23 (0xdc) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_24 (0x100200e0) +#ifndef SHA512_REG_SHA512_BLOCK_24 #define SHA512_REG_SHA512_BLOCK_24 (0xe0) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_25 (0x100200e4) +#ifndef SHA512_REG_SHA512_BLOCK_25 #define SHA512_REG_SHA512_BLOCK_25 (0xe4) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_26 (0x100200e8) +#ifndef SHA512_REG_SHA512_BLOCK_26 #define SHA512_REG_SHA512_BLOCK_26 (0xe8) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_27 (0x100200ec) +#ifndef SHA512_REG_SHA512_BLOCK_27 #define SHA512_REG_SHA512_BLOCK_27 (0xec) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_28 (0x100200f0) +#ifndef SHA512_REG_SHA512_BLOCK_28 #define SHA512_REG_SHA512_BLOCK_28 (0xf0) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_29 (0x100200f4) +#ifndef SHA512_REG_SHA512_BLOCK_29 #define SHA512_REG_SHA512_BLOCK_29 (0xf4) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_30 (0x100200f8) +#ifndef SHA512_REG_SHA512_BLOCK_30 #define SHA512_REG_SHA512_BLOCK_30 (0xf8) +#endif #define CLP_SHA512_REG_SHA512_BLOCK_31 (0x100200fc) +#ifndef SHA512_REG_SHA512_BLOCK_31 #define SHA512_REG_SHA512_BLOCK_31 (0xfc) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_0 (0x10020100) +#ifndef SHA512_REG_SHA512_DIGEST_0 #define SHA512_REG_SHA512_DIGEST_0 (0x100) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_1 (0x10020104) +#ifndef SHA512_REG_SHA512_DIGEST_1 #define SHA512_REG_SHA512_DIGEST_1 (0x104) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_2 (0x10020108) +#ifndef SHA512_REG_SHA512_DIGEST_2 #define SHA512_REG_SHA512_DIGEST_2 (0x108) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_3 (0x1002010c) +#ifndef SHA512_REG_SHA512_DIGEST_3 #define SHA512_REG_SHA512_DIGEST_3 (0x10c) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_4 (0x10020110) +#ifndef SHA512_REG_SHA512_DIGEST_4 #define SHA512_REG_SHA512_DIGEST_4 (0x110) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_5 (0x10020114) +#ifndef SHA512_REG_SHA512_DIGEST_5 #define SHA512_REG_SHA512_DIGEST_5 (0x114) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_6 (0x10020118) +#ifndef SHA512_REG_SHA512_DIGEST_6 #define SHA512_REG_SHA512_DIGEST_6 (0x118) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_7 (0x1002011c) +#ifndef SHA512_REG_SHA512_DIGEST_7 #define SHA512_REG_SHA512_DIGEST_7 (0x11c) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_8 (0x10020120) +#ifndef SHA512_REG_SHA512_DIGEST_8 #define SHA512_REG_SHA512_DIGEST_8 (0x120) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_9 (0x10020124) +#ifndef SHA512_REG_SHA512_DIGEST_9 #define SHA512_REG_SHA512_DIGEST_9 (0x124) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_10 (0x10020128) +#ifndef SHA512_REG_SHA512_DIGEST_10 #define SHA512_REG_SHA512_DIGEST_10 (0x128) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_11 (0x1002012c) +#ifndef SHA512_REG_SHA512_DIGEST_11 #define SHA512_REG_SHA512_DIGEST_11 (0x12c) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_12 (0x10020130) +#ifndef SHA512_REG_SHA512_DIGEST_12 #define SHA512_REG_SHA512_DIGEST_12 (0x130) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_13 (0x10020134) +#ifndef SHA512_REG_SHA512_DIGEST_13 #define SHA512_REG_SHA512_DIGEST_13 (0x134) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_14 (0x10020138) +#ifndef SHA512_REG_SHA512_DIGEST_14 #define SHA512_REG_SHA512_DIGEST_14 (0x138) +#endif #define CLP_SHA512_REG_SHA512_DIGEST_15 (0x1002013c) +#ifndef SHA512_REG_SHA512_DIGEST_15 #define SHA512_REG_SHA512_DIGEST_15 (0x13c) +#endif #define CLP_SHA512_REG_SHA512_VAULT_RD_CTRL (0x10020600) +#ifndef SHA512_REG_SHA512_VAULT_RD_CTRL #define SHA512_REG_SHA512_VAULT_RD_CTRL (0x600) #define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_EN_LOW (0) #define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_EN_MASK (0x1) @@ -4186,7 +7273,9 @@ #define SHA512_REG_SHA512_VAULT_RD_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define SHA512_REG_SHA512_VAULT_RD_CTRL_RSVD_LOW (7) #define SHA512_REG_SHA512_VAULT_RD_CTRL_RSVD_MASK (0xffffff80) +#endif #define CLP_SHA512_REG_SHA512_VAULT_RD_STATUS (0x10020604) +#ifndef SHA512_REG_SHA512_VAULT_RD_STATUS #define SHA512_REG_SHA512_VAULT_RD_STATUS (0x604) #define SHA512_REG_SHA512_VAULT_RD_STATUS_READY_LOW (0) #define SHA512_REG_SHA512_VAULT_RD_STATUS_READY_MASK (0x1) @@ -4194,7 +7283,9 @@ #define SHA512_REG_SHA512_VAULT_RD_STATUS_VALID_MASK (0x2) #define SHA512_REG_SHA512_VAULT_RD_STATUS_ERROR_LOW (2) #define SHA512_REG_SHA512_VAULT_RD_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_SHA512_REG_SHA512_KV_WR_CTRL (0x10020608) +#ifndef SHA512_REG_SHA512_KV_WR_CTRL #define SHA512_REG_SHA512_KV_WR_CTRL (0x608) #define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_EN_LOW (0) #define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_EN_MASK (0x1) @@ -4214,7 +7305,9 @@ #define SHA512_REG_SHA512_KV_WR_CTRL_AES_KEY_DEST_VALID_MASK (0x800) #define SHA512_REG_SHA512_KV_WR_CTRL_RSVD_LOW (12) #define SHA512_REG_SHA512_KV_WR_CTRL_RSVD_MASK (0xfffff000) +#endif #define CLP_SHA512_REG_SHA512_KV_WR_STATUS (0x1002060c) +#ifndef SHA512_REG_SHA512_KV_WR_STATUS #define SHA512_REG_SHA512_KV_WR_STATUS (0x60c) #define SHA512_REG_SHA512_KV_WR_STATUS_READY_LOW (0) #define SHA512_REG_SHA512_KV_WR_STATUS_READY_MASK (0x1) @@ -4222,72 +7315,128 @@ #define SHA512_REG_SHA512_KV_WR_STATUS_VALID_MASK (0x2) #define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_LOW (2) #define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0 (0x10020610) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0 #define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0 (0x610) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1 (0x10020614) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1 #define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1 (0x614) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2 (0x10020618) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2 #define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2 (0x618) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3 (0x1002061c) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3 #define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3 (0x61c) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4 (0x10020620) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4 #define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4 (0x620) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5 (0x10020624) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5 #define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5 (0x624) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6 (0x10020628) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6 #define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6 (0x628) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7 (0x1002062c) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7 #define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7 (0x62c) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_CTRL (0x10020630) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_CTRL #define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL (0x630) #define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_LOW (0) #define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_MASK (0x1) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_STATUS (0x10020634) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_STATUS #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS (0x634) #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_LOW (0) #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_MASK (0x1) #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_LOW (1) #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_MASK (0x2) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0 (0x10020638) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0 (0x638) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1 (0x1002063c) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1 (0x63c) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2 (0x10020640) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2 (0x640) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3 (0x10020644) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3 (0x644) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4 (0x10020648) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4 (0x648) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5 (0x1002064c) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5 (0x64c) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6 (0x10020650) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6 (0x650) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7 (0x10020654) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7 (0x654) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8 (0x10020658) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8 (0x658) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9 (0x1002065c) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9 (0x65c) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10 (0x10020660) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10 (0x660) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11 (0x10020664) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11 (0x664) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_12 (0x10020668) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_12 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_12 (0x668) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_13 (0x1002066c) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_13 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_13 (0x66c) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_14 (0x10020670) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_14 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_14 (0x670) +#endif #define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_15 (0x10020674) +#ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_15 #define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_15 (0x674) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_START (0x10020800) #define CLP_SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x10020800) +#ifndef SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x10020804) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (0x1) @@ -4297,19 +7446,27 @@ #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (0x4) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (0x8) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x10020808) +#ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x1002080c) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x10020810) +#ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x10020814) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (0x1) @@ -4319,11 +7476,15 @@ #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (0x4) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (0x8) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x10020818) +#ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x1002081c) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (0x1) @@ -4333,50 +7494,82 @@ #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (0x4) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) #define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (0x8) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x10020820) +#ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x10020900) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R #define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x900) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x10020904) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R #define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x904) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x10020908) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R #define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x908) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x1002090c) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R #define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x90c) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x10020980) +#ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R #define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x980) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0x10020a00) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R #define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0xa00) #define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0x10020a04) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R #define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0xa04) #define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0x10020a08) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R #define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0xa08) #define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0x10020a0c) +#ifndef SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R #define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0xa0c) #define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x10020a10) +#ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R #define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa10) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA256_REG_BASE_ADDR (0x10028000) #define CLP_SHA256_REG_SHA256_NAME_0 (0x10028000) +#ifndef SHA256_REG_SHA256_NAME_0 #define SHA256_REG_SHA256_NAME_0 (0x0) +#endif #define CLP_SHA256_REG_SHA256_NAME_1 (0x10028004) +#ifndef SHA256_REG_SHA256_NAME_1 #define SHA256_REG_SHA256_NAME_1 (0x4) +#endif #define CLP_SHA256_REG_SHA256_VERSION_0 (0x10028008) +#ifndef SHA256_REG_SHA256_VERSION_0 #define SHA256_REG_SHA256_VERSION_0 (0x8) +#endif #define CLP_SHA256_REG_SHA256_VERSION_1 (0x1002800c) +#ifndef SHA256_REG_SHA256_VERSION_1 #define SHA256_REG_SHA256_VERSION_1 (0xc) +#endif #define CLP_SHA256_REG_SHA256_CTRL (0x10028010) +#ifndef SHA256_REG_SHA256_CTRL #define SHA256_REG_SHA256_CTRL (0x10) #define SHA256_REG_SHA256_CTRL_INIT_LOW (0) #define SHA256_REG_SHA256_CTRL_INIT_MASK (0x1) @@ -4392,7 +7585,9 @@ #define SHA256_REG_SHA256_CTRL_WNTZ_W_MASK (0x1e0) #define SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_LOW (9) #define SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_MASK (0x200) +#endif #define CLP_SHA256_REG_SHA256_STATUS (0x10028018) +#ifndef SHA256_REG_SHA256_STATUS #define SHA256_REG_SHA256_STATUS (0x18) #define SHA256_REG_SHA256_STATUS_READY_LOW (0) #define SHA256_REG_SHA256_STATUS_READY_MASK (0x1) @@ -4400,62 +7595,114 @@ #define SHA256_REG_SHA256_STATUS_VALID_MASK (0x2) #define SHA256_REG_SHA256_STATUS_WNTZ_BUSY_LOW (2) #define SHA256_REG_SHA256_STATUS_WNTZ_BUSY_MASK (0x4) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_0 (0x10028080) +#ifndef SHA256_REG_SHA256_BLOCK_0 #define SHA256_REG_SHA256_BLOCK_0 (0x80) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_1 (0x10028084) +#ifndef SHA256_REG_SHA256_BLOCK_1 #define SHA256_REG_SHA256_BLOCK_1 (0x84) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_2 (0x10028088) +#ifndef SHA256_REG_SHA256_BLOCK_2 #define SHA256_REG_SHA256_BLOCK_2 (0x88) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_3 (0x1002808c) +#ifndef SHA256_REG_SHA256_BLOCK_3 #define SHA256_REG_SHA256_BLOCK_3 (0x8c) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_4 (0x10028090) +#ifndef SHA256_REG_SHA256_BLOCK_4 #define SHA256_REG_SHA256_BLOCK_4 (0x90) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_5 (0x10028094) +#ifndef SHA256_REG_SHA256_BLOCK_5 #define SHA256_REG_SHA256_BLOCK_5 (0x94) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_6 (0x10028098) +#ifndef SHA256_REG_SHA256_BLOCK_6 #define SHA256_REG_SHA256_BLOCK_6 (0x98) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_7 (0x1002809c) +#ifndef SHA256_REG_SHA256_BLOCK_7 #define SHA256_REG_SHA256_BLOCK_7 (0x9c) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_8 (0x100280a0) +#ifndef SHA256_REG_SHA256_BLOCK_8 #define SHA256_REG_SHA256_BLOCK_8 (0xa0) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_9 (0x100280a4) +#ifndef SHA256_REG_SHA256_BLOCK_9 #define SHA256_REG_SHA256_BLOCK_9 (0xa4) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_10 (0x100280a8) +#ifndef SHA256_REG_SHA256_BLOCK_10 #define SHA256_REG_SHA256_BLOCK_10 (0xa8) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_11 (0x100280ac) +#ifndef SHA256_REG_SHA256_BLOCK_11 #define SHA256_REG_SHA256_BLOCK_11 (0xac) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_12 (0x100280b0) +#ifndef SHA256_REG_SHA256_BLOCK_12 #define SHA256_REG_SHA256_BLOCK_12 (0xb0) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_13 (0x100280b4) +#ifndef SHA256_REG_SHA256_BLOCK_13 #define SHA256_REG_SHA256_BLOCK_13 (0xb4) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_14 (0x100280b8) +#ifndef SHA256_REG_SHA256_BLOCK_14 #define SHA256_REG_SHA256_BLOCK_14 (0xb8) +#endif #define CLP_SHA256_REG_SHA256_BLOCK_15 (0x100280bc) +#ifndef SHA256_REG_SHA256_BLOCK_15 #define SHA256_REG_SHA256_BLOCK_15 (0xbc) +#endif #define CLP_SHA256_REG_SHA256_DIGEST_0 (0x10028100) +#ifndef SHA256_REG_SHA256_DIGEST_0 #define SHA256_REG_SHA256_DIGEST_0 (0x100) +#endif #define CLP_SHA256_REG_SHA256_DIGEST_1 (0x10028104) +#ifndef SHA256_REG_SHA256_DIGEST_1 #define SHA256_REG_SHA256_DIGEST_1 (0x104) +#endif #define CLP_SHA256_REG_SHA256_DIGEST_2 (0x10028108) +#ifndef SHA256_REG_SHA256_DIGEST_2 #define SHA256_REG_SHA256_DIGEST_2 (0x108) +#endif #define CLP_SHA256_REG_SHA256_DIGEST_3 (0x1002810c) +#ifndef SHA256_REG_SHA256_DIGEST_3 #define SHA256_REG_SHA256_DIGEST_3 (0x10c) +#endif #define CLP_SHA256_REG_SHA256_DIGEST_4 (0x10028110) +#ifndef SHA256_REG_SHA256_DIGEST_4 #define SHA256_REG_SHA256_DIGEST_4 (0x110) +#endif #define CLP_SHA256_REG_SHA256_DIGEST_5 (0x10028114) +#ifndef SHA256_REG_SHA256_DIGEST_5 #define SHA256_REG_SHA256_DIGEST_5 (0x114) +#endif #define CLP_SHA256_REG_SHA256_DIGEST_6 (0x10028118) +#ifndef SHA256_REG_SHA256_DIGEST_6 #define SHA256_REG_SHA256_DIGEST_6 (0x118) +#endif #define CLP_SHA256_REG_SHA256_DIGEST_7 (0x1002811c) +#ifndef SHA256_REG_SHA256_DIGEST_7 #define SHA256_REG_SHA256_DIGEST_7 (0x11c) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_START (0x10028800) #define CLP_SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x10028800) +#ifndef SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x10028804) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (0x1) @@ -4465,19 +7712,27 @@ #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (0x4) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (0x8) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x10028808) +#ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x1002880c) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x10028810) +#ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x10028814) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (0x1) @@ -4487,11 +7742,15 @@ #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (0x4) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (0x8) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x10028818) +#ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x1002881c) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (0x1) @@ -4501,50 +7760,82 @@ #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (0x4) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) #define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (0x8) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x10028820) +#ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x10028900) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R #define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x900) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x10028904) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R #define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x904) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x10028908) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R #define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x908) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x1002890c) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R #define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x90c) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x10028980) +#ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R #define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x980) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0x10028a00) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R #define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0xa00) #define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0x10028a04) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R #define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0xa04) #define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0x10028a08) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R #define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0xa08) #define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0x10028a0c) +#ifndef SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R #define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0xa0c) #define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x10028a10) +#ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R #define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa10) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_MLDSA_REG_BASE_ADDR (0x10030000) #define CLP_MLDSA_REG_MLDSA_NAME_0 (0x10030000) +#ifndef MLDSA_REG_MLDSA_NAME_0 #define MLDSA_REG_MLDSA_NAME_0 (0x0) +#endif #define CLP_MLDSA_REG_MLDSA_NAME_1 (0x10030004) +#ifndef MLDSA_REG_MLDSA_NAME_1 #define MLDSA_REG_MLDSA_NAME_1 (0x4) +#endif #define CLP_MLDSA_REG_MLDSA_VERSION_0 (0x10030008) +#ifndef MLDSA_REG_MLDSA_VERSION_0 #define MLDSA_REG_MLDSA_VERSION_0 (0x8) +#endif #define CLP_MLDSA_REG_MLDSA_VERSION_1 (0x1003000c) +#ifndef MLDSA_REG_MLDSA_VERSION_1 #define MLDSA_REG_MLDSA_VERSION_1 (0xc) +#endif #define CLP_MLDSA_REG_MLDSA_CTRL (0x10030010) +#ifndef MLDSA_REG_MLDSA_CTRL #define MLDSA_REG_MLDSA_CTRL (0x10) #define MLDSA_REG_MLDSA_CTRL_CTRL_LOW (0) #define MLDSA_REG_MLDSA_CTRL_CTRL_MASK (0x7) @@ -4552,140 +7843,271 @@ #define MLDSA_REG_MLDSA_CTRL_ZEROIZE_MASK (0x8) #define MLDSA_REG_MLDSA_CTRL_PCR_SIGN_LOW (4) #define MLDSA_REG_MLDSA_CTRL_PCR_SIGN_MASK (0x10) +#endif #define CLP_MLDSA_REG_MLDSA_STATUS (0x10030014) +#ifndef MLDSA_REG_MLDSA_STATUS #define MLDSA_REG_MLDSA_STATUS (0x14) #define MLDSA_REG_MLDSA_STATUS_READY_LOW (0) #define MLDSA_REG_MLDSA_STATUS_READY_MASK (0x1) #define MLDSA_REG_MLDSA_STATUS_VALID_LOW (1) #define MLDSA_REG_MLDSA_STATUS_VALID_MASK (0x2) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_0 (0x10030018) +#ifndef MLDSA_REG_MLDSA_ENTROPY_0 #define MLDSA_REG_MLDSA_ENTROPY_0 (0x18) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_1 (0x1003001c) +#ifndef MLDSA_REG_MLDSA_ENTROPY_1 #define MLDSA_REG_MLDSA_ENTROPY_1 (0x1c) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_2 (0x10030020) +#ifndef MLDSA_REG_MLDSA_ENTROPY_2 #define MLDSA_REG_MLDSA_ENTROPY_2 (0x20) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_3 (0x10030024) +#ifndef MLDSA_REG_MLDSA_ENTROPY_3 #define MLDSA_REG_MLDSA_ENTROPY_3 (0x24) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_4 (0x10030028) +#ifndef MLDSA_REG_MLDSA_ENTROPY_4 #define MLDSA_REG_MLDSA_ENTROPY_4 (0x28) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_5 (0x1003002c) +#ifndef MLDSA_REG_MLDSA_ENTROPY_5 #define MLDSA_REG_MLDSA_ENTROPY_5 (0x2c) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_6 (0x10030030) +#ifndef MLDSA_REG_MLDSA_ENTROPY_6 #define MLDSA_REG_MLDSA_ENTROPY_6 (0x30) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_7 (0x10030034) +#ifndef MLDSA_REG_MLDSA_ENTROPY_7 #define MLDSA_REG_MLDSA_ENTROPY_7 (0x34) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_8 (0x10030038) +#ifndef MLDSA_REG_MLDSA_ENTROPY_8 #define MLDSA_REG_MLDSA_ENTROPY_8 (0x38) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_9 (0x1003003c) +#ifndef MLDSA_REG_MLDSA_ENTROPY_9 #define MLDSA_REG_MLDSA_ENTROPY_9 (0x3c) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_10 (0x10030040) +#ifndef MLDSA_REG_MLDSA_ENTROPY_10 #define MLDSA_REG_MLDSA_ENTROPY_10 (0x40) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_11 (0x10030044) +#ifndef MLDSA_REG_MLDSA_ENTROPY_11 #define MLDSA_REG_MLDSA_ENTROPY_11 (0x44) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_12 (0x10030048) +#ifndef MLDSA_REG_MLDSA_ENTROPY_12 #define MLDSA_REG_MLDSA_ENTROPY_12 (0x48) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_13 (0x1003004c) +#ifndef MLDSA_REG_MLDSA_ENTROPY_13 #define MLDSA_REG_MLDSA_ENTROPY_13 (0x4c) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_14 (0x10030050) +#ifndef MLDSA_REG_MLDSA_ENTROPY_14 #define MLDSA_REG_MLDSA_ENTROPY_14 (0x50) +#endif #define CLP_MLDSA_REG_MLDSA_ENTROPY_15 (0x10030054) +#ifndef MLDSA_REG_MLDSA_ENTROPY_15 #define MLDSA_REG_MLDSA_ENTROPY_15 (0x54) +#endif #define CLP_MLDSA_REG_MLDSA_SEED_0 (0x10030058) +#ifndef MLDSA_REG_MLDSA_SEED_0 #define MLDSA_REG_MLDSA_SEED_0 (0x58) +#endif #define CLP_MLDSA_REG_MLDSA_SEED_1 (0x1003005c) +#ifndef MLDSA_REG_MLDSA_SEED_1 #define MLDSA_REG_MLDSA_SEED_1 (0x5c) +#endif #define CLP_MLDSA_REG_MLDSA_SEED_2 (0x10030060) +#ifndef MLDSA_REG_MLDSA_SEED_2 #define MLDSA_REG_MLDSA_SEED_2 (0x60) +#endif #define CLP_MLDSA_REG_MLDSA_SEED_3 (0x10030064) +#ifndef MLDSA_REG_MLDSA_SEED_3 #define MLDSA_REG_MLDSA_SEED_3 (0x64) +#endif #define CLP_MLDSA_REG_MLDSA_SEED_4 (0x10030068) +#ifndef MLDSA_REG_MLDSA_SEED_4 #define MLDSA_REG_MLDSA_SEED_4 (0x68) +#endif #define CLP_MLDSA_REG_MLDSA_SEED_5 (0x1003006c) +#ifndef MLDSA_REG_MLDSA_SEED_5 #define MLDSA_REG_MLDSA_SEED_5 (0x6c) +#endif #define CLP_MLDSA_REG_MLDSA_SEED_6 (0x10030070) +#ifndef MLDSA_REG_MLDSA_SEED_6 #define MLDSA_REG_MLDSA_SEED_6 (0x70) +#endif #define CLP_MLDSA_REG_MLDSA_SEED_7 (0x10030074) +#ifndef MLDSA_REG_MLDSA_SEED_7 #define MLDSA_REG_MLDSA_SEED_7 (0x74) +#endif #define CLP_MLDSA_REG_MLDSA_SIGN_RND_0 (0x10030078) +#ifndef MLDSA_REG_MLDSA_SIGN_RND_0 #define MLDSA_REG_MLDSA_SIGN_RND_0 (0x78) +#endif #define CLP_MLDSA_REG_MLDSA_SIGN_RND_1 (0x1003007c) +#ifndef MLDSA_REG_MLDSA_SIGN_RND_1 #define MLDSA_REG_MLDSA_SIGN_RND_1 (0x7c) +#endif #define CLP_MLDSA_REG_MLDSA_SIGN_RND_2 (0x10030080) +#ifndef MLDSA_REG_MLDSA_SIGN_RND_2 #define MLDSA_REG_MLDSA_SIGN_RND_2 (0x80) +#endif #define CLP_MLDSA_REG_MLDSA_SIGN_RND_3 (0x10030084) +#ifndef MLDSA_REG_MLDSA_SIGN_RND_3 #define MLDSA_REG_MLDSA_SIGN_RND_3 (0x84) +#endif #define CLP_MLDSA_REG_MLDSA_SIGN_RND_4 (0x10030088) +#ifndef MLDSA_REG_MLDSA_SIGN_RND_4 #define MLDSA_REG_MLDSA_SIGN_RND_4 (0x88) +#endif #define CLP_MLDSA_REG_MLDSA_SIGN_RND_5 (0x1003008c) +#ifndef MLDSA_REG_MLDSA_SIGN_RND_5 #define MLDSA_REG_MLDSA_SIGN_RND_5 (0x8c) +#endif #define CLP_MLDSA_REG_MLDSA_SIGN_RND_6 (0x10030090) +#ifndef MLDSA_REG_MLDSA_SIGN_RND_6 #define MLDSA_REG_MLDSA_SIGN_RND_6 (0x90) +#endif #define CLP_MLDSA_REG_MLDSA_SIGN_RND_7 (0x10030094) +#ifndef MLDSA_REG_MLDSA_SIGN_RND_7 #define MLDSA_REG_MLDSA_SIGN_RND_7 (0x94) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_0 (0x10030098) +#ifndef MLDSA_REG_MLDSA_MSG_0 #define MLDSA_REG_MLDSA_MSG_0 (0x98) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_1 (0x1003009c) +#ifndef MLDSA_REG_MLDSA_MSG_1 #define MLDSA_REG_MLDSA_MSG_1 (0x9c) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_2 (0x100300a0) +#ifndef MLDSA_REG_MLDSA_MSG_2 #define MLDSA_REG_MLDSA_MSG_2 (0xa0) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_3 (0x100300a4) +#ifndef MLDSA_REG_MLDSA_MSG_3 #define MLDSA_REG_MLDSA_MSG_3 (0xa4) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_4 (0x100300a8) +#ifndef MLDSA_REG_MLDSA_MSG_4 #define MLDSA_REG_MLDSA_MSG_4 (0xa8) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_5 (0x100300ac) +#ifndef MLDSA_REG_MLDSA_MSG_5 #define MLDSA_REG_MLDSA_MSG_5 (0xac) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_6 (0x100300b0) +#ifndef MLDSA_REG_MLDSA_MSG_6 #define MLDSA_REG_MLDSA_MSG_6 (0xb0) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_7 (0x100300b4) +#ifndef MLDSA_REG_MLDSA_MSG_7 #define MLDSA_REG_MLDSA_MSG_7 (0xb4) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_8 (0x100300b8) +#ifndef MLDSA_REG_MLDSA_MSG_8 #define MLDSA_REG_MLDSA_MSG_8 (0xb8) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_9 (0x100300bc) +#ifndef MLDSA_REG_MLDSA_MSG_9 #define MLDSA_REG_MLDSA_MSG_9 (0xbc) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_10 (0x100300c0) +#ifndef MLDSA_REG_MLDSA_MSG_10 #define MLDSA_REG_MLDSA_MSG_10 (0xc0) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_11 (0x100300c4) +#ifndef MLDSA_REG_MLDSA_MSG_11 #define MLDSA_REG_MLDSA_MSG_11 (0xc4) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_12 (0x100300c8) +#ifndef MLDSA_REG_MLDSA_MSG_12 #define MLDSA_REG_MLDSA_MSG_12 (0xc8) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_13 (0x100300cc) +#ifndef MLDSA_REG_MLDSA_MSG_13 #define MLDSA_REG_MLDSA_MSG_13 (0xcc) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_14 (0x100300d0) +#ifndef MLDSA_REG_MLDSA_MSG_14 #define MLDSA_REG_MLDSA_MSG_14 (0xd0) +#endif #define CLP_MLDSA_REG_MLDSA_MSG_15 (0x100300d4) +#ifndef MLDSA_REG_MLDSA_MSG_15 #define MLDSA_REG_MLDSA_MSG_15 (0xd4) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_0 (0x100300d8) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_0 #define MLDSA_REG_MLDSA_VERIFY_RES_0 (0xd8) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_1 (0x100300dc) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_1 #define MLDSA_REG_MLDSA_VERIFY_RES_1 (0xdc) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_2 (0x100300e0) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_2 #define MLDSA_REG_MLDSA_VERIFY_RES_2 (0xe0) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_3 (0x100300e4) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_3 #define MLDSA_REG_MLDSA_VERIFY_RES_3 (0xe4) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_4 (0x100300e8) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_4 #define MLDSA_REG_MLDSA_VERIFY_RES_4 (0xe8) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_5 (0x100300ec) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_5 #define MLDSA_REG_MLDSA_VERIFY_RES_5 (0xec) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_6 (0x100300f0) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_6 #define MLDSA_REG_MLDSA_VERIFY_RES_6 (0xf0) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_7 (0x100300f4) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_7 #define MLDSA_REG_MLDSA_VERIFY_RES_7 (0xf4) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_8 (0x100300f8) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_8 #define MLDSA_REG_MLDSA_VERIFY_RES_8 (0xf8) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_9 (0x100300fc) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_9 #define MLDSA_REG_MLDSA_VERIFY_RES_9 (0xfc) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_10 (0x10030100) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_10 #define MLDSA_REG_MLDSA_VERIFY_RES_10 (0x100) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_11 (0x10030104) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_11 #define MLDSA_REG_MLDSA_VERIFY_RES_11 (0x104) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_12 (0x10030108) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_12 #define MLDSA_REG_MLDSA_VERIFY_RES_12 (0x108) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_13 (0x1003010c) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_13 #define MLDSA_REG_MLDSA_VERIFY_RES_13 (0x10c) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_14 (0x10030110) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_14 #define MLDSA_REG_MLDSA_VERIFY_RES_14 (0x110) +#endif #define CLP_MLDSA_REG_MLDSA_VERIFY_RES_15 (0x10030114) +#ifndef MLDSA_REG_MLDSA_VERIFY_RES_15 #define MLDSA_REG_MLDSA_VERIFY_RES_15 (0x114) +#endif #define CLP_MLDSA_REG_MLDSA_PUBKEY_BASE_ADDR (0x10031000) #define CLP_MLDSA_REG_MLDSA_PUBKEY_END_ADDR (0x10031a1f) #define CLP_MLDSA_REG_MLDSA_SIGNATURE_BASE_ADDR (0x10032000) @@ -4695,6 +8117,7 @@ #define CLP_MLDSA_REG_MLDSA_PRIVKEY_IN_BASE_ADDR (0x10036000) #define CLP_MLDSA_REG_MLDSA_PRIVKEY_IN_END_ADDR (0x1003731f) #define CLP_MLDSA_REG_MLDSA_KV_RD_SEED_CTRL (0x10038000) +#ifndef MLDSA_REG_MLDSA_KV_RD_SEED_CTRL #define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL (0x8000) #define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_EN_LOW (0) #define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_EN_MASK (0x1) @@ -4704,7 +8127,9 @@ #define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (0x40) #define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_RSVD_LOW (7) #define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_RSVD_MASK (0xffffff80) +#endif #define CLP_MLDSA_REG_MLDSA_KV_RD_SEED_STATUS (0x10038004) +#ifndef MLDSA_REG_MLDSA_KV_RD_SEED_STATUS #define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS (0x8004) #define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_READY_LOW (0) #define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_READY_MASK (0x1) @@ -4712,59 +8137,87 @@ #define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_VALID_MASK (0x2) #define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_ERROR_LOW (2) #define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_ERROR_MASK (0x3fc) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_START (0x10038100) #define CLP_MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x10038100) +#ifndef MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x8100) #define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x10038104) +#ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x8104) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x10038108) +#ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x8108) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x1003810c) +#ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x810c) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x10038110) +#ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x8110) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x10038114) +#ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x8114) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x10038118) +#ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x8118) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x1003811c) +#ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x811c) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x10038120) +#ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x8120) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (0x10038200) +#ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (0x8200) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x10038280) +#ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x8280) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (0x10038300) +#ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (0x8300) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x10038304) +#ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x8304) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_CSRNG_REG_BASE_ADDR (0x20002000) #define CLP_CSRNG_REG_INTERRUPT_STATE (0x20002000) +#ifndef CSRNG_REG_INTERRUPT_STATE #define CSRNG_REG_INTERRUPT_STATE (0x0) #define CSRNG_REG_INTERRUPT_STATE_CS_CMD_REQ_DONE_LOW (0) #define CSRNG_REG_INTERRUPT_STATE_CS_CMD_REQ_DONE_MASK (0x1) @@ -4774,7 +8227,9 @@ #define CSRNG_REG_INTERRUPT_STATE_CS_HW_INST_EXC_MASK (0x4) #define CSRNG_REG_INTERRUPT_STATE_CS_FATAL_ERR_LOW (3) #define CSRNG_REG_INTERRUPT_STATE_CS_FATAL_ERR_MASK (0x8) +#endif #define CLP_CSRNG_REG_INTERRUPT_ENABLE (0x20002004) +#ifndef CSRNG_REG_INTERRUPT_ENABLE #define CSRNG_REG_INTERRUPT_ENABLE (0x4) #define CSRNG_REG_INTERRUPT_ENABLE_CS_CMD_REQ_DONE_LOW (0) #define CSRNG_REG_INTERRUPT_ENABLE_CS_CMD_REQ_DONE_MASK (0x1) @@ -4784,7 +8239,9 @@ #define CSRNG_REG_INTERRUPT_ENABLE_CS_HW_INST_EXC_MASK (0x4) #define CSRNG_REG_INTERRUPT_ENABLE_CS_FATAL_ERR_LOW (3) #define CSRNG_REG_INTERRUPT_ENABLE_CS_FATAL_ERR_MASK (0x8) +#endif #define CLP_CSRNG_REG_INTERRUPT_TEST (0x20002008) +#ifndef CSRNG_REG_INTERRUPT_TEST #define CSRNG_REG_INTERRUPT_TEST (0x8) #define CSRNG_REG_INTERRUPT_TEST_CS_CMD_REQ_DONE_LOW (0) #define CSRNG_REG_INTERRUPT_TEST_CS_CMD_REQ_DONE_MASK (0x1) @@ -4794,17 +8251,23 @@ #define CSRNG_REG_INTERRUPT_TEST_CS_HW_INST_EXC_MASK (0x4) #define CSRNG_REG_INTERRUPT_TEST_CS_FATAL_ERR_LOW (3) #define CSRNG_REG_INTERRUPT_TEST_CS_FATAL_ERR_MASK (0x8) +#endif #define CLP_CSRNG_REG_ALERT_TEST (0x2000200c) +#ifndef CSRNG_REG_ALERT_TEST #define CSRNG_REG_ALERT_TEST (0xc) #define CSRNG_REG_ALERT_TEST_RECOV_ALERT_LOW (0) #define CSRNG_REG_ALERT_TEST_RECOV_ALERT_MASK (0x1) #define CSRNG_REG_ALERT_TEST_FATAL_ALERT_LOW (1) #define CSRNG_REG_ALERT_TEST_FATAL_ALERT_MASK (0x2) +#endif #define CLP_CSRNG_REG_REGWEN (0x20002010) +#ifndef CSRNG_REG_REGWEN #define CSRNG_REG_REGWEN (0x10) #define CSRNG_REG_REGWEN_REGWEN_LOW (0) #define CSRNG_REG_REGWEN_REGWEN_MASK (0x1) +#endif #define CLP_CSRNG_REG_CTRL (0x20002014) +#ifndef CSRNG_REG_CTRL #define CSRNG_REG_CTRL (0x14) #define CSRNG_REG_CTRL_ENABLE_LOW (0) #define CSRNG_REG_CTRL_ENABLE_MASK (0xf) @@ -4812,7 +8275,9 @@ #define CSRNG_REG_CTRL_SW_APP_ENABLE_MASK (0xf0) #define CSRNG_REG_CTRL_READ_INT_STATE_LOW (8) #define CSRNG_REG_CTRL_READ_INT_STATE_MASK (0xf00) +#endif #define CLP_CSRNG_REG_CMD_REQ (0x20002018) +#ifndef CSRNG_REG_CMD_REQ #define CSRNG_REG_CMD_REQ (0x18) #define CSRNG_REG_CMD_REQ_ACMD_LOW (0) #define CSRNG_REG_CMD_REQ_ACMD_MASK (0xf) @@ -4822,31 +8287,45 @@ #define CSRNG_REG_CMD_REQ_FLAG0_MASK (0xf00) #define CSRNG_REG_CMD_REQ_GLEN_LOW (12) #define CSRNG_REG_CMD_REQ_GLEN_MASK (0x1fff000) +#endif #define CLP_CSRNG_REG_SW_CMD_STS (0x2000201c) +#ifndef CSRNG_REG_SW_CMD_STS #define CSRNG_REG_SW_CMD_STS (0x1c) #define CSRNG_REG_SW_CMD_STS_CMD_RDY_LOW (0) #define CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK (0x1) #define CSRNG_REG_SW_CMD_STS_CMD_STS_LOW (1) #define CSRNG_REG_SW_CMD_STS_CMD_STS_MASK (0x2) +#endif #define CLP_CSRNG_REG_GENBITS_VLD (0x20002020) +#ifndef CSRNG_REG_GENBITS_VLD #define CSRNG_REG_GENBITS_VLD (0x20) #define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_LOW (0) #define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_MASK (0x1) #define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_LOW (1) #define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_MASK (0x2) +#endif #define CLP_CSRNG_REG_GENBITS (0x20002024) +#ifndef CSRNG_REG_GENBITS #define CSRNG_REG_GENBITS (0x24) +#endif #define CLP_CSRNG_REG_INT_STATE_NUM (0x20002028) +#ifndef CSRNG_REG_INT_STATE_NUM #define CSRNG_REG_INT_STATE_NUM (0x28) #define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_LOW (0) #define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_MASK (0xf) +#endif #define CLP_CSRNG_REG_INT_STATE_VAL (0x2000202c) +#ifndef CSRNG_REG_INT_STATE_VAL #define CSRNG_REG_INT_STATE_VAL (0x2c) +#endif #define CLP_CSRNG_REG_HW_EXC_STS (0x20002030) +#ifndef CSRNG_REG_HW_EXC_STS #define CSRNG_REG_HW_EXC_STS (0x30) #define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_LOW (0) #define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_MASK (0xffff) +#endif #define CLP_CSRNG_REG_RECOV_ALERT_STS (0x20002034) +#ifndef CSRNG_REG_RECOV_ALERT_STS #define CSRNG_REG_RECOV_ALERT_STS (0x34) #define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_LOW (0) #define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_MASK (0x1) @@ -4860,7 +8339,9 @@ #define CSRNG_REG_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_MASK (0x1000) #define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_LOW (13) #define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_MASK (0x2000) +#endif #define CLP_CSRNG_REG_ERR_CODE (0x20002038) +#ifndef CSRNG_REG_ERR_CODE #define CSRNG_REG_ERR_CODE (0x38) #define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_LOW (0) #define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_MASK (0x1) @@ -4914,16 +8395,22 @@ #define CSRNG_REG_ERR_CODE_FIFO_READ_ERR_MASK (0x20000000) #define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30) #define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_MASK (0x40000000) +#endif #define CLP_CSRNG_REG_ERR_CODE_TEST (0x2000203c) +#ifndef CSRNG_REG_ERR_CODE_TEST #define CSRNG_REG_ERR_CODE_TEST (0x3c) #define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0) #define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (0x1f) +#endif #define CLP_CSRNG_REG_MAIN_SM_STATE (0x20002040) +#ifndef CSRNG_REG_MAIN_SM_STATE #define CSRNG_REG_MAIN_SM_STATE (0x40) #define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) #define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (0xff) +#endif #define CLP_ENTROPY_SRC_REG_BASE_ADDR (0x20003000) #define CLP_ENTROPY_SRC_REG_INTERRUPT_STATE (0x20003000) +#ifndef ENTROPY_SRC_REG_INTERRUPT_STATE #define ENTROPY_SRC_REG_INTERRUPT_STATE (0x0) #define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_ENTROPY_VALID_LOW (0) #define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_ENTROPY_VALID_MASK (0x1) @@ -4933,7 +8420,9 @@ #define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_OBSERVE_FIFO_READY_MASK (0x4) #define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_FATAL_ERR_LOW (3) #define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_FATAL_ERR_MASK (0x8) +#endif #define CLP_ENTROPY_SRC_REG_INTERRUPT_ENABLE (0x20003004) +#ifndef ENTROPY_SRC_REG_INTERRUPT_ENABLE #define ENTROPY_SRC_REG_INTERRUPT_ENABLE (0x4) #define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_ENTROPY_VALID_LOW (0) #define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_ENTROPY_VALID_MASK (0x1) @@ -4943,7 +8432,9 @@ #define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_OBSERVE_FIFO_READY_MASK (0x4) #define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_FATAL_ERR_LOW (3) #define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_FATAL_ERR_MASK (0x8) +#endif #define CLP_ENTROPY_SRC_REG_INTERRUPT_TEST (0x20003008) +#ifndef ENTROPY_SRC_REG_INTERRUPT_TEST #define ENTROPY_SRC_REG_INTERRUPT_TEST (0x8) #define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_ENTROPY_VALID_LOW (0) #define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_ENTROPY_VALID_MASK (0x1) @@ -4953,25 +8444,35 @@ #define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_OBSERVE_FIFO_READY_MASK (0x4) #define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_FATAL_ERR_LOW (3) #define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_FATAL_ERR_MASK (0x8) +#endif #define CLP_ENTROPY_SRC_REG_ALERT_TEST (0x2000300c) +#ifndef ENTROPY_SRC_REG_ALERT_TEST #define ENTROPY_SRC_REG_ALERT_TEST (0xc) #define ENTROPY_SRC_REG_ALERT_TEST_RECOV_ALERT_LOW (0) #define ENTROPY_SRC_REG_ALERT_TEST_RECOV_ALERT_MASK (0x1) #define ENTROPY_SRC_REG_ALERT_TEST_FATAL_ALERT_LOW (1) #define ENTROPY_SRC_REG_ALERT_TEST_FATAL_ALERT_MASK (0x2) +#endif #define CLP_ENTROPY_SRC_REG_ME_REGWEN (0x20003010) +#ifndef ENTROPY_SRC_REG_ME_REGWEN #define ENTROPY_SRC_REG_ME_REGWEN (0x10) #define ENTROPY_SRC_REG_ME_REGWEN_ME_REGWEN_LOW (0) #define ENTROPY_SRC_REG_ME_REGWEN_ME_REGWEN_MASK (0x1) +#endif #define CLP_ENTROPY_SRC_REG_SW_REGUPD (0x20003014) +#ifndef ENTROPY_SRC_REG_SW_REGUPD #define ENTROPY_SRC_REG_SW_REGUPD (0x14) #define ENTROPY_SRC_REG_SW_REGUPD_SW_REGUPD_LOW (0) #define ENTROPY_SRC_REG_SW_REGUPD_SW_REGUPD_MASK (0x1) +#endif #define CLP_ENTROPY_SRC_REG_REGWEN (0x20003018) +#ifndef ENTROPY_SRC_REG_REGWEN #define ENTROPY_SRC_REG_REGWEN (0x18) #define ENTROPY_SRC_REG_REGWEN_REGWEN_LOW (0) #define ENTROPY_SRC_REG_REGWEN_REGWEN_MASK (0x1) +#endif #define CLP_ENTROPY_SRC_REG_REV (0x2000301c) +#ifndef ENTROPY_SRC_REG_REV #define ENTROPY_SRC_REG_REV (0x1c) #define ENTROPY_SRC_REG_REV_ABI_REVISION_LOW (0) #define ENTROPY_SRC_REG_REV_ABI_REVISION_MASK (0xff) @@ -4979,11 +8480,15 @@ #define ENTROPY_SRC_REG_REV_HW_REVISION_MASK (0xff00) #define ENTROPY_SRC_REG_REV_CHIP_TYPE_LOW (16) #define ENTROPY_SRC_REG_REV_CHIP_TYPE_MASK (0xff0000) +#endif #define CLP_ENTROPY_SRC_REG_MODULE_ENABLE (0x20003020) +#ifndef ENTROPY_SRC_REG_MODULE_ENABLE #define ENTROPY_SRC_REG_MODULE_ENABLE (0x20) #define ENTROPY_SRC_REG_MODULE_ENABLE_MODULE_ENABLE_LOW (0) #define ENTROPY_SRC_REG_MODULE_ENABLE_MODULE_ENABLE_MASK (0xf) +#endif #define CLP_ENTROPY_SRC_REG_CONF (0x20003024) +#ifndef ENTROPY_SRC_REG_CONF #define ENTROPY_SRC_REG_CONF (0x24) #define ENTROPY_SRC_REG_CONF_FIPS_ENABLE_LOW (0) #define ENTROPY_SRC_REG_CONF_FIPS_ENABLE_MASK (0xf) @@ -4995,157 +8500,223 @@ #define ENTROPY_SRC_REG_CONF_RNG_BIT_ENABLE_MASK (0xf00000) #define ENTROPY_SRC_REG_CONF_RNG_BIT_SEL_LOW (24) #define ENTROPY_SRC_REG_CONF_RNG_BIT_SEL_MASK (0x3000000) +#endif #define CLP_ENTROPY_SRC_REG_ENTROPY_CONTROL (0x20003028) +#ifndef ENTROPY_SRC_REG_ENTROPY_CONTROL #define ENTROPY_SRC_REG_ENTROPY_CONTROL (0x28) #define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_ROUTE_LOW (0) #define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_ROUTE_MASK (0xf) #define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_TYPE_LOW (4) #define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_TYPE_MASK (0xf0) +#endif #define CLP_ENTROPY_SRC_REG_ENTROPY_DATA (0x2000302c) +#ifndef ENTROPY_SRC_REG_ENTROPY_DATA #define ENTROPY_SRC_REG_ENTROPY_DATA (0x2c) +#endif #define CLP_ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS (0x20003030) +#ifndef ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS #define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS (0x30) #define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_FIPS_WINDOW_LOW (0) #define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_FIPS_WINDOW_MASK (0xffff) #define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_LOW (16) #define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_REPCNT_THRESHOLDS (0x20003034) +#ifndef ENTROPY_SRC_REG_REPCNT_THRESHOLDS #define ENTROPY_SRC_REG_REPCNT_THRESHOLDS (0x34) #define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_REPCNTS_THRESHOLDS (0x20003038) +#ifndef ENTROPY_SRC_REG_REPCNTS_THRESHOLDS #define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS (0x38) #define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS (0x2000303c) +#ifndef ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS #define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS (0x3c) #define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS (0x20003040) +#ifndef ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS #define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS (0x40) #define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_BUCKET_THRESHOLDS (0x20003044) +#ifndef ENTROPY_SRC_REG_BUCKET_THRESHOLDS #define ENTROPY_SRC_REG_BUCKET_THRESHOLDS (0x44) #define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS (0x20003048) +#ifndef ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS #define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS (0x48) #define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS (0x2000304c) +#ifndef ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS #define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS (0x4c) #define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS (0x20003050) +#ifndef ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS #define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS (0x50) #define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS (0x20003054) +#ifndef ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS #define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS (0x54) #define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_FIPS_THRESH_LOW (0) #define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_FIPS_THRESH_MASK (0xffff) #define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) #define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS (0x20003058) +#ifndef ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS #define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS (0x58) #define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS (0x2000305c) +#ifndef ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS #define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS (0x5c) #define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS (0x20003060) +#ifndef ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS #define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS (0x60) #define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS (0x20003064) +#ifndef ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS #define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS (0x64) #define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS (0x20003068) +#ifndef ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS #define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS (0x68) #define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS (0x2000306c) +#ifndef ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS #define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS (0x6c) #define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS (0x20003070) +#ifndef ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS #define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS (0x70) #define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS (0x20003074) +#ifndef ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS #define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS (0x74) #define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS (0x20003078) +#ifndef ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS #define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS (0x78) #define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) #define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_MASK (0xffff) #define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) #define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_REPCNT_TOTAL_FAILS (0x2000307c) +#ifndef ENTROPY_SRC_REG_REPCNT_TOTAL_FAILS #define ENTROPY_SRC_REG_REPCNT_TOTAL_FAILS (0x7c) +#endif #define CLP_ENTROPY_SRC_REG_REPCNTS_TOTAL_FAILS (0x20003080) +#ifndef ENTROPY_SRC_REG_REPCNTS_TOTAL_FAILS #define ENTROPY_SRC_REG_REPCNTS_TOTAL_FAILS (0x80) +#endif #define CLP_ENTROPY_SRC_REG_ADAPTP_HI_TOTAL_FAILS (0x20003084) +#ifndef ENTROPY_SRC_REG_ADAPTP_HI_TOTAL_FAILS #define ENTROPY_SRC_REG_ADAPTP_HI_TOTAL_FAILS (0x84) +#endif #define CLP_ENTROPY_SRC_REG_ADAPTP_LO_TOTAL_FAILS (0x20003088) +#ifndef ENTROPY_SRC_REG_ADAPTP_LO_TOTAL_FAILS #define ENTROPY_SRC_REG_ADAPTP_LO_TOTAL_FAILS (0x88) +#endif #define CLP_ENTROPY_SRC_REG_BUCKET_TOTAL_FAILS (0x2000308c) +#ifndef ENTROPY_SRC_REG_BUCKET_TOTAL_FAILS #define ENTROPY_SRC_REG_BUCKET_TOTAL_FAILS (0x8c) +#endif #define CLP_ENTROPY_SRC_REG_MARKOV_HI_TOTAL_FAILS (0x20003090) +#ifndef ENTROPY_SRC_REG_MARKOV_HI_TOTAL_FAILS #define ENTROPY_SRC_REG_MARKOV_HI_TOTAL_FAILS (0x90) +#endif #define CLP_ENTROPY_SRC_REG_MARKOV_LO_TOTAL_FAILS (0x20003094) +#ifndef ENTROPY_SRC_REG_MARKOV_LO_TOTAL_FAILS #define ENTROPY_SRC_REG_MARKOV_LO_TOTAL_FAILS (0x94) +#endif #define CLP_ENTROPY_SRC_REG_EXTHT_HI_TOTAL_FAILS (0x20003098) +#ifndef ENTROPY_SRC_REG_EXTHT_HI_TOTAL_FAILS #define ENTROPY_SRC_REG_EXTHT_HI_TOTAL_FAILS (0x98) +#endif #define CLP_ENTROPY_SRC_REG_EXTHT_LO_TOTAL_FAILS (0x2000309c) +#ifndef ENTROPY_SRC_REG_EXTHT_LO_TOTAL_FAILS #define ENTROPY_SRC_REG_EXTHT_LO_TOTAL_FAILS (0x9c) +#endif #define CLP_ENTROPY_SRC_REG_ALERT_THRESHOLD (0x200030a0) +#ifndef ENTROPY_SRC_REG_ALERT_THRESHOLD #define ENTROPY_SRC_REG_ALERT_THRESHOLD (0xa0) #define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_LOW (0) #define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_MASK (0xffff) #define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_LOW (16) #define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_MASK (0xffff0000) +#endif #define CLP_ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS (0x200030a4) +#ifndef ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS #define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS (0xa4) #define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_LOW (0) #define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_MASK (0xffff) +#endif #define CLP_ENTROPY_SRC_REG_ALERT_FAIL_COUNTS (0x200030a8) +#ifndef ENTROPY_SRC_REG_ALERT_FAIL_COUNTS #define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS (0xa8) #define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_LOW (4) #define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_MASK (0xf0) @@ -5161,43 +8732,63 @@ #define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_MASK (0xf000000) #define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_LOW (28) #define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_MASK (0xf0000000) +#endif #define CLP_ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS (0x200030ac) +#ifndef ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS #define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS (0xac) #define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_LOW (0) #define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_MASK (0xf) #define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_LOW (4) #define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_MASK (0xf0) +#endif #define CLP_ENTROPY_SRC_REG_FW_OV_CONTROL (0x200030b0) +#ifndef ENTROPY_SRC_REG_FW_OV_CONTROL #define ENTROPY_SRC_REG_FW_OV_CONTROL (0xb0) #define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_MODE_LOW (0) #define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_MODE_MASK (0xf) #define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_LOW (4) #define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK (0xf0) +#endif #define CLP_ENTROPY_SRC_REG_FW_OV_SHA3_START (0x200030b4) +#ifndef ENTROPY_SRC_REG_FW_OV_SHA3_START #define ENTROPY_SRC_REG_FW_OV_SHA3_START (0xb4) #define ENTROPY_SRC_REG_FW_OV_SHA3_START_FW_OV_INSERT_START_LOW (0) #define ENTROPY_SRC_REG_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK (0xf) +#endif #define CLP_ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL (0x200030b8) +#ifndef ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL #define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL (0xb8) #define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_LOW (0) #define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_MASK (0x1) +#endif #define CLP_ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW (0x200030bc) +#ifndef ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW #define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW (0xbc) #define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_LOW (0) #define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_MASK (0x1) +#endif #define CLP_ENTROPY_SRC_REG_FW_OV_RD_DATA (0x200030c0) +#ifndef ENTROPY_SRC_REG_FW_OV_RD_DATA #define ENTROPY_SRC_REG_FW_OV_RD_DATA (0xc0) +#endif #define CLP_ENTROPY_SRC_REG_FW_OV_WR_DATA (0x200030c4) +#ifndef ENTROPY_SRC_REG_FW_OV_WR_DATA #define ENTROPY_SRC_REG_FW_OV_WR_DATA (0xc4) +#endif #define CLP_ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH (0x200030c8) +#ifndef ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH #define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH (0xc8) #define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_LOW (0) #define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK (0x7f) +#endif #define CLP_ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH (0x200030cc) +#ifndef ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH #define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH (0xcc) #define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_LOW (0) #define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_MASK (0x7f) +#endif #define CLP_ENTROPY_SRC_REG_DEBUG_STATUS (0x200030d0) +#ifndef ENTROPY_SRC_REG_DEBUG_STATUS #define ENTROPY_SRC_REG_DEBUG_STATUS (0xd0) #define ENTROPY_SRC_REG_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_LOW (0) #define ENTROPY_SRC_REG_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_MASK (0x7) @@ -5215,7 +8806,9 @@ #define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_IDLE_MASK (0x10000) #define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_BOOT_DONE_LOW (17) #define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_BOOT_DONE_MASK (0x20000) +#endif #define CLP_ENTROPY_SRC_REG_RECOV_ALERT_STS (0x200030d4) +#ifndef ENTROPY_SRC_REG_RECOV_ALERT_STS #define ENTROPY_SRC_REG_RECOV_ALERT_STS (0xd4) #define ENTROPY_SRC_REG_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_LOW (0) #define ENTROPY_SRC_REG_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_MASK (0x1) @@ -5247,7 +8840,9 @@ #define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_MASK (0x8000) #define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_LOW (16) #define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_MASK (0x10000) +#endif #define CLP_ENTROPY_SRC_REG_ERR_CODE (0x200030d8) +#ifndef ENTROPY_SRC_REG_ERR_CODE #define ENTROPY_SRC_REG_ERR_CODE (0xd8) #define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESRNG_ERR_LOW (0) #define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESRNG_ERR_MASK (0x1) @@ -5271,34 +8866,54 @@ #define ENTROPY_SRC_REG_ERR_CODE_FIFO_READ_ERR_MASK (0x20000000) #define ENTROPY_SRC_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30) #define ENTROPY_SRC_REG_ERR_CODE_FIFO_STATE_ERR_MASK (0x40000000) +#endif #define CLP_ENTROPY_SRC_REG_ERR_CODE_TEST (0x200030dc) +#ifndef ENTROPY_SRC_REG_ERR_CODE_TEST #define ENTROPY_SRC_REG_ERR_CODE_TEST (0xdc) #define ENTROPY_SRC_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0) #define ENTROPY_SRC_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (0x1f) +#endif #define CLP_ENTROPY_SRC_REG_MAIN_SM_STATE (0x200030e0) +#ifndef ENTROPY_SRC_REG_MAIN_SM_STATE #define ENTROPY_SRC_REG_MAIN_SM_STATE (0xe0) #define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) #define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (0x1ff) +#endif #define CLP_MBOX_CSR_BASE_ADDR (0x30020000) #define CLP_MBOX_CSR_MBOX_LOCK (0x30020000) +#ifndef MBOX_CSR_MBOX_LOCK #define MBOX_CSR_MBOX_LOCK (0x0) #define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) #define MBOX_CSR_MBOX_LOCK_LOCK_MASK (0x1) +#endif #define CLP_MBOX_CSR_MBOX_USER (0x30020004) +#ifndef MBOX_CSR_MBOX_USER #define MBOX_CSR_MBOX_USER (0x4) +#endif #define CLP_MBOX_CSR_MBOX_CMD (0x30020008) +#ifndef MBOX_CSR_MBOX_CMD #define MBOX_CSR_MBOX_CMD (0x8) +#endif #define CLP_MBOX_CSR_MBOX_DLEN (0x3002000c) +#ifndef MBOX_CSR_MBOX_DLEN #define MBOX_CSR_MBOX_DLEN (0xc) +#endif #define CLP_MBOX_CSR_MBOX_DATAIN (0x30020010) +#ifndef MBOX_CSR_MBOX_DATAIN #define MBOX_CSR_MBOX_DATAIN (0x10) +#endif #define CLP_MBOX_CSR_MBOX_DATAOUT (0x30020014) +#ifndef MBOX_CSR_MBOX_DATAOUT #define MBOX_CSR_MBOX_DATAOUT (0x14) +#endif #define CLP_MBOX_CSR_MBOX_EXECUTE (0x30020018) +#ifndef MBOX_CSR_MBOX_EXECUTE #define MBOX_CSR_MBOX_EXECUTE (0x18) #define MBOX_CSR_MBOX_EXECUTE_EXECUTE_LOW (0) #define MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK (0x1) +#endif #define CLP_MBOX_CSR_MBOX_STATUS (0x3002001c) +#ifndef MBOX_CSR_MBOX_STATUS #define MBOX_CSR_MBOX_STATUS (0x1c) #define MBOX_CSR_MBOX_STATUS_STATUS_LOW (0) #define MBOX_CSR_MBOX_STATUS_STATUS_MASK (0xf) @@ -5312,87 +8927,145 @@ #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (0x200) #define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) #define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (0x3fffc00) +#endif #define CLP_MBOX_CSR_MBOX_UNLOCK (0x30020020) +#ifndef MBOX_CSR_MBOX_UNLOCK #define MBOX_CSR_MBOX_UNLOCK (0x20) #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (0x1) +#endif #define CLP_MBOX_CSR_TAP_MODE (0x30020024) +#ifndef MBOX_CSR_TAP_MODE #define MBOX_CSR_TAP_MODE (0x24) #define MBOX_CSR_TAP_MODE_ENABLED_LOW (0) #define MBOX_CSR_TAP_MODE_ENABLED_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_BASE_ADDR (0x30021000) #define CLP_SHA512_ACC_CSR_LOCK (0x30021000) +#ifndef SHA512_ACC_CSR_LOCK #define SHA512_ACC_CSR_LOCK (0x0) #define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) #define SHA512_ACC_CSR_LOCK_LOCK_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_USER (0x30021004) +#ifndef SHA512_ACC_CSR_USER #define SHA512_ACC_CSR_USER (0x4) +#endif #define CLP_SHA512_ACC_CSR_MODE (0x30021008) +#ifndef SHA512_ACC_CSR_MODE #define SHA512_ACC_CSR_MODE (0x8) #define SHA512_ACC_CSR_MODE_MODE_LOW (0) #define SHA512_ACC_CSR_MODE_MODE_MASK (0x3) #define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_LOW (2) #define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_MASK (0x4) +#endif #define CLP_SHA512_ACC_CSR_START_ADDRESS (0x3002100c) +#ifndef SHA512_ACC_CSR_START_ADDRESS #define SHA512_ACC_CSR_START_ADDRESS (0xc) +#endif #define CLP_SHA512_ACC_CSR_DLEN (0x30021010) +#ifndef SHA512_ACC_CSR_DLEN #define SHA512_ACC_CSR_DLEN (0x10) +#endif #define CLP_SHA512_ACC_CSR_DATAIN (0x30021014) +#ifndef SHA512_ACC_CSR_DATAIN #define SHA512_ACC_CSR_DATAIN (0x14) +#endif #define CLP_SHA512_ACC_CSR_EXECUTE (0x30021018) +#ifndef SHA512_ACC_CSR_EXECUTE #define SHA512_ACC_CSR_EXECUTE (0x18) #define SHA512_ACC_CSR_EXECUTE_EXECUTE_LOW (0) #define SHA512_ACC_CSR_EXECUTE_EXECUTE_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_STATUS (0x3002101c) +#ifndef SHA512_ACC_CSR_STATUS #define SHA512_ACC_CSR_STATUS (0x1c) #define SHA512_ACC_CSR_STATUS_VALID_LOW (0) #define SHA512_ACC_CSR_STATUS_VALID_MASK (0x1) #define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW (1) #define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK (0x2) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_0 (0x30021020) +#ifndef SHA512_ACC_CSR_DIGEST_0 #define SHA512_ACC_CSR_DIGEST_0 (0x20) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_1 (0x30021024) +#ifndef SHA512_ACC_CSR_DIGEST_1 #define SHA512_ACC_CSR_DIGEST_1 (0x24) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_2 (0x30021028) +#ifndef SHA512_ACC_CSR_DIGEST_2 #define SHA512_ACC_CSR_DIGEST_2 (0x28) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_3 (0x3002102c) +#ifndef SHA512_ACC_CSR_DIGEST_3 #define SHA512_ACC_CSR_DIGEST_3 (0x2c) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_4 (0x30021030) +#ifndef SHA512_ACC_CSR_DIGEST_4 #define SHA512_ACC_CSR_DIGEST_4 (0x30) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_5 (0x30021034) +#ifndef SHA512_ACC_CSR_DIGEST_5 #define SHA512_ACC_CSR_DIGEST_5 (0x34) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_6 (0x30021038) +#ifndef SHA512_ACC_CSR_DIGEST_6 #define SHA512_ACC_CSR_DIGEST_6 (0x38) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_7 (0x3002103c) +#ifndef SHA512_ACC_CSR_DIGEST_7 #define SHA512_ACC_CSR_DIGEST_7 (0x3c) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_8 (0x30021040) +#ifndef SHA512_ACC_CSR_DIGEST_8 #define SHA512_ACC_CSR_DIGEST_8 (0x40) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_9 (0x30021044) +#ifndef SHA512_ACC_CSR_DIGEST_9 #define SHA512_ACC_CSR_DIGEST_9 (0x44) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_10 (0x30021048) +#ifndef SHA512_ACC_CSR_DIGEST_10 #define SHA512_ACC_CSR_DIGEST_10 (0x48) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_11 (0x3002104c) +#ifndef SHA512_ACC_CSR_DIGEST_11 #define SHA512_ACC_CSR_DIGEST_11 (0x4c) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_12 (0x30021050) +#ifndef SHA512_ACC_CSR_DIGEST_12 #define SHA512_ACC_CSR_DIGEST_12 (0x50) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_13 (0x30021054) +#ifndef SHA512_ACC_CSR_DIGEST_13 #define SHA512_ACC_CSR_DIGEST_13 (0x54) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_14 (0x30021058) +#ifndef SHA512_ACC_CSR_DIGEST_14 #define SHA512_ACC_CSR_DIGEST_14 (0x58) +#endif #define CLP_SHA512_ACC_CSR_DIGEST_15 (0x3002105c) +#ifndef SHA512_ACC_CSR_DIGEST_15 #define SHA512_ACC_CSR_DIGEST_15 (0x5c) +#endif #define CLP_SHA512_ACC_CSR_CONTROL (0x30021060) +#ifndef SHA512_ACC_CSR_CONTROL #define SHA512_ACC_CSR_CONTROL (0x60) #define SHA512_ACC_CSR_CONTROL_ZEROIZE_LOW (0) #define SHA512_ACC_CSR_CONTROL_ZEROIZE_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_START (0x30021800) #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x30021800) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x30021804) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (0x1) @@ -5402,19 +9075,27 @@ #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (0x4) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (0x8) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x30021808) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x3002180c) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x30021810) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x30021814) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (0x1) @@ -5424,11 +9105,15 @@ #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (0x4) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (0x8) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x30021818) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x3002181c) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (0x1) @@ -5438,50 +9123,78 @@ #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (0x4) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (0x8) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x30021820) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x30021900) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (0x900) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x30021904) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (0x904) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x30021908) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (0x908) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x3002190c) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (0x90c) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x30021980) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (0x980) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0x30021a00) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (0xa00) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0x30021a04) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (0xa04) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0x30021a08) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (0xa08) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0x30021a0c) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (0xa0c) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0x30021a10) +#ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (0xa10) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_BASE_ADDR (0x30022000) #define CLP_AXI_DMA_REG_ID (0x30022000) +#ifndef AXI_DMA_REG_ID #define AXI_DMA_REG_ID (0x0) +#endif #define CLP_AXI_DMA_REG_CAP (0x30022004) +#ifndef AXI_DMA_REG_CAP #define AXI_DMA_REG_CAP (0x4) #define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW (0) #define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK (0xfff) #define AXI_DMA_REG_CAP_RSVD_LOW (12) #define AXI_DMA_REG_CAP_RSVD_MASK (0xfffff000) +#endif #define CLP_AXI_DMA_REG_CTRL (0x30022008) +#ifndef AXI_DMA_REG_CTRL #define AXI_DMA_REG_CTRL (0x8) #define AXI_DMA_REG_CTRL_GO_LOW (0) #define AXI_DMA_REG_CTRL_GO_MASK (0x1) @@ -5505,7 +9218,9 @@ #define AXI_DMA_REG_CTRL_WR_FIXED_MASK (0x10000000) #define AXI_DMA_REG_CTRL_RSVD4_LOW (29) #define AXI_DMA_REG_CTRL_RSVD4_MASK (0xe0000000) +#endif #define CLP_AXI_DMA_REG_STATUS0 (0x3002200c) +#ifndef AXI_DMA_REG_STATUS0 #define AXI_DMA_REG_STATUS0 (0xc) #define AXI_DMA_REG_STATUS0_BUSY_LOW (0) #define AXI_DMA_REG_STATUS0_BUSY_MASK (0x1) @@ -5523,36 +9238,58 @@ #define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_MASK (0x80000) #define AXI_DMA_REG_STATUS0_RSVD1_LOW (20) #define AXI_DMA_REG_STATUS0_RSVD1_MASK (0xfff00000) +#endif #define CLP_AXI_DMA_REG_STATUS1 (0x30022010) +#ifndef AXI_DMA_REG_STATUS1 #define AXI_DMA_REG_STATUS1 (0x10) +#endif #define CLP_AXI_DMA_REG_SRC_ADDR_L (0x30022014) +#ifndef AXI_DMA_REG_SRC_ADDR_L #define AXI_DMA_REG_SRC_ADDR_L (0x14) +#endif #define CLP_AXI_DMA_REG_SRC_ADDR_H (0x30022018) +#ifndef AXI_DMA_REG_SRC_ADDR_H #define AXI_DMA_REG_SRC_ADDR_H (0x18) +#endif #define CLP_AXI_DMA_REG_DST_ADDR_L (0x3002201c) +#ifndef AXI_DMA_REG_DST_ADDR_L #define AXI_DMA_REG_DST_ADDR_L (0x1c) +#endif #define CLP_AXI_DMA_REG_DST_ADDR_H (0x30022020) +#ifndef AXI_DMA_REG_DST_ADDR_H #define AXI_DMA_REG_DST_ADDR_H (0x20) +#endif #define CLP_AXI_DMA_REG_BYTE_COUNT (0x30022024) +#ifndef AXI_DMA_REG_BYTE_COUNT #define AXI_DMA_REG_BYTE_COUNT (0x24) +#endif #define CLP_AXI_DMA_REG_BLOCK_SIZE (0x30022028) +#ifndef AXI_DMA_REG_BLOCK_SIZE #define AXI_DMA_REG_BLOCK_SIZE (0x28) #define AXI_DMA_REG_BLOCK_SIZE_SIZE_LOW (0) #define AXI_DMA_REG_BLOCK_SIZE_SIZE_MASK (0xfff) #define AXI_DMA_REG_BLOCK_SIZE_RSVD_LOW (12) #define AXI_DMA_REG_BLOCK_SIZE_RSVD_MASK (0xfffff000) +#endif #define CLP_AXI_DMA_REG_WRITE_DATA (0x3002202c) +#ifndef AXI_DMA_REG_WRITE_DATA #define AXI_DMA_REG_WRITE_DATA (0x2c) +#endif #define CLP_AXI_DMA_REG_READ_DATA (0x30022030) +#ifndef AXI_DMA_REG_READ_DATA #define AXI_DMA_REG_READ_DATA (0x30) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_START (0x30022800) #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x30022800) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x30022804) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK (0x1) @@ -5568,7 +9305,9 @@ #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK (0x20) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_LOW (6) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK (0x40) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x30022808) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK (0x1) @@ -5580,15 +9319,21 @@ #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK (0x8) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_LOW (4) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK (0x10) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x3002280c) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x30022810) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x30022814) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK (0x1) @@ -5604,7 +9349,9 @@ #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK (0x20) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_LOW (6) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK (0x40) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x30022818) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK (0x1) @@ -5616,7 +9363,9 @@ #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK (0x8) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_LOW (4) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK (0x10) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x3002281c) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_MASK (0x1) @@ -5632,7 +9381,9 @@ #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_MASK (0x20) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_LOW (6) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_MASK (0x40) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x30022820) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_MASK (0x1) @@ -5644,80 +9395,130 @@ #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_MASK (0x8) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_LOW (4) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_MASK (0x10) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (0x30022900) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (0x900) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (0x30022904) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (0x904) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (0x30022908) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (0x908) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (0x3002290c) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (0x90c) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (0x30022910) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (0x910) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (0x30022914) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (0x914) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (0x30022918) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (0x918) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (0x30022980) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (0x980) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (0x30022984) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (0x984) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (0x30022988) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (0x988) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (0x3002298c) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (0x98c) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (0x30022990) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (0x990) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (0x30022a00) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (0xa00) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (0x30022a04) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (0xa04) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (0x30022a08) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (0xa08) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (0x30022a0c) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (0xa0c) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (0x30022a10) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (0xa10) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (0x30022a14) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (0xa14) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (0x30022a18) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (0xa18) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (0x30022a1c) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (0xa1c) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (0x30022a20) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (0xa20) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (0x30022a24) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (0xa24) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (0x30022a28) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (0xa28) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (0x30022a2c) +#ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (0xa2c) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) #define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_BASE_ADDR (0x30030000) #define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (0x30030000) +#ifndef SOC_IFC_REG_CPTRA_HW_ERROR_FATAL #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (0x0) #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW (0) #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK (0x1) @@ -5729,7 +9530,9 @@ #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (0x8) #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4) #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (0xfffffff0) +#endif #define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (0x30030004) +#ifndef SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL #define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (0x4) #define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK (0x1) @@ -5739,33 +9542,61 @@ #define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (0x4) #define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3) #define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (0xfffffff8) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (0x30030008) +#ifndef SOC_IFC_REG_CPTRA_FW_ERROR_FATAL #define SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (0x8) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL (0x3003000c) +#ifndef SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL #define SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL (0xc) +#endif #define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_ENC (0x30030010) +#ifndef SOC_IFC_REG_CPTRA_HW_ERROR_ENC #define SOC_IFC_REG_CPTRA_HW_ERROR_ENC (0x10) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_ENC (0x30030014) +#ifndef SOC_IFC_REG_CPTRA_FW_ERROR_ENC #define SOC_IFC_REG_CPTRA_FW_ERROR_ENC (0x14) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (0x30030018) +#ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 #define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (0x18) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (0x3003001c) +#ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 #define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (0x1c) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (0x30030020) +#ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 #define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (0x20) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (0x30030024) +#ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 #define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (0x24) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (0x30030028) +#ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 #define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (0x28) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (0x3003002c) +#ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 #define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (0x2c) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (0x30030030) +#ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 #define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (0x30) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (0x30030034) +#ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 #define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (0x34) +#endif #define CLP_SOC_IFC_REG_CPTRA_BOOT_STATUS (0x30030038) +#ifndef SOC_IFC_REG_CPTRA_BOOT_STATUS #define SOC_IFC_REG_CPTRA_BOOT_STATUS (0x38) +#endif #define CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS (0x3003003c) +#ifndef SOC_IFC_REG_CPTRA_FLOW_STATUS #define SOC_IFC_REG_CPTRA_FLOW_STATUS (0x3c) #define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_LOW (0) #define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK (0xffffff) @@ -5781,13 +9612,17 @@ #define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK (0x40000000) #define SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_LOW (31) #define SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK (0x80000000) +#endif #define CLP_SOC_IFC_REG_CPTRA_RESET_REASON (0x30030040) +#ifndef SOC_IFC_REG_CPTRA_RESET_REASON #define SOC_IFC_REG_CPTRA_RESET_REASON (0x40) #define SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_LOW (0) #define SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK (0x1) #define SOC_IFC_REG_CPTRA_RESET_REASON_WARM_RESET_LOW (1) #define SOC_IFC_REG_CPTRA_RESET_REASON_WARM_RESET_MASK (0x2) +#endif #define CLP_SOC_IFC_REG_CPTRA_SECURITY_STATE (0x30030044) +#ifndef SOC_IFC_REG_CPTRA_SECURITY_STATE #define SOC_IFC_REG_CPTRA_SECURITY_STATE (0x44) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_LOW (0) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_MASK (0x3) @@ -5797,111 +9632,189 @@ #define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (0x8) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) #define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (0xfffffff0) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x30030048) +#ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 #define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x48) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x3003004c) +#ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 #define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x4c) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x30030050) +#ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 #define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x50) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x30030054) +#ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 #define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x54) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x30030058) +#ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 #define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x58) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x3003005c) +#ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x5c) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x30030060) +#ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x60) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x30030064) +#ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x64) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x30030068) +#ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x68) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x3003006c) +#ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x6c) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (0x30030070) +#ifndef SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER #define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (0x70) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (0x30030074) +#ifndef SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK #define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (0x74) #define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x30030078) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_0 #define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x78) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (0x3003007c) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_1 #define SOC_IFC_REG_CPTRA_TRNG_DATA_1 (0x7c) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_2 (0x30030080) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_2 #define SOC_IFC_REG_CPTRA_TRNG_DATA_2 (0x80) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_3 (0x30030084) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_3 #define SOC_IFC_REG_CPTRA_TRNG_DATA_3 (0x84) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_4 (0x30030088) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_4 #define SOC_IFC_REG_CPTRA_TRNG_DATA_4 (0x88) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_5 (0x3003008c) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_5 #define SOC_IFC_REG_CPTRA_TRNG_DATA_5 (0x8c) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_6 (0x30030090) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_6 #define SOC_IFC_REG_CPTRA_TRNG_DATA_6 (0x90) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_7 (0x30030094) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_7 #define SOC_IFC_REG_CPTRA_TRNG_DATA_7 (0x94) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_8 (0x30030098) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_8 #define SOC_IFC_REG_CPTRA_TRNG_DATA_8 (0x98) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_9 (0x3003009c) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_9 #define SOC_IFC_REG_CPTRA_TRNG_DATA_9 (0x9c) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_10 (0x300300a0) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_10 #define SOC_IFC_REG_CPTRA_TRNG_DATA_10 (0xa0) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_11 (0x300300a4) +#ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_11 #define SOC_IFC_REG_CPTRA_TRNG_DATA_11 (0xa4) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_CTRL (0x300300a8) +#ifndef SOC_IFC_REG_CPTRA_TRNG_CTRL #define SOC_IFC_REG_CPTRA_TRNG_CTRL (0xa8) #define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_LOW (0) #define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS (0x300300ac) +#ifndef SOC_IFC_REG_CPTRA_TRNG_STATUS #define SOC_IFC_REG_CPTRA_TRNG_STATUS (0xac) #define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW (0) #define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK (0x1) #define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW (1) #define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK (0x2) +#endif #define CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE (0x300300b0) +#ifndef SOC_IFC_REG_CPTRA_FUSE_WR_DONE #define SOC_IFC_REG_CPTRA_FUSE_WR_DONE (0xb0) #define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_LOW (0) #define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_TIMER_CONFIG (0x300300b4) +#ifndef SOC_IFC_REG_CPTRA_TIMER_CONFIG #define SOC_IFC_REG_CPTRA_TIMER_CONFIG (0xb4) +#endif #define CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO (0x300300b8) +#ifndef SOC_IFC_REG_CPTRA_BOOTFSM_GO #define SOC_IFC_REG_CPTRA_BOOTFSM_GO (0xb8) #define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_LOW (0) #define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG (0x300300bc) +#ifndef SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG #define SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG (0xbc) +#endif #define CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN (0x300300c0) +#ifndef SOC_IFC_REG_CPTRA_CLK_GATING_EN #define SOC_IFC_REG_CPTRA_CLK_GATING_EN (0xc0) #define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW (0) #define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0 (0x300300c4) +#ifndef SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0 #define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0 (0xc4) +#endif #define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1 (0x300300c8) +#ifndef SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1 #define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1 (0xc8) +#endif #define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (0x300300cc) +#ifndef SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 #define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (0xcc) +#endif #define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (0x300300d0) +#ifndef SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 #define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (0xd0) +#endif #define CLP_SOC_IFC_REG_CPTRA_HW_REV_ID (0x300300d4) +#ifndef SOC_IFC_REG_CPTRA_HW_REV_ID #define SOC_IFC_REG_CPTRA_HW_REV_ID (0xd4) #define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW (0) #define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK (0xffff) #define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW (16) #define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK (0xffff0000) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_0 (0x300300d8) +#ifndef SOC_IFC_REG_CPTRA_FW_REV_ID_0 #define SOC_IFC_REG_CPTRA_FW_REV_ID_0 (0xd8) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_1 (0x300300dc) +#ifndef SOC_IFC_REG_CPTRA_FW_REV_ID_1 #define SOC_IFC_REG_CPTRA_FW_REV_ID_1 (0xdc) +#endif #define CLP_SOC_IFC_REG_CPTRA_HW_CONFIG (0x300300e0) +#ifndef SOC_IFC_REG_CPTRA_HW_CONFIG #define SOC_IFC_REG_CPTRA_HW_CONFIG (0xe0) #define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0) #define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (0x1) @@ -5911,315 +9824,585 @@ #define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10) #define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5) #define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (0x20) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (0x300300e4) +#ifndef SOC_IFC_REG_CPTRA_WDT_TIMER1_EN #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (0xe4) #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL (0x300300e8) +#ifndef SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL #define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL (0xe8) #define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW (0) #define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (0x300300ec) +#ifndef SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 #define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (0xec) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (0x300300f0) +#ifndef SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 #define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (0xf0) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN (0x300300f4) +#ifndef SOC_IFC_REG_CPTRA_WDT_TIMER2_EN #define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN (0xf4) #define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW (0) #define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL (0x300300f8) +#ifndef SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL #define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL (0xf8) #define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW (0) #define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (0x300300fc) +#ifndef SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 #define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (0xfc) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (0x30030100) +#ifndef SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 #define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (0x100) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_STATUS (0x30030104) +#ifndef SOC_IFC_REG_CPTRA_WDT_STATUS #define SOC_IFC_REG_CPTRA_WDT_STATUS (0x104) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW (0) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (0x1) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (0x2) +#endif #define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (0x30030108) +#ifndef SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER #define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (0x108) +#endif #define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (0x3003010c) +#ifndef SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK #define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (0x10c) #define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x30030110) +#ifndef SOC_IFC_REG_CPTRA_WDT_CFG_0 #define SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x110) +#endif #define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (0x30030114) +#ifndef SOC_IFC_REG_CPTRA_WDT_CFG_1 #define SOC_IFC_REG_CPTRA_WDT_CFG_1 (0x114) +#endif #define CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (0x30030118) +#ifndef SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (0x118) #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW (0) #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK (0xffff) #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW (16) #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK (0xffff0000) +#endif #define CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (0x3003011c) +#ifndef SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (0x11c) #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW (0) #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK (0xffff) #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW (16) #define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK (0xffff0000) +#endif #define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_0 (0x30030120) +#ifndef SOC_IFC_REG_CPTRA_RSVD_REG_0 #define SOC_IFC_REG_CPTRA_RSVD_REG_0 (0x120) +#endif #define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1 (0x30030124) +#ifndef SOC_IFC_REG_CPTRA_RSVD_REG_1 #define SOC_IFC_REG_CPTRA_RSVD_REG_1 (0x124) +#endif #define CLP_SOC_IFC_REG_CPTRA_HW_CAPABILITIES (0x30030128) +#ifndef SOC_IFC_REG_CPTRA_HW_CAPABILITIES #define SOC_IFC_REG_CPTRA_HW_CAPABILITIES (0x128) +#endif #define CLP_SOC_IFC_REG_CPTRA_FW_CAPABILITIES (0x3003012c) +#ifndef SOC_IFC_REG_CPTRA_FW_CAPABILITIES #define SOC_IFC_REG_CPTRA_FW_CAPABILITIES (0x12c) +#endif #define CLP_SOC_IFC_REG_CPTRA_CAP_LOCK (0x30030130) +#ifndef SOC_IFC_REG_CPTRA_CAP_LOCK #define SOC_IFC_REG_CPTRA_CAP_LOCK (0x130) #define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (0x30030140) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (0x140) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (0x30030144) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (0x144) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (0x30030148) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (0x148) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (0x3003014c) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (0x14c) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (0x30030150) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (0x150) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (0x30030154) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (0x154) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (0x30030158) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (0x158) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (0x3003015c) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (0x15c) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (0x30030160) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (0x160) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (0x30030164) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (0x164) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (0x30030168) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (0x168) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (0x3003016c) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (0x16c) +#endif #define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (0x30030170) +#ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (0x170) #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0) #define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_0 (0x30030200) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_0 #define SOC_IFC_REG_FUSE_UDS_SEED_0 (0x200) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_1 (0x30030204) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_1 #define SOC_IFC_REG_FUSE_UDS_SEED_1 (0x204) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_2 (0x30030208) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_2 #define SOC_IFC_REG_FUSE_UDS_SEED_2 (0x208) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_3 (0x3003020c) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_3 #define SOC_IFC_REG_FUSE_UDS_SEED_3 (0x20c) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_4 (0x30030210) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_4 #define SOC_IFC_REG_FUSE_UDS_SEED_4 (0x210) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_5 (0x30030214) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_5 #define SOC_IFC_REG_FUSE_UDS_SEED_5 (0x214) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_6 (0x30030218) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_6 #define SOC_IFC_REG_FUSE_UDS_SEED_6 (0x218) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_7 (0x3003021c) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_7 #define SOC_IFC_REG_FUSE_UDS_SEED_7 (0x21c) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_8 (0x30030220) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_8 #define SOC_IFC_REG_FUSE_UDS_SEED_8 (0x220) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_9 (0x30030224) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_9 #define SOC_IFC_REG_FUSE_UDS_SEED_9 (0x224) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_10 (0x30030228) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_10 #define SOC_IFC_REG_FUSE_UDS_SEED_10 (0x228) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_11 (0x3003022c) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_11 #define SOC_IFC_REG_FUSE_UDS_SEED_11 (0x22c) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_12 (0x30030230) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_12 #define SOC_IFC_REG_FUSE_UDS_SEED_12 (0x230) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_13 (0x30030234) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_13 #define SOC_IFC_REG_FUSE_UDS_SEED_13 (0x234) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_14 (0x30030238) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_14 #define SOC_IFC_REG_FUSE_UDS_SEED_14 (0x238) +#endif #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_15 (0x3003023c) +#ifndef SOC_IFC_REG_FUSE_UDS_SEED_15 #define SOC_IFC_REG_FUSE_UDS_SEED_15 (0x23c) +#endif #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 (0x30030240) +#ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 (0x240) +#endif #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_1 (0x30030244) +#ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_1 #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_1 (0x244) +#endif #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_2 (0x30030248) +#ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_2 #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_2 (0x248) +#endif #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_3 (0x3003024c) +#ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_3 #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_3 (0x24c) +#endif #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_4 (0x30030250) +#ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_4 #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_4 (0x250) +#endif #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_5 (0x30030254) +#ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_5 #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_5 (0x254) +#endif #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 (0x30030258) +#ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 (0x258) +#endif #define CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (0x3003025c) +#ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 #define SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (0x25c) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (0x30030260) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (0x260) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (0x30030264) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (0x264) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (0x30030268) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (0x268) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (0x3003026c) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (0x26c) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (0x30030270) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (0x270) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (0x30030274) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (0x274) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (0x30030278) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (0x278) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (0x3003027c) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (0x27c) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (0x30030280) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (0x280) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (0x30030284) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (0x284) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (0x30030288) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (0x288) +#endif #define CLP_SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (0x3003028c) +#ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 #define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (0x28c) +#endif #define CLP_SOC_IFC_REG_FUSE_ECC_REVOCATION (0x30030290) +#ifndef SOC_IFC_REG_FUSE_ECC_REVOCATION #define SOC_IFC_REG_FUSE_ECC_REVOCATION (0x290) #define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) #define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (0xf) +#endif #define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x300302b4) +#ifndef SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN #define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2b4) +#endif #define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (0x300302b8) +#ifndef SOC_IFC_REG_FUSE_RUNTIME_SVN_0 #define SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (0x2b8) +#endif #define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (0x300302bc) +#ifndef SOC_IFC_REG_FUSE_RUNTIME_SVN_1 #define SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (0x2bc) +#endif #define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (0x300302c0) +#ifndef SOC_IFC_REG_FUSE_RUNTIME_SVN_2 #define SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (0x2c0) +#endif #define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (0x300302c4) +#ifndef SOC_IFC_REG_FUSE_RUNTIME_SVN_3 #define SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (0x2c4) +#endif #define CLP_SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x300302c8) +#ifndef SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE #define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x2c8) #define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0) #define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (0x300302cc) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (0x2cc) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (0x300302d0) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (0x2d0) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (0x300302d4) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (0x2d4) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (0x300302d8) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (0x2d8) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (0x300302dc) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (0x2dc) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (0x300302e0) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (0x2e0) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (0x300302e4) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (0x2e4) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (0x300302e8) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (0x2e8) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (0x300302ec) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (0x2ec) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (0x300302f0) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (0x2f0) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (0x300302f4) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (0x2f4) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (0x300302f8) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (0x2f8) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (0x300302fc) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (0x2fc) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (0x30030300) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (0x300) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (0x30030304) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (0x304) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (0x30030308) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (0x308) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (0x3003030c) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (0x30c) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (0x30030310) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (0x310) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (0x30030314) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (0x314) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (0x30030318) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (0x318) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (0x3003031c) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (0x31c) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (0x30030320) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (0x320) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (0x30030324) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (0x324) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (0x30030328) +#ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 #define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (0x328) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x3003032c) +#ifndef SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 #define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x32c) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x30030330) +#ifndef SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 #define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x330) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x30030334) +#ifndef SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 #define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x334) +#endif #define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x30030338) +#ifndef SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 #define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x338) +#endif #define CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION (0x30030340) +#ifndef SOC_IFC_REG_FUSE_LMS_REVOCATION #define SOC_IFC_REG_FUSE_LMS_REVOCATION (0x340) +#endif #define CLP_SOC_IFC_REG_FUSE_MLDSA_REVOCATION (0x30030344) +#ifndef SOC_IFC_REG_FUSE_MLDSA_REVOCATION #define SOC_IFC_REG_FUSE_MLDSA_REVOCATION (0x344) #define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0) #define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (0xf) +#endif #define CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID (0x30030348) +#ifndef SOC_IFC_REG_FUSE_SOC_STEPPING_ID #define SOC_IFC_REG_FUSE_SOC_STEPPING_ID (0x348) #define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0) #define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (0xffff) +#endif #define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (0x3003034c) +#ifndef SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 #define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (0x34c) +#endif #define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (0x30030350) +#ifndef SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 #define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (0x350) +#endif #define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x30030354) +#ifndef SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 #define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x354) +#endif #define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x30030358) +#ifndef SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 #define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x358) +#endif #define CLP_SOC_IFC_REG_FUSE_PQC_KEY_TYPE (0x3003035c) +#ifndef SOC_IFC_REG_FUSE_PQC_KEY_TYPE #define SOC_IFC_REG_FUSE_PQC_KEY_TYPE (0x35c) #define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) #define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (0x3) +#endif #define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (0x30030360) +#ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 #define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (0x360) +#endif #define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (0x30030364) +#ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 #define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (0x364) +#endif #define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (0x30030368) +#ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 #define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (0x368) +#endif #define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (0x3003036c) +#ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 #define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (0x36c) +#endif #define CLP_SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (0x30030370) +#ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN #define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (0x370) #define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) #define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (0xff) +#endif #define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (0x30030500) +#ifndef SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L #define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (0x500) +#endif #define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (0x30030504) +#ifndef SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H #define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (0x504) +#endif #define CLP_SOC_IFC_REG_SS_MCI_BASE_ADDR_L (0x30030508) +#ifndef SOC_IFC_REG_SS_MCI_BASE_ADDR_L #define SOC_IFC_REG_SS_MCI_BASE_ADDR_L (0x508) +#endif #define CLP_SOC_IFC_REG_SS_MCI_BASE_ADDR_H (0x3003050c) +#ifndef SOC_IFC_REG_SS_MCI_BASE_ADDR_H #define SOC_IFC_REG_SS_MCI_BASE_ADDR_H (0x50c) +#endif #define CLP_SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (0x30030510) +#ifndef SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L #define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (0x510) +#endif #define CLP_SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (0x30030514) +#ifndef SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H #define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (0x514) +#endif #define CLP_SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (0x30030518) +#ifndef SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L #define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (0x518) +#endif #define CLP_SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (0x3003051c) +#ifndef SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H #define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (0x51c) +#endif #define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (0x30030520) +#ifndef SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L #define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (0x520) +#endif #define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (0x30030524) +#ifndef SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H #define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (0x524) +#endif #define CLP_SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x30030528) +#ifndef SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET #define SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x528) +#endif #define CLP_SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x3003052c) +#ifndef SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES #define SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x52c) +#endif #define CLP_SOC_IFC_REG_SS_DEBUG_INTENT (0x30030530) +#ifndef SOC_IFC_REG_SS_DEBUG_INTENT #define SOC_IFC_REG_SS_DEBUG_INTENT (0x530) #define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0) #define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_0 (0x300305a0) +#ifndef SOC_IFC_REG_SS_STRAP_GENERIC_0 #define SOC_IFC_REG_SS_STRAP_GENERIC_0 (0x5a0) +#endif #define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_1 (0x300305a4) +#ifndef SOC_IFC_REG_SS_STRAP_GENERIC_1 #define SOC_IFC_REG_SS_STRAP_GENERIC_1 (0x5a4) +#endif #define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_2 (0x300305a8) +#ifndef SOC_IFC_REG_SS_STRAP_GENERIC_2 #define SOC_IFC_REG_SS_STRAP_GENERIC_2 (0x5a8) +#endif #define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_3 (0x300305ac) +#ifndef SOC_IFC_REG_SS_STRAP_GENERIC_3 #define SOC_IFC_REG_SS_STRAP_GENERIC_3 (0x5ac) +#endif #define CLP_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (0x300305c0) +#ifndef SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (0x5c0) #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0) #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (0x1) @@ -6229,7 +10412,9 @@ #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (0x4) #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3) #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (0xfffffff8) +#endif #define CLP_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (0x300305c4) +#ifndef SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (0x5c4) #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0) #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (0x1) @@ -6251,49 +10436,87 @@ #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (0x100) #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9) #define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (0xfffffe00) +#endif #define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x300305c8) +#ifndef SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 #define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x5c8) +#endif #define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x300305cc) +#ifndef SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 #define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x5cc) +#endif #define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x300305d0) +#ifndef SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 #define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x5d0) +#endif #define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x300305d4) +#ifndef SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 #define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x5d4) +#endif #define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (0x300305d8) +#ifndef SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 #define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (0x5d8) +#endif #define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (0x300305dc) +#ifndef SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 #define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (0x5dc) +#endif #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0 (0x30030600) +#ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_0 #define SOC_IFC_REG_INTERNAL_OBF_KEY_0 (0x600) +#endif #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_1 (0x30030604) +#ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_1 #define SOC_IFC_REG_INTERNAL_OBF_KEY_1 (0x604) +#endif #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_2 (0x30030608) +#ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_2 #define SOC_IFC_REG_INTERNAL_OBF_KEY_2 (0x608) +#endif #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_3 (0x3003060c) +#ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_3 #define SOC_IFC_REG_INTERNAL_OBF_KEY_3 (0x60c) +#endif #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_4 (0x30030610) +#ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_4 #define SOC_IFC_REG_INTERNAL_OBF_KEY_4 (0x610) +#endif #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_5 (0x30030614) +#ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_5 #define SOC_IFC_REG_INTERNAL_OBF_KEY_5 (0x614) +#endif #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_6 (0x30030618) +#ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_6 #define SOC_IFC_REG_INTERNAL_OBF_KEY_6 (0x618) +#endif #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_7 (0x3003061c) +#ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_7 #define SOC_IFC_REG_INTERNAL_OBF_KEY_7 (0x61c) +#endif #define CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK (0x30030620) +#ifndef SOC_IFC_REG_INTERNAL_ICCM_LOCK #define SOC_IFC_REG_INTERNAL_ICCM_LOCK (0x620) #define SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_LOW (0) #define SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET (0x30030624) +#ifndef SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET #define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET (0x624) #define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_LOW (0) #define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES (0x30030628) +#ifndef SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES #define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES (0x628) #define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_LOW (0) #define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_MASK (0xff) +#endif #define CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR (0x3003062c) +#ifndef SOC_IFC_REG_INTERNAL_NMI_VECTOR #define SOC_IFC_REG_INTERNAL_NMI_VECTOR (0x62c) +#endif #define CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK (0x30030630) +#ifndef SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK #define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK (0x630) #define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_LOW (0) #define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK (0x1) @@ -6303,7 +10526,9 @@ #define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK (0x4) #define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_CRYPTO_ERR_LOW (3) #define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_CRYPTO_ERR_MASK (0x8) +#endif #define CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK (0x30030634) +#ifndef SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK #define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK (0x634) #define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_LOW (0) #define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_MASK (0x1) @@ -6311,26 +10536,42 @@ #define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_MASK (0x2) #define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_LOW (2) #define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK (0x4) +#endif #define CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK (0x30030638) +#ifndef SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK #define SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK (0x638) +#endif #define CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK (0x3003063c) +#ifndef SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK #define SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK (0x63c) +#endif #define CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L (0x30030640) +#ifndef SOC_IFC_REG_INTERNAL_RV_MTIME_L #define SOC_IFC_REG_INTERNAL_RV_MTIME_L (0x640) +#endif #define CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H (0x30030644) +#ifndef SOC_IFC_REG_INTERNAL_RV_MTIME_H #define SOC_IFC_REG_INTERNAL_RV_MTIME_H (0x644) +#endif #define CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L (0x30030648) +#ifndef SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L #define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L (0x648) +#endif #define CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H (0x3003064c) +#ifndef SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H #define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H (0x64c) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_START (0x30030800) #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x30030800) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R #define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (0x800) #define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (0x1) #define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) #define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (0x2) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x30030804) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (0x804) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (0x1) @@ -6348,7 +10589,9 @@ #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK (0x40) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_LOW (7) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK (0x80) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x30030808) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (0x808) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_MASK (0x1) @@ -6362,15 +10605,21 @@ #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK (0x10) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_LOW (5) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK (0x20) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x3003080c) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (0x80c) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x30030810) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (0x810) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x30030814) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (0x814) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (0x1) @@ -6388,7 +10637,9 @@ #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK (0x40) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_LOW (7) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK (0x80) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x30030818) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (0x818) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK (0x1) @@ -6402,7 +10653,9 @@ #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK (0x10) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_LOW (5) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK (0x20) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x3003081c) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (0x81c) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (0x1) @@ -6420,7 +10673,9 @@ #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER1_TIMEOUT_TRIG_MASK (0x40) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_LOW (7) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_MASK (0x80) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x30030820) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (0x820) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_MASK (0x1) @@ -6434,90 +10689,147 @@ #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK (0x10) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_LOW (5) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_MASK (0x20) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (0x30030900) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (0x900) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R (0x30030904) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R (0x904) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R (0x30030908) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R (0x908) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R (0x3003090c) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R (0x90c) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R (0x30030910) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R (0x910) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R (0x30030914) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R (0x914) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R (0x30030918) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R (0x918) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R (0x3003091c) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R (0x91c) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R (0x30030980) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R (0x980) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R (0x30030984) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R (0x984) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R (0x30030988) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R (0x988) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R (0x3003098c) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R (0x98c) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R (0x30030990) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R (0x990) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R (0x30030994) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R (0x994) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (0x30030a00) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (0xa00) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R (0x30030a04) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R (0xa04) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R (0x30030a08) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R (0xa08) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R (0x30030a0c) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R (0xa0c) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R (0x30030a10) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R (0xa10) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R (0x30030a14) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R (0xa14) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R (0x30030a18) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R (0xa18) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R (0x30030a1c) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R (0xa1c) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R (0x30030a20) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R (0xa20) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R (0x30030a24) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R (0xa24) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R (0x30030a28) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R (0xa28) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R (0x30030a2c) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R (0xa2c) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R (0x30030a30) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R (0xa30) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R (0x30030a34) +#ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R (0xa34) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW (0) #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK (0x1) +#endif #define CLP_MBOX_SRAM_BASE_ADDR (0x30040000) #define CLP_MBOX_SRAM_END_ADDR (0x3007ffff) diff --git a/src/integration/rtl/caliptra_reg_field_defines.svh b/src/integration/rtl/caliptra_reg_field_defines.svh index d5f799bd1..592fcbc97 100644 --- a/src/integration/rtl/caliptra_reg_field_defines.svh +++ b/src/integration/rtl/caliptra_reg_field_defines.svh @@ -16,15 +16,26 @@ `define CALIPTRA_REG_FIELD_DEFINES_HEADER +`ifndef DOE_REG_DOE_IV_0 `define DOE_REG_DOE_IV_0 (32'h0) +`endif +`ifndef DOE_REG_DOE_IV_1 `define DOE_REG_DOE_IV_1 (32'h4) +`endif +`ifndef DOE_REG_DOE_IV_2 `define DOE_REG_DOE_IV_2 (32'h8) +`endif +`ifndef DOE_REG_DOE_IV_3 `define DOE_REG_DOE_IV_3 (32'hc) +`endif +`ifndef DOE_REG_DOE_CTRL `define DOE_REG_DOE_CTRL (32'h10) `define DOE_REG_DOE_CTRL_CMD_LOW (0) `define DOE_REG_DOE_CTRL_CMD_MASK (32'h3) `define DOE_REG_DOE_CTRL_DEST_LOW (2) `define DOE_REG_DOE_CTRL_DEST_MASK (32'h7c) +`endif +`ifndef DOE_REG_DOE_STATUS `define DOE_REG_DOE_STATUS (32'h14) `define DOE_REG_DOE_STATUS_READY_LOW (0) `define DOE_REG_DOE_STATUS_READY_MASK (32'h1) @@ -36,11 +47,15 @@ `define DOE_REG_DOE_STATUS_FE_FLOW_DONE_MASK (32'h8) `define DOE_REG_DOE_STATUS_DEOBF_SECRETS_CLEARED_LOW (4) `define DOE_REG_DOE_STATUS_DEOBF_SECRETS_CLEARED_MASK (32'h10) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) @@ -50,15 +65,23 @@ `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define DOE_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define DOE_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) @@ -68,9 +91,13 @@ `define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) @@ -80,33 +107,65 @@ `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) `define DOE_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) `define DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R `define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R `define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R `define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R `define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R `define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R `define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) `define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) `define DOE_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R `define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) `define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) `define DOE_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R `define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) `define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) `define DOE_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R `define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) `define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) `define DOE_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R `define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) `define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define DOE_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef ECC_REG_ECC_NAME_0 `define ECC_REG_ECC_NAME_0 (32'h0) +`endif +`ifndef ECC_REG_ECC_NAME_1 `define ECC_REG_ECC_NAME_1 (32'h4) +`endif +`ifndef ECC_REG_ECC_VERSION_0 `define ECC_REG_ECC_VERSION_0 (32'h8) +`endif +`ifndef ECC_REG_ECC_VERSION_1 `define ECC_REG_ECC_VERSION_1 (32'hc) +`endif +`ifndef ECC_REG_ECC_CTRL `define ECC_REG_ECC_CTRL (32'h10) `define ECC_REG_ECC_CTRL_CTRL_LOW (0) `define ECC_REG_ECC_CTRL_CTRL_MASK (32'h3) @@ -116,155 +175,447 @@ `define ECC_REG_ECC_CTRL_PCR_SIGN_MASK (32'h8) `define ECC_REG_ECC_CTRL_DH_SHAREDKEY_LOW (4) `define ECC_REG_ECC_CTRL_DH_SHAREDKEY_MASK (32'h10) +`endif +`ifndef ECC_REG_ECC_STATUS `define ECC_REG_ECC_STATUS (32'h18) `define ECC_REG_ECC_STATUS_READY_LOW (0) `define ECC_REG_ECC_STATUS_READY_MASK (32'h1) `define ECC_REG_ECC_STATUS_VALID_LOW (1) `define ECC_REG_ECC_STATUS_VALID_MASK (32'h2) +`endif +`ifndef ECC_REG_ECC_SEED_0 `define ECC_REG_ECC_SEED_0 (32'h80) +`endif +`ifndef ECC_REG_ECC_SEED_1 `define ECC_REG_ECC_SEED_1 (32'h84) +`endif +`ifndef ECC_REG_ECC_SEED_2 `define ECC_REG_ECC_SEED_2 (32'h88) +`endif +`ifndef ECC_REG_ECC_SEED_3 `define ECC_REG_ECC_SEED_3 (32'h8c) +`endif +`ifndef ECC_REG_ECC_SEED_4 `define ECC_REG_ECC_SEED_4 (32'h90) +`endif +`ifndef ECC_REG_ECC_SEED_5 `define ECC_REG_ECC_SEED_5 (32'h94) +`endif +`ifndef ECC_REG_ECC_SEED_6 `define ECC_REG_ECC_SEED_6 (32'h98) +`endif +`ifndef ECC_REG_ECC_SEED_7 `define ECC_REG_ECC_SEED_7 (32'h9c) +`endif +`ifndef ECC_REG_ECC_SEED_8 `define ECC_REG_ECC_SEED_8 (32'ha0) +`endif +`ifndef ECC_REG_ECC_SEED_9 `define ECC_REG_ECC_SEED_9 (32'ha4) +`endif +`ifndef ECC_REG_ECC_SEED_10 `define ECC_REG_ECC_SEED_10 (32'ha8) +`endif +`ifndef ECC_REG_ECC_SEED_11 `define ECC_REG_ECC_SEED_11 (32'hac) +`endif +`ifndef ECC_REG_ECC_MSG_0 `define ECC_REG_ECC_MSG_0 (32'h100) +`endif +`ifndef ECC_REG_ECC_MSG_1 `define ECC_REG_ECC_MSG_1 (32'h104) +`endif +`ifndef ECC_REG_ECC_MSG_2 `define ECC_REG_ECC_MSG_2 (32'h108) +`endif +`ifndef ECC_REG_ECC_MSG_3 `define ECC_REG_ECC_MSG_3 (32'h10c) +`endif +`ifndef ECC_REG_ECC_MSG_4 `define ECC_REG_ECC_MSG_4 (32'h110) +`endif +`ifndef ECC_REG_ECC_MSG_5 `define ECC_REG_ECC_MSG_5 (32'h114) +`endif +`ifndef ECC_REG_ECC_MSG_6 `define ECC_REG_ECC_MSG_6 (32'h118) +`endif +`ifndef ECC_REG_ECC_MSG_7 `define ECC_REG_ECC_MSG_7 (32'h11c) +`endif +`ifndef ECC_REG_ECC_MSG_8 `define ECC_REG_ECC_MSG_8 (32'h120) +`endif +`ifndef ECC_REG_ECC_MSG_9 `define ECC_REG_ECC_MSG_9 (32'h124) +`endif +`ifndef ECC_REG_ECC_MSG_10 `define ECC_REG_ECC_MSG_10 (32'h128) +`endif +`ifndef ECC_REG_ECC_MSG_11 `define ECC_REG_ECC_MSG_11 (32'h12c) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_0 `define ECC_REG_ECC_PRIVKEY_OUT_0 (32'h180) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_1 `define ECC_REG_ECC_PRIVKEY_OUT_1 (32'h184) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_2 `define ECC_REG_ECC_PRIVKEY_OUT_2 (32'h188) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_3 `define ECC_REG_ECC_PRIVKEY_OUT_3 (32'h18c) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_4 `define ECC_REG_ECC_PRIVKEY_OUT_4 (32'h190) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_5 `define ECC_REG_ECC_PRIVKEY_OUT_5 (32'h194) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_6 `define ECC_REG_ECC_PRIVKEY_OUT_6 (32'h198) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_7 `define ECC_REG_ECC_PRIVKEY_OUT_7 (32'h19c) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_8 `define ECC_REG_ECC_PRIVKEY_OUT_8 (32'h1a0) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_9 `define ECC_REG_ECC_PRIVKEY_OUT_9 (32'h1a4) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_10 `define ECC_REG_ECC_PRIVKEY_OUT_10 (32'h1a8) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_OUT_11 `define ECC_REG_ECC_PRIVKEY_OUT_11 (32'h1ac) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_0 `define ECC_REG_ECC_PUBKEY_X_0 (32'h200) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_1 `define ECC_REG_ECC_PUBKEY_X_1 (32'h204) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_2 `define ECC_REG_ECC_PUBKEY_X_2 (32'h208) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_3 `define ECC_REG_ECC_PUBKEY_X_3 (32'h20c) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_4 `define ECC_REG_ECC_PUBKEY_X_4 (32'h210) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_5 `define ECC_REG_ECC_PUBKEY_X_5 (32'h214) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_6 `define ECC_REG_ECC_PUBKEY_X_6 (32'h218) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_7 `define ECC_REG_ECC_PUBKEY_X_7 (32'h21c) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_8 `define ECC_REG_ECC_PUBKEY_X_8 (32'h220) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_9 `define ECC_REG_ECC_PUBKEY_X_9 (32'h224) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_10 `define ECC_REG_ECC_PUBKEY_X_10 (32'h228) +`endif +`ifndef ECC_REG_ECC_PUBKEY_X_11 `define ECC_REG_ECC_PUBKEY_X_11 (32'h22c) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_0 `define ECC_REG_ECC_PUBKEY_Y_0 (32'h280) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_1 `define ECC_REG_ECC_PUBKEY_Y_1 (32'h284) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_2 `define ECC_REG_ECC_PUBKEY_Y_2 (32'h288) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_3 `define ECC_REG_ECC_PUBKEY_Y_3 (32'h28c) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_4 `define ECC_REG_ECC_PUBKEY_Y_4 (32'h290) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_5 `define ECC_REG_ECC_PUBKEY_Y_5 (32'h294) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_6 `define ECC_REG_ECC_PUBKEY_Y_6 (32'h298) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_7 `define ECC_REG_ECC_PUBKEY_Y_7 (32'h29c) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_8 `define ECC_REG_ECC_PUBKEY_Y_8 (32'h2a0) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_9 `define ECC_REG_ECC_PUBKEY_Y_9 (32'h2a4) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_10 `define ECC_REG_ECC_PUBKEY_Y_10 (32'h2a8) +`endif +`ifndef ECC_REG_ECC_PUBKEY_Y_11 `define ECC_REG_ECC_PUBKEY_Y_11 (32'h2ac) +`endif +`ifndef ECC_REG_ECC_SIGN_R_0 `define ECC_REG_ECC_SIGN_R_0 (32'h300) +`endif +`ifndef ECC_REG_ECC_SIGN_R_1 `define ECC_REG_ECC_SIGN_R_1 (32'h304) +`endif +`ifndef ECC_REG_ECC_SIGN_R_2 `define ECC_REG_ECC_SIGN_R_2 (32'h308) +`endif +`ifndef ECC_REG_ECC_SIGN_R_3 `define ECC_REG_ECC_SIGN_R_3 (32'h30c) +`endif +`ifndef ECC_REG_ECC_SIGN_R_4 `define ECC_REG_ECC_SIGN_R_4 (32'h310) +`endif +`ifndef ECC_REG_ECC_SIGN_R_5 `define ECC_REG_ECC_SIGN_R_5 (32'h314) +`endif +`ifndef ECC_REG_ECC_SIGN_R_6 `define ECC_REG_ECC_SIGN_R_6 (32'h318) +`endif +`ifndef ECC_REG_ECC_SIGN_R_7 `define ECC_REG_ECC_SIGN_R_7 (32'h31c) +`endif +`ifndef ECC_REG_ECC_SIGN_R_8 `define ECC_REG_ECC_SIGN_R_8 (32'h320) +`endif +`ifndef ECC_REG_ECC_SIGN_R_9 `define ECC_REG_ECC_SIGN_R_9 (32'h324) +`endif +`ifndef ECC_REG_ECC_SIGN_R_10 `define ECC_REG_ECC_SIGN_R_10 (32'h328) +`endif +`ifndef ECC_REG_ECC_SIGN_R_11 `define ECC_REG_ECC_SIGN_R_11 (32'h32c) +`endif +`ifndef ECC_REG_ECC_SIGN_S_0 `define ECC_REG_ECC_SIGN_S_0 (32'h380) +`endif +`ifndef ECC_REG_ECC_SIGN_S_1 `define ECC_REG_ECC_SIGN_S_1 (32'h384) +`endif +`ifndef ECC_REG_ECC_SIGN_S_2 `define ECC_REG_ECC_SIGN_S_2 (32'h388) +`endif +`ifndef ECC_REG_ECC_SIGN_S_3 `define ECC_REG_ECC_SIGN_S_3 (32'h38c) +`endif +`ifndef ECC_REG_ECC_SIGN_S_4 `define ECC_REG_ECC_SIGN_S_4 (32'h390) +`endif +`ifndef ECC_REG_ECC_SIGN_S_5 `define ECC_REG_ECC_SIGN_S_5 (32'h394) +`endif +`ifndef ECC_REG_ECC_SIGN_S_6 `define ECC_REG_ECC_SIGN_S_6 (32'h398) +`endif +`ifndef ECC_REG_ECC_SIGN_S_7 `define ECC_REG_ECC_SIGN_S_7 (32'h39c) +`endif +`ifndef ECC_REG_ECC_SIGN_S_8 `define ECC_REG_ECC_SIGN_S_8 (32'h3a0) +`endif +`ifndef ECC_REG_ECC_SIGN_S_9 `define ECC_REG_ECC_SIGN_S_9 (32'h3a4) +`endif +`ifndef ECC_REG_ECC_SIGN_S_10 `define ECC_REG_ECC_SIGN_S_10 (32'h3a8) +`endif +`ifndef ECC_REG_ECC_SIGN_S_11 `define ECC_REG_ECC_SIGN_S_11 (32'h3ac) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_0 `define ECC_REG_ECC_VERIFY_R_0 (32'h400) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_1 `define ECC_REG_ECC_VERIFY_R_1 (32'h404) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_2 `define ECC_REG_ECC_VERIFY_R_2 (32'h408) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_3 `define ECC_REG_ECC_VERIFY_R_3 (32'h40c) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_4 `define ECC_REG_ECC_VERIFY_R_4 (32'h410) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_5 `define ECC_REG_ECC_VERIFY_R_5 (32'h414) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_6 `define ECC_REG_ECC_VERIFY_R_6 (32'h418) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_7 `define ECC_REG_ECC_VERIFY_R_7 (32'h41c) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_8 `define ECC_REG_ECC_VERIFY_R_8 (32'h420) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_9 `define ECC_REG_ECC_VERIFY_R_9 (32'h424) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_10 `define ECC_REG_ECC_VERIFY_R_10 (32'h428) +`endif +`ifndef ECC_REG_ECC_VERIFY_R_11 `define ECC_REG_ECC_VERIFY_R_11 (32'h42c) +`endif +`ifndef ECC_REG_ECC_IV_0 `define ECC_REG_ECC_IV_0 (32'h480) +`endif +`ifndef ECC_REG_ECC_IV_1 `define ECC_REG_ECC_IV_1 (32'h484) +`endif +`ifndef ECC_REG_ECC_IV_2 `define ECC_REG_ECC_IV_2 (32'h488) +`endif +`ifndef ECC_REG_ECC_IV_3 `define ECC_REG_ECC_IV_3 (32'h48c) +`endif +`ifndef ECC_REG_ECC_IV_4 `define ECC_REG_ECC_IV_4 (32'h490) +`endif +`ifndef ECC_REG_ECC_IV_5 `define ECC_REG_ECC_IV_5 (32'h494) +`endif +`ifndef ECC_REG_ECC_IV_6 `define ECC_REG_ECC_IV_6 (32'h498) +`endif +`ifndef ECC_REG_ECC_IV_7 `define ECC_REG_ECC_IV_7 (32'h49c) +`endif +`ifndef ECC_REG_ECC_IV_8 `define ECC_REG_ECC_IV_8 (32'h4a0) +`endif +`ifndef ECC_REG_ECC_IV_9 `define ECC_REG_ECC_IV_9 (32'h4a4) +`endif +`ifndef ECC_REG_ECC_IV_10 `define ECC_REG_ECC_IV_10 (32'h4a8) +`endif +`ifndef ECC_REG_ECC_IV_11 `define ECC_REG_ECC_IV_11 (32'h4ac) +`endif +`ifndef ECC_REG_ECC_NONCE_0 `define ECC_REG_ECC_NONCE_0 (32'h500) +`endif +`ifndef ECC_REG_ECC_NONCE_1 `define ECC_REG_ECC_NONCE_1 (32'h504) +`endif +`ifndef ECC_REG_ECC_NONCE_2 `define ECC_REG_ECC_NONCE_2 (32'h508) +`endif +`ifndef ECC_REG_ECC_NONCE_3 `define ECC_REG_ECC_NONCE_3 (32'h50c) +`endif +`ifndef ECC_REG_ECC_NONCE_4 `define ECC_REG_ECC_NONCE_4 (32'h510) +`endif +`ifndef ECC_REG_ECC_NONCE_5 `define ECC_REG_ECC_NONCE_5 (32'h514) +`endif +`ifndef ECC_REG_ECC_NONCE_6 `define ECC_REG_ECC_NONCE_6 (32'h518) +`endif +`ifndef ECC_REG_ECC_NONCE_7 `define ECC_REG_ECC_NONCE_7 (32'h51c) +`endif +`ifndef ECC_REG_ECC_NONCE_8 `define ECC_REG_ECC_NONCE_8 (32'h520) +`endif +`ifndef ECC_REG_ECC_NONCE_9 `define ECC_REG_ECC_NONCE_9 (32'h524) +`endif +`ifndef ECC_REG_ECC_NONCE_10 `define ECC_REG_ECC_NONCE_10 (32'h528) +`endif +`ifndef ECC_REG_ECC_NONCE_11 `define ECC_REG_ECC_NONCE_11 (32'h52c) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_0 `define ECC_REG_ECC_PRIVKEY_IN_0 (32'h580) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_1 `define ECC_REG_ECC_PRIVKEY_IN_1 (32'h584) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_2 `define ECC_REG_ECC_PRIVKEY_IN_2 (32'h588) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_3 `define ECC_REG_ECC_PRIVKEY_IN_3 (32'h58c) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_4 `define ECC_REG_ECC_PRIVKEY_IN_4 (32'h590) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_5 `define ECC_REG_ECC_PRIVKEY_IN_5 (32'h594) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_6 `define ECC_REG_ECC_PRIVKEY_IN_6 (32'h598) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_7 `define ECC_REG_ECC_PRIVKEY_IN_7 (32'h59c) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_8 `define ECC_REG_ECC_PRIVKEY_IN_8 (32'h5a0) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_9 `define ECC_REG_ECC_PRIVKEY_IN_9 (32'h5a4) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_10 `define ECC_REG_ECC_PRIVKEY_IN_10 (32'h5a8) +`endif +`ifndef ECC_REG_ECC_PRIVKEY_IN_11 `define ECC_REG_ECC_PRIVKEY_IN_11 (32'h5ac) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_0 `define ECC_REG_ECC_DH_SHARED_KEY_0 (32'h5c0) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_1 `define ECC_REG_ECC_DH_SHARED_KEY_1 (32'h5c4) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_2 `define ECC_REG_ECC_DH_SHARED_KEY_2 (32'h5c8) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_3 `define ECC_REG_ECC_DH_SHARED_KEY_3 (32'h5cc) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_4 `define ECC_REG_ECC_DH_SHARED_KEY_4 (32'h5d0) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_5 `define ECC_REG_ECC_DH_SHARED_KEY_5 (32'h5d4) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_6 `define ECC_REG_ECC_DH_SHARED_KEY_6 (32'h5d8) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_7 `define ECC_REG_ECC_DH_SHARED_KEY_7 (32'h5dc) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_8 `define ECC_REG_ECC_DH_SHARED_KEY_8 (32'h5e0) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_9 `define ECC_REG_ECC_DH_SHARED_KEY_9 (32'h5e4) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_10 `define ECC_REG_ECC_DH_SHARED_KEY_10 (32'h5e8) +`endif +`ifndef ECC_REG_ECC_DH_SHARED_KEY_11 `define ECC_REG_ECC_DH_SHARED_KEY_11 (32'h5ec) +`endif +`ifndef ECC_REG_ECC_KV_RD_PKEY_CTRL `define ECC_REG_ECC_KV_RD_PKEY_CTRL (32'h600) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_LOW (0) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_READ_EN_MASK (32'h1) @@ -274,6 +625,8 @@ `define ECC_REG_ECC_KV_RD_PKEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_LOW (7) `define ECC_REG_ECC_KV_RD_PKEY_CTRL_RSVD_MASK (32'hffffff80) +`endif +`ifndef ECC_REG_ECC_KV_RD_PKEY_STATUS `define ECC_REG_ECC_KV_RD_PKEY_STATUS (32'h604) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_LOW (0) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_READY_MASK (32'h1) @@ -281,6 +634,8 @@ `define ECC_REG_ECC_KV_RD_PKEY_STATUS_VALID_MASK (32'h2) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_LOW (2) `define ECC_REG_ECC_KV_RD_PKEY_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef ECC_REG_ECC_KV_RD_SEED_CTRL `define ECC_REG_ECC_KV_RD_SEED_CTRL (32'h608) `define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_LOW (0) `define ECC_REG_ECC_KV_RD_SEED_CTRL_READ_EN_MASK (32'h1) @@ -290,6 +645,8 @@ `define ECC_REG_ECC_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_LOW (7) `define ECC_REG_ECC_KV_RD_SEED_CTRL_RSVD_MASK (32'hffffff80) +`endif +`ifndef ECC_REG_ECC_KV_RD_SEED_STATUS `define ECC_REG_ECC_KV_RD_SEED_STATUS (32'h60c) `define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_LOW (0) `define ECC_REG_ECC_KV_RD_SEED_STATUS_READY_MASK (32'h1) @@ -297,6 +654,8 @@ `define ECC_REG_ECC_KV_RD_SEED_STATUS_VALID_MASK (32'h2) `define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_LOW (2) `define ECC_REG_ECC_KV_RD_SEED_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef ECC_REG_ECC_KV_WR_PKEY_CTRL `define ECC_REG_ECC_KV_WR_PKEY_CTRL (32'h610) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_LOW (0) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_WRITE_EN_MASK (32'h1) @@ -316,6 +675,8 @@ `define ECC_REG_ECC_KV_WR_PKEY_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_LOW (12) `define ECC_REG_ECC_KV_WR_PKEY_CTRL_RSVD_MASK (32'hfffff000) +`endif +`ifndef ECC_REG_ECC_KV_WR_PKEY_STATUS `define ECC_REG_ECC_KV_WR_PKEY_STATUS (32'h614) `define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_LOW (0) `define ECC_REG_ECC_KV_WR_PKEY_STATUS_READY_MASK (32'h1) @@ -323,47 +684,83 @@ `define ECC_REG_ECC_KV_WR_PKEY_STATUS_VALID_MASK (32'h2) `define ECC_REG_ECC_KV_WR_PKEY_STATUS_ERROR_LOW (2) `define ECC_REG_ECC_KV_WR_PKEY_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) `define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define ECC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define ECC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) `define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) `define ECC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) `define ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R `define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h900) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R `define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R `define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'ha00) `define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) `define ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R `define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha04) `define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define ECC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef HMAC_REG_HMAC512_NAME_0 `define HMAC_REG_HMAC512_NAME_0 (32'h0) +`endif +`ifndef HMAC_REG_HMAC512_NAME_1 `define HMAC_REG_HMAC512_NAME_1 (32'h4) +`endif +`ifndef HMAC_REG_HMAC512_VERSION_0 `define HMAC_REG_HMAC512_VERSION_0 (32'h8) +`endif +`ifndef HMAC_REG_HMAC512_VERSION_1 `define HMAC_REG_HMAC512_VERSION_1 (32'hc) +`endif +`ifndef HMAC_REG_HMAC512_CTRL `define HMAC_REG_HMAC512_CTRL (32'h10) `define HMAC_REG_HMAC512_CTRL_INIT_LOW (0) `define HMAC_REG_HMAC512_CTRL_INIT_MASK (32'h1) @@ -377,87 +774,243 @@ `define HMAC_REG_HMAC512_CTRL_CSR_MODE_MASK (32'h10) `define HMAC_REG_HMAC512_CTRL_RESERVED_LOW (5) `define HMAC_REG_HMAC512_CTRL_RESERVED_MASK (32'h20) +`endif +`ifndef HMAC_REG_HMAC512_STATUS `define HMAC_REG_HMAC512_STATUS (32'h18) `define HMAC_REG_HMAC512_STATUS_READY_LOW (0) `define HMAC_REG_HMAC512_STATUS_READY_MASK (32'h1) `define HMAC_REG_HMAC512_STATUS_VALID_LOW (1) `define HMAC_REG_HMAC512_STATUS_VALID_MASK (32'h2) +`endif +`ifndef HMAC_REG_HMAC512_KEY_0 `define HMAC_REG_HMAC512_KEY_0 (32'h40) +`endif +`ifndef HMAC_REG_HMAC512_KEY_1 `define HMAC_REG_HMAC512_KEY_1 (32'h44) +`endif +`ifndef HMAC_REG_HMAC512_KEY_2 `define HMAC_REG_HMAC512_KEY_2 (32'h48) +`endif +`ifndef HMAC_REG_HMAC512_KEY_3 `define HMAC_REG_HMAC512_KEY_3 (32'h4c) +`endif +`ifndef HMAC_REG_HMAC512_KEY_4 `define HMAC_REG_HMAC512_KEY_4 (32'h50) +`endif +`ifndef HMAC_REG_HMAC512_KEY_5 `define HMAC_REG_HMAC512_KEY_5 (32'h54) +`endif +`ifndef HMAC_REG_HMAC512_KEY_6 `define HMAC_REG_HMAC512_KEY_6 (32'h58) +`endif +`ifndef HMAC_REG_HMAC512_KEY_7 `define HMAC_REG_HMAC512_KEY_7 (32'h5c) +`endif +`ifndef HMAC_REG_HMAC512_KEY_8 `define HMAC_REG_HMAC512_KEY_8 (32'h60) +`endif +`ifndef HMAC_REG_HMAC512_KEY_9 `define HMAC_REG_HMAC512_KEY_9 (32'h64) +`endif +`ifndef HMAC_REG_HMAC512_KEY_10 `define HMAC_REG_HMAC512_KEY_10 (32'h68) +`endif +`ifndef HMAC_REG_HMAC512_KEY_11 `define HMAC_REG_HMAC512_KEY_11 (32'h6c) +`endif +`ifndef HMAC_REG_HMAC512_KEY_12 `define HMAC_REG_HMAC512_KEY_12 (32'h70) +`endif +`ifndef HMAC_REG_HMAC512_KEY_13 `define HMAC_REG_HMAC512_KEY_13 (32'h74) +`endif +`ifndef HMAC_REG_HMAC512_KEY_14 `define HMAC_REG_HMAC512_KEY_14 (32'h78) +`endif +`ifndef HMAC_REG_HMAC512_KEY_15 `define HMAC_REG_HMAC512_KEY_15 (32'h7c) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_0 `define HMAC_REG_HMAC512_BLOCK_0 (32'h80) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_1 `define HMAC_REG_HMAC512_BLOCK_1 (32'h84) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_2 `define HMAC_REG_HMAC512_BLOCK_2 (32'h88) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_3 `define HMAC_REG_HMAC512_BLOCK_3 (32'h8c) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_4 `define HMAC_REG_HMAC512_BLOCK_4 (32'h90) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_5 `define HMAC_REG_HMAC512_BLOCK_5 (32'h94) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_6 `define HMAC_REG_HMAC512_BLOCK_6 (32'h98) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_7 `define HMAC_REG_HMAC512_BLOCK_7 (32'h9c) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_8 `define HMAC_REG_HMAC512_BLOCK_8 (32'ha0) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_9 `define HMAC_REG_HMAC512_BLOCK_9 (32'ha4) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_10 `define HMAC_REG_HMAC512_BLOCK_10 (32'ha8) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_11 `define HMAC_REG_HMAC512_BLOCK_11 (32'hac) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_12 `define HMAC_REG_HMAC512_BLOCK_12 (32'hb0) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_13 `define HMAC_REG_HMAC512_BLOCK_13 (32'hb4) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_14 `define HMAC_REG_HMAC512_BLOCK_14 (32'hb8) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_15 `define HMAC_REG_HMAC512_BLOCK_15 (32'hbc) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_16 `define HMAC_REG_HMAC512_BLOCK_16 (32'hc0) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_17 `define HMAC_REG_HMAC512_BLOCK_17 (32'hc4) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_18 `define HMAC_REG_HMAC512_BLOCK_18 (32'hc8) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_19 `define HMAC_REG_HMAC512_BLOCK_19 (32'hcc) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_20 `define HMAC_REG_HMAC512_BLOCK_20 (32'hd0) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_21 `define HMAC_REG_HMAC512_BLOCK_21 (32'hd4) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_22 `define HMAC_REG_HMAC512_BLOCK_22 (32'hd8) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_23 `define HMAC_REG_HMAC512_BLOCK_23 (32'hdc) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_24 `define HMAC_REG_HMAC512_BLOCK_24 (32'he0) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_25 `define HMAC_REG_HMAC512_BLOCK_25 (32'he4) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_26 `define HMAC_REG_HMAC512_BLOCK_26 (32'he8) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_27 `define HMAC_REG_HMAC512_BLOCK_27 (32'hec) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_28 `define HMAC_REG_HMAC512_BLOCK_28 (32'hf0) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_29 `define HMAC_REG_HMAC512_BLOCK_29 (32'hf4) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_30 `define HMAC_REG_HMAC512_BLOCK_30 (32'hf8) +`endif +`ifndef HMAC_REG_HMAC512_BLOCK_31 `define HMAC_REG_HMAC512_BLOCK_31 (32'hfc) +`endif +`ifndef HMAC_REG_HMAC512_TAG_0 `define HMAC_REG_HMAC512_TAG_0 (32'h100) +`endif +`ifndef HMAC_REG_HMAC512_TAG_1 `define HMAC_REG_HMAC512_TAG_1 (32'h104) +`endif +`ifndef HMAC_REG_HMAC512_TAG_2 `define HMAC_REG_HMAC512_TAG_2 (32'h108) +`endif +`ifndef HMAC_REG_HMAC512_TAG_3 `define HMAC_REG_HMAC512_TAG_3 (32'h10c) +`endif +`ifndef HMAC_REG_HMAC512_TAG_4 `define HMAC_REG_HMAC512_TAG_4 (32'h110) +`endif +`ifndef HMAC_REG_HMAC512_TAG_5 `define HMAC_REG_HMAC512_TAG_5 (32'h114) +`endif +`ifndef HMAC_REG_HMAC512_TAG_6 `define HMAC_REG_HMAC512_TAG_6 (32'h118) +`endif +`ifndef HMAC_REG_HMAC512_TAG_7 `define HMAC_REG_HMAC512_TAG_7 (32'h11c) +`endif +`ifndef HMAC_REG_HMAC512_TAG_8 `define HMAC_REG_HMAC512_TAG_8 (32'h120) +`endif +`ifndef HMAC_REG_HMAC512_TAG_9 `define HMAC_REG_HMAC512_TAG_9 (32'h124) +`endif +`ifndef HMAC_REG_HMAC512_TAG_10 `define HMAC_REG_HMAC512_TAG_10 (32'h128) +`endif +`ifndef HMAC_REG_HMAC512_TAG_11 `define HMAC_REG_HMAC512_TAG_11 (32'h12c) +`endif +`ifndef HMAC_REG_HMAC512_TAG_12 `define HMAC_REG_HMAC512_TAG_12 (32'h130) +`endif +`ifndef HMAC_REG_HMAC512_TAG_13 `define HMAC_REG_HMAC512_TAG_13 (32'h134) +`endif +`ifndef HMAC_REG_HMAC512_TAG_14 `define HMAC_REG_HMAC512_TAG_14 (32'h138) +`endif +`ifndef HMAC_REG_HMAC512_TAG_15 `define HMAC_REG_HMAC512_TAG_15 (32'h13c) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_0 `define HMAC_REG_HMAC512_LFSR_SEED_0 (32'h140) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_1 `define HMAC_REG_HMAC512_LFSR_SEED_1 (32'h144) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_2 `define HMAC_REG_HMAC512_LFSR_SEED_2 (32'h148) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_3 `define HMAC_REG_HMAC512_LFSR_SEED_3 (32'h14c) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_4 `define HMAC_REG_HMAC512_LFSR_SEED_4 (32'h150) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_5 `define HMAC_REG_HMAC512_LFSR_SEED_5 (32'h154) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_6 `define HMAC_REG_HMAC512_LFSR_SEED_6 (32'h158) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_7 `define HMAC_REG_HMAC512_LFSR_SEED_7 (32'h15c) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_8 `define HMAC_REG_HMAC512_LFSR_SEED_8 (32'h160) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_9 `define HMAC_REG_HMAC512_LFSR_SEED_9 (32'h164) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_10 `define HMAC_REG_HMAC512_LFSR_SEED_10 (32'h168) +`endif +`ifndef HMAC_REG_HMAC512_LFSR_SEED_11 `define HMAC_REG_HMAC512_LFSR_SEED_11 (32'h16c) +`endif +`ifndef HMAC_REG_HMAC512_KV_RD_KEY_CTRL `define HMAC_REG_HMAC512_KV_RD_KEY_CTRL (32'h600) `define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_LOW (0) `define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_READ_EN_MASK (32'h1) @@ -467,6 +1020,8 @@ `define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_RSVD_LOW (7) `define HMAC_REG_HMAC512_KV_RD_KEY_CTRL_RSVD_MASK (32'hffffff80) +`endif +`ifndef HMAC_REG_HMAC512_KV_RD_KEY_STATUS `define HMAC_REG_HMAC512_KV_RD_KEY_STATUS (32'h604) `define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_READY_LOW (0) `define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_READY_MASK (32'h1) @@ -474,6 +1029,8 @@ `define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_VALID_MASK (32'h2) `define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_ERROR_LOW (2) `define HMAC_REG_HMAC512_KV_RD_KEY_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL `define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL (32'h608) `define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_EN_LOW (0) `define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_READ_EN_MASK (32'h1) @@ -483,6 +1040,8 @@ `define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_RSVD_LOW (7) `define HMAC_REG_HMAC512_KV_RD_BLOCK_CTRL_RSVD_MASK (32'hffffff80) +`endif +`ifndef HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS `define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS (32'h60c) `define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_READY_LOW (0) `define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_READY_MASK (32'h1) @@ -490,6 +1049,8 @@ `define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_VALID_MASK (32'h2) `define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_ERROR_LOW (2) `define HMAC_REG_HMAC512_KV_RD_BLOCK_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef HMAC_REG_HMAC512_KV_WR_CTRL `define HMAC_REG_HMAC512_KV_WR_CTRL (32'h610) `define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_EN_LOW (0) `define HMAC_REG_HMAC512_KV_WR_CTRL_WRITE_EN_MASK (32'h1) @@ -509,6 +1070,8 @@ `define HMAC_REG_HMAC512_KV_WR_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) `define HMAC_REG_HMAC512_KV_WR_CTRL_RSVD_LOW (12) `define HMAC_REG_HMAC512_KV_WR_CTRL_RSVD_MASK (32'hfffff000) +`endif +`ifndef HMAC_REG_HMAC512_KV_WR_STATUS `define HMAC_REG_HMAC512_KV_WR_STATUS (32'h614) `define HMAC_REG_HMAC512_KV_WR_STATUS_READY_LOW (0) `define HMAC_REG_HMAC512_KV_WR_STATUS_READY_MASK (32'h1) @@ -516,11 +1079,15 @@ `define HMAC_REG_HMAC512_KV_WR_STATUS_VALID_MASK (32'h2) `define HMAC_REG_HMAC512_KV_WR_STATUS_ERROR_LOW (2) `define HMAC_REG_HMAC512_KV_WR_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define HMAC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_MODE_ERROR_EN_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_KEY_MODE_ERROR_EN_MASK (32'h1) @@ -530,15 +1097,23 @@ `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_MODE_ERROR_STS_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_KEY_MODE_ERROR_STS_MASK (32'h1) @@ -548,9 +1123,13 @@ `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_MODE_ERROR_TRIG_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_KEY_MODE_ERROR_TRIG_MASK (32'h1) @@ -560,57 +1139,137 @@ `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) `define HMAC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_R `define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_R (32'h900) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_R `define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_R (32'h904) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R `define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R `define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R `define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R `define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R (32'ha00) `define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R_PULSE_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_KEY_MODE_ERROR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R `define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R (32'ha04) `define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R_PULSE_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_KEY_ZERO_ERROR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R `define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) `define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R `define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) `define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R `define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define HMAC_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AES_REG_KEY_SHARE0_0 `define AES_REG_KEY_SHARE0_0 (32'h4) +`endif +`ifndef AES_REG_KEY_SHARE0_1 `define AES_REG_KEY_SHARE0_1 (32'h8) +`endif +`ifndef AES_REG_KEY_SHARE0_2 `define AES_REG_KEY_SHARE0_2 (32'hc) +`endif +`ifndef AES_REG_KEY_SHARE0_3 `define AES_REG_KEY_SHARE0_3 (32'h10) +`endif +`ifndef AES_REG_KEY_SHARE0_4 `define AES_REG_KEY_SHARE0_4 (32'h14) +`endif +`ifndef AES_REG_KEY_SHARE0_5 `define AES_REG_KEY_SHARE0_5 (32'h18) +`endif +`ifndef AES_REG_KEY_SHARE0_6 `define AES_REG_KEY_SHARE0_6 (32'h1c) +`endif +`ifndef AES_REG_KEY_SHARE0_7 `define AES_REG_KEY_SHARE0_7 (32'h20) +`endif +`ifndef AES_REG_KEY_SHARE1_0 `define AES_REG_KEY_SHARE1_0 (32'h24) +`endif +`ifndef AES_REG_KEY_SHARE1_1 `define AES_REG_KEY_SHARE1_1 (32'h28) +`endif +`ifndef AES_REG_KEY_SHARE1_2 `define AES_REG_KEY_SHARE1_2 (32'h2c) +`endif +`ifndef AES_REG_KEY_SHARE1_3 `define AES_REG_KEY_SHARE1_3 (32'h30) +`endif +`ifndef AES_REG_KEY_SHARE1_4 `define AES_REG_KEY_SHARE1_4 (32'h34) +`endif +`ifndef AES_REG_KEY_SHARE1_5 `define AES_REG_KEY_SHARE1_5 (32'h38) +`endif +`ifndef AES_REG_KEY_SHARE1_6 `define AES_REG_KEY_SHARE1_6 (32'h3c) +`endif +`ifndef AES_REG_KEY_SHARE1_7 `define AES_REG_KEY_SHARE1_7 (32'h40) +`endif +`ifndef AES_REG_IV_0 `define AES_REG_IV_0 (32'h44) +`endif +`ifndef AES_REG_IV_1 `define AES_REG_IV_1 (32'h48) +`endif +`ifndef AES_REG_IV_2 `define AES_REG_IV_2 (32'h4c) +`endif +`ifndef AES_REG_IV_3 `define AES_REG_IV_3 (32'h50) +`endif +`ifndef AES_REG_DATA_IN_0 `define AES_REG_DATA_IN_0 (32'h54) +`endif +`ifndef AES_REG_DATA_IN_1 `define AES_REG_DATA_IN_1 (32'h58) +`endif +`ifndef AES_REG_DATA_IN_2 `define AES_REG_DATA_IN_2 (32'h5c) +`endif +`ifndef AES_REG_DATA_IN_3 `define AES_REG_DATA_IN_3 (32'h60) +`endif +`ifndef AES_REG_DATA_OUT_0 `define AES_REG_DATA_OUT_0 (32'h64) +`endif +`ifndef AES_REG_DATA_OUT_1 `define AES_REG_DATA_OUT_1 (32'h68) +`endif +`ifndef AES_REG_DATA_OUT_2 `define AES_REG_DATA_OUT_2 (32'h6c) +`endif +`ifndef AES_REG_DATA_OUT_3 `define AES_REG_DATA_OUT_3 (32'h70) +`endif +`ifndef AES_REG_CTRL_SHADOWED `define AES_REG_CTRL_SHADOWED (32'h74) `define AES_REG_CTRL_SHADOWED_OPERATION_LOW (0) `define AES_REG_CTRL_SHADOWED_OPERATION_MASK (32'h3) @@ -624,14 +1283,20 @@ `define AES_REG_CTRL_SHADOWED_PRNG_RESEED_RATE_MASK (32'h7000) `define AES_REG_CTRL_SHADOWED_MANUAL_OPERATION_LOW (15) `define AES_REG_CTRL_SHADOWED_MANUAL_OPERATION_MASK (32'h8000) +`endif +`ifndef AES_REG_CTRL_AUX_SHADOWED `define AES_REG_CTRL_AUX_SHADOWED (32'h78) `define AES_REG_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_LOW (0) `define AES_REG_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_MASK (32'h1) `define AES_REG_CTRL_AUX_SHADOWED_FORCE_MASKS_LOW (1) `define AES_REG_CTRL_AUX_SHADOWED_FORCE_MASKS_MASK (32'h2) +`endif +`ifndef AES_REG_CTRL_AUX_REGWEN `define AES_REG_CTRL_AUX_REGWEN (32'h7c) `define AES_REG_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_LOW (0) `define AES_REG_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_MASK (32'h1) +`endif +`ifndef AES_REG_TRIGGER `define AES_REG_TRIGGER (32'h80) `define AES_REG_TRIGGER_START_LOW (0) `define AES_REG_TRIGGER_START_MASK (32'h1) @@ -641,6 +1306,8 @@ `define AES_REG_TRIGGER_DATA_OUT_CLEAR_MASK (32'h4) `define AES_REG_TRIGGER_PRNG_RESEED_LOW (3) `define AES_REG_TRIGGER_PRNG_RESEED_MASK (32'h8) +`endif +`ifndef AES_REG_STATUS `define AES_REG_STATUS (32'h84) `define AES_REG_STATUS_IDLE_LOW (0) `define AES_REG_STATUS_IDLE_MASK (32'h1) @@ -656,15 +1323,27 @@ `define AES_REG_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK (32'h20) `define AES_REG_STATUS_ALERT_FATAL_FAULT_LOW (6) `define AES_REG_STATUS_ALERT_FATAL_FAULT_MASK (32'h40) +`endif +`ifndef AES_REG_CTRL_GCM_SHADOWED `define AES_REG_CTRL_GCM_SHADOWED (32'h88) `define AES_REG_CTRL_GCM_SHADOWED_PHASE_LOW (0) `define AES_REG_CTRL_GCM_SHADOWED_PHASE_MASK (32'h3f) `define AES_REG_CTRL_GCM_SHADOWED_NUM_VALID_BYTES_LOW (6) `define AES_REG_CTRL_GCM_SHADOWED_NUM_VALID_BYTES_MASK (32'h7c0) +`endif +`ifndef AES_CLP_REG_AES_NAME_0 `define AES_CLP_REG_AES_NAME_0 (32'h100) +`endif +`ifndef AES_CLP_REG_AES_NAME_1 `define AES_CLP_REG_AES_NAME_1 (32'h104) +`endif +`ifndef AES_CLP_REG_AES_VERSION_0 `define AES_CLP_REG_AES_VERSION_0 (32'h108) +`endif +`ifndef AES_CLP_REG_AES_VERSION_1 `define AES_CLP_REG_AES_VERSION_1 (32'h10c) +`endif +`ifndef AES_CLP_REG_AES_KV_RD_KEY_CTRL `define AES_CLP_REG_AES_KV_RD_KEY_CTRL (32'h600) `define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_EN_LOW (0) `define AES_CLP_REG_AES_KV_RD_KEY_CTRL_READ_EN_MASK (32'h1) @@ -674,6 +1353,8 @@ `define AES_CLP_REG_AES_KV_RD_KEY_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define AES_CLP_REG_AES_KV_RD_KEY_CTRL_RSVD_LOW (7) `define AES_CLP_REG_AES_KV_RD_KEY_CTRL_RSVD_MASK (32'hffffff80) +`endif +`ifndef AES_CLP_REG_AES_KV_RD_KEY_STATUS `define AES_CLP_REG_AES_KV_RD_KEY_STATUS (32'h604) `define AES_CLP_REG_AES_KV_RD_KEY_STATUS_READY_LOW (0) `define AES_CLP_REG_AES_KV_RD_KEY_STATUS_READY_MASK (32'h1) @@ -681,11 +1362,15 @@ `define AES_CLP_REG_AES_KV_RD_KEY_STATUS_VALID_MASK (32'h2) `define AES_CLP_REG_AES_KV_RD_KEY_STATUS_ERROR_LOW (2) `define AES_CLP_REG_AES_KV_RD_KEY_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define AES_CLP_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) @@ -695,15 +1380,23 @@ `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) @@ -713,9 +1406,13 @@ `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) @@ -725,29 +1422,53 @@ `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R `define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AES_CLP_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef KV_REG_KEY_CTRL_0 `define KV_REG_KEY_CTRL_0 (32'h0) `define KV_REG_KEY_CTRL_0_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_0_LOCK_WR_MASK (32'h1) @@ -763,6 +1484,8 @@ `define KV_REG_KEY_CTRL_0_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_0_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_0_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_1 `define KV_REG_KEY_CTRL_1 (32'h4) `define KV_REG_KEY_CTRL_1_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_1_LOCK_WR_MASK (32'h1) @@ -778,6 +1501,8 @@ `define KV_REG_KEY_CTRL_1_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_1_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_1_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_2 `define KV_REG_KEY_CTRL_2 (32'h8) `define KV_REG_KEY_CTRL_2_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_2_LOCK_WR_MASK (32'h1) @@ -793,6 +1518,8 @@ `define KV_REG_KEY_CTRL_2_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_2_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_2_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_3 `define KV_REG_KEY_CTRL_3 (32'hc) `define KV_REG_KEY_CTRL_3_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_3_LOCK_WR_MASK (32'h1) @@ -808,6 +1535,8 @@ `define KV_REG_KEY_CTRL_3_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_3_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_3_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_4 `define KV_REG_KEY_CTRL_4 (32'h10) `define KV_REG_KEY_CTRL_4_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_4_LOCK_WR_MASK (32'h1) @@ -823,6 +1552,8 @@ `define KV_REG_KEY_CTRL_4_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_4_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_4_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_5 `define KV_REG_KEY_CTRL_5 (32'h14) `define KV_REG_KEY_CTRL_5_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_5_LOCK_WR_MASK (32'h1) @@ -838,6 +1569,8 @@ `define KV_REG_KEY_CTRL_5_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_5_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_5_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_6 `define KV_REG_KEY_CTRL_6 (32'h18) `define KV_REG_KEY_CTRL_6_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_6_LOCK_WR_MASK (32'h1) @@ -853,6 +1586,8 @@ `define KV_REG_KEY_CTRL_6_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_6_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_6_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_7 `define KV_REG_KEY_CTRL_7 (32'h1c) `define KV_REG_KEY_CTRL_7_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_7_LOCK_WR_MASK (32'h1) @@ -868,6 +1603,8 @@ `define KV_REG_KEY_CTRL_7_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_7_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_7_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_8 `define KV_REG_KEY_CTRL_8 (32'h20) `define KV_REG_KEY_CTRL_8_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_8_LOCK_WR_MASK (32'h1) @@ -883,6 +1620,8 @@ `define KV_REG_KEY_CTRL_8_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_8_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_8_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_9 `define KV_REG_KEY_CTRL_9 (32'h24) `define KV_REG_KEY_CTRL_9_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_9_LOCK_WR_MASK (32'h1) @@ -898,6 +1637,8 @@ `define KV_REG_KEY_CTRL_9_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_9_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_9_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_10 `define KV_REG_KEY_CTRL_10 (32'h28) `define KV_REG_KEY_CTRL_10_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_10_LOCK_WR_MASK (32'h1) @@ -913,6 +1654,8 @@ `define KV_REG_KEY_CTRL_10_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_10_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_10_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_11 `define KV_REG_KEY_CTRL_11 (32'h2c) `define KV_REG_KEY_CTRL_11_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_11_LOCK_WR_MASK (32'h1) @@ -928,6 +1671,8 @@ `define KV_REG_KEY_CTRL_11_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_11_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_11_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_12 `define KV_REG_KEY_CTRL_12 (32'h30) `define KV_REG_KEY_CTRL_12_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_12_LOCK_WR_MASK (32'h1) @@ -943,6 +1688,8 @@ `define KV_REG_KEY_CTRL_12_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_12_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_12_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_13 `define KV_REG_KEY_CTRL_13 (32'h34) `define KV_REG_KEY_CTRL_13_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_13_LOCK_WR_MASK (32'h1) @@ -958,6 +1705,8 @@ `define KV_REG_KEY_CTRL_13_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_13_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_13_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_14 `define KV_REG_KEY_CTRL_14 (32'h38) `define KV_REG_KEY_CTRL_14_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_14_LOCK_WR_MASK (32'h1) @@ -973,6 +1722,8 @@ `define KV_REG_KEY_CTRL_14_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_14_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_14_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_15 `define KV_REG_KEY_CTRL_15 (32'h3c) `define KV_REG_KEY_CTRL_15_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_15_LOCK_WR_MASK (32'h1) @@ -988,6 +1739,8 @@ `define KV_REG_KEY_CTRL_15_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_15_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_15_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_16 `define KV_REG_KEY_CTRL_16 (32'h40) `define KV_REG_KEY_CTRL_16_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_16_LOCK_WR_MASK (32'h1) @@ -1003,6 +1756,8 @@ `define KV_REG_KEY_CTRL_16_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_16_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_16_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_17 `define KV_REG_KEY_CTRL_17 (32'h44) `define KV_REG_KEY_CTRL_17_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_17_LOCK_WR_MASK (32'h1) @@ -1018,6 +1773,8 @@ `define KV_REG_KEY_CTRL_17_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_17_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_17_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_18 `define KV_REG_KEY_CTRL_18 (32'h48) `define KV_REG_KEY_CTRL_18_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_18_LOCK_WR_MASK (32'h1) @@ -1033,6 +1790,8 @@ `define KV_REG_KEY_CTRL_18_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_18_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_18_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_19 `define KV_REG_KEY_CTRL_19 (32'h4c) `define KV_REG_KEY_CTRL_19_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_19_LOCK_WR_MASK (32'h1) @@ -1048,6 +1807,8 @@ `define KV_REG_KEY_CTRL_19_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_19_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_19_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_20 `define KV_REG_KEY_CTRL_20 (32'h50) `define KV_REG_KEY_CTRL_20_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_20_LOCK_WR_MASK (32'h1) @@ -1063,6 +1824,8 @@ `define KV_REG_KEY_CTRL_20_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_20_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_20_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_21 `define KV_REG_KEY_CTRL_21 (32'h54) `define KV_REG_KEY_CTRL_21_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_21_LOCK_WR_MASK (32'h1) @@ -1078,6 +1841,8 @@ `define KV_REG_KEY_CTRL_21_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_21_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_21_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_22 `define KV_REG_KEY_CTRL_22 (32'h58) `define KV_REG_KEY_CTRL_22_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_22_LOCK_WR_MASK (32'h1) @@ -1093,6 +1858,8 @@ `define KV_REG_KEY_CTRL_22_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_22_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_22_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_CTRL_23 `define KV_REG_KEY_CTRL_23 (32'h5c) `define KV_REG_KEY_CTRL_23_LOCK_WR_LOW (0) `define KV_REG_KEY_CTRL_23_LOCK_WR_MASK (32'h1) @@ -1108,395 +1875,1167 @@ `define KV_REG_KEY_CTRL_23_DEST_VALID_MASK (32'h1fe00) `define KV_REG_KEY_CTRL_23_LAST_DWORD_LOW (17) `define KV_REG_KEY_CTRL_23_LAST_DWORD_MASK (32'h1e0000) +`endif +`ifndef KV_REG_KEY_ENTRY_0_0 `define KV_REG_KEY_ENTRY_0_0 (32'h600) +`endif +`ifndef KV_REG_KEY_ENTRY_0_1 `define KV_REG_KEY_ENTRY_0_1 (32'h604) +`endif +`ifndef KV_REG_KEY_ENTRY_0_2 `define KV_REG_KEY_ENTRY_0_2 (32'h608) +`endif +`ifndef KV_REG_KEY_ENTRY_0_3 `define KV_REG_KEY_ENTRY_0_3 (32'h60c) +`endif +`ifndef KV_REG_KEY_ENTRY_0_4 `define KV_REG_KEY_ENTRY_0_4 (32'h610) +`endif +`ifndef KV_REG_KEY_ENTRY_0_5 `define KV_REG_KEY_ENTRY_0_5 (32'h614) +`endif +`ifndef KV_REG_KEY_ENTRY_0_6 `define KV_REG_KEY_ENTRY_0_6 (32'h618) +`endif +`ifndef KV_REG_KEY_ENTRY_0_7 `define KV_REG_KEY_ENTRY_0_7 (32'h61c) +`endif +`ifndef KV_REG_KEY_ENTRY_0_8 `define KV_REG_KEY_ENTRY_0_8 (32'h620) +`endif +`ifndef KV_REG_KEY_ENTRY_0_9 `define KV_REG_KEY_ENTRY_0_9 (32'h624) +`endif +`ifndef KV_REG_KEY_ENTRY_0_10 `define KV_REG_KEY_ENTRY_0_10 (32'h628) +`endif +`ifndef KV_REG_KEY_ENTRY_0_11 `define KV_REG_KEY_ENTRY_0_11 (32'h62c) +`endif +`ifndef KV_REG_KEY_ENTRY_0_12 `define KV_REG_KEY_ENTRY_0_12 (32'h630) +`endif +`ifndef KV_REG_KEY_ENTRY_0_13 `define KV_REG_KEY_ENTRY_0_13 (32'h634) +`endif +`ifndef KV_REG_KEY_ENTRY_0_14 `define KV_REG_KEY_ENTRY_0_14 (32'h638) +`endif +`ifndef KV_REG_KEY_ENTRY_0_15 `define KV_REG_KEY_ENTRY_0_15 (32'h63c) +`endif +`ifndef KV_REG_KEY_ENTRY_1_0 `define KV_REG_KEY_ENTRY_1_0 (32'h640) +`endif +`ifndef KV_REG_KEY_ENTRY_1_1 `define KV_REG_KEY_ENTRY_1_1 (32'h644) +`endif +`ifndef KV_REG_KEY_ENTRY_1_2 `define KV_REG_KEY_ENTRY_1_2 (32'h648) +`endif +`ifndef KV_REG_KEY_ENTRY_1_3 `define KV_REG_KEY_ENTRY_1_3 (32'h64c) +`endif +`ifndef KV_REG_KEY_ENTRY_1_4 `define KV_REG_KEY_ENTRY_1_4 (32'h650) +`endif +`ifndef KV_REG_KEY_ENTRY_1_5 `define KV_REG_KEY_ENTRY_1_5 (32'h654) +`endif +`ifndef KV_REG_KEY_ENTRY_1_6 `define KV_REG_KEY_ENTRY_1_6 (32'h658) +`endif +`ifndef KV_REG_KEY_ENTRY_1_7 `define KV_REG_KEY_ENTRY_1_7 (32'h65c) +`endif +`ifndef KV_REG_KEY_ENTRY_1_8 `define KV_REG_KEY_ENTRY_1_8 (32'h660) +`endif +`ifndef KV_REG_KEY_ENTRY_1_9 `define KV_REG_KEY_ENTRY_1_9 (32'h664) +`endif +`ifndef KV_REG_KEY_ENTRY_1_10 `define KV_REG_KEY_ENTRY_1_10 (32'h668) +`endif +`ifndef KV_REG_KEY_ENTRY_1_11 `define KV_REG_KEY_ENTRY_1_11 (32'h66c) +`endif +`ifndef KV_REG_KEY_ENTRY_1_12 `define KV_REG_KEY_ENTRY_1_12 (32'h670) +`endif +`ifndef KV_REG_KEY_ENTRY_1_13 `define KV_REG_KEY_ENTRY_1_13 (32'h674) +`endif +`ifndef KV_REG_KEY_ENTRY_1_14 `define KV_REG_KEY_ENTRY_1_14 (32'h678) +`endif +`ifndef KV_REG_KEY_ENTRY_1_15 `define KV_REG_KEY_ENTRY_1_15 (32'h67c) +`endif +`ifndef KV_REG_KEY_ENTRY_2_0 `define KV_REG_KEY_ENTRY_2_0 (32'h680) +`endif +`ifndef KV_REG_KEY_ENTRY_2_1 `define KV_REG_KEY_ENTRY_2_1 (32'h684) +`endif +`ifndef KV_REG_KEY_ENTRY_2_2 `define KV_REG_KEY_ENTRY_2_2 (32'h688) +`endif +`ifndef KV_REG_KEY_ENTRY_2_3 `define KV_REG_KEY_ENTRY_2_3 (32'h68c) +`endif +`ifndef KV_REG_KEY_ENTRY_2_4 `define KV_REG_KEY_ENTRY_2_4 (32'h690) +`endif +`ifndef KV_REG_KEY_ENTRY_2_5 `define KV_REG_KEY_ENTRY_2_5 (32'h694) +`endif +`ifndef KV_REG_KEY_ENTRY_2_6 `define KV_REG_KEY_ENTRY_2_6 (32'h698) +`endif +`ifndef KV_REG_KEY_ENTRY_2_7 `define KV_REG_KEY_ENTRY_2_7 (32'h69c) +`endif +`ifndef KV_REG_KEY_ENTRY_2_8 `define KV_REG_KEY_ENTRY_2_8 (32'h6a0) +`endif +`ifndef KV_REG_KEY_ENTRY_2_9 `define KV_REG_KEY_ENTRY_2_9 (32'h6a4) +`endif +`ifndef KV_REG_KEY_ENTRY_2_10 `define KV_REG_KEY_ENTRY_2_10 (32'h6a8) +`endif +`ifndef KV_REG_KEY_ENTRY_2_11 `define KV_REG_KEY_ENTRY_2_11 (32'h6ac) +`endif +`ifndef KV_REG_KEY_ENTRY_2_12 `define KV_REG_KEY_ENTRY_2_12 (32'h6b0) +`endif +`ifndef KV_REG_KEY_ENTRY_2_13 `define KV_REG_KEY_ENTRY_2_13 (32'h6b4) +`endif +`ifndef KV_REG_KEY_ENTRY_2_14 `define KV_REG_KEY_ENTRY_2_14 (32'h6b8) +`endif +`ifndef KV_REG_KEY_ENTRY_2_15 `define KV_REG_KEY_ENTRY_2_15 (32'h6bc) +`endif +`ifndef KV_REG_KEY_ENTRY_3_0 `define KV_REG_KEY_ENTRY_3_0 (32'h6c0) +`endif +`ifndef KV_REG_KEY_ENTRY_3_1 `define KV_REG_KEY_ENTRY_3_1 (32'h6c4) +`endif +`ifndef KV_REG_KEY_ENTRY_3_2 `define KV_REG_KEY_ENTRY_3_2 (32'h6c8) +`endif +`ifndef KV_REG_KEY_ENTRY_3_3 `define KV_REG_KEY_ENTRY_3_3 (32'h6cc) +`endif +`ifndef KV_REG_KEY_ENTRY_3_4 `define KV_REG_KEY_ENTRY_3_4 (32'h6d0) +`endif +`ifndef KV_REG_KEY_ENTRY_3_5 `define KV_REG_KEY_ENTRY_3_5 (32'h6d4) +`endif +`ifndef KV_REG_KEY_ENTRY_3_6 `define KV_REG_KEY_ENTRY_3_6 (32'h6d8) +`endif +`ifndef KV_REG_KEY_ENTRY_3_7 `define KV_REG_KEY_ENTRY_3_7 (32'h6dc) +`endif +`ifndef KV_REG_KEY_ENTRY_3_8 `define KV_REG_KEY_ENTRY_3_8 (32'h6e0) +`endif +`ifndef KV_REG_KEY_ENTRY_3_9 `define KV_REG_KEY_ENTRY_3_9 (32'h6e4) +`endif +`ifndef KV_REG_KEY_ENTRY_3_10 `define KV_REG_KEY_ENTRY_3_10 (32'h6e8) +`endif +`ifndef KV_REG_KEY_ENTRY_3_11 `define KV_REG_KEY_ENTRY_3_11 (32'h6ec) +`endif +`ifndef KV_REG_KEY_ENTRY_3_12 `define KV_REG_KEY_ENTRY_3_12 (32'h6f0) +`endif +`ifndef KV_REG_KEY_ENTRY_3_13 `define KV_REG_KEY_ENTRY_3_13 (32'h6f4) +`endif +`ifndef KV_REG_KEY_ENTRY_3_14 `define KV_REG_KEY_ENTRY_3_14 (32'h6f8) +`endif +`ifndef KV_REG_KEY_ENTRY_3_15 `define KV_REG_KEY_ENTRY_3_15 (32'h6fc) +`endif +`ifndef KV_REG_KEY_ENTRY_4_0 `define KV_REG_KEY_ENTRY_4_0 (32'h700) +`endif +`ifndef KV_REG_KEY_ENTRY_4_1 `define KV_REG_KEY_ENTRY_4_1 (32'h704) +`endif +`ifndef KV_REG_KEY_ENTRY_4_2 `define KV_REG_KEY_ENTRY_4_2 (32'h708) +`endif +`ifndef KV_REG_KEY_ENTRY_4_3 `define KV_REG_KEY_ENTRY_4_3 (32'h70c) +`endif +`ifndef KV_REG_KEY_ENTRY_4_4 `define KV_REG_KEY_ENTRY_4_4 (32'h710) +`endif +`ifndef KV_REG_KEY_ENTRY_4_5 `define KV_REG_KEY_ENTRY_4_5 (32'h714) +`endif +`ifndef KV_REG_KEY_ENTRY_4_6 `define KV_REG_KEY_ENTRY_4_6 (32'h718) +`endif +`ifndef KV_REG_KEY_ENTRY_4_7 `define KV_REG_KEY_ENTRY_4_7 (32'h71c) +`endif +`ifndef KV_REG_KEY_ENTRY_4_8 `define KV_REG_KEY_ENTRY_4_8 (32'h720) +`endif +`ifndef KV_REG_KEY_ENTRY_4_9 `define KV_REG_KEY_ENTRY_4_9 (32'h724) +`endif +`ifndef KV_REG_KEY_ENTRY_4_10 `define KV_REG_KEY_ENTRY_4_10 (32'h728) +`endif +`ifndef KV_REG_KEY_ENTRY_4_11 `define KV_REG_KEY_ENTRY_4_11 (32'h72c) +`endif +`ifndef KV_REG_KEY_ENTRY_4_12 `define KV_REG_KEY_ENTRY_4_12 (32'h730) +`endif +`ifndef KV_REG_KEY_ENTRY_4_13 `define KV_REG_KEY_ENTRY_4_13 (32'h734) +`endif +`ifndef KV_REG_KEY_ENTRY_4_14 `define KV_REG_KEY_ENTRY_4_14 (32'h738) +`endif +`ifndef KV_REG_KEY_ENTRY_4_15 `define KV_REG_KEY_ENTRY_4_15 (32'h73c) +`endif +`ifndef KV_REG_KEY_ENTRY_5_0 `define KV_REG_KEY_ENTRY_5_0 (32'h740) +`endif +`ifndef KV_REG_KEY_ENTRY_5_1 `define KV_REG_KEY_ENTRY_5_1 (32'h744) +`endif +`ifndef KV_REG_KEY_ENTRY_5_2 `define KV_REG_KEY_ENTRY_5_2 (32'h748) +`endif +`ifndef KV_REG_KEY_ENTRY_5_3 `define KV_REG_KEY_ENTRY_5_3 (32'h74c) +`endif +`ifndef KV_REG_KEY_ENTRY_5_4 `define KV_REG_KEY_ENTRY_5_4 (32'h750) +`endif +`ifndef KV_REG_KEY_ENTRY_5_5 `define KV_REG_KEY_ENTRY_5_5 (32'h754) +`endif +`ifndef KV_REG_KEY_ENTRY_5_6 `define KV_REG_KEY_ENTRY_5_6 (32'h758) +`endif +`ifndef KV_REG_KEY_ENTRY_5_7 `define KV_REG_KEY_ENTRY_5_7 (32'h75c) +`endif +`ifndef KV_REG_KEY_ENTRY_5_8 `define KV_REG_KEY_ENTRY_5_8 (32'h760) +`endif +`ifndef KV_REG_KEY_ENTRY_5_9 `define KV_REG_KEY_ENTRY_5_9 (32'h764) +`endif +`ifndef KV_REG_KEY_ENTRY_5_10 `define KV_REG_KEY_ENTRY_5_10 (32'h768) +`endif +`ifndef KV_REG_KEY_ENTRY_5_11 `define KV_REG_KEY_ENTRY_5_11 (32'h76c) +`endif +`ifndef KV_REG_KEY_ENTRY_5_12 `define KV_REG_KEY_ENTRY_5_12 (32'h770) +`endif +`ifndef KV_REG_KEY_ENTRY_5_13 `define KV_REG_KEY_ENTRY_5_13 (32'h774) +`endif +`ifndef KV_REG_KEY_ENTRY_5_14 `define KV_REG_KEY_ENTRY_5_14 (32'h778) +`endif +`ifndef KV_REG_KEY_ENTRY_5_15 `define KV_REG_KEY_ENTRY_5_15 (32'h77c) +`endif +`ifndef KV_REG_KEY_ENTRY_6_0 `define KV_REG_KEY_ENTRY_6_0 (32'h780) +`endif +`ifndef KV_REG_KEY_ENTRY_6_1 `define KV_REG_KEY_ENTRY_6_1 (32'h784) +`endif +`ifndef KV_REG_KEY_ENTRY_6_2 `define KV_REG_KEY_ENTRY_6_2 (32'h788) +`endif +`ifndef KV_REG_KEY_ENTRY_6_3 `define KV_REG_KEY_ENTRY_6_3 (32'h78c) +`endif +`ifndef KV_REG_KEY_ENTRY_6_4 `define KV_REG_KEY_ENTRY_6_4 (32'h790) +`endif +`ifndef KV_REG_KEY_ENTRY_6_5 `define KV_REG_KEY_ENTRY_6_5 (32'h794) +`endif +`ifndef KV_REG_KEY_ENTRY_6_6 `define KV_REG_KEY_ENTRY_6_6 (32'h798) +`endif +`ifndef KV_REG_KEY_ENTRY_6_7 `define KV_REG_KEY_ENTRY_6_7 (32'h79c) +`endif +`ifndef KV_REG_KEY_ENTRY_6_8 `define KV_REG_KEY_ENTRY_6_8 (32'h7a0) +`endif +`ifndef KV_REG_KEY_ENTRY_6_9 `define KV_REG_KEY_ENTRY_6_9 (32'h7a4) +`endif +`ifndef KV_REG_KEY_ENTRY_6_10 `define KV_REG_KEY_ENTRY_6_10 (32'h7a8) +`endif +`ifndef KV_REG_KEY_ENTRY_6_11 `define KV_REG_KEY_ENTRY_6_11 (32'h7ac) +`endif +`ifndef KV_REG_KEY_ENTRY_6_12 `define KV_REG_KEY_ENTRY_6_12 (32'h7b0) +`endif +`ifndef KV_REG_KEY_ENTRY_6_13 `define KV_REG_KEY_ENTRY_6_13 (32'h7b4) +`endif +`ifndef KV_REG_KEY_ENTRY_6_14 `define KV_REG_KEY_ENTRY_6_14 (32'h7b8) +`endif +`ifndef KV_REG_KEY_ENTRY_6_15 `define KV_REG_KEY_ENTRY_6_15 (32'h7bc) +`endif +`ifndef KV_REG_KEY_ENTRY_7_0 `define KV_REG_KEY_ENTRY_7_0 (32'h7c0) +`endif +`ifndef KV_REG_KEY_ENTRY_7_1 `define KV_REG_KEY_ENTRY_7_1 (32'h7c4) +`endif +`ifndef KV_REG_KEY_ENTRY_7_2 `define KV_REG_KEY_ENTRY_7_2 (32'h7c8) +`endif +`ifndef KV_REG_KEY_ENTRY_7_3 `define KV_REG_KEY_ENTRY_7_3 (32'h7cc) +`endif +`ifndef KV_REG_KEY_ENTRY_7_4 `define KV_REG_KEY_ENTRY_7_4 (32'h7d0) +`endif +`ifndef KV_REG_KEY_ENTRY_7_5 `define KV_REG_KEY_ENTRY_7_5 (32'h7d4) +`endif +`ifndef KV_REG_KEY_ENTRY_7_6 `define KV_REG_KEY_ENTRY_7_6 (32'h7d8) +`endif +`ifndef KV_REG_KEY_ENTRY_7_7 `define KV_REG_KEY_ENTRY_7_7 (32'h7dc) +`endif +`ifndef KV_REG_KEY_ENTRY_7_8 `define KV_REG_KEY_ENTRY_7_8 (32'h7e0) +`endif +`ifndef KV_REG_KEY_ENTRY_7_9 `define KV_REG_KEY_ENTRY_7_9 (32'h7e4) +`endif +`ifndef KV_REG_KEY_ENTRY_7_10 `define KV_REG_KEY_ENTRY_7_10 (32'h7e8) +`endif +`ifndef KV_REG_KEY_ENTRY_7_11 `define KV_REG_KEY_ENTRY_7_11 (32'h7ec) +`endif +`ifndef KV_REG_KEY_ENTRY_7_12 `define KV_REG_KEY_ENTRY_7_12 (32'h7f0) +`endif +`ifndef KV_REG_KEY_ENTRY_7_13 `define KV_REG_KEY_ENTRY_7_13 (32'h7f4) +`endif +`ifndef KV_REG_KEY_ENTRY_7_14 `define KV_REG_KEY_ENTRY_7_14 (32'h7f8) +`endif +`ifndef KV_REG_KEY_ENTRY_7_15 `define KV_REG_KEY_ENTRY_7_15 (32'h7fc) +`endif +`ifndef KV_REG_KEY_ENTRY_8_0 `define KV_REG_KEY_ENTRY_8_0 (32'h800) +`endif +`ifndef KV_REG_KEY_ENTRY_8_1 `define KV_REG_KEY_ENTRY_8_1 (32'h804) +`endif +`ifndef KV_REG_KEY_ENTRY_8_2 `define KV_REG_KEY_ENTRY_8_2 (32'h808) +`endif +`ifndef KV_REG_KEY_ENTRY_8_3 `define KV_REG_KEY_ENTRY_8_3 (32'h80c) +`endif +`ifndef KV_REG_KEY_ENTRY_8_4 `define KV_REG_KEY_ENTRY_8_4 (32'h810) +`endif +`ifndef KV_REG_KEY_ENTRY_8_5 `define KV_REG_KEY_ENTRY_8_5 (32'h814) +`endif +`ifndef KV_REG_KEY_ENTRY_8_6 `define KV_REG_KEY_ENTRY_8_6 (32'h818) +`endif +`ifndef KV_REG_KEY_ENTRY_8_7 `define KV_REG_KEY_ENTRY_8_7 (32'h81c) +`endif +`ifndef KV_REG_KEY_ENTRY_8_8 `define KV_REG_KEY_ENTRY_8_8 (32'h820) +`endif +`ifndef KV_REG_KEY_ENTRY_8_9 `define KV_REG_KEY_ENTRY_8_9 (32'h824) +`endif +`ifndef KV_REG_KEY_ENTRY_8_10 `define KV_REG_KEY_ENTRY_8_10 (32'h828) +`endif +`ifndef KV_REG_KEY_ENTRY_8_11 `define KV_REG_KEY_ENTRY_8_11 (32'h82c) +`endif +`ifndef KV_REG_KEY_ENTRY_8_12 `define KV_REG_KEY_ENTRY_8_12 (32'h830) +`endif +`ifndef KV_REG_KEY_ENTRY_8_13 `define KV_REG_KEY_ENTRY_8_13 (32'h834) +`endif +`ifndef KV_REG_KEY_ENTRY_8_14 `define KV_REG_KEY_ENTRY_8_14 (32'h838) +`endif +`ifndef KV_REG_KEY_ENTRY_8_15 `define KV_REG_KEY_ENTRY_8_15 (32'h83c) +`endif +`ifndef KV_REG_KEY_ENTRY_9_0 `define KV_REG_KEY_ENTRY_9_0 (32'h840) +`endif +`ifndef KV_REG_KEY_ENTRY_9_1 `define KV_REG_KEY_ENTRY_9_1 (32'h844) +`endif +`ifndef KV_REG_KEY_ENTRY_9_2 `define KV_REG_KEY_ENTRY_9_2 (32'h848) +`endif +`ifndef KV_REG_KEY_ENTRY_9_3 `define KV_REG_KEY_ENTRY_9_3 (32'h84c) +`endif +`ifndef KV_REG_KEY_ENTRY_9_4 `define KV_REG_KEY_ENTRY_9_4 (32'h850) +`endif +`ifndef KV_REG_KEY_ENTRY_9_5 `define KV_REG_KEY_ENTRY_9_5 (32'h854) +`endif +`ifndef KV_REG_KEY_ENTRY_9_6 `define KV_REG_KEY_ENTRY_9_6 (32'h858) +`endif +`ifndef KV_REG_KEY_ENTRY_9_7 `define KV_REG_KEY_ENTRY_9_7 (32'h85c) +`endif +`ifndef KV_REG_KEY_ENTRY_9_8 `define KV_REG_KEY_ENTRY_9_8 (32'h860) +`endif +`ifndef KV_REG_KEY_ENTRY_9_9 `define KV_REG_KEY_ENTRY_9_9 (32'h864) +`endif +`ifndef KV_REG_KEY_ENTRY_9_10 `define KV_REG_KEY_ENTRY_9_10 (32'h868) +`endif +`ifndef KV_REG_KEY_ENTRY_9_11 `define KV_REG_KEY_ENTRY_9_11 (32'h86c) +`endif +`ifndef KV_REG_KEY_ENTRY_9_12 `define KV_REG_KEY_ENTRY_9_12 (32'h870) +`endif +`ifndef KV_REG_KEY_ENTRY_9_13 `define KV_REG_KEY_ENTRY_9_13 (32'h874) +`endif +`ifndef KV_REG_KEY_ENTRY_9_14 `define KV_REG_KEY_ENTRY_9_14 (32'h878) +`endif +`ifndef KV_REG_KEY_ENTRY_9_15 `define KV_REG_KEY_ENTRY_9_15 (32'h87c) +`endif +`ifndef KV_REG_KEY_ENTRY_10_0 `define KV_REG_KEY_ENTRY_10_0 (32'h880) +`endif +`ifndef KV_REG_KEY_ENTRY_10_1 `define KV_REG_KEY_ENTRY_10_1 (32'h884) +`endif +`ifndef KV_REG_KEY_ENTRY_10_2 `define KV_REG_KEY_ENTRY_10_2 (32'h888) +`endif +`ifndef KV_REG_KEY_ENTRY_10_3 `define KV_REG_KEY_ENTRY_10_3 (32'h88c) +`endif +`ifndef KV_REG_KEY_ENTRY_10_4 `define KV_REG_KEY_ENTRY_10_4 (32'h890) +`endif +`ifndef KV_REG_KEY_ENTRY_10_5 `define KV_REG_KEY_ENTRY_10_5 (32'h894) +`endif +`ifndef KV_REG_KEY_ENTRY_10_6 `define KV_REG_KEY_ENTRY_10_6 (32'h898) +`endif +`ifndef KV_REG_KEY_ENTRY_10_7 `define KV_REG_KEY_ENTRY_10_7 (32'h89c) +`endif +`ifndef KV_REG_KEY_ENTRY_10_8 `define KV_REG_KEY_ENTRY_10_8 (32'h8a0) +`endif +`ifndef KV_REG_KEY_ENTRY_10_9 `define KV_REG_KEY_ENTRY_10_9 (32'h8a4) +`endif +`ifndef KV_REG_KEY_ENTRY_10_10 `define KV_REG_KEY_ENTRY_10_10 (32'h8a8) +`endif +`ifndef KV_REG_KEY_ENTRY_10_11 `define KV_REG_KEY_ENTRY_10_11 (32'h8ac) +`endif +`ifndef KV_REG_KEY_ENTRY_10_12 `define KV_REG_KEY_ENTRY_10_12 (32'h8b0) +`endif +`ifndef KV_REG_KEY_ENTRY_10_13 `define KV_REG_KEY_ENTRY_10_13 (32'h8b4) +`endif +`ifndef KV_REG_KEY_ENTRY_10_14 `define KV_REG_KEY_ENTRY_10_14 (32'h8b8) +`endif +`ifndef KV_REG_KEY_ENTRY_10_15 `define KV_REG_KEY_ENTRY_10_15 (32'h8bc) +`endif +`ifndef KV_REG_KEY_ENTRY_11_0 `define KV_REG_KEY_ENTRY_11_0 (32'h8c0) +`endif +`ifndef KV_REG_KEY_ENTRY_11_1 `define KV_REG_KEY_ENTRY_11_1 (32'h8c4) +`endif +`ifndef KV_REG_KEY_ENTRY_11_2 `define KV_REG_KEY_ENTRY_11_2 (32'h8c8) +`endif +`ifndef KV_REG_KEY_ENTRY_11_3 `define KV_REG_KEY_ENTRY_11_3 (32'h8cc) +`endif +`ifndef KV_REG_KEY_ENTRY_11_4 `define KV_REG_KEY_ENTRY_11_4 (32'h8d0) +`endif +`ifndef KV_REG_KEY_ENTRY_11_5 `define KV_REG_KEY_ENTRY_11_5 (32'h8d4) +`endif +`ifndef KV_REG_KEY_ENTRY_11_6 `define KV_REG_KEY_ENTRY_11_6 (32'h8d8) +`endif +`ifndef KV_REG_KEY_ENTRY_11_7 `define KV_REG_KEY_ENTRY_11_7 (32'h8dc) +`endif +`ifndef KV_REG_KEY_ENTRY_11_8 `define KV_REG_KEY_ENTRY_11_8 (32'h8e0) +`endif +`ifndef KV_REG_KEY_ENTRY_11_9 `define KV_REG_KEY_ENTRY_11_9 (32'h8e4) +`endif +`ifndef KV_REG_KEY_ENTRY_11_10 `define KV_REG_KEY_ENTRY_11_10 (32'h8e8) +`endif +`ifndef KV_REG_KEY_ENTRY_11_11 `define KV_REG_KEY_ENTRY_11_11 (32'h8ec) +`endif +`ifndef KV_REG_KEY_ENTRY_11_12 `define KV_REG_KEY_ENTRY_11_12 (32'h8f0) +`endif +`ifndef KV_REG_KEY_ENTRY_11_13 `define KV_REG_KEY_ENTRY_11_13 (32'h8f4) +`endif +`ifndef KV_REG_KEY_ENTRY_11_14 `define KV_REG_KEY_ENTRY_11_14 (32'h8f8) +`endif +`ifndef KV_REG_KEY_ENTRY_11_15 `define KV_REG_KEY_ENTRY_11_15 (32'h8fc) +`endif +`ifndef KV_REG_KEY_ENTRY_12_0 `define KV_REG_KEY_ENTRY_12_0 (32'h900) +`endif +`ifndef KV_REG_KEY_ENTRY_12_1 `define KV_REG_KEY_ENTRY_12_1 (32'h904) +`endif +`ifndef KV_REG_KEY_ENTRY_12_2 `define KV_REG_KEY_ENTRY_12_2 (32'h908) +`endif +`ifndef KV_REG_KEY_ENTRY_12_3 `define KV_REG_KEY_ENTRY_12_3 (32'h90c) +`endif +`ifndef KV_REG_KEY_ENTRY_12_4 `define KV_REG_KEY_ENTRY_12_4 (32'h910) +`endif +`ifndef KV_REG_KEY_ENTRY_12_5 `define KV_REG_KEY_ENTRY_12_5 (32'h914) +`endif +`ifndef KV_REG_KEY_ENTRY_12_6 `define KV_REG_KEY_ENTRY_12_6 (32'h918) +`endif +`ifndef KV_REG_KEY_ENTRY_12_7 `define KV_REG_KEY_ENTRY_12_7 (32'h91c) +`endif +`ifndef KV_REG_KEY_ENTRY_12_8 `define KV_REG_KEY_ENTRY_12_8 (32'h920) +`endif +`ifndef KV_REG_KEY_ENTRY_12_9 `define KV_REG_KEY_ENTRY_12_9 (32'h924) +`endif +`ifndef KV_REG_KEY_ENTRY_12_10 `define KV_REG_KEY_ENTRY_12_10 (32'h928) +`endif +`ifndef KV_REG_KEY_ENTRY_12_11 `define KV_REG_KEY_ENTRY_12_11 (32'h92c) +`endif +`ifndef KV_REG_KEY_ENTRY_12_12 `define KV_REG_KEY_ENTRY_12_12 (32'h930) +`endif +`ifndef KV_REG_KEY_ENTRY_12_13 `define KV_REG_KEY_ENTRY_12_13 (32'h934) +`endif +`ifndef KV_REG_KEY_ENTRY_12_14 `define KV_REG_KEY_ENTRY_12_14 (32'h938) +`endif +`ifndef KV_REG_KEY_ENTRY_12_15 `define KV_REG_KEY_ENTRY_12_15 (32'h93c) +`endif +`ifndef KV_REG_KEY_ENTRY_13_0 `define KV_REG_KEY_ENTRY_13_0 (32'h940) +`endif +`ifndef KV_REG_KEY_ENTRY_13_1 `define KV_REG_KEY_ENTRY_13_1 (32'h944) +`endif +`ifndef KV_REG_KEY_ENTRY_13_2 `define KV_REG_KEY_ENTRY_13_2 (32'h948) +`endif +`ifndef KV_REG_KEY_ENTRY_13_3 `define KV_REG_KEY_ENTRY_13_3 (32'h94c) +`endif +`ifndef KV_REG_KEY_ENTRY_13_4 `define KV_REG_KEY_ENTRY_13_4 (32'h950) +`endif +`ifndef KV_REG_KEY_ENTRY_13_5 `define KV_REG_KEY_ENTRY_13_5 (32'h954) +`endif +`ifndef KV_REG_KEY_ENTRY_13_6 `define KV_REG_KEY_ENTRY_13_6 (32'h958) +`endif +`ifndef KV_REG_KEY_ENTRY_13_7 `define KV_REG_KEY_ENTRY_13_7 (32'h95c) +`endif +`ifndef KV_REG_KEY_ENTRY_13_8 `define KV_REG_KEY_ENTRY_13_8 (32'h960) +`endif +`ifndef KV_REG_KEY_ENTRY_13_9 `define KV_REG_KEY_ENTRY_13_9 (32'h964) +`endif +`ifndef KV_REG_KEY_ENTRY_13_10 `define KV_REG_KEY_ENTRY_13_10 (32'h968) +`endif +`ifndef KV_REG_KEY_ENTRY_13_11 `define KV_REG_KEY_ENTRY_13_11 (32'h96c) +`endif +`ifndef KV_REG_KEY_ENTRY_13_12 `define KV_REG_KEY_ENTRY_13_12 (32'h970) +`endif +`ifndef KV_REG_KEY_ENTRY_13_13 `define KV_REG_KEY_ENTRY_13_13 (32'h974) +`endif +`ifndef KV_REG_KEY_ENTRY_13_14 `define KV_REG_KEY_ENTRY_13_14 (32'h978) +`endif +`ifndef KV_REG_KEY_ENTRY_13_15 `define KV_REG_KEY_ENTRY_13_15 (32'h97c) +`endif +`ifndef KV_REG_KEY_ENTRY_14_0 `define KV_REG_KEY_ENTRY_14_0 (32'h980) +`endif +`ifndef KV_REG_KEY_ENTRY_14_1 `define KV_REG_KEY_ENTRY_14_1 (32'h984) +`endif +`ifndef KV_REG_KEY_ENTRY_14_2 `define KV_REG_KEY_ENTRY_14_2 (32'h988) +`endif +`ifndef KV_REG_KEY_ENTRY_14_3 `define KV_REG_KEY_ENTRY_14_3 (32'h98c) +`endif +`ifndef KV_REG_KEY_ENTRY_14_4 `define KV_REG_KEY_ENTRY_14_4 (32'h990) +`endif +`ifndef KV_REG_KEY_ENTRY_14_5 `define KV_REG_KEY_ENTRY_14_5 (32'h994) +`endif +`ifndef KV_REG_KEY_ENTRY_14_6 `define KV_REG_KEY_ENTRY_14_6 (32'h998) +`endif +`ifndef KV_REG_KEY_ENTRY_14_7 `define KV_REG_KEY_ENTRY_14_7 (32'h99c) +`endif +`ifndef KV_REG_KEY_ENTRY_14_8 `define KV_REG_KEY_ENTRY_14_8 (32'h9a0) +`endif +`ifndef KV_REG_KEY_ENTRY_14_9 `define KV_REG_KEY_ENTRY_14_9 (32'h9a4) +`endif +`ifndef KV_REG_KEY_ENTRY_14_10 `define KV_REG_KEY_ENTRY_14_10 (32'h9a8) +`endif +`ifndef KV_REG_KEY_ENTRY_14_11 `define KV_REG_KEY_ENTRY_14_11 (32'h9ac) +`endif +`ifndef KV_REG_KEY_ENTRY_14_12 `define KV_REG_KEY_ENTRY_14_12 (32'h9b0) +`endif +`ifndef KV_REG_KEY_ENTRY_14_13 `define KV_REG_KEY_ENTRY_14_13 (32'h9b4) +`endif +`ifndef KV_REG_KEY_ENTRY_14_14 `define KV_REG_KEY_ENTRY_14_14 (32'h9b8) +`endif +`ifndef KV_REG_KEY_ENTRY_14_15 `define KV_REG_KEY_ENTRY_14_15 (32'h9bc) +`endif +`ifndef KV_REG_KEY_ENTRY_15_0 `define KV_REG_KEY_ENTRY_15_0 (32'h9c0) +`endif +`ifndef KV_REG_KEY_ENTRY_15_1 `define KV_REG_KEY_ENTRY_15_1 (32'h9c4) +`endif +`ifndef KV_REG_KEY_ENTRY_15_2 `define KV_REG_KEY_ENTRY_15_2 (32'h9c8) +`endif +`ifndef KV_REG_KEY_ENTRY_15_3 `define KV_REG_KEY_ENTRY_15_3 (32'h9cc) +`endif +`ifndef KV_REG_KEY_ENTRY_15_4 `define KV_REG_KEY_ENTRY_15_4 (32'h9d0) +`endif +`ifndef KV_REG_KEY_ENTRY_15_5 `define KV_REG_KEY_ENTRY_15_5 (32'h9d4) +`endif +`ifndef KV_REG_KEY_ENTRY_15_6 `define KV_REG_KEY_ENTRY_15_6 (32'h9d8) +`endif +`ifndef KV_REG_KEY_ENTRY_15_7 `define KV_REG_KEY_ENTRY_15_7 (32'h9dc) +`endif +`ifndef KV_REG_KEY_ENTRY_15_8 `define KV_REG_KEY_ENTRY_15_8 (32'h9e0) +`endif +`ifndef KV_REG_KEY_ENTRY_15_9 `define KV_REG_KEY_ENTRY_15_9 (32'h9e4) +`endif +`ifndef KV_REG_KEY_ENTRY_15_10 `define KV_REG_KEY_ENTRY_15_10 (32'h9e8) +`endif +`ifndef KV_REG_KEY_ENTRY_15_11 `define KV_REG_KEY_ENTRY_15_11 (32'h9ec) +`endif +`ifndef KV_REG_KEY_ENTRY_15_12 `define KV_REG_KEY_ENTRY_15_12 (32'h9f0) +`endif +`ifndef KV_REG_KEY_ENTRY_15_13 `define KV_REG_KEY_ENTRY_15_13 (32'h9f4) +`endif +`ifndef KV_REG_KEY_ENTRY_15_14 `define KV_REG_KEY_ENTRY_15_14 (32'h9f8) +`endif +`ifndef KV_REG_KEY_ENTRY_15_15 `define KV_REG_KEY_ENTRY_15_15 (32'h9fc) +`endif +`ifndef KV_REG_KEY_ENTRY_16_0 `define KV_REG_KEY_ENTRY_16_0 (32'ha00) +`endif +`ifndef KV_REG_KEY_ENTRY_16_1 `define KV_REG_KEY_ENTRY_16_1 (32'ha04) +`endif +`ifndef KV_REG_KEY_ENTRY_16_2 `define KV_REG_KEY_ENTRY_16_2 (32'ha08) +`endif +`ifndef KV_REG_KEY_ENTRY_16_3 `define KV_REG_KEY_ENTRY_16_3 (32'ha0c) +`endif +`ifndef KV_REG_KEY_ENTRY_16_4 `define KV_REG_KEY_ENTRY_16_4 (32'ha10) +`endif +`ifndef KV_REG_KEY_ENTRY_16_5 `define KV_REG_KEY_ENTRY_16_5 (32'ha14) +`endif +`ifndef KV_REG_KEY_ENTRY_16_6 `define KV_REG_KEY_ENTRY_16_6 (32'ha18) +`endif +`ifndef KV_REG_KEY_ENTRY_16_7 `define KV_REG_KEY_ENTRY_16_7 (32'ha1c) +`endif +`ifndef KV_REG_KEY_ENTRY_16_8 `define KV_REG_KEY_ENTRY_16_8 (32'ha20) +`endif +`ifndef KV_REG_KEY_ENTRY_16_9 `define KV_REG_KEY_ENTRY_16_9 (32'ha24) +`endif +`ifndef KV_REG_KEY_ENTRY_16_10 `define KV_REG_KEY_ENTRY_16_10 (32'ha28) +`endif +`ifndef KV_REG_KEY_ENTRY_16_11 `define KV_REG_KEY_ENTRY_16_11 (32'ha2c) +`endif +`ifndef KV_REG_KEY_ENTRY_16_12 `define KV_REG_KEY_ENTRY_16_12 (32'ha30) +`endif +`ifndef KV_REG_KEY_ENTRY_16_13 `define KV_REG_KEY_ENTRY_16_13 (32'ha34) +`endif +`ifndef KV_REG_KEY_ENTRY_16_14 `define KV_REG_KEY_ENTRY_16_14 (32'ha38) +`endif +`ifndef KV_REG_KEY_ENTRY_16_15 `define KV_REG_KEY_ENTRY_16_15 (32'ha3c) +`endif +`ifndef KV_REG_KEY_ENTRY_17_0 `define KV_REG_KEY_ENTRY_17_0 (32'ha40) +`endif +`ifndef KV_REG_KEY_ENTRY_17_1 `define KV_REG_KEY_ENTRY_17_1 (32'ha44) +`endif +`ifndef KV_REG_KEY_ENTRY_17_2 `define KV_REG_KEY_ENTRY_17_2 (32'ha48) +`endif +`ifndef KV_REG_KEY_ENTRY_17_3 `define KV_REG_KEY_ENTRY_17_3 (32'ha4c) +`endif +`ifndef KV_REG_KEY_ENTRY_17_4 `define KV_REG_KEY_ENTRY_17_4 (32'ha50) +`endif +`ifndef KV_REG_KEY_ENTRY_17_5 `define KV_REG_KEY_ENTRY_17_5 (32'ha54) +`endif +`ifndef KV_REG_KEY_ENTRY_17_6 `define KV_REG_KEY_ENTRY_17_6 (32'ha58) +`endif +`ifndef KV_REG_KEY_ENTRY_17_7 `define KV_REG_KEY_ENTRY_17_7 (32'ha5c) +`endif +`ifndef KV_REG_KEY_ENTRY_17_8 `define KV_REG_KEY_ENTRY_17_8 (32'ha60) +`endif +`ifndef KV_REG_KEY_ENTRY_17_9 `define KV_REG_KEY_ENTRY_17_9 (32'ha64) +`endif +`ifndef KV_REG_KEY_ENTRY_17_10 `define KV_REG_KEY_ENTRY_17_10 (32'ha68) +`endif +`ifndef KV_REG_KEY_ENTRY_17_11 `define KV_REG_KEY_ENTRY_17_11 (32'ha6c) +`endif +`ifndef KV_REG_KEY_ENTRY_17_12 `define KV_REG_KEY_ENTRY_17_12 (32'ha70) +`endif +`ifndef KV_REG_KEY_ENTRY_17_13 `define KV_REG_KEY_ENTRY_17_13 (32'ha74) +`endif +`ifndef KV_REG_KEY_ENTRY_17_14 `define KV_REG_KEY_ENTRY_17_14 (32'ha78) +`endif +`ifndef KV_REG_KEY_ENTRY_17_15 `define KV_REG_KEY_ENTRY_17_15 (32'ha7c) +`endif +`ifndef KV_REG_KEY_ENTRY_18_0 `define KV_REG_KEY_ENTRY_18_0 (32'ha80) +`endif +`ifndef KV_REG_KEY_ENTRY_18_1 `define KV_REG_KEY_ENTRY_18_1 (32'ha84) +`endif +`ifndef KV_REG_KEY_ENTRY_18_2 `define KV_REG_KEY_ENTRY_18_2 (32'ha88) +`endif +`ifndef KV_REG_KEY_ENTRY_18_3 `define KV_REG_KEY_ENTRY_18_3 (32'ha8c) +`endif +`ifndef KV_REG_KEY_ENTRY_18_4 `define KV_REG_KEY_ENTRY_18_4 (32'ha90) +`endif +`ifndef KV_REG_KEY_ENTRY_18_5 `define KV_REG_KEY_ENTRY_18_5 (32'ha94) +`endif +`ifndef KV_REG_KEY_ENTRY_18_6 `define KV_REG_KEY_ENTRY_18_6 (32'ha98) +`endif +`ifndef KV_REG_KEY_ENTRY_18_7 `define KV_REG_KEY_ENTRY_18_7 (32'ha9c) +`endif +`ifndef KV_REG_KEY_ENTRY_18_8 `define KV_REG_KEY_ENTRY_18_8 (32'haa0) +`endif +`ifndef KV_REG_KEY_ENTRY_18_9 `define KV_REG_KEY_ENTRY_18_9 (32'haa4) +`endif +`ifndef KV_REG_KEY_ENTRY_18_10 `define KV_REG_KEY_ENTRY_18_10 (32'haa8) +`endif +`ifndef KV_REG_KEY_ENTRY_18_11 `define KV_REG_KEY_ENTRY_18_11 (32'haac) +`endif +`ifndef KV_REG_KEY_ENTRY_18_12 `define KV_REG_KEY_ENTRY_18_12 (32'hab0) +`endif +`ifndef KV_REG_KEY_ENTRY_18_13 `define KV_REG_KEY_ENTRY_18_13 (32'hab4) +`endif +`ifndef KV_REG_KEY_ENTRY_18_14 `define KV_REG_KEY_ENTRY_18_14 (32'hab8) +`endif +`ifndef KV_REG_KEY_ENTRY_18_15 `define KV_REG_KEY_ENTRY_18_15 (32'habc) +`endif +`ifndef KV_REG_KEY_ENTRY_19_0 `define KV_REG_KEY_ENTRY_19_0 (32'hac0) +`endif +`ifndef KV_REG_KEY_ENTRY_19_1 `define KV_REG_KEY_ENTRY_19_1 (32'hac4) +`endif +`ifndef KV_REG_KEY_ENTRY_19_2 `define KV_REG_KEY_ENTRY_19_2 (32'hac8) +`endif +`ifndef KV_REG_KEY_ENTRY_19_3 `define KV_REG_KEY_ENTRY_19_3 (32'hacc) +`endif +`ifndef KV_REG_KEY_ENTRY_19_4 `define KV_REG_KEY_ENTRY_19_4 (32'had0) +`endif +`ifndef KV_REG_KEY_ENTRY_19_5 `define KV_REG_KEY_ENTRY_19_5 (32'had4) +`endif +`ifndef KV_REG_KEY_ENTRY_19_6 `define KV_REG_KEY_ENTRY_19_6 (32'had8) +`endif +`ifndef KV_REG_KEY_ENTRY_19_7 `define KV_REG_KEY_ENTRY_19_7 (32'hadc) +`endif +`ifndef KV_REG_KEY_ENTRY_19_8 `define KV_REG_KEY_ENTRY_19_8 (32'hae0) +`endif +`ifndef KV_REG_KEY_ENTRY_19_9 `define KV_REG_KEY_ENTRY_19_9 (32'hae4) +`endif +`ifndef KV_REG_KEY_ENTRY_19_10 `define KV_REG_KEY_ENTRY_19_10 (32'hae8) +`endif +`ifndef KV_REG_KEY_ENTRY_19_11 `define KV_REG_KEY_ENTRY_19_11 (32'haec) +`endif +`ifndef KV_REG_KEY_ENTRY_19_12 `define KV_REG_KEY_ENTRY_19_12 (32'haf0) +`endif +`ifndef KV_REG_KEY_ENTRY_19_13 `define KV_REG_KEY_ENTRY_19_13 (32'haf4) +`endif +`ifndef KV_REG_KEY_ENTRY_19_14 `define KV_REG_KEY_ENTRY_19_14 (32'haf8) +`endif +`ifndef KV_REG_KEY_ENTRY_19_15 `define KV_REG_KEY_ENTRY_19_15 (32'hafc) +`endif +`ifndef KV_REG_KEY_ENTRY_20_0 `define KV_REG_KEY_ENTRY_20_0 (32'hb00) +`endif +`ifndef KV_REG_KEY_ENTRY_20_1 `define KV_REG_KEY_ENTRY_20_1 (32'hb04) +`endif +`ifndef KV_REG_KEY_ENTRY_20_2 `define KV_REG_KEY_ENTRY_20_2 (32'hb08) +`endif +`ifndef KV_REG_KEY_ENTRY_20_3 `define KV_REG_KEY_ENTRY_20_3 (32'hb0c) +`endif +`ifndef KV_REG_KEY_ENTRY_20_4 `define KV_REG_KEY_ENTRY_20_4 (32'hb10) +`endif +`ifndef KV_REG_KEY_ENTRY_20_5 `define KV_REG_KEY_ENTRY_20_5 (32'hb14) +`endif +`ifndef KV_REG_KEY_ENTRY_20_6 `define KV_REG_KEY_ENTRY_20_6 (32'hb18) +`endif +`ifndef KV_REG_KEY_ENTRY_20_7 `define KV_REG_KEY_ENTRY_20_7 (32'hb1c) +`endif +`ifndef KV_REG_KEY_ENTRY_20_8 `define KV_REG_KEY_ENTRY_20_8 (32'hb20) +`endif +`ifndef KV_REG_KEY_ENTRY_20_9 `define KV_REG_KEY_ENTRY_20_9 (32'hb24) +`endif +`ifndef KV_REG_KEY_ENTRY_20_10 `define KV_REG_KEY_ENTRY_20_10 (32'hb28) +`endif +`ifndef KV_REG_KEY_ENTRY_20_11 `define KV_REG_KEY_ENTRY_20_11 (32'hb2c) +`endif +`ifndef KV_REG_KEY_ENTRY_20_12 `define KV_REG_KEY_ENTRY_20_12 (32'hb30) +`endif +`ifndef KV_REG_KEY_ENTRY_20_13 `define KV_REG_KEY_ENTRY_20_13 (32'hb34) +`endif +`ifndef KV_REG_KEY_ENTRY_20_14 `define KV_REG_KEY_ENTRY_20_14 (32'hb38) +`endif +`ifndef KV_REG_KEY_ENTRY_20_15 `define KV_REG_KEY_ENTRY_20_15 (32'hb3c) +`endif +`ifndef KV_REG_KEY_ENTRY_21_0 `define KV_REG_KEY_ENTRY_21_0 (32'hb40) +`endif +`ifndef KV_REG_KEY_ENTRY_21_1 `define KV_REG_KEY_ENTRY_21_1 (32'hb44) +`endif +`ifndef KV_REG_KEY_ENTRY_21_2 `define KV_REG_KEY_ENTRY_21_2 (32'hb48) +`endif +`ifndef KV_REG_KEY_ENTRY_21_3 `define KV_REG_KEY_ENTRY_21_3 (32'hb4c) +`endif +`ifndef KV_REG_KEY_ENTRY_21_4 `define KV_REG_KEY_ENTRY_21_4 (32'hb50) +`endif +`ifndef KV_REG_KEY_ENTRY_21_5 `define KV_REG_KEY_ENTRY_21_5 (32'hb54) +`endif +`ifndef KV_REG_KEY_ENTRY_21_6 `define KV_REG_KEY_ENTRY_21_6 (32'hb58) +`endif +`ifndef KV_REG_KEY_ENTRY_21_7 `define KV_REG_KEY_ENTRY_21_7 (32'hb5c) +`endif +`ifndef KV_REG_KEY_ENTRY_21_8 `define KV_REG_KEY_ENTRY_21_8 (32'hb60) +`endif +`ifndef KV_REG_KEY_ENTRY_21_9 `define KV_REG_KEY_ENTRY_21_9 (32'hb64) +`endif +`ifndef KV_REG_KEY_ENTRY_21_10 `define KV_REG_KEY_ENTRY_21_10 (32'hb68) +`endif +`ifndef KV_REG_KEY_ENTRY_21_11 `define KV_REG_KEY_ENTRY_21_11 (32'hb6c) +`endif +`ifndef KV_REG_KEY_ENTRY_21_12 `define KV_REG_KEY_ENTRY_21_12 (32'hb70) +`endif +`ifndef KV_REG_KEY_ENTRY_21_13 `define KV_REG_KEY_ENTRY_21_13 (32'hb74) +`endif +`ifndef KV_REG_KEY_ENTRY_21_14 `define KV_REG_KEY_ENTRY_21_14 (32'hb78) +`endif +`ifndef KV_REG_KEY_ENTRY_21_15 `define KV_REG_KEY_ENTRY_21_15 (32'hb7c) +`endif +`ifndef KV_REG_KEY_ENTRY_22_0 `define KV_REG_KEY_ENTRY_22_0 (32'hb80) +`endif +`ifndef KV_REG_KEY_ENTRY_22_1 `define KV_REG_KEY_ENTRY_22_1 (32'hb84) +`endif +`ifndef KV_REG_KEY_ENTRY_22_2 `define KV_REG_KEY_ENTRY_22_2 (32'hb88) +`endif +`ifndef KV_REG_KEY_ENTRY_22_3 `define KV_REG_KEY_ENTRY_22_3 (32'hb8c) +`endif +`ifndef KV_REG_KEY_ENTRY_22_4 `define KV_REG_KEY_ENTRY_22_4 (32'hb90) +`endif +`ifndef KV_REG_KEY_ENTRY_22_5 `define KV_REG_KEY_ENTRY_22_5 (32'hb94) +`endif +`ifndef KV_REG_KEY_ENTRY_22_6 `define KV_REG_KEY_ENTRY_22_6 (32'hb98) +`endif +`ifndef KV_REG_KEY_ENTRY_22_7 `define KV_REG_KEY_ENTRY_22_7 (32'hb9c) +`endif +`ifndef KV_REG_KEY_ENTRY_22_8 `define KV_REG_KEY_ENTRY_22_8 (32'hba0) +`endif +`ifndef KV_REG_KEY_ENTRY_22_9 `define KV_REG_KEY_ENTRY_22_9 (32'hba4) +`endif +`ifndef KV_REG_KEY_ENTRY_22_10 `define KV_REG_KEY_ENTRY_22_10 (32'hba8) +`endif +`ifndef KV_REG_KEY_ENTRY_22_11 `define KV_REG_KEY_ENTRY_22_11 (32'hbac) +`endif +`ifndef KV_REG_KEY_ENTRY_22_12 `define KV_REG_KEY_ENTRY_22_12 (32'hbb0) +`endif +`ifndef KV_REG_KEY_ENTRY_22_13 `define KV_REG_KEY_ENTRY_22_13 (32'hbb4) +`endif +`ifndef KV_REG_KEY_ENTRY_22_14 `define KV_REG_KEY_ENTRY_22_14 (32'hbb8) +`endif +`ifndef KV_REG_KEY_ENTRY_22_15 `define KV_REG_KEY_ENTRY_22_15 (32'hbbc) +`endif +`ifndef KV_REG_KEY_ENTRY_23_0 `define KV_REG_KEY_ENTRY_23_0 (32'hbc0) +`endif +`ifndef KV_REG_KEY_ENTRY_23_1 `define KV_REG_KEY_ENTRY_23_1 (32'hbc4) +`endif +`ifndef KV_REG_KEY_ENTRY_23_2 `define KV_REG_KEY_ENTRY_23_2 (32'hbc8) +`endif +`ifndef KV_REG_KEY_ENTRY_23_3 `define KV_REG_KEY_ENTRY_23_3 (32'hbcc) +`endif +`ifndef KV_REG_KEY_ENTRY_23_4 `define KV_REG_KEY_ENTRY_23_4 (32'hbd0) +`endif +`ifndef KV_REG_KEY_ENTRY_23_5 `define KV_REG_KEY_ENTRY_23_5 (32'hbd4) +`endif +`ifndef KV_REG_KEY_ENTRY_23_6 `define KV_REG_KEY_ENTRY_23_6 (32'hbd8) +`endif +`ifndef KV_REG_KEY_ENTRY_23_7 `define KV_REG_KEY_ENTRY_23_7 (32'hbdc) +`endif +`ifndef KV_REG_KEY_ENTRY_23_8 `define KV_REG_KEY_ENTRY_23_8 (32'hbe0) +`endif +`ifndef KV_REG_KEY_ENTRY_23_9 `define KV_REG_KEY_ENTRY_23_9 (32'hbe4) +`endif +`ifndef KV_REG_KEY_ENTRY_23_10 `define KV_REG_KEY_ENTRY_23_10 (32'hbe8) +`endif +`ifndef KV_REG_KEY_ENTRY_23_11 `define KV_REG_KEY_ENTRY_23_11 (32'hbec) +`endif +`ifndef KV_REG_KEY_ENTRY_23_12 `define KV_REG_KEY_ENTRY_23_12 (32'hbf0) +`endif +`ifndef KV_REG_KEY_ENTRY_23_13 `define KV_REG_KEY_ENTRY_23_13 (32'hbf4) +`endif +`ifndef KV_REG_KEY_ENTRY_23_14 `define KV_REG_KEY_ENTRY_23_14 (32'hbf8) +`endif +`ifndef KV_REG_KEY_ENTRY_23_15 `define KV_REG_KEY_ENTRY_23_15 (32'hbfc) +`endif +`ifndef KV_REG_CLEAR_SECRETS `define KV_REG_CLEAR_SECRETS (32'hc00) `define KV_REG_CLEAR_SECRETS_WR_DEBUG_VALUES_LOW (0) `define KV_REG_CLEAR_SECRETS_WR_DEBUG_VALUES_MASK (32'h1) `define KV_REG_CLEAR_SECRETS_SEL_DEBUG_VALUE_LOW (1) `define KV_REG_CLEAR_SECRETS_SEL_DEBUG_VALUE_MASK (32'h2) +`endif +`ifndef PV_REG_PCR_CTRL_0 `define PV_REG_PCR_CTRL_0 (32'h0) `define PV_REG_PCR_CTRL_0_LOCK_LOW (0) `define PV_REG_PCR_CTRL_0_LOCK_MASK (32'h1) @@ -1506,6 +3045,8 @@ `define PV_REG_PCR_CTRL_0_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_0_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_0_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_1 `define PV_REG_PCR_CTRL_1 (32'h4) `define PV_REG_PCR_CTRL_1_LOCK_LOW (0) `define PV_REG_PCR_CTRL_1_LOCK_MASK (32'h1) @@ -1515,6 +3056,8 @@ `define PV_REG_PCR_CTRL_1_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_1_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_1_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_2 `define PV_REG_PCR_CTRL_2 (32'h8) `define PV_REG_PCR_CTRL_2_LOCK_LOW (0) `define PV_REG_PCR_CTRL_2_LOCK_MASK (32'h1) @@ -1524,6 +3067,8 @@ `define PV_REG_PCR_CTRL_2_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_2_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_2_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_3 `define PV_REG_PCR_CTRL_3 (32'hc) `define PV_REG_PCR_CTRL_3_LOCK_LOW (0) `define PV_REG_PCR_CTRL_3_LOCK_MASK (32'h1) @@ -1533,6 +3078,8 @@ `define PV_REG_PCR_CTRL_3_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_3_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_3_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_4 `define PV_REG_PCR_CTRL_4 (32'h10) `define PV_REG_PCR_CTRL_4_LOCK_LOW (0) `define PV_REG_PCR_CTRL_4_LOCK_MASK (32'h1) @@ -1542,6 +3089,8 @@ `define PV_REG_PCR_CTRL_4_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_4_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_4_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_5 `define PV_REG_PCR_CTRL_5 (32'h14) `define PV_REG_PCR_CTRL_5_LOCK_LOW (0) `define PV_REG_PCR_CTRL_5_LOCK_MASK (32'h1) @@ -1551,6 +3100,8 @@ `define PV_REG_PCR_CTRL_5_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_5_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_5_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_6 `define PV_REG_PCR_CTRL_6 (32'h18) `define PV_REG_PCR_CTRL_6_LOCK_LOW (0) `define PV_REG_PCR_CTRL_6_LOCK_MASK (32'h1) @@ -1560,6 +3111,8 @@ `define PV_REG_PCR_CTRL_6_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_6_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_6_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_7 `define PV_REG_PCR_CTRL_7 (32'h1c) `define PV_REG_PCR_CTRL_7_LOCK_LOW (0) `define PV_REG_PCR_CTRL_7_LOCK_MASK (32'h1) @@ -1569,6 +3122,8 @@ `define PV_REG_PCR_CTRL_7_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_7_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_7_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_8 `define PV_REG_PCR_CTRL_8 (32'h20) `define PV_REG_PCR_CTRL_8_LOCK_LOW (0) `define PV_REG_PCR_CTRL_8_LOCK_MASK (32'h1) @@ -1578,6 +3133,8 @@ `define PV_REG_PCR_CTRL_8_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_8_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_8_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_9 `define PV_REG_PCR_CTRL_9 (32'h24) `define PV_REG_PCR_CTRL_9_LOCK_LOW (0) `define PV_REG_PCR_CTRL_9_LOCK_MASK (32'h1) @@ -1587,6 +3144,8 @@ `define PV_REG_PCR_CTRL_9_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_9_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_9_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_10 `define PV_REG_PCR_CTRL_10 (32'h28) `define PV_REG_PCR_CTRL_10_LOCK_LOW (0) `define PV_REG_PCR_CTRL_10_LOCK_MASK (32'h1) @@ -1596,6 +3155,8 @@ `define PV_REG_PCR_CTRL_10_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_10_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_10_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_11 `define PV_REG_PCR_CTRL_11 (32'h2c) `define PV_REG_PCR_CTRL_11_LOCK_LOW (0) `define PV_REG_PCR_CTRL_11_LOCK_MASK (32'h1) @@ -1605,6 +3166,8 @@ `define PV_REG_PCR_CTRL_11_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_11_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_11_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_12 `define PV_REG_PCR_CTRL_12 (32'h30) `define PV_REG_PCR_CTRL_12_LOCK_LOW (0) `define PV_REG_PCR_CTRL_12_LOCK_MASK (32'h1) @@ -1614,6 +3177,8 @@ `define PV_REG_PCR_CTRL_12_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_12_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_12_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_13 `define PV_REG_PCR_CTRL_13 (32'h34) `define PV_REG_PCR_CTRL_13_LOCK_LOW (0) `define PV_REG_PCR_CTRL_13_LOCK_MASK (32'h1) @@ -1623,6 +3188,8 @@ `define PV_REG_PCR_CTRL_13_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_13_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_13_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_14 `define PV_REG_PCR_CTRL_14 (32'h38) `define PV_REG_PCR_CTRL_14_LOCK_LOW (0) `define PV_REG_PCR_CTRL_14_LOCK_MASK (32'h1) @@ -1632,6 +3199,8 @@ `define PV_REG_PCR_CTRL_14_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_14_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_14_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_15 `define PV_REG_PCR_CTRL_15 (32'h3c) `define PV_REG_PCR_CTRL_15_LOCK_LOW (0) `define PV_REG_PCR_CTRL_15_LOCK_MASK (32'h1) @@ -1641,6 +3210,8 @@ `define PV_REG_PCR_CTRL_15_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_15_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_15_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_16 `define PV_REG_PCR_CTRL_16 (32'h40) `define PV_REG_PCR_CTRL_16_LOCK_LOW (0) `define PV_REG_PCR_CTRL_16_LOCK_MASK (32'h1) @@ -1650,6 +3221,8 @@ `define PV_REG_PCR_CTRL_16_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_16_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_16_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_17 `define PV_REG_PCR_CTRL_17 (32'h44) `define PV_REG_PCR_CTRL_17_LOCK_LOW (0) `define PV_REG_PCR_CTRL_17_LOCK_MASK (32'h1) @@ -1659,6 +3232,8 @@ `define PV_REG_PCR_CTRL_17_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_17_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_17_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_18 `define PV_REG_PCR_CTRL_18 (32'h48) `define PV_REG_PCR_CTRL_18_LOCK_LOW (0) `define PV_REG_PCR_CTRL_18_LOCK_MASK (32'h1) @@ -1668,6 +3243,8 @@ `define PV_REG_PCR_CTRL_18_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_18_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_18_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_19 `define PV_REG_PCR_CTRL_19 (32'h4c) `define PV_REG_PCR_CTRL_19_LOCK_LOW (0) `define PV_REG_PCR_CTRL_19_LOCK_MASK (32'h1) @@ -1677,6 +3254,8 @@ `define PV_REG_PCR_CTRL_19_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_19_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_19_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_20 `define PV_REG_PCR_CTRL_20 (32'h50) `define PV_REG_PCR_CTRL_20_LOCK_LOW (0) `define PV_REG_PCR_CTRL_20_LOCK_MASK (32'h1) @@ -1686,6 +3265,8 @@ `define PV_REG_PCR_CTRL_20_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_20_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_20_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_21 `define PV_REG_PCR_CTRL_21 (32'h54) `define PV_REG_PCR_CTRL_21_LOCK_LOW (0) `define PV_REG_PCR_CTRL_21_LOCK_MASK (32'h1) @@ -1695,6 +3276,8 @@ `define PV_REG_PCR_CTRL_21_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_21_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_21_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_22 `define PV_REG_PCR_CTRL_22 (32'h58) `define PV_REG_PCR_CTRL_22_LOCK_LOW (0) `define PV_REG_PCR_CTRL_22_LOCK_MASK (32'h1) @@ -1704,6 +3287,8 @@ `define PV_REG_PCR_CTRL_22_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_22_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_22_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_23 `define PV_REG_PCR_CTRL_23 (32'h5c) `define PV_REG_PCR_CTRL_23_LOCK_LOW (0) `define PV_REG_PCR_CTRL_23_LOCK_MASK (32'h1) @@ -1713,6 +3298,8 @@ `define PV_REG_PCR_CTRL_23_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_23_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_23_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_24 `define PV_REG_PCR_CTRL_24 (32'h60) `define PV_REG_PCR_CTRL_24_LOCK_LOW (0) `define PV_REG_PCR_CTRL_24_LOCK_MASK (32'h1) @@ -1722,6 +3309,8 @@ `define PV_REG_PCR_CTRL_24_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_24_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_24_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_25 `define PV_REG_PCR_CTRL_25 (32'h64) `define PV_REG_PCR_CTRL_25_LOCK_LOW (0) `define PV_REG_PCR_CTRL_25_LOCK_MASK (32'h1) @@ -1731,6 +3320,8 @@ `define PV_REG_PCR_CTRL_25_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_25_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_25_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_26 `define PV_REG_PCR_CTRL_26 (32'h68) `define PV_REG_PCR_CTRL_26_LOCK_LOW (0) `define PV_REG_PCR_CTRL_26_LOCK_MASK (32'h1) @@ -1740,6 +3331,8 @@ `define PV_REG_PCR_CTRL_26_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_26_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_26_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_27 `define PV_REG_PCR_CTRL_27 (32'h6c) `define PV_REG_PCR_CTRL_27_LOCK_LOW (0) `define PV_REG_PCR_CTRL_27_LOCK_MASK (32'h1) @@ -1749,6 +3342,8 @@ `define PV_REG_PCR_CTRL_27_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_27_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_27_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_28 `define PV_REG_PCR_CTRL_28 (32'h70) `define PV_REG_PCR_CTRL_28_LOCK_LOW (0) `define PV_REG_PCR_CTRL_28_LOCK_MASK (32'h1) @@ -1758,6 +3353,8 @@ `define PV_REG_PCR_CTRL_28_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_28_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_28_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_29 `define PV_REG_PCR_CTRL_29 (32'h74) `define PV_REG_PCR_CTRL_29_LOCK_LOW (0) `define PV_REG_PCR_CTRL_29_LOCK_MASK (32'h1) @@ -1767,6 +3364,8 @@ `define PV_REG_PCR_CTRL_29_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_29_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_29_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_30 `define PV_REG_PCR_CTRL_30 (32'h78) `define PV_REG_PCR_CTRL_30_LOCK_LOW (0) `define PV_REG_PCR_CTRL_30_LOCK_MASK (32'h1) @@ -1776,6 +3375,8 @@ `define PV_REG_PCR_CTRL_30_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_30_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_30_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_CTRL_31 `define PV_REG_PCR_CTRL_31 (32'h7c) `define PV_REG_PCR_CTRL_31_LOCK_LOW (0) `define PV_REG_PCR_CTRL_31_LOCK_MASK (32'h1) @@ -1785,774 +3386,2160 @@ `define PV_REG_PCR_CTRL_31_RSVD0_MASK (32'h4) `define PV_REG_PCR_CTRL_31_RSVD1_LOW (3) `define PV_REG_PCR_CTRL_31_RSVD1_MASK (32'hf8) +`endif +`ifndef PV_REG_PCR_ENTRY_0_0 `define PV_REG_PCR_ENTRY_0_0 (32'h600) +`endif +`ifndef PV_REG_PCR_ENTRY_0_1 `define PV_REG_PCR_ENTRY_0_1 (32'h604) +`endif +`ifndef PV_REG_PCR_ENTRY_0_2 `define PV_REG_PCR_ENTRY_0_2 (32'h608) +`endif +`ifndef PV_REG_PCR_ENTRY_0_3 `define PV_REG_PCR_ENTRY_0_3 (32'h60c) +`endif +`ifndef PV_REG_PCR_ENTRY_0_4 `define PV_REG_PCR_ENTRY_0_4 (32'h610) +`endif +`ifndef PV_REG_PCR_ENTRY_0_5 `define PV_REG_PCR_ENTRY_0_5 (32'h614) +`endif +`ifndef PV_REG_PCR_ENTRY_0_6 `define PV_REG_PCR_ENTRY_0_6 (32'h618) +`endif +`ifndef PV_REG_PCR_ENTRY_0_7 `define PV_REG_PCR_ENTRY_0_7 (32'h61c) +`endif +`ifndef PV_REG_PCR_ENTRY_0_8 `define PV_REG_PCR_ENTRY_0_8 (32'h620) +`endif +`ifndef PV_REG_PCR_ENTRY_0_9 `define PV_REG_PCR_ENTRY_0_9 (32'h624) +`endif +`ifndef PV_REG_PCR_ENTRY_0_10 `define PV_REG_PCR_ENTRY_0_10 (32'h628) +`endif +`ifndef PV_REG_PCR_ENTRY_0_11 `define PV_REG_PCR_ENTRY_0_11 (32'h62c) +`endif +`ifndef PV_REG_PCR_ENTRY_1_0 `define PV_REG_PCR_ENTRY_1_0 (32'h630) +`endif +`ifndef PV_REG_PCR_ENTRY_1_1 `define PV_REG_PCR_ENTRY_1_1 (32'h634) +`endif +`ifndef PV_REG_PCR_ENTRY_1_2 `define PV_REG_PCR_ENTRY_1_2 (32'h638) +`endif +`ifndef PV_REG_PCR_ENTRY_1_3 `define PV_REG_PCR_ENTRY_1_3 (32'h63c) +`endif +`ifndef PV_REG_PCR_ENTRY_1_4 `define PV_REG_PCR_ENTRY_1_4 (32'h640) +`endif +`ifndef PV_REG_PCR_ENTRY_1_5 `define PV_REG_PCR_ENTRY_1_5 (32'h644) +`endif +`ifndef PV_REG_PCR_ENTRY_1_6 `define PV_REG_PCR_ENTRY_1_6 (32'h648) +`endif +`ifndef PV_REG_PCR_ENTRY_1_7 `define PV_REG_PCR_ENTRY_1_7 (32'h64c) +`endif +`ifndef PV_REG_PCR_ENTRY_1_8 `define PV_REG_PCR_ENTRY_1_8 (32'h650) +`endif +`ifndef PV_REG_PCR_ENTRY_1_9 `define PV_REG_PCR_ENTRY_1_9 (32'h654) +`endif +`ifndef PV_REG_PCR_ENTRY_1_10 `define PV_REG_PCR_ENTRY_1_10 (32'h658) +`endif +`ifndef PV_REG_PCR_ENTRY_1_11 `define PV_REG_PCR_ENTRY_1_11 (32'h65c) +`endif +`ifndef PV_REG_PCR_ENTRY_2_0 `define PV_REG_PCR_ENTRY_2_0 (32'h660) +`endif +`ifndef PV_REG_PCR_ENTRY_2_1 `define PV_REG_PCR_ENTRY_2_1 (32'h664) +`endif +`ifndef PV_REG_PCR_ENTRY_2_2 `define PV_REG_PCR_ENTRY_2_2 (32'h668) +`endif +`ifndef PV_REG_PCR_ENTRY_2_3 `define PV_REG_PCR_ENTRY_2_3 (32'h66c) +`endif +`ifndef PV_REG_PCR_ENTRY_2_4 `define PV_REG_PCR_ENTRY_2_4 (32'h670) +`endif +`ifndef PV_REG_PCR_ENTRY_2_5 `define PV_REG_PCR_ENTRY_2_5 (32'h674) +`endif +`ifndef PV_REG_PCR_ENTRY_2_6 `define PV_REG_PCR_ENTRY_2_6 (32'h678) +`endif +`ifndef PV_REG_PCR_ENTRY_2_7 `define PV_REG_PCR_ENTRY_2_7 (32'h67c) +`endif +`ifndef PV_REG_PCR_ENTRY_2_8 `define PV_REG_PCR_ENTRY_2_8 (32'h680) +`endif +`ifndef PV_REG_PCR_ENTRY_2_9 `define PV_REG_PCR_ENTRY_2_9 (32'h684) +`endif +`ifndef PV_REG_PCR_ENTRY_2_10 `define PV_REG_PCR_ENTRY_2_10 (32'h688) +`endif +`ifndef PV_REG_PCR_ENTRY_2_11 `define PV_REG_PCR_ENTRY_2_11 (32'h68c) +`endif +`ifndef PV_REG_PCR_ENTRY_3_0 `define PV_REG_PCR_ENTRY_3_0 (32'h690) +`endif +`ifndef PV_REG_PCR_ENTRY_3_1 `define PV_REG_PCR_ENTRY_3_1 (32'h694) +`endif +`ifndef PV_REG_PCR_ENTRY_3_2 `define PV_REG_PCR_ENTRY_3_2 (32'h698) +`endif +`ifndef PV_REG_PCR_ENTRY_3_3 `define PV_REG_PCR_ENTRY_3_3 (32'h69c) +`endif +`ifndef PV_REG_PCR_ENTRY_3_4 `define PV_REG_PCR_ENTRY_3_4 (32'h6a0) +`endif +`ifndef PV_REG_PCR_ENTRY_3_5 `define PV_REG_PCR_ENTRY_3_5 (32'h6a4) +`endif +`ifndef PV_REG_PCR_ENTRY_3_6 `define PV_REG_PCR_ENTRY_3_6 (32'h6a8) +`endif +`ifndef PV_REG_PCR_ENTRY_3_7 `define PV_REG_PCR_ENTRY_3_7 (32'h6ac) +`endif +`ifndef PV_REG_PCR_ENTRY_3_8 `define PV_REG_PCR_ENTRY_3_8 (32'h6b0) +`endif +`ifndef PV_REG_PCR_ENTRY_3_9 `define PV_REG_PCR_ENTRY_3_9 (32'h6b4) +`endif +`ifndef PV_REG_PCR_ENTRY_3_10 `define PV_REG_PCR_ENTRY_3_10 (32'h6b8) +`endif +`ifndef PV_REG_PCR_ENTRY_3_11 `define PV_REG_PCR_ENTRY_3_11 (32'h6bc) +`endif +`ifndef PV_REG_PCR_ENTRY_4_0 `define PV_REG_PCR_ENTRY_4_0 (32'h6c0) +`endif +`ifndef PV_REG_PCR_ENTRY_4_1 `define PV_REG_PCR_ENTRY_4_1 (32'h6c4) +`endif +`ifndef PV_REG_PCR_ENTRY_4_2 `define PV_REG_PCR_ENTRY_4_2 (32'h6c8) +`endif +`ifndef PV_REG_PCR_ENTRY_4_3 `define PV_REG_PCR_ENTRY_4_3 (32'h6cc) +`endif +`ifndef PV_REG_PCR_ENTRY_4_4 `define PV_REG_PCR_ENTRY_4_4 (32'h6d0) +`endif +`ifndef PV_REG_PCR_ENTRY_4_5 `define PV_REG_PCR_ENTRY_4_5 (32'h6d4) +`endif +`ifndef PV_REG_PCR_ENTRY_4_6 `define PV_REG_PCR_ENTRY_4_6 (32'h6d8) +`endif +`ifndef PV_REG_PCR_ENTRY_4_7 `define PV_REG_PCR_ENTRY_4_7 (32'h6dc) +`endif +`ifndef PV_REG_PCR_ENTRY_4_8 `define PV_REG_PCR_ENTRY_4_8 (32'h6e0) +`endif +`ifndef PV_REG_PCR_ENTRY_4_9 `define PV_REG_PCR_ENTRY_4_9 (32'h6e4) +`endif +`ifndef PV_REG_PCR_ENTRY_4_10 `define PV_REG_PCR_ENTRY_4_10 (32'h6e8) +`endif +`ifndef PV_REG_PCR_ENTRY_4_11 `define PV_REG_PCR_ENTRY_4_11 (32'h6ec) +`endif +`ifndef PV_REG_PCR_ENTRY_5_0 `define PV_REG_PCR_ENTRY_5_0 (32'h6f0) +`endif +`ifndef PV_REG_PCR_ENTRY_5_1 `define PV_REG_PCR_ENTRY_5_1 (32'h6f4) +`endif +`ifndef PV_REG_PCR_ENTRY_5_2 `define PV_REG_PCR_ENTRY_5_2 (32'h6f8) +`endif +`ifndef PV_REG_PCR_ENTRY_5_3 `define PV_REG_PCR_ENTRY_5_3 (32'h6fc) +`endif +`ifndef PV_REG_PCR_ENTRY_5_4 `define PV_REG_PCR_ENTRY_5_4 (32'h700) +`endif +`ifndef PV_REG_PCR_ENTRY_5_5 `define PV_REG_PCR_ENTRY_5_5 (32'h704) +`endif +`ifndef PV_REG_PCR_ENTRY_5_6 `define PV_REG_PCR_ENTRY_5_6 (32'h708) +`endif +`ifndef PV_REG_PCR_ENTRY_5_7 `define PV_REG_PCR_ENTRY_5_7 (32'h70c) +`endif +`ifndef PV_REG_PCR_ENTRY_5_8 `define PV_REG_PCR_ENTRY_5_8 (32'h710) +`endif +`ifndef PV_REG_PCR_ENTRY_5_9 `define PV_REG_PCR_ENTRY_5_9 (32'h714) +`endif +`ifndef PV_REG_PCR_ENTRY_5_10 `define PV_REG_PCR_ENTRY_5_10 (32'h718) +`endif +`ifndef PV_REG_PCR_ENTRY_5_11 `define PV_REG_PCR_ENTRY_5_11 (32'h71c) +`endif +`ifndef PV_REG_PCR_ENTRY_6_0 `define PV_REG_PCR_ENTRY_6_0 (32'h720) +`endif +`ifndef PV_REG_PCR_ENTRY_6_1 `define PV_REG_PCR_ENTRY_6_1 (32'h724) +`endif +`ifndef PV_REG_PCR_ENTRY_6_2 `define PV_REG_PCR_ENTRY_6_2 (32'h728) +`endif +`ifndef PV_REG_PCR_ENTRY_6_3 `define PV_REG_PCR_ENTRY_6_3 (32'h72c) +`endif +`ifndef PV_REG_PCR_ENTRY_6_4 `define PV_REG_PCR_ENTRY_6_4 (32'h730) +`endif +`ifndef PV_REG_PCR_ENTRY_6_5 `define PV_REG_PCR_ENTRY_6_5 (32'h734) +`endif +`ifndef PV_REG_PCR_ENTRY_6_6 `define PV_REG_PCR_ENTRY_6_6 (32'h738) +`endif +`ifndef PV_REG_PCR_ENTRY_6_7 `define PV_REG_PCR_ENTRY_6_7 (32'h73c) +`endif +`ifndef PV_REG_PCR_ENTRY_6_8 `define PV_REG_PCR_ENTRY_6_8 (32'h740) +`endif +`ifndef PV_REG_PCR_ENTRY_6_9 `define PV_REG_PCR_ENTRY_6_9 (32'h744) +`endif +`ifndef PV_REG_PCR_ENTRY_6_10 `define PV_REG_PCR_ENTRY_6_10 (32'h748) +`endif +`ifndef PV_REG_PCR_ENTRY_6_11 `define PV_REG_PCR_ENTRY_6_11 (32'h74c) +`endif +`ifndef PV_REG_PCR_ENTRY_7_0 `define PV_REG_PCR_ENTRY_7_0 (32'h750) +`endif +`ifndef PV_REG_PCR_ENTRY_7_1 `define PV_REG_PCR_ENTRY_7_1 (32'h754) +`endif +`ifndef PV_REG_PCR_ENTRY_7_2 `define PV_REG_PCR_ENTRY_7_2 (32'h758) +`endif +`ifndef PV_REG_PCR_ENTRY_7_3 `define PV_REG_PCR_ENTRY_7_3 (32'h75c) +`endif +`ifndef PV_REG_PCR_ENTRY_7_4 `define PV_REG_PCR_ENTRY_7_4 (32'h760) +`endif +`ifndef PV_REG_PCR_ENTRY_7_5 `define PV_REG_PCR_ENTRY_7_5 (32'h764) +`endif +`ifndef PV_REG_PCR_ENTRY_7_6 `define PV_REG_PCR_ENTRY_7_6 (32'h768) +`endif +`ifndef PV_REG_PCR_ENTRY_7_7 `define PV_REG_PCR_ENTRY_7_7 (32'h76c) +`endif +`ifndef PV_REG_PCR_ENTRY_7_8 `define PV_REG_PCR_ENTRY_7_8 (32'h770) +`endif +`ifndef PV_REG_PCR_ENTRY_7_9 `define PV_REG_PCR_ENTRY_7_9 (32'h774) +`endif +`ifndef PV_REG_PCR_ENTRY_7_10 `define PV_REG_PCR_ENTRY_7_10 (32'h778) +`endif +`ifndef PV_REG_PCR_ENTRY_7_11 `define PV_REG_PCR_ENTRY_7_11 (32'h77c) +`endif +`ifndef PV_REG_PCR_ENTRY_8_0 `define PV_REG_PCR_ENTRY_8_0 (32'h780) +`endif +`ifndef PV_REG_PCR_ENTRY_8_1 `define PV_REG_PCR_ENTRY_8_1 (32'h784) +`endif +`ifndef PV_REG_PCR_ENTRY_8_2 `define PV_REG_PCR_ENTRY_8_2 (32'h788) +`endif +`ifndef PV_REG_PCR_ENTRY_8_3 `define PV_REG_PCR_ENTRY_8_3 (32'h78c) +`endif +`ifndef PV_REG_PCR_ENTRY_8_4 `define PV_REG_PCR_ENTRY_8_4 (32'h790) +`endif +`ifndef PV_REG_PCR_ENTRY_8_5 `define PV_REG_PCR_ENTRY_8_5 (32'h794) +`endif +`ifndef PV_REG_PCR_ENTRY_8_6 `define PV_REG_PCR_ENTRY_8_6 (32'h798) +`endif +`ifndef PV_REG_PCR_ENTRY_8_7 `define PV_REG_PCR_ENTRY_8_7 (32'h79c) +`endif +`ifndef PV_REG_PCR_ENTRY_8_8 `define PV_REG_PCR_ENTRY_8_8 (32'h7a0) +`endif +`ifndef PV_REG_PCR_ENTRY_8_9 `define PV_REG_PCR_ENTRY_8_9 (32'h7a4) +`endif +`ifndef PV_REG_PCR_ENTRY_8_10 `define PV_REG_PCR_ENTRY_8_10 (32'h7a8) +`endif +`ifndef PV_REG_PCR_ENTRY_8_11 `define PV_REG_PCR_ENTRY_8_11 (32'h7ac) +`endif +`ifndef PV_REG_PCR_ENTRY_9_0 `define PV_REG_PCR_ENTRY_9_0 (32'h7b0) +`endif +`ifndef PV_REG_PCR_ENTRY_9_1 `define PV_REG_PCR_ENTRY_9_1 (32'h7b4) +`endif +`ifndef PV_REG_PCR_ENTRY_9_2 `define PV_REG_PCR_ENTRY_9_2 (32'h7b8) +`endif +`ifndef PV_REG_PCR_ENTRY_9_3 `define PV_REG_PCR_ENTRY_9_3 (32'h7bc) +`endif +`ifndef PV_REG_PCR_ENTRY_9_4 `define PV_REG_PCR_ENTRY_9_4 (32'h7c0) +`endif +`ifndef PV_REG_PCR_ENTRY_9_5 `define PV_REG_PCR_ENTRY_9_5 (32'h7c4) +`endif +`ifndef PV_REG_PCR_ENTRY_9_6 `define PV_REG_PCR_ENTRY_9_6 (32'h7c8) +`endif +`ifndef PV_REG_PCR_ENTRY_9_7 `define PV_REG_PCR_ENTRY_9_7 (32'h7cc) +`endif +`ifndef PV_REG_PCR_ENTRY_9_8 `define PV_REG_PCR_ENTRY_9_8 (32'h7d0) +`endif +`ifndef PV_REG_PCR_ENTRY_9_9 `define PV_REG_PCR_ENTRY_9_9 (32'h7d4) +`endif +`ifndef PV_REG_PCR_ENTRY_9_10 `define PV_REG_PCR_ENTRY_9_10 (32'h7d8) +`endif +`ifndef PV_REG_PCR_ENTRY_9_11 `define PV_REG_PCR_ENTRY_9_11 (32'h7dc) +`endif +`ifndef PV_REG_PCR_ENTRY_10_0 `define PV_REG_PCR_ENTRY_10_0 (32'h7e0) +`endif +`ifndef PV_REG_PCR_ENTRY_10_1 `define PV_REG_PCR_ENTRY_10_1 (32'h7e4) +`endif +`ifndef PV_REG_PCR_ENTRY_10_2 `define PV_REG_PCR_ENTRY_10_2 (32'h7e8) +`endif +`ifndef PV_REG_PCR_ENTRY_10_3 `define PV_REG_PCR_ENTRY_10_3 (32'h7ec) +`endif +`ifndef PV_REG_PCR_ENTRY_10_4 `define PV_REG_PCR_ENTRY_10_4 (32'h7f0) +`endif +`ifndef PV_REG_PCR_ENTRY_10_5 `define PV_REG_PCR_ENTRY_10_5 (32'h7f4) +`endif +`ifndef PV_REG_PCR_ENTRY_10_6 `define PV_REG_PCR_ENTRY_10_6 (32'h7f8) +`endif +`ifndef PV_REG_PCR_ENTRY_10_7 `define PV_REG_PCR_ENTRY_10_7 (32'h7fc) +`endif +`ifndef PV_REG_PCR_ENTRY_10_8 `define PV_REG_PCR_ENTRY_10_8 (32'h800) +`endif +`ifndef PV_REG_PCR_ENTRY_10_9 `define PV_REG_PCR_ENTRY_10_9 (32'h804) +`endif +`ifndef PV_REG_PCR_ENTRY_10_10 `define PV_REG_PCR_ENTRY_10_10 (32'h808) +`endif +`ifndef PV_REG_PCR_ENTRY_10_11 `define PV_REG_PCR_ENTRY_10_11 (32'h80c) +`endif +`ifndef PV_REG_PCR_ENTRY_11_0 `define PV_REG_PCR_ENTRY_11_0 (32'h810) +`endif +`ifndef PV_REG_PCR_ENTRY_11_1 `define PV_REG_PCR_ENTRY_11_1 (32'h814) +`endif +`ifndef PV_REG_PCR_ENTRY_11_2 `define PV_REG_PCR_ENTRY_11_2 (32'h818) +`endif +`ifndef PV_REG_PCR_ENTRY_11_3 `define PV_REG_PCR_ENTRY_11_3 (32'h81c) +`endif +`ifndef PV_REG_PCR_ENTRY_11_4 `define PV_REG_PCR_ENTRY_11_4 (32'h820) +`endif +`ifndef PV_REG_PCR_ENTRY_11_5 `define PV_REG_PCR_ENTRY_11_5 (32'h824) +`endif +`ifndef PV_REG_PCR_ENTRY_11_6 `define PV_REG_PCR_ENTRY_11_6 (32'h828) +`endif +`ifndef PV_REG_PCR_ENTRY_11_7 `define PV_REG_PCR_ENTRY_11_7 (32'h82c) +`endif +`ifndef PV_REG_PCR_ENTRY_11_8 `define PV_REG_PCR_ENTRY_11_8 (32'h830) +`endif +`ifndef PV_REG_PCR_ENTRY_11_9 `define PV_REG_PCR_ENTRY_11_9 (32'h834) +`endif +`ifndef PV_REG_PCR_ENTRY_11_10 `define PV_REG_PCR_ENTRY_11_10 (32'h838) +`endif +`ifndef PV_REG_PCR_ENTRY_11_11 `define PV_REG_PCR_ENTRY_11_11 (32'h83c) +`endif +`ifndef PV_REG_PCR_ENTRY_12_0 `define PV_REG_PCR_ENTRY_12_0 (32'h840) +`endif +`ifndef PV_REG_PCR_ENTRY_12_1 `define PV_REG_PCR_ENTRY_12_1 (32'h844) +`endif +`ifndef PV_REG_PCR_ENTRY_12_2 `define PV_REG_PCR_ENTRY_12_2 (32'h848) +`endif +`ifndef PV_REG_PCR_ENTRY_12_3 `define PV_REG_PCR_ENTRY_12_3 (32'h84c) +`endif +`ifndef PV_REG_PCR_ENTRY_12_4 `define PV_REG_PCR_ENTRY_12_4 (32'h850) +`endif +`ifndef PV_REG_PCR_ENTRY_12_5 `define PV_REG_PCR_ENTRY_12_5 (32'h854) +`endif +`ifndef PV_REG_PCR_ENTRY_12_6 `define PV_REG_PCR_ENTRY_12_6 (32'h858) +`endif +`ifndef PV_REG_PCR_ENTRY_12_7 `define PV_REG_PCR_ENTRY_12_7 (32'h85c) +`endif +`ifndef PV_REG_PCR_ENTRY_12_8 `define PV_REG_PCR_ENTRY_12_8 (32'h860) +`endif +`ifndef PV_REG_PCR_ENTRY_12_9 `define PV_REG_PCR_ENTRY_12_9 (32'h864) +`endif +`ifndef PV_REG_PCR_ENTRY_12_10 `define PV_REG_PCR_ENTRY_12_10 (32'h868) +`endif +`ifndef PV_REG_PCR_ENTRY_12_11 `define PV_REG_PCR_ENTRY_12_11 (32'h86c) +`endif +`ifndef PV_REG_PCR_ENTRY_13_0 `define PV_REG_PCR_ENTRY_13_0 (32'h870) +`endif +`ifndef PV_REG_PCR_ENTRY_13_1 `define PV_REG_PCR_ENTRY_13_1 (32'h874) +`endif +`ifndef PV_REG_PCR_ENTRY_13_2 `define PV_REG_PCR_ENTRY_13_2 (32'h878) +`endif +`ifndef PV_REG_PCR_ENTRY_13_3 `define PV_REG_PCR_ENTRY_13_3 (32'h87c) +`endif +`ifndef PV_REG_PCR_ENTRY_13_4 `define PV_REG_PCR_ENTRY_13_4 (32'h880) +`endif +`ifndef PV_REG_PCR_ENTRY_13_5 `define PV_REG_PCR_ENTRY_13_5 (32'h884) +`endif +`ifndef PV_REG_PCR_ENTRY_13_6 `define PV_REG_PCR_ENTRY_13_6 (32'h888) +`endif +`ifndef PV_REG_PCR_ENTRY_13_7 `define PV_REG_PCR_ENTRY_13_7 (32'h88c) +`endif +`ifndef PV_REG_PCR_ENTRY_13_8 `define PV_REG_PCR_ENTRY_13_8 (32'h890) +`endif +`ifndef PV_REG_PCR_ENTRY_13_9 `define PV_REG_PCR_ENTRY_13_9 (32'h894) +`endif +`ifndef PV_REG_PCR_ENTRY_13_10 `define PV_REG_PCR_ENTRY_13_10 (32'h898) +`endif +`ifndef PV_REG_PCR_ENTRY_13_11 `define PV_REG_PCR_ENTRY_13_11 (32'h89c) +`endif +`ifndef PV_REG_PCR_ENTRY_14_0 `define PV_REG_PCR_ENTRY_14_0 (32'h8a0) +`endif +`ifndef PV_REG_PCR_ENTRY_14_1 `define PV_REG_PCR_ENTRY_14_1 (32'h8a4) +`endif +`ifndef PV_REG_PCR_ENTRY_14_2 `define PV_REG_PCR_ENTRY_14_2 (32'h8a8) +`endif +`ifndef PV_REG_PCR_ENTRY_14_3 `define PV_REG_PCR_ENTRY_14_3 (32'h8ac) +`endif +`ifndef PV_REG_PCR_ENTRY_14_4 `define PV_REG_PCR_ENTRY_14_4 (32'h8b0) +`endif +`ifndef PV_REG_PCR_ENTRY_14_5 `define PV_REG_PCR_ENTRY_14_5 (32'h8b4) +`endif +`ifndef PV_REG_PCR_ENTRY_14_6 `define PV_REG_PCR_ENTRY_14_6 (32'h8b8) +`endif +`ifndef PV_REG_PCR_ENTRY_14_7 `define PV_REG_PCR_ENTRY_14_7 (32'h8bc) +`endif +`ifndef PV_REG_PCR_ENTRY_14_8 `define PV_REG_PCR_ENTRY_14_8 (32'h8c0) +`endif +`ifndef PV_REG_PCR_ENTRY_14_9 `define PV_REG_PCR_ENTRY_14_9 (32'h8c4) +`endif +`ifndef PV_REG_PCR_ENTRY_14_10 `define PV_REG_PCR_ENTRY_14_10 (32'h8c8) +`endif +`ifndef PV_REG_PCR_ENTRY_14_11 `define PV_REG_PCR_ENTRY_14_11 (32'h8cc) +`endif +`ifndef PV_REG_PCR_ENTRY_15_0 `define PV_REG_PCR_ENTRY_15_0 (32'h8d0) +`endif +`ifndef PV_REG_PCR_ENTRY_15_1 `define PV_REG_PCR_ENTRY_15_1 (32'h8d4) +`endif +`ifndef PV_REG_PCR_ENTRY_15_2 `define PV_REG_PCR_ENTRY_15_2 (32'h8d8) +`endif +`ifndef PV_REG_PCR_ENTRY_15_3 `define PV_REG_PCR_ENTRY_15_3 (32'h8dc) +`endif +`ifndef PV_REG_PCR_ENTRY_15_4 `define PV_REG_PCR_ENTRY_15_4 (32'h8e0) +`endif +`ifndef PV_REG_PCR_ENTRY_15_5 `define PV_REG_PCR_ENTRY_15_5 (32'h8e4) +`endif +`ifndef PV_REG_PCR_ENTRY_15_6 `define PV_REG_PCR_ENTRY_15_6 (32'h8e8) +`endif +`ifndef PV_REG_PCR_ENTRY_15_7 `define PV_REG_PCR_ENTRY_15_7 (32'h8ec) +`endif +`ifndef PV_REG_PCR_ENTRY_15_8 `define PV_REG_PCR_ENTRY_15_8 (32'h8f0) +`endif +`ifndef PV_REG_PCR_ENTRY_15_9 `define PV_REG_PCR_ENTRY_15_9 (32'h8f4) +`endif +`ifndef PV_REG_PCR_ENTRY_15_10 `define PV_REG_PCR_ENTRY_15_10 (32'h8f8) +`endif +`ifndef PV_REG_PCR_ENTRY_15_11 `define PV_REG_PCR_ENTRY_15_11 (32'h8fc) +`endif +`ifndef PV_REG_PCR_ENTRY_16_0 `define PV_REG_PCR_ENTRY_16_0 (32'h900) +`endif +`ifndef PV_REG_PCR_ENTRY_16_1 `define PV_REG_PCR_ENTRY_16_1 (32'h904) +`endif +`ifndef PV_REG_PCR_ENTRY_16_2 `define PV_REG_PCR_ENTRY_16_2 (32'h908) +`endif +`ifndef PV_REG_PCR_ENTRY_16_3 `define PV_REG_PCR_ENTRY_16_3 (32'h90c) +`endif +`ifndef PV_REG_PCR_ENTRY_16_4 `define PV_REG_PCR_ENTRY_16_4 (32'h910) +`endif +`ifndef PV_REG_PCR_ENTRY_16_5 `define PV_REG_PCR_ENTRY_16_5 (32'h914) +`endif +`ifndef PV_REG_PCR_ENTRY_16_6 `define PV_REG_PCR_ENTRY_16_6 (32'h918) +`endif +`ifndef PV_REG_PCR_ENTRY_16_7 `define PV_REG_PCR_ENTRY_16_7 (32'h91c) +`endif +`ifndef PV_REG_PCR_ENTRY_16_8 `define PV_REG_PCR_ENTRY_16_8 (32'h920) +`endif +`ifndef PV_REG_PCR_ENTRY_16_9 `define PV_REG_PCR_ENTRY_16_9 (32'h924) +`endif +`ifndef PV_REG_PCR_ENTRY_16_10 `define PV_REG_PCR_ENTRY_16_10 (32'h928) +`endif +`ifndef PV_REG_PCR_ENTRY_16_11 `define PV_REG_PCR_ENTRY_16_11 (32'h92c) +`endif +`ifndef PV_REG_PCR_ENTRY_17_0 `define PV_REG_PCR_ENTRY_17_0 (32'h930) +`endif +`ifndef PV_REG_PCR_ENTRY_17_1 `define PV_REG_PCR_ENTRY_17_1 (32'h934) +`endif +`ifndef PV_REG_PCR_ENTRY_17_2 `define PV_REG_PCR_ENTRY_17_2 (32'h938) +`endif +`ifndef PV_REG_PCR_ENTRY_17_3 `define PV_REG_PCR_ENTRY_17_3 (32'h93c) +`endif +`ifndef PV_REG_PCR_ENTRY_17_4 `define PV_REG_PCR_ENTRY_17_4 (32'h940) +`endif +`ifndef PV_REG_PCR_ENTRY_17_5 `define PV_REG_PCR_ENTRY_17_5 (32'h944) +`endif +`ifndef PV_REG_PCR_ENTRY_17_6 `define PV_REG_PCR_ENTRY_17_6 (32'h948) +`endif +`ifndef PV_REG_PCR_ENTRY_17_7 `define PV_REG_PCR_ENTRY_17_7 (32'h94c) +`endif +`ifndef PV_REG_PCR_ENTRY_17_8 `define PV_REG_PCR_ENTRY_17_8 (32'h950) +`endif +`ifndef PV_REG_PCR_ENTRY_17_9 `define PV_REG_PCR_ENTRY_17_9 (32'h954) +`endif +`ifndef PV_REG_PCR_ENTRY_17_10 `define PV_REG_PCR_ENTRY_17_10 (32'h958) +`endif +`ifndef PV_REG_PCR_ENTRY_17_11 `define PV_REG_PCR_ENTRY_17_11 (32'h95c) +`endif +`ifndef PV_REG_PCR_ENTRY_18_0 `define PV_REG_PCR_ENTRY_18_0 (32'h960) +`endif +`ifndef PV_REG_PCR_ENTRY_18_1 `define PV_REG_PCR_ENTRY_18_1 (32'h964) +`endif +`ifndef PV_REG_PCR_ENTRY_18_2 `define PV_REG_PCR_ENTRY_18_2 (32'h968) +`endif +`ifndef PV_REG_PCR_ENTRY_18_3 `define PV_REG_PCR_ENTRY_18_3 (32'h96c) +`endif +`ifndef PV_REG_PCR_ENTRY_18_4 `define PV_REG_PCR_ENTRY_18_4 (32'h970) +`endif +`ifndef PV_REG_PCR_ENTRY_18_5 `define PV_REG_PCR_ENTRY_18_5 (32'h974) +`endif +`ifndef PV_REG_PCR_ENTRY_18_6 `define PV_REG_PCR_ENTRY_18_6 (32'h978) +`endif +`ifndef PV_REG_PCR_ENTRY_18_7 `define PV_REG_PCR_ENTRY_18_7 (32'h97c) +`endif +`ifndef PV_REG_PCR_ENTRY_18_8 `define PV_REG_PCR_ENTRY_18_8 (32'h980) +`endif +`ifndef PV_REG_PCR_ENTRY_18_9 `define PV_REG_PCR_ENTRY_18_9 (32'h984) +`endif +`ifndef PV_REG_PCR_ENTRY_18_10 `define PV_REG_PCR_ENTRY_18_10 (32'h988) +`endif +`ifndef PV_REG_PCR_ENTRY_18_11 `define PV_REG_PCR_ENTRY_18_11 (32'h98c) +`endif +`ifndef PV_REG_PCR_ENTRY_19_0 `define PV_REG_PCR_ENTRY_19_0 (32'h990) +`endif +`ifndef PV_REG_PCR_ENTRY_19_1 `define PV_REG_PCR_ENTRY_19_1 (32'h994) +`endif +`ifndef PV_REG_PCR_ENTRY_19_2 `define PV_REG_PCR_ENTRY_19_2 (32'h998) +`endif +`ifndef PV_REG_PCR_ENTRY_19_3 `define PV_REG_PCR_ENTRY_19_3 (32'h99c) +`endif +`ifndef PV_REG_PCR_ENTRY_19_4 `define PV_REG_PCR_ENTRY_19_4 (32'h9a0) +`endif +`ifndef PV_REG_PCR_ENTRY_19_5 `define PV_REG_PCR_ENTRY_19_5 (32'h9a4) +`endif +`ifndef PV_REG_PCR_ENTRY_19_6 `define PV_REG_PCR_ENTRY_19_6 (32'h9a8) +`endif +`ifndef PV_REG_PCR_ENTRY_19_7 `define PV_REG_PCR_ENTRY_19_7 (32'h9ac) +`endif +`ifndef PV_REG_PCR_ENTRY_19_8 `define PV_REG_PCR_ENTRY_19_8 (32'h9b0) +`endif +`ifndef PV_REG_PCR_ENTRY_19_9 `define PV_REG_PCR_ENTRY_19_9 (32'h9b4) +`endif +`ifndef PV_REG_PCR_ENTRY_19_10 `define PV_REG_PCR_ENTRY_19_10 (32'h9b8) +`endif +`ifndef PV_REG_PCR_ENTRY_19_11 `define PV_REG_PCR_ENTRY_19_11 (32'h9bc) +`endif +`ifndef PV_REG_PCR_ENTRY_20_0 `define PV_REG_PCR_ENTRY_20_0 (32'h9c0) +`endif +`ifndef PV_REG_PCR_ENTRY_20_1 `define PV_REG_PCR_ENTRY_20_1 (32'h9c4) +`endif +`ifndef PV_REG_PCR_ENTRY_20_2 `define PV_REG_PCR_ENTRY_20_2 (32'h9c8) +`endif +`ifndef PV_REG_PCR_ENTRY_20_3 `define PV_REG_PCR_ENTRY_20_3 (32'h9cc) +`endif +`ifndef PV_REG_PCR_ENTRY_20_4 `define PV_REG_PCR_ENTRY_20_4 (32'h9d0) +`endif +`ifndef PV_REG_PCR_ENTRY_20_5 `define PV_REG_PCR_ENTRY_20_5 (32'h9d4) +`endif +`ifndef PV_REG_PCR_ENTRY_20_6 `define PV_REG_PCR_ENTRY_20_6 (32'h9d8) +`endif +`ifndef PV_REG_PCR_ENTRY_20_7 `define PV_REG_PCR_ENTRY_20_7 (32'h9dc) +`endif +`ifndef PV_REG_PCR_ENTRY_20_8 `define PV_REG_PCR_ENTRY_20_8 (32'h9e0) +`endif +`ifndef PV_REG_PCR_ENTRY_20_9 `define PV_REG_PCR_ENTRY_20_9 (32'h9e4) +`endif +`ifndef PV_REG_PCR_ENTRY_20_10 `define PV_REG_PCR_ENTRY_20_10 (32'h9e8) +`endif +`ifndef PV_REG_PCR_ENTRY_20_11 `define PV_REG_PCR_ENTRY_20_11 (32'h9ec) +`endif +`ifndef PV_REG_PCR_ENTRY_21_0 `define PV_REG_PCR_ENTRY_21_0 (32'h9f0) +`endif +`ifndef PV_REG_PCR_ENTRY_21_1 `define PV_REG_PCR_ENTRY_21_1 (32'h9f4) +`endif +`ifndef PV_REG_PCR_ENTRY_21_2 `define PV_REG_PCR_ENTRY_21_2 (32'h9f8) +`endif +`ifndef PV_REG_PCR_ENTRY_21_3 `define PV_REG_PCR_ENTRY_21_3 (32'h9fc) +`endif +`ifndef PV_REG_PCR_ENTRY_21_4 `define PV_REG_PCR_ENTRY_21_4 (32'ha00) +`endif +`ifndef PV_REG_PCR_ENTRY_21_5 `define PV_REG_PCR_ENTRY_21_5 (32'ha04) +`endif +`ifndef PV_REG_PCR_ENTRY_21_6 `define PV_REG_PCR_ENTRY_21_6 (32'ha08) +`endif +`ifndef PV_REG_PCR_ENTRY_21_7 `define PV_REG_PCR_ENTRY_21_7 (32'ha0c) +`endif +`ifndef PV_REG_PCR_ENTRY_21_8 `define PV_REG_PCR_ENTRY_21_8 (32'ha10) +`endif +`ifndef PV_REG_PCR_ENTRY_21_9 `define PV_REG_PCR_ENTRY_21_9 (32'ha14) +`endif +`ifndef PV_REG_PCR_ENTRY_21_10 `define PV_REG_PCR_ENTRY_21_10 (32'ha18) +`endif +`ifndef PV_REG_PCR_ENTRY_21_11 `define PV_REG_PCR_ENTRY_21_11 (32'ha1c) +`endif +`ifndef PV_REG_PCR_ENTRY_22_0 `define PV_REG_PCR_ENTRY_22_0 (32'ha20) +`endif +`ifndef PV_REG_PCR_ENTRY_22_1 `define PV_REG_PCR_ENTRY_22_1 (32'ha24) +`endif +`ifndef PV_REG_PCR_ENTRY_22_2 `define PV_REG_PCR_ENTRY_22_2 (32'ha28) +`endif +`ifndef PV_REG_PCR_ENTRY_22_3 `define PV_REG_PCR_ENTRY_22_3 (32'ha2c) +`endif +`ifndef PV_REG_PCR_ENTRY_22_4 `define PV_REG_PCR_ENTRY_22_4 (32'ha30) +`endif +`ifndef PV_REG_PCR_ENTRY_22_5 `define PV_REG_PCR_ENTRY_22_5 (32'ha34) +`endif +`ifndef PV_REG_PCR_ENTRY_22_6 `define PV_REG_PCR_ENTRY_22_6 (32'ha38) +`endif +`ifndef PV_REG_PCR_ENTRY_22_7 `define PV_REG_PCR_ENTRY_22_7 (32'ha3c) +`endif +`ifndef PV_REG_PCR_ENTRY_22_8 `define PV_REG_PCR_ENTRY_22_8 (32'ha40) +`endif +`ifndef PV_REG_PCR_ENTRY_22_9 `define PV_REG_PCR_ENTRY_22_9 (32'ha44) +`endif +`ifndef PV_REG_PCR_ENTRY_22_10 `define PV_REG_PCR_ENTRY_22_10 (32'ha48) +`endif +`ifndef PV_REG_PCR_ENTRY_22_11 `define PV_REG_PCR_ENTRY_22_11 (32'ha4c) +`endif +`ifndef PV_REG_PCR_ENTRY_23_0 `define PV_REG_PCR_ENTRY_23_0 (32'ha50) +`endif +`ifndef PV_REG_PCR_ENTRY_23_1 `define PV_REG_PCR_ENTRY_23_1 (32'ha54) +`endif +`ifndef PV_REG_PCR_ENTRY_23_2 `define PV_REG_PCR_ENTRY_23_2 (32'ha58) +`endif +`ifndef PV_REG_PCR_ENTRY_23_3 `define PV_REG_PCR_ENTRY_23_3 (32'ha5c) +`endif +`ifndef PV_REG_PCR_ENTRY_23_4 `define PV_REG_PCR_ENTRY_23_4 (32'ha60) +`endif +`ifndef PV_REG_PCR_ENTRY_23_5 `define PV_REG_PCR_ENTRY_23_5 (32'ha64) +`endif +`ifndef PV_REG_PCR_ENTRY_23_6 `define PV_REG_PCR_ENTRY_23_6 (32'ha68) +`endif +`ifndef PV_REG_PCR_ENTRY_23_7 `define PV_REG_PCR_ENTRY_23_7 (32'ha6c) +`endif +`ifndef PV_REG_PCR_ENTRY_23_8 `define PV_REG_PCR_ENTRY_23_8 (32'ha70) +`endif +`ifndef PV_REG_PCR_ENTRY_23_9 `define PV_REG_PCR_ENTRY_23_9 (32'ha74) +`endif +`ifndef PV_REG_PCR_ENTRY_23_10 `define PV_REG_PCR_ENTRY_23_10 (32'ha78) +`endif +`ifndef PV_REG_PCR_ENTRY_23_11 `define PV_REG_PCR_ENTRY_23_11 (32'ha7c) +`endif +`ifndef PV_REG_PCR_ENTRY_24_0 `define PV_REG_PCR_ENTRY_24_0 (32'ha80) +`endif +`ifndef PV_REG_PCR_ENTRY_24_1 `define PV_REG_PCR_ENTRY_24_1 (32'ha84) +`endif +`ifndef PV_REG_PCR_ENTRY_24_2 `define PV_REG_PCR_ENTRY_24_2 (32'ha88) +`endif +`ifndef PV_REG_PCR_ENTRY_24_3 `define PV_REG_PCR_ENTRY_24_3 (32'ha8c) +`endif +`ifndef PV_REG_PCR_ENTRY_24_4 `define PV_REG_PCR_ENTRY_24_4 (32'ha90) +`endif +`ifndef PV_REG_PCR_ENTRY_24_5 `define PV_REG_PCR_ENTRY_24_5 (32'ha94) +`endif +`ifndef PV_REG_PCR_ENTRY_24_6 `define PV_REG_PCR_ENTRY_24_6 (32'ha98) +`endif +`ifndef PV_REG_PCR_ENTRY_24_7 `define PV_REG_PCR_ENTRY_24_7 (32'ha9c) +`endif +`ifndef PV_REG_PCR_ENTRY_24_8 `define PV_REG_PCR_ENTRY_24_8 (32'haa0) +`endif +`ifndef PV_REG_PCR_ENTRY_24_9 `define PV_REG_PCR_ENTRY_24_9 (32'haa4) +`endif +`ifndef PV_REG_PCR_ENTRY_24_10 `define PV_REG_PCR_ENTRY_24_10 (32'haa8) +`endif +`ifndef PV_REG_PCR_ENTRY_24_11 `define PV_REG_PCR_ENTRY_24_11 (32'haac) +`endif +`ifndef PV_REG_PCR_ENTRY_25_0 `define PV_REG_PCR_ENTRY_25_0 (32'hab0) +`endif +`ifndef PV_REG_PCR_ENTRY_25_1 `define PV_REG_PCR_ENTRY_25_1 (32'hab4) +`endif +`ifndef PV_REG_PCR_ENTRY_25_2 `define PV_REG_PCR_ENTRY_25_2 (32'hab8) +`endif +`ifndef PV_REG_PCR_ENTRY_25_3 `define PV_REG_PCR_ENTRY_25_3 (32'habc) +`endif +`ifndef PV_REG_PCR_ENTRY_25_4 `define PV_REG_PCR_ENTRY_25_4 (32'hac0) +`endif +`ifndef PV_REG_PCR_ENTRY_25_5 `define PV_REG_PCR_ENTRY_25_5 (32'hac4) +`endif +`ifndef PV_REG_PCR_ENTRY_25_6 `define PV_REG_PCR_ENTRY_25_6 (32'hac8) +`endif +`ifndef PV_REG_PCR_ENTRY_25_7 `define PV_REG_PCR_ENTRY_25_7 (32'hacc) +`endif +`ifndef PV_REG_PCR_ENTRY_25_8 `define PV_REG_PCR_ENTRY_25_8 (32'had0) +`endif +`ifndef PV_REG_PCR_ENTRY_25_9 `define PV_REG_PCR_ENTRY_25_9 (32'had4) +`endif +`ifndef PV_REG_PCR_ENTRY_25_10 `define PV_REG_PCR_ENTRY_25_10 (32'had8) +`endif +`ifndef PV_REG_PCR_ENTRY_25_11 `define PV_REG_PCR_ENTRY_25_11 (32'hadc) +`endif +`ifndef PV_REG_PCR_ENTRY_26_0 `define PV_REG_PCR_ENTRY_26_0 (32'hae0) +`endif +`ifndef PV_REG_PCR_ENTRY_26_1 `define PV_REG_PCR_ENTRY_26_1 (32'hae4) +`endif +`ifndef PV_REG_PCR_ENTRY_26_2 `define PV_REG_PCR_ENTRY_26_2 (32'hae8) +`endif +`ifndef PV_REG_PCR_ENTRY_26_3 `define PV_REG_PCR_ENTRY_26_3 (32'haec) +`endif +`ifndef PV_REG_PCR_ENTRY_26_4 `define PV_REG_PCR_ENTRY_26_4 (32'haf0) +`endif +`ifndef PV_REG_PCR_ENTRY_26_5 `define PV_REG_PCR_ENTRY_26_5 (32'haf4) +`endif +`ifndef PV_REG_PCR_ENTRY_26_6 `define PV_REG_PCR_ENTRY_26_6 (32'haf8) +`endif +`ifndef PV_REG_PCR_ENTRY_26_7 `define PV_REG_PCR_ENTRY_26_7 (32'hafc) +`endif +`ifndef PV_REG_PCR_ENTRY_26_8 `define PV_REG_PCR_ENTRY_26_8 (32'hb00) +`endif +`ifndef PV_REG_PCR_ENTRY_26_9 `define PV_REG_PCR_ENTRY_26_9 (32'hb04) +`endif +`ifndef PV_REG_PCR_ENTRY_26_10 `define PV_REG_PCR_ENTRY_26_10 (32'hb08) +`endif +`ifndef PV_REG_PCR_ENTRY_26_11 `define PV_REG_PCR_ENTRY_26_11 (32'hb0c) +`endif +`ifndef PV_REG_PCR_ENTRY_27_0 `define PV_REG_PCR_ENTRY_27_0 (32'hb10) +`endif +`ifndef PV_REG_PCR_ENTRY_27_1 `define PV_REG_PCR_ENTRY_27_1 (32'hb14) +`endif +`ifndef PV_REG_PCR_ENTRY_27_2 `define PV_REG_PCR_ENTRY_27_2 (32'hb18) +`endif +`ifndef PV_REG_PCR_ENTRY_27_3 `define PV_REG_PCR_ENTRY_27_3 (32'hb1c) +`endif +`ifndef PV_REG_PCR_ENTRY_27_4 `define PV_REG_PCR_ENTRY_27_4 (32'hb20) +`endif +`ifndef PV_REG_PCR_ENTRY_27_5 `define PV_REG_PCR_ENTRY_27_5 (32'hb24) +`endif +`ifndef PV_REG_PCR_ENTRY_27_6 `define PV_REG_PCR_ENTRY_27_6 (32'hb28) +`endif +`ifndef PV_REG_PCR_ENTRY_27_7 `define PV_REG_PCR_ENTRY_27_7 (32'hb2c) +`endif +`ifndef PV_REG_PCR_ENTRY_27_8 `define PV_REG_PCR_ENTRY_27_8 (32'hb30) +`endif +`ifndef PV_REG_PCR_ENTRY_27_9 `define PV_REG_PCR_ENTRY_27_9 (32'hb34) +`endif +`ifndef PV_REG_PCR_ENTRY_27_10 `define PV_REG_PCR_ENTRY_27_10 (32'hb38) +`endif +`ifndef PV_REG_PCR_ENTRY_27_11 `define PV_REG_PCR_ENTRY_27_11 (32'hb3c) +`endif +`ifndef PV_REG_PCR_ENTRY_28_0 `define PV_REG_PCR_ENTRY_28_0 (32'hb40) +`endif +`ifndef PV_REG_PCR_ENTRY_28_1 `define PV_REG_PCR_ENTRY_28_1 (32'hb44) +`endif +`ifndef PV_REG_PCR_ENTRY_28_2 `define PV_REG_PCR_ENTRY_28_2 (32'hb48) +`endif +`ifndef PV_REG_PCR_ENTRY_28_3 `define PV_REG_PCR_ENTRY_28_3 (32'hb4c) +`endif +`ifndef PV_REG_PCR_ENTRY_28_4 `define PV_REG_PCR_ENTRY_28_4 (32'hb50) +`endif +`ifndef PV_REG_PCR_ENTRY_28_5 `define PV_REG_PCR_ENTRY_28_5 (32'hb54) +`endif +`ifndef PV_REG_PCR_ENTRY_28_6 `define PV_REG_PCR_ENTRY_28_6 (32'hb58) +`endif +`ifndef PV_REG_PCR_ENTRY_28_7 `define PV_REG_PCR_ENTRY_28_7 (32'hb5c) +`endif +`ifndef PV_REG_PCR_ENTRY_28_8 `define PV_REG_PCR_ENTRY_28_8 (32'hb60) +`endif +`ifndef PV_REG_PCR_ENTRY_28_9 `define PV_REG_PCR_ENTRY_28_9 (32'hb64) +`endif +`ifndef PV_REG_PCR_ENTRY_28_10 `define PV_REG_PCR_ENTRY_28_10 (32'hb68) +`endif +`ifndef PV_REG_PCR_ENTRY_28_11 `define PV_REG_PCR_ENTRY_28_11 (32'hb6c) +`endif +`ifndef PV_REG_PCR_ENTRY_29_0 `define PV_REG_PCR_ENTRY_29_0 (32'hb70) +`endif +`ifndef PV_REG_PCR_ENTRY_29_1 `define PV_REG_PCR_ENTRY_29_1 (32'hb74) +`endif +`ifndef PV_REG_PCR_ENTRY_29_2 `define PV_REG_PCR_ENTRY_29_2 (32'hb78) +`endif +`ifndef PV_REG_PCR_ENTRY_29_3 `define PV_REG_PCR_ENTRY_29_3 (32'hb7c) +`endif +`ifndef PV_REG_PCR_ENTRY_29_4 `define PV_REG_PCR_ENTRY_29_4 (32'hb80) +`endif +`ifndef PV_REG_PCR_ENTRY_29_5 `define PV_REG_PCR_ENTRY_29_5 (32'hb84) +`endif +`ifndef PV_REG_PCR_ENTRY_29_6 `define PV_REG_PCR_ENTRY_29_6 (32'hb88) +`endif +`ifndef PV_REG_PCR_ENTRY_29_7 `define PV_REG_PCR_ENTRY_29_7 (32'hb8c) +`endif +`ifndef PV_REG_PCR_ENTRY_29_8 `define PV_REG_PCR_ENTRY_29_8 (32'hb90) +`endif +`ifndef PV_REG_PCR_ENTRY_29_9 `define PV_REG_PCR_ENTRY_29_9 (32'hb94) +`endif +`ifndef PV_REG_PCR_ENTRY_29_10 `define PV_REG_PCR_ENTRY_29_10 (32'hb98) +`endif +`ifndef PV_REG_PCR_ENTRY_29_11 `define PV_REG_PCR_ENTRY_29_11 (32'hb9c) +`endif +`ifndef PV_REG_PCR_ENTRY_30_0 `define PV_REG_PCR_ENTRY_30_0 (32'hba0) +`endif +`ifndef PV_REG_PCR_ENTRY_30_1 `define PV_REG_PCR_ENTRY_30_1 (32'hba4) +`endif +`ifndef PV_REG_PCR_ENTRY_30_2 `define PV_REG_PCR_ENTRY_30_2 (32'hba8) +`endif +`ifndef PV_REG_PCR_ENTRY_30_3 `define PV_REG_PCR_ENTRY_30_3 (32'hbac) +`endif +`ifndef PV_REG_PCR_ENTRY_30_4 `define PV_REG_PCR_ENTRY_30_4 (32'hbb0) +`endif +`ifndef PV_REG_PCR_ENTRY_30_5 `define PV_REG_PCR_ENTRY_30_5 (32'hbb4) +`endif +`ifndef PV_REG_PCR_ENTRY_30_6 `define PV_REG_PCR_ENTRY_30_6 (32'hbb8) +`endif +`ifndef PV_REG_PCR_ENTRY_30_7 `define PV_REG_PCR_ENTRY_30_7 (32'hbbc) +`endif +`ifndef PV_REG_PCR_ENTRY_30_8 `define PV_REG_PCR_ENTRY_30_8 (32'hbc0) +`endif +`ifndef PV_REG_PCR_ENTRY_30_9 `define PV_REG_PCR_ENTRY_30_9 (32'hbc4) +`endif +`ifndef PV_REG_PCR_ENTRY_30_10 `define PV_REG_PCR_ENTRY_30_10 (32'hbc8) +`endif +`ifndef PV_REG_PCR_ENTRY_30_11 `define PV_REG_PCR_ENTRY_30_11 (32'hbcc) +`endif +`ifndef PV_REG_PCR_ENTRY_31_0 `define PV_REG_PCR_ENTRY_31_0 (32'hbd0) +`endif +`ifndef PV_REG_PCR_ENTRY_31_1 `define PV_REG_PCR_ENTRY_31_1 (32'hbd4) +`endif +`ifndef PV_REG_PCR_ENTRY_31_2 `define PV_REG_PCR_ENTRY_31_2 (32'hbd8) +`endif +`ifndef PV_REG_PCR_ENTRY_31_3 `define PV_REG_PCR_ENTRY_31_3 (32'hbdc) +`endif +`ifndef PV_REG_PCR_ENTRY_31_4 `define PV_REG_PCR_ENTRY_31_4 (32'hbe0) +`endif +`ifndef PV_REG_PCR_ENTRY_31_5 `define PV_REG_PCR_ENTRY_31_5 (32'hbe4) +`endif +`ifndef PV_REG_PCR_ENTRY_31_6 `define PV_REG_PCR_ENTRY_31_6 (32'hbe8) +`endif +`ifndef PV_REG_PCR_ENTRY_31_7 `define PV_REG_PCR_ENTRY_31_7 (32'hbec) +`endif +`ifndef PV_REG_PCR_ENTRY_31_8 `define PV_REG_PCR_ENTRY_31_8 (32'hbf0) +`endif +`ifndef PV_REG_PCR_ENTRY_31_9 `define PV_REG_PCR_ENTRY_31_9 (32'hbf4) +`endif +`ifndef PV_REG_PCR_ENTRY_31_10 `define PV_REG_PCR_ENTRY_31_10 (32'hbf8) +`endif +`ifndef PV_REG_PCR_ENTRY_31_11 `define PV_REG_PCR_ENTRY_31_11 (32'hbfc) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_0 `define DV_REG_STICKYDATAVAULTCTRL_0 (32'h0) `define DV_REG_STICKYDATAVAULTCTRL_0_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_0_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_1 `define DV_REG_STICKYDATAVAULTCTRL_1 (32'h4) `define DV_REG_STICKYDATAVAULTCTRL_1_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_1_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_2 `define DV_REG_STICKYDATAVAULTCTRL_2 (32'h8) `define DV_REG_STICKYDATAVAULTCTRL_2_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_2_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_3 `define DV_REG_STICKYDATAVAULTCTRL_3 (32'hc) `define DV_REG_STICKYDATAVAULTCTRL_3_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_3_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_4 `define DV_REG_STICKYDATAVAULTCTRL_4 (32'h10) `define DV_REG_STICKYDATAVAULTCTRL_4_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_4_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_5 `define DV_REG_STICKYDATAVAULTCTRL_5 (32'h14) `define DV_REG_STICKYDATAVAULTCTRL_5_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_5_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_6 `define DV_REG_STICKYDATAVAULTCTRL_6 (32'h18) `define DV_REG_STICKYDATAVAULTCTRL_6_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_6_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_7 `define DV_REG_STICKYDATAVAULTCTRL_7 (32'h1c) `define DV_REG_STICKYDATAVAULTCTRL_7_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_7_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_8 `define DV_REG_STICKYDATAVAULTCTRL_8 (32'h20) `define DV_REG_STICKYDATAVAULTCTRL_8_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_8_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYDATAVAULTCTRL_9 `define DV_REG_STICKYDATAVAULTCTRL_9 (32'h24) `define DV_REG_STICKYDATAVAULTCTRL_9_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYDATAVAULTCTRL_9_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_0 (32'h28) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_1 (32'h2c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_2 (32'h30) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_3 (32'h34) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_4 (32'h38) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_5 (32'h3c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_6 (32'h40) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_7 (32'h44) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_8 (32'h48) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_9 (32'h4c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_10 (32'h50) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_0_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_0_11 (32'h54) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_0 (32'h58) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_1 (32'h5c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_2 (32'h60) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_3 (32'h64) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_4 (32'h68) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_5 (32'h6c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_6 (32'h70) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_7 (32'h74) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_8 (32'h78) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_9 (32'h7c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_10 (32'h80) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_1_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_1_11 (32'h84) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_0 (32'h88) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_1 (32'h8c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_2 (32'h90) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_3 (32'h94) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_4 (32'h98) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_5 (32'h9c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_6 (32'ha0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_7 (32'ha4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_8 (32'ha8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_9 (32'hac) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_10 (32'hb0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_2_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_2_11 (32'hb4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_0 (32'hb8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_1 (32'hbc) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_2 (32'hc0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_3 (32'hc4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_4 (32'hc8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_5 (32'hcc) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_6 (32'hd0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_7 (32'hd4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_8 (32'hd8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_9 (32'hdc) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_10 (32'he0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_3_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_3_11 (32'he4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_0 (32'he8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_1 (32'hec) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_2 (32'hf0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_3 (32'hf4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_4 (32'hf8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_5 (32'hfc) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_6 (32'h100) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_7 (32'h104) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_8 (32'h108) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_9 (32'h10c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_10 (32'h110) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_4_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_4_11 (32'h114) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_0 (32'h118) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_1 (32'h11c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_2 (32'h120) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_3 (32'h124) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_4 (32'h128) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_5 (32'h12c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_6 (32'h130) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_7 (32'h134) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_8 (32'h138) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_9 (32'h13c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_10 (32'h140) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_5_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_5_11 (32'h144) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_0 (32'h148) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_1 (32'h14c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_2 (32'h150) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_3 (32'h154) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_4 (32'h158) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_5 (32'h15c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_6 (32'h160) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_7 (32'h164) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_8 (32'h168) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_9 (32'h16c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_10 (32'h170) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_6_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_6_11 (32'h174) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_0 (32'h178) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_1 (32'h17c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_2 (32'h180) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_3 (32'h184) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_4 (32'h188) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_5 (32'h18c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_6 (32'h190) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_7 (32'h194) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_8 (32'h198) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_9 (32'h19c) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_10 (32'h1a0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_7_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_7_11 (32'h1a4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_0 (32'h1a8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_1 (32'h1ac) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_2 (32'h1b0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_3 (32'h1b4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_4 (32'h1b8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_5 (32'h1bc) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_6 (32'h1c0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_7 (32'h1c4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_8 (32'h1c8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_9 (32'h1cc) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_10 (32'h1d0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_8_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_8_11 (32'h1d4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_0 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_0 (32'h1d8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_1 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_1 (32'h1dc) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_2 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_2 (32'h1e0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_3 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_3 (32'h1e4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_4 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_4 (32'h1e8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_5 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_5 (32'h1ec) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_6 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_6 (32'h1f0) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_7 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_7 (32'h1f4) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_8 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_8 (32'h1f8) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_9 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_9 (32'h1fc) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_10 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_10 (32'h200) +`endif +`ifndef DV_REG_STICKY_DATA_VAULT_ENTRY_9_11 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_11 (32'h204) +`endif +`ifndef DV_REG_DATAVAULTCTRL_0 `define DV_REG_DATAVAULTCTRL_0 (32'h208) `define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_1 `define DV_REG_DATAVAULTCTRL_1 (32'h20c) `define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_2 `define DV_REG_DATAVAULTCTRL_2 (32'h210) `define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_3 `define DV_REG_DATAVAULTCTRL_3 (32'h214) `define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_4 `define DV_REG_DATAVAULTCTRL_4 (32'h218) `define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_5 `define DV_REG_DATAVAULTCTRL_5 (32'h21c) `define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_6 `define DV_REG_DATAVAULTCTRL_6 (32'h220) `define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_7 `define DV_REG_DATAVAULTCTRL_7 (32'h224) `define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_8 `define DV_REG_DATAVAULTCTRL_8 (32'h228) `define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATAVAULTCTRL_9 `define DV_REG_DATAVAULTCTRL_9 (32'h22c) `define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_LOW (0) `define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_0 `define DV_REG_DATA_VAULT_ENTRY_0_0 (32'h230) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_1 `define DV_REG_DATA_VAULT_ENTRY_0_1 (32'h234) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_2 `define DV_REG_DATA_VAULT_ENTRY_0_2 (32'h238) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_3 `define DV_REG_DATA_VAULT_ENTRY_0_3 (32'h23c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_4 `define DV_REG_DATA_VAULT_ENTRY_0_4 (32'h240) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_5 `define DV_REG_DATA_VAULT_ENTRY_0_5 (32'h244) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_6 `define DV_REG_DATA_VAULT_ENTRY_0_6 (32'h248) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_7 `define DV_REG_DATA_VAULT_ENTRY_0_7 (32'h24c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_8 `define DV_REG_DATA_VAULT_ENTRY_0_8 (32'h250) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_9 `define DV_REG_DATA_VAULT_ENTRY_0_9 (32'h254) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_10 `define DV_REG_DATA_VAULT_ENTRY_0_10 (32'h258) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_0_11 `define DV_REG_DATA_VAULT_ENTRY_0_11 (32'h25c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_0 `define DV_REG_DATA_VAULT_ENTRY_1_0 (32'h260) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_1 `define DV_REG_DATA_VAULT_ENTRY_1_1 (32'h264) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_2 `define DV_REG_DATA_VAULT_ENTRY_1_2 (32'h268) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_3 `define DV_REG_DATA_VAULT_ENTRY_1_3 (32'h26c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_4 `define DV_REG_DATA_VAULT_ENTRY_1_4 (32'h270) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_5 `define DV_REG_DATA_VAULT_ENTRY_1_5 (32'h274) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_6 `define DV_REG_DATA_VAULT_ENTRY_1_6 (32'h278) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_7 `define DV_REG_DATA_VAULT_ENTRY_1_7 (32'h27c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_8 `define DV_REG_DATA_VAULT_ENTRY_1_8 (32'h280) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_9 `define DV_REG_DATA_VAULT_ENTRY_1_9 (32'h284) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_10 `define DV_REG_DATA_VAULT_ENTRY_1_10 (32'h288) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_1_11 `define DV_REG_DATA_VAULT_ENTRY_1_11 (32'h28c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_0 `define DV_REG_DATA_VAULT_ENTRY_2_0 (32'h290) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_1 `define DV_REG_DATA_VAULT_ENTRY_2_1 (32'h294) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_2 `define DV_REG_DATA_VAULT_ENTRY_2_2 (32'h298) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_3 `define DV_REG_DATA_VAULT_ENTRY_2_3 (32'h29c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_4 `define DV_REG_DATA_VAULT_ENTRY_2_4 (32'h2a0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_5 `define DV_REG_DATA_VAULT_ENTRY_2_5 (32'h2a4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_6 `define DV_REG_DATA_VAULT_ENTRY_2_6 (32'h2a8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_7 `define DV_REG_DATA_VAULT_ENTRY_2_7 (32'h2ac) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_8 `define DV_REG_DATA_VAULT_ENTRY_2_8 (32'h2b0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_9 `define DV_REG_DATA_VAULT_ENTRY_2_9 (32'h2b4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_10 `define DV_REG_DATA_VAULT_ENTRY_2_10 (32'h2b8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_2_11 `define DV_REG_DATA_VAULT_ENTRY_2_11 (32'h2bc) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_0 `define DV_REG_DATA_VAULT_ENTRY_3_0 (32'h2c0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_1 `define DV_REG_DATA_VAULT_ENTRY_3_1 (32'h2c4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_2 `define DV_REG_DATA_VAULT_ENTRY_3_2 (32'h2c8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_3 `define DV_REG_DATA_VAULT_ENTRY_3_3 (32'h2cc) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_4 `define DV_REG_DATA_VAULT_ENTRY_3_4 (32'h2d0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_5 `define DV_REG_DATA_VAULT_ENTRY_3_5 (32'h2d4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_6 `define DV_REG_DATA_VAULT_ENTRY_3_6 (32'h2d8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_7 `define DV_REG_DATA_VAULT_ENTRY_3_7 (32'h2dc) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_8 `define DV_REG_DATA_VAULT_ENTRY_3_8 (32'h2e0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_9 `define DV_REG_DATA_VAULT_ENTRY_3_9 (32'h2e4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_10 `define DV_REG_DATA_VAULT_ENTRY_3_10 (32'h2e8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_3_11 `define DV_REG_DATA_VAULT_ENTRY_3_11 (32'h2ec) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_0 `define DV_REG_DATA_VAULT_ENTRY_4_0 (32'h2f0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_1 `define DV_REG_DATA_VAULT_ENTRY_4_1 (32'h2f4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_2 `define DV_REG_DATA_VAULT_ENTRY_4_2 (32'h2f8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_3 `define DV_REG_DATA_VAULT_ENTRY_4_3 (32'h2fc) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_4 `define DV_REG_DATA_VAULT_ENTRY_4_4 (32'h300) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_5 `define DV_REG_DATA_VAULT_ENTRY_4_5 (32'h304) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_6 `define DV_REG_DATA_VAULT_ENTRY_4_6 (32'h308) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_7 `define DV_REG_DATA_VAULT_ENTRY_4_7 (32'h30c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_8 `define DV_REG_DATA_VAULT_ENTRY_4_8 (32'h310) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_9 `define DV_REG_DATA_VAULT_ENTRY_4_9 (32'h314) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_10 `define DV_REG_DATA_VAULT_ENTRY_4_10 (32'h318) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_4_11 `define DV_REG_DATA_VAULT_ENTRY_4_11 (32'h31c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_0 `define DV_REG_DATA_VAULT_ENTRY_5_0 (32'h320) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_1 `define DV_REG_DATA_VAULT_ENTRY_5_1 (32'h324) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_2 `define DV_REG_DATA_VAULT_ENTRY_5_2 (32'h328) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_3 `define DV_REG_DATA_VAULT_ENTRY_5_3 (32'h32c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_4 `define DV_REG_DATA_VAULT_ENTRY_5_4 (32'h330) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_5 `define DV_REG_DATA_VAULT_ENTRY_5_5 (32'h334) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_6 `define DV_REG_DATA_VAULT_ENTRY_5_6 (32'h338) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_7 `define DV_REG_DATA_VAULT_ENTRY_5_7 (32'h33c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_8 `define DV_REG_DATA_VAULT_ENTRY_5_8 (32'h340) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_9 `define DV_REG_DATA_VAULT_ENTRY_5_9 (32'h344) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_10 `define DV_REG_DATA_VAULT_ENTRY_5_10 (32'h348) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_5_11 `define DV_REG_DATA_VAULT_ENTRY_5_11 (32'h34c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_0 `define DV_REG_DATA_VAULT_ENTRY_6_0 (32'h350) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_1 `define DV_REG_DATA_VAULT_ENTRY_6_1 (32'h354) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_2 `define DV_REG_DATA_VAULT_ENTRY_6_2 (32'h358) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_3 `define DV_REG_DATA_VAULT_ENTRY_6_3 (32'h35c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_4 `define DV_REG_DATA_VAULT_ENTRY_6_4 (32'h360) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_5 `define DV_REG_DATA_VAULT_ENTRY_6_5 (32'h364) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_6 `define DV_REG_DATA_VAULT_ENTRY_6_6 (32'h368) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_7 `define DV_REG_DATA_VAULT_ENTRY_6_7 (32'h36c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_8 `define DV_REG_DATA_VAULT_ENTRY_6_8 (32'h370) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_9 `define DV_REG_DATA_VAULT_ENTRY_6_9 (32'h374) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_10 `define DV_REG_DATA_VAULT_ENTRY_6_10 (32'h378) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_6_11 `define DV_REG_DATA_VAULT_ENTRY_6_11 (32'h37c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_0 `define DV_REG_DATA_VAULT_ENTRY_7_0 (32'h380) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_1 `define DV_REG_DATA_VAULT_ENTRY_7_1 (32'h384) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_2 `define DV_REG_DATA_VAULT_ENTRY_7_2 (32'h388) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_3 `define DV_REG_DATA_VAULT_ENTRY_7_3 (32'h38c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_4 `define DV_REG_DATA_VAULT_ENTRY_7_4 (32'h390) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_5 `define DV_REG_DATA_VAULT_ENTRY_7_5 (32'h394) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_6 `define DV_REG_DATA_VAULT_ENTRY_7_6 (32'h398) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_7 `define DV_REG_DATA_VAULT_ENTRY_7_7 (32'h39c) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_8 `define DV_REG_DATA_VAULT_ENTRY_7_8 (32'h3a0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_9 `define DV_REG_DATA_VAULT_ENTRY_7_9 (32'h3a4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_10 `define DV_REG_DATA_VAULT_ENTRY_7_10 (32'h3a8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_7_11 `define DV_REG_DATA_VAULT_ENTRY_7_11 (32'h3ac) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_0 `define DV_REG_DATA_VAULT_ENTRY_8_0 (32'h3b0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_1 `define DV_REG_DATA_VAULT_ENTRY_8_1 (32'h3b4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_2 `define DV_REG_DATA_VAULT_ENTRY_8_2 (32'h3b8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_3 `define DV_REG_DATA_VAULT_ENTRY_8_3 (32'h3bc) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_4 `define DV_REG_DATA_VAULT_ENTRY_8_4 (32'h3c0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_5 `define DV_REG_DATA_VAULT_ENTRY_8_5 (32'h3c4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_6 `define DV_REG_DATA_VAULT_ENTRY_8_6 (32'h3c8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_7 `define DV_REG_DATA_VAULT_ENTRY_8_7 (32'h3cc) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_8 `define DV_REG_DATA_VAULT_ENTRY_8_8 (32'h3d0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_9 `define DV_REG_DATA_VAULT_ENTRY_8_9 (32'h3d4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_10 `define DV_REG_DATA_VAULT_ENTRY_8_10 (32'h3d8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_8_11 `define DV_REG_DATA_VAULT_ENTRY_8_11 (32'h3dc) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_0 `define DV_REG_DATA_VAULT_ENTRY_9_0 (32'h3e0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_1 `define DV_REG_DATA_VAULT_ENTRY_9_1 (32'h3e4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_2 `define DV_REG_DATA_VAULT_ENTRY_9_2 (32'h3e8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_3 `define DV_REG_DATA_VAULT_ENTRY_9_3 (32'h3ec) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_4 `define DV_REG_DATA_VAULT_ENTRY_9_4 (32'h3f0) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_5 `define DV_REG_DATA_VAULT_ENTRY_9_5 (32'h3f4) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_6 `define DV_REG_DATA_VAULT_ENTRY_9_6 (32'h3f8) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_7 `define DV_REG_DATA_VAULT_ENTRY_9_7 (32'h3fc) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_8 `define DV_REG_DATA_VAULT_ENTRY_9_8 (32'h400) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_9 `define DV_REG_DATA_VAULT_ENTRY_9_9 (32'h404) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_10 `define DV_REG_DATA_VAULT_ENTRY_9_10 (32'h408) +`endif +`ifndef DV_REG_DATA_VAULT_ENTRY_9_11 `define DV_REG_DATA_VAULT_ENTRY_9_11 (32'h40c) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_0 `define DV_REG_LOCKABLESCRATCHREGCTRL_0 (32'h410) `define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_1 `define DV_REG_LOCKABLESCRATCHREGCTRL_1 (32'h414) `define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_2 `define DV_REG_LOCKABLESCRATCHREGCTRL_2 (32'h418) `define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_3 `define DV_REG_LOCKABLESCRATCHREGCTRL_3 (32'h41c) `define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_4 `define DV_REG_LOCKABLESCRATCHREGCTRL_4 (32'h420) `define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_5 `define DV_REG_LOCKABLESCRATCHREGCTRL_5 (32'h424) `define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_6 `define DV_REG_LOCKABLESCRATCHREGCTRL_6 (32'h428) `define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_7 `define DV_REG_LOCKABLESCRATCHREGCTRL_7 (32'h42c) `define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_8 `define DV_REG_LOCKABLESCRATCHREGCTRL_8 (32'h430) `define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREGCTRL_9 `define DV_REG_LOCKABLESCRATCHREGCTRL_9 (32'h434) `define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_LOW (0) `define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_0 `define DV_REG_LOCKABLESCRATCHREG_0 (32'h438) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_1 `define DV_REG_LOCKABLESCRATCHREG_1 (32'h43c) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_2 `define DV_REG_LOCKABLESCRATCHREG_2 (32'h440) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_3 `define DV_REG_LOCKABLESCRATCHREG_3 (32'h444) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_4 `define DV_REG_LOCKABLESCRATCHREG_4 (32'h448) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_5 `define DV_REG_LOCKABLESCRATCHREG_5 (32'h44c) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_6 `define DV_REG_LOCKABLESCRATCHREG_6 (32'h450) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_7 `define DV_REG_LOCKABLESCRATCHREG_7 (32'h454) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_8 `define DV_REG_LOCKABLESCRATCHREG_8 (32'h458) +`endif +`ifndef DV_REG_LOCKABLESCRATCHREG_9 `define DV_REG_LOCKABLESCRATCHREG_9 (32'h45c) +`endif +`ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_0 `define DV_REG_NONSTICKYGENERICSCRATCHREG_0 (32'h460) +`endif +`ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_1 `define DV_REG_NONSTICKYGENERICSCRATCHREG_1 (32'h464) +`endif +`ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_2 `define DV_REG_NONSTICKYGENERICSCRATCHREG_2 (32'h468) +`endif +`ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_3 `define DV_REG_NONSTICKYGENERICSCRATCHREG_3 (32'h46c) +`endif +`ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_4 `define DV_REG_NONSTICKYGENERICSCRATCHREG_4 (32'h470) +`endif +`ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_5 `define DV_REG_NONSTICKYGENERICSCRATCHREG_5 (32'h474) +`endif +`ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_6 `define DV_REG_NONSTICKYGENERICSCRATCHREG_6 (32'h478) +`endif +`ifndef DV_REG_NONSTICKYGENERICSCRATCHREG_7 `define DV_REG_NONSTICKYGENERICSCRATCHREG_7 (32'h47c) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0 `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0 (32'h480) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1 `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1 (32'h484) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2 `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2 (32'h488) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3 `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3 (32'h48c) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4 `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4 (32'h490) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5 `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5 (32'h494) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6 `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6 (32'h498) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7 `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7 (32'h49c) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW (0) `define DV_REG_STICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK (32'h1) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREG_0 `define DV_REG_STICKYLOCKABLESCRATCHREG_0 (32'h4a0) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREG_1 `define DV_REG_STICKYLOCKABLESCRATCHREG_1 (32'h4a4) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREG_2 `define DV_REG_STICKYLOCKABLESCRATCHREG_2 (32'h4a8) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREG_3 `define DV_REG_STICKYLOCKABLESCRATCHREG_3 (32'h4ac) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREG_4 `define DV_REG_STICKYLOCKABLESCRATCHREG_4 (32'h4b0) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREG_5 `define DV_REG_STICKYLOCKABLESCRATCHREG_5 (32'h4b4) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREG_6 `define DV_REG_STICKYLOCKABLESCRATCHREG_6 (32'h4b8) +`endif +`ifndef DV_REG_STICKYLOCKABLESCRATCHREG_7 `define DV_REG_STICKYLOCKABLESCRATCHREG_7 (32'h4bc) +`endif +`ifndef SHA512_REG_SHA512_NAME_0 `define SHA512_REG_SHA512_NAME_0 (32'h0) +`endif +`ifndef SHA512_REG_SHA512_NAME_1 `define SHA512_REG_SHA512_NAME_1 (32'h4) +`endif +`ifndef SHA512_REG_SHA512_VERSION_0 `define SHA512_REG_SHA512_VERSION_0 (32'h8) +`endif +`ifndef SHA512_REG_SHA512_VERSION_1 `define SHA512_REG_SHA512_VERSION_1 (32'hc) +`endif +`ifndef SHA512_REG_SHA512_CTRL `define SHA512_REG_SHA512_CTRL (32'h10) `define SHA512_REG_SHA512_CTRL_INIT_LOW (0) `define SHA512_REG_SHA512_CTRL_INIT_MASK (32'h1) @@ -2566,59 +5553,159 @@ `define SHA512_REG_SHA512_CTRL_LAST_MASK (32'h20) `define SHA512_REG_SHA512_CTRL_RESTORE_LOW (6) `define SHA512_REG_SHA512_CTRL_RESTORE_MASK (32'h40) +`endif +`ifndef SHA512_REG_SHA512_STATUS `define SHA512_REG_SHA512_STATUS (32'h18) `define SHA512_REG_SHA512_STATUS_READY_LOW (0) `define SHA512_REG_SHA512_STATUS_READY_MASK (32'h1) `define SHA512_REG_SHA512_STATUS_VALID_LOW (1) `define SHA512_REG_SHA512_STATUS_VALID_MASK (32'h2) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_0 `define SHA512_REG_SHA512_BLOCK_0 (32'h80) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_1 `define SHA512_REG_SHA512_BLOCK_1 (32'h84) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_2 `define SHA512_REG_SHA512_BLOCK_2 (32'h88) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_3 `define SHA512_REG_SHA512_BLOCK_3 (32'h8c) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_4 `define SHA512_REG_SHA512_BLOCK_4 (32'h90) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_5 `define SHA512_REG_SHA512_BLOCK_5 (32'h94) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_6 `define SHA512_REG_SHA512_BLOCK_6 (32'h98) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_7 `define SHA512_REG_SHA512_BLOCK_7 (32'h9c) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_8 `define SHA512_REG_SHA512_BLOCK_8 (32'ha0) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_9 `define SHA512_REG_SHA512_BLOCK_9 (32'ha4) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_10 `define SHA512_REG_SHA512_BLOCK_10 (32'ha8) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_11 `define SHA512_REG_SHA512_BLOCK_11 (32'hac) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_12 `define SHA512_REG_SHA512_BLOCK_12 (32'hb0) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_13 `define SHA512_REG_SHA512_BLOCK_13 (32'hb4) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_14 `define SHA512_REG_SHA512_BLOCK_14 (32'hb8) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_15 `define SHA512_REG_SHA512_BLOCK_15 (32'hbc) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_16 `define SHA512_REG_SHA512_BLOCK_16 (32'hc0) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_17 `define SHA512_REG_SHA512_BLOCK_17 (32'hc4) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_18 `define SHA512_REG_SHA512_BLOCK_18 (32'hc8) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_19 `define SHA512_REG_SHA512_BLOCK_19 (32'hcc) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_20 `define SHA512_REG_SHA512_BLOCK_20 (32'hd0) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_21 `define SHA512_REG_SHA512_BLOCK_21 (32'hd4) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_22 `define SHA512_REG_SHA512_BLOCK_22 (32'hd8) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_23 `define SHA512_REG_SHA512_BLOCK_23 (32'hdc) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_24 `define SHA512_REG_SHA512_BLOCK_24 (32'he0) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_25 `define SHA512_REG_SHA512_BLOCK_25 (32'he4) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_26 `define SHA512_REG_SHA512_BLOCK_26 (32'he8) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_27 `define SHA512_REG_SHA512_BLOCK_27 (32'hec) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_28 `define SHA512_REG_SHA512_BLOCK_28 (32'hf0) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_29 `define SHA512_REG_SHA512_BLOCK_29 (32'hf4) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_30 `define SHA512_REG_SHA512_BLOCK_30 (32'hf8) +`endif +`ifndef SHA512_REG_SHA512_BLOCK_31 `define SHA512_REG_SHA512_BLOCK_31 (32'hfc) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_0 `define SHA512_REG_SHA512_DIGEST_0 (32'h100) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_1 `define SHA512_REG_SHA512_DIGEST_1 (32'h104) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_2 `define SHA512_REG_SHA512_DIGEST_2 (32'h108) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_3 `define SHA512_REG_SHA512_DIGEST_3 (32'h10c) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_4 `define SHA512_REG_SHA512_DIGEST_4 (32'h110) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_5 `define SHA512_REG_SHA512_DIGEST_5 (32'h114) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_6 `define SHA512_REG_SHA512_DIGEST_6 (32'h118) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_7 `define SHA512_REG_SHA512_DIGEST_7 (32'h11c) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_8 `define SHA512_REG_SHA512_DIGEST_8 (32'h120) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_9 `define SHA512_REG_SHA512_DIGEST_9 (32'h124) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_10 `define SHA512_REG_SHA512_DIGEST_10 (32'h128) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_11 `define SHA512_REG_SHA512_DIGEST_11 (32'h12c) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_12 `define SHA512_REG_SHA512_DIGEST_12 (32'h130) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_13 `define SHA512_REG_SHA512_DIGEST_13 (32'h134) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_14 `define SHA512_REG_SHA512_DIGEST_14 (32'h138) +`endif +`ifndef SHA512_REG_SHA512_DIGEST_15 `define SHA512_REG_SHA512_DIGEST_15 (32'h13c) +`endif +`ifndef SHA512_REG_SHA512_VAULT_RD_CTRL `define SHA512_REG_SHA512_VAULT_RD_CTRL (32'h600) `define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_EN_LOW (0) `define SHA512_REG_SHA512_VAULT_RD_CTRL_READ_EN_MASK (32'h1) @@ -2628,6 +5715,8 @@ `define SHA512_REG_SHA512_VAULT_RD_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define SHA512_REG_SHA512_VAULT_RD_CTRL_RSVD_LOW (7) `define SHA512_REG_SHA512_VAULT_RD_CTRL_RSVD_MASK (32'hffffff80) +`endif +`ifndef SHA512_REG_SHA512_VAULT_RD_STATUS `define SHA512_REG_SHA512_VAULT_RD_STATUS (32'h604) `define SHA512_REG_SHA512_VAULT_RD_STATUS_READY_LOW (0) `define SHA512_REG_SHA512_VAULT_RD_STATUS_READY_MASK (32'h1) @@ -2635,6 +5724,8 @@ `define SHA512_REG_SHA512_VAULT_RD_STATUS_VALID_MASK (32'h2) `define SHA512_REG_SHA512_VAULT_RD_STATUS_ERROR_LOW (2) `define SHA512_REG_SHA512_VAULT_RD_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef SHA512_REG_SHA512_KV_WR_CTRL `define SHA512_REG_SHA512_KV_WR_CTRL (32'h608) `define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_EN_LOW (0) `define SHA512_REG_SHA512_KV_WR_CTRL_WRITE_EN_MASK (32'h1) @@ -2654,6 +5745,8 @@ `define SHA512_REG_SHA512_KV_WR_CTRL_AES_KEY_DEST_VALID_MASK (32'h800) `define SHA512_REG_SHA512_KV_WR_CTRL_RSVD_LOW (12) `define SHA512_REG_SHA512_KV_WR_CTRL_RSVD_MASK (32'hfffff000) +`endif +`ifndef SHA512_REG_SHA512_KV_WR_STATUS `define SHA512_REG_SHA512_KV_WR_STATUS (32'h60c) `define SHA512_REG_SHA512_KV_WR_STATUS_READY_LOW (0) `define SHA512_REG_SHA512_KV_WR_STATUS_READY_MASK (32'h1) @@ -2661,43 +5754,99 @@ `define SHA512_REG_SHA512_KV_WR_STATUS_VALID_MASK (32'h2) `define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_LOW (2) `define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0 `define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0 (32'h610) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1 `define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1 (32'h614) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2 `define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2 (32'h618) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3 `define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3 (32'h61c) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4 `define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4 (32'h620) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5 `define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5 (32'h624) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6 `define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6 (32'h628) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7 `define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7 (32'h62c) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_CTRL `define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL (32'h630) `define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_LOW (0) `define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_MASK (32'h1) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_STATUS `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS (32'h634) `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_LOW (0) `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_MASK (32'h1) `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_LOW (1) `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_MASK (32'h2) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0 (32'h638) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1 (32'h63c) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2 (32'h640) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3 (32'h644) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4 (32'h648) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5 (32'h64c) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6 (32'h650) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7 (32'h654) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8 (32'h658) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9 (32'h65c) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10 (32'h660) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11 (32'h664) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_12 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_12 (32'h668) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_13 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_13 (32'h66c) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_14 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_14 (32'h670) +`endif +`ifndef SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_15 `define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_15 (32'h674) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) @@ -2707,15 +5856,23 @@ `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) @@ -2725,9 +5882,13 @@ `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) @@ -2737,33 +5898,65 @@ `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) `define SHA512_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R `define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R `define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R `define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R `define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R `define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R `define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) `define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R `define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) `define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R `define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) `define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R `define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) `define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R `define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA256_REG_SHA256_NAME_0 `define SHA256_REG_SHA256_NAME_0 (32'h0) +`endif +`ifndef SHA256_REG_SHA256_NAME_1 `define SHA256_REG_SHA256_NAME_1 (32'h4) +`endif +`ifndef SHA256_REG_SHA256_VERSION_0 `define SHA256_REG_SHA256_VERSION_0 (32'h8) +`endif +`ifndef SHA256_REG_SHA256_VERSION_1 `define SHA256_REG_SHA256_VERSION_1 (32'hc) +`endif +`ifndef SHA256_REG_SHA256_CTRL `define SHA256_REG_SHA256_CTRL (32'h10) `define SHA256_REG_SHA256_CTRL_INIT_LOW (0) `define SHA256_REG_SHA256_CTRL_INIT_MASK (32'h1) @@ -2779,6 +5972,8 @@ `define SHA256_REG_SHA256_CTRL_WNTZ_W_MASK (32'h1e0) `define SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_LOW (9) `define SHA256_REG_SHA256_CTRL_WNTZ_N_MODE_MASK (32'h200) +`endif +`ifndef SHA256_REG_SHA256_STATUS `define SHA256_REG_SHA256_STATUS (32'h18) `define SHA256_REG_SHA256_STATUS_READY_LOW (0) `define SHA256_REG_SHA256_STATUS_READY_MASK (32'h1) @@ -2786,35 +5981,87 @@ `define SHA256_REG_SHA256_STATUS_VALID_MASK (32'h2) `define SHA256_REG_SHA256_STATUS_WNTZ_BUSY_LOW (2) `define SHA256_REG_SHA256_STATUS_WNTZ_BUSY_MASK (32'h4) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_0 `define SHA256_REG_SHA256_BLOCK_0 (32'h80) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_1 `define SHA256_REG_SHA256_BLOCK_1 (32'h84) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_2 `define SHA256_REG_SHA256_BLOCK_2 (32'h88) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_3 `define SHA256_REG_SHA256_BLOCK_3 (32'h8c) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_4 `define SHA256_REG_SHA256_BLOCK_4 (32'h90) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_5 `define SHA256_REG_SHA256_BLOCK_5 (32'h94) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_6 `define SHA256_REG_SHA256_BLOCK_6 (32'h98) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_7 `define SHA256_REG_SHA256_BLOCK_7 (32'h9c) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_8 `define SHA256_REG_SHA256_BLOCK_8 (32'ha0) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_9 `define SHA256_REG_SHA256_BLOCK_9 (32'ha4) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_10 `define SHA256_REG_SHA256_BLOCK_10 (32'ha8) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_11 `define SHA256_REG_SHA256_BLOCK_11 (32'hac) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_12 `define SHA256_REG_SHA256_BLOCK_12 (32'hb0) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_13 `define SHA256_REG_SHA256_BLOCK_13 (32'hb4) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_14 `define SHA256_REG_SHA256_BLOCK_14 (32'hb8) +`endif +`ifndef SHA256_REG_SHA256_BLOCK_15 `define SHA256_REG_SHA256_BLOCK_15 (32'hbc) +`endif +`ifndef SHA256_REG_SHA256_DIGEST_0 `define SHA256_REG_SHA256_DIGEST_0 (32'h100) +`endif +`ifndef SHA256_REG_SHA256_DIGEST_1 `define SHA256_REG_SHA256_DIGEST_1 (32'h104) +`endif +`ifndef SHA256_REG_SHA256_DIGEST_2 `define SHA256_REG_SHA256_DIGEST_2 (32'h108) +`endif +`ifndef SHA256_REG_SHA256_DIGEST_3 `define SHA256_REG_SHA256_DIGEST_3 (32'h10c) +`endif +`ifndef SHA256_REG_SHA256_DIGEST_4 `define SHA256_REG_SHA256_DIGEST_4 (32'h110) +`endif +`ifndef SHA256_REG_SHA256_DIGEST_5 `define SHA256_REG_SHA256_DIGEST_5 (32'h114) +`endif +`ifndef SHA256_REG_SHA256_DIGEST_6 `define SHA256_REG_SHA256_DIGEST_6 (32'h118) +`endif +`ifndef SHA256_REG_SHA256_DIGEST_7 `define SHA256_REG_SHA256_DIGEST_7 (32'h11c) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define SHA256_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) @@ -2824,15 +6071,23 @@ `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) @@ -2842,9 +6097,13 @@ `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) @@ -2854,33 +6113,65 @@ `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) `define SHA256_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R `define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R `define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R `define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R `define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R `define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R `define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) `define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R `define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) `define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R `define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) `define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R `define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) `define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R `define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef MLDSA_REG_MLDSA_NAME_0 `define MLDSA_REG_MLDSA_NAME_0 (32'h0) +`endif +`ifndef MLDSA_REG_MLDSA_NAME_1 `define MLDSA_REG_MLDSA_NAME_1 (32'h4) +`endif +`ifndef MLDSA_REG_MLDSA_VERSION_0 `define MLDSA_REG_MLDSA_VERSION_0 (32'h8) +`endif +`ifndef MLDSA_REG_MLDSA_VERSION_1 `define MLDSA_REG_MLDSA_VERSION_1 (32'hc) +`endif +`ifndef MLDSA_REG_MLDSA_CTRL `define MLDSA_REG_MLDSA_CTRL (32'h10) `define MLDSA_REG_MLDSA_CTRL_CTRL_LOW (0) `define MLDSA_REG_MLDSA_CTRL_CTRL_MASK (32'h7) @@ -2888,75 +6179,207 @@ `define MLDSA_REG_MLDSA_CTRL_ZEROIZE_MASK (32'h8) `define MLDSA_REG_MLDSA_CTRL_PCR_SIGN_LOW (4) `define MLDSA_REG_MLDSA_CTRL_PCR_SIGN_MASK (32'h10) +`endif +`ifndef MLDSA_REG_MLDSA_STATUS `define MLDSA_REG_MLDSA_STATUS (32'h14) `define MLDSA_REG_MLDSA_STATUS_READY_LOW (0) `define MLDSA_REG_MLDSA_STATUS_READY_MASK (32'h1) `define MLDSA_REG_MLDSA_STATUS_VALID_LOW (1) `define MLDSA_REG_MLDSA_STATUS_VALID_MASK (32'h2) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_0 `define MLDSA_REG_MLDSA_ENTROPY_0 (32'h18) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_1 `define MLDSA_REG_MLDSA_ENTROPY_1 (32'h1c) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_2 `define MLDSA_REG_MLDSA_ENTROPY_2 (32'h20) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_3 `define MLDSA_REG_MLDSA_ENTROPY_3 (32'h24) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_4 `define MLDSA_REG_MLDSA_ENTROPY_4 (32'h28) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_5 `define MLDSA_REG_MLDSA_ENTROPY_5 (32'h2c) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_6 `define MLDSA_REG_MLDSA_ENTROPY_6 (32'h30) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_7 `define MLDSA_REG_MLDSA_ENTROPY_7 (32'h34) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_8 `define MLDSA_REG_MLDSA_ENTROPY_8 (32'h38) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_9 `define MLDSA_REG_MLDSA_ENTROPY_9 (32'h3c) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_10 `define MLDSA_REG_MLDSA_ENTROPY_10 (32'h40) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_11 `define MLDSA_REG_MLDSA_ENTROPY_11 (32'h44) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_12 `define MLDSA_REG_MLDSA_ENTROPY_12 (32'h48) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_13 `define MLDSA_REG_MLDSA_ENTROPY_13 (32'h4c) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_14 `define MLDSA_REG_MLDSA_ENTROPY_14 (32'h50) +`endif +`ifndef MLDSA_REG_MLDSA_ENTROPY_15 `define MLDSA_REG_MLDSA_ENTROPY_15 (32'h54) +`endif +`ifndef MLDSA_REG_MLDSA_SEED_0 `define MLDSA_REG_MLDSA_SEED_0 (32'h58) +`endif +`ifndef MLDSA_REG_MLDSA_SEED_1 `define MLDSA_REG_MLDSA_SEED_1 (32'h5c) +`endif +`ifndef MLDSA_REG_MLDSA_SEED_2 `define MLDSA_REG_MLDSA_SEED_2 (32'h60) +`endif +`ifndef MLDSA_REG_MLDSA_SEED_3 `define MLDSA_REG_MLDSA_SEED_3 (32'h64) +`endif +`ifndef MLDSA_REG_MLDSA_SEED_4 `define MLDSA_REG_MLDSA_SEED_4 (32'h68) +`endif +`ifndef MLDSA_REG_MLDSA_SEED_5 `define MLDSA_REG_MLDSA_SEED_5 (32'h6c) +`endif +`ifndef MLDSA_REG_MLDSA_SEED_6 `define MLDSA_REG_MLDSA_SEED_6 (32'h70) +`endif +`ifndef MLDSA_REG_MLDSA_SEED_7 `define MLDSA_REG_MLDSA_SEED_7 (32'h74) +`endif +`ifndef MLDSA_REG_MLDSA_SIGN_RND_0 `define MLDSA_REG_MLDSA_SIGN_RND_0 (32'h78) +`endif +`ifndef MLDSA_REG_MLDSA_SIGN_RND_1 `define MLDSA_REG_MLDSA_SIGN_RND_1 (32'h7c) +`endif +`ifndef MLDSA_REG_MLDSA_SIGN_RND_2 `define MLDSA_REG_MLDSA_SIGN_RND_2 (32'h80) +`endif +`ifndef MLDSA_REG_MLDSA_SIGN_RND_3 `define MLDSA_REG_MLDSA_SIGN_RND_3 (32'h84) +`endif +`ifndef MLDSA_REG_MLDSA_SIGN_RND_4 `define MLDSA_REG_MLDSA_SIGN_RND_4 (32'h88) +`endif +`ifndef MLDSA_REG_MLDSA_SIGN_RND_5 `define MLDSA_REG_MLDSA_SIGN_RND_5 (32'h8c) +`endif +`ifndef MLDSA_REG_MLDSA_SIGN_RND_6 `define MLDSA_REG_MLDSA_SIGN_RND_6 (32'h90) +`endif +`ifndef MLDSA_REG_MLDSA_SIGN_RND_7 `define MLDSA_REG_MLDSA_SIGN_RND_7 (32'h94) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_0 `define MLDSA_REG_MLDSA_MSG_0 (32'h98) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_1 `define MLDSA_REG_MLDSA_MSG_1 (32'h9c) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_2 `define MLDSA_REG_MLDSA_MSG_2 (32'ha0) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_3 `define MLDSA_REG_MLDSA_MSG_3 (32'ha4) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_4 `define MLDSA_REG_MLDSA_MSG_4 (32'ha8) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_5 `define MLDSA_REG_MLDSA_MSG_5 (32'hac) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_6 `define MLDSA_REG_MLDSA_MSG_6 (32'hb0) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_7 `define MLDSA_REG_MLDSA_MSG_7 (32'hb4) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_8 `define MLDSA_REG_MLDSA_MSG_8 (32'hb8) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_9 `define MLDSA_REG_MLDSA_MSG_9 (32'hbc) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_10 `define MLDSA_REG_MLDSA_MSG_10 (32'hc0) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_11 `define MLDSA_REG_MLDSA_MSG_11 (32'hc4) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_12 `define MLDSA_REG_MLDSA_MSG_12 (32'hc8) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_13 `define MLDSA_REG_MLDSA_MSG_13 (32'hcc) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_14 `define MLDSA_REG_MLDSA_MSG_14 (32'hd0) +`endif +`ifndef MLDSA_REG_MLDSA_MSG_15 `define MLDSA_REG_MLDSA_MSG_15 (32'hd4) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_0 `define MLDSA_REG_MLDSA_VERIFY_RES_0 (32'hd8) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_1 `define MLDSA_REG_MLDSA_VERIFY_RES_1 (32'hdc) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_2 `define MLDSA_REG_MLDSA_VERIFY_RES_2 (32'he0) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_3 `define MLDSA_REG_MLDSA_VERIFY_RES_3 (32'he4) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_4 `define MLDSA_REG_MLDSA_VERIFY_RES_4 (32'he8) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_5 `define MLDSA_REG_MLDSA_VERIFY_RES_5 (32'hec) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_6 `define MLDSA_REG_MLDSA_VERIFY_RES_6 (32'hf0) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_7 `define MLDSA_REG_MLDSA_VERIFY_RES_7 (32'hf4) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_8 `define MLDSA_REG_MLDSA_VERIFY_RES_8 (32'hf8) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_9 `define MLDSA_REG_MLDSA_VERIFY_RES_9 (32'hfc) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_10 `define MLDSA_REG_MLDSA_VERIFY_RES_10 (32'h100) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_11 `define MLDSA_REG_MLDSA_VERIFY_RES_11 (32'h104) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_12 `define MLDSA_REG_MLDSA_VERIFY_RES_12 (32'h108) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_13 `define MLDSA_REG_MLDSA_VERIFY_RES_13 (32'h10c) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_14 `define MLDSA_REG_MLDSA_VERIFY_RES_14 (32'h110) +`endif +`ifndef MLDSA_REG_MLDSA_VERIFY_RES_15 `define MLDSA_REG_MLDSA_VERIFY_RES_15 (32'h114) +`endif +`ifndef MLDSA_REG_MLDSA_KV_RD_SEED_CTRL `define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL (32'h8000) `define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_EN_LOW (0) `define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_READ_EN_MASK (32'h1) @@ -2966,6 +6389,8 @@ `define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_PCR_HASH_EXTEND_MASK (32'h40) `define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_RSVD_LOW (7) `define MLDSA_REG_MLDSA_KV_RD_SEED_CTRL_RSVD_MASK (32'hffffff80) +`endif +`ifndef MLDSA_REG_MLDSA_KV_RD_SEED_STATUS `define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS (32'h8004) `define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_READY_LOW (0) `define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_READY_MASK (32'h1) @@ -2973,43 +6398,71 @@ `define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_VALID_MASK (32'h2) `define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_ERROR_LOW (2) `define MLDSA_REG_MLDSA_KV_RD_SEED_STATUS_ERROR_MASK (32'h3fc) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h8100) `define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define MLDSA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h8104) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h8108) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h810c) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h8110) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h8114) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h8118) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h811c) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h8120) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h8200) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h8280) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'h8300) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'h8304) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define MLDSA_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef CSRNG_REG_INTERRUPT_STATE `define CSRNG_REG_INTERRUPT_STATE (32'h0) `define CSRNG_REG_INTERRUPT_STATE_CS_CMD_REQ_DONE_LOW (0) `define CSRNG_REG_INTERRUPT_STATE_CS_CMD_REQ_DONE_MASK (32'h1) @@ -3019,6 +6472,8 @@ `define CSRNG_REG_INTERRUPT_STATE_CS_HW_INST_EXC_MASK (32'h4) `define CSRNG_REG_INTERRUPT_STATE_CS_FATAL_ERR_LOW (3) `define CSRNG_REG_INTERRUPT_STATE_CS_FATAL_ERR_MASK (32'h8) +`endif +`ifndef CSRNG_REG_INTERRUPT_ENABLE `define CSRNG_REG_INTERRUPT_ENABLE (32'h4) `define CSRNG_REG_INTERRUPT_ENABLE_CS_CMD_REQ_DONE_LOW (0) `define CSRNG_REG_INTERRUPT_ENABLE_CS_CMD_REQ_DONE_MASK (32'h1) @@ -3028,6 +6483,8 @@ `define CSRNG_REG_INTERRUPT_ENABLE_CS_HW_INST_EXC_MASK (32'h4) `define CSRNG_REG_INTERRUPT_ENABLE_CS_FATAL_ERR_LOW (3) `define CSRNG_REG_INTERRUPT_ENABLE_CS_FATAL_ERR_MASK (32'h8) +`endif +`ifndef CSRNG_REG_INTERRUPT_TEST `define CSRNG_REG_INTERRUPT_TEST (32'h8) `define CSRNG_REG_INTERRUPT_TEST_CS_CMD_REQ_DONE_LOW (0) `define CSRNG_REG_INTERRUPT_TEST_CS_CMD_REQ_DONE_MASK (32'h1) @@ -3037,14 +6494,20 @@ `define CSRNG_REG_INTERRUPT_TEST_CS_HW_INST_EXC_MASK (32'h4) `define CSRNG_REG_INTERRUPT_TEST_CS_FATAL_ERR_LOW (3) `define CSRNG_REG_INTERRUPT_TEST_CS_FATAL_ERR_MASK (32'h8) +`endif +`ifndef CSRNG_REG_ALERT_TEST `define CSRNG_REG_ALERT_TEST (32'hc) `define CSRNG_REG_ALERT_TEST_RECOV_ALERT_LOW (0) `define CSRNG_REG_ALERT_TEST_RECOV_ALERT_MASK (32'h1) `define CSRNG_REG_ALERT_TEST_FATAL_ALERT_LOW (1) `define CSRNG_REG_ALERT_TEST_FATAL_ALERT_MASK (32'h2) +`endif +`ifndef CSRNG_REG_REGWEN `define CSRNG_REG_REGWEN (32'h10) `define CSRNG_REG_REGWEN_REGWEN_LOW (0) `define CSRNG_REG_REGWEN_REGWEN_MASK (32'h1) +`endif +`ifndef CSRNG_REG_CTRL `define CSRNG_REG_CTRL (32'h14) `define CSRNG_REG_CTRL_ENABLE_LOW (0) `define CSRNG_REG_CTRL_ENABLE_MASK (32'hf) @@ -3052,6 +6515,8 @@ `define CSRNG_REG_CTRL_SW_APP_ENABLE_MASK (32'hf0) `define CSRNG_REG_CTRL_READ_INT_STATE_LOW (8) `define CSRNG_REG_CTRL_READ_INT_STATE_MASK (32'hf00) +`endif +`ifndef CSRNG_REG_CMD_REQ `define CSRNG_REG_CMD_REQ (32'h18) `define CSRNG_REG_CMD_REQ_ACMD_LOW (0) `define CSRNG_REG_CMD_REQ_ACMD_MASK (32'hf) @@ -3061,24 +6526,38 @@ `define CSRNG_REG_CMD_REQ_FLAG0_MASK (32'hf00) `define CSRNG_REG_CMD_REQ_GLEN_LOW (12) `define CSRNG_REG_CMD_REQ_GLEN_MASK (32'h1fff000) +`endif +`ifndef CSRNG_REG_SW_CMD_STS `define CSRNG_REG_SW_CMD_STS (32'h1c) `define CSRNG_REG_SW_CMD_STS_CMD_RDY_LOW (0) `define CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK (32'h1) `define CSRNG_REG_SW_CMD_STS_CMD_STS_LOW (1) `define CSRNG_REG_SW_CMD_STS_CMD_STS_MASK (32'h2) +`endif +`ifndef CSRNG_REG_GENBITS_VLD `define CSRNG_REG_GENBITS_VLD (32'h20) `define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_LOW (0) `define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_MASK (32'h1) `define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_LOW (1) `define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_MASK (32'h2) +`endif +`ifndef CSRNG_REG_GENBITS `define CSRNG_REG_GENBITS (32'h24) +`endif +`ifndef CSRNG_REG_INT_STATE_NUM `define CSRNG_REG_INT_STATE_NUM (32'h28) `define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_LOW (0) `define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_MASK (32'hf) +`endif +`ifndef CSRNG_REG_INT_STATE_VAL `define CSRNG_REG_INT_STATE_VAL (32'h2c) +`endif +`ifndef CSRNG_REG_HW_EXC_STS `define CSRNG_REG_HW_EXC_STS (32'h30) `define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_LOW (0) `define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_MASK (32'hffff) +`endif +`ifndef CSRNG_REG_RECOV_ALERT_STS `define CSRNG_REG_RECOV_ALERT_STS (32'h34) `define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_LOW (0) `define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_MASK (32'h1) @@ -3092,6 +6571,8 @@ `define CSRNG_REG_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_MASK (32'h1000) `define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_LOW (13) `define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_MASK (32'h2000) +`endif +`ifndef CSRNG_REG_ERR_CODE `define CSRNG_REG_ERR_CODE (32'h38) `define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_LOW (0) `define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_MASK (32'h1) @@ -3145,12 +6626,18 @@ `define CSRNG_REG_ERR_CODE_FIFO_READ_ERR_MASK (32'h20000000) `define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30) `define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_MASK (32'h40000000) +`endif +`ifndef CSRNG_REG_ERR_CODE_TEST `define CSRNG_REG_ERR_CODE_TEST (32'h3c) `define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0) `define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (32'h1f) +`endif +`ifndef CSRNG_REG_MAIN_SM_STATE `define CSRNG_REG_MAIN_SM_STATE (32'h40) `define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) `define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (32'hff) +`endif +`ifndef ENTROPY_SRC_REG_INTERRUPT_STATE `define ENTROPY_SRC_REG_INTERRUPT_STATE (32'h0) `define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_ENTROPY_VALID_LOW (0) `define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_ENTROPY_VALID_MASK (32'h1) @@ -3160,6 +6647,8 @@ `define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_OBSERVE_FIFO_READY_MASK (32'h4) `define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_FATAL_ERR_LOW (3) `define ENTROPY_SRC_REG_INTERRUPT_STATE_ES_FATAL_ERR_MASK (32'h8) +`endif +`ifndef ENTROPY_SRC_REG_INTERRUPT_ENABLE `define ENTROPY_SRC_REG_INTERRUPT_ENABLE (32'h4) `define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_ENTROPY_VALID_LOW (0) `define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_ENTROPY_VALID_MASK (32'h1) @@ -3169,6 +6658,8 @@ `define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_OBSERVE_FIFO_READY_MASK (32'h4) `define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_FATAL_ERR_LOW (3) `define ENTROPY_SRC_REG_INTERRUPT_ENABLE_ES_FATAL_ERR_MASK (32'h8) +`endif +`ifndef ENTROPY_SRC_REG_INTERRUPT_TEST `define ENTROPY_SRC_REG_INTERRUPT_TEST (32'h8) `define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_ENTROPY_VALID_LOW (0) `define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_ENTROPY_VALID_MASK (32'h1) @@ -3178,20 +6669,30 @@ `define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_OBSERVE_FIFO_READY_MASK (32'h4) `define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_FATAL_ERR_LOW (3) `define ENTROPY_SRC_REG_INTERRUPT_TEST_ES_FATAL_ERR_MASK (32'h8) +`endif +`ifndef ENTROPY_SRC_REG_ALERT_TEST `define ENTROPY_SRC_REG_ALERT_TEST (32'hc) `define ENTROPY_SRC_REG_ALERT_TEST_RECOV_ALERT_LOW (0) `define ENTROPY_SRC_REG_ALERT_TEST_RECOV_ALERT_MASK (32'h1) `define ENTROPY_SRC_REG_ALERT_TEST_FATAL_ALERT_LOW (1) `define ENTROPY_SRC_REG_ALERT_TEST_FATAL_ALERT_MASK (32'h2) +`endif +`ifndef ENTROPY_SRC_REG_ME_REGWEN `define ENTROPY_SRC_REG_ME_REGWEN (32'h10) `define ENTROPY_SRC_REG_ME_REGWEN_ME_REGWEN_LOW (0) `define ENTROPY_SRC_REG_ME_REGWEN_ME_REGWEN_MASK (32'h1) +`endif +`ifndef ENTROPY_SRC_REG_SW_REGUPD `define ENTROPY_SRC_REG_SW_REGUPD (32'h14) `define ENTROPY_SRC_REG_SW_REGUPD_SW_REGUPD_LOW (0) `define ENTROPY_SRC_REG_SW_REGUPD_SW_REGUPD_MASK (32'h1) +`endif +`ifndef ENTROPY_SRC_REG_REGWEN `define ENTROPY_SRC_REG_REGWEN (32'h18) `define ENTROPY_SRC_REG_REGWEN_REGWEN_LOW (0) `define ENTROPY_SRC_REG_REGWEN_REGWEN_MASK (32'h1) +`endif +`ifndef ENTROPY_SRC_REG_REV `define ENTROPY_SRC_REG_REV (32'h1c) `define ENTROPY_SRC_REG_REV_ABI_REVISION_LOW (0) `define ENTROPY_SRC_REG_REV_ABI_REVISION_MASK (32'hff) @@ -3199,9 +6700,13 @@ `define ENTROPY_SRC_REG_REV_HW_REVISION_MASK (32'hff00) `define ENTROPY_SRC_REG_REV_CHIP_TYPE_LOW (16) `define ENTROPY_SRC_REG_REV_CHIP_TYPE_MASK (32'hff0000) +`endif +`ifndef ENTROPY_SRC_REG_MODULE_ENABLE `define ENTROPY_SRC_REG_MODULE_ENABLE (32'h20) `define ENTROPY_SRC_REG_MODULE_ENABLE_MODULE_ENABLE_LOW (0) `define ENTROPY_SRC_REG_MODULE_ENABLE_MODULE_ENABLE_MASK (32'hf) +`endif +`ifndef ENTROPY_SRC_REG_CONF `define ENTROPY_SRC_REG_CONF (32'h24) `define ENTROPY_SRC_REG_CONF_FIPS_ENABLE_LOW (0) `define ENTROPY_SRC_REG_CONF_FIPS_ENABLE_MASK (32'hf) @@ -3213,124 +6718,190 @@ `define ENTROPY_SRC_REG_CONF_RNG_BIT_ENABLE_MASK (32'hf00000) `define ENTROPY_SRC_REG_CONF_RNG_BIT_SEL_LOW (24) `define ENTROPY_SRC_REG_CONF_RNG_BIT_SEL_MASK (32'h3000000) +`endif +`ifndef ENTROPY_SRC_REG_ENTROPY_CONTROL `define ENTROPY_SRC_REG_ENTROPY_CONTROL (32'h28) `define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_ROUTE_LOW (0) `define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_ROUTE_MASK (32'hf) `define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_TYPE_LOW (4) `define ENTROPY_SRC_REG_ENTROPY_CONTROL_ES_TYPE_MASK (32'hf0) +`endif +`ifndef ENTROPY_SRC_REG_ENTROPY_DATA `define ENTROPY_SRC_REG_ENTROPY_DATA (32'h2c) +`endif +`ifndef ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS `define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS (32'h30) `define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_FIPS_WINDOW_LOW (0) `define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_FIPS_WINDOW_MASK (32'hffff) `define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_LOW (16) `define ENTROPY_SRC_REG_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_REPCNT_THRESHOLDS `define ENTROPY_SRC_REG_REPCNT_THRESHOLDS (32'h34) `define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_REPCNT_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_REPCNTS_THRESHOLDS `define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS (32'h38) `define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_REPCNTS_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS `define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS (32'h3c) `define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS `define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS (32'h40) `define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_ADAPTP_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_BUCKET_THRESHOLDS `define ENTROPY_SRC_REG_BUCKET_THRESHOLDS (32'h44) `define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_BUCKET_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS `define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS (32'h48) `define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_MARKOV_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS `define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS (32'h4c) `define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_MARKOV_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS `define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS (32'h50) `define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_EXTHT_HI_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS `define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS (32'h54) `define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_FIPS_THRESH_LOW (0) `define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_FIPS_THRESH_MASK (32'hffff) `define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_LOW (16) `define ENTROPY_SRC_REG_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS `define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS (32'h58) `define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_REPCNT_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS `define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS (32'h5c) `define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_REPCNTS_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS `define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS (32'h60) `define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_ADAPTP_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS `define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS (32'h64) `define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_ADAPTP_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS `define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS (32'h68) `define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_EXTHT_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS `define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS (32'h6c) `define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_EXTHT_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS `define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS (32'h70) `define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_BUCKET_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS `define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS (32'h74) `define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_MARKOV_HI_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS `define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS (32'h78) `define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_LOW (0) `define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_MASK (32'hffff) `define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_LOW (16) `define ENTROPY_SRC_REG_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_REPCNT_TOTAL_FAILS `define ENTROPY_SRC_REG_REPCNT_TOTAL_FAILS (32'h7c) +`endif +`ifndef ENTROPY_SRC_REG_REPCNTS_TOTAL_FAILS `define ENTROPY_SRC_REG_REPCNTS_TOTAL_FAILS (32'h80) +`endif +`ifndef ENTROPY_SRC_REG_ADAPTP_HI_TOTAL_FAILS `define ENTROPY_SRC_REG_ADAPTP_HI_TOTAL_FAILS (32'h84) +`endif +`ifndef ENTROPY_SRC_REG_ADAPTP_LO_TOTAL_FAILS `define ENTROPY_SRC_REG_ADAPTP_LO_TOTAL_FAILS (32'h88) +`endif +`ifndef ENTROPY_SRC_REG_BUCKET_TOTAL_FAILS `define ENTROPY_SRC_REG_BUCKET_TOTAL_FAILS (32'h8c) +`endif +`ifndef ENTROPY_SRC_REG_MARKOV_HI_TOTAL_FAILS `define ENTROPY_SRC_REG_MARKOV_HI_TOTAL_FAILS (32'h90) +`endif +`ifndef ENTROPY_SRC_REG_MARKOV_LO_TOTAL_FAILS `define ENTROPY_SRC_REG_MARKOV_LO_TOTAL_FAILS (32'h94) +`endif +`ifndef ENTROPY_SRC_REG_EXTHT_HI_TOTAL_FAILS `define ENTROPY_SRC_REG_EXTHT_HI_TOTAL_FAILS (32'h98) +`endif +`ifndef ENTROPY_SRC_REG_EXTHT_LO_TOTAL_FAILS `define ENTROPY_SRC_REG_EXTHT_LO_TOTAL_FAILS (32'h9c) +`endif +`ifndef ENTROPY_SRC_REG_ALERT_THRESHOLD `define ENTROPY_SRC_REG_ALERT_THRESHOLD (32'ha0) `define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_LOW (0) `define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_MASK (32'hffff) `define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_LOW (16) `define ENTROPY_SRC_REG_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_MASK (32'hffff0000) +`endif +`ifndef ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS `define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS (32'ha4) `define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_LOW (0) `define ENTROPY_SRC_REG_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_MASK (32'hffff) +`endif +`ifndef ENTROPY_SRC_REG_ALERT_FAIL_COUNTS `define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS (32'ha8) `define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_LOW (4) `define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_MASK (32'hf0) @@ -3346,33 +6917,53 @@ `define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_MASK (32'hf000000) `define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_LOW (28) `define ENTROPY_SRC_REG_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_MASK (32'hf0000000) +`endif +`ifndef ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS `define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS (32'hac) `define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_LOW (0) `define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_MASK (32'hf) `define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_LOW (4) `define ENTROPY_SRC_REG_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_MASK (32'hf0) +`endif +`ifndef ENTROPY_SRC_REG_FW_OV_CONTROL `define ENTROPY_SRC_REG_FW_OV_CONTROL (32'hb0) `define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_MODE_LOW (0) `define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_MODE_MASK (32'hf) `define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_LOW (4) `define ENTROPY_SRC_REG_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK (32'hf0) +`endif +`ifndef ENTROPY_SRC_REG_FW_OV_SHA3_START `define ENTROPY_SRC_REG_FW_OV_SHA3_START (32'hb4) `define ENTROPY_SRC_REG_FW_OV_SHA3_START_FW_OV_INSERT_START_LOW (0) `define ENTROPY_SRC_REG_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK (32'hf) +`endif +`ifndef ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL `define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL (32'hb8) `define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_LOW (0) `define ENTROPY_SRC_REG_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_MASK (32'h1) +`endif +`ifndef ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW `define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW (32'hbc) `define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_LOW (0) `define ENTROPY_SRC_REG_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_MASK (32'h1) +`endif +`ifndef ENTROPY_SRC_REG_FW_OV_RD_DATA `define ENTROPY_SRC_REG_FW_OV_RD_DATA (32'hc0) +`endif +`ifndef ENTROPY_SRC_REG_FW_OV_WR_DATA `define ENTROPY_SRC_REG_FW_OV_WR_DATA (32'hc4) +`endif +`ifndef ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH `define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH (32'hc8) `define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_LOW (0) `define ENTROPY_SRC_REG_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK (32'h7f) +`endif +`ifndef ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH `define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH (32'hcc) `define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_LOW (0) `define ENTROPY_SRC_REG_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_MASK (32'h7f) +`endif +`ifndef ENTROPY_SRC_REG_DEBUG_STATUS `define ENTROPY_SRC_REG_DEBUG_STATUS (32'hd0) `define ENTROPY_SRC_REG_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_LOW (0) `define ENTROPY_SRC_REG_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_MASK (32'h7) @@ -3390,6 +6981,8 @@ `define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_IDLE_MASK (32'h10000) `define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_BOOT_DONE_LOW (17) `define ENTROPY_SRC_REG_DEBUG_STATUS_MAIN_SM_BOOT_DONE_MASK (32'h20000) +`endif +`ifndef ENTROPY_SRC_REG_RECOV_ALERT_STS `define ENTROPY_SRC_REG_RECOV_ALERT_STS (32'hd4) `define ENTROPY_SRC_REG_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_LOW (0) `define ENTROPY_SRC_REG_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_MASK (32'h1) @@ -3421,6 +7014,8 @@ `define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_MASK (32'h8000) `define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_LOW (16) `define ENTROPY_SRC_REG_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_MASK (32'h10000) +`endif +`ifndef ENTROPY_SRC_REG_ERR_CODE `define ENTROPY_SRC_REG_ERR_CODE (32'hd8) `define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESRNG_ERR_LOW (0) `define ENTROPY_SRC_REG_ERR_CODE_SFIFO_ESRNG_ERR_MASK (32'h1) @@ -3444,23 +7039,43 @@ `define ENTROPY_SRC_REG_ERR_CODE_FIFO_READ_ERR_MASK (32'h20000000) `define ENTROPY_SRC_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30) `define ENTROPY_SRC_REG_ERR_CODE_FIFO_STATE_ERR_MASK (32'h40000000) +`endif +`ifndef ENTROPY_SRC_REG_ERR_CODE_TEST `define ENTROPY_SRC_REG_ERR_CODE_TEST (32'hdc) `define ENTROPY_SRC_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0) `define ENTROPY_SRC_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (32'h1f) +`endif +`ifndef ENTROPY_SRC_REG_MAIN_SM_STATE `define ENTROPY_SRC_REG_MAIN_SM_STATE (32'he0) `define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0) `define ENTROPY_SRC_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (32'h1ff) +`endif +`ifndef MBOX_CSR_MBOX_LOCK `define MBOX_CSR_MBOX_LOCK (32'h0) `define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) `define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef MBOX_CSR_MBOX_USER `define MBOX_CSR_MBOX_USER (32'h4) +`endif +`ifndef MBOX_CSR_MBOX_CMD `define MBOX_CSR_MBOX_CMD (32'h8) +`endif +`ifndef MBOX_CSR_MBOX_DLEN `define MBOX_CSR_MBOX_DLEN (32'hc) +`endif +`ifndef MBOX_CSR_MBOX_DATAIN `define MBOX_CSR_MBOX_DATAIN (32'h10) +`endif +`ifndef MBOX_CSR_MBOX_DATAOUT `define MBOX_CSR_MBOX_DATAOUT (32'h14) +`endif +`ifndef MBOX_CSR_MBOX_EXECUTE `define MBOX_CSR_MBOX_EXECUTE (32'h18) `define MBOX_CSR_MBOX_EXECUTE_EXECUTE_LOW (0) `define MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK (32'h1) +`endif +`ifndef MBOX_CSR_MBOX_STATUS `define MBOX_CSR_MBOX_STATUS (32'h1c) `define MBOX_CSR_MBOX_STATUS_STATUS_LOW (0) `define MBOX_CSR_MBOX_STATUS_STATUS_MASK (32'hf) @@ -3474,56 +7089,114 @@ `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (32'h200) `define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) `define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h3fffc00) +`endif +`ifndef MBOX_CSR_MBOX_UNLOCK `define MBOX_CSR_MBOX_UNLOCK (32'h20) `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (32'h1) +`endif +`ifndef MBOX_CSR_TAP_MODE `define MBOX_CSR_TAP_MODE (32'h24) `define MBOX_CSR_TAP_MODE_ENABLED_LOW (0) `define MBOX_CSR_TAP_MODE_ENABLED_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_LOCK `define SHA512_ACC_CSR_LOCK (32'h0) `define SHA512_ACC_CSR_LOCK_LOCK_LOW (0) `define SHA512_ACC_CSR_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_USER `define SHA512_ACC_CSR_USER (32'h4) +`endif +`ifndef SHA512_ACC_CSR_MODE `define SHA512_ACC_CSR_MODE (32'h8) `define SHA512_ACC_CSR_MODE_MODE_LOW (0) `define SHA512_ACC_CSR_MODE_MODE_MASK (32'h3) `define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_LOW (2) `define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_MASK (32'h4) +`endif +`ifndef SHA512_ACC_CSR_START_ADDRESS `define SHA512_ACC_CSR_START_ADDRESS (32'hc) +`endif +`ifndef SHA512_ACC_CSR_DLEN `define SHA512_ACC_CSR_DLEN (32'h10) +`endif +`ifndef SHA512_ACC_CSR_DATAIN `define SHA512_ACC_CSR_DATAIN (32'h14) +`endif +`ifndef SHA512_ACC_CSR_EXECUTE `define SHA512_ACC_CSR_EXECUTE (32'h18) `define SHA512_ACC_CSR_EXECUTE_EXECUTE_LOW (0) `define SHA512_ACC_CSR_EXECUTE_EXECUTE_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_STATUS `define SHA512_ACC_CSR_STATUS (32'h1c) `define SHA512_ACC_CSR_STATUS_VALID_LOW (0) `define SHA512_ACC_CSR_STATUS_VALID_MASK (32'h1) `define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW (1) `define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK (32'h2) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_0 `define SHA512_ACC_CSR_DIGEST_0 (32'h20) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_1 `define SHA512_ACC_CSR_DIGEST_1 (32'h24) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_2 `define SHA512_ACC_CSR_DIGEST_2 (32'h28) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_3 `define SHA512_ACC_CSR_DIGEST_3 (32'h2c) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_4 `define SHA512_ACC_CSR_DIGEST_4 (32'h30) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_5 `define SHA512_ACC_CSR_DIGEST_5 (32'h34) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_6 `define SHA512_ACC_CSR_DIGEST_6 (32'h38) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_7 `define SHA512_ACC_CSR_DIGEST_7 (32'h3c) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_8 `define SHA512_ACC_CSR_DIGEST_8 (32'h40) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_9 `define SHA512_ACC_CSR_DIGEST_9 (32'h44) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_10 `define SHA512_ACC_CSR_DIGEST_10 (32'h48) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_11 `define SHA512_ACC_CSR_DIGEST_11 (32'h4c) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_12 `define SHA512_ACC_CSR_DIGEST_12 (32'h50) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_13 `define SHA512_ACC_CSR_DIGEST_13 (32'h54) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_14 `define SHA512_ACC_CSR_DIGEST_14 (32'h58) +`endif +`ifndef SHA512_ACC_CSR_DIGEST_15 `define SHA512_ACC_CSR_DIGEST_15 (32'h5c) +`endif +`ifndef SHA512_ACC_CSR_CONTROL `define SHA512_ACC_CSR_CONTROL (32'h60) `define SHA512_ACC_CSR_CONTROL_ZEROIZE_LOW (0) `define SHA512_ACC_CSR_CONTROL_ZEROIZE_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK (32'h1) @@ -3533,15 +7206,23 @@ `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK (32'h4) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_LOW (3) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK (32'h8) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK (32'h1) @@ -3551,9 +7232,13 @@ `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK (32'h4) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_LOW (3) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK (32'h8) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK (32'h1) @@ -3563,35 +7248,63 @@ `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK (32'h4) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_LOW (3) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK (32'h8) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R (32'h900) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R (32'h904) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R (32'h908) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R (32'h90c) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R (32'h980) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R (32'ha00) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R (32'ha04) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R (32'ha08) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R (32'ha0c) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R (32'ha10) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_ID `define AXI_DMA_REG_ID (32'h0) +`endif +`ifndef AXI_DMA_REG_CAP `define AXI_DMA_REG_CAP (32'h4) `define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW (0) `define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK (32'hfff) `define AXI_DMA_REG_CAP_RSVD_LOW (12) `define AXI_DMA_REG_CAP_RSVD_MASK (32'hfffff000) +`endif +`ifndef AXI_DMA_REG_CTRL `define AXI_DMA_REG_CTRL (32'h8) `define AXI_DMA_REG_CTRL_GO_LOW (0) `define AXI_DMA_REG_CTRL_GO_MASK (32'h1) @@ -3615,6 +7328,8 @@ `define AXI_DMA_REG_CTRL_WR_FIXED_MASK (32'h10000000) `define AXI_DMA_REG_CTRL_RSVD4_LOW (29) `define AXI_DMA_REG_CTRL_RSVD4_MASK (32'he0000000) +`endif +`ifndef AXI_DMA_REG_STATUS0 `define AXI_DMA_REG_STATUS0 (32'hc) `define AXI_DMA_REG_STATUS0_BUSY_LOW (0) `define AXI_DMA_REG_STATUS0_BUSY_MASK (32'h1) @@ -3632,24 +7347,46 @@ `define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_MASK (32'h80000) `define AXI_DMA_REG_STATUS0_RSVD1_LOW (20) `define AXI_DMA_REG_STATUS0_RSVD1_MASK (32'hfff00000) +`endif +`ifndef AXI_DMA_REG_STATUS1 `define AXI_DMA_REG_STATUS1 (32'h10) +`endif +`ifndef AXI_DMA_REG_SRC_ADDR_L `define AXI_DMA_REG_SRC_ADDR_L (32'h14) +`endif +`ifndef AXI_DMA_REG_SRC_ADDR_H `define AXI_DMA_REG_SRC_ADDR_H (32'h18) +`endif +`ifndef AXI_DMA_REG_DST_ADDR_L `define AXI_DMA_REG_DST_ADDR_L (32'h1c) +`endif +`ifndef AXI_DMA_REG_DST_ADDR_H `define AXI_DMA_REG_DST_ADDR_H (32'h20) +`endif +`ifndef AXI_DMA_REG_BYTE_COUNT `define AXI_DMA_REG_BYTE_COUNT (32'h24) +`endif +`ifndef AXI_DMA_REG_BLOCK_SIZE `define AXI_DMA_REG_BLOCK_SIZE (32'h28) `define AXI_DMA_REG_BLOCK_SIZE_SIZE_LOW (0) `define AXI_DMA_REG_BLOCK_SIZE_SIZE_MASK (32'hfff) `define AXI_DMA_REG_BLOCK_SIZE_RSVD_LOW (12) `define AXI_DMA_REG_BLOCK_SIZE_RSVD_MASK (32'hfffff000) +`endif +`ifndef AXI_DMA_REG_WRITE_DATA `define AXI_DMA_REG_WRITE_DATA (32'h2c) +`endif +`ifndef AXI_DMA_REG_READ_DATA `define AXI_DMA_REG_READ_DATA (32'h30) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define AXI_DMA_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_DEC_EN_MASK (32'h1) @@ -3665,6 +7402,8 @@ `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_OFLOW_EN_MASK (32'h20) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_LOW (6) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_FIFO_UFLOW_EN_MASK (32'h40) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_TXN_DONE_EN_MASK (32'h1) @@ -3676,12 +7415,18 @@ `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_FULL_EN_MASK (32'h8) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_LOW (4) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_FIFO_NOT_FULL_EN_MASK (32'h10) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_DEC_STS_MASK (32'h1) @@ -3697,6 +7442,8 @@ `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_OFLOW_STS_MASK (32'h20) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_LOW (6) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_FIFO_UFLOW_STS_MASK (32'h40) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_TXN_DONE_STS_MASK (32'h1) @@ -3708,6 +7455,8 @@ `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_FULL_STS_MASK (32'h8) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_LOW (4) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_FIFO_NOT_FULL_STS_MASK (32'h10) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_DEC_TRIG_MASK (32'h1) @@ -3723,6 +7472,8 @@ `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_OFLOW_TRIG_MASK (32'h20) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_LOW (6) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_FIFO_UFLOW_TRIG_MASK (32'h40) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_TXN_DONE_TRIG_MASK (32'h1) @@ -3734,54 +7485,104 @@ `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_FULL_TRIG_MASK (32'h8) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_LOW (4) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_FIFO_NOT_FULL_TRIG_MASK (32'h10) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_R (32'h900) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_R (32'h904) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_R (32'h908) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_R (32'h90c) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_R (32'h910) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_R (32'h914) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_R (32'h918) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_R (32'h980) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_R (32'h984) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_R (32'h988) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_R (32'h98c) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_R (32'h990) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R (32'ha00) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_CMD_DEC_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R (32'ha04) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_RD_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R (32'ha08) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_AXI_WR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R (32'ha0c) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_MBOX_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R (32'ha10) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_SHA_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R (32'ha14) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_OFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R (32'ha18) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_ERROR_FIFO_UFLOW_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R (32'ha1c) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_TXN_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R (32'ha20) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R (32'ha24) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_EMPTY_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R (32'ha28) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R (32'ha2c) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_LOW (0) `define AXI_DMA_REG_INTR_BLOCK_RF_NOTIF_FIFO_NOT_FULL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_HW_ERROR_FATAL `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL (32'h0) `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW (0) `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK (32'h1) @@ -3793,6 +7594,8 @@ `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8) `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4) `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0) +`endif +`ifndef SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL `define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4) `define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK (32'h1) @@ -3802,19 +7605,47 @@ `define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (32'h4) `define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3) `define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (32'hfffffff8) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_ERROR_FATAL `define SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (32'h8) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL `define SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL (32'hc) +`endif +`ifndef SOC_IFC_REG_CPTRA_HW_ERROR_ENC `define SOC_IFC_REG_CPTRA_HW_ERROR_ENC (32'h10) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_ERROR_ENC `define SOC_IFC_REG_CPTRA_FW_ERROR_ENC (32'h14) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 `define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (32'h18) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 `define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (32'h1c) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 `define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (32'h20) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 `define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (32'h24) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 `define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (32'h28) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 `define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (32'h2c) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 `define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (32'h30) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 `define SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (32'h34) +`endif +`ifndef SOC_IFC_REG_CPTRA_BOOT_STATUS `define SOC_IFC_REG_CPTRA_BOOT_STATUS (32'h38) +`endif +`ifndef SOC_IFC_REG_CPTRA_FLOW_STATUS `define SOC_IFC_REG_CPTRA_FLOW_STATUS (32'h3c) `define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_LOW (0) `define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK (32'hffffff) @@ -3830,11 +7661,15 @@ `define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK (32'h40000000) `define SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_LOW (31) `define SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK (32'h80000000) +`endif +`ifndef SOC_IFC_REG_CPTRA_RESET_REASON `define SOC_IFC_REG_CPTRA_RESET_REASON (32'h40) `define SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_LOW (0) `define SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK (32'h1) `define SOC_IFC_REG_CPTRA_RESET_REASON_WARM_RESET_LOW (1) `define SOC_IFC_REG_CPTRA_RESET_REASON_WARM_RESET_MASK (32'h2) +`endif +`ifndef SOC_IFC_REG_CPTRA_SECURITY_STATE `define SOC_IFC_REG_CPTRA_SECURITY_STATE (32'h44) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_LOW (0) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_MASK (32'h3) @@ -3844,72 +7679,150 @@ `define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) `define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 `define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h48) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 `define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h4c) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 `define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h50) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 `define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h54) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 `define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h58) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h5c) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h60) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h64) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h68) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h6c) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER `define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (32'h70) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK `define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h74) `define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_0 `define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (32'h78) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_1 `define SOC_IFC_REG_CPTRA_TRNG_DATA_1 (32'h7c) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_2 `define SOC_IFC_REG_CPTRA_TRNG_DATA_2 (32'h80) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_3 `define SOC_IFC_REG_CPTRA_TRNG_DATA_3 (32'h84) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_4 `define SOC_IFC_REG_CPTRA_TRNG_DATA_4 (32'h88) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_5 `define SOC_IFC_REG_CPTRA_TRNG_DATA_5 (32'h8c) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_6 `define SOC_IFC_REG_CPTRA_TRNG_DATA_6 (32'h90) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_7 `define SOC_IFC_REG_CPTRA_TRNG_DATA_7 (32'h94) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_8 `define SOC_IFC_REG_CPTRA_TRNG_DATA_8 (32'h98) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_9 `define SOC_IFC_REG_CPTRA_TRNG_DATA_9 (32'h9c) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_10 `define SOC_IFC_REG_CPTRA_TRNG_DATA_10 (32'ha0) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_DATA_11 `define SOC_IFC_REG_CPTRA_TRNG_DATA_11 (32'ha4) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_CTRL `define SOC_IFC_REG_CPTRA_TRNG_CTRL (32'ha8) `define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_LOW (0) `define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_TRNG_STATUS `define SOC_IFC_REG_CPTRA_TRNG_STATUS (32'hac) `define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW (0) `define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK (32'h1) `define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW (1) `define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK (32'h2) +`endif +`ifndef SOC_IFC_REG_CPTRA_FUSE_WR_DONE `define SOC_IFC_REG_CPTRA_FUSE_WR_DONE (32'hb0) `define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_LOW (0) `define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_TIMER_CONFIG `define SOC_IFC_REG_CPTRA_TIMER_CONFIG (32'hb4) +`endif +`ifndef SOC_IFC_REG_CPTRA_BOOTFSM_GO `define SOC_IFC_REG_CPTRA_BOOTFSM_GO (32'hb8) `define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_LOW (0) `define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG `define SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG (32'hbc) +`endif +`ifndef SOC_IFC_REG_CPTRA_CLK_GATING_EN `define SOC_IFC_REG_CPTRA_CLK_GATING_EN (32'hc0) `define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW (0) `define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0 `define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0 (32'hc4) +`endif +`ifndef SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1 `define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1 (32'hc8) +`endif +`ifndef SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 `define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (32'hcc) +`endif +`ifndef SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 `define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (32'hd0) +`endif +`ifndef SOC_IFC_REG_CPTRA_HW_REV_ID `define SOC_IFC_REG_CPTRA_HW_REV_ID (32'hd4) `define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW (0) `define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK (32'hffff) `define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW (16) `define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK (32'hffff0000) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_REV_ID_0 `define SOC_IFC_REG_CPTRA_FW_REV_ID_0 (32'hd8) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_REV_ID_1 `define SOC_IFC_REG_CPTRA_FW_REV_ID_1 (32'hdc) +`endif +`ifndef SOC_IFC_REG_CPTRA_HW_CONFIG `define SOC_IFC_REG_CPTRA_HW_CONFIG (32'he0) `define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0) `define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (32'h1) @@ -3919,180 +7832,450 @@ `define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) `define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5) `define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (32'h20) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_TIMER1_EN `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'he4) `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL `define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL (32'he8) `define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW (0) `define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 `define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'hec) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 `define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'hf0) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_TIMER2_EN `define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN (32'hf4) `define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW (0) `define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL `define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL (32'hf8) `define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW (0) `define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 `define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'hfc) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 `define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h100) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_STATUS `define SOC_IFC_REG_CPTRA_WDT_STATUS (32'h104) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW (0) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) +`endif +`ifndef SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER `define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (32'h108) +`endif +`ifndef SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK `define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h10c) `define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_CFG_0 `define SOC_IFC_REG_CPTRA_WDT_CFG_0 (32'h110) +`endif +`ifndef SOC_IFC_REG_CPTRA_WDT_CFG_1 `define SOC_IFC_REG_CPTRA_WDT_CFG_1 (32'h114) +`endif +`ifndef SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (32'h118) `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW (0) `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK (32'hffff) `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW (16) `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK (32'hffff0000) +`endif +`ifndef SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (32'h11c) `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW (0) `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK (32'hffff) `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW (16) `define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK (32'hffff0000) +`endif +`ifndef SOC_IFC_REG_CPTRA_RSVD_REG_0 `define SOC_IFC_REG_CPTRA_RSVD_REG_0 (32'h120) +`endif +`ifndef SOC_IFC_REG_CPTRA_RSVD_REG_1 `define SOC_IFC_REG_CPTRA_RSVD_REG_1 (32'h124) +`endif +`ifndef SOC_IFC_REG_CPTRA_HW_CAPABILITIES `define SOC_IFC_REG_CPTRA_HW_CAPABILITIES (32'h128) +`endif +`ifndef SOC_IFC_REG_CPTRA_FW_CAPABILITIES `define SOC_IFC_REG_CPTRA_FW_CAPABILITIES (32'h12c) +`endif +`ifndef SOC_IFC_REG_CPTRA_CAP_LOCK `define SOC_IFC_REG_CPTRA_CAP_LOCK (32'h130) `define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (32'h140) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (32'h144) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (32'h148) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (32'h14c) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (32'h150) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (32'h154) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (32'h158) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (32'h15c) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (32'h160) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (32'h164) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (32'h168) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (32'h16c) +`endif +`ifndef SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h170) `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0) `define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_0 `define SOC_IFC_REG_FUSE_UDS_SEED_0 (32'h200) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_1 `define SOC_IFC_REG_FUSE_UDS_SEED_1 (32'h204) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_2 `define SOC_IFC_REG_FUSE_UDS_SEED_2 (32'h208) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_3 `define SOC_IFC_REG_FUSE_UDS_SEED_3 (32'h20c) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_4 `define SOC_IFC_REG_FUSE_UDS_SEED_4 (32'h210) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_5 `define SOC_IFC_REG_FUSE_UDS_SEED_5 (32'h214) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_6 `define SOC_IFC_REG_FUSE_UDS_SEED_6 (32'h218) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_7 `define SOC_IFC_REG_FUSE_UDS_SEED_7 (32'h21c) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_8 `define SOC_IFC_REG_FUSE_UDS_SEED_8 (32'h220) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_9 `define SOC_IFC_REG_FUSE_UDS_SEED_9 (32'h224) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_10 `define SOC_IFC_REG_FUSE_UDS_SEED_10 (32'h228) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_11 `define SOC_IFC_REG_FUSE_UDS_SEED_11 (32'h22c) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_12 `define SOC_IFC_REG_FUSE_UDS_SEED_12 (32'h230) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_13 `define SOC_IFC_REG_FUSE_UDS_SEED_13 (32'h234) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_14 `define SOC_IFC_REG_FUSE_UDS_SEED_14 (32'h238) +`endif +`ifndef SOC_IFC_REG_FUSE_UDS_SEED_15 `define SOC_IFC_REG_FUSE_UDS_SEED_15 (32'h23c) +`endif +`ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 (32'h240) +`endif +`ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_1 `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_1 (32'h244) +`endif +`ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_2 `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_2 (32'h248) +`endif +`ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_3 `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_3 (32'h24c) +`endif +`ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_4 `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_4 (32'h250) +`endif +`ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_5 `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_5 (32'h254) +`endif +`ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_6 (32'h258) +`endif +`ifndef SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 `define SOC_IFC_REG_FUSE_FIELD_ENTROPY_7 (32'h25c) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_0 (32'h260) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_1 (32'h264) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_2 (32'h268) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_3 (32'h26c) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_4 (32'h270) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_5 (32'h274) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_6 (32'h278) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_7 (32'h27c) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_8 (32'h280) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_9 (32'h284) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_10 (32'h288) +`endif +`ifndef SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 `define SOC_IFC_REG_FUSE_VENDOR_PK_HASH_11 (32'h28c) +`endif +`ifndef SOC_IFC_REG_FUSE_ECC_REVOCATION `define SOC_IFC_REG_FUSE_ECC_REVOCATION (32'h290) `define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) `define SOC_IFC_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (32'hf) +`endif +`ifndef SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN `define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) +`endif +`ifndef SOC_IFC_REG_FUSE_RUNTIME_SVN_0 `define SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h2b8) +`endif +`ifndef SOC_IFC_REG_FUSE_RUNTIME_SVN_1 `define SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (32'h2bc) +`endif +`ifndef SOC_IFC_REG_FUSE_RUNTIME_SVN_2 `define SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (32'h2c0) +`endif +`ifndef SOC_IFC_REG_FUSE_RUNTIME_SVN_3 `define SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (32'h2c4) +`endif +`ifndef SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE `define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2c8) `define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0) `define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2cc) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2d0) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2d4) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2d8) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2dc) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2e0) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2e4) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2e8) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2ec) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h2f0) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h2f4) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h2f8) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h2fc) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h300) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h304) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h308) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h30c) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h310) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h314) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h318) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h31c) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h320) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h324) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 `define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h328) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 `define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h32c) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 `define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h330) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 `define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h334) +`endif +`ifndef SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 `define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h338) +`endif +`ifndef SOC_IFC_REG_FUSE_LMS_REVOCATION `define SOC_IFC_REG_FUSE_LMS_REVOCATION (32'h340) +`endif +`ifndef SOC_IFC_REG_FUSE_MLDSA_REVOCATION `define SOC_IFC_REG_FUSE_MLDSA_REVOCATION (32'h344) `define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0) `define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (32'hf) +`endif +`ifndef SOC_IFC_REG_FUSE_SOC_STEPPING_ID `define SOC_IFC_REG_FUSE_SOC_STEPPING_ID (32'h348) `define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0) `define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) +`endif +`ifndef SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 `define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h34c) +`endif +`ifndef SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 `define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h350) +`endif +`ifndef SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 `define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354) +`endif +`ifndef SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 `define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358) +`endif +`ifndef SOC_IFC_REG_FUSE_PQC_KEY_TYPE `define SOC_IFC_REG_FUSE_PQC_KEY_TYPE (32'h35c) `define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) `define SOC_IFC_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (32'h3) +`endif +`ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 `define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h360) +`endif +`ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 `define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h364) +`endif +`ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 `define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h368) +`endif +`ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 `define SOC_IFC_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h36c) +`endif +`ifndef SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN `define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h370) `define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) `define SOC_IFC_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (32'hff) +`endif +`ifndef SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L `define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500) +`endif +`ifndef SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H `define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (32'h504) +`endif +`ifndef SOC_IFC_REG_SS_MCI_BASE_ADDR_L `define SOC_IFC_REG_SS_MCI_BASE_ADDR_L (32'h508) +`endif +`ifndef SOC_IFC_REG_SS_MCI_BASE_ADDR_H `define SOC_IFC_REG_SS_MCI_BASE_ADDR_H (32'h50c) +`endif +`ifndef SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L `define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h510) +`endif +`ifndef SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H `define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h514) +`endif +`ifndef SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L `define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (32'h518) +`endif +`ifndef SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H `define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (32'h51c) +`endif +`ifndef SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L `define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (32'h520) +`endif +`ifndef SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H `define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (32'h524) +`endif +`ifndef SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET `define SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h528) +`endif +`ifndef SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES `define SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h52c) +`endif +`ifndef SOC_IFC_REG_SS_DEBUG_INTENT `define SOC_IFC_REG_SS_DEBUG_INTENT (32'h530) `define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0) `define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_SS_STRAP_GENERIC_0 `define SOC_IFC_REG_SS_STRAP_GENERIC_0 (32'h5a0) +`endif +`ifndef SOC_IFC_REG_SS_STRAP_GENERIC_1 `define SOC_IFC_REG_SS_STRAP_GENERIC_1 (32'h5a4) +`endif +`ifndef SOC_IFC_REG_SS_STRAP_GENERIC_2 `define SOC_IFC_REG_SS_STRAP_GENERIC_2 (32'h5a8) +`endif +`ifndef SOC_IFC_REG_SS_STRAP_GENERIC_3 `define SOC_IFC_REG_SS_STRAP_GENERIC_3 (32'h5ac) +`endif +`ifndef SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h5c0) `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0) `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (32'h1) @@ -4102,6 +8285,8 @@ `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (32'h4) `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3) `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (32'hfffffff8) +`endif +`ifndef SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h5c4) `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0) `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (32'h1) @@ -4123,30 +8308,68 @@ `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (32'h100) `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9) `define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (32'hfffffe00) +`endif +`ifndef SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 `define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h5c8) +`endif +`ifndef SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 `define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h5cc) +`endif +`ifndef SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 `define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h5d0) +`endif +`ifndef SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 `define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h5d4) +`endif +`ifndef SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 `define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h5d8) +`endif +`ifndef SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 `define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h5dc) +`endif +`ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_0 `define SOC_IFC_REG_INTERNAL_OBF_KEY_0 (32'h600) +`endif +`ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_1 `define SOC_IFC_REG_INTERNAL_OBF_KEY_1 (32'h604) +`endif +`ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_2 `define SOC_IFC_REG_INTERNAL_OBF_KEY_2 (32'h608) +`endif +`ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_3 `define SOC_IFC_REG_INTERNAL_OBF_KEY_3 (32'h60c) +`endif +`ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_4 `define SOC_IFC_REG_INTERNAL_OBF_KEY_4 (32'h610) +`endif +`ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_5 `define SOC_IFC_REG_INTERNAL_OBF_KEY_5 (32'h614) +`endif +`ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_6 `define SOC_IFC_REG_INTERNAL_OBF_KEY_6 (32'h618) +`endif +`ifndef SOC_IFC_REG_INTERNAL_OBF_KEY_7 `define SOC_IFC_REG_INTERNAL_OBF_KEY_7 (32'h61c) +`endif +`ifndef SOC_IFC_REG_INTERNAL_ICCM_LOCK `define SOC_IFC_REG_INTERNAL_ICCM_LOCK (32'h620) `define SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_LOW (0) `define SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET `define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET (32'h624) `define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_LOW (0) `define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES `define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES (32'h628) `define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_LOW (0) `define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_MASK (32'hff) +`endif +`ifndef SOC_IFC_REG_INTERNAL_NMI_VECTOR `define SOC_IFC_REG_INTERNAL_NMI_VECTOR (32'h62c) +`endif +`ifndef SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK `define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK (32'h630) `define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_LOW (0) `define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK (32'h1) @@ -4156,6 +8379,8 @@ `define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK (32'h4) `define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_CRYPTO_ERR_LOW (3) `define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_CRYPTO_ERR_MASK (32'h8) +`endif +`ifndef SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK `define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK (32'h634) `define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_LOW (0) `define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_MASK (32'h1) @@ -4163,17 +8388,33 @@ `define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_MASK (32'h2) `define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_LOW (2) `define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK (32'h4) +`endif +`ifndef SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK `define SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK (32'h638) +`endif +`ifndef SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK `define SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK (32'h63c) +`endif +`ifndef SOC_IFC_REG_INTERNAL_RV_MTIME_L `define SOC_IFC_REG_INTERNAL_RV_MTIME_L (32'h640) +`endif +`ifndef SOC_IFC_REG_INTERNAL_RV_MTIME_H `define SOC_IFC_REG_INTERNAL_RV_MTIME_H (32'h644) +`endif +`ifndef SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L `define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L (32'h648) +`endif +`ifndef SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H `define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H (32'h64c) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R `define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R (32'h800) `define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK (32'h1) `define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_LOW (1) `define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK (32'h2) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R (32'h804) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK (32'h1) @@ -4191,6 +8432,8 @@ `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK (32'h40) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_LOW (7) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK (32'h80) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R (32'h808) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_MASK (32'h1) @@ -4204,12 +8447,18 @@ `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK (32'h10) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_LOW (5) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK (32'h20) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R (32'h80c) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R (32'h810) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R (32'h814) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK (32'h1) @@ -4227,6 +8476,8 @@ `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK (32'h40) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_LOW (7) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK (32'h80) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R (32'h818) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK (32'h1) @@ -4240,6 +8491,8 @@ `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK (32'h10) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_LOW (5) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK (32'h20) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R (32'h81c) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK (32'h1) @@ -4257,6 +8510,8 @@ `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER1_TIMEOUT_TRIG_MASK (32'h40) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_LOW (7) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_MASK (32'h80) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R (32'h820) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_MASK (32'h1) @@ -4270,62 +8525,119 @@ `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK (32'h10) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_LOW (5) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_MASK (32'h20) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R (32'h900) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R (32'h904) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R (32'h908) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R (32'h90c) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R (32'h910) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R (32'h914) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R (32'h918) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R (32'h91c) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R (32'h980) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R (32'h984) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R (32'h988) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R (32'h98c) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R (32'h990) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R (32'h994) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'ha00) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R (32'ha04) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R (32'ha08) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R (32'ha0c) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R (32'ha10) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R (32'ha14) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R (32'ha18) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R (32'ha1c) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R (32'ha20) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R (32'ha24) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R (32'ha28) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R (32'ha2c) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R (32'ha30) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif +`ifndef SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R (32'ha34) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW (0) `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1) +`endif `endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index dc0794cf1..b58d4ff13 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -19,24 +19,39 @@ #define CALIPTRA_TOP_REG_BASE_ADDR (0x0) #define CALIPTRA_TOP_REG_MBOX_CSR_BASE_ADDR (0x20000) #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_LOCK (0x20000) +#ifndef MBOX_CSR_MBOX_LOCK #define MBOX_CSR_MBOX_LOCK (0x0) #define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) #define MBOX_CSR_MBOX_LOCK_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_USER (0x20004) +#ifndef MBOX_CSR_MBOX_USER #define MBOX_CSR_MBOX_USER (0x4) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_CMD (0x20008) +#ifndef MBOX_CSR_MBOX_CMD #define MBOX_CSR_MBOX_CMD (0x8) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DLEN (0x2000c) +#ifndef MBOX_CSR_MBOX_DLEN #define MBOX_CSR_MBOX_DLEN (0xc) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DATAIN (0x20010) +#ifndef MBOX_CSR_MBOX_DATAIN #define MBOX_CSR_MBOX_DATAIN (0x10) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_DATAOUT (0x20014) +#ifndef MBOX_CSR_MBOX_DATAOUT #define MBOX_CSR_MBOX_DATAOUT (0x14) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_EXECUTE (0x20018) +#ifndef MBOX_CSR_MBOX_EXECUTE #define MBOX_CSR_MBOX_EXECUTE (0x18) #define MBOX_CSR_MBOX_EXECUTE_EXECUTE_LOW (0) #define MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_STATUS (0x2001c) +#ifndef MBOX_CSR_MBOX_STATUS #define MBOX_CSR_MBOX_STATUS (0x1c) #define MBOX_CSR_MBOX_STATUS_STATUS_LOW (0) #define MBOX_CSR_MBOX_STATUS_STATUS_MASK (0xf) @@ -50,16 +65,22 @@ #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (0x200) #define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) #define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (0x3fffc00) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_UNLOCK (0x20020) +#ifndef MBOX_CSR_MBOX_UNLOCK #define MBOX_CSR_MBOX_UNLOCK (0x20) #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_MBOX_CSR_TAP_MODE (0x20024) +#ifndef MBOX_CSR_TAP_MODE #define MBOX_CSR_TAP_MODE (0x24) #define MBOX_CSR_TAP_MODE_ENABLED_LOW (0) #define MBOX_CSR_TAP_MODE_ENABLED_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_BASE_ADDR (0x30000) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (0x30000) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (0x0) #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK (0x1) @@ -71,7 +92,9 @@ #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (0x8) #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4) #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (0xfffffff0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (0x30004) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (0x4) #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK (0x1) @@ -81,33 +104,61 @@ #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (0x4) #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3) #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (0xfffffff8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (0x30008) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL #define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (0x8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL (0x3000c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL #define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL (0xc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_ENC (0x30010) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_ENC #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_ENC (0x10) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_ENC (0x30014) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_ENC #define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_ENC (0x14) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (0x30018) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 #define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (0x18) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (0x3001c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 #define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (0x1c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (0x30020) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 #define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (0x20) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (0x30024) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 #define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (0x24) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (0x30028) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 #define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (0x28) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (0x3002c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 #define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (0x2c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (0x30030) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 #define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (0x30) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (0x30034) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 #define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (0x34) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_BOOT_STATUS (0x30038) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_BOOT_STATUS #define GENERIC_AND_FUSE_REG_CPTRA_BOOT_STATUS (0x38) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS (0x3003c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS (0x3c) #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_MASK (0xffffff) @@ -123,13 +174,17 @@ #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK (0x40000000) #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_LOW (31) #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK (0x80000000) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON (0x30040) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON #define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON (0x40) #define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_FW_UPD_RESET_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK (0x1) #define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_WARM_RESET_LOW (1) #define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_WARM_RESET_MASK (0x2) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE (0x30044) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE (0x44) #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_MASK (0x3) @@ -139,111 +194,189 @@ #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (0x8) #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) #define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_MASK (0xfffffff0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x30048) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x48) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x3004c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x4c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x30050) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x50) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x30054) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x54) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x30058) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x58) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x3005c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x5c) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x30060) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x60) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x30064) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x64) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x30068) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x68) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x3006c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x6c) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (0x30070) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (0x70) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (0x30074) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (0x74) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (0x30078) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (0x78) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (0x3007c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (0x7c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_2 (0x30080) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_2 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_2 (0x80) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_3 (0x30084) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_3 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_3 (0x84) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_4 (0x30088) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_4 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_4 (0x88) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_5 (0x3008c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_5 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_5 (0x8c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_6 (0x30090) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_6 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_6 (0x90) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_7 (0x30094) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_7 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_7 (0x94) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_8 (0x30098) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_8 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_8 (0x98) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_9 (0x3009c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_9 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_9 (0x9c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10 (0x300a0) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10 (0xa0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11 (0x300a4) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11 (0xa4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL (0x300a8) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL (0xa8) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS (0x300ac) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS (0xac) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK (0x1) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW (1) #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK (0x2) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE (0x300b0) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE (0xb0) #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG (0x300b4) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG #define GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG (0xb4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO (0x300b8) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO #define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO (0xb8) #define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG (0x300bc) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG #define GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG (0xbc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN (0x300c0) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN #define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN (0xc0) #define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0 (0x300c4) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0 #define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0 (0xc4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1 (0x300c8) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1 #define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1 (0xc8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (0x300cc) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 #define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (0xcc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (0x300d0) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 #define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (0xd0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID (0x300d4) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID #define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID (0xd4) #define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK (0xffff) #define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW (16) #define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK (0xffff0000) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0 (0x300d8) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0 #define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0 (0xd8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1 (0x300dc) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1 #define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1 (0xdc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG (0x300e0) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG (0xe0) #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (0x1) @@ -253,315 +386,585 @@ #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10) #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5) #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (0x20) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (0x300e4) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (0xe4) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL (0x300e8) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL (0xe8) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (0x300ec) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (0xec) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (0x300f0) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (0xf0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN (0x300f4) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN (0xf4) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL (0x300f8) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL (0xf8) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (0x300fc) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (0xfc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (0x30100) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (0x100) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS (0x30104) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS (0x104) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (0x1) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (0x2) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (0x30108) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (0x108) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (0x3010c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (0x10c) #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (0x30110) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (0x110) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (0x30114) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (0x114) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (0x30118) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (0x118) #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK (0xffff) #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW (16) #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK (0xffff0000) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (0x3011c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (0x11c) #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK (0xffff) #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW (16) #define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK (0xffff0000) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 (0x30120) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 #define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 (0x120) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (0x30124) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 #define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (0x124) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (0x30128) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES #define GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (0x128) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (0x3012c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES #define GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (0x12c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (0x30130) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK #define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (0x130) #define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (0x30140) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (0x140) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (0x30144) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (0x144) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (0x30148) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (0x148) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (0x3014c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (0x14c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (0x30150) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (0x150) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (0x30154) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (0x154) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (0x30158) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (0x158) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (0x3015c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (0x15c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (0x30160) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (0x160) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (0x30164) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (0x164) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (0x30168) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (0x168) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (0x3016c) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (0x16c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (0x30170) +#ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (0x170) #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0) #define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (0x30200) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (0x200) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 (0x30204) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 (0x204) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_2 (0x30208) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_2 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_2 (0x208) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_3 (0x3020c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_3 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_3 (0x20c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_4 (0x30210) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_4 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_4 (0x210) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_5 (0x30214) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_5 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_5 (0x214) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_6 (0x30218) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_6 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_6 (0x218) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_7 (0x3021c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_7 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_7 (0x21c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_8 (0x30220) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_8 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_8 (0x220) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_9 (0x30224) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_9 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_9 (0x224) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_10 (0x30228) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_10 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_10 (0x228) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_11 (0x3022c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_11 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_11 (0x22c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_12 (0x30230) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_12 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_12 (0x230) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_13 (0x30234) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_13 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_13 (0x234) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_14 (0x30238) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_14 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_14 (0x238) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_15 (0x3023c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_15 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_15 (0x23c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_0 (0x30240) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_0 #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_0 (0x240) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_1 (0x30244) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_1 #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_1 (0x244) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_2 (0x30248) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_2 #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_2 (0x248) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_3 (0x3024c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_3 #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_3 (0x24c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_4 (0x30250) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_4 #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_4 (0x250) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_5 (0x30254) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_5 #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_5 (0x254) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 (0x30258) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 (0x258) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (0x3025c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 #define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (0x25c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (0x30260) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (0x260) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (0x30264) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (0x264) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (0x30268) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (0x268) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (0x3026c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (0x26c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (0x30270) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (0x270) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (0x30274) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (0x274) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (0x30278) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (0x278) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (0x3027c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (0x27c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (0x30280) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (0x280) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (0x30284) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (0x284) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (0x30288) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (0x288) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (0x3028c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 #define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (0x28c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (0x30290) +#ifndef GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION #define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (0x290) #define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) #define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (0xf) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x302b4) +#ifndef GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN #define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2b4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (0x302b8) +#ifndef GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 #define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (0x2b8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (0x302bc) +#ifndef GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 #define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (0x2bc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (0x302c0) +#ifndef GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 #define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (0x2c0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (0x302c4) +#ifndef GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 #define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (0x2c4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x302c8) +#ifndef GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE #define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x2c8) #define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0) #define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (0x302cc) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (0x2cc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (0x302d0) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (0x2d0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (0x302d4) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (0x2d4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (0x302d8) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (0x2d8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (0x302dc) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (0x2dc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (0x302e0) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (0x2e0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (0x302e4) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (0x2e4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (0x302e8) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (0x2e8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (0x302ec) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (0x2ec) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (0x302f0) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (0x2f0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (0x302f4) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (0x2f4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (0x302f8) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (0x2f8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (0x302fc) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (0x2fc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (0x30300) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (0x300) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (0x30304) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (0x304) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (0x30308) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (0x308) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (0x3030c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (0x30c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (0x30310) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (0x310) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (0x30314) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (0x314) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (0x30318) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (0x318) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (0x3031c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (0x31c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (0x30320) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (0x320) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (0x30324) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (0x324) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (0x30328) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (0x328) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x3032c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x32c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x30330) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x330) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x30334) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x334) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x30338) +#ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 #define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x338) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (0x30340) +#ifndef GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION #define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (0x340) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (0x30344) +#ifndef GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION #define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (0x344) #define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0) #define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (0xf) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (0x30348) +#ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID #define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (0x348) #define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0) #define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (0xffff) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (0x3034c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 #define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (0x34c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (0x30350) +#ifndef GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 #define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (0x350) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x30354) +#ifndef GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 #define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x354) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x30358) +#ifndef GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 #define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x358) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (0x3035c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE #define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (0x35c) #define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) #define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (0x3) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (0x30360) +#ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 #define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (0x360) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (0x30364) +#ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 #define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (0x364) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (0x30368) +#ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 #define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (0x368) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (0x3036c) +#ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 #define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (0x36c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (0x30370) +#ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN #define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (0x370) #define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) #define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (0xff) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (0x30500) +#ifndef GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L #define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (0x500) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (0x30504) +#ifndef GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H #define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (0x504) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (0x30508) +#ifndef GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L #define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (0x508) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (0x3050c) +#ifndef GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H #define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (0x50c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (0x30510) +#ifndef GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L #define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (0x510) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (0x30514) +#ifndef GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H #define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (0x514) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (0x30518) +#ifndef GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L #define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (0x518) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (0x3051c) +#ifndef GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H #define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (0x51c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (0x30520) +#ifndef GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L #define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (0x520) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (0x30524) +#ifndef GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H #define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (0x524) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x30528) +#ifndef GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET #define GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x528) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x3052c) +#ifndef GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES #define GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x52c) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (0x30530) +#ifndef GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT #define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (0x530) #define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0) #define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (0x1) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (0x305a0) +#ifndef GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 #define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (0x5a0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (0x305a4) +#ifndef GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 #define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (0x5a4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (0x305a8) +#ifndef GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 #define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (0x5a8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (0x305ac) +#ifndef GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 #define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (0x5ac) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (0x305c0) +#ifndef GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (0x5c0) #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0) #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (0x1) @@ -571,7 +974,9 @@ #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (0x4) #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3) #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (0xfffffff8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (0x305c4) +#ifndef GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (0x5c4) #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0) #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (0x1) @@ -593,18 +998,31 @@ #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (0x100) #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9) #define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (0xfffffe00) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x305c8) +#ifndef GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 #define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x5c8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x305cc) +#ifndef GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 #define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x5cc) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x305d0) +#ifndef GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 #define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x5d0) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x305d4) +#ifndef GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 #define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x5d4) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (0x305d8) +#ifndef GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 #define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (0x5d8) +#endif #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (0x305dc) +#ifndef GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 #define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (0x5dc) +#endif #endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/caliptra_top_reg_field_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_field_defines.svh index d53601ca4..dcf518e08 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_field_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_field_defines.svh @@ -16,17 +16,32 @@ `define CALIPTRA_TOP_REG_FIELD_DEFINES_HEADER +`ifndef MBOX_CSR_MBOX_LOCK `define MBOX_CSR_MBOX_LOCK (32'h0) `define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0) `define MBOX_CSR_MBOX_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef MBOX_CSR_MBOX_USER `define MBOX_CSR_MBOX_USER (32'h4) +`endif +`ifndef MBOX_CSR_MBOX_CMD `define MBOX_CSR_MBOX_CMD (32'h8) +`endif +`ifndef MBOX_CSR_MBOX_DLEN `define MBOX_CSR_MBOX_DLEN (32'hc) +`endif +`ifndef MBOX_CSR_MBOX_DATAIN `define MBOX_CSR_MBOX_DATAIN (32'h10) +`endif +`ifndef MBOX_CSR_MBOX_DATAOUT `define MBOX_CSR_MBOX_DATAOUT (32'h14) +`endif +`ifndef MBOX_CSR_MBOX_EXECUTE `define MBOX_CSR_MBOX_EXECUTE (32'h18) `define MBOX_CSR_MBOX_EXECUTE_EXECUTE_LOW (0) `define MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK (32'h1) +`endif +`ifndef MBOX_CSR_MBOX_STATUS `define MBOX_CSR_MBOX_STATUS (32'h1c) `define MBOX_CSR_MBOX_STATUS_STATUS_LOW (0) `define MBOX_CSR_MBOX_STATUS_STATUS_MASK (32'hf) @@ -40,12 +55,18 @@ `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK (32'h200) `define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW (10) `define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK (32'h3fffc00) +`endif +`ifndef MBOX_CSR_MBOX_UNLOCK `define MBOX_CSR_MBOX_UNLOCK (32'h20) `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0) `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (32'h1) +`endif +`ifndef MBOX_CSR_TAP_MODE `define MBOX_CSR_TAP_MODE (32'h24) `define MBOX_CSR_TAP_MODE_ENABLED_LOW (0) `define MBOX_CSR_TAP_MODE_ENABLED_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (32'h0) `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK (32'h1) @@ -57,6 +78,8 @@ `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8) `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4) `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4) `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK (32'h1) @@ -66,19 +89,47 @@ `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (32'h4) `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3) `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (32'hfffffff8) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL `define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (32'h8) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL `define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL (32'hc) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_ENC `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_ENC (32'h10) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_ENC `define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_ENC (32'h14) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 `define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0 (32'h18) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 `define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1 (32'h1c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 `define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2 (32'h20) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 `define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3 (32'h24) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 `define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4 (32'h28) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 `define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5 (32'h2c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 `define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6 (32'h30) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 `define GENERIC_AND_FUSE_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7 (32'h34) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_BOOT_STATUS `define GENERIC_AND_FUSE_REG_CPTRA_BOOT_STATUS (32'h38) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS (32'h3c) `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_MASK (32'hffffff) @@ -94,11 +145,15 @@ `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK (32'h40000000) `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_LOW (31) `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK (32'h80000000) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON `define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON (32'h40) `define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_FW_UPD_RESET_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK (32'h1) `define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_WARM_RESET_LOW (1) `define GENERIC_AND_FUSE_REG_CPTRA_RESET_REASON_WARM_RESET_MASK (32'h2) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE (32'h44) `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_DEVICE_LIFECYCLE_MASK (32'h3) @@ -108,72 +163,150 @@ `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (32'h8) `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4) `define GENERIC_AND_FUSE_REG_CPTRA_SECURITY_STATE_RSVD_MASK (32'hfffffff0) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_0 (32'h48) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_1 (32'h4c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_2 (32'h50) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_3 (32'h54) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_VALID_AXI_USER_4 (32'h58) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (32'h5c) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (32'h60) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (32'h64) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (32'h68) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (32'h6c) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_VALID_AXI_USER (32'h70) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK (32'h74) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_0 (32'h78) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_1 (32'h7c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_2 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_2 (32'h80) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_3 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_3 (32'h84) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_4 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_4 (32'h88) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_5 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_5 (32'h8c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_6 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_6 (32'h90) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_7 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_7 (32'h94) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_8 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_8 (32'h98) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_9 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_9 (32'h9c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10 (32'ha0) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11 (32'ha4) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL (32'ha8) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS (32'hac) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK (32'h1) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW (1) `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK (32'h2) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE (32'hb0) `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG `define GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG (32'hb4) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO `define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO (32'hb8) `define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG `define GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG (32'hbc) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN `define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN (32'hc0) `define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0 `define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0 (32'hc4) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1 `define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1 (32'hc8) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 `define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0 (32'hcc) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 `define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1 (32'hd0) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID `define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID (32'hd4) `define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK (32'hffff) `define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW (16) `define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK (32'hffff0000) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0 `define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0 (32'hd8) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1 `define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1 (32'hdc) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG (32'he0) `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (32'h1) @@ -183,180 +316,450 @@ `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5) `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (32'h20) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'he4) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL (32'he8) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0 (32'hec) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1 (32'hf0) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN (32'hf4) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL (32'hf8) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0 (32'hfc) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1 (32'h100) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS (32'h104) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (32'h1) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (32'h2) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_AXI_USER (32'h108) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK (32'h10c) `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0 (32'h110) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1 (32'h114) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0 (32'h118) `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK (32'hffff) `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW (16) `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK (32'hffff0000) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1 (32'h11c) `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK (32'hffff) `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW (16) `define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK (32'hffff0000) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 `define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 (32'h120) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 `define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (32'h124) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES `define GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (32'h128) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES `define GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (32'h12c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK `define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (32'h130) `define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (32'h140) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (32'h144) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (32'h148) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (32'h14c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (32'h150) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (32'h154) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (32'h158) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (32'h15c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (32'h160) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (32'h164) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (32'h168) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (32'h16c) +`endif +`ifndef GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h170) `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0) `define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (32'h200) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 (32'h204) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_2 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_2 (32'h208) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_3 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_3 (32'h20c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_4 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_4 (32'h210) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_5 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_5 (32'h214) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_6 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_6 (32'h218) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_7 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_7 (32'h21c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_8 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_8 (32'h220) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_9 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_9 (32'h224) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_10 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_10 (32'h228) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_11 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_11 (32'h22c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_12 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_12 (32'h230) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_13 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_13 (32'h234) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_14 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_14 (32'h238) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_15 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_15 (32'h23c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_0 `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_0 (32'h240) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_1 `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_1 (32'h244) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_2 `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_2 (32'h248) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_3 `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_3 (32'h24c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_4 `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_4 (32'h250) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_5 `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_5 (32'h254) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_6 (32'h258) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 `define GENERIC_AND_FUSE_REG_FUSE_FIELD_ENTROPY_7 (32'h25c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_0 (32'h260) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_1 (32'h264) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_2 (32'h268) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_3 (32'h26c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_4 (32'h270) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_5 (32'h274) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_6 (32'h278) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_7 (32'h27c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_8 (32'h280) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_9 (32'h284) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_10 (32'h288) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 `define GENERIC_AND_FUSE_REG_FUSE_VENDOR_PK_HASH_11 (32'h28c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION `define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION (32'h290) `define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_LOW (0) `define GENERIC_AND_FUSE_REG_FUSE_ECC_REVOCATION_ECC_REVOCATION_MASK (32'hf) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN `define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 `define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h2b8) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 `define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (32'h2bc) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 `define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (32'h2c0) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 `define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (32'h2c4) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE `define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2c8) `define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0) `define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2cc) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2d0) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2d4) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2d8) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2dc) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2e0) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2e4) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2e8) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2ec) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h2f0) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h2f4) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h2f8) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h2fc) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h300) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h304) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h308) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h30c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h310) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h314) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h318) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h31c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h320) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h324) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h328) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h32c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h330) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h334) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 `define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h338) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION `define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (32'h340) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION `define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (32'h344) `define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0) `define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (32'hf) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID `define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (32'h348) `define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0) `define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 `define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h34c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 `define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h350) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 `define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 `define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE `define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE (32'h35c) `define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_LOW (0) `define GENERIC_AND_FUSE_REG_FUSE_PQC_KEY_TYPE_KEY_TYPE_MASK (32'h3) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 `define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_0 (32'h360) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 `define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_1 (32'h364) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 `define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_2 (32'h368) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 `define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_SVN_3 (32'h36c) +`endif +`ifndef GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN `define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN (32'h370) `define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_LOW (0) `define GENERIC_AND_FUSE_REG_FUSE_SOC_MANIFEST_MAX_SVN_SVN_MASK (32'hff) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L `define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H `define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (32'h504) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L `define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (32'h508) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H `define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (32'h50c) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L `define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h510) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H `define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h514) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L `define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (32'h518) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H `define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (32'h51c) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L `define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (32'h520) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H `define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (32'h524) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET `define GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h528) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES `define GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h52c) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT `define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (32'h530) `define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0) `define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (32'h1) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 `define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (32'h5a0) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 `define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (32'h5a4) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 `define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (32'h5a8) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 `define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (32'h5ac) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h5c0) `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0) `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (32'h1) @@ -366,6 +769,8 @@ `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (32'h4) `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3) `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (32'hfffffff8) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h5c4) `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0) `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (32'h1) @@ -387,12 +792,25 @@ `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (32'h100) `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9) `define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (32'hfffffe00) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 `define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h5c8) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 `define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h5cc) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 `define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h5d0) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 `define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h5d4) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 `define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h5d8) +`endif +`ifndef GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 `define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h5dc) +`endif `endif \ No newline at end of file diff --git a/tools/scripts/reg_doc_gen.py b/tools/scripts/reg_doc_gen.py index 314b09dfa..f109d2e7e 100644 --- a/tools/scripts/reg_doc_gen.py +++ b/tools/scripts/reg_doc_gen.py @@ -92,7 +92,11 @@ def enter_Reg(self, node): if self.tick == "`": address = address.replace("0x", "32'h", 1) if self.do_rel == 1: + self.file.write( self.tick + "ifndef " + register_name.upper() + "\n") self.file.write((self.tick + "define " + register_name.upper() + "\t(" + address + ")\n").expandtabs(100)) + def exit_Reg(self, node): + if self.do_rel == 1: + self.file.write( self.tick + "endif\n") def enter_Field(self, node): field_name = node.get_rel_path(self.top_node.parent,"^","_",'_{index:d}') if node.width == 1: From 4ed4b87192e7329ef81beda99d4137fbb4c22d33 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 17 Jan 2025 10:26:58 -0800 Subject: [PATCH 7/9] Significantly reduce test run-time by only accessing boundary dwords --- .../smoke_test_mbox_byte_read.c | 47 +++++++++++++++---- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c b/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c index 49a6b46b4..70ef0730f 100644 --- a/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c +++ b/src/integration/test_suites/smoke_test_mbox_byte_read/smoke_test_mbox_byte_read.c @@ -34,7 +34,7 @@ void main () { uint32_t data; uint8_t* read_addr; - uint8_t odd_offset; +// uint8_t odd_offset; // Message VPRINTF(LOW, "----------------------------------\n"); @@ -48,22 +48,26 @@ void main () { while(1); } - //Randomize odd or even entries to shorten test run time - odd_offset = (rand() % 2) * 4; +// //Randomize odd or even entries to shorten test run time +// odd_offset = (rand() % 2) * 4; // Write data to fill mailbox - for (data = CLP_MBOX_SRAM_BASE_ADDR + odd_offset; data < CLP_MBOX_SRAM_END_ADDR; data+=8) { + // Only write 1 dword on either side of the 1KiB boundaries to reduce sim-time + // This should catch any interesting edge-cases + for (data = CLP_MBOX_SRAM_BASE_ADDR; data < CLP_MBOX_SRAM_END_ADDR; data+=1024) { // Data written is the address being written to - lsu_write_32((uintptr_t) data, data); - if ((data & 0xfff) == odd_offset) { + if (((data & 0x3fff) == 0) || (verbosity_g > MEDIUM)) { VPRINTF(MEDIUM, "Writing [0x%x] to addr [0x%x]\n", data, data) } + lsu_write_32((uintptr_t) data, data); + VPRINTF(HIGH, "Writing [0x%x] to addr [0x%x]\n", data + 1020, data + 1020) + lsu_write_32((uintptr_t) data + 1020, data + 1020); } // Read back one byte at a time and check values - read_addr = (uint8_t*) CLP_MBOX_SRAM_BASE_ADDR + odd_offset; + read_addr = (uint8_t*) CLP_MBOX_SRAM_BASE_ADDR; while(read_addr <= (uint8_t*) CLP_MBOX_SRAM_END_ADDR) { - if (((uintptr_t)read_addr & 0xfff) == odd_offset) { + if ((((uintptr_t)read_addr & 0x3fff) == 0) || (verbosity_g > MEDIUM)) { VPRINTF(MEDIUM, "Reading from addr [0x%x]\n", read_addr) } // Data should match the address being read from @@ -91,7 +95,32 @@ void main () { while(1); } read_addr++; - read_addr += 4; + read_addr += 1016; + // Data should match the address being read from + if (*read_addr != (uint8_t)(((uintptr_t) read_addr) )) { + VPRINTF(ERROR, "ERROR: Data mismatch at addr [0x%x]. Exp [0x%x] got [0x%x]\n", (uintptr_t) read_addr, (uint8_t)(((uintptr_t) read_addr) >> 0 ), *read_addr); + SEND_STDOUT_CTRL( 0x1); + while(1); + } + read_addr++; + if (*read_addr != (uint8_t)(((uintptr_t) read_addr) >> 8)) { + VPRINTF(ERROR, "ERROR: Data mismatch at addr [0x%x]. Exp [0x%x] got [0x%x]\n", (uintptr_t) read_addr, (uint8_t)(((uintptr_t) read_addr) >> 8 ), *read_addr); + SEND_STDOUT_CTRL( 0x1); + while(1); + } + read_addr++; + if (*read_addr != (uint8_t)(((uintptr_t) read_addr) >> 16)) { + VPRINTF(ERROR, "ERROR: Data mismatch at addr [0x%x]. Exp [0x%x] got [0x%x]\n", (uintptr_t) read_addr, (uint8_t)(((uintptr_t) read_addr) >> 16), *read_addr); + SEND_STDOUT_CTRL( 0x1); + while(1); + } + read_addr++; + if (*read_addr != (uint8_t)(((uintptr_t) read_addr) >> 24)) { + VPRINTF(ERROR, "ERROR: Data mismatch at addr [0x%x]. Exp [0x%x] got [0x%x]\n", (uintptr_t) read_addr, (uint8_t)(((uintptr_t) read_addr) >> 24), *read_addr); + SEND_STDOUT_CTRL( 0x1); + while(1); + } + read_addr++; } // Force unlock From 8f32d19577c92957bc2e087e88ba0634484bae9e Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 17 Jan 2025 11:07:15 -0800 Subject: [PATCH 8/9] Don't explicitly compile include file --- src/integration/config/compile.yml | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml index 8a249d664..4ec954362 100644 --- a/src/integration/config/compile.yml +++ b/src/integration/config/compile.yml @@ -7,12 +7,10 @@ targets: files: - $COMPILE_ROOT/rtl/config_defines.svh - $COMPILE_ROOT/rtl/caliptra_reg_defines.svh - - $COMPILE_ROOT/rtl/caliptra_reg_field_defines.svh rtl: directories: [$COMPILE_ROOT/rtl] files: - $COMPILE_ROOT/rtl/config_defines.svh - - $COMPILE_ROOT/rtl/caliptra_reg_field_defines.svh --- provides: [caliptra_top] schema_version: 2.4.0 From de8587213e1b5f5904028745945096be1611a984 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 17 Jan 2025 12:23:53 -0800 Subject: [PATCH 9/9] Regenerate file lists --- src/integration/config/caliptra_top_defines.vf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/integration/config/caliptra_top_defines.vf b/src/integration/config/caliptra_top_defines.vf index 32aaeaef2..7ec5f7f65 100644 --- a/src/integration/config/caliptra_top_defines.vf +++ b/src/integration/config/caliptra_top_defines.vf @@ -1,4 +1,4 @@ +incdir+${CALIPTRA_ROOT}/src/integration/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh -${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh \ No newline at end of file +${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh \ No newline at end of file