From 55790bd955a7d86ec7d7692395e79ca805709b2e Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur.heymans@9elements.com>
Date: Thu, 19 Dec 2024 14:43:42 +0100
Subject: [PATCH] Implement add ops for AxiAddr

Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
---
 drivers/src/dma.rs | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/src/dma.rs b/drivers/src/dma.rs
index 56936dea5f..bab3d91ded 100644
--- a/drivers/src/dma.rs
+++ b/drivers/src/dma.rs
@@ -17,6 +17,7 @@ use caliptra_registers::axi_dma::{
     enums::{RdRouteE, WrRouteE},
     AxiDmaReg,
 };
+use core::ops::Add;
 use zerocopy::AsBytes;
 
 pub enum DmaReadTarget {
@@ -39,6 +40,22 @@ impl From<u64> for AxiAddr {
         }
     }
 }
+impl From<AxiAddr> for u64 {
+    fn from(addr: AxiAddr) -> Self {
+        (addr.hi as u64) << 32 | (addr.lo as u64)
+    }
+}
+
+impl Add for AxiAddr {
+    type Output = Self;
+
+    fn add(self, rhs: Self) -> Self {
+        let self_u64: u64 = self.into();
+        let rhs_u64: u64 = rhs.into();
+        let sum = self_u64 + rhs_u64;
+        sum.into()
+    }
+}
 
 pub struct DmaReadTransaction {
     pub read_addr: AxiAddr,