From 54193856499a4849a401710e208ebbb8d09a72dd Mon Sep 17 00:00:00 2001 From: Albert Chen Date: Wed, 29 Nov 2023 16:37:24 +0800 Subject: [PATCH] update Initialization Coverage spec for zero-width Specify that non-zero-width components must be initialized, while zero-width components are implicitly initialized with value zero. --- spec.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/spec.md b/spec.md index d5b439da..8aa0ba27 100644 --- a/spec.md +++ b/spec.md @@ -1616,8 +1616,10 @@ module MyModule : ``` This is an illegal FIRRTL circuit and an error will be thrown during compilation. -All wires, memory ports, instance ports, and module ports that can be connected to must be connected to under all conditions. +All non-zero-width wires, memory ports, instance ports, and module ports that can be connected to must be connected to under all conditions. Registers do not need to be connected to under all conditions, as it will keep its previous value if unconnected. +Zero-width wires, memory ports, instance ports, and module ports do not need to be connected. +These are implicitly initialized with a value of zero. ## Conditional Scopes