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Internal error when loading masked memory from file #2492
Comments
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I've determined that the "correct" way to do this is to avoid using a Vec memory and instead do the masking manually: class Ram(size: Int, addrw: Int, dataw: Int, memfile: String = "") extends Module {
val io = IO(Flipped(new RamIO(addrw, dataw)))
val mem = SyncReadMem(size, UInt(dataw.W))
if (memfile.trim().nonEmpty) {
loadMemoryFromFileInline(mem, memfile)
}
val rvalid = RegNext(io.req)
io.rvalid := rvalid
val addr = io.addr / (dataw / 8).U
io.rdata := mem.read(addr, io.req)
val write = (0 until (dataw / 8)).foldLeft(0.U(dataw.W)) { (write, i) =>
write |
(Mux(
io.req && io.be(i),
io.wdata,
mem(addr)
)(8 * (i + 1) - 1, 8 * i) << (8 * i).U).asUInt
}
when (io.req && io.we) {
mem.write(addr, write)
}
}Leaving this open since the original behavior is still a bug. I also noticed that this issue is related to #1289. Note: this doesn't actually work the way you want, so you have to use an external verilog ram. |
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Checklist
What is the current behavior?
I am trying to make a memory that supports masked writes, and initialize it from a hex file for simulation. Following documentation online I arrived at:
where
mem/test.hexisWhen I attempt to run this (generate Verilog) or run a test simulation it produces an internal error:
Full error message below:
I think the error is caused by the memory masking, but I am not sure how to fix it (different hex file format? different Chisel implementation?). I couldn't find any details in the documentation.
What is the expected behavior?
I would expect it to generate Verilog with a
readmemhstatement to load the memory from a file. If there is a problem with my file format, I would expect it to give an error message about that.Steps to Reproduce
See details above.
Your environment
Chisel Version: 3.5.1
OS: Linux mint 5.4.0-65-generic Ubuntu x86_64 GNU/Linux
Verilator version: Verilator 4.028 2020-02-06 rev v4.026-92-g890cecc1
External Information
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