From 2379dfa81bd570045cbfc50ffd940bb93be5c81c Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Mon, 15 Jul 2024 21:08:16 +0800 Subject: [PATCH] [rtl] fix width of instruction valid. --- ipemu/src/TestBench.scala | 5 ++--- t1/src/T1.scala | 4 ++-- t1/src/lsu/LSU.scala | 10 +++++----- t1/src/package.scala | 7 ++++++- t1/src/vrf/ChainingCheck.scala | 2 +- t1/src/vrf/VRF.scala | 4 ++-- t1/src/vrf/WriteCheck.scala | 2 +- 7 files changed, 19 insertions(+), 15 deletions(-) diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala index 35ed4fe838..3e61d34136 100644 --- a/ipemu/src/TestBench.scala +++ b/ipemu/src/TestBench.scala @@ -186,7 +186,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends val vrfWriteScoreboard: Seq[Valid[UInt]] = Seq.tabulate(2 * dut.parameter.chainingSize) { _ => RegInit(0.U.asTypeOf(Valid(UInt(16.W))))} vrfWriteScoreboard.foreach(scoreboard => dontTouch(scoreboard)) val instructionValid = - (laneProbes.map(laneProbe => laneProbe.instructionValid) :+ + (laneProbes.map(laneProbe => laneProbe.instructionValid ## laneProbe.instructionValid) :+ lsuProbe.lsuInstructionValid :+ t1Probe.instructionValid).reduce(_ | _) val scoreboardEnq = Mux(t1Probe.instructionIssue, UIntToOH(t1Probe.issueTag), 0.U((2 * dut.parameter.chainingSize).W)) vrfWriteScoreboard.zipWithIndex.foreach { case (scoreboard, tag) => @@ -204,8 +204,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends ).asUInt // always equal to array index scoreboard.bits := scoreboard.bits + PopCount(writeEnq) - val tagTruncation: Int = (1 << log2Ceil(dut.parameter.chainingSize)) - 1 - when(scoreboard.valid && !instructionValid(tag & tagTruncation)){ + when(scoreboard.valid && !instructionValid(tag)){ printf(cf"""{"event":"VrfScoreboardReport","count":${scoreboard.bits},"issue_idx":${tag},"cycle":${simulationTime}}\n""") scoreboard.valid := false.B } diff --git a/t1/src/T1.scala b/t1/src/T1.scala index 3edd658787..b3b7ff3779 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -278,7 +278,7 @@ class T1Probe(param: T1Parameter) extends Bundle { val writeQueueEnq: ValidIO[UInt] = Valid(UInt(param.instructionIndexBits.W)) val writeQueueEnqMask: UInt = UInt((param.datapathWidth / 8).W) // mask unit instruction valid - val instructionValid: UInt = UInt(param.chainingSize.W) + val instructionValid: UInt = UInt((param.chainingSize * 2).W) // instruction index for check rd val responseCounter: UInt = UInt(param.instructionIndexBits.W) } @@ -1701,7 +1701,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa probeWire.writeQueueEnqMask := maskUnitWrite.bits.mask probeWire.instructionValid := maskAnd( !slots.last.state.sMaskUnitExecution && !slots.last.state.idle, - indexToOH(slots.last.record.instructionIndex, parameter.chainingSize)).asUInt + indexToOH(slots.last.record.instructionIndex, parameter.chainingSize * 2)).asUInt probeWire.responseCounter := responseCounter diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala index fdd8c5864f..3fa7a7ae92 100644 --- a/t1/src/lsu/LSU.scala +++ b/t1/src/lsu/LSU.scala @@ -97,7 +97,7 @@ class LSUProbe(param: LSUParameter) extends Bundle { val storeUnitProbe = new MemoryWriteProbe(param.mshrParam) val otherUnitProbe = new MemoryWriteProbe(param.mshrParam) val reqEnq: UInt = UInt(param.lsuMSHRSize.W) - val lsuInstructionValid: UInt = UInt(param.chainingSize.W) + val lsuInstructionValid: UInt = UInt((param.chainingSize * 2).W) } /** Load Store Unit @@ -292,9 +292,9 @@ class LSU(param: LSUParameter) extends Module { probeWire.lsuInstructionValid := // The load unit becomes idle when it writes vrf for the last time. maskAnd(!loadUnit.status.idle || VecInit(loadUnit.vrfWritePort.map(_.valid)).asUInt.orR, - indexToOH(loadUnit.status.instructionIndex, param.chainingSize)).asUInt | - maskAnd(!storeUnit.status.idle, indexToOH(storeUnit.status.instructionIndex, param.chainingSize)).asUInt | - maskAnd(!otherUnit.status.idle, indexToOH(otherUnit.status.instructionIndex, param.chainingSize)).asUInt + indexToOH(loadUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt | + maskAnd(!storeUnit.status.idle, indexToOH(storeUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt | + maskAnd(!otherUnit.status.idle, indexToOH(otherUnit.status.instructionIndex, 2 * param.chainingSize)).asUInt vrfWritePort.zip(writeQueueVec).foreach { case (p, q) => p.valid := q.io.deq.valid @@ -435,7 +435,7 @@ class LSU(param: LSUParameter) extends Module { loadUnit.writeReadyForLsu := writeReadyForLsu storeUnit.vrfReadyToStore := vrfReadyToStore - val unitOrder: Bool = instIndexL(loadUnit.status.instructionIndex, storeUnit.status.instructionIndex) + val unitOrder: Bool = instIndexLE(loadUnit.status.instructionIndex, storeUnit.status.instructionIndex) val storeStartLargerThanLoadStart: Bool = loadUnit.status.startAddress <= storeUnit.status.startAddress val storeStartLessThanLoadEnd: Bool = storeUnit.status.startAddress <= loadUnit.status.endAddress val storeEndLargerThanLoadStart: Bool = loadUnit.status.startAddress <= storeUnit.status.endAddress diff --git a/t1/src/package.scala b/t1/src/package.scala index c5ee29c6ee..637bca8ce1 100644 --- a/t1/src/package.scala +++ b/t1/src/package.scala @@ -24,7 +24,12 @@ package object rtl { def instIndexL(a: UInt, b: UInt): Bool = { require(a.getWidth == b.getWidth) - a === b || ((a(a.getWidth - 2, 0) < b(b.getWidth - 2, 0)) ^ a(a.getWidth - 1) ^ b(b.getWidth - 1)) + (a(a.getWidth - 2, 0) < b(b.getWidth - 2, 0)) ^ a(a.getWidth - 1) ^ b(b.getWidth - 1) + } + + def instIndexLE(a: UInt, b: UInt): Bool = { + require(a.getWidth == b.getWidth) + a === b || instIndexL(a, b) } def ffo(input: UInt): UInt = { diff --git a/t1/src/vrf/ChainingCheck.scala b/t1/src/vrf/ChainingCheck.scala index 92a9bf29e4..f90f9b87d6 100644 --- a/t1/src/vrf/ChainingCheck.scala +++ b/t1/src/vrf/ChainingCheck.scala @@ -27,7 +27,7 @@ class ChainingCheck(val parameter: VRFParam) extends Module { val checkResult: Bool = IO(Output(Bool())) // 先看新老 - val older: Bool = instIndexL(read.instructionIndex, record.bits.instIndex) + val older: Bool = instIndexLE(read.instructionIndex, record.bits.instIndex) val sameInst: Bool = read.instructionIndex === record.bits.instIndex // 3: 8 register diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala index 6808c013e2..0032a8b563 100644 --- a/t1/src/vrf/VRF.scala +++ b/t1/src/vrf/VRF.scala @@ -8,7 +8,7 @@ import chisel3.experimental.hierarchy.{Instantiate, instantiable, public} import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import chisel3.probe.{Probe, ProbeValue, define} import chisel3.util._ -import org.chipsalliance.t1.rtl.{LSUWriteCheck, VRFReadPipe, VRFReadRequest, VRFWriteReport, VRFWriteRequest, ffo, instIndexL, ohCheck} +import org.chipsalliance.t1.rtl.{LSUWriteCheck, VRFReadPipe, VRFReadRequest, VRFWriteReport, VRFWriteRequest, ffo, instIndexL, instIndexLE, ohCheck} sealed trait RamType object RamType { @@ -512,7 +512,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar ((sinkRecord.bits.vd.bits === sourceRecord.bits.vs1.bits) && sourceRecord.bits.vs1.valid) ) // source更新 - val older = instIndexL(sinkRecord.bits.instIndex, sourceRecord.bits.instIndex) + val older = instIndexLE(sinkRecord.bits.instIndex, sourceRecord.bits.instIndex) val hazardForeLoad = Mux(older, isLoad.head && isSlow.last, isLoad.last && isSlow.head) && ( // waw samVd || diff --git a/t1/src/vrf/WriteCheck.scala b/t1/src/vrf/WriteCheck.scala index cd2306139f..9b22b7c142 100644 --- a/t1/src/vrf/WriteCheck.scala +++ b/t1/src/vrf/WriteCheck.scala @@ -25,7 +25,7 @@ class WriteCheck(val parameter: VRFParam) extends Module { val checkResult: Bool = IO(Output(Bool())) // 先看新老 - val older: Bool = instIndexL(check.instructionIndex, record.bits.instIndex) + val older: Bool = instIndexLE(check.instructionIndex, record.bits.instIndex) val sameInst: Bool = check.instructionIndex === record.bits.instIndex val checkOH: UInt = UIntToOH((check.vd ## check.offset)(parameter.vrfOffsetBits + 3 - 1, 0))