From 2eace1c2c8ee217726602d72bcc3e8ebc3261e53 Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Tue, 20 Aug 2024 00:08:03 +0800 Subject: [PATCH] [t1rocket] remove rd check because of the repeatition with regwrite --- t1rocketemu/offline/src/difftest.rs | 4 -- t1rocketemu/offline/src/json_events.rs | 62 +++++++-------------- t1rocketemu/spike_rs/src/spike_event.rs | 30 +++------- t1rocketemu/src/TestBench.scala | 7 --- t1rocketemu/test_common/src/spike_runner.rs | 6 +- 5 files changed, 29 insertions(+), 80 deletions(-) diff --git a/t1rocketemu/offline/src/difftest.rs b/t1rocketemu/offline/src/difftest.rs index 23b7facf88..65137ee91a 100644 --- a/t1rocketemu/offline/src/difftest.rs +++ b/t1rocketemu/offline/src/difftest.rs @@ -78,10 +78,6 @@ impl Difftest { cycle: *cycle, }) } - JsonEvents::CheckRd { data, issue_idx, cycle } => { - self.runner.cycle = *cycle; - self.runner.check_rd(&CheckRdEvent { data: *data, issue_idx: *issue_idx, cycle: *cycle }) - } JsonEvents::VrfScoreboard { count, issue_idx, cycle } => { self.runner.cycle = *cycle; self.runner.vrf_scoreboard(&VrfScoreboardEvent { diff --git a/t1rocketemu/offline/src/json_events.rs b/t1rocketemu/offline/src/json_events.rs index d3cfc1adac..2f2487b293 100644 --- a/t1rocketemu/offline/src/json_events.rs +++ b/t1rocketemu/offline/src/json_events.rs @@ -90,12 +90,6 @@ pub(crate) enum JsonEvents { address: u32, cycle: u64, }, - CheckRd { - #[serde(deserialize_with = "str_to_u32", default)] - data: u32, - issue_idx: u8, - cycle: u64, - }, VrfScoreboard { count: u32, issue_idx: u8, @@ -143,12 +137,6 @@ pub struct VrfScoreboardEvent { pub cycle: u64, } -pub struct CheckRdEvent { - pub data: u32, - pub issue_idx: u8, - pub cycle: u64, -} - pub(crate) trait JsonEventRunner { fn peek_reg_write(&mut self, reg_write: &RegWriteEvent) -> anyhow::Result<()>; @@ -164,8 +152,6 @@ pub(crate) trait JsonEventRunner { fn check_and_clear_fence(&mut self); - fn check_rd(&mut self, check_rd: &CheckRdEvent) -> anyhow::Result<()>; - fn retire(&mut self, cycle: u64, issue_idx: u8) -> anyhow::Result<()>; } @@ -175,17 +161,27 @@ impl JsonEventRunner for SpikeRunner { let idx = reg_write.idx; let data = reg_write.data; - let se = self.find_rf_se(); + let se = self.find_reg_write_se(); info!( - "[{cycle}] RegWrite: rtl idx={idx}, data={data:08x}; se idx={}, data={:08x} ({})", + "[{cycle}] RegWrite: rtl idx={idx}, data={data:#08x}; se idx={}, data={:#08x} ({})", se.rd_idx, se.rd_bits, se.describe_insn() ); - assert!(idx as u32 == se.rd_idx, "rtl idx({:#x}) should be equal to spike idx({:#x})", idx, se.rd_idx); - assert!(data == se.rd_bits, "rtl data({:#x}) should be equal to spike data({:#x})", data, se.rd_bits); + assert!( + idx as u32 == se.rd_idx, + "rtl idx({:#x}) should be equal to spike idx({:#x})", + idx, + se.rd_idx + ); + assert!( + data == se.rd_bits, + "rtl data({:#x}) should be equal to spike data({:#x})", + data, + se.rd_bits + ); Ok(()) } @@ -274,7 +270,7 @@ impl JsonEventRunner for SpikeRunner { assert_eq!( record.byte, written_byte, - "[{}] {offset}th byte incorrect ({:02x} record != {written_byte:02x} written) \ + "[{}] {offset}th byte incorrect ({:#02x} record != {written_byte:#02x} written) \ for vrf write (lane={}, vd={}, offset={}, mask={}, data={:x?}) \ issue_idx={} [vrf_idx={}] (disasm: {}, pc: {:#x}, bits: {:#x})", vrf_write.cycle, @@ -328,7 +324,7 @@ impl JsonEventRunner for SpikeRunner { let lsu_idx = memory_write.lsu_idx; if let Some(se) = self.commit_queue.iter_mut().find(|se| se.lsu_idx == lsu_idx) { - info!("[{cycle}] MemoryWrite: address={base_addr:08x}, size={}, data={data:x?}, mask={}, pc = {:#x}, disasm = {}", data.len(), mask_display(&mask), se.pc, se.disasm); + info!("[{cycle}] MemoryWrite: address={base_addr:#08x}, size={}, data={data:x?}, mask={}, pc = {:#x}, disasm = {}", data.len(), mask_display(&mask), se.pc, se.disasm); // compare with spike event record mask.iter().enumerate() .filter(|(_, &mask)| mask) @@ -337,11 +333,11 @@ impl JsonEventRunner for SpikeRunner { let data_byte = *data.get(offset).unwrap_or(&0); let mem_write = se.mem_access_record.all_writes.get_mut(&byte_addr).unwrap_or_else(|| { - panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:08x}") + panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:#08x}") }); let single_mem_write_val = mem_write.writes[mem_write.num_completed_writes].val; mem_write.num_completed_writes += 1; - assert_eq!(single_mem_write_val, data_byte, "[{cycle}] expect mem write of byte {single_mem_write_val:02X}, actual byte {data_byte:02X} (byte_addr={byte_addr:08X}, pc = {:#x}, disasm = {})", se.pc, se.disasm); + assert_eq!(single_mem_write_val, data_byte, "[{cycle}] expect mem write of byte {single_mem_write_val:#02x}, actual byte {data_byte:#02x} (byte_addr={byte_addr:#08x}, pc = {:#x}, disasm = {})", se.pc, se.disasm); }); return Ok(()); } @@ -363,8 +359,7 @@ impl JsonEventRunner for SpikeRunner { se.vrf_access_record.retired_writes, se.describe_insn() ); - // if instruction writes rd, it will retire in check_rd() - if count == se.vrf_access_record.retired_writes && !se.is_rd_written { + if count == se.vrf_access_record.retired_writes { should_retire = Some(issue_idx); } // if all writes are committed, retire the se @@ -397,25 +392,6 @@ impl JsonEventRunner for SpikeRunner { } } - fn check_rd(&mut self, check_rd: &CheckRdEvent) -> anyhow::Result<()> { - let data = check_rd.data; - let cycle = check_rd.cycle; - let issue_idx = check_rd.issue_idx; - - let se = - self.commit_queue.iter_mut().find(|se| se.issue_idx == issue_idx).unwrap_or_else(|| { - panic!("[{cycle}] cannot find se with instruction issue_idx={issue_idx}") - }); - - info!("[{cycle}] CheckRd: issue_idx={issue_idx}, data={data:x?}"); - - se.check_rd(data).expect("Failed to check_rd"); - - self.retire(cycle, issue_idx).unwrap(); - - Ok(()) - } - fn retire(&mut self, cycle: u64, issue_idx: u8) -> anyhow::Result<()> { if let Some(idx) = self.commit_queue.iter().position(|se| se.issue_idx == issue_idx) { if let Some(se) = self.commit_queue.remove(idx) { diff --git a/t1rocketemu/spike_rs/src/spike_event.rs b/t1rocketemu/spike_rs/src/spike_event.rs index 6df387d74a..1b9c8e9450 100644 --- a/t1rocketemu/spike_rs/src/spike_event.rs +++ b/t1rocketemu/spike_rs/src/spike_event.rs @@ -325,18 +325,15 @@ impl SpikeEvent { pub fn pre_log_arch_changes(&mut self, spike: &Spike, vlen: u32) -> anyhow::Result<()> { if self.do_log_vrf { - self.rd_bits = spike.get_proc().get_rd(); - // record the vrf writes before executing the insn - let vlen_in_bytes = vlen; - let proc = spike.get_proc(); - let (start, len) = self.get_vrf_write_range(vlen_in_bytes).unwrap(); + self.rd_bits = proc.get_state().get_reg(self.rd_idx, false); + let (start, len) = self.get_vrf_write_range(vlen).unwrap(); self.vd_write_record.vd_bytes.resize(len as usize, 0u8); for i in 0..len { let offset = start + i; - let vreg_index = offset / vlen_in_bytes; - let vreg_offset = offset % vlen_in_bytes; + let vreg_index = offset / vlen; + let vreg_offset = offset % vlen; let cur_byte = proc.get_vreg_data(vreg_index, vreg_offset); self.vd_write_record.vd_bytes[i as usize] = cur_byte; } @@ -412,7 +409,7 @@ impl SpikeEvent { self.is_rd_written = true; self.rd_bits = data; trace!( - "ScalarRFChange: idx={:02x}, data={:08x}", + "ScalarRFChange: idx={:#02x}, data={:08x}", self.rd_idx, self.rd_bits ); @@ -424,13 +421,13 @@ impl SpikeEvent { self.is_rd_written = true; self.rd_bits = data; trace!( - "FloatRFChange: idx={:02x}, data={:08x}", + "FloatRFChange: idx={:#02x}, data={:08x}", self.rd_idx, self.rd_bits ); } _ => trace!( - "UnknownRegChange, idx={:02x}, spike detect unknown reg change", + "UnknownRegChange, idx={:#02x}, spike detect unknown reg change", self.rd_idx ), } @@ -494,19 +491,6 @@ impl SpikeEvent { Ok(()) } - pub fn check_rd(&self, data: u32) -> anyhow::Result<()> { - // TODO: rtl should indicate whether resp_bits_data is valid - if self.is_rd_written { - assert_eq!( - data, self.rd_bits, - "expect to write rd[{}] = {}, actual {}", - self.rd_idx, self.rd_bits, data - ); - } - - Ok(()) - } - pub fn check_is_ready_for_commit(&self, cycle: u64) -> anyhow::Result<()> { for (addr, record) in &self.mem_access_record.all_writes { assert_eq!( diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala index c4bda1add1..946846a95e 100644 --- a/t1rocketemu/src/TestBench.scala +++ b/t1rocketemu/src/TestBench.scala @@ -249,13 +249,6 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil printf(cf"""{"event":"Issue","idx":${t1Probe.issue.bits},"cycle":${simulationTime}}\n""") ) - // t1 retire - when(t1Probe.retire.valid)( - printf( - cf"""{"event":"CheckRd","data":"${t1Probe.retire.bits}%x","issue_idx":${t1Probe.responseCounter},"cycle":${simulationTime}}\n""" - ) - ) - // t1 lsu enq when(t1Probe.lsuProbe.reqEnq.orR)( printf(cf"""{"event":"LsuEnq","enq":${t1Probe.lsuProbe.reqEnq},"cycle":${simulationTime}}\n""") diff --git a/t1rocketemu/test_common/src/spike_runner.rs b/t1rocketemu/test_common/src/spike_runner.rs index 2afcc96824..d3f9a031c3 100644 --- a/t1rocketemu/test_common/src/spike_runner.rs +++ b/t1rocketemu/test_common/src/spike_runner.rs @@ -128,7 +128,7 @@ impl SpikeRunner { event } - pub fn find_rf_se(&mut self) -> SpikeEvent { + pub fn find_reg_write_se(&mut self) -> SpikeEvent { if !self.scalar_queue.is_empty() { // return the back (oldest) scalar insn self.scalar_queue.pop_back().unwrap() @@ -136,7 +136,7 @@ impl SpikeRunner { // else, loop until find a se, and push the se to the front loop { let se = self.spike_step(); - if se.is_scalar() && se.is_rd_written && se.rd_idx != 0 { + if se.is_rd_written && se.rd_idx != 0 { return se; } else if se.is_v() { self.vector_queue.push_front(se.clone()); @@ -153,7 +153,7 @@ impl SpikeRunner { // else, loop until find a se, and push the se to the front loop { let se = self.spike_step(); - if se.is_scalar() && se.is_rd_written && se.rd_idx != 0 { + if se.is_rd_written && se.rd_idx != 0 { self.scalar_queue.push_front(se.clone()); } else if se.is_v() { return se;