diff --git a/rocket/src/AbstractT1.scala b/rocket/src/AbstractT1.scala
index 0e6bfe62b..cce56c90d 100644
--- a/rocket/src/AbstractT1.scala
+++ b/rocket/src/AbstractT1.scala
@@ -1,6 +1,7 @@
 package org.chipsalliance.t1.rockettile
 
 import chisel3._
+import chisel3.properties.{ClassType, Path, Property}
 import chisel3.util._
 import chisel3.util.experimental.BitSet
 import freechips.rocketchip.diplomacy._
@@ -152,6 +153,9 @@ abstract class AbstractLazyT1()(implicit p: Parameters) extends LazyModule {
     BundleBridgeSource(() => Valid(new VectorResponse(xLen)))
   val hazardControlNode: BundleBridgeSource[VectorHazardControl] =
     BundleBridgeSource(() => Output(new VectorHazardControl))
+  val t1OM = ClassType.unsafeGetClassTypeByName("T1OM")
+  // Diplomacy is dirty and doesn't support Property yet, this is a dirty hack and will be bore from top
+  val om = InModuleBody{ IO(Output(Property[t1OM.Type]())).suggestName("T1OM") }
 }
 
 /** This is a vector interface comply to chipsalliance/t1 project.
@@ -162,6 +166,7 @@ abstract class AbstractLazyT1ModuleImp(val outer: AbstractLazyT1)(implicit p: Pa
   val csr:           CSRInterface = outer.csrSinkNode.bundle
   val response:      ValidIO[VectorResponse] = outer.responseNode.bundle
   val hazardControl: VectorHazardControl = outer.hazardControlNode.bundle
+  val om:            Property[ClassType] = outer.om
 }
 
 trait HasLazyT1 { this: BaseTile =>
diff --git a/subsystem/src/LazyT1.scala b/subsystem/src/LazyT1.scala
index fe4f7c838..06bcc2543 100644
--- a/subsystem/src/LazyT1.scala
+++ b/subsystem/src/LazyT1.scala
@@ -5,6 +5,7 @@ package org.chipsalliance.t1.subsystem
 
 import chisel3._
 import chisel3.experimental.SerializableModuleGenerator
+import chisel3.properties.{ClassType, Path, Property}
 import freechips.rocketchip.diplomacy.AddressSet
 import freechips.rocketchip.subsystem.{BaseSubsystem, InstantiatesHierarchicalElements}
 import org.chipsalliance.cde.config._
@@ -12,9 +13,6 @@ import org.chipsalliance.t1.rockettile.{AbstractLazyT1, AbstractLazyT1ModuleImp,
 import org.chipsalliance.t1.rtl.{T1, T1Parameter}
 
 case object T1Generator extends Field[SerializableModuleGenerator[T1, T1Parameter]]
-trait HasT1Tiles { this: BaseSubsystem with InstantiatesHierarchicalElements =>
-  lazy val t1Tiles = totalTiles.values.collect { case r: org.chipsalliance.t1.rocketcore.T1Tile => r }
-}
 
 class LazyT1()(implicit p: Parameters) extends AbstractLazyT1 {
   lazy val module = new LazyT1Imp(this)
@@ -81,4 +79,6 @@ class LazyT1Imp(outer: LazyT1)(implicit p: Parameters) extends AbstractLazyT1Mod
       bundle.d.ready := t1.memoryPorts(i).d.ready
 
   }
+
+  om := t1.t1OMOutput
 }
diff --git a/subsystem/src/Subsystem.scala b/subsystem/src/Subsystem.scala
index 66cf852dc..b28913303 100644
--- a/subsystem/src/Subsystem.scala
+++ b/subsystem/src/Subsystem.scala
@@ -4,7 +4,10 @@
 package org.chipsalliance.t1.subsystem
 
 import chisel3._
+import chisel3.experimental.hierarchy.{Instance, Instantiate, instantiable, public}
+import chisel3.experimental.hierarchy.core.Definition
 import chisel3.experimental.{SerializableModuleGenerator, UnlocatableSourceInfo}
+import chisel3.properties.Class.ClassDefinitionOps
 import chisel3.util.experimental.BitSet
 import chisel3.util.{BitPat, Counter}
 import freechips.rocketchip.devices.debug.DebugModuleKey
@@ -17,9 +20,23 @@ import freechips.rocketchip.tile.{FPUParams, MaxHartIdBits, XLen}
 import freechips.rocketchip.tilelink.{BroadcastFilter, HasTLBusParams, TLBusWrapper, TLBusWrapperConnection, TLBusWrapperInstantiationLike, TLBusWrapperTopology, TLEdge, TLFIFOFixer, TLFragmenter, TLInwardNode, TLManagerNode, TLOutwardNode, TLSlaveParameters, TLSlavePortParameters, TLWidthWidget, TLXbar}
 import freechips.rocketchip.util.Location
 import org.chipsalliance.cde.config._
-import org.chipsalliance.t1.rocketcore.{T1CrossingParams, T1TileAttachParams, T1TileParams}
+import org.chipsalliance.t1.rocketcore.{T1CrossingParams, T1Tile, T1TileAttachParams, T1TileParams}
 import org.chipsalliance.t1.rockettile.BuildT1
-import org.chipsalliance.t1.rtl.{T1, T1Parameter}
+import org.chipsalliance.t1.rtl.{T1, T1OM, T1Parameter}
+import chisel3.properties.{Class, ClassType, Path, Property}
+import chisel3.util.experimental.BoringUtils.bore
+
+
+/** The top OM we need to read. */
+@instantiable
+class T1SubsystemOM extends Class {
+  val t1OM = ClassType.unsafeGetClassTypeByName("T1OM")
+  val t1 = IO(Output(Property[t1OM.Type]()))
+  @public
+  val t1In = IO(Input(Property[t1OM.Type]()))
+  t1 := t1In
+  // TODO: add memory ranges, scalar core info, here.
+}
 
 // The Subsystem that T1 lives in.
 case object T1Subsystem extends HierarchicalLocation("T1Subsystem")
@@ -423,6 +440,11 @@ class T1Subsystem(implicit p: Parameters)
   }.unzip
 
   // IOs
+  val t1OM = InModuleBody {
+    val t1SubsystemOM: Instance[T1SubsystemOM] = Instantiate(new T1SubsystemOM)
+    // bore T1OM at here.
+    t1SubsystemOM.t1In := bore(totalTiles.head._2.asInstanceOf[T1Tile].t1.map(_.om).get)
+  }
   val scalarPort = InModuleBody { scalarMemoryNode.makeIOs() }
   val mmioPort = InModuleBody { mmioNode.makeIOs() }
   val vectorPorts = InModuleBody {
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
index af63a81b5..df933d791 100644
--- a/t1/src/Lane.scala
+++ b/t1/src/Lane.scala
@@ -7,12 +7,22 @@ import chisel3._
 import chisel3.experimental.hierarchy.{Instance, Instantiate, instantiable, public}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.probe.{Probe, ProbeValue, define}
+import chisel3.properties.{ClassType, Path, Property, Class}
 import chisel3.util._
 import chisel3.util.experimental.decode.DecodeBundle
 import org.chipsalliance.t1.rtl.decoder.Decoder
 import org.chipsalliance.t1.rtl.lane._
 import org.chipsalliance.t1.rtl.vrf.{RamType, VRF, VRFParam, VRFProbe}
 
+@instantiable
+class T1LaneOM extends Class {
+  @public
+  val retime = IO(Output(Property[Seq[Path]]()))
+  @public
+  val retimeIn = IO(Input(Property[Seq[Path]]()))
+  retime := retimeIn
+}
+
 class LaneSlotProbe extends Bundle {
   val stage0EnqueueReady: Bool = Bool()
   val stage0EnqueueValid: Bool = Bool()
@@ -159,6 +169,10 @@ case class LaneParameter(
   */
 @instantiable
 class Lane(val parameter: LaneParameter) extends Module with SerializableModule[LaneParameter] {
+  val laneOM: Instance[T1LaneOM] = Instantiate(new T1LaneOM)
+  val laneOMClassType: ClassType = laneOM.toDefinition.getClassType
+  val laneOMOutput: Property[ClassType] = IO(Output(Property[laneOMClassType.Type]()))
+  laneOMOutput := laneOM.getPropertyReference
 
   /** laneIndex is a IO constant for D/I and physical implementations. */
   @public
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
index e9a57e1f6..eb1e61ee2 100644
--- a/t1/src/T1.scala
+++ b/t1/src/T1.scala
@@ -15,6 +15,21 @@ import org.chipsalliance.t1.rtl.decoder.Decoder
 import org.chipsalliance.t1.rtl.lsu.{LSU, LSUParameter, LSUProbe}
 import org.chipsalliance.t1.rtl.vrf.{RamType, VRFParam, VRFProbe}
 
+// TODO: this should be a object model. There should 3 object model here:
+//       1. T1SubsystemOM(T1(OM), MemoryRegion, Cache configuration)
+//       2. T1(Lane(OM), VLEN, DLEN, uarch parameters, customer IDs(for floorplan);)
+//       3. Lane(Retime, VRF memory type, id, multiple instances(does it affect dedup? not for sure))
+@instantiable
+class T1OM(p: T1Parameter) extends Class {
+  val T1LaneOM: ClassType = ClassType.unsafeGetClassTypeByName("T1LaneOM")
+
+  @public
+  val laneOMs: Seq[Property[ClassType]] = Seq.tabulate(p.laneNumber)(i => IO(Output(Property[T1LaneOM.Type]())).suggestName(s"lane${i}OM"))
+  @public
+  val laneOMsIn: Seq[Property[ClassType]] = Seq.tabulate(p.laneNumber)(i => IO(Input(Property[T1LaneOM.Type]())).suggestName(s"lane${i}OMIn"))
+  laneOMs.zip(laneOMsIn).foreach{case (o, i) => o := i}
+}
+
 object T1Parameter {
   implicit def bitSetP:upickle.default.ReadWriter[BitSet] = upickle.default.readwriter[String].bimap[BitSet](
     bs => bs.terms.map("b" + _.rawString).mkString("\n"),
@@ -244,6 +259,11 @@ class T1Probe(param: T1Parameter) extends Bundle {
   * The logic of [[T1]] contains the Vector Sequencer and Mask Unit.
   */
 class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Parameter] {
+  val t1OM: Instance[T1OM] = Instantiate(new T1OM(parameter))
+  val laneOMsIn: Seq[Property[ClassType]] = t1OM.laneOMsIn
+  val t1OMClassType: ClassType = t1OM.toDefinition.getClassType
+  val t1OMOutput: Property[ClassType] = IO(Output(Property[t1OMClassType.Type]()))
+  t1OMOutput := t1OM.getPropertyReference
 
   /** request from CPU.
     * because the interrupt and exception of previous instruction is unpredictable,