From 69ad66fdc4957b4433383f51b5ba3905d8caa517 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Thu, 26 Dec 2024 11:43:56 +0800 Subject: [PATCH] [rtl] The commit of the load instruction needs to wait for the confirmation of the lane. --- t1/src/T1.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/t1/src/T1.scala b/t1/src/T1.scala index 5d06b4c53..2320fa37c 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -486,7 +486,7 @@ class T1(val parameter: T1Parameter) val readOnlyInstruction: Bool = decodeResult(Decoder.readOnly) // 只进mask unit的指令 val maskUnitInstruction: Bool = (decodeResult(Decoder.slid) || decodeResult(Decoder.mv)) - val skipLastFromLane: Bool = isLoadStoreType || maskUnitInstruction || readOnlyInstruction + val skipLastFromLane: Bool = isStoreType || maskUnitInstruction || readOnlyInstruction val instructionValid: Bool = requestReg.bits.issue.vl > requestReg.bits.issue.vstart // TODO: these should be decoding results