From 889f7b1920754241f7e918d166616f282ba61aa8 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Thu, 12 Dec 2024 15:25:03 +0800 Subject: [PATCH] [rtl] fix logic. --- t1/src/LaneLogic.scala | 2 +- t1/src/MaskedLogic.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/t1/src/LaneLogic.scala b/t1/src/LaneLogic.scala index a34641997..f4adc7b39 100644 --- a/t1/src/LaneLogic.scala +++ b/t1/src/LaneLogic.scala @@ -46,7 +46,7 @@ class LaneLogic(val parameter: LaneLogicParameter) resp := VecInit(req.src.map(_.asBools).transpose.map { case Seq(sr0, sr1) => chisel3.util.experimental.decode.decoder .qmc( - req.opcode ## (sr0 ## (req.opcode(2) ^ sr1)), + req.opcode(1, 0) ## (sr0 ## (req.opcode(2) ^ sr1)), TruthTable(TableGenerator.LogicTable.table, BitPat.dontCare(1)) ) ^ req.opcode(3) diff --git a/t1/src/MaskedLogic.scala b/t1/src/MaskedLogic.scala index 08008e3eb..3465bb51d 100644 --- a/t1/src/MaskedLogic.scala +++ b/t1/src/MaskedLogic.scala @@ -55,7 +55,7 @@ class MaskedLogic(val parameter: LogicParam) extends VFUModule with Serializable sr3, chisel3.util.experimental.decode.decoder .qmc( - request.opcode ## ((request.opcode(2) ^ sr0) ## sr1), + request.opcode(1, 0) ## ((request.opcode(2) ^ sr0) ## sr1), TruthTable(TableGenerator.LogicTable.table, BitPat.dontCare(1)) ) ^ request.opcode(3), sr2