diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
index 1b614cd8a..b46ca9c35 100644
--- a/t1/src/mask/MaskUnit.scala
+++ b/t1/src/mask/MaskUnit.scala
@@ -788,7 +788,7 @@ class MaskUnit(val parameter: T1Parameter)
       val tokenSize         = log2Ceil(reorderQueueSize + 1)
       val counter           = RegInit(0.U(tokenSize.W))
       val counterWillUpdate = RegInit(0.U(tokenSize.W))
-      val release           = reorderQueueVec(i).deq.fire
+      val release           = reorderQueueVec(i).deq.fire && readType
       val allocate          = Mux(readIssueStageEnq, accessCountEnq(i), 0.U)
       val counterUpdate     = counter + allocate - release
       when(release || readIssueStageEnq) {