diff --git a/.github/cases/blastoise/default.json b/.github/cases/blastoise/default.json index 87427cde3..5a0093182 100644 --- a/.github/cases/blastoise/default.json +++ b/.github/cases/blastoise/default.json @@ -1,502 +1,502 @@ { - "mlir.rvv_vp_intrinsic_add": 311, - "mlir.rvv_vp_intrinsic_add_scalable": 476, - "mlir.hello": 77, - "mlir.stripmining": 21839, - "asm.mmm": 70399, - "asm.smoke": 5319, - "intrinsic.conv2d_less_m2": 1456, - "intrinsic.linear_normalization": 2938, - "intrinsic.softmax": 8381, - "codegen.vaadd_vv": 484202, - "codegen.vaadd_vx": 670241, - "codegen.vaaddu_vv": 484202, - "codegen.vaaddu_vx": 670241, - "codegen.vadc_vim": 74259, - "codegen.vadc_vvm": 60600, - "codegen.vadc_vxm": 81283, - "codegen.vadd_vi": 151179, - "codegen.vadd_vv": 121068, - "codegen.vadd_vx": 167576, - "codegen.vand_vi": 151183, - "codegen.vand_vv": 121068, - "codegen.vand_vx": 167575, - "codegen.vasub_vv": 484202, - "codegen.vasub_vx": 670241, - "codegen.vasubu_vv": 484202, - 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"codegen.vsuxseg7ei8_v": 206891, + "codegen.vsuxseg8ei16_v": 157669, + "codegen.vsuxseg8ei32_v": 84787, + "codegen.vsuxseg8ei8_v": 222199, + "codegen.vwadd_vv": 170703, + "codegen.vwadd_vx": 417405, + "codegen.vwadd_wv": 179332, + "codegen.vwadd_wx": 420859, + "codegen.vwaddu_vv": 170703, + "codegen.vwaddu_vx": 417405, + "codegen.vwaddu_wv": 179332, + "codegen.vwaddu_wx": 420859, + "codegen.vwmacc_vv": 170991, + "codegen.vwmacc_vx": 418422, + "codegen.vwmaccsu_vv": 170991, + "codegen.vwmaccsu_vx": 418422, + "codegen.vwmaccu_vv": 170991, + "codegen.vwmaccu_vx": 418422, + "codegen.vwmaccus_vx": 418422, + "codegen.vwmul_vv": 170823, + "codegen.vwmul_vx": 539885, + "codegen.vwmulsu_vv": 170823, + "codegen.vwmulsu_vx": 539885, + "codegen.vwmulu_vv": 170823, + "codegen.vwmulu_vx": 539885, + "codegen.vwredsum_vs": 165878, + "codegen.vwredsumu_vs": 165878, + "codegen.vwsub_vv": 170703, + "codegen.vwsub_vx": 417405, + "codegen.vwsub_wv": 179332, + "codegen.vwsub_wx": 420859, + "codegen.vwsubu_vv": 170703, + "codegen.vwsubu_vx": 417405, + "codegen.vwsubu_wv": 179332, + "codegen.vwsubu_wx": 420859, + "codegen.vxor_vi": 524606, + "codegen.vxor_vv": 309304, + "codegen.vxor_vx": 668246, + "codegen.vzext_vf2": 230080, + "codegen.vzext_vf4": 46736 } \ No newline at end of file diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala index 9d65fae1b..69b67cf71 100644 --- a/t1/src/Bundles.scala +++ b/t1/src/Bundles.scala @@ -692,3 +692,13 @@ class VFUResponseToSlot(parameter: LaneParameter) extends Bundle { } final class EmptyBundle extends Bundle + + +class VRFReadPipe(size: BigInt) extends Bundle { + val address: UInt = UInt(log2Ceil(size).W) +} + +class DataPipeInReadStage(dataWidth: Int, arbitrate: Boolean) extends Bundle { + val data: UInt = UInt(dataWidth.W) + val choose: Option[Bool] = Option.when(arbitrate)(Bool()) +} diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala index e3d70bd65..af63a81b5 100644 --- a/t1/src/Lane.scala +++ b/t1/src/Lane.scala @@ -1045,7 +1045,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ laneRequest.ready := !slotOccupied.last && vrf.instructionWriteReport.ready val instructionFinishAndNotReportByTop: Bool = - entranceControl.instructionFinished && !laneRequest.bits.decodeResult(Decoder.readOnly) + entranceControl.instructionFinished && !laneRequest.bits.decodeResult(Decoder.readOnly) && (writeCount === 0.U) val needWaitCrossWrite: Bool = laneRequest.bits.decodeResult(Decoder.crossWrite) && csrInterface.vl.orR // normal instruction, LSU instruction will be report to VRF. vrf.instructionWriteReport.valid := laneRequest.bits.issueInst && (!instructionFinishAndNotReportByTop || needWaitCrossWrite) @@ -1113,7 +1113,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ Mux(topWriteQueue.valid, indexToOH(topWriteQueue.bits.instructionIndex, parameter.chainingSize), 0.U) | maskedWriteUnit.maskedWrite1H | dataInPipeQueue instructionFinished := instructionFinishedVec.reduce(_ | _) - crossWriteDataInSlot := crossWriteDataInSlotVec.reduce(_ | _) + crossWriteDataInSlot := crossWriteDataInSlotVec.reduce(_ | _) | dataInPipeQueue | maskedWriteUnit.maskedWrite1H writeReadyForLsu := vrf.writeReadyForLsu vrfReadyToStore := vrf.vrfReadyToStore diff --git a/t1/src/T1.scala b/t1/src/T1.scala index 81e5fa929..e9a57e1f6 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -9,9 +9,7 @@ import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import chisel3.util._ import chisel3.util.experimental.decode._ import tilelink.{TLBundle, TLBundleParameter, TLChannelAParameter, TLChannelDParameter} -import chisel3.probe.Probe -import chisel3.probe.ProbeValue -import chisel3.probe.define +import chisel3.probe.{Probe, ProbeValue, define, force} import chisel3.util.experimental.BitSet import org.chipsalliance.t1.rtl.decoder.Decoder import org.chipsalliance.t1.rtl.lsu.{LSU, LSUParameter, LSUProbe} @@ -181,7 +179,7 @@ case class T1Parameter( val maskWidth: Int = lsuBankParameters.head.beatbyte // todo - val vrfReadLatency = 1 + val vrfReadLatency = 2 // each element: Each lane will be connected to the other two lanes, // and the values are their respective delays. @@ -480,7 +478,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa RegEnable( !requestRegDequeue.fire, false.B, - (RegNext(maskUnitReadReady) && gatherNeedRead) || requestRegDequeue.fire + (RegNext(RegNext(maskUnitReadReady)) && gatherNeedRead) || requestRegDequeue.fire ) val gatherReadDataOffset: UInt = Wire(UInt(5.W)) val gatherData: UInt = Mux(gatherOverlap, 0.U, (WARRedResult.bits >> gatherReadDataOffset).asUInt) @@ -760,7 +758,8 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa val lastExecuteForGroup = writeBackCounter.andR // 计算正写的这个lane是不是在边界上 val endOH = UIntToOH(csrRegForMaskUnit.vl(parameter.dataPathWidthBits - 1, 0)) - val border = lastExecute && dataPathMisaligned && !(decodeResultReg(Decoder.compress)) + val border = lastExecute && dataPathMisaligned && + !(decodeResultReg(Decoder.compress) || decodeResultReg(Decoder.gather)) val lastGroupMask = scanRightOr(endOH(parameter.datapathWidth - 1, 1)) val mvType = decodeResultReg(Decoder.mv) val readMv = mvType && decodeResultReg(Decoder.targetRd) @@ -772,13 +771,17 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa val skipLaneData: Bool = decodeResultReg(Decoder.mv) mixedUnit := writeMv || readMv maskReadLaneSelect.head := UIntToOH(writeBackCounter) + maskReadLaneSelect.head := UIntToOH(writeBackCounter) maskWriteLaneSelect.head := maskReadLaneSelect.head maskUnitReadVec.head.valid := false.B maskUnitReadVec.head.bits.vs := Mux(readMv, vs2, Mux(reduce, vs1, vd)) maskUnitReadVec.head.bits.readSource := Mux(readMv, 1.U, Mux(reduce, 0.U, 2.U)) maskUnitReadVec.head.bits.offset := groupCounter maskUnitRead.bits.instructionIndex := control.record.instructionIndex - val readResultSelectResult = Mux1H(RegNext(maskUnitReadSelect), laneReadResult) + val readResultSelectResult = Mux1H( + Pipe(true.B, maskUnitReadSelect, parameter.vrfReadLatency).bits + , laneReadResult + ) // 把mask选出来 val maskSelect = v0(groupCounter ## writeBackCounter) val fullMask: UInt = (-1.S(parameter.datapathWidth.W)).asUInt @@ -802,8 +805,11 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa maskUnitWriteVec.head.bits.last := control.state.wLast || reduce maskUnitWriteVec.head.bits.instructionIndex := control.record.instructionIndex - val maskUnitReadVrf = maskUnitReadReady && maskUnitReadVec.map(_.valid).reduce(_ || _) - when(RegNext(maskUnitReadVrf)) { + val waitReadResult: Bool = Wire(Bool()) + val maskUnitReadVrf = maskUnitReadReady && maskUnitReadVec.map(_.valid).reduce(_ || _) && !waitReadResult + val readNext = RegNext(maskUnitReadVrf) + waitReadResult := RegNext(readNext) || readNext + when(Pipe(maskUnitReadVrf, false.B, parameter.vrfReadLatency).valid) { WARRedResult.bits := readResultSelectResult WARRedResult.valid := true.B } @@ -993,8 +999,10 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa val skipRead = readOverlap || (gather && compareResult) || extend val maskUnitWriteVecFire1 = maskUnitReadVec(1).valid && maskUnitReadReady val readFireNext1: Bool = RegNext(maskUnitWriteVecFire1) - val gatherTryToRead = gatherNeedRead && !VecInit(lsu.vrfReadDataPorts.map(_.valid)).asUInt.orR - maskUnitReadVec(1).valid := (readState || gatherTryToRead) && !readFireNext1 + val readFireNextNext1: Bool = RegNext(readFireNext1) + val port1WaitForResult: Bool = readFireNext1 || readFireNextNext1 + val gatherTryToRead = gatherNeedRead && !VecInit(lsu.vrfReadDataPorts.map(_.valid)).asUInt.orR && !gatherReadFinish + maskUnitReadVec(1).valid := (readState || gatherTryToRead) && !port1WaitForResult maskUnitReadVec(1).bits.vs := Mux(readState, vs2, requestRegDequeue.bits.instruction(24, 20)) + readGrowth maskUnitReadVec(1).bits.readSource := 1.U maskUnitReadVec(1).bits.offset := readOffset @@ -1044,7 +1052,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa } when(readState) { // 不需要valid,因为这个状态下一定是valid的 - when(readFireNext1) { + when(readFireNextNext1) { slideState := sWrite } } @@ -1080,7 +1088,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa val compressStateWrite = compressState === sWrite1 // compress 用vs1当mask,需要先读vs1 - val readCompressMaskNext = RegNext(maskUnitReadReady && compressStateRead) + val readCompressMaskNext = Pipe(maskUnitReadReady && compressStateRead, false.B, parameter.vrfReadLatency).valid when(readCompressMaskNext) { maskDataForCompress := readResultSelectResult } @@ -1093,6 +1101,8 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa val maskUnitReadFire2: Bool = maskUnitReadVec(2).valid && maskUnitReadReady val readFireNext2 = RegNext(maskUnitReadFire2) + val readFireNextNext2 = RegNext(readFireNext2) + val port2WaitForResult = readFireNextNext2 || readFireNext2 /** 计算需要读的mask的相关 * elementIndexCount -> 11bit @@ -1102,7 +1112,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa * elementIndexCount(9, 8)作为offset */ // compress read - maskUnitReadVec(2).valid := compressStateRead && !readFireNext2 + maskUnitReadVec(2).valid := compressStateRead && !port2WaitForResult maskUnitReadVec(2).bits.vs := vs1 maskUnitReadVec(2).bits.readSource := 0.U maskUnitReadVec(2).bits.offset := elementIndexCount( @@ -1143,7 +1153,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa compressState := firstState } - when(compressStateRead && readFireNext2) { + when(compressStateRead && readFireNextNext2) { compressState := sWrite1 } diff --git a/t1/src/laneStage/LaneStage1.scala b/t1/src/laneStage/LaneStage1.scala index a13c999af..c635e2801 100644 --- a/t1/src/laneStage/LaneStage1.scala +++ b/t1/src/laneStage/LaneStage1.scala @@ -103,9 +103,9 @@ class LaneStage1(parameter: LaneParameter, isLastSlot: Boolean) extends Module { enqueue.ready := allReadQueueReady && pipeQueue.io.enq.ready // request enqueue - readRequestQueueVs1.io.enq.valid := enqueue.valid && allReadQueueReady && state.decodeResult(Decoder.vtype) && !state.skipRead - readRequestQueueVs2.io.enq.valid := enqueue.valid && allReadQueueReady && !state.skipRead - readRequestQueueVd.io.enq.valid := enqueue.valid && allReadQueueReady && !state.decodeResult(Decoder.sReadVD) + readRequestQueueVs1.io.enq.valid := enqueue.fire && state.decodeResult(Decoder.vtype) && !state.skipRead + readRequestQueueVs2.io.enq.valid := enqueue.fire && !state.skipRead + readRequestQueueVd.io.enq.valid := enqueue.fire && !state.decodeResult(Decoder.sReadVD) (readRequestQueueLSB ++ readRequestQueueMSB).foreach { q => q.io.enq.valid := enqueue.valid && allReadQueueReady && state.decodeResult(Decoder.crossRead) } diff --git a/t1/src/laneStage/MaskedWrite.scala b/t1/src/laneStage/MaskedWrite.scala index ff79e3b0c..b964c69ac 100644 --- a/t1/src/laneStage/MaskedWrite.scala +++ b/t1/src/laneStage/MaskedWrite.scala @@ -6,8 +6,17 @@ package org.chipsalliance.t1.rtl.lane import chisel3._ import chisel3.experimental.hierarchy.{instantiable, public} import chisel3.util._ -import org.chipsalliance.t1.rtl.{LaneParameter, VRFReadRequest, VRFWriteRequest, ffo, indexToOH} +import org.chipsalliance.t1.rtl.{LaneParameter, VRFReadRequest, VRFWriteRequest, ffo, indexToOH, maskAnd} +import scala.annotation.unused + +/** s0 enqueue read fire + * raw check: hit s1, hit s2, hit s3 + * + * s1 wait arbiter(reg) + * s2 wait sram read(reg) + * s3 dequeu(reg) + **/ @instantiable class MaskedWrite(parameter: LaneParameter) extends Module { val vrfWriteBundle: VRFWriteRequest = new VRFWriteRequest( @@ -31,40 +40,117 @@ class MaskedWrite(parameter: LaneParameter) extends Module { */ @public val vrfReadResult: UInt = IO(Input(UInt(parameter.datapathWidth.W))) + + def address(req: VRFWriteRequest): UInt = req.vd ## req.offset + + val dequeueWire: DecoupledIO[VRFWriteRequest] = Wire(chiselTypeOf(dequeue)) + val dequeueQueue: Queue[VRFWriteRequest] = Module(new Queue(chiselTypeOf(dequeue.bits), 1, flow = true)) + dequeueQueue.io.enq <> dequeueWire + val s3Valid: Bool = RegInit(false.B) + val s3Pipe: VRFWriteRequest = RegInit(0.U.asTypeOf(enqueue.bits)) + val s3BypassData: UInt = RegInit(0.U.asTypeOf(UInt(parameter.datapathWidth.W))) + val dataInS3: UInt = maskAnd(s3Valid, indexToOH(s3Pipe.instructionIndex, parameter.chainingSize)).asUInt + val fwd3: Bool = RegInit(false.B) + + val s2Valid: Bool = RegInit(false.B) + val s2Pipe: VRFWriteRequest = RegInit(0.U.asTypeOf(enqueue.bits)) + val s2BypassData: UInt = RegInit(0.U.asTypeOf(UInt(parameter.datapathWidth.W))) + val s2EnqHitS1: Bool = RegInit(false.B) + val dataInS2: UInt = maskAnd(s2Valid, indexToOH(s2Pipe.instructionIndex, parameter.chainingSize)).asUInt + val fwd2: Bool = RegInit(false.B) + + val s1Valid: Bool = RegInit(false.B) + val s1Pipe: VRFWriteRequest = RegInit(0.U.asTypeOf(enqueue.bits)) + val s1BypassData: UInt = RegInit(0.U.asTypeOf(UInt(parameter.datapathWidth.W))) + val s1EnqHitS1: Bool = RegInit(false.B) + val s1EnqHitS2: Bool = RegInit(false.B) + val dataInS1: UInt = maskAnd(s1Valid, indexToOH(s1Pipe.instructionIndex, parameter.chainingSize)).asUInt + val fwd1: Bool = RegInit(false.B) + + val s3EnqReady: Bool = dequeueWire.ready || !s3Valid + val s3Fire: Bool = s3EnqReady && s2Valid + + val s2EnqReady: Bool = s3EnqReady || !s2Valid + val s2Fire: Bool = s2EnqReady && s1Valid + + val s1EnqReady: Bool = Wire(Bool()) + enqueue.ready := s1EnqReady + val s1Fire: Bool = enqueue.fire + // raw forward - val hitWrite: Bool = Wire(Bool()) + val enqHitS1: Bool = s1Valid && address(enqueue.bits) === address(s1Pipe) + val enqHitS2: Bool = s2Valid && address(enqueue.bits) === address(s2Pipe) + val enqHitS3: Bool = s3Valid && address(enqueue.bits) === address(s3Pipe) + val hitQueue: Bool = dequeueQueue.io.count =/= 0.U && + address(enqueue.bits) === address(dequeueQueue.io.deq.bits) + val fwd: Bool = enqHitS1 || enqHitS2 || enqHitS3 + s1EnqReady := (s2EnqReady || !s1Valid) && !hitQueue + val dataInQueue: UInt = maskAnd(dequeueQueue.io.count =/= 0.U, + indexToOH(dequeueQueue.io.deq.bits.instructionIndex, parameter.chainingSize)).asUInt + val enqNeedRead: Bool = !enqueue.bits.mask.andR && !fwd // 需要这个读端口完全ready - val readBeforeWrite: Bool = enqueue.fire && !enqueue.bits.mask.andR - vrfReadRequest.valid := readBeforeWrite && !hitWrite + val readBeforeWrite: Bool = enqueue.fire && enqNeedRead + vrfReadRequest.valid := readBeforeWrite vrfReadRequest.bits.vs := enqueue.bits.vd vrfReadRequest.bits.readSource := 2.U vrfReadRequest.bits.offset := enqueue.bits.offset vrfReadRequest.bits.instructionIndex := enqueue.bits.instructionIndex - // latch data - val readNext: Bool = RegNext(readBeforeWrite, false.B) - val dataFromWrite: Bool = RegNext(hitWrite, false.B) - val writeNext: UInt = RegNext(dequeue.bits.data, 0.U) - val readDataSelect: UInt = Mux(dataFromWrite, writeNext, vrfReadResult) - val dataReg: UInt = RegEnable(readDataSelect, 0.U(parameter.datapathWidth.W), readNext) - val latchDataSelect: UInt = Mux(readNext, readDataSelect, dataReg) - - val pipeValid: Bool = RegInit(false.B) - val enqueuePipe: VRFWriteRequest = RegEnable(enqueue.bits, 0.U.asTypeOf(enqueue.bits), enqueue.fire) - val writeQueue: Queue[VRFWriteRequest] = Module(new Queue(chiselTypeOf(enqueue.bits), entries = 1, flow = true)) - dequeue <> writeQueue.io.deq - writeQueue.io.enq.valid := pipeValid - writeQueue.io.enq.bits := enqueuePipe - val maskFill: UInt = FillInterleaved(8, enqueuePipe.mask) - writeQueue.io.enq.bits.data := enqueuePipe.data & maskFill | (latchDataSelect & (~maskFill)) - maskedWrite1H := - Mux(writeQueue.io.deq.valid, indexToOH(writeQueue.io.deq.bits.instructionIndex, parameter.chainingSize), 0.U) | - Mux(pipeValid, indexToOH(enqueuePipe.instructionIndex, parameter.chainingSize), 0.U) - enqueue.ready := !pipeValid || writeQueue.io.enq.ready - when(enqueue.fire ^ writeQueue.io.enq.fire) { - pipeValid := enqueue.fire + + val vrfReadPipe: Queue[UInt] = Module(new Queue( + UInt(parameter.datapathWidth.W), + parameter.vrfParam.vrfReadLatency + 2)) + + val readDataValid: Bool = Pipe( + readBeforeWrite, + false.B, + parameter.vrfParam.vrfReadLatency + ).valid + + vrfReadPipe.io.enq.valid := readDataValid + vrfReadPipe.io.enq.bits := vrfReadResult + + maskedWrite1H := dataInS3 | dataInS2 | dataInS1 | dataInQueue + + val maskFill: UInt = FillInterleaved(8, s3Pipe.mask) + val readDataSelect = Mux(fwd3, s3BypassData, vrfReadPipe.io.deq.bits) + val s3ReadFromVrf: Bool = !s3Pipe.mask.andR && !fwd3 + dequeueWire.valid := s3Valid + dequeueWire.bits := s3Pipe + dequeueWire.bits.data := s3Pipe.data & maskFill | (readDataSelect & (~maskFill)) + vrfReadPipe.io.deq.ready := dequeueWire.fire && s3ReadFromVrf + + // update s1 reg + when(s1Fire) { + s1BypassData := dequeueWire.bits.data + s1EnqHitS1 := enqHitS1 + s1EnqHitS2 := enqHitS2 + fwd1 := fwd + s1Pipe := enqueue.bits + } + when(s1Fire ^ s2Fire) { + s1Valid := s1Fire + } + + // update s2 reg + when(s2Fire) { + s2BypassData := Mux(s1EnqHitS2, dequeueWire.bits.data, s1BypassData) + s2EnqHitS1 := s1EnqHitS1 + fwd2 := fwd1 + s2Pipe := s1Pipe + } + when(s2Fire ^ s3Fire) { + s2Valid := s2Fire + } + + // update s3 reg + when(s3Fire) { + s3BypassData := Mux(s2EnqHitS1, dequeueWire.bits.data, s2BypassData) + fwd3 := fwd2 + s3Pipe := s2Pipe + } + when(s3Fire ^ dequeueWire.fire) { + s3Valid := s3Fire } - hitWrite := writeQueue.io.deq.valid && - (writeQueue.io.deq.bits.vd === enqueue.bits.vd) && - (writeQueue.io.deq.bits.offset === enqueue.bits.offset) + dequeue <> dequeueQueue.io.deq } diff --git a/t1/src/laneStage/VrfReadPipe.scala b/t1/src/laneStage/VrfReadPipe.scala index d61ba7e22..9d8e0f8e0 100644 --- a/t1/src/laneStage/VrfReadPipe.scala +++ b/t1/src/laneStage/VrfReadPipe.scala @@ -6,7 +6,7 @@ package org.chipsalliance.t1.rtl.lane import chisel3._ import chisel3.experimental.hierarchy.{instantiable, public} import chisel3.util._ -import org.chipsalliance.t1.rtl.{LaneParameter, VRFReadQueueEntry, VRFReadRequest} +import org.chipsalliance.t1.rtl.{DataPipeInReadStage, LaneParameter, VRFReadQueueEntry, VRFReadRequest} @instantiable class VrfReadPipe(parameter: LaneParameter, arbitrate: Boolean = false) extends Module { @@ -42,30 +42,25 @@ class VrfReadPipe(parameter: LaneParameter, arbitrate: Boolean = false) extends (Seq(enqueue) ++ contender).zip(reqArbitrate.io.in).foreach { case (source, sink) => sink <> source } - val dataStageFree = Wire(Bool()) // access read port - vrfReadRequest.valid := reqArbitrate.io.out.valid && dataStageFree + vrfReadRequest.valid := reqArbitrate.io.out.valid && dequeue.ready vrfReadRequest.bits.vs := reqArbitrate.io.out.bits.vs vrfReadRequest.bits.readSource := reqArbitrate.io.out.bits.readSource vrfReadRequest.bits.offset := reqArbitrate.io.out.bits.offset vrfReadRequest.bits.instructionIndex := reqArbitrate.io.out.bits.instructionIndex - reqArbitrate.io.out.ready := dataStageFree && vrfReadRequest.ready + reqArbitrate.io.out.ready := dequeue.ready && vrfReadRequest.ready - // read pipe stage1 - val readPortFire: Bool = vrfReadRequest.fire - val stage1Valid: Bool = RegInit(false.B) - val ReadFireNext: Bool = RegNext(readPortFire) - val dataReg: UInt = RegEnable(vrfReadResult, 0.U(parameter.datapathWidth.W), ReadFireNext) - val stage1Choose: Option[Bool] = Option.when(arbitrate)(RegEnable(enqueue.fire, false.B, readPortFire)) + val vrfReadLatency = parameter.vrfParam.vrfReadLatency + val dataQueue = Module(new Queue(new DataPipeInReadStage(parameter.datapathWidth, arbitrate), vrfReadLatency + 2)) + val dataResponsePipe = Pipe(vrfReadRequest.fire, enqueue.fire, vrfReadLatency) - stage1Choose.foreach {d => when(readPortFire) { d := enqueue.fire}} - when(readPortFire ^ dequeue.fire) { - stage1Valid := readPortFire - } + dataQueue.io.enq.valid := dataResponsePipe.valid + dataQueue.io.enq.bits.data := vrfReadResult + dataQueue.io.enq.bits.choose.foreach(_ := dataResponsePipe.bits) + assert(!dataQueue.io.enq.valid || dataQueue.io.enq.ready, "queue overflow") - dataStageFree := !stage1Valid || dequeue.ready - - dequeueChoose.zip(stage1Choose).foreach { case (io, data) => io := data } - dequeue.valid := stage1Valid - dequeue.bits := Mux(ReadFireNext, vrfReadResult, dataReg) + dequeueChoose.foreach { _ := dataQueue.io.deq.bits.choose.get } + dequeue.valid := dataQueue.io.deq.valid + dequeue.bits := dataQueue.io.deq.bits.data + dataQueue.io.deq.ready := dequeue.ready } diff --git a/t1/src/lsu/Bundle.scala b/t1/src/lsu/Bundle.scala index dad0d42bb..fc02111ca 100644 --- a/t1/src/lsu/Bundle.scala +++ b/t1/src/lsu/Bundle.scala @@ -65,4 +65,5 @@ class SimpleAccessStage1(param: MSHRParam) extends Bundle { // 访问l2的地址 val address: UInt = UInt(param.paWidth.W) + val readData: UInt = UInt(param.datapathWidth.W) } diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala index cc87eaa61..ea850c7c4 100644 --- a/t1/src/lsu/LSU.scala +++ b/t1/src/lsu/LSU.scala @@ -283,7 +283,10 @@ class LSU(param: LSUParameter) extends Module { storeUnit.vrfReadResults(index) := vrfReadResults(index) } otherUnit.vrfReadDataPorts.ready := (otherTryReadVrf & VecInit(vrfReadDataPorts.map(_.ready)).asUInt).orR - otherUnit.vrfReadResults := Mux1H(RegNext(otherUnit.status.targetLane), vrfReadResults) + val pipeOtherRead: ValidIO[UInt] = + Pipe(otherUnit.vrfReadDataPorts.fire, otherUnit.status.targetLane, param.vrfReadLatency) + otherUnit.vrfReadResults.bits := Mux1H(pipeOtherRead.bits, vrfReadResults) + otherUnit.vrfReadResults.valid := pipeOtherRead.valid // write vrf val otherTryToWrite: UInt = Mux(otherUnit.vrfWritePort.valid, otherUnit.status.targetLane, 0.U) diff --git a/t1/src/lsu/SimpleAccessUnit.scala b/t1/src/lsu/SimpleAccessUnit.scala index c08721086..4fa89307e 100644 --- a/t1/src/lsu/SimpleAccessUnit.scala +++ b/t1/src/lsu/SimpleAccessUnit.scala @@ -160,7 +160,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic { * see [[LSU.vrfReadResults]] */ @public - val vrfReadResults: UInt = IO(Input(UInt(param.datapathWidth.W))) + val vrfReadResults: ValidIO[UInt] = IO(Input(Valid(UInt(param.datapathWidth.W)))) /** offset of indexed load/store instructions. */ @public @@ -718,11 +718,13 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic { // ask Scheduler to change offset group status.offsetGroupEnd := needRequestOffset && requestOffset && !requestOffsetNext + val s0DequeueFire: Bool = Wire(Bool()) + /** valid signal to enqueue to s0. */ val s0EnqueueValid: Bool = stateReady && !last /** there exist valid signal inside s0. */ - val s0Valid: Bool = RegEnable(s0Fire, false.B, s0Fire ^ s1Fire) + val s0Valid: Bool = RegEnable(s0Fire, false.B, s0Fire ^ s0DequeueFire) /** request enqueue to s0. */ val s0Wire: MSHRStage0Bundle = Wire(new MSHRStage0Bundle(param)) @@ -736,6 +738,10 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic { /** element index enqueuing to s0. */ val s0ElementIndex: UInt = groupIndex ## nextElementForMemoryRequestIndex + // Reading vrf may take multiple cycles and requires additional information to be stored + val s1EnqQueue: Queue[SimpleAccessStage1] = Module(new Queue(new SimpleAccessStage1(param), param.vrfReadLatency + 2)) + val s1EnqDataQueue: Queue[UInt] = Module(new Queue(UInt(param.datapathWidth.W), param.vrfReadLatency + 2)) + /** which byte to access in VRF, e.g. * VLEN=1024,datapath=32,laneNumber=8 * XXXXXXXXXX <- 10 bits for element(32bits) index @@ -789,7 +795,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic { // s1 access VRF // TODO: perf `lsuRequestReg.instructionInformation.isStore && vrfReadDataPorts.ready` to check the VRF bandwidth // limitation affecting to LSU store. - vrfReadDataPorts.valid := s0Valid && lsuRequestReg.instructionInformation.isStore && s1EnqueueReady + vrfReadDataPorts.valid := s0Valid && lsuRequestReg.instructionInformation.isStore && s1EnqQueue.io.enq.ready vrfReadDataPorts.bits.offset := s0Reg.offsetForVSInLane.getOrElse(DontCare) vrfReadDataPorts.bits.vs := s0Reg.readVS vrfReadDataPorts.bits.readSource := 2.U @@ -798,9 +804,6 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic { /** ready to read VRF to store to memory. */ val readReady: Bool = !lsuRequestReg.instructionInformation.isStore || vrfReadDataPorts.ready - /** valid signal to enqueue to s1 */ - val s1EnqueueValid: Bool = s0Valid && readReady - /** data is valid in s1 */ val s1Valid: Bool = RegEnable(s1Fire, false.B, s1Fire ^ s2Fire) @@ -814,36 +817,35 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic { val s2EnqueueReady: Bool = tlPort.a.ready && sourceFree s1EnqueueReady := s2EnqueueReady || !s1Valid - s1Fire := s1EnqueueValid && s1EnqueueReady /** ready signal to enqueue to s0. */ - val s0EnqueueReady: Bool = (s1EnqueueReady && readReady) || !s0Valid + val s0EnqueueReady: Bool = (s1EnqQueue.io.enq.ready && readReady) || !s0Valid s0Fire := s0EnqueueReady && s0EnqueueValid /** pipeline is flushed. */ - val pipelineClear: Bool = !s0Valid && !s1Valid - - s1Wire.address := lsuRequestReg.rs1Data + s0Reg.addressOffset - s1Wire.indexInMaskGroup := s0Reg.indexInGroup - s1Wire.segmentIndex := s0Reg.segmentIndex - - /** previous cycle sent the VRF read request, - * this cycle should got response from each lanes - * TODO: I think the latency is too large here. - */ - val readVRFResponseValid: Bool = RegNext(s1Fire) && lsuRequestReg.instructionInformation.isStore - // readResult hold unless readNext - /** latch from lanes [[vrfReadResults]] */ - val vrfReadResultsReg: UInt = RegEnable(vrfReadResults, 0.U.asTypeOf(vrfReadResults), readVRFResponseValid) - - /** is [[vrfReadResultsReg]] valid or not? - * TODO: I think this is bad for timing... - */ - val readDataRegValid: Bool = - RegEnable(readVRFResponseValid, false.B, (readVRFResponseValid ^ tlPort.a.fire) || lsuRequest.valid) - - /** mux to select from [[vrfReadResultsReg]] or [[vrfReadResults]] */ - val readDataResultSelect: UInt = Mux(readDataRegValid, vrfReadResultsReg, vrfReadResults) + val pipelineClear: Bool = !s0Valid && !s1Valid && !s1EnqQueue.io.deq.valid + + s0DequeueFire := s1EnqQueue.io.enq.fire + s1EnqQueue.io.enq.valid := s0Valid && readReady + s1EnqQueue.io.enq.bits.address := lsuRequestReg.rs1Data + s0Reg.addressOffset + s1EnqQueue.io.enq.bits.indexInMaskGroup := s0Reg.indexInGroup + s1EnqQueue.io.enq.bits.segmentIndex := s0Reg.segmentIndex + s1EnqQueue.io.enq.bits.readData := DontCare + // pipe read data + s1EnqDataQueue.io.enq.valid := vrfReadResults.valid + assert(s1EnqDataQueue.io.enq.ready || !vrfReadResults.valid, "read queue in simple access ") + s1EnqDataQueue.io.enq.bits := vrfReadResults.bits + + s1Wire.address := s1EnqQueue.io.deq.bits.address + s1Wire.indexInMaskGroup := s1EnqQueue.io.deq.bits.indexInMaskGroup + s1Wire.segmentIndex := s1EnqQueue.io.deq.bits.segmentIndex + s1Wire.readData := s1EnqDataQueue.io.deq.bits + + val s1DataEnqValid: Bool = s1EnqDataQueue.io.deq.valid || !lsuRequestReg.instructionInformation.isStore + val s1EnqValid: Bool = s1DataEnqValid && s1EnqQueue.io.deq.valid + s1Fire := s1EnqValid && s1EnqueueReady + s1EnqQueue.io.deq.ready := s1EnqueueReady && s1DataEnqValid + s1EnqDataQueue.io.deq.ready := s1EnqueueReady val addressInBeatByte: UInt = s1Reg.address(log2Ceil(param.tlParam.a.maskWidth) - 1, 0) // 1 -> 1 2 -> 3 4 -> 15 @@ -858,7 +860,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic { * TODO: use Mux1H to select(only 4 cases). */ val storeData: UInt = - ((readDataResultSelect << (addressInBeatByte ## 0.U(3.W))) >> (storeOffsetByIndex ## 0.U(3.W))).asUInt + ((s1Reg.readData << (addressInBeatByte ## 0.U(3.W))) >> (storeOffsetByIndex ## 0.U(3.W))).asUInt // only PutFull / Get for now tlPort.a.bits.opcode := !lsuRequestReg.instructionInformation.isStore ## 0.U(2.W) tlPort.a.bits.param := 0.U diff --git a/t1/src/lsu/StoreUnit.scala b/t1/src/lsu/StoreUnit.scala index 58f60aad2..cb86bab54 100644 --- a/t1/src/lsu/StoreUnit.scala +++ b/t1/src/lsu/StoreUnit.scala @@ -116,7 +116,7 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic { assert(!queue.io.enq.valid || queue.io.enq.ready) vrfReadQueueVec(laneIndex).io.enq <> queue.io.deq - stageValid + stageValid || RegNext(readPort.fire) }.reduce(_ || _) // stage buffer stage: data before regroup diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala index 8c018994e..a8771bcb8 100644 --- a/t1/src/vrf/VRF.scala +++ b/t1/src/vrf/VRF.scala @@ -8,7 +8,7 @@ import chisel3.experimental.hierarchy.{Instantiate, instantiable, public} import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import chisel3.probe.{Probe, ProbeValue, define} import chisel3.util._ -import org.chipsalliance.t1.rtl.{LSUWriteCheck, VRFReadRequest, VRFWriteReport, VRFWriteRequest, ffo, instIndexL, ohCheck} +import org.chipsalliance.t1.rtl.{LSUWriteCheck, VRFReadPipe, VRFReadRequest, VRFWriteReport, VRFWriteRequest, ffo, instIndexL, ohCheck} sealed trait RamType object RamType { @@ -102,9 +102,11 @@ case class VRFParam( val elementSize: Int = vLen * 8 / datapathWidth / laneNumber - val indexBits: Int = log2Ceil(rfDepth) // todo: 4 bit for ecc val memoryWidth: Int = ramWidth + 4 + + // 1: pipe access request + 1: SyncReadMem + val vrfReadLatency = 2 } class VRFProbe(regNumBits: Int, offsetBits: Int, instructionIndexSize: Int, dataPathWidth: Int) extends Bundle { @@ -242,6 +244,13 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar val readResultF: Vec[UInt] = Wire(Vec(parameter.rfBankNum, UInt(parameter.ramWidth.W))) val readResultS: Vec[UInt] = Wire(Vec(parameter.rfBankNum, UInt(parameter.ramWidth.W))) + val firstReadPipe: Seq[ValidIO[VRFReadPipe]] = Seq.tabulate(parameter.rfBankNum) { _ => RegInit(0.U.asTypeOf(Valid(new VRFReadPipe(parameter.rfDepth))))} + val secondReadPipe: Seq[ValidIO[VRFReadPipe]] = Seq.tabulate(parameter.rfBankNum) { _ => RegInit(0.U.asTypeOf(Valid(new VRFReadPipe(parameter.rfDepth))))} + val writePipe: ValidIO[VRFWriteRequest] = RegInit(0.U.asTypeOf(Valid(chiselTypeOf(write.bits)))) + writePipe.valid := write.fire + when(write.fire) { writePipe.bits := write.bits } + val writeBankPipe: UInt = RegNext(writeBank) + val checkSize: Int = readRequests.size val (firstOccupied, secondOccupied) = readRequests.zipWithIndex.foldLeft( (0.U(parameter.rfBankNum.W), 0.U(parameter.rfBankNum.W)) @@ -270,7 +279,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar val validCorrect: Bool = if (i == 0) v.valid else v.valid && checkResult // select bank val bank = if (parameter.rfBankNum == 1) true.B else UIntToOH(v.bits.offset(log2Ceil(parameter.rfBankNum) - 1, 0)) - val bankNext = RegNext(bank) + val pipeBank = Pipe(true.B, bank, parameter.vrfReadLatency).bits val bankCorrect = Mux(validCorrect, bank, 0.U(parameter.rfBankNum.W)) val readPortCheckSelect = parameter.ramType match { case RamType.p0rw => o @@ -280,14 +289,16 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar portConflictCheck := (parameter.ramType match { case RamType.p0rw => true.B case _ => - !(write.valid && bank === writeBank && write.bits.vd === v.bits.vs && write.bits.offset === v.bits.offset) + !((write.valid && bank === writeBank && write.bits.vd === v.bits.vs && write.bits.offset === v.bits.offset) || + (writePipe.valid && bank === writeBankPipe && writePipe.bits.vd === v.bits.vs && writePipe.bits.offset === v.bits.offset)) }) // 我选的这个port的第二个read port 没被占用 v.ready := (bank & (~readPortCheckSelect)).orR && checkResult val firstUsed = (bank & o).orR bankReadF(i) := bankCorrect & (~o) bankReadS(i) := bankCorrect & (~t) & o - readResults(i) := Mux(RegNext(firstUsed), Mux1H(bankNext, readResultS), Mux1H(bankNext, readResultF)) + val pipeFirstUsed = Pipe(true.B, firstUsed, parameter.vrfReadLatency).bits + readResults(i) := Mux(pipeFirstUsed, Mux1H(pipeBank, readResultS), Mux1H(pipeBank, readResultF)) (o | bankCorrect, (bankCorrect & o) | t) } write.ready := (parameter.ramType match { @@ -317,49 +328,62 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar case RamType.p0rwp1rw => 2 } ) + val writeValid: Bool = writePipe.valid && writeBankPipe(bank) parameter.ramType match { case RamType.p0rw => - rf.readwritePorts.last.address := Mux( - write.fire && writeBank(bank), - (write.bits.vd ## write.bits.offset) >> log2Ceil(parameter.rfBankNum), + firstReadPipe(bank).bits.address := Mux1H(bankReadF.map(_(bank)), readRequests.map(r => (r.bits.vs ## r.bits.offset) >> log2Ceil(parameter.rfBankNum))) + firstReadPipe(bank).valid := bankReadF.map(_(bank)).reduce(_ || _) + rf.readwritePorts.last.address := Mux( + writeValid, + (writePipe.bits.vd ## writePipe.bits.offset) >> log2Ceil(parameter.rfBankNum), + firstReadPipe(bank).bits.address ) - rf.readwritePorts.last.enable := write.fire && writeBank(bank) || bankReadF.map(_(bank)).reduce(_ || _) - rf.readwritePorts.last.isWrite := write.fire && writeBank(bank) - rf.readwritePorts.last.writeData := write.bits.data + rf.readwritePorts.last.enable := writeValid || firstReadPipe(bank).valid + rf.readwritePorts.last.isWrite := writeValid + rf.readwritePorts.last.writeData := writePipe.bits.data + assert(!(writeValid && firstReadPipe(bank).valid), "port conflict") readResultF(bank) := rf.readwritePorts.head.readData readResultS(bank) := DontCare case RamType.p0rp1w => - // connect readPorts - rf.readPorts.head.address := + firstReadPipe(bank).bits.address := Mux1H(bankReadF.map(_(bank)), readRequests.map(r => (r.bits.vs ## r.bits.offset) >> log2Ceil(parameter.rfBankNum))) - rf.readPorts.head.enable := bankReadF.map(_(bank)).reduce(_ || _) + firstReadPipe(bank).valid := bankReadF.map(_(bank)).reduce(_ || _) + // connect readPorts + rf.readPorts.head.address := firstReadPipe(bank).bits.address + rf.readPorts.head.enable := firstReadPipe(bank).valid readResultF(bank) := rf.readPorts.head.data readResultS(bank) := DontCare - rf.writePorts.head.enable := write.fire && writeBank(bank) - rf.writePorts.head.address := (write.bits.vd ## write.bits.offset) >> log2Ceil(parameter.rfBankNum) - rf.writePorts.head.data := write.bits.data + rf.writePorts.head.enable := writeValid + rf.writePorts.head.address := (writePipe.bits.vd ## writePipe.bits.offset) >> log2Ceil(parameter.rfBankNum) + rf.writePorts.head.data := writePipe.bits.data case RamType.p0rwp1rw => - // connect readPorts - rf.readwritePorts.head.address := + firstReadPipe(bank).bits.address := Mux1H(bankReadF.map(_(bank)), readRequests.map(r => (r.bits.vs ## r.bits.offset) >> log2Ceil(parameter.rfBankNum))) - rf.readwritePorts.head.enable := bankReadF.map(_(bank)).reduce(_ || _) + firstReadPipe(bank).valid := bankReadF.map(_(bank)).reduce(_ || _) + // connect readPorts + rf.readwritePorts.head.address := firstReadPipe(bank).bits.address + rf.readwritePorts.head.enable := firstReadPipe(bank).valid rf.readwritePorts.head.isWrite := false.B rf.readwritePorts.head.writeData := DontCare readResultF(bank) := rf.readwritePorts.head.readData readResultS(bank) := rf.readwritePorts.last.readData - rf.readwritePorts.last.address := Mux( - write.fire && writeBank(bank), - (write.bits.vd ## write.bits.offset) >> log2Ceil(parameter.rfBankNum), + secondReadPipe(bank).bits.address := Mux1H(bankReadS.map(_(bank)), readRequests.map(r => (r.bits.vs ## r.bits.offset) >> log2Ceil(parameter.rfBankNum))) + secondReadPipe(bank).valid := bankReadS.map(_(bank)).reduce(_ || _) + rf.readwritePorts.last.address := Mux( + writeValid, + (writePipe.bits.vd ## writePipe.bits.offset) >> log2Ceil(parameter.rfBankNum), + secondReadPipe(bank).bits.address ) - rf.readwritePorts.last.enable := write.fire && writeBank(bank) || bankReadS.map(_(bank)).reduce(_ || _) - rf.readwritePorts.last.isWrite := write.fire && writeBank(bank) - rf.readwritePorts.last.writeData := write.bits.data + rf.readwritePorts.last.enable := writeValid || secondReadPipe(bank).valid + rf.readwritePorts.last.isWrite := writeValid + rf.readwritePorts.last.writeData := writePipe.bits.data + assert(!(writeValid && secondReadPipe(bank).valid), "port conflict") } rf @@ -383,7 +407,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar 0.U((parameter.chainingSize + 1).W) ) - val writePort: Seq[DecoupledIO[VRFWriteRequest]] = Seq(write) + val writePort: Seq[ValidIO[VRFWriteRequest]] = Seq(writePipe) val writeOH = writePort.map(p => UIntToOH((p.bits.vd ## p.bits.offset)(parameter.vrfOffsetBits + 3 - 1, 0))) val loadUnitReadPorts: Seq[DecoupledIO[VRFReadRequest]] = Seq(readRequests.last) val loadReadOH: Seq[UInt] =