From 4b93a82217fb7398b9b45d123eaf1bfc8611e7dc Mon Sep 17 00:00:00 2001 From: Avimitin Date: Tue, 17 Dec 2024 01:51:52 +0800 Subject: [PATCH 1/7] [tests] bump rvv-codegen Signed-off-by: Avimitin --- nix/pkgs/rvv-codegen.nix | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/nix/pkgs/rvv-codegen.nix b/nix/pkgs/rvv-codegen.nix index b12aa0baf..b7077538d 100644 --- a/nix/pkgs/rvv-codegen.nix +++ b/nix/pkgs/rvv-codegen.nix @@ -1,29 +1,22 @@ { fetchFromGitHub, buildGoModule }: -let - riscv-test-env = fetchFromGitHub { - owner = "riscv"; - repo = "riscv-test-env"; - rev = "1c577dc7c7d6aee27b8d5cb0e2e87c8473e3ad12"; - hash = "sha256-JZ7Yn4cTel9uVo6uGu0zs3IMMySoGzjSMW544YLYips="; - }; -in buildGoModule { pname = "riscv-vector-test"; version = "unstable-2023-04-12"; src = fetchFromGitHub { owner = "chipsalliance"; repo = "riscv-vector-tests"; - rev = "6f24d9aab1e64a452e3493c85297e9bde805e30c"; - hash = "sha256-5Ie5gZMOqxl8L8tuzpYdrqb/7F6o5UzOMGhn4xzPvQo="; + rev = "52ccb798b355d4442f5d86a710e6bfa0eeb20cc2"; + hash = "sha256-vfr7iMkqy3QUjkfM1by4RYUMpPHIsOk0XZSW8Big39s="; + fetchSubmodules = true; }; doCheck = false; - vendorHash = "sha256-9cQlivpHg6IDYpmgBp34n6BR/I0FIYnmrXCuiGmAhNE="; + vendorHash = "sha256-1A5yCj9AJHp9tcUIpLKamXn4Tl3KPFEtzke5X7h6V+4="; # Get rid of copying the whole source postInstall = '' cp -r $src/configs $out/configs mkdir $out/include - cp ${riscv-test-env}/encoding.h $out/include + cp env/riscv-test-env/encoding.h $out/include ''; } From 1bef4b7e30b0e03e75aa2a6dea922c25b500639b Mon Sep 17 00:00:00 2001 From: Avimitin Date: Tue, 17 Dec 2024 15:32:11 +0800 Subject: [PATCH 2/7] [nix] remove legacy 'rvv-codegen' naming --- nix/overlay.nix | 2 +- nix/pkgs/{rvv-codegen.nix => riscv-vector-test.nix} | 2 +- tests/codegen/default.nix | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) rename nix/pkgs/{rvv-codegen.nix => riscv-vector-test.nix} (94%) diff --git a/nix/overlay.nix b/nix/overlay.nix index 4df089e9c..27c40b0a8 100644 --- a/nix/overlay.nix +++ b/nix/overlay.nix @@ -34,7 +34,7 @@ rec { fetchMillDeps = final.callPackage ./pkgs/mill-builder.nix { }; circt-full = final.callPackage ./pkgs/circt-full.nix { }; - rvv-codegen = final.callPackage ./pkgs/rvv-codegen.nix { }; + riscv-vector-test = final.callPackage ./pkgs/riscv-vector-test.nix { }; add-determinism = final.callPackage ./pkgs/add-determinism { }; # faster strip-undetereminism snps-fhs-env = final.callPackage ./pkgs/snps-fhs-env.nix { }; diff --git a/nix/pkgs/rvv-codegen.nix b/nix/pkgs/riscv-vector-test.nix similarity index 94% rename from nix/pkgs/rvv-codegen.nix rename to nix/pkgs/riscv-vector-test.nix index b7077538d..5a0f03ba8 100644 --- a/nix/pkgs/rvv-codegen.nix +++ b/nix/pkgs/riscv-vector-test.nix @@ -1,7 +1,7 @@ { fetchFromGitHub, buildGoModule }: buildGoModule { pname = "riscv-vector-test"; - version = "unstable-2023-04-12"; + version = "unstable-2024-12-16"; src = fetchFromGitHub { owner = "chipsalliance"; repo = "riscv-vector-tests"; diff --git a/tests/codegen/default.nix b/tests/codegen/default.nix index 7fea95968..4bf91db83 100644 --- a/tests/codegen/default.nix +++ b/tests/codegen/default.nix @@ -1,6 +1,6 @@ { lib , linkerScript -, rvv-codegen +, riscv-vector-test , makeBuilder # Instead of testing feature is supported on TOP level, # codegen case are always generated with supported code. @@ -18,7 +18,7 @@ let includeArgs = [ "-I${./include}" - "-I${rvv-codegen}/include" + "-I${riscv-vector-test}/include" ]; dontUnpack = true; @@ -26,12 +26,12 @@ let buildPhase = '' runHook preBuild - ${rvv-codegen}/bin/single \ + ${riscv-vector-test}/bin/single \ -VLEN "${builtins.toString rtlDesignMetadata.vlen}" \ -XLEN "${builtins.toString rtlDesignMetadata.xlen}" \ -repeat 16 \ -testfloat3level 2 \ - -configfile ${rvv-codegen}/configs/${rawCaseName}.toml \ + -configfile ${riscv-vector-test}/configs/${rawCaseName}.toml \ -outputfile $pname.S # temporary fix, to be extended later From 69193cc7cfdffdd34265631039948cb1f6f97ab0 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Tue, 17 Dec 2024 16:52:07 +0800 Subject: [PATCH 3/7] [tests] set floa16 to false for all codegen cases --- tests/codegen/default.nix | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/codegen/default.nix b/tests/codegen/default.nix index 4bf91db83..9a895d34c 100644 --- a/tests/codegen/default.nix +++ b/tests/codegen/default.nix @@ -26,9 +26,11 @@ let buildPhase = '' runHook preBuild + # Golang only accept "-flag=value" pattern to set value for flag, don't mess around with other cmd line option. ${riscv-vector-test}/bin/single \ -VLEN "${builtins.toString rtlDesignMetadata.vlen}" \ -XLEN "${builtins.toString rtlDesignMetadata.xlen}" \ + -float16=false \ -repeat 16 \ -testfloat3level 2 \ -configfile ${riscv-vector-test}/configs/${rawCaseName}.toml \ From f2b4168e883587654217f417d288783789308011 Mon Sep 17 00:00:00 2001 From: Shupei Fan Date: Wed, 18 Dec 2024 14:13:15 +0000 Subject: [PATCH 4/7] [difftest] fix a bug in memory map route --- difftest/dpi_t1rocketemu/src/interconnect.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/difftest/dpi_t1rocketemu/src/interconnect.rs b/difftest/dpi_t1rocketemu/src/interconnect.rs index 363e5e7bb..206d805dc 100644 --- a/difftest/dpi_t1rocketemu/src/interconnect.rs +++ b/difftest/dpi_t1rocketemu/src/interconnect.rs @@ -180,7 +180,7 @@ impl AddressSpace { for (idx, dev) in self.devices.iter().enumerate() { let (base, size) = dev.base_and_size; if base <= addr && addr - base < size { - return if addr - base + len < size { + return if addr - base + len <= size { Some(idx) } else { None From 5d7ebfe687cfba4e3aad3aa21d254ef7f9a3ab22 Mon Sep 17 00:00:00 2001 From: github-actions Date: Wed, 18 Dec 2024 15:00:47 +0000 Subject: [PATCH 5/7] [ci] update t1 test case cycle data --- .github/designs/blastoise/t1rocketemu.json | 990 ++++++++++----------- .github/designs/rookidee/t1rocketemu.json | 858 +++++++++--------- 2 files changed, 924 insertions(+), 924 deletions(-) diff --git a/.github/designs/blastoise/t1rocketemu.json b/.github/designs/blastoise/t1rocketemu.json index bcf65da3a..2aa308d9b 100644 --- a/.github/designs/blastoise/t1rocketemu.json +++ b/.github/designs/blastoise/t1rocketemu.json @@ -4,501 +4,501 @@ "asm.smoke": 7614, "asm.strlen": 8256, "asm.utf8_count": 282, - "codegen.vaadd_vv": 193940, - "codegen.vaadd_vx": 612032, - "codegen.vaaddu_vv": 193940, - "codegen.vaaddu_vx": 612032, - "codegen.vadc_vim": 52177, - "codegen.vadc_vvm": 24192, - "codegen.vadc_vxm": 74833, - "codegen.vadd_vi": 104896, - "codegen.vadd_vv": 48842, - "codegen.vadd_vx": 153662, - "codegen.vand_vi": 104886, - "codegen.vand_vv": 48842, - "codegen.vand_vx": 153988, - "codegen.vasub_vv": 193940, - "codegen.vasub_vx": 612032, - "codegen.vasubu_vv": 193940, - "codegen.vasubu_vx": 612032, - "codegen.vcompress_vm": 22457, - "codegen.vcpop_m": 3999, - "codegen.vdiv_vv": 73223, - "codegen.vdiv_vx": 602724, - "codegen.vdivu_vv": 73628, - "codegen.vdivu_vx": 634057, - "codegen.vfadd_vf": 822357, - "codegen.vfadd_vv": 167347, - "codegen.vfclass_v": 13040, - "codegen.vfcvt_f_x_v": 13026, - "codegen.vfcvt_f_xu_v": 13026, - "codegen.vfcvt_rtz_x_f_v": 13026, - "codegen.vfcvt_rtz_xu_f_v": 13026, - "codegen.vfcvt_x_f_v": 13026, - "codegen.vfcvt_xu_f_v": 13026, - "codegen.vfdiv_vf": 2375369, - "codegen.vfdiv_vv": 324902, - "codegen.vfirst_m": 3870, - "codegen.vfmacc_vf": 806927, - "codegen.vfmacc_vv": 174831, - "codegen.vfmadd_vf": 911664, - "codegen.vfmadd_vv": 174831, - "codegen.vfmax_vf": 770429, - "codegen.vfmax_vv": 174959, - "codegen.vfmerge_vfm": 548061, - "codegen.vfmin_vf": 822357, - "codegen.vfmin_vv": 174959, - "codegen.vfmsac_vf": 911664, - "codegen.vfmsac_vv": 174831, - "codegen.vfmsub_vf": 911664, - "codegen.vfmsub_vv": 174831, - "codegen.vfmul_vf": 822357, - "codegen.vfmul_vv": 174959, - "codegen.vfmv_f_s": 16004, - "codegen.vfmv_s_f": 1944, - "codegen.vfmv_v_f": 4341, - "codegen.vfnmacc_vf": 879542, - "codegen.vfnmacc_vv": 174831, - "codegen.vfnmadd_vf": 838629, - "codegen.vfnmadd_vv": 174831, - "codegen.vfnmsac_vf": 838629, - "codegen.vfnmsac_vv": 174831, - "codegen.vfnmsub_vf": 838629, - "codegen.vfnmsub_vv": 174831, - "codegen.vfrdiv_vf": 2375369, - "codegen.vfrec7_v": 13026, - "codegen.vfredmax_vs": 248941, - "codegen.vfredmin_vs": 244112, - "codegen.vfredosum_vs": 328537, - "codegen.vfredusum_vs": 248941, - "codegen.vfrsqrt7_v": 13026, - "codegen.vfrsub_vf": 770429, - "codegen.vfsgnj_vf": 694055, - "codegen.vfsgnj_vv": 174959, - "codegen.vfsgnjn_vf": 694055, - "codegen.vfsgnjn_vv": 167347, - "codegen.vfsgnjx_vf": 694055, - "codegen.vfsgnjx_vv": 167347, - "codegen.vfslide1down_vf": 1083428, - "codegen.vfslide1up_vf": 1125410, - "codegen.vfsqrt_v": 29527, - "codegen.vfsub_vf": 822357, - "codegen.vfsub_vv": 167347, - "codegen.vid_v": 30414, - "codegen.viota_m": 42562, - "codegen.vl1re16_v": 1932, - "codegen.vl1re32_v": 1932, - "codegen.vl1re8_v": 1932, - "codegen.vl2re16_v": 2012, - "codegen.vl2re32_v": 2059, - "codegen.vl2re8_v": 2059, - "codegen.vl4re16_v": 2312, - "codegen.vl4re32_v": 2312, - "codegen.vl4re8_v": 2489, - "codegen.vl8re16_v": 2828, - "codegen.vl8re32_v": 2780, - "codegen.vl8re8_v": 2780, - "codegen.vle16_v": 10544, - "codegen.vle16ff_v": 26632, - "codegen.vle32_v": 8787, - "codegen.vle32ff_v": 16142, - "codegen.vle8_v": 12407, - "codegen.vle8ff_v": 49109, - "codegen.vlm_v": 2062, - "codegen.vloxei16_v": 72665, - "codegen.vloxei32_v": 39513, - "codegen.vloxei8_v": 113610, - "codegen.vloxseg2ei16_v": 74960, - "codegen.vloxseg2ei32_v": 41026, - "codegen.vloxseg2ei8_v": 95376, - "codegen.vloxseg3ei16_v": 51203, - "codegen.vloxseg3ei32_v": 32461, - "codegen.vloxseg3ei8_v": 70470, - "codegen.vloxseg4ei16_v": 61882, - "codegen.vloxseg4ei32_v": 37613, - "codegen.vloxseg4ei8_v": 87090, - "codegen.vloxseg5ei16_v": 37494, - "codegen.vloxseg5ei32_v": 17766, - "codegen.vloxseg5ei8_v": 50692, - "codegen.vloxseg6ei16_v": 42469, - "codegen.vloxseg6ei32_v": 19478, - "codegen.vloxseg6ei8_v": 58040, - "codegen.vloxseg7ei16_v": 47444, - "codegen.vloxseg7ei32_v": 21190, - "codegen.vloxseg7ei8_v": 65388, - "codegen.vloxseg8ei16_v": 52419, - "codegen.vloxseg8ei32_v": 22902, - "codegen.vloxseg8ei8_v": 72736, - "codegen.vlse16_v": 121534, - "codegen.vlse32_v": 70837, - "codegen.vlse8_v": 233203, - "codegen.vlseg2e16_v": 8814, - "codegen.vlseg2e32_v": 6890, - "codegen.vlseg2e8_v": 10556, - "codegen.vlseg3e16_v": 7175, - "codegen.vlseg3e32_v": 5510, - "codegen.vlseg3e8_v": 8794, - "codegen.vlseg4e16_v": 6928, - "codegen.vlseg4e32_v": 5372, - "codegen.vlseg4e8_v": 9184, - "codegen.vlseg5e16_v": 5651, - "codegen.vlseg5e32_v": 3748, - "codegen.vlseg5e8_v": 7334, - "codegen.vlseg6e16_v": 5842, - "codegen.vlseg6e32_v": 3861, - "codegen.vlseg6e8_v": 7546, - "codegen.vlseg7e16_v": 6031, - "codegen.vlseg7e32_v": 3972, - "codegen.vlseg7e8_v": 7773, - "codegen.vlseg8e16_v": 6205, - "codegen.vlseg8e32_v": 4085, - "codegen.vlseg8e8_v": 8019, - "codegen.vlsseg2e16_v": 114994, - "codegen.vlsseg2e32_v": 58322, - "codegen.vlsseg2e8_v": 209647, - "codegen.vlsseg3e16_v": 81646, - "codegen.vlsseg3e32_v": 40318, - "codegen.vlsseg3e8_v": 164996, - "codegen.vlsseg4e16_v": 101751, - "codegen.vlsseg4e32_v": 48731, - "codegen.vlsseg4e8_v": 210118, - "codegen.vlsseg5e16_v": 65265, - "codegen.vlsseg5e32_v": 23381, - "codegen.vlsseg5e8_v": 135877, - "codegen.vlsseg6e16_v": 74835, - "codegen.vlsseg6e32_v": 26231, - "codegen.vlsseg6e8_v": 157627, - "codegen.vlsseg7e16_v": 84405, - "codegen.vlsseg7e32_v": 29081, - "codegen.vlsseg7e8_v": 179377, - "codegen.vlsseg8e16_v": 93975, - "codegen.vlsseg8e32_v": 31931, - "codegen.vlsseg8e8_v": 201127, - "codegen.vluxei16_v": 72665, - "codegen.vluxei32_v": 39513, - "codegen.vluxei8_v": 113610, - "codegen.vluxseg2ei16_v": 74960, - "codegen.vluxseg2ei32_v": 41026, - "codegen.vluxseg2ei8_v": 95376, - "codegen.vluxseg3ei16_v": 51203, - "codegen.vluxseg3ei32_v": 32461, - "codegen.vluxseg3ei8_v": 70470, - "codegen.vluxseg4ei16_v": 61882, - "codegen.vluxseg4ei32_v": 37613, - "codegen.vluxseg4ei8_v": 87090, - "codegen.vluxseg5ei16_v": 37494, - "codegen.vluxseg5ei32_v": 17766, - "codegen.vluxseg5ei8_v": 50692, - "codegen.vluxseg6ei16_v": 42469, - "codegen.vluxseg6ei32_v": 19478, - "codegen.vluxseg6ei8_v": 58040, - "codegen.vluxseg7ei16_v": 47444, - "codegen.vluxseg7ei32_v": 21190, - "codegen.vluxseg7ei8_v": 65388, - "codegen.vluxseg8ei16_v": 52419, - "codegen.vluxseg8ei32_v": 22902, - "codegen.vluxseg8ei8_v": 72736, - "codegen.vmacc_vv": 48980, - "codegen.vmacc_vx": 170194, - "codegen.vmadc_vi": 56653, - "codegen.vmadc_vim": 58154, - "codegen.vmadc_vv": 20118, - "codegen.vmadc_vvm": 23259, - "codegen.vmadc_vx": 79271, - "codegen.vmadc_vxm": 80307, - "codegen.vmadd_vv": 48980, - "codegen.vmadd_vx": 158976, - "codegen.vmand_mm": 19061, - "codegen.vmandn_mm": 19061, - "codegen.vmax_vv": 48842, - "codegen.vmax_vx": 153662, - "codegen.vmaxu_vv": 48842, - "codegen.vmaxu_vx": 153662, - "codegen.vmerge_vim": 86001, - "codegen.vmerge_vvm": 28350, - "codegen.vmerge_vxm": 121703, - "codegen.vmfeq_vf": 968857, - "codegen.vmfeq_vv": 180905, - "codegen.vmfge_vf": 976132, - "codegen.vmfgt_vf": 974240, - "codegen.vmfle_vf": 964070, - "codegen.vmfle_vv": 180905, - "codegen.vmflt_vf": 970749, - "codegen.vmflt_vv": 171623, - "codegen.vmfne_vf": 974240, - "codegen.vmfne_vv": 171623, - "codegen.vmin_vv": 48842, - "codegen.vmin_vx": 153662, - "codegen.vminu_vv": 48842, - "codegen.vminu_vx": 153662, - "codegen.vmnand_mm": 19061, - "codegen.vmnor_mm": 19061, - "codegen.vmor_mm": 19061, - "codegen.vmorn_mm": 19061, - "codegen.vmsbc_vv": 20118, - "codegen.vmsbc_vvm": 23259, - "codegen.vmsbc_vx": 79487, - "codegen.vmsbc_vxm": 81097, - "codegen.vmsbf_m": 2920, - "codegen.vmseq_vi": 116802, - "codegen.vmseq_vv": 45635, - "codegen.vmseq_vx": 161625, - "codegen.vmsgt_vi": 114653, - "codegen.vmsgt_vv": 45577, - "codegen.vmsgt_vx": 161625, - "codegen.vmsgtu_vi": 114653, - "codegen.vmsgtu_vv": 45577, - "codegen.vmsgtu_vx": 161625, - "codegen.vmsif_m": 2920, - "codegen.vmsle_vi": 116387, - "codegen.vmsle_vv": 45635, - "codegen.vmsle_vx": 161625, - "codegen.vmsleu_vi": 115068, - "codegen.vmsleu_vv": 44843, - "codegen.vmsleu_vx": 161625, - "codegen.vmslt_vv": 44843, - "codegen.vmslt_vx": 161625, - "codegen.vmsltu_vv": 45635, - "codegen.vmsltu_vx": 161625, - "codegen.vmsne_vi": 116387, - "codegen.vmsne_vv": 44843, - "codegen.vmsne_vx": 161625, - "codegen.vmsof_m": 2920, - "codegen.vmul_vv": 48962, - "codegen.vmul_vx": 211633, - "codegen.vmulh_vv": 48962, - "codegen.vmulh_vx": 211633, - "codegen.vmulhsu_vv": 48962, - "codegen.vmulhsu_vx": 211633, - "codegen.vmulhu_vv": 48962, - "codegen.vmulhu_vx": 211633, - "codegen.vmv1r_v": 3207, - "codegen.vmv2r_v": 3222, - "codegen.vmv4r_v": 4702, - "codegen.vmv8r_v": 6862, - "codegen.vmv_s_x": 2772, - "codegen.vmv_v_i": 45349, - "codegen.vmv_v_v": 18820, - "codegen.vmv_v_x": 14814, - "codegen.vmv_x_s": 4407, - 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84503, + "codegen.vsadd_vv": 40802, + "codegen.vsadd_vx": 118052, + "codegen.vsaddu_vi": 84503, + "codegen.vsaddu_vv": 40802, + "codegen.vsaddu_vx": 118052, + "codegen.vsbc_vvm": 19566, + "codegen.vsbc_vxm": 85710, + "codegen.vse16_v": 8626, + "codegen.vse32_v": 6869, + "codegen.vse8_v": 10234, + "codegen.vsetivli": 4057, + "codegen.vsetvl": 904, + "codegen.vsetvli": 12501, + "codegen.vsext_vf2": 14567, + "codegen.vsext_vf4": 4260, + "codegen.vslide1down_vx": 210631, + "codegen.vslide1up_vx": 211511, + "codegen.vslidedown_vi": 147102, + "codegen.vslidedown_vx": 173420, + "codegen.vslideup_vi": 146690, + "codegen.vslideup_vx": 163054, + "codegen.vsll_vi": 102442, + "codegen.vsll_vv": 41626, + "codegen.vsll_vx": 143271, + "codegen.vsm_v": 1159, + "codegen.vsmul_vv": 165551, + "codegen.vsmul_vx": 474770, + "codegen.vsoxei16_v": 38399, + "codegen.vsoxei32_v": 23665, + "codegen.vsoxei8_v": 52319, + "codegen.vsoxseg2ei16_v": 34524, + "codegen.vsoxseg2ei32_v": 22501, + "codegen.vsoxseg2ei8_v": 40551, + "codegen.vsoxseg3ei16_v": 24252, + "codegen.vsoxseg3ei32_v": 16852, + "codegen.vsoxseg3ei8_v": 29327, + "codegen.vsoxseg4ei16_v": 27893, + "codegen.vsoxseg4ei32_v": 18944, + "codegen.vsoxseg4ei8_v": 34499, + "codegen.vsoxseg5ei16_v": 17084, + "codegen.vsoxseg5ei32_v": 10529, + "codegen.vsoxseg5ei8_v": 21638, + "codegen.vsoxseg6ei16_v": 18830, + "codegen.vsoxseg6ei32_v": 11323, + "codegen.vsoxseg6ei8_v": 24199, + "codegen.vsoxseg7ei16_v": 20734, + "codegen.vsoxseg7ei32_v": 12185, + "codegen.vsoxseg7ei8_v": 26816, + "codegen.vsoxseg8ei16_v": 22588, + "codegen.vsoxseg8ei32_v": 13303, + "codegen.vsoxseg8ei8_v": 29520, + "codegen.vsra_vi": 102442, + "codegen.vsra_vv": 41626, + "codegen.vsra_vx": 143271, + "codegen.vsrl_vi": 102442, + "codegen.vsrl_vv": 41626, + "codegen.vsrl_vx": 143271, + "codegen.vsse16_v": 31091, + "codegen.vsse32_v": 22311, + "codegen.vsse8_v": 46594, + "codegen.vsseg2e16_v": 8236, + "codegen.vsseg2e32_v": 6255, + "codegen.vsseg2e8_v": 10169, + "codegen.vsseg3e16_v": 7103, + "codegen.vsseg3e32_v": 4806, + "codegen.vsseg3e8_v": 9408, + "codegen.vsseg4e16_v": 8059, + "codegen.vsseg4e32_v": 5491, + "codegen.vsseg4e8_v": 10796, + "codegen.vsseg5e16_v": 6099, + "codegen.vsseg5e32_v": 3159, + "codegen.vsseg5e8_v": 9041, + "codegen.vsseg6e16_v": 6734, + "codegen.vsseg6e32_v": 3467, + "codegen.vsseg6e8_v": 9923, + "codegen.vsseg7e16_v": 7367, + "codegen.vsseg7e32_v": 3773, + "codegen.vsseg7e8_v": 10967, + "codegen.vsseg8e16_v": 8008, + "codegen.vsseg8e32_v": 4123, + "codegen.vsseg8e8_v": 11943, + "codegen.vssra_vi": 410935, + "codegen.vssra_vv": 168222, + "codegen.vssra_vx": 870223, + "codegen.vssrl_vi": 410935, + "codegen.vssrl_vv": 168222, + "codegen.vssrl_vx": 870223, + "codegen.vssseg2e16_v": 31894, + "codegen.vssseg2e32_v": 22586, + "codegen.vssseg2e8_v": 45695, + "codegen.vssseg3e16_v": 28242, + "codegen.vssseg3e32_v": 18526, + "codegen.vssseg3e8_v": 40952, + "codegen.vssseg4e16_v": 35921, + "codegen.vssseg4e32_v": 23407, + "codegen.vssseg4e8_v": 52450, + "codegen.vssseg5e16_v": 28258, + "codegen.vssseg5e32_v": 14329, + "codegen.vssseg5e8_v": 42863, + "codegen.vssseg6e16_v": 33129, + "codegen.vssseg6e32_v": 16739, + "codegen.vssseg6e8_v": 50361, + "codegen.vssseg7e16_v": 37958, + "codegen.vssseg7e32_v": 19128, + "codegen.vssseg7e8_v": 57836, + "codegen.vssseg8e16_v": 42704, + "codegen.vssseg8e32_v": 21555, + "codegen.vssseg8e8_v": 65354, + "codegen.vssub_vv": 39388, + "codegen.vssub_vx": 172470, + "codegen.vssubu_vv": 39388, + "codegen.vssubu_vx": 172470, + "codegen.vsub_vv": 39388, + "codegen.vsub_vx": 172470, + "codegen.vsuxei16_v": 38399, + "codegen.vsuxei32_v": 23665, + "codegen.vsuxei8_v": 52319, + "codegen.vsuxseg2ei16_v": 34524, + "codegen.vsuxseg2ei32_v": 22501, + "codegen.vsuxseg2ei8_v": 40551, + "codegen.vsuxseg3ei16_v": 24252, + "codegen.vsuxseg3ei32_v": 16852, + "codegen.vsuxseg3ei8_v": 29327, + "codegen.vsuxseg4ei16_v": 27893, + "codegen.vsuxseg4ei32_v": 18944, + "codegen.vsuxseg4ei8_v": 34499, + "codegen.vsuxseg5ei16_v": 17084, + "codegen.vsuxseg5ei32_v": 10529, + "codegen.vsuxseg5ei8_v": 21638, + "codegen.vsuxseg6ei16_v": 18830, + "codegen.vsuxseg6ei32_v": 11323, + "codegen.vsuxseg6ei8_v": 24199, + "codegen.vsuxseg7ei16_v": 20734, + "codegen.vsuxseg7ei32_v": 12185, + "codegen.vsuxseg7ei8_v": 26816, + "codegen.vsuxseg8ei16_v": 22588, + "codegen.vsuxseg8ei32_v": 13303, + "codegen.vsuxseg8ei8_v": 29520, + "codegen.vwadd_vv": 22835, + "codegen.vwadd_vx": 70092, + "codegen.vwadd_wv": 23546, + "codegen.vwadd_wx": 74546, + "codegen.vwaddu_vv": 22835, + "codegen.vwaddu_vx": 70092, + "codegen.vwaddu_wv": 23546, + "codegen.vwaddu_wx": 74546, + "codegen.vwmacc_vv": 23456, + "codegen.vwmacc_vx": 84084, + "codegen.vwmaccsu_vv": 23456, + "codegen.vwmaccsu_vx": 84084, + "codegen.vwmaccu_vv": 23456, + "codegen.vwmaccu_vx": 78853, + "codegen.vwmaccus_vx": 78853, + "codegen.vwmul_vv": 22835, + "codegen.vwmul_vx": 92916, + "codegen.vwmulsu_vv": 22835, + "codegen.vwmulsu_vx": 92916, + "codegen.vwmulu_vv": 22835, + "codegen.vwmulu_vx": 92916, + "codegen.vwredsum_vs": 23688, + "codegen.vwredsumu_vs": 23688, + "codegen.vwsub_vv": 22835, + "codegen.vwsub_vx": 70092, + "codegen.vwsub_wv": 23546, + "codegen.vwsub_wx": 74546, + "codegen.vwsubu_vv": 22835, + "codegen.vwsubu_vx": 70092, + "codegen.vwsubu_wv": 23546, + "codegen.vwsubu_wx": 74546, + "codegen.vxor_vi": 83104, + "codegen.vxor_vv": 39388, + "codegen.vxor_vx": 116361, + "codegen.vzext_vf2": 14567, + "codegen.vzext_vf4": 4260, "intrinsic.conv2d_less_m2": 2677, "mlir.hello": 216, "mlir.rvv_vp_intrinsic_add": 554, From 1f01c1a434d41915946f404888d570ef0ec3d603 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Wed, 25 Dec 2024 18:54:54 +0800 Subject: [PATCH 6/7] [tests] update test env macro Signed-off-by: Avimitin --- tests/codegen/include/riscv_test.h | 21 +++++++++++++-------- tests/riscv-test-env/p/riscv_test.h | 10 ++++++++++ tests/riscv-test-env/v/riscv_test.h | 4 ++++ 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/tests/codegen/include/riscv_test.h b/tests/codegen/include/riscv_test.h index 05ae7111d..96deb9638 100644 --- a/tests/codegen/include/riscv_test.h +++ b/tests/codegen/include/riscv_test.h @@ -16,14 +16,14 @@ RVTEST_FP_ENABLE; \ .endm -#define RVTEST_RV64UV \ - .macro init; \ - RVTEST_VECTOR_ENABLE; \ +#define RVTEST_RV64UV \ + .macro init; \ + RVTEST_VECTOR_ENABLE; \ .endm -#define RVTEST_RV64UFV \ +#define RVTEST_RV64UVX \ .macro init; \ - RVTEST_FP_VECTOR_ENABLE; \ + RVTEST_ZVE32X_ENABLE; \ .endm #define RVTEST_RV32U \ @@ -40,6 +40,11 @@ RVTEST_VECTOR_ENABLE; \ .endm +#define RVTEST_RV32UVX \ + .macro init; \ + RVTEST_ZVE32X_ENABLE; \ + .endm + #define INIT_XREG \ li x1, 0; \ li x2, 0; \ @@ -115,14 +120,14 @@ csrs mstatus, a0; \ csrwi fcsr, 0 -#define RVTEST_FP_VECTOR_ENABLE \ +#define RVTEST_VECTOR_ENABLE \ li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | (MSTATUS_FS & (MSTATUS_FS >> 1)); \ csrs mstatus, a0; \ csrwi fcsr, 0; \ csrwi vcsr, 0; -#define RVTEST_VECTOR_ENABLE \ - li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | (MSTATUS_FS & (MSTATUS_FS >> 1)); \ +#define RVTEST_ZVE32X_ENABLE \ + li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)); \ csrs mstatus, a0; \ csrwi vcsr, 0; diff --git a/tests/riscv-test-env/p/riscv_test.h b/tests/riscv-test-env/p/riscv_test.h index 00dc5b95a..5ebdc9089 100644 --- a/tests/riscv-test-env/p/riscv_test.h +++ b/tests/riscv-test-env/p/riscv_test.h @@ -23,6 +23,11 @@ RVTEST_VECTOR_ENABLE; \ .endm +#define RVTEST_RV64UVX \ + .macro init; \ + RVTEST_ZVE32X_ENABLE; \ + .endm + #define RVTEST_RV32U \ .macro init; \ .endm @@ -37,6 +42,11 @@ RVTEST_VECTOR_ENABLE; \ .endm +#define RVTEST_RV32UVX \ + .macro init; \ + RVTEST_ZVE32X_ENABLE; \ + .endm + #define RVTEST_RV64M \ .macro init; \ RVTEST_ENABLE_MACHINE; \ diff --git a/tests/riscv-test-env/v/riscv_test.h b/tests/riscv-test-env/v/riscv_test.h index f56c0228c..e9353762a 100644 --- a/tests/riscv-test-env/v/riscv_test.h +++ b/tests/riscv-test-env/v/riscv_test.h @@ -17,6 +17,10 @@ csrwi fcsr, 0; \ csrwi vcsr, 0; +#undef RVTEST_ZVE32X_ENABLE +#define RVTEST_ZVE32X_ENABLE \ + csrwi vcsr, 0; + #undef RVTEST_CODE_BEGIN #define RVTEST_CODE_BEGIN \ .text; \ From 212d6e753fb1686d4f8999f8ea915c0d77043c20 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Thu, 26 Dec 2024 00:43:38 +0800 Subject: [PATCH 7/7] [t1rocketemu] increase sram size to 16M Signed-off-by: Avimitin --- difftest/dpi_t1rocketemu/src/interconnect.rs | 2 +- tests/t1.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/difftest/dpi_t1rocketemu/src/interconnect.rs b/difftest/dpi_t1rocketemu/src/interconnect.rs index 206d805dc..a4b0a3f74 100644 --- a/difftest/dpi_t1rocketemu/src/interconnect.rs +++ b/difftest/dpi_t1rocketemu/src/interconnect.rs @@ -201,7 +201,7 @@ pub fn create_emu_addrspace() -> (AddressSpace, ExitFlagRef) { const DDR_BASE: u32 = 0x2000_0000; const DDR_SIZE: u32 = 0xa000_0000; const SRAM_BASE: u32 = 0xc000_0000; - const SRAM_SIZE: u32 = 0x0040_0000; + const SRAM_SIZE: u32 = 0x0100_0000; const SIMCTRL_BASE: u32 = 0x1000_0000; const SIMCTRL_SIZE: u32 = 0x0000_1000; // one page diff --git a/tests/t1.ld b/tests/t1.ld index 1a8248c01..a00961b52 100644 --- a/tests/t1.ld +++ b/tests/t1.ld @@ -5,7 +5,7 @@ MEMORY { SCALAR (RWX) : ORIGIN = 0x20000000, LENGTH = 512M /* put first to set it as default */ MMIO (RW) : ORIGIN = 0x00000000, LENGTH = 512M DDR (RW) : ORIGIN = 0x40000000, LENGTH = 2048M - SRAM (RW) : ORIGIN = 0xc0000000, LENGTH = 4M /* TODO: read from config */ + SRAM (RW) : ORIGIN = 0xc0000000, LENGTH = 16M /* TODO: read from config */ } SECTIONS {