Memory reset synchronization in TETC chain

[aryd]

In the process of merging PR 277 we had one event with a discrepancy between the simulation of the TETC chain and the emulation. This was tracked down to an issue where the nentry counter in the SP memories were reset before the last processing clock in the TC was finish. This meant that the TC thought it was done processing stub pairs and hence lost the last SP. A fix was provided in which the nentries are saved locally in the TC module to not be affected by the overwriting of the nentries in the SP memory. I did not track down the source of this problem, but I wonder if it is related to the warning from the rewind pragma in the TC module that states that it can not start processing on the first clock. This would then delay the processing of the last SP and could cause this problem.