This repository has been archived by the owner on Jan 31, 2022. It is now read-only.
-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathoptohybrid_top.par
363 lines (308 loc) · 23.2 KB
/
optohybrid_top.par
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
THOMAS-LENZI-PC:: Tue Apr 21 12:32:02 2015
par -w -intstyle ise -ol high -mt 4 optohybrid_top_map.ncd optohybrid_top.ncd
optohybrid_top.pcf
Constraints file: optohybrid_top.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"optohybrid_top" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 8,546 out of 184,304 4%
Number used as Flip Flops: 8,541
Number used as Latches: 5
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,274 out of 92,152 5%
Number used as logic: 4,609 out of 92,152 5%
Number using O6 output only: 3,409
Number using O5 output only: 550
Number using O5 and O6: 650
Number used as ROM: 0
Number used as Memory: 186 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 186
Number using O6 output only: 129
Number using O5 output only: 0
Number using O5 and O6: 57
Number used exclusively as route-thrus: 479
Number with same-slice register load: 453
Number with same-slice carry load: 26
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,735 out of 23,038 11%
Number of MUXCYs used: 844 out of 46,076 1%
Number of LUT Flip Flop pairs used: 9,071
Number with an unused Flip Flop: 1,294 out of 9,071 14%
Number with an unused LUT: 3,797 out of 9,071 41%
Number of fully used LUT-FF pairs: 3,980 out of 9,071 43%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 97 out of 396 24%
Number of LOCed IOBs: 91 out of 97 93%
IOB Master Pads: 3
IOB Slave Pads: 3
Number of bonded IPADs: 16 out of 32 50%
Number of LOCed IPADs: 16 out of 16 100%
Number of bonded OPADs: 8 out of 16 50%
Number of LOCed OPADs: 8 out of 8 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 7 out of 268 2%
Number of RAMB8BWERs: 9 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 7
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 3 out of 12 25%
Number used as DCMs: 3
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 0 out of 586 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 2 out of 4 50%
Number of LOCed GTPA1_DUALs: 2 out of 2 100%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
PAR will use up to 4 processors
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
WARNING:Par:289 - The signal fpga_tx_o_OBUF has no driver. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cdce_miso_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:289 - The signal cdce_sclk_o_OBUF has no driver. PAR will not attempt to route this signal.
WARNING:Par:289 - The signal cdce_mosi_o_OBUF has no driver. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cdce_auxout_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal fpga_test_io<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal fpga_test_io<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal fpga_test_io<5>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/RESET has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_UPDATE_OUT[63].UPDATE_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<12> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<13> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<14> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<15> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<8> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<9> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<10> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<11> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/out_temp has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<4> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<5> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<6> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<7> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<0> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<1> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<2> has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal chipscope_vio_inst/U0/I_VIO/UPDATE<3> has no load. PAR will not attempt to route this signal.
Starting Multi-threaded Router
Phase 1 : 36366 unrouted; REAL time: 16 secs
Phase 2 : 30699 unrouted; REAL time: 24 secs
Phase 3 : 15021 unrouted; REAL time: 1 mins 2 secs
Phase 4 : 15020 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 8 secs
Updating file: optohybrid_top.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 30 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 30 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 30 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 30 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 30 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 32 secs
Total REAL time to Router completion: 1 mins 32 secs
Total CPU time to Router completion (all processors): 2 mins 27 secs
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| vfat2_clk | BUFGMUX_X2Y4| No | 1441 | 0.329 | 1.413 |
+---------------------+--------------+------+------+------------+-------------+
| gtp_clk | BUFGMUX_X2Y2| No | 846 | 0.397 | 1.483 |
+---------------------+--------------+------+------+------------+-------------+
| cs_icon0<0> | BUFGMUX_X2Y1| No | 153 | 0.324 | 1.410 |
+---------------------+--------------+------+------+------------+-------------+
| fpga_clk | BUFGMUX_X2Y3| No | 13 | 0.166 | 1.431 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
| _userclk2<1> | BUFGMUX_X2Y10| No | 5 | 0.010 | 1.297 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
| _userclk<1> | BUFGMUX_X2Y12| No | 4 | 0.009 | 1.296 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
| _userclk<0> | BUFGMUX_X3Y13| No | 4 | 0.010 | 1.483 |
+---------------------+--------------+------+------+------------+-------------+
|link_tracking_1_inst | | | | | |
|/vi2c_core_inst/chip | | | | | |
| _select_2 | Local| | 5 | 0.163 | 3.135 |
+---------------------+--------------+------+------+------------+-------------+
| cs_icon1<13> | Local| | 5 | 0.000 | 0.544 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
|_refclk_0_ibufds_ML_ | | | | | |
| IBUF2 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
|_refclk_1_ibufds_ML_ | | | | | |
| IBUF2 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
|_refclk_2_ibufds_ML_ | | | | | |
| IBUF2 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
|_refclk_3_ibufds_ML_ | | | | | |
| IBUF2 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
|_refclk_0_ibufds_ML_ | | | | | |
| IBUF1 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
|_refclk_1_ibufds_ML_ | | | | | |
| IBUF1 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
|_refclk_2_ibufds_ML_ | | | | | |
| IBUF1 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
|_refclk_3_ibufds_ML_ | | | | | |
| IBUF1 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
| _refclk<3> | Local| | 1 | 0.000 | 0.001 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
| _refclk<0> | Local| | 1 | 0.000 | 0.001 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
| _refclk<1> | Local| | 1 | 0.000 | 0.001 |
+---------------------+--------------+------+------+------------+-------------+
|gtp_wrapper_inst/gtp | | | | | |
| _refclk<2> | Local| | 1 | 0.000 | 0.001 |
+---------------------+--------------+------+------+------------+-------------+
|chipscope_icon_inst/ | | | | | |
| U0/iUPDATE_OUT | Local| | 1 | 0.000 | 2.134 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
Number of Timing Constraints that were not applied: 5
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_gtp_clk = PERIOD TIMEGRP "gtp_clk" 6.2 | SETUP | 0.261ns| 5.989ns| 0| 0
5 ns HIGH 50% | HOLD | 0.185ns| | 0| 0
| MINPERIOD | 0.000ns| 6.250ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_gtp_userclk00 = PERIOD TIMEGRP "gtp_us | MINPERIOD | 0.000ns| 3.125ns| 0| 0
erclk00" 3.125 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_gtp_userclk01 = PERIOD TIMEGRP "gtp_us | MINPERIOD | 0.000ns| 3.125ns| 0| 0
erclk01" 3.125 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_vfat2_clk = PERIOD TIMEGRP "vfat2_clk" | SETUP | 15.024ns| 9.976ns| 0| 0
25 ns HIGH 50% | HOLD | 0.349ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_fpga_clk = PERIOD TIMEGRP "fpga_clk" 2 | SETUP | 15.977ns| 4.023ns| 0| 0
0 ns HIGH 50% | HOLD | 0.459ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_vfat2_clk_ext = PERIOD TIMEGRP "vfat2_ | SETUP | 22.728ns| 2.272ns| 0| 0
clk_ext" 25 ns HIGH 50% | HOLD | 0.402ns| | 0| 0
| MINPERIOD | 21.876ns| 3.124ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_vfat2_clk_fpga = PERIOD TIMEGRP "vfat2 | MINPERIOD | 21.876ns| 3.124ns| 0| 0
_clk_fpga" 25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_vfat2_clk_muxed = PERIOD TIMEGRP "vfat | MINPERIOD | 21.876ns| 3.124ns| 0| 0
2_clk_muxed" 25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cdce_clk_muxed = PERIOD TIMEGRP "cdce_ | N/A | N/A| N/A| N/A| N/A
clk_muxed" 25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 34 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:284 - There are 3 sourceless signals in this design. This design will not pass the DRC check run by Bitgen.
Total REAL time to PAR completion: 1 mins 38 secs
Total CPU time to PAR completion (all processors): 2 mins 32 secs
Peak Memory Usage: 658 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 41
Number of info messages: 1
Writing design to file optohybrid_top.ncd
PAR done!