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--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml optohybrid_top.twx optohybrid_top.ncd -o
optohybrid_top.twr optohybrid_top.pcf
Design file: optohybrid_top.ncd
Physical constraint file: optohybrid_top.pcf
Device,package,speed: xc6slx150t,fgg676,C,-3 (PRODUCTION 1.23 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_fpga_clk = PERIOD TIMEGRP "fpga_clk" 20 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
422 paths analyzed, 94 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 4.023ns.
--------------------------------------------------------------------------------
Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/counter_0 (SLICE_X62Y135.CE), 12 paths
--------------------------------------------------------------------------------
Slack (setup path): 15.977ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 (FF)
Requirement: 20.000ns
Data Path Delay: 3.888ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 to gtp_wrapper_inst/gtp_link_reset_inst/counter_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y135.BQ Tcko 0.408 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_1
SLICE_X63Y136.D1 net (fanout=2) 0.763 gtp_wrapper_inst/gtp_link_reset_inst/counter<1>
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.335 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_0
------------------------------------------------- ---------------------------
Total 3.888ns (1.520ns logic, 2.368ns route)
(39.1% logic, 60.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 16.155ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/state_0 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 (FF)
Requirement: 20.000ns
Data Path Delay: 3.696ns (Levels of Logic = 3)
Clock Path Skew: -0.014ns (0.232 - 0.246)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/state_0 to gtp_wrapper_inst/gtp_link_reset_inst/counter_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X63Y136.BMUX Tshcko 0.461 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/state_0
SLICE_X63Y136.D6 net (fanout=3) 0.518 gtp_wrapper_inst/gtp_link_reset_inst/state_0
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.335 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_0
------------------------------------------------- ---------------------------
Total 3.696ns (1.573ns logic, 2.123ns route)
(42.6% logic, 57.4% route)
--------------------------------------------------------------------------------
Slack (setup path): 16.230ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 (FF)
Requirement: 20.000ns
Data Path Delay: 3.635ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 to gtp_wrapper_inst/gtp_link_reset_inst/counter_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y135.AQ Tcko 0.408 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_0
SLICE_X63Y136.D3 net (fanout=2) 0.510 gtp_wrapper_inst/gtp_link_reset_inst/counter<0>
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.335 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_0
------------------------------------------------- ---------------------------
Total 3.635ns (1.520ns logic, 2.115ns route)
(41.8% logic, 58.2% route)
--------------------------------------------------------------------------------
Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/counter_3 (SLICE_X62Y135.CE), 12 paths
--------------------------------------------------------------------------------
Slack (setup path): 15.997ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_3 (FF)
Requirement: 20.000ns
Data Path Delay: 3.868ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 to gtp_wrapper_inst/gtp_link_reset_inst/counter_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y135.BQ Tcko 0.408 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_1
SLICE_X63Y136.D1 net (fanout=2) 0.763 gtp_wrapper_inst/gtp_link_reset_inst/counter<1>
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.315 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_3
------------------------------------------------- ---------------------------
Total 3.868ns (1.500ns logic, 2.368ns route)
(38.8% logic, 61.2% route)
--------------------------------------------------------------------------------
Slack (setup path): 16.175ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/state_0 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_3 (FF)
Requirement: 20.000ns
Data Path Delay: 3.676ns (Levels of Logic = 3)
Clock Path Skew: -0.014ns (0.232 - 0.246)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/state_0 to gtp_wrapper_inst/gtp_link_reset_inst/counter_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X63Y136.BMUX Tshcko 0.461 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/state_0
SLICE_X63Y136.D6 net (fanout=3) 0.518 gtp_wrapper_inst/gtp_link_reset_inst/state_0
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.315 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_3
------------------------------------------------- ---------------------------
Total 3.676ns (1.553ns logic, 2.123ns route)
(42.2% logic, 57.8% route)
--------------------------------------------------------------------------------
Slack (setup path): 16.250ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_3 (FF)
Requirement: 20.000ns
Data Path Delay: 3.615ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 to gtp_wrapper_inst/gtp_link_reset_inst/counter_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y135.AQ Tcko 0.408 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_0
SLICE_X63Y136.D3 net (fanout=2) 0.510 gtp_wrapper_inst/gtp_link_reset_inst/counter<0>
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.315 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_3
------------------------------------------------- ---------------------------
Total 3.615ns (1.500ns logic, 2.115ns route)
(41.5% logic, 58.5% route)
--------------------------------------------------------------------------------
Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/counter_2 (SLICE_X62Y135.CE), 12 paths
--------------------------------------------------------------------------------
Slack (setup path): 15.998ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_2 (FF)
Requirement: 20.000ns
Data Path Delay: 3.867ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 to gtp_wrapper_inst/gtp_link_reset_inst/counter_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y135.BQ Tcko 0.408 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_1
SLICE_X63Y136.D1 net (fanout=2) 0.763 gtp_wrapper_inst/gtp_link_reset_inst/counter<1>
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.314 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_2
------------------------------------------------- ---------------------------
Total 3.867ns (1.499ns logic, 2.368ns route)
(38.8% logic, 61.2% route)
--------------------------------------------------------------------------------
Slack (setup path): 16.176ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/state_0 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_2 (FF)
Requirement: 20.000ns
Data Path Delay: 3.675ns (Levels of Logic = 3)
Clock Path Skew: -0.014ns (0.232 - 0.246)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/state_0 to gtp_wrapper_inst/gtp_link_reset_inst/counter_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X63Y136.BMUX Tshcko 0.461 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/state_0
SLICE_X63Y136.D6 net (fanout=3) 0.518 gtp_wrapper_inst/gtp_link_reset_inst/state_0
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.314 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_2
------------------------------------------------- ---------------------------
Total 3.675ns (1.552ns logic, 2.123ns route)
(42.2% logic, 57.8% route)
--------------------------------------------------------------------------------
Slack (setup path): 16.251ns (requirement - (data path - clock path skew + uncertainty))
Source: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_2 (FF)
Requirement: 20.000ns
Data Path Delay: 3.614ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/counter_0 to gtp_wrapper_inst/gtp_link_reset_inst/counter_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y135.AQ Tcko 0.408 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_0
SLICE_X63Y136.D3 net (fanout=2) 0.510 gtp_wrapper_inst/gtp_link_reset_inst/counter<0>
SLICE_X63Y136.D Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0
SLICE_X63Y136.A3 net (fanout=1) 0.291 gtp_wrapper_inst/gtp_link_reset_inst/N0
SLICE_X63Y136.A Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B3 net (fanout=1) 0.831 gtp_wrapper_inst/gtp_link_reset_inst/_n0018
SLICE_X63Y136.B Tilo 0.259 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1
SLICE_X62Y135.CE net (fanout=3) 0.483 gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv
SLICE_X62Y135.CLK Tceck 0.314 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_2
------------------------------------------------- ---------------------------
Total 3.614ns (1.499ns logic, 2.115ns route)
(41.5% logic, 58.5% route)
--------------------------------------------------------------------------------
Hold Paths: TS_fpga_clk = PERIOD TIMEGRP "fpga_clk" 20 ns HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point clock_control_inst/cdce_count_11 (SLICE_X38Y78.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.459ns (requirement - (clock path skew + uncertainty - data path))
Source: clock_control_inst/cdce_count_11 (FF)
Destination: clock_control_inst/cdce_count_11 (FF)
Requirement: 0.000ns
Data Path Delay: 0.459ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 20.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: clock_control_inst/cdce_count_11 to clock_control_inst/cdce_count_11
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y78.DQ Tcko 0.200 clock_control_inst/cdce_count<11>
clock_control_inst/cdce_count_11
SLICE_X38Y78.D6 net (fanout=2) 0.022 clock_control_inst/cdce_count<11>
SLICE_X38Y78.CLK Tah (-Th) -0.237 clock_control_inst/cdce_count<11>
clock_control_inst/cdce_count<11>_rt
clock_control_inst/Mcount_cdce_count_xor<11>
clock_control_inst/cdce_count_11
------------------------------------------------- ---------------------------
Total 0.459ns (0.437ns logic, 0.022ns route)
(95.2% logic, 4.8% route)
--------------------------------------------------------------------------------
Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/reset_o (SLICE_X63Y136.C6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.488ns (requirement - (clock path skew + uncertainty - data path))
Source: gtp_wrapper_inst/gtp_link_reset_inst/state_0 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/reset_o (FF)
Requirement: 0.000ns
Data Path Delay: 0.488ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 20.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/state_0 to gtp_wrapper_inst/gtp_link_reset_inst/reset_o
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X63Y136.BMUX Tshcko 0.244 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/state_0
SLICE_X63Y136.C6 net (fanout=3) 0.029 gtp_wrapper_inst/gtp_link_reset_inst/state_0
SLICE_X63Y136.CLK Tah (-Th) -0.215 gtp_wrapper_inst/local_reset
gtp_wrapper_inst/gtp_link_reset_inst/reset_o_rstpot1_INV_0
gtp_wrapper_inst/gtp_link_reset_inst/reset_o
------------------------------------------------- ---------------------------
Total 0.488ns (0.459ns logic, 0.029ns route)
(94.1% logic, 5.9% route)
--------------------------------------------------------------------------------
Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/counter_1 (SLICE_X62Y135.B5), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.509ns (requirement - (clock path skew + uncertainty - data path))
Source: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 (FF)
Destination: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 (FF)
Requirement: 0.000ns
Data Path Delay: 0.509ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 20.000ns
Destination Clock: fpga_clk rising at 20.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: gtp_wrapper_inst/gtp_link_reset_inst/counter_1 to gtp_wrapper_inst/gtp_link_reset_inst/counter_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y135.BQ Tcko 0.200 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_1
SLICE_X62Y135.B5 net (fanout=2) 0.075 gtp_wrapper_inst/gtp_link_reset_inst/counter<1>
SLICE_X62Y135.CLK Tah (-Th) -0.234 gtp_wrapper_inst/gtp_link_reset_inst/counter<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter<1>_rt
gtp_wrapper_inst/gtp_link_reset_inst/Mcount_counter_cy<3>
gtp_wrapper_inst/gtp_link_reset_inst/counter_1
------------------------------------------------- ---------------------------
Total 0.509ns (0.434ns logic, 0.075ns route)
(85.3% logic, 14.7% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_fpga_clk = PERIOD TIMEGRP "fpga_clk" 20 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 19.570ns (period - min period limit)
Period: 20.000ns
Min period limit: 0.430ns (2325.581MHz) (Tcp)
Physical resource: gtp_wrapper_inst/gtp_link_reset_inst/counter<3>/CLK
Logical resource: gtp_wrapper_inst/gtp_link_reset_inst/counter_0/CK
Location pin: SLICE_X62Y135.CLK
Clock network: fpga_clk
--------------------------------------------------------------------------------
Slack: 19.570ns (period - min period limit)
Period: 20.000ns
Min period limit: 0.430ns (2325.581MHz) (Tcp)
Physical resource: gtp_wrapper_inst/gtp_link_reset_inst/counter<3>/CLK
Logical resource: gtp_wrapper_inst/gtp_link_reset_inst/counter_1/CK
Location pin: SLICE_X62Y135.CLK
Clock network: fpga_clk
--------------------------------------------------------------------------------
Slack: 19.570ns (period - min period limit)
Period: 20.000ns
Min period limit: 0.430ns (2325.581MHz) (Tcp)
Physical resource: gtp_wrapper_inst/gtp_link_reset_inst/counter<3>/CLK
Logical resource: gtp_wrapper_inst/gtp_link_reset_inst/counter_2/CK
Location pin: SLICE_X62Y135.CLK
Clock network: fpga_clk
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_vfat2_clk_ext = PERIOD TIMEGRP "vfat2_clk_ext" 25 ns HIGH
50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
36 paths analyzed, 26 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 3.124ns.
--------------------------------------------------------------------------------
Paths for end point clock_control_inst/vfat2_count_4 (SLICE_X38Y48.B2), 4 paths
--------------------------------------------------------------------------------
Slack (setup path): 22.728ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_3 (FF)
Destination: clock_control_inst/vfat2_count_4 (FF)
Requirement: 25.000ns
Data Path Delay: 2.129ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_3 to clock_control_inst/vfat2_count_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.CQ Tcko 0.408 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_3
SLICE_X38Y48.A3 net (fanout=2) 0.465 clock_control_inst/vfat2_count<3>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.B2 net (fanout=3) 0.710 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.341 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>11
clock_control_inst/vfat2_count_4
------------------------------------------------- ---------------------------
Total 2.129ns (0.954ns logic, 1.175ns route)
(44.8% logic, 55.2% route)
--------------------------------------------------------------------------------
Slack (setup path): 22.781ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_1 (FF)
Destination: clock_control_inst/vfat2_count_4 (FF)
Requirement: 25.000ns
Data Path Delay: 2.076ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_1 to clock_control_inst/vfat2_count_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.BQ Tcko 0.408 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_1
SLICE_X38Y48.A4 net (fanout=3) 0.412 clock_control_inst/vfat2_count<1>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.B2 net (fanout=3) 0.710 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.341 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>11
clock_control_inst/vfat2_count_4
------------------------------------------------- ---------------------------
Total 2.076ns (0.954ns logic, 1.122ns route)
(46.0% logic, 54.0% route)
--------------------------------------------------------------------------------
Slack (setup path): 22.828ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_2 (FF)
Destination: clock_control_inst/vfat2_count_4 (FF)
Requirement: 25.000ns
Data Path Delay: 2.029ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_2 to clock_control_inst/vfat2_count_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.BMUX Tshcko 0.455 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_2
SLICE_X38Y48.A6 net (fanout=3) 0.318 clock_control_inst/vfat2_count<2>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.B2 net (fanout=3) 0.710 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.341 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>11
clock_control_inst/vfat2_count_4
------------------------------------------------- ---------------------------
Total 2.029ns (1.001ns logic, 1.028ns route)
(49.3% logic, 50.7% route)
--------------------------------------------------------------------------------
Paths for end point clock_control_inst/vfat2_count_5 (SLICE_X38Y48.B2), 4 paths
--------------------------------------------------------------------------------
Slack (setup path): 22.856ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_3 (FF)
Destination: clock_control_inst/vfat2_count_5 (FF)
Requirement: 25.000ns
Data Path Delay: 2.001ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_3 to clock_control_inst/vfat2_count_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.CQ Tcko 0.408 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_3
SLICE_X38Y48.A3 net (fanout=2) 0.465 clock_control_inst/vfat2_count<3>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.B2 net (fanout=3) 0.710 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.213 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<5>11
clock_control_inst/vfat2_count_5
------------------------------------------------- ---------------------------
Total 2.001ns (0.826ns logic, 1.175ns route)
(41.3% logic, 58.7% route)
--------------------------------------------------------------------------------
Slack (setup path): 22.909ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_1 (FF)
Destination: clock_control_inst/vfat2_count_5 (FF)
Requirement: 25.000ns
Data Path Delay: 1.948ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_1 to clock_control_inst/vfat2_count_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.BQ Tcko 0.408 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_1
SLICE_X38Y48.A4 net (fanout=3) 0.412 clock_control_inst/vfat2_count<1>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.B2 net (fanout=3) 0.710 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.213 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<5>11
clock_control_inst/vfat2_count_5
------------------------------------------------- ---------------------------
Total 1.948ns (0.826ns logic, 1.122ns route)
(42.4% logic, 57.6% route)
--------------------------------------------------------------------------------
Slack (setup path): 22.956ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_2 (FF)
Destination: clock_control_inst/vfat2_count_5 (FF)
Requirement: 25.000ns
Data Path Delay: 1.901ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_2 to clock_control_inst/vfat2_count_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.BMUX Tshcko 0.455 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_2
SLICE_X38Y48.A6 net (fanout=3) 0.318 clock_control_inst/vfat2_count<2>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.B2 net (fanout=3) 0.710 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.213 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<5>11
clock_control_inst/vfat2_count_5
------------------------------------------------- ---------------------------
Total 1.901ns (0.873ns logic, 1.028ns route)
(45.9% logic, 54.1% route)
--------------------------------------------------------------------------------
Paths for end point clock_control_inst/vfat2_count_6 (SLICE_X38Y48.C1), 4 paths
--------------------------------------------------------------------------------
Slack (setup path): 22.987ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_3 (FF)
Destination: clock_control_inst/vfat2_count_6 (FF)
Requirement: 25.000ns
Data Path Delay: 1.870ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_3 to clock_control_inst/vfat2_count_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.CQ Tcko 0.408 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_3
SLICE_X38Y48.A3 net (fanout=2) 0.465 clock_control_inst/vfat2_count<3>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.C1 net (fanout=3) 0.451 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.341 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<6>11
clock_control_inst/vfat2_count_6
------------------------------------------------- ---------------------------
Total 1.870ns (0.954ns logic, 0.916ns route)
(51.0% logic, 49.0% route)
--------------------------------------------------------------------------------
Slack (setup path): 23.040ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_1 (FF)
Destination: clock_control_inst/vfat2_count_6 (FF)
Requirement: 25.000ns
Data Path Delay: 1.817ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_1 to clock_control_inst/vfat2_count_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.BQ Tcko 0.408 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_1
SLICE_X38Y48.A4 net (fanout=3) 0.412 clock_control_inst/vfat2_count<1>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.C1 net (fanout=3) 0.451 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.341 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<6>11
clock_control_inst/vfat2_count_6
------------------------------------------------- ---------------------------
Total 1.817ns (0.954ns logic, 0.863ns route)
(52.5% logic, 47.5% route)
--------------------------------------------------------------------------------
Slack (setup path): 23.087ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control_inst/vfat2_count_2 (FF)
Destination: clock_control_inst/vfat2_count_6 (FF)
Requirement: 25.000ns
Data Path Delay: 1.770ns (Levels of Logic = 2)
Clock Path Skew: -0.008ns (0.155 - 0.163)
Source Clock: fpga_clk rising at 0.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.200ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: clock_control_inst/vfat2_count_2 to clock_control_inst/vfat2_count_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.BMUX Tshcko 0.455 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_2
SLICE_X38Y48.A6 net (fanout=3) 0.318 clock_control_inst/vfat2_count<2>
SLICE_X38Y48.A Tilo 0.205 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<4>111
SLICE_X38Y48.C1 net (fanout=3) 0.451 clock_control_inst/Mcount_vfat2_count_xor<4>11
SLICE_X38Y48.CLK Tas 0.341 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<6>11
clock_control_inst/vfat2_count_6
------------------------------------------------- ---------------------------
Total 1.770ns (1.001ns logic, 0.769ns route)
(56.6% logic, 43.4% route)
--------------------------------------------------------------------------------
Hold Paths: TS_vfat2_clk_ext = PERIOD TIMEGRP "vfat2_clk_ext" 25 ns HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point clock_control_inst/vfat2_count_2 (SLICE_X38Y49.B5), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.402ns (requirement - (clock path skew + uncertainty - data path))
Source: clock_control_inst/vfat2_count_1 (FF)
Destination: clock_control_inst/vfat2_count_2 (FF)
Requirement: 0.000ns
Data Path Delay: 0.402ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 25.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: clock_control_inst/vfat2_count_1 to clock_control_inst/vfat2_count_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.BQ Tcko 0.200 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_1
SLICE_X38Y49.B5 net (fanout=3) 0.081 clock_control_inst/vfat2_count<1>
SLICE_X38Y49.CLK Tah (-Th) -0.121 clock_control_inst/vfat2_count<3>
clock_control_inst/Mcount_vfat2_count_xor<2>11
clock_control_inst/vfat2_count_2
------------------------------------------------- ---------------------------
Total 0.402ns (0.321ns logic, 0.081ns route)
(79.9% logic, 20.1% route)
--------------------------------------------------------------------------------
Paths for end point clock_control_inst/vfat2_count_3 (SLICE_X38Y49.C6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.459ns (requirement - (clock path skew + uncertainty - data path))
Source: clock_control_inst/vfat2_count_2 (FF)
Destination: clock_control_inst/vfat2_count_3 (FF)
Requirement: 0.000ns
Data Path Delay: 0.459ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 25.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: clock_control_inst/vfat2_count_2 to clock_control_inst/vfat2_count_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y49.BMUX Tshcko 0.238 clock_control_inst/vfat2_count<3>
clock_control_inst/vfat2_count_2
SLICE_X38Y49.C6 net (fanout=3) 0.031 clock_control_inst/vfat2_count<2>
SLICE_X38Y49.CLK Tah (-Th) -0.190 clock_control_inst/vfat2_count<3>
clock_control_inst/Mcount_vfat2_count_xor<3>11
clock_control_inst/vfat2_count_3
------------------------------------------------- ---------------------------
Total 0.459ns (0.428ns logic, 0.031ns route)
(93.2% logic, 6.8% route)
--------------------------------------------------------------------------------
Paths for end point clock_control_inst/vfat2_count_6 (SLICE_X38Y48.C6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.462ns (requirement - (clock path skew + uncertainty - data path))
Source: clock_control_inst/vfat2_count_5 (FF)
Destination: clock_control_inst/vfat2_count_6 (FF)
Requirement: 0.000ns
Data Path Delay: 0.462ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: fpga_clk rising at 25.000ns
Destination Clock: fpga_clk rising at 25.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: clock_control_inst/vfat2_count_5 to clock_control_inst/vfat2_count_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y48.BMUX Tshcko 0.238 clock_control_inst/vfat2_count<6>
clock_control_inst/vfat2_count_5
SLICE_X38Y48.C6 net (fanout=3) 0.034 clock_control_inst/vfat2_count<5>
SLICE_X38Y48.CLK Tah (-Th) -0.190 clock_control_inst/vfat2_count<6>
clock_control_inst/Mcount_vfat2_count_xor<6>11
clock_control_inst/vfat2_count_6
------------------------------------------------- ---------------------------
Total 0.462ns (0.428ns logic, 0.034ns route)
(92.6% logic, 7.4% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_vfat2_clk_ext = PERIOD TIMEGRP "vfat2_clk_ext" 25 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 21.876ns (period - min period limit)
Period: 25.000ns
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Logical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Location pin: RAMB8_X3Y42.CLKAWRCLK
Clock network: vfat2_clk
--------------------------------------------------------------------------------
Slack: 21.876ns (period - min period limit)
Period: 25.000ns
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Logical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Location pin: RAMB8_X3Y49.CLKAWRCLK
Clock network: vfat2_clk
--------------------------------------------------------------------------------
Slack: 21.876ns (period - min period limit)
Period: 25.000ns
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Logical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Location pin: RAMB8_X3Y32.CLKAWRCLK
Clock network: vfat2_clk
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_vfat2_clk_fpga = PERIOD TIMEGRP "vfat2_clk_fpga" 25 ns
HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 3.124ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_vfat2_clk_fpga = PERIOD TIMEGRP "vfat2_clk_fpga" 25 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 21.876ns (period - min period limit)
Period: 25.000ns
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Logical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Location pin: RAMB8_X3Y42.CLKAWRCLK
Clock network: vfat2_clk
--------------------------------------------------------------------------------
Slack: 21.876ns (period - min period limit)
Period: 25.000ns
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Logical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Location pin: RAMB8_X3Y49.CLKAWRCLK
Clock network: vfat2_clk
--------------------------------------------------------------------------------
Slack: 21.876ns (period - min period limit)
Period: 25.000ns
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Logical resource: link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Location pin: RAMB8_X3Y32.CLKAWRCLK
Clock network: vfat2_clk
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_vfat2_clk_muxed = PERIOD TIMEGRP "vfat2_clk_muxed" 25 ns
HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 3.124ns.
--------------------------------------------------------------------------------