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optohybrid_top.twx
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml optohybrid_top.twx optohybrid_top.ncd -o
optohybrid_top.twr optohybrid_top.pcf
</twCmdLine><twDesign>optohybrid_top.ncd</twDesign><twDesignPath>optohybrid_top.ncd</twDesignPath><twPCF>optohybrid_top.pcf</twPCF><twPcfPath>optohybrid_top.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg676"><twDevName>xc6slx150t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="6" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_fpga_clk = PERIOD TIMEGRP "fpga_clk" 20 ns HIGH 50%;</twConstName><twItemCnt>422</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>94</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>4.023</twMinPer></twConstHead><twPathRptBanner iPaths="12" iCriticalPaths="0" sType="EndPoint">Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/counter_0 (SLICE_X62Y135.CE), 12 paths
</twPathRptBanner><twPathRpt anchorID="7"><twConstPath anchorID="8" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.977</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twDest><twTotPathDel>3.888</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X62Y135.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X62Y135.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<1></twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twBEL></twPathDel><twLogDel>1.520</twLogDel><twRouteDel>2.368</twRouteDel><twTotDel>3.888</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>39.1</twPctLog><twPctRoute>60.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="9"><twConstPath anchorID="10" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.155</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/state_0</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twDest><twTotPathDel>3.696</twTotPathDel><twClkSkew dest = "0.232" src = "0.246">0.014</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X63Y136.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X63Y136.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.461</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.518</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twBEL></twPathDel><twLogDel>1.573</twLogDel><twRouteDel>2.123</twRouteDel><twTotDel>3.696</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>42.6</twPctLog><twPctRoute>57.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="11"><twConstPath anchorID="12" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.230</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twDest><twTotPathDel>3.635</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X62Y135.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X62Y135.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.510</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<0></twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twBEL></twPathDel><twLogDel>1.520</twLogDel><twRouteDel>2.115</twRouteDel><twTotDel>3.635</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>41.8</twPctLog><twPctRoute>58.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="12" iCriticalPaths="0" sType="EndPoint">Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/counter_3 (SLICE_X62Y135.CE), 12 paths
</twPathRptBanner><twPathRpt anchorID="13"><twConstPath anchorID="14" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.997</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twDest><twTotPathDel>3.868</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X62Y135.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X62Y135.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<1></twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.315</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twBEL></twPathDel><twLogDel>1.500</twLogDel><twRouteDel>2.368</twRouteDel><twTotDel>3.868</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>38.8</twPctLog><twPctRoute>61.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="15"><twConstPath anchorID="16" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.175</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/state_0</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twDest><twTotPathDel>3.676</twTotPathDel><twClkSkew dest = "0.232" src = "0.246">0.014</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X63Y136.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X63Y136.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.461</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.518</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.315</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twBEL></twPathDel><twLogDel>1.553</twLogDel><twRouteDel>2.123</twRouteDel><twTotDel>3.676</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>42.2</twPctLog><twPctRoute>57.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="17"><twConstPath anchorID="18" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.250</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twDest><twTotPathDel>3.615</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X62Y135.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X62Y135.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.510</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<0></twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.315</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_3</twBEL></twPathDel><twLogDel>1.500</twLogDel><twRouteDel>2.115</twRouteDel><twTotDel>3.615</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>41.5</twPctLog><twPctRoute>58.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="12" iCriticalPaths="0" sType="EndPoint">Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/counter_2 (SLICE_X62Y135.CE), 12 paths
</twPathRptBanner><twPathRpt anchorID="19"><twConstPath anchorID="20" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.998</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twDest><twTotPathDel>3.867</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X62Y135.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X62Y135.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<1></twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.314</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twBEL></twPathDel><twLogDel>1.499</twLogDel><twRouteDel>2.368</twRouteDel><twTotDel>3.867</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>38.8</twPctLog><twPctRoute>61.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="21"><twConstPath anchorID="22" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.176</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/state_0</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twDest><twTotPathDel>3.675</twTotPathDel><twClkSkew dest = "0.232" src = "0.246">0.014</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X63Y136.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X63Y136.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.461</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.518</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.314</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twBEL></twPathDel><twLogDel>1.552</twLogDel><twRouteDel>2.123</twRouteDel><twTotDel>3.675</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>42.2</twPctLog><twPctRoute>57.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="23"><twConstPath anchorID="24" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.251</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twDest><twTotPathDel>3.614</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X62Y135.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X62Y135.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.D3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.510</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<0></twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/N0</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.831</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0018</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y136.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.CE</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/_n0021_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.314</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_2</twBEL></twPathDel><twLogDel>1.499</twLogDel><twRouteDel>2.115</twRouteDel><twTotDel>3.614</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>41.5</twPctLog><twPctRoute>58.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_fpga_clk = PERIOD TIMEGRP "fpga_clk" 20 ns HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point clock_control_inst/cdce_count_11 (SLICE_X38Y78.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.459</twSlack><twSrc BELType="FF">clock_control_inst/cdce_count_11</twSrc><twDest BELType="FF">clock_control_inst/cdce_count_11</twDest><twTotPathDel>0.459</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>clock_control_inst/cdce_count_11</twSrc><twDest BELType='FF'>clock_control_inst/cdce_count_11</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X38Y78.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y78.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>clock_control_inst/cdce_count<11></twComp><twBEL>clock_control_inst/cdce_count_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y78.D6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.022</twDelInfo><twComp>clock_control_inst/cdce_count<11></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X38Y78.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.237</twDelInfo><twComp>clock_control_inst/cdce_count<11></twComp><twBEL>clock_control_inst/cdce_count<11>_rt</twBEL><twBEL>clock_control_inst/Mcount_cdce_count_xor<11></twBEL><twBEL>clock_control_inst/cdce_count_11</twBEL></twPathDel><twLogDel>0.437</twLogDel><twRouteDel>0.022</twRouteDel><twTotDel>0.459</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>95.2</twPctLog><twPctRoute>4.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/reset_o (SLICE_X63Y136.C6), 1 path
</twPathRptBanner><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.488</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/state_0</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/reset_o</twDest><twTotPathDel>0.488</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/reset_o</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X63Y136.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X63Y136.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twFalling">0.244</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y136.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.029</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/state_0</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X63Y136.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>gtp_wrapper_inst/local_reset</twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/reset_o_rstpot1_INV_0</twBEL><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/reset_o</twBEL></twPathDel><twLogDel>0.459</twLogDel><twRouteDel>0.029</twRouteDel><twTotDel>0.488</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>94.1</twPctLog><twPctRoute>5.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point gtp_wrapper_inst/gtp_link_reset_inst/counter_1 (SLICE_X62Y135.B5), 1 path
</twPathRptBanner><twPathRpt anchorID="29"><twConstPath anchorID="30" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.509</twSlack><twSrc BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twSrc><twDest BELType="FF">gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twDest><twTotPathDel>0.509</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twSrc><twDest BELType='FF'>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X62Y135.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X62Y135.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y135.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.075</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<1></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X62Y135.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>gtp_wrapper_inst/gtp_link_reset_inst/counter<3></twComp><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter<1>_rt</twBEL><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/Mcount_counter_cy<3></twBEL><twBEL>gtp_wrapper_inst/gtp_link_reset_inst/counter_1</twBEL></twPathDel><twLogDel>0.434</twLogDel><twRouteDel>0.075</twRouteDel><twTotDel>0.509</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_clk</twDestClk><twPctLog>85.3</twPctLog><twPctRoute>14.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="31"><twPinLimitBanner>Component Switching Limit Checks: TS_fpga_clk = PERIOD TIMEGRP "fpga_clk" 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="32" type="MINPERIOD" name="Tcp" slack="19.570" period="20.000" constraintValue="20.000" deviceLimit="0.430" freqLimit="2325.581" physResource="gtp_wrapper_inst/gtp_link_reset_inst/counter<3>/CLK" logResource="gtp_wrapper_inst/gtp_link_reset_inst/counter_0/CK" locationPin="SLICE_X62Y135.CLK" clockNet="fpga_clk"/><twPinLimit anchorID="33" type="MINPERIOD" name="Tcp" slack="19.570" period="20.000" constraintValue="20.000" deviceLimit="0.430" freqLimit="2325.581" physResource="gtp_wrapper_inst/gtp_link_reset_inst/counter<3>/CLK" logResource="gtp_wrapper_inst/gtp_link_reset_inst/counter_1/CK" locationPin="SLICE_X62Y135.CLK" clockNet="fpga_clk"/><twPinLimit anchorID="34" type="MINPERIOD" name="Tcp" slack="19.570" period="20.000" constraintValue="20.000" deviceLimit="0.430" freqLimit="2325.581" physResource="gtp_wrapper_inst/gtp_link_reset_inst/counter<3>/CLK" logResource="gtp_wrapper_inst/gtp_link_reset_inst/counter_2/CK" locationPin="SLICE_X62Y135.CLK" clockNet="fpga_clk"/></twPinLimitRpt></twConst><twConst anchorID="35" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_vfat2_clk_ext = PERIOD TIMEGRP "vfat2_clk_ext" 25 ns HIGH 50%;</twConstName><twItemCnt>36</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>26</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.124</twMinPer></twConstHead><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point clock_control_inst/vfat2_count_4 (SLICE_X38Y48.B2), 4 paths
</twPathRptBanner><twPathRpt anchorID="36"><twConstPath anchorID="37" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>22.728</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_3</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_4</twDest><twTotPathDel>2.129</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_3</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_4</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.465</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.B2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.710</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.341</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>11</twBEL><twBEL>clock_control_inst/vfat2_count_4</twBEL></twPathDel><twLogDel>0.954</twLogDel><twRouteDel>1.175</twRouteDel><twTotDel>2.129</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>44.8</twPctLog><twPctRoute>55.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="38"><twConstPath anchorID="39" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>22.781</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_1</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_4</twDest><twTotPathDel>2.076</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_1</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_4</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.412</twDelInfo><twComp>clock_control_inst/vfat2_count<1></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.B2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.710</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.341</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>11</twBEL><twBEL>clock_control_inst/vfat2_count_4</twBEL></twPathDel><twLogDel>0.954</twLogDel><twRouteDel>1.122</twRouteDel><twTotDel>2.076</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>46.0</twPctLog><twPctRoute>54.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="40"><twConstPath anchorID="41" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>22.828</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_2</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_4</twDest><twTotPathDel>2.029</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_2</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_4</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.455</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.318</twDelInfo><twComp>clock_control_inst/vfat2_count<2></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.B2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.710</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.341</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>11</twBEL><twBEL>clock_control_inst/vfat2_count_4</twBEL></twPathDel><twLogDel>1.001</twLogDel><twRouteDel>1.028</twRouteDel><twTotDel>2.029</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>49.3</twPctLog><twPctRoute>50.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point clock_control_inst/vfat2_count_5 (SLICE_X38Y48.B2), 4 paths
</twPathRptBanner><twPathRpt anchorID="42"><twConstPath anchorID="43" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>22.856</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_3</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_5</twDest><twTotPathDel>2.001</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_3</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_5</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.465</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.B2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.710</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.213</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<5>11</twBEL><twBEL>clock_control_inst/vfat2_count_5</twBEL></twPathDel><twLogDel>0.826</twLogDel><twRouteDel>1.175</twRouteDel><twTotDel>2.001</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>41.3</twPctLog><twPctRoute>58.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="44"><twConstPath anchorID="45" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>22.909</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_1</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_5</twDest><twTotPathDel>1.948</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_1</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_5</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.412</twDelInfo><twComp>clock_control_inst/vfat2_count<1></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.B2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.710</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.213</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<5>11</twBEL><twBEL>clock_control_inst/vfat2_count_5</twBEL></twPathDel><twLogDel>0.826</twLogDel><twRouteDel>1.122</twRouteDel><twTotDel>1.948</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>42.4</twPctLog><twPctRoute>57.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="46"><twConstPath anchorID="47" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>22.956</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_2</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_5</twDest><twTotPathDel>1.901</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_2</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_5</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.455</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.318</twDelInfo><twComp>clock_control_inst/vfat2_count<2></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.B2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.710</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.213</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<5>11</twBEL><twBEL>clock_control_inst/vfat2_count_5</twBEL></twPathDel><twLogDel>0.873</twLogDel><twRouteDel>1.028</twRouteDel><twTotDel>1.901</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>45.9</twPctLog><twPctRoute>54.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point clock_control_inst/vfat2_count_6 (SLICE_X38Y48.C1), 4 paths
</twPathRptBanner><twPathRpt anchorID="48"><twConstPath anchorID="49" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>22.987</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_3</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_6</twDest><twTotPathDel>1.870</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_3</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_6</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.465</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.C1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.451</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.341</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<6>11</twBEL><twBEL>clock_control_inst/vfat2_count_6</twBEL></twPathDel><twLogDel>0.954</twLogDel><twRouteDel>0.916</twRouteDel><twTotDel>1.870</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>51.0</twPctLog><twPctRoute>49.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="50"><twConstPath anchorID="51" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>23.040</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_1</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_6</twDest><twTotPathDel>1.817</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_1</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_6</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.412</twDelInfo><twComp>clock_control_inst/vfat2_count<1></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.C1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.451</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.341</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<6>11</twBEL><twBEL>clock_control_inst/vfat2_count_6</twBEL></twPathDel><twLogDel>0.954</twLogDel><twRouteDel>0.863</twRouteDel><twTotDel>1.817</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>52.5</twPctLog><twPctRoute>47.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="52"><twConstPath anchorID="53" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>23.087</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_2</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_6</twDest><twTotPathDel>1.770</twTotPathDel><twClkSkew dest = "0.155" src = "0.163">0.008</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_2</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_6</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.455</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.A6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.318</twDelInfo><twComp>clock_control_inst/vfat2_count<2></twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<4>111</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.C1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.451</twDelInfo><twComp>clock_control_inst/Mcount_vfat2_count_xor<4>11</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.341</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<6>11</twBEL><twBEL>clock_control_inst/vfat2_count_6</twBEL></twPathDel><twLogDel>1.001</twLogDel><twRouteDel>0.769</twRouteDel><twTotDel>1.770</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>56.6</twPctLog><twPctRoute>43.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_vfat2_clk_ext = PERIOD TIMEGRP "vfat2_clk_ext" 25 ns HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point clock_control_inst/vfat2_count_2 (SLICE_X38Y49.B5), 1 path
</twPathRptBanner><twPathRpt anchorID="54"><twConstPath anchorID="55" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.402</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_1</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_2</twDest><twTotPathDel>0.402</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_1</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_2</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y49.B5</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.081</twDelInfo><twComp>clock_control_inst/vfat2_count<1></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X38Y49.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.121</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<2>11</twBEL><twBEL>clock_control_inst/vfat2_count_2</twBEL></twPathDel><twLogDel>0.321</twLogDel><twRouteDel>0.081</twRouteDel><twTotDel>0.402</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>79.9</twPctLog><twPctRoute>20.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point clock_control_inst/vfat2_count_3 (SLICE_X38Y49.C6), 1 path
</twPathRptBanner><twPathRpt anchorID="56"><twConstPath anchorID="57" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.459</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_2</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_3</twDest><twTotPathDel>0.459</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_2</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X38Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y49.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twFalling">0.238</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/vfat2_count_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y49.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.031</twDelInfo><twComp>clock_control_inst/vfat2_count<2></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X38Y49.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>clock_control_inst/vfat2_count<3></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<3>11</twBEL><twBEL>clock_control_inst/vfat2_count_3</twBEL></twPathDel><twLogDel>0.428</twLogDel><twRouteDel>0.031</twRouteDel><twTotDel>0.459</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>93.2</twPctLog><twPctRoute>6.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point clock_control_inst/vfat2_count_6 (SLICE_X38Y48.C6), 1 path
</twPathRptBanner><twPathRpt anchorID="58"><twConstPath anchorID="59" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.462</twSlack><twSrc BELType="FF">clock_control_inst/vfat2_count_5</twSrc><twDest BELType="FF">clock_control_inst/vfat2_count_6</twDest><twTotPathDel>0.462</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>clock_control_inst/vfat2_count_5</twSrc><twDest BELType='FF'>clock_control_inst/vfat2_count_6</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X38Y48.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twSrcClk><twPathDel><twSite>SLICE_X38Y48.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twFalling">0.238</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/vfat2_count_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y48.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.034</twDelInfo><twComp>clock_control_inst/vfat2_count<5></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X38Y48.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>clock_control_inst/vfat2_count<6></twComp><twBEL>clock_control_inst/Mcount_vfat2_count_xor<6>11</twBEL><twBEL>clock_control_inst/vfat2_count_6</twBEL></twPathDel><twLogDel>0.428</twLogDel><twRouteDel>0.034</twRouteDel><twTotDel>0.462</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">fpga_clk</twDestClk><twPctLog>92.6</twPctLog><twPctRoute>7.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="60"><twPinLimitBanner>Component Switching Limit Checks: TS_vfat2_clk_ext = PERIOD TIMEGRP "vfat2_clk_ext" 25 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="61" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y42.CLKAWRCLK" clockNet="vfat2_clk"/><twPinLimit anchorID="62" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y49.CLKAWRCLK" clockNet="vfat2_clk"/><twPinLimit anchorID="63" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y32.CLKAWRCLK" clockNet="vfat2_clk"/></twPinLimitRpt></twConst><twConst anchorID="64" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_vfat2_clk_fpga = PERIOD TIMEGRP "vfat2_clk_fpga" 25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.124</twMinPer></twConstHead><twPinLimitRpt anchorID="65"><twPinLimitBanner>Component Switching Limit Checks: TS_vfat2_clk_fpga = PERIOD TIMEGRP "vfat2_clk_fpga" 25 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="66" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y42.CLKAWRCLK" clockNet="vfat2_clk"/><twPinLimit anchorID="67" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y49.CLKAWRCLK" clockNet="vfat2_clk"/><twPinLimit anchorID="68" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y32.CLKAWRCLK" clockNet="vfat2_clk"/></twPinLimitRpt></twConst><twConst anchorID="69" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_vfat2_clk_muxed = PERIOD TIMEGRP "vfat2_clk_muxed" 25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.124</twMinPer></twConstHead><twPinLimitRpt anchorID="70"><twPinLimitBanner>Component Switching Limit Checks: TS_vfat2_clk_muxed = PERIOD TIMEGRP "vfat2_clk_muxed" 25 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="71" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y42.CLKAWRCLK" clockNet="vfat2_clk"/><twPinLimit anchorID="72" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y49.CLKAWRCLK" clockNet="vfat2_clk"/><twPinLimit anchorID="73" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y32.CLKAWRCLK" clockNet="vfat2_clk"/></twPinLimitRpt></twConst><twConst anchorID="74" twConstType="PERIOD" ><twConstHead uID="5"><twConstName UCFConstName="" ScopeName="">TS_cdce_clk_muxed = PERIOD TIMEGRP "cdce_clk_muxed" 25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead><twPinLimitRpt anchorID="75"><twPinLimitBanner>Component Switching Limit Checks: TS_cdce_clk_muxed = PERIOD TIMEGRP "cdce_clk_muxed" 25 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="76" twConstType="PERIOD" ><twConstHead uID="6"><twConstName UCFConstName="" ScopeName="">TS_gtp_clk = PERIOD TIMEGRP "gtp_clk" 6.25 ns HIGH 50%;</twConstName><twItemCnt>33628</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>10155</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>6.250</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point chipscope_ila_inst/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GANDX.U_match/I_CS_GANDX.U_CS_GANDX_SRL/I_S6.U_CS_GANDX_SRL_S6/U_CS_GAND_SRL_S6/I_USE_RPM_EQ0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[3].U_GAND_SRL_SLICE_NO_RPM/I_IS_TERMINATION_SLICE_NE0.I_USE_OUTPUT_REG_NE0.U_OREG (SLICE_X14Y128.SR), 1 path
</twPathRptBanner><twPathRpt anchorID="77"><twConstPath anchorID="78" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.261</twSlack><twSrc BELType="FF">chipscope_ila_inst/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST</twSrc><twDest BELType="FF">chipscope_ila_inst/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GANDX.U_match/I_CS_GANDX.U_CS_GANDX_SRL/I_S6.U_CS_GANDX_SRL_S6/U_CS_GAND_SRL_S6/I_USE_RPM_EQ0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[3].U_GAND_SRL_SLICE_NO_RPM/I_IS_TERMINATION_SLICE_NE0.I_USE_OUTPUT_REG_NE0.U_OREG</twDest><twTotPathDel>6.015</twTotPathDel><twClkSkew dest = "0.795" src = "0.634">-0.161</twClkSkew><twDelConst>6.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>chipscope_ila_inst/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST</twSrc><twDest BELType='FF'>chipscope_ila_inst/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GANDX.U_match/I_CS_GANDX.U_CS_GANDX_SRL/I_S6.U_CS_GANDX_SRL_S6/U_CS_GAND_SRL_S6/I_USE_RPM_EQ0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[3].U_GAND_SRL_SLICE_NO_RPM/I_IS_TERMINATION_SLICE_NE0.I_USE_OUTPUT_REG_NE0.U_OREG</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X75Y153.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gtp_clk</twSrcClk><twPathDel><twSite>SLICE_X75Y153.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>chipscope_ila_inst/U0/I_NO_D.U_ILA/iRESET<1></twComp><twBEL>chipscope_ila_inst/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y128.SR</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">5.234</twDelInfo><twComp>chipscope_ila_inst/U0/I_NO_D.U_ILA/iRESET<0></twComp></twPathDel><twPathDel><twSite>SLICE_X14Y128.CLK</twSite><twDelType>Tsrck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>chipscope_ila_inst/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp</twComp><twBEL>chipscope_ila_inst/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GANDX.U_match/I_CS_GANDX.U_CS_GANDX_SRL/I_S6.U_CS_GANDX_SRL_S6/U_CS_GAND_SRL_S6/I_USE_RPM_EQ0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[3].U_GAND_SRL_SLICE_NO_RPM/I_IS_TERMINATION_SLICE_NE0.I_USE_OUTPUT_REG_NE0.U_OREG</twBEL></twPathDel><twLogDel>0.781</twLogDel><twRouteDel>5.234</twRouteDel><twTotDel>6.015</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twDestClk><twPctLog>13.0</twPctLog><twPctRoute>87.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="52" iCriticalPaths="0" sType="EndPoint">Paths for end point link_tracking_1_inst/registers_core_inst/data_byte_20 (SLICE_X29Y130.C4), 52 paths
</twPathRptBanner><twPathRpt anchorID="79"><twConstPath anchorID="80" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.293</twSlack><twSrc BELType="FF">link_tracking_1_inst/registers_core_inst/register_byte_0</twSrc><twDest BELType="FF">link_tracking_1_inst/registers_core_inst/data_byte_20</twDest><twTotPathDel>5.806</twTotPathDel><twClkSkew dest = "0.242" src = "0.258">0.016</twClkSkew><twDelConst>6.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/registers_core_inst/register_byte_0</twSrc><twDest BELType='FF'>link_tracking_1_inst/registers_core_inst/data_byte_20</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X27Y131.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gtp_clk</twSrcClk><twPathDel><twSite>SLICE_X27Y131.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte<2></twComp><twBEL>link_tracking_1_inst/registers_core_inst/register_byte_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y148.A3</twSite><twDelType>net</twDelType><twFanCnt>286</twFanCnt><twDelInfo twEdge="twRising">2.222</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte<0></twComp></twPathDel><twPathDel><twSite>SLICE_X29Y148.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_1264</twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_1264</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y134.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.310</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_1264</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y134.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.338</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_13126</twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_4121</twBEL><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_2_f7_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y130.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.964</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT<20></twComp></twPathDel><twPathDel><twSite>SLICE_X29Y130.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.322</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/data_byte<20></twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux__n2062131</twBEL><twBEL>link_tracking_1_inst/registers_core_inst/data_byte_20</twBEL></twPathDel><twLogDel>1.310</twLogDel><twRouteDel>4.496</twRouteDel><twTotDel>5.806</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twDestClk><twPctLog>22.6</twPctLog><twPctRoute>77.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="81"><twConstPath anchorID="82" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.419</twSlack><twSrc BELType="FF">link_tracking_1_inst/registers_core_inst/register_byte_1</twSrc><twDest BELType="FF">link_tracking_1_inst/registers_core_inst/data_byte_20</twDest><twTotPathDel>5.680</twTotPathDel><twClkSkew dest = "0.242" src = "0.258">0.016</twClkSkew><twDelConst>6.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/registers_core_inst/register_byte_1</twSrc><twDest BELType='FF'>link_tracking_1_inst/registers_core_inst/data_byte_20</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X27Y131.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gtp_clk</twSrcClk><twPathDel><twSite>SLICE_X27Y131.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte<2></twComp><twBEL>link_tracking_1_inst/registers_core_inst/register_byte_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y148.A5</twSite><twDelType>net</twDelType><twFanCnt>286</twFanCnt><twDelInfo twEdge="twRising">2.096</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte<1></twComp></twPathDel><twPathDel><twSite>SLICE_X29Y148.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_1264</twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_1264</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y134.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.310</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_1264</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y134.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.338</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_13126</twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_4121</twBEL><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_2_f7_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y130.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.964</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT<20></twComp></twPathDel><twPathDel><twSite>SLICE_X29Y130.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.322</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/data_byte<20></twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux__n2062131</twBEL><twBEL>link_tracking_1_inst/registers_core_inst/data_byte_20</twBEL></twPathDel><twLogDel>1.310</twLogDel><twRouteDel>4.370</twRouteDel><twTotDel>5.680</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twDestClk><twPctLog>23.1</twPctLog><twPctRoute>76.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="83"><twConstPath anchorID="84" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.527</twSlack><twSrc BELType="FF">link_tracking_1_inst/registers_core_inst/register_byte_1</twSrc><twDest BELType="FF">link_tracking_1_inst/registers_core_inst/data_byte_20</twDest><twTotPathDel>5.572</twTotPathDel><twClkSkew dest = "0.242" src = "0.258">0.016</twClkSkew><twDelConst>6.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/registers_core_inst/register_byte_1</twSrc><twDest BELType='FF'>link_tracking_1_inst/registers_core_inst/data_byte_20</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X27Y131.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gtp_clk</twSrcClk><twPathDel><twSite>SLICE_X27Y131.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte<2></twComp><twBEL>link_tracking_1_inst/registers_core_inst/register_byte_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X33Y127.B3</twSite><twDelType>net</twDelType><twFanCnt>286</twFanCnt><twDelInfo twEdge="twRising">1.640</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte<1></twComp></twPathDel><twPathDel><twSite>SLICE_X33Y127.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>request_write<11><19></twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_13120</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y134.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.007</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_13120</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y134.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_13126</twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_712</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y134.C1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.441</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_712</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y134.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.343</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_13126</twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_312</twBEL><twBEL>link_tracking_1_inst/registers_core_inst/Mmux_register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT_2_f7_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y130.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.964</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/register_byte[6]_rbus_i[127][31]_wide_mux_12_OUT<20></twComp></twPathDel><twPathDel><twSite>SLICE_X29Y130.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.322</twDelInfo><twComp>link_tracking_1_inst/registers_core_inst/data_byte<20></twComp><twBEL>link_tracking_1_inst/registers_core_inst/Mmux__n2062131</twBEL><twBEL>link_tracking_1_inst/registers_core_inst/data_byte_20</twBEL></twPathDel><twLogDel>1.520</twLogDel><twRouteDel>4.052</twRouteDel><twTotDel>5.572</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twDestClk><twPctLog>27.3</twPctLog><twPctRoute>72.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i (GTPA1_DUAL_X0Y1.TXDATA113), 1 path
</twPathRptBanner><twPathRpt anchorID="85"><twConstPath anchorID="86" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.329</twSlack><twSrc BELType="FF">link_tracking_1_inst/gtp_tx_mux_inst/tx_data_o_13</twSrc><twDest BELType="HSIO">gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i</twDest><twTotPathDel>6.136</twTotPathDel><twClkSkew dest = "0.988" src = "0.638">-0.350</twClkSkew><twDelConst>6.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.200" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.135</twClkUncert><twDetPath maxSiteLen="26" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/gtp_tx_mux_inst/tx_data_o_13</twSrc><twDest BELType='HSIO'>gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X69Y128.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gtp_clk</twSrcClk><twPathDel><twSite>SLICE_X69Y128.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.391</twDelInfo><twComp>tx_data<30></twComp><twBEL>link_tracking_1_inst/gtp_tx_mux_inst/tx_data_o_13</twBEL></twPathDel><twPathDel><twSite>GTPA1_DUAL_X0Y1.TXDATA113</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">5.295</twDelInfo><twComp>tx_data<29></twComp></twPathDel><twPathDel><twSite>GTPA1_DUAL_X0Y1.TXUSRCLK21</twSite><twDelType>Tgtpcck_TXDATA</twDelType><twDelInfo twEdge="twRising">0.450</twDelInfo><twComp>gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i</twComp><twBEL>gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i</twBEL></twPathDel><twLogDel>0.841</twLogDel><twRouteDel>5.295</twRouteDel><twTotDel>6.136</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twDestClk><twPctLog>13.7</twPctLog><twPctRoute>86.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_gtp_clk = PERIOD TIMEGRP "gtp_clk" 6.25 ns HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT (SLICE_X71Y122.SR), 1 path
</twPathRptBanner><twPathRpt anchorID="87"><twConstPath anchorID="88" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.185</twSlack><twSrc BELType="FF">chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT1</twSrc><twDest BELType="FF">chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT</twDest><twTotPathDel>0.184</twTotPathDel><twClkSkew dest = "0.036" src = "0.037">0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT1</twSrc><twDest BELType='FF'>chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X70Y123.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twSrcClk><twPathDel><twSite>SLICE_X70Y123.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/iDIN<1></twComp><twBEL>chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT1</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y122.SR</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.115</twDelInfo><twComp>chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/iDIN<1></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X71Y122.CLK</twSite><twDelType>Tcksr</twDelType><twDelInfo twEdge="twFalling">-0.131</twDelInfo><twComp>chipscope_vio_inst/U0/I_VIO/ARM_pulse</twComp><twBEL>chipscope_vio_inst/U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT</twBEL></twPathDel><twLogDel>0.069</twLogDel><twRouteDel>0.115</twRouteDel><twTotDel>0.184</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twDestClk><twPctLog>37.5</twPctLog><twPctRoute>62.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/i2c_master_inst/u2/Mshreg_enable_reg (SLICE_X124Y157.AI), 1 path
</twPathRptBanner><twPathRpt anchorID="89"><twConstPath anchorID="90" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.248</twSlack><twSrc BELType="FF">link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/enable</twSrc><twDest BELType="FF">link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/i2c_master_inst/u2/Mshreg_enable_reg</twDest><twTotPathDel>0.250</twTotPathDel><twClkSkew dest = "0.042" src = "0.040">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/enable</twSrc><twDest BELType='FF'>link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/i2c_master_inst/u2/Mshreg_enable_reg</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X125Y157.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twSrcClk><twPathDel><twSite>SLICE_X125Y157.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/enable</twComp><twBEL>link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/enable</twBEL></twPathDel><twPathDel><twSite>SLICE_X124Y157.AI</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.022</twDelInfo><twComp>link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/enable</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X124Y157.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">0.030</twDelInfo><twComp>link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/i2c_master_inst/u2/enable_reg</twComp><twBEL>link_tracking_1_inst/vi2c_core_inst/vi2c_wrapper_inst/i2c_master_inst/u2/Mshreg_enable_reg</twBEL></twPathDel><twLogDel>0.228</twLogDel><twRouteDel>0.022</twRouteDel><twTotDel>0.250</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twDestClk><twPctLog>91.2</twPctLog><twPctRoute>8.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point chipscope_ila_inst/U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[119].I_SRLT_NE_0.DLY9/SRL16E (SLICE_X22Y134.DI), 1 path
</twPathRptBanner><twPathRpt anchorID="91"><twConstPath anchorID="92" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.254</twSlack><twSrc BELType="FF">chipscope_ila_inst/U0/I_TQ3.G_TW[23].U_TQ</twSrc><twDest BELType="FF">chipscope_ila_inst/U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[119].I_SRLT_NE_0.DLY9/SRL16E</twDest><twTotPathDel>0.256</twTotPathDel><twClkSkew dest = "0.034" src = "0.032">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>chipscope_ila_inst/U0/I_TQ3.G_TW[23].U_TQ</twSrc><twDest BELType='FF'>chipscope_ila_inst/U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[119].I_SRLT_NE_0.DLY9/SRL16E</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X23Y134.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twSrcClk><twPathDel><twSite>SLICE_X23Y134.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>chipscope_ila_inst/U0/iTRIG_IN<119></twComp><twBEL>chipscope_ila_inst/U0/I_TQ3.G_TW[23].U_TQ</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y134.DI</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.025</twDelInfo><twComp>chipscope_ila_inst/U0/iTRIG_IN<119></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X22Y134.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">0.033</twDelInfo><twComp>chipscope_ila_inst/U0/I_NO_D.U_ILA/iDATA<119></twComp><twBEL>chipscope_ila_inst/U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[119].I_SRLT_NE_0.DLY9/SRL16E</twBEL></twPathDel><twLogDel>0.231</twLogDel><twRouteDel>0.025</twRouteDel><twTotDel>0.256</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.250">gtp_clk</twDestClk><twPctLog>90.2</twPctLog><twPctRoute>9.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="93"><twPinLimitBanner>Component Switching Limit Checks: TS_gtp_clk = PERIOD TIMEGRP "gtp_clk" 6.25 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="94" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="6.250" constraintValue="6.250" deviceLimit="6.250" freqLimit="160.000" physResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/RXUSRCLK20" logResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/RXUSRCLK20" locationPin="GTPA1_DUAL_X0Y1.RXUSRCLK20" clockNet="gtp_clk"/><twPinLimit anchorID="95" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="6.250" constraintValue="6.250" deviceLimit="6.250" freqLimit="160.000" physResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/RXUSRCLK21" logResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/RXUSRCLK21" locationPin="GTPA1_DUAL_X0Y1.RXUSRCLK21" clockNet="gtp_clk"/><twPinLimit anchorID="96" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="0.000" period="6.250" constraintValue="6.250" deviceLimit="6.250" freqLimit="160.000" physResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/TXUSRCLK20" logResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/TXUSRCLK20" locationPin="GTPA1_DUAL_X0Y1.TXUSRCLK20" clockNet="gtp_clk"/></twPinLimitRpt></twConst><twConst anchorID="97" twConstType="PERIOD" ><twConstHead uID="7"><twConstName UCFConstName="" ScopeName="">TS_vfat2_clk = PERIOD TIMEGRP "vfat2_clk" 25 ns HIGH 50%;</twConstName><twItemCnt>55683</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>20769</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>9.976</twMinPer></twConstHead><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_112 (SLICE_X126Y46.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="98"><twConstPath anchorID="99" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.024</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twSrc><twDest BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_112</twDest><twTotPathDel>9.579</twTotPathDel><twClkSkew dest = "0.623" src = "0.635">0.012</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.700" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.385</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twSrc><twDest BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_112</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X101Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X101Y49.DMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.461</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/_n0273</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X86Y79.A5</twSite><twDelType>net</twDelType><twFanCnt>210</twFanCnt><twDelInfo twEdge="twRising">3.007</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X86Y79.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_PWR_56_o_GND_121_o_MUX_920_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X126Y46.CE</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">5.571</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp></twPathDel><twPathDel><twSite>SLICE_X126Y46.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_data<5><115></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_112</twBEL></twPathDel><twLogDel>1.001</twLogDel><twRouteDel>8.578</twRouteDel><twTotDel>9.579</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>10.4</twPctLog><twPctRoute>89.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="100"><twConstPath anchorID="101" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.221</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twSrc><twDest BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_112</twDest><twTotPathDel>9.387</twTotPathDel><twClkSkew dest = "0.623" src = "0.630">0.007</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.700" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.385</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twSrc><twDest BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_112</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X100Y52.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X100Y52.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twBEL></twPathDel><twPathDel><twSite>SLICE_X86Y79.A2</twSite><twDelType>net</twDelType><twFanCnt>211</twFanCnt><twDelInfo twEdge="twRising">2.829</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twComp></twPathDel><twPathDel><twSite>SLICE_X86Y79.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_PWR_56_o_GND_121_o_MUX_920_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X126Y46.CE</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">5.571</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp></twPathDel><twPathDel><twSite>SLICE_X126Y46.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_data<5><115></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_112</twBEL></twPathDel><twLogDel>0.987</twLogDel><twRouteDel>8.400</twRouteDel><twTotDel>9.387</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>10.5</twPctLog><twPctRoute>89.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_115 (SLICE_X126Y46.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="102"><twConstPath anchorID="103" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.044</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twSrc><twDest BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_115</twDest><twTotPathDel>9.559</twTotPathDel><twClkSkew dest = "0.623" src = "0.635">0.012</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.700" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.385</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twSrc><twDest BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_115</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X101Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X101Y49.DMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.461</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/_n0273</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X86Y79.A5</twSite><twDelType>net</twDelType><twFanCnt>210</twFanCnt><twDelInfo twEdge="twRising">3.007</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X86Y79.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_PWR_56_o_GND_121_o_MUX_920_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X126Y46.CE</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">5.571</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp></twPathDel><twPathDel><twSite>SLICE_X126Y46.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.315</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_data<5><115></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_115</twBEL></twPathDel><twLogDel>0.981</twLogDel><twRouteDel>8.578</twRouteDel><twTotDel>9.559</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>10.3</twPctLog><twPctRoute>89.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="104"><twConstPath anchorID="105" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.241</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twSrc><twDest BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_115</twDest><twTotPathDel>9.367</twTotPathDel><twClkSkew dest = "0.623" src = "0.630">0.007</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.700" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.385</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twSrc><twDest BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_115</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X100Y52.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X100Y52.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twBEL></twPathDel><twPathDel><twSite>SLICE_X86Y79.A2</twSite><twDelType>net</twDelType><twFanCnt>211</twFanCnt><twDelInfo twEdge="twRising">2.829</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twComp></twPathDel><twPathDel><twSite>SLICE_X86Y79.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_PWR_56_o_GND_121_o_MUX_920_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X126Y46.CE</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">5.571</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp></twPathDel><twPathDel><twSite>SLICE_X126Y46.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.315</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_data<5><115></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_115</twBEL></twPathDel><twLogDel>0.967</twLogDel><twRouteDel>8.400</twRouteDel><twTotDel>9.367</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>10.3</twPctLog><twPctRoute>89.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_114 (SLICE_X126Y46.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="106"><twConstPath anchorID="107" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.045</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twSrc><twDest BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_114</twDest><twTotPathDel>9.558</twTotPathDel><twClkSkew dest = "0.623" src = "0.635">0.012</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.700" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.385</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twSrc><twDest BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_114</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X101Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X101Y49.DMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.461</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/_n0273</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X86Y79.A5</twSite><twDelType>net</twDelType><twFanCnt>210</twFanCnt><twDelInfo twEdge="twRising">3.007</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X86Y79.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_PWR_56_o_GND_121_o_MUX_920_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X126Y46.CE</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">5.571</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp></twPathDel><twPathDel><twSite>SLICE_X126Y46.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.314</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_data<5><115></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_114</twBEL></twPathDel><twLogDel>0.980</twLogDel><twRouteDel>8.578</twRouteDel><twTotDel>9.558</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>10.3</twPctLog><twPctRoute>89.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="108"><twConstPath anchorID="109" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>15.242</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twSrc><twDest BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_114</twDest><twTotPathDel>9.366</twTotPathDel><twClkSkew dest = "0.623" src = "0.630">0.007</twClkSkew><twDelConst>25.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.700" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.385</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twSrc><twDest BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_114</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X100Y52.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X100Y52.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twBEL></twPathDel><twPathDel><twSite>SLICE_X86Y79.A2</twSite><twDelType>net</twDelType><twFanCnt>211</twFanCnt><twDelInfo twEdge="twRising">2.829</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_FSM_FFd1</twComp></twPathDel><twPathDel><twSite>SLICE_X86Y79.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/state_PWR_56_o_GND_121_o_MUX_920_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X126Y46.CE</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">5.571</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/PWR_56_o_GND_121_o_MUX_920_o</twComp></twPathDel><twPathDel><twSite>SLICE_X126Y46.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.314</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_data<5><115></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_114</twBEL></twPathDel><twLogDel>0.966</twLogDel><twRouteDel>8.400</twRouteDel><twTotDel>9.366</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>10.3</twPctLog><twPctRoute>89.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_vfat2_clk = PERIOD TIMEGRP "vfat2_clk" 25 ns HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X3Y32.DIADI14), 1 path
</twPathRptBanner><twPathRpt anchorID="110"><twConstPath anchorID="111" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.349</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/tracking_concentrator_inst/data_o_159</twSrc><twDest BELType="RAM">link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram</twDest><twTotPathDel>0.438</twTotPathDel><twClkSkew dest = "0.428" src = "0.339">-0.089</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="21" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/tracking_concentrator_inst/data_o_159</twSrc><twDest BELType='RAM'>link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X84Y63.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X84Y63.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/data_fifo_din<159></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/tracking_concentrator_inst/data_o_159</twBEL></twPathDel><twPathDel><twSite>RAMB8_X3Y32.DIADI14</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.257</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/data_fifo_din<159></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB8_X3Y32.CLKAWRCLK</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.053</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram</twComp><twBEL>link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram</twBEL></twPathDel><twLogDel>0.181</twLogDel><twRouteDel>0.257</twRouteDel><twTotDel>0.438</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>41.3</twPctLog><twPctRoute>58.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_170 (SLICE_X88Y30.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="112"><twConstPath anchorID="113" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.366</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_170</twSrc><twDest BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_170</twDest><twTotPathDel>0.456</twTotPathDel><twClkSkew dest = "0.434" src = "0.344">-0.090</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_170</twSrc><twDest BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_170</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X88Y32.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X88Y32.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/data<171></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_170</twBEL></twPathDel><twPathDel><twSite>SLICE_X88Y30.CX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.208</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/data<170></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X88Y30.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_data<5><171></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_170</twBEL></twPathDel><twLogDel>0.248</twLogDel><twRouteDel>0.208</twRouteDel><twTotDel>0.456</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>54.4</twPctLog><twPctRoute>45.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_171 (SLICE_X88Y30.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="114"><twConstPath anchorID="115" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.366</twSlack><twSrc BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_171</twSrc><twDest BELType="FF">link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_171</twDest><twTotPathDel>0.456</twTotPathDel><twClkSkew dest = "0.434" src = "0.344">-0.090</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_171</twSrc><twDest BELType='FF'>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_171</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X88Y32.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twSrcClk><twPathDel><twSite>SLICE_X88Y32.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/data<171></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_171</twBEL></twPathDel><twPathDel><twSite>SLICE_X88Y30.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.208</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_5_inst/data<171></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X88Y30.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>link_tracking_1_inst/tracking_core_inst/track_data<5><171></twComp><twBEL>link_tracking_1_inst/tracking_core_inst/track_5_inst/data_o_171</twBEL></twPathDel><twLogDel>0.248</twLogDel><twRouteDel>0.208</twRouteDel><twTotDel>0.456</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="25.000">vfat2_clk</twDestClk><twPctLog>54.4</twPctLog><twPctRoute>45.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="116"><twPinLimitBanner>Component Switching Limit Checks: TS_vfat2_clk = PERIOD TIMEGRP "vfat2_clk" 25 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="117" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y42.CLKAWRCLK" clockNet="vfat2_clk"/><twPinLimit anchorID="118" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y49.CLKAWRCLK" clockNet="vfat2_clk"/><twPinLimit anchorID="119" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="21.876" period="25.000" constraintValue="25.000" deviceLimit="3.124" freqLimit="320.102" physResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" logResource="link_tracking_1_inst/tracking_core_inst/tracking_data_fifo_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X3Y32.CLKAWRCLK" clockNet="vfat2_clk"/></twPinLimitRpt></twConst><twConst anchorID="120" twConstType="PERIOD" ><twConstHead uID="8"><twConstName UCFConstName="" ScopeName="">TS_gtp_userclk00 = PERIOD TIMEGRP "gtp_userclk00" 3.125 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.125</twMinPer></twConstHead><twPinLimitRpt anchorID="121"><twPinLimitBanner>Component Switching Limit Checks: TS_gtp_userclk00 = PERIOD TIMEGRP "gtp_userclk00" 3.125 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="122" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="3.125" constraintValue="3.125" deviceLimit="3.125" freqLimit="320.000" physResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/RXUSRCLK0" logResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/RXUSRCLK0" locationPin="GTPA1_DUAL_X0Y1.RXUSRCLK0" clockNet="gtp_wrapper_inst/gtp_userclk<0>"/><twPinLimit anchorID="123" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="3.125" constraintValue="3.125" deviceLimit="3.125" freqLimit="320.000" physResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/RXUSRCLK1" logResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/RXUSRCLK1" locationPin="GTPA1_DUAL_X0Y1.RXUSRCLK1" clockNet="gtp_wrapper_inst/gtp_userclk<0>"/><twPinLimit anchorID="124" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="0.000" period="3.125" constraintValue="3.125" deviceLimit="3.125" freqLimit="320.000" physResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/TXUSRCLK0" logResource="gtp_wrapper_inst/gtp_inst/tile0_gtp_i/gtpa1_dual_i/TXUSRCLK0" locationPin="GTPA1_DUAL_X0Y1.TXUSRCLK0" clockNet="gtp_wrapper_inst/gtp_userclk<0>"/></twPinLimitRpt></twConst><twConst anchorID="125" twConstType="PERIOD" ><twConstHead uID="9"><twConstName UCFConstName="" ScopeName="">TS_gtp_userclk01 = PERIOD TIMEGRP "gtp_userclk01" 3.125 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.125</twMinPer></twConstHead><twPinLimitRpt anchorID="126"><twPinLimitBanner>Component Switching Limit Checks: TS_gtp_userclk01 = PERIOD TIMEGRP "gtp_userclk01" 3.125 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="127" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="3.125" constraintValue="3.125" deviceLimit="3.125" freqLimit="320.000" physResource="gtp_wrapper_inst/gtp_inst/tile1_gtp_i/gtpa1_dual_i/RXUSRCLK0" logResource="gtp_wrapper_inst/gtp_inst/tile1_gtp_i/gtpa1_dual_i/RXUSRCLK0" locationPin="GTPA1_DUAL_X1Y1.RXUSRCLK0" clockNet="gtp_wrapper_inst/gtp_userclk<1>"/><twPinLimit anchorID="128" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="3.125" constraintValue="3.125" deviceLimit="3.125" freqLimit="320.000" physResource="gtp_wrapper_inst/gtp_inst/tile1_gtp_i/gtpa1_dual_i/RXUSRCLK1" logResource="gtp_wrapper_inst/gtp_inst/tile1_gtp_i/gtpa1_dual_i/RXUSRCLK1" locationPin="GTPA1_DUAL_X1Y1.RXUSRCLK1" clockNet="gtp_wrapper_inst/gtp_userclk<1>"/><twPinLimit anchorID="129" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="0.000" period="3.125" constraintValue="3.125" deviceLimit="3.125" freqLimit="320.000" physResource="gtp_wrapper_inst/gtp_inst/tile1_gtp_i/gtpa1_dual_i/TXUSRCLK0" logResource="gtp_wrapper_inst/gtp_inst/tile1_gtp_i/gtpa1_dual_i/TXUSRCLK0" locationPin="GTPA1_DUAL_X1Y1.TXUSRCLK0" clockNet="gtp_wrapper_inst/gtp_userclk<1>"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="130">0</twUnmetConstCnt><twDataSheet anchorID="131" twNameLen="15"><twClk2SUList anchorID="132" twDestWidth="15"><twDest>fpga_clk_i</twDest><twClk2SU><twSrc>fpga_clk_i</twSrc><twRiseRise>9.976</twRiseRise></twClk2SU><twClk2SU><twSrc>fpga_test_io<1></twSrc><twRiseRise>9.976</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="133" twDestWidth="15"><twDest>fpga_test_io<1></twDest><twClk2SU><twSrc>fpga_clk_i</twSrc><twRiseRise>9.976</twRiseRise></twClk2SU><twClk2SU><twSrc>fpga_test_io<1></twSrc><twRiseRise>9.976</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="134"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>89769</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>31069</twConnCnt></twConstCov><twStats anchorID="135"><twMinPer>9.976</twMinPer><twFootnote number="1" /><twMaxFreq>100.241</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Tue Apr 21 12:34:03 2015 </twTimestamp></twFoot><twClientInfo anchorID="136"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 532 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>