diff --git a/cache/cache.hpp b/cache/cache.hpp
index e64b073..e6c4721 100644
--- a/cache/cache.hpp
+++ b/cache/cache.hpp
@@ -191,6 +191,10 @@ class CacheBase : public CacheMonitorSupport
   // access both meta and data in one function call
   virtual std::pair<CMMetadataBase *, CMDataBase *> access_line(uint32_t ai, uint32_t s, uint32_t w) = 0;
 
+  virtual void replace_read(uint32_t ai, uint32_t s, uint32_t w, bool prefetch, bool genre = false) = 0;
+  virtual void replace_write(uint32_t ai, uint32_t s, uint32_t w, bool demand_acc, bool genre = false) = 0;
+  virtual void replace_manage(uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool genre = false) = 0;
+
   virtual bool query_coloc(uint64_t addrA, uint64_t addrB) = 0;
   virtual LocInfo query_loc(uint64_t addr) { return LocInfo(id, this, addr); }
   virtual void query_fill_loc(LocInfo *loc, uint64_t addr) = 0;
@@ -330,21 +334,30 @@ class CacheSkewed : public CacheBase
     data_return_buffer(buffer_data);
   }
 
-  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool prefetch, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) override {
-    if(ai < P) replacer[ai].access(s, w, true, prefetch);
+  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) override {
     if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_read(addr, ai, s, w, hit, meta, data, delay);
   }
 
-  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool demand_acc, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) override {
-    if(ai < P) replacer[ai].access(s, w, demand_acc, false);
+  virtual void replace_read(uint32_t ai, uint32_t s, uint32_t w, bool prefetch, bool genre = false) override {
+    if(ai < P) replacer[ai].access(s, w, true, prefetch);
+  }
+
+  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) override {
     if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_write(addr, ai, s, w, hit, meta, data, delay);
   }
 
+  virtual void replace_write(uint32_t ai, uint32_t s, uint32_t w, bool demand_acc, bool genre = false) override {
+    if(ai < P) replacer[ai].access(s, w, demand_acc, false);
+  }
+
   virtual void hook_manage(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool writeback, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) override {
-    if(ai < P && hit && evict) replacer[ai].invalid(s, w, evict == 2);
     if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_manage(addr, ai, s, w, hit, evict, writeback, meta, data, delay);
   }
 
+  virtual void replace_manage(uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool genre = false) override {
+    if(ai < P && hit && evict) replacer[ai].invalid(s, w, evict == 2);
+  }
+
   virtual CMDataBase *data_copy_buffer() override {
     if (data_buffer_pool_set.empty()) return nullptr;
     if constexpr (EnMT) {
diff --git a/cache/coherence.hpp b/cache/coherence.hpp
index 84c83ac..6a90e3a 100644
--- a/cache/coherence.hpp
+++ b/cache/coherence.hpp
@@ -47,7 +47,6 @@ class OuterCohPortBase
 
   virtual void acquire_req(uint64_t addr, CMMetadataBase *meta, CMDataBase *data, coh_cmd_t cmd, uint64_t *delay) = 0;
   virtual void writeback_req(uint64_t addr, CMMetadataBase *meta, CMDataBase *data, coh_cmd_t cmd, uint64_t *delay) = 0;
-  virtual void prefetch_req(uint64_t addr, coh_cmd_t cmd, uint64_t *delay) = 0;
 
   // may not implement probe_resp() and finish_req() if the port is uncached
   virtual std::pair<bool, bool> probe_resp(uint64_t addr, CMMetadataBase *meta, CMDataBase *data, coh_cmd_t cmd, uint64_t *delay) { return std::make_pair(false,false); }
@@ -78,7 +77,6 @@ class InnerCohPortBase
 
   virtual void acquire_resp(uint64_t addr, CMDataBase *data_inner, CMMetadataBase *meta_inner, coh_cmd_t outer_cmd, uint64_t *delay) = 0;
   virtual void writeback_resp(uint64_t addr, CMDataBase *data_inner, CMMetadataBase *meta_inner, coh_cmd_t outer_cmd, uint64_t *delay) = 0;
-  virtual void prefetch_resp(uint64_t addr, coh_cmd_t outer_cmd, uint64_t *delay) = 0;
 
   // may not implement probe_req() and finish_resp() if the port is uncached
   virtual std::pair<bool,bool> probe_req(uint64_t addr, CMMetadataBase *meta, CMDataBase *data, coh_cmd_t cmd, uint64_t *delay) { return std::make_pair(false,false); }
@@ -144,11 +142,6 @@ class OuterCohPortUncached : public OuterCohPortBase
     Policy::meta_after_writeback(outer_cmd, meta);
   }
 
-  virtual void prefetch_req(uint64_t addr, coh_cmd_t outer_cmd, uint64_t *delay) override {
-    outer_cmd.id = coh_id;
-    coh->prefetch_resp(addr, outer_cmd, delay);
-  }
-
   virtual void query_loc_req(uint64_t addr, std::list<LocInfo> *locs) override {
     coh->query_loc_resp(addr, locs);
   }
@@ -191,18 +184,23 @@ class OuterCohPortT : public OPUC<Policy, EnMT, Extra...>
       auto sync = Policy::probe_need_sync(outer_cmd, meta);
       if(sync.first) {
         auto [phit, pwb] = OuterCohPortBase::inner->probe_req(addr, meta, data, sync.second, delay);
-        if(pwb) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay);
+        if(pwb) {
+          cache->replace_write(ai, s, w, false);
+          cache->hook_write(addr, ai, s, w, true, meta, data, delay);
+        }
       }
 
       // now we should be able to safely operate on the cache line
       if constexpr (EnMT) {assert(meta->match(addr)); meta_outer->lock(); }
       if((writeback = Policy::probe_need_writeback(outer_cmd, meta))) { if(data_outer) data_outer->copy(data); } // writeback if dirty
       Policy::meta_after_probe(outer_cmd, meta, meta_outer, coh_id, writeback); // alway update meta
+      cache->replace_manage(ai, s, w, hit, (coh::is_evict(outer_cmd) ? 1 : 0));
       cache->hook_manage(addr, ai, s, w, hit, (coh::is_evict(outer_cmd) ? 1 : 0), writeback, meta, data, delay);
       if constexpr (EnMT) { meta_outer->unlock(); meta->unlock(); cache->reset_mt_state(ai, s, XactPrio::probe); }
     } else {
       if constexpr (EnMT) meta_outer->lock();
       Policy::meta_after_probe(outer_cmd, meta, meta_outer, coh_id, writeback); // alway update meta
+      cache->replace_manage(ai, s, w, hit, (coh::is_evict(outer_cmd) ? 1 : 0));
       cache->hook_manage(addr, ai, s, w, hit, (coh::is_evict(outer_cmd) ? 1 : 0), writeback, meta, data, delay);
       if constexpr (EnMT) meta_outer->unlock();
     }
@@ -225,10 +223,12 @@ class InnerCohPortUncached : public InnerCohPortBase
 public:
   virtual void acquire_resp(uint64_t addr, CMDataBase *data_inner, CMMetadataBase *meta_inner, coh_cmd_t cmd, uint64_t *delay) override {
     auto [meta, data, ai, s, w, hit] = access_line(addr, cmd, XactPrio::acquire, delay);
+    bool act_as_prefetch = coh::is_prefetch(cmd) && Policy::is_uncached(); // only tweak replace priority at the LLC accoridng to [Guo2022-MICRO]
 
     if (data_inner && data) data_inner->copy(data);
     Policy::meta_after_grant(cmd, meta, meta_inner);
-    cache->hook_read(addr, ai, s, w, hit, coh::is_prefetch(cmd), meta, data, delay);
+    if(!act_as_prefetch || !hit) cache->replace_read(ai, s, w, act_as_prefetch);
+    cache->hook_read(addr, ai, s, w, hit, meta, data, delay);
     finish_record(addr, coh::cmd_for_finish(cmd.id), !hit, meta, ai, s);
     if(cmd.id == -1) finish_resp(addr, coh::cmd_for_finish(cmd.id));
   }
@@ -240,10 +240,6 @@ class InnerCohPortUncached : public InnerCohPortBase
       write_line(addr, data_inner, meta_inner, cmd, delay);
   }
 
-  virtual void prefetch_resp(uint64_t addr, coh_cmd_t cmd, uint64_t *delay) override {
-    prefetch_line(addr, cmd, delay);
-  }
-
   virtual void query_loc_resp(uint64_t addr, std::list<LocInfo> *locs) override {
     outer->query_loc_req(addr, locs);
     locs->push_front(cache->query_loc(addr));
@@ -258,33 +254,35 @@ class InnerCohPortUncached : public InnerCohPortBase
     if(sync.first) {
       if constexpr (EnMT && Policy::sync_need_lock()) cache->set_mt_state(ai, s, XactPrio::sync);
       auto [phit, pwb] = probe_req(addr, meta, data, sync.second, delay); // sync if necessary
-      if(pwb) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay); // a write occurred during the probe
+      if(pwb){
+        cache->replace_write(ai, s, w, false);
+        cache->hook_write(addr, ai, s, w, true, meta, data, delay); // a write occurred during the probe
+      }
       if constexpr (EnMT && Policy::sync_need_lock()) cache->reset_mt_state(ai, s, XactPrio::sync);
     }
     auto writeback = Policy::writeback_need_writeback(meta);
     if(writeback.first) outer->writeback_req(addr, meta, data, writeback.second, delay); // writeback if dirty
     Policy::meta_after_evict(meta);
+    cache->replace_manage(ai, s, w, true, 1);
     cache->hook_manage(addr, ai, s, w, true, 1, writeback.first, meta, data, delay);
   }
 
   virtual std::tuple<bool, CMMetadataBase *, CMDataBase *, uint32_t, uint32_t, uint32_t>
-  check_hit_or_replace(uint64_t addr, uint16_t prio, bool do_replace, bool prefetch, uint64_t *delay) { // check hit or get a replacement target
+  check_hit_or_replace(uint64_t addr, uint16_t prio, bool do_replace, uint64_t *delay) { // check hit or get a replacement target
     uint32_t ai, s, w;
     CMMetadataBase *meta = nullptr;
     CMDataBase *data = nullptr;
     bool hit;
     if constexpr (EnMT) {
       while(true) {
-        hit = cache->hit(addr, &ai, &s, &w, prio, !prefetch);
+        hit = cache->hit(addr, &ai, &s, &w, prio, true);
         if(hit) {
           std::tie(meta, data) = cache->access_line(ai, s, w);
-          if(!prefetch) { // no need to lock for prefetch
-            meta->lock();
-            if(!cache->check_mt_state(ai, s, prio) || !meta->match(addr)) { // acquire is intercepted by a probe and even invalidated
-              meta->unlock(); meta = nullptr; data = nullptr;
-              cache->reset_mt_state(ai, s, prio);
-              continue; // redo the hit check
-            }
+          meta->lock();
+          if(!cache->check_mt_state(ai, s, prio) || !meta->match(addr)) { // acquire is intercepted by a probe and even invalidated
+            meta->unlock(); meta = nullptr; data = nullptr;
+            cache->reset_mt_state(ai, s, prio);
+            continue; // redo the hit check
           }
         } else if(do_replace) { // miss
           if(cache->replace(addr, &ai, &s, &w, prio)) { // lock the cache set and get a replacement candidate
@@ -310,14 +308,16 @@ class InnerCohPortUncached : public InnerCohPortBase
 
   virtual std::tuple<CMMetadataBase *, CMDataBase *, uint32_t, uint32_t, uint32_t, bool>
   access_line(uint64_t addr, coh_cmd_t cmd, uint16_t prio, uint64_t *delay) { // common function for access a line in the cache
-    auto [hit, meta, data, ai, s, w] = check_hit_or_replace(addr, prio, true, false, delay);
-
+    auto [hit, meta, data, ai, s, w] = check_hit_or_replace(addr, prio, true, delay);
     if(hit) {
       auto sync = Policy::access_need_sync(cmd, meta);
       if(sync.first) {
         if constexpr (EnMT && Policy::sync_need_lock()) { assert(prio < XactPrio::sync); cache->set_mt_state(ai, s, XactPrio::sync);}
         auto [phit, pwb] = probe_req(addr, meta, data, sync.second, delay); // sync if necessary
-        if(pwb) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay); // a write occurred during the probe
+        if(pwb){
+          cache->replace_write(ai, s, w, false);
+          cache->hook_write(addr, ai, s, w, true, meta, data, delay); // a write occurred during the probe
+        }
         if constexpr (EnMT && Policy::sync_need_lock()) cache->reset_mt_state(ai, s, XactPrio::sync);
       }
       auto [promote, promote_local, promote_cmd] = Policy::access_need_promote(cmd, meta);
@@ -325,7 +325,7 @@ class InnerCohPortUncached : public InnerCohPortBase
       else if(promote_local) meta->to_modified(-1);
     } else { // miss
       if(meta->is_valid()) evict(meta, data, ai, s, w, delay);
-      outer->acquire_req(addr, meta, data, Policy::cmd_for_outer_acquire(cmd), delay); // fetch the missing block
+      outer->acquire_req(addr, meta, data, coh::is_prefetch(cmd) ? cmd : Policy::cmd_for_outer_acquire(cmd), delay); // fetch the missing block
     }
     return std::make_tuple(meta, data, ai, s, w, hit);
   }
@@ -336,7 +336,8 @@ class InnerCohPortUncached : public InnerCohPortBase
     if(data_inner) data->copy(data_inner);
     Policy::meta_after_release(cmd, meta, meta_inner);
     assert(meta_inner); // assume meta_inner is valid for all writebacks
-    cache->hook_write(addr, ai, s, w, hit, false, meta, data, delay);
+    cache->replace_write(ai, s, w, false);
+    cache->hook_write(addr, ai, s, w, hit, meta, data, delay);
     if constexpr (EnMT) { meta->unlock(); cache->reset_mt_state(ai, s, XactPrio::release); }
   }
 
@@ -344,14 +345,17 @@ class InnerCohPortUncached : public InnerCohPortBase
     if constexpr (!Policy::is_uncached())
       outer->writeback_req(addr, nullptr, nullptr, coh::cmd_for_flush(), delay);
     else {
-      auto [hit, meta, data, ai, s, w] = check_hit_or_replace(addr, XactPrio::flush, false, false, delay);
+      auto [hit, meta, data, ai, s, w] = check_hit_or_replace(addr, XactPrio::flush, false, delay);
       auto [probe, probe_cmd] = Policy::flush_need_sync(cmd, meta);
       if(!hit) return;
 
       if(probe) {
         if constexpr (EnMT && Policy::sync_need_lock()) cache->set_mt_state(ai, s, XactPrio::sync);
         auto [phit, pwb] = probe_req(addr, meta, data, probe_cmd, delay); // sync if necessary
-        if(pwb) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay); // a write occurred during the probe
+        if(pwb){
+          cache->replace_write(ai, s, w, false); // a write occurred during the probe
+          cache->hook_write(addr, ai, s, w, true, meta, data, delay); // a write occurred during the probe
+        }
         if constexpr (EnMT && Policy::sync_need_lock()) cache->reset_mt_state(ai, s, XactPrio::sync);
       }
 
@@ -359,26 +363,13 @@ class InnerCohPortUncached : public InnerCohPortBase
       if(writeback.first) outer->writeback_req(addr, meta, data, writeback.second, delay); // writeback if dirty
 
       Policy::meta_after_flush(cmd, meta, cache);
+      cache->replace_manage(ai, s, w, hit, (coh::is_evict(cmd) ? 2 : 0)); // identify flush to hook_manager
       cache->hook_manage(addr, ai, s, w, hit, (coh::is_evict(cmd) ? 2 : 0), writeback.first, meta, data, delay); // identify flush to hook_manager
 
       if constexpr (EnMT) { meta->unlock(); cache->reset_mt_state(ai, s, XactPrio::flush); }
     }
   }
 
-  virtual void prefetch_line(uint64_t addr, coh_cmd_t cmd, uint64_t *delay) {
-    if constexpr (!Policy::is_uncached())
-      outer->prefetch_req(addr, coh::cmd_for_prefetch(), delay);
-    else {
-      auto [hit, meta, data, ai, s, w] = check_hit_or_replace(addr, XactPrio::acquire, true, true, delay);
-      if(!hit) {
-        if(meta->is_valid()) evict(meta, data, ai, s, w, delay);
-        outer->acquire_req(addr, meta, data, coh::cmd_for_prefetch(), delay); // fetch the missing block
-        cache->hook_read(addr, ai, s, w, hit, true, meta, data, delay);
-        finish_record(addr, coh::cmd_for_finish(-1), !hit, meta, ai, s);
-        finish_resp(addr, coh::cmd_for_finish(-1));
-      }
-    }
-  }
 };
 
 template<template <typename, bool, typename...> class IPUC, typename Policy, bool EnMT, typename... Extra> requires C_DERIVE<IPUC<Policy, EnMT, Extra...>, InnerCohPortBase>
@@ -441,7 +432,7 @@ class CoreInterfaceBase
   // writeback and invalidate all dirty cache blocks, sync with NVM (wbinvd in x86-64)
   virtual void writeback_invalidate(uint64_t *delay) = 0;
   // prefetch a block
-  virtual void prefetch(uint64_t addr, uint64_t *delay) = 0;
+  virtual const CMDataBase *prefetch(uint64_t addr, uint64_t *delay) = 0;
 
   // flush the whole cache
   virtual void flush_cache(uint64_t *delay) = 0;
@@ -458,14 +449,19 @@ class CoreInterface : public InnerCohPortUncached<Policy, EnMT>, public CoreInte
   using BaseT::cache;
   using BaseT::outer;
 
-public:
-  using BaseT::BaseT;
-
-  virtual const CMDataBase *read(uint64_t addr, uint64_t *delay) override {
+  virtual const CMDataBase *read_write_access(uint64_t addr, const CMDataBase *m_data, const coh_cmd_t cmd, uint64_t *delay) {
     addr = normalize(addr);
-    auto cmd = coh::cmd_for_read();
     auto [meta, data, ai, s, w, hit] = this->access_line(addr, cmd, XactPrio::acquire, delay);
-    cache->hook_read(addr, ai, s, w, hit, false, meta, data, delay);
+    if(coh::is_write(cmd)) {
+      meta->to_dirty();
+      if(data) data->copy(m_data);
+      cache->replace_write(ai, s, w, true);
+      cache->hook_write(addr, ai, s, w, hit, meta, data, delay);
+    } else {
+      bool act_as_prefetch = coh::is_prefetch(cmd) && Policy::is_uncached(); // only tweak replace priority at the LLC accoridng to [Guo2022-MICRO]
+      if(!act_as_prefetch || !hit) cache->replace_read(ai, s, w, act_as_prefetch);
+      cache->hook_read(addr, ai, s, w, hit, meta, data, delay);
+    }
     if constexpr (EnMT) { meta->unlock(); cache->reset_mt_state(ai, s, XactPrio::acquire);}
     if(!hit) outer->finish_req(addr);
 #ifdef CHECK_MULTI
@@ -474,24 +470,15 @@ class CoreInterface : public InnerCohPortUncached<Policy, EnMT>, public CoreInte
     return data; // potentially dangerous and the data pointer is returned without lock
   }
 
-  virtual void write(uint64_t addr, const CMDataBase *m_data, uint64_t *delay) override {
-    addr = normalize(addr);
-    auto cmd = coh::cmd_for_write();
-    auto [meta, data, ai, s, w, hit] = this->access_line(addr, cmd, XactPrio::acquire, delay);
-    meta->to_dirty();
-    if(data) data->copy(m_data);
-    cache->hook_write(addr, ai, s, w, hit, true, meta, data, delay);
-    if constexpr (EnMT) { meta->unlock(); cache->reset_mt_state(ai, s, XactPrio::acquire);}
-    if(!hit) outer->finish_req(addr);
-#ifdef CHECK_MULTI
-    if constexpr (EnMT) { global_lock_checker->check(); }
-#endif
-  }
+public:
+  using BaseT::BaseT;
 
+  virtual const CMDataBase *read(uint64_t addr, uint64_t *delay) override { return read_write_access(addr, nullptr, coh::cmd_for_read(), delay); }
+  virtual void write(uint64_t addr, const CMDataBase *m_data, uint64_t *delay) override { read_write_access(addr, m_data, coh::cmd_for_write(), delay); }
   virtual void flush(uint64_t addr, uint64_t *delay) override     { this->flush_line(normalize(addr), coh::cmd_for_flush(), delay); }
   virtual void writeback(uint64_t addr, uint64_t *delay) override { this->flush_line(normalize(addr), coh::cmd_for_writeback(), delay); }
   virtual void writeback_invalidate(uint64_t *delay) override     { assert(nullptr == "Error: L1.writeback_invalidate() is not implemented yet!"); }
-  virtual void prefetch(uint64_t addr, uint64_t *delay) override  { this->prefetch_line(normalize(addr), coh::cmd_for_prefetch(), delay); }
+  virtual const CMDataBase *prefetch(uint64_t addr, uint64_t *delay) override { return read_write_access(addr, nullptr, coh::cmd_for_prefetch(), delay); }
 
   virtual void flush_cache(uint64_t *delay) override {
     auto [npar, nset, nway] = cache->size();
@@ -589,9 +576,6 @@ class SliceDispatcher : public CohMasterBase
   virtual void writeback_resp(uint64_t addr, CMDataBase *data, CMMetadataBase *meta_inner, coh_cmd_t cmd, uint64_t *delay) override {
     cohm[hasher(addr)]->writeback_resp(addr, data, meta_inner, cmd, delay);
   }
-  virtual void prefetch_resp(uint64_t addr, coh_cmd_t cmd, uint64_t *delay) override {
-    cohm[hasher(addr)]->prefetch_resp(addr, cmd, delay);
-  }
   virtual void query_loc_resp(uint64_t addr, std::list<LocInfo> *locs) override {
     cohm[hasher(addr)]->query_loc_resp(addr, locs);
   }
diff --git a/cache/dynamic_random.hpp b/cache/dynamic_random.hpp
index 319e489..3fbe3cc 100644
--- a/cache/dynamic_random.hpp
+++ b/cache/dynamic_random.hpp
@@ -5,7 +5,8 @@
 #include "util/monitor.hpp"
 #include <numeric>
 
-#define MAGIC_ID_REMAP 2024091300ul
+#define MAGIC_ID_REMAP_ASK  2024091300ul
+#define MAGIC_ID_REMAP_END  2024102700ul
 
 struct RemapHelper {
   static const unsigned int replace_for_relocate = 2408200ul;
@@ -112,7 +113,7 @@ class InnerCohPortRemapT : public InnerCohPortT<InnerCohPortUncached, Policy, En
     auto [p, s, w] = cache->size();
     uint32_t P, nset, nway;
     std::tie(P, nset, nway) = std::make_tuple(static_cast<uint32_t>(p), static_cast<uint32_t>(s), static_cast<uint32_t>(w));
-    cache->monitors->pause();
+    // cache->monitors->pause();
     static_cast<CT *>(cache)->remap_start();
     for(uint32_t ai = 0; ai < P; ai++){
       for(uint32_t idx = 0; idx < nset; idx++){
@@ -123,13 +124,16 @@ class InnerCohPortRemapT : public InnerCohPortT<InnerCohPortUncached, Policy, En
       }
     }
     static_cast<CT *>(cache)->remap_end();
-    cache->monitors->resume();
+    // cache->monitors->resume();
   }
   
   virtual void finish_resp(uint64_t addr, coh_cmd_t outer_cmd){
-    cache->monitors->magic_func(addr, MAGIC_ID_REMAP, &remap_flag);
-    if(remap_flag) remap();
-    remap_flag = false;
+    cache->monitors->magic_func(addr, MAGIC_ID_REMAP_ASK, &remap_flag);
+    if(remap_flag){
+      remap();
+      cache->monitors->magic_func(addr, MAGIC_ID_REMAP_END, nullptr);
+      remap_flag = false;
+    }
     InnerT::finish_resp(addr, outer_cmd);
   }
 
@@ -140,11 +144,13 @@ class InnerCohPortRemapT : public InnerCohPortT<InnerCohPortUncached, Policy, En
     auto[m_meta, m_data] = cache->access_line(new_ai, new_idx, new_way);
     uint64_t m_addr = m_meta->addr(new_idx); 
     if (m_meta->is_valid()) {
-      if (static_cast<MT *>(m_meta)->is_relocated()) this->evict(m_meta, m_data, new_ai, new_idx, new_way, nullptr);
-      else cache->hook_manage(m_addr, new_ai, new_idx, new_way, true, 1, false, m_meta, m_data, nullptr);
+      if (static_cast<MT *>(m_meta)->is_relocated())
+        this->evict(m_meta, m_data, new_ai, new_idx, new_way, nullptr);
+      else
+        cache->replace_manage(new_ai, new_idx, new_way, true, 1);
     }
     static_cast<CT *>(cache)->swap(m_addr, c_addr, m_meta, c_meta, m_data, c_data);
-    cache->hook_read(c_addr, new_ai, new_idx, new_way, false, false, m_meta, m_data, nullptr);
+    cache->replace_read(new_ai, new_idx, new_way, false);
     static_cast<MT *>(m_meta)->to_relocated();
     c_addr = m_addr;
   }
@@ -157,11 +163,10 @@ class InnerCohPortRemapT : public InnerCohPortT<InnerCohPortUncached, Policy, En
     auto c_data = data ? cache->data_copy_buffer() : nullptr;
     static_cast<CT *>(cache)->relocate(c_addr, meta, c_meta, data, c_data);
     static_cast<MT *>(meta)->to_relocated();
-    cache->hook_manage(c_addr, ai, idx, way, true, 1, false, c_meta, c_data, nullptr);
+    cache->replace_manage(ai, idx, way, true, 1);
+
+    while(c_meta->is_valid()) relocation(c_meta, c_data, c_addr);
 
-    while(c_meta->is_valid()){
-      relocation(c_meta, c_data, c_addr);
-    }
     cache->meta_return_buffer(c_meta);
     cache->data_return_buffer(c_data);
   }
@@ -177,15 +182,17 @@ class RemapperBase : public SimpleAccMonitor
 public:
   RemapperBase(bool remap_enable = true) : SimpleAccMonitor(true), remap_enable(remap_enable) {}
 
-  virtual void reset() override {
-    remap = false;
-    SimpleAccMonitor::reset();
-  }
-
   virtual bool magic_func(uint64_t cache_id, uint64_t addr, uint64_t magic_id, void *magic_data) override {
-    if (magic_id == MAGIC_ID_REMAP) {
-      if(remap_enable) *static_cast<bool*>(magic_data) |= remap;
+    if (magic_id == MAGIC_ID_REMAP_ASK) {
+      if(remap_enable){
+        *static_cast<bool*>(magic_data) |= remap;
+        if(remap) active = false;
+      }
+      return true;
+    }
+    if (magic_id == MAGIC_ID_REMAP_END) {
       remap = false;
+      active = true;
       return true;
     }
     return false;
@@ -259,15 +266,12 @@ class ZSEVRemapper : public RemapperBase
   }
   virtual void write(uint64_t cache_id, uint64_t addr, int32_t ai, int32_t s, int32_t w, bool hit, const CMMetadataBase *meta, const CMDataBase *data) override {
     if(!active) return;
-    cnt_access++; cnt_write++;
-    if(!hit) {  cnt_miss++; cnt_write_miss++;}
-    if(access_period != 0 && (cnt_access % access_period) == 0) {
-      if(Z_Score_detect()) {
-        remap = true;
-      }
-      evicts.fill(0);
+    cnt_write++;
+    if(!hit) {
+      cnt_write_miss++;
     }
   }
+
   virtual void invalid(uint64_t cache_id, uint64_t addr, int32_t ai, int32_t s, int32_t w, const CMMetadataBase *meta, const CMDataBase *data) override {
     if(!active) return;
     cnt_invalid++;
@@ -278,10 +282,22 @@ class ZSEVRemapper : public RemapperBase
     }
   }
 
-  virtual void reset() override {
-    evicts.fill(0);
-    set_evict_history.fill(0.0);
-    RemapperBase::reset();
+  virtual bool magic_func(uint64_t cache_id, uint64_t addr, uint64_t magic_id, void *magic_data) override {
+    if (magic_id == MAGIC_ID_REMAP_ASK) {
+      if(remap_enable){
+        *static_cast<bool*>(magic_data) |= remap;
+        if(remap) active = false;
+      }
+      return true;
+    }
+    if (magic_id == MAGIC_ID_REMAP_END) {
+      remap = false;
+      active = true;
+      cnt_access = 0; cnt_miss = 0; cnt_write = 0;  cnt_write_miss = 0; cnt_invalid = 0;
+      evicts.fill(0); set_evict_history.fill(0.0);
+      return true;
+    }
+    return false;
   }
 };
 
diff --git a/cache/exclusive.hpp b/cache/exclusive.hpp
index b44749e..202a75f 100644
--- a/cache/exclusive.hpp
+++ b/cache/exclusive.hpp
@@ -17,7 +17,7 @@ struct ExclusiveMSIPolicy : public MSIPolicy<false, uncached, Outer>    // alway
   static __always_inline void meta_after_grant(coh_cmd_t cmd, CMMetadataBase *meta, CMMetadataBase *meta_inner) { // after grant to inner
     int32_t id = cmd.id;
     if constexpr (EnDir) {
-      if(coh::is_fetch_read(cmd)) {
+      if(coh::is_fetch_read(cmd) || coh::is_prefetch(cmd)) {
         meta->to_shared(id);
         meta_inner->to_shared(-1);
       } else {
@@ -25,8 +25,8 @@ struct ExclusiveMSIPolicy : public MSIPolicy<false, uncached, Outer>    // alway
         meta_inner->to_modified(-1);
       }
     } else {
-      if(coh::is_fetch_read(cmd)) meta_inner->to_shared(-1);
-      else                        meta_inner->to_modified(-1);
+      if(coh::is_fetch_read(cmd) || coh::is_prefetch(cmd)) meta_inner->to_shared(-1);
+      else                                                 meta_inner->to_modified(-1);
 
       if(id != -1) meta->to_invalid();
       else         meta->to_shared(-1); // as the inner does not exist, state is shared
@@ -76,7 +76,7 @@ struct ExclusiveMESIPolicy : public ExclusiveMSIPolicy<isL1, uncached, Outer, En
   static __always_inline void meta_after_grant(coh_cmd_t cmd, CMMetadataBase *meta, CMMetadataBase *meta_inner) { // after grant to inner
     int32_t id = cmd.id;
     if(id != -1) { // inner cache is cached
-      if(coh::is_fetch_read(cmd)) {
+      if(coh::is_fetch_read(cmd) || coh::is_prefetch(cmd)) {
         meta->to_shared(id);
         if(static_cast<MetadataDirectoryBase *>(meta)->is_exclusive_sharer(id)) { // add the support for exclusive
           meta->to_exclusive(id);
@@ -89,8 +89,8 @@ struct ExclusiveMESIPolicy : public ExclusiveMSIPolicy<isL1, uncached, Outer, En
         meta_inner->to_modified(-1);
       }
     } else { // acquire from an uncached inner, still cache it in normal way as the inner does not exist
-      if(coh::is_fetch_read(cmd)) meta_inner->to_shared(-1);
-      else                        meta_inner->to_modified(-1);
+      if(coh::is_fetch_read(cmd) || coh::is_prefetch(cmd)) meta_inner->to_shared(-1);
+      else                                                 meta_inner->to_modified(-1);
       meta->to_shared(-1); // as the inner does not exist, state is shared
     }
     assert(!meta_inner->is_dirty());
@@ -127,37 +127,52 @@ class CacheSkewedExclusive : public CacheSkewed<IW, NW, P, MT, DT, IDX, RPC, DLY
     return true; // ToDo: support multithread
   }
 
-  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool prefetch, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
+  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
     if(ai < P) {
-      if(w >= NW) ext_replacer[ai].access(s, w-NW, true, prefetch);
-      else        replacer[ai].access(s, w, true, prefetch);
       if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_read(addr, ai, s, w, hit, meta, data, delay);
     } else {
       if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_read(addr, -1, -1, -1, hit, meta, data, delay);
     }
   }
 
-  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool demand_acc, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
+  virtual void replace_read(uint32_t ai, uint32_t s, uint32_t w, bool prefetch, bool genre = false) override {
+    if(ai < P) {
+      if(w >= NW) ext_replacer[ai].access(s, w-NW, true, prefetch);
+      else        replacer[ai].access(s, w, true, prefetch);
+    }
+  }
+
+  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
     if(ai < P) {
-      if(w >= NW) ext_replacer[ai].access(s, w-NW, demand_acc, false);
-      else        replacer[ai].access(s, w, demand_acc, false);
       if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_write(addr, ai, s, w, hit, meta, data, delay);
     } else {
       if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_write(addr, -1, -1, -1, hit, meta, data, delay);
     }
   }
 
+  virtual void replace_write(uint32_t ai, uint32_t s, uint32_t w, bool demand_acc, bool genre = false) override {
+    if(ai < P) {
+      if(w >= NW) ext_replacer[ai].access(s, w-NW, demand_acc, false);
+      else        replacer[ai].access(s, w, demand_acc, false);
+    } 
+  }
+
   virtual void hook_manage(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool writeback, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
     if(ai < P){
-      if(hit && evict) {
-        if(w >= NW) ext_replacer[ai].invalid(s, w-NW);
-        else        replacer[ai].invalid(s, w, evict == 2);
-      }
       if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_manage(addr, ai, s, w, hit, evict, writeback, meta, data, delay);
     } else {
       if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_manage(addr, -1, -1, -1, hit, evict, writeback, meta, data, delay);
     }
   }
+
+  virtual void replace_manage(uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool genre = false) override {
+    if(ai < P){
+      if(hit && evict) {
+        if(w >= NW) ext_replacer[ai].invalid(s, w-NW);
+        else        replacer[ai].invalid(s, w, evict == 2);
+      }
+    } 
+  }
 };
 
 // Norm Exclusive Cache
@@ -180,10 +195,12 @@ class ExclusiveInnerCohPortUncachedBroadcast : public InnerCohPortUncached<Polic
 public:
   virtual void acquire_resp(uint64_t addr, CMDataBase *data_inner, CMMetadataBase *meta_inner, coh_cmd_t cmd, uint64_t *delay) override {
     auto [meta, data, ai, s, w, hit] = access_line(addr, cmd, XactPrio::acquire, delay);
+    bool act_as_prefetch = coh::is_prefetch(cmd) && Policy::is_uncached(); // only tweak replace priority at the LLC accoridng to [Guo2022-MICRO]
 
     if (data_inner && data) data_inner->copy(data);
     Policy::meta_after_grant(cmd, meta, meta_inner);
-    cache->hook_read(addr, ai, s, w, hit, coh::is_prefetch(cmd), meta, data, delay);
+    if(!act_as_prefetch || !hit) cache->replace_read(ai, s, w, act_as_prefetch);
+    cache->hook_read(addr, ai, s, w, hit, meta, data, delay);
 
     cache->meta_return_buffer(meta);
     cache->data_return_buffer(data);
@@ -207,7 +224,7 @@ class ExclusiveInnerCohPortUncachedBroadcast : public InnerCohPortUncached<Polic
     }
 
     if(!probe_writeback) // need to fetch it from outer
-      outer->acquire_req(addr, meta, data, Policy::cmd_for_outer_acquire(cmd), delay);
+      outer->acquire_req(addr, meta, data, coh::is_prefetch(cmd) ? cmd : Policy::cmd_for_outer_acquire(cmd), delay);
 
     if(probe_hit && !coh::is_write(cmd)) // manually maintain the coherence if there are other inner copies, must be share
       meta->get_outer_meta()->to_shared(-1);
@@ -244,7 +261,8 @@ class ExclusiveInnerCohPortUncachedBroadcast : public InnerCohPortUncached<Polic
         if(mmeta->is_valid()) this->evict(mmeta, mdata, mai, ms, mw, delay);
         mmeta->init(addr); mmeta->copy(meta); meta->to_invalid();
         if(mdata) mdata->copy(data);
-        cache->hook_write(addr, mai, ms, mw, false, true, mmeta, mdata, delay); // a write occurred during the probe
+        cache->replace_write(mai, ms, mw, true);
+        cache->hook_write(addr, mai, ms, mw, false, mmeta, mdata, delay); // a write occurred during the probe
         cache->meta_return_buffer(meta);
         cache->data_return_buffer(data);
         return std::make_tuple(mmeta, mdata, mai, ms, mw, hit);
@@ -288,7 +306,8 @@ class ExclusiveInnerCohPortUncachedBroadcast : public InnerCohPortUncached<Polic
       if(meta->is_valid()) this->evict(meta, data, ai, s, w, delay);
       if(data_inner && data) data->copy(data_inner);
       meta->init(addr); Policy::meta_after_release(cmd, meta, meta_inner);
-      cache->hook_write(addr, ai, s, w, false, true, meta, data, delay);
+      cache->replace_write(ai, s, w, true);
+      cache->hook_write(addr, ai, s, w, false, meta, data, delay);
     }
   }
 
@@ -296,7 +315,7 @@ class ExclusiveInnerCohPortUncachedBroadcast : public InnerCohPortUncached<Polic
     if constexpr (!Policy::is_uncached()) {
       outer->writeback_req(addr, nullptr, nullptr, coh::cmd_for_flush(), delay);
     } else {
-      auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, XactPrio::flush, false, false, delay);
+      auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, XactPrio::flush, false, delay);
       auto [probe, probe_cmd] = Policy::flush_need_sync(cmd, meta);
 
       if(!hit) {
@@ -306,13 +325,17 @@ class ExclusiveInnerCohPortUncachedBroadcast : public InnerCohPortUncached<Polic
 
       if(probe) {
         auto [phit, pwb] = this->probe_req(addr, meta, data, probe_cmd, delay); // sync if necessary
-        if(pwb) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay); // a write occurred during the probe
+        if(pwb){
+          cache->replace_write(ai, s, w, false);
+          cache->hook_write(addr, ai, s, w, true, meta, data, delay); // a write occurred during the probe
+        }
       }
 
       auto writeback = Policy::writeback_need_writeback(meta);
       if(writeback.first) outer->writeback_req(addr, meta, data, writeback.second, delay); // writeback if dirty
 
       Policy::meta_after_flush(cmd, meta, cache);
+      cache->replace_manage(ai, s, w, hit, (coh::is_evict(cmd) ? 2 : 0));
       cache->hook_manage(addr, ai, s, w, hit, (coh::is_evict(cmd) ? 2 : 0), writeback.first, meta, data, delay);
 
       if(!hit) {
@@ -347,10 +370,12 @@ class ExclusiveInnerCohPortUncachedDirectory : public InnerCohPortUncached<Polic
 public:
   virtual void acquire_resp(uint64_t addr, CMDataBase *data_inner, CMMetadataBase *meta_inner, coh_cmd_t cmd, uint64_t *delay) override {
     auto [meta, data, ai, s, w, hit] = access_line(addr, cmd, XactPrio::acquire, delay);
+    bool act_as_prefetch = coh::is_prefetch(cmd) && Policy::is_uncached(); // only tweak replace priority at the LLC accoridng to [Guo2022-MICRO]
 
     if (data_inner && data) data_inner->copy(data);
     Policy::meta_after_grant(cmd, meta, meta_inner);
-    cache->hook_read(addr, ai, s, w, hit, coh::is_prefetch(cmd), meta, data, delay);
+    if(!act_as_prefetch || !hit) cache->replace_read(ai, s, w, act_as_prefetch);
+    cache->hook_read(addr, ai, s, w, hit, meta, data, delay);
 
     // difficult to know when data is borrowed from buffer, just return it.
     cache->data_return_buffer(data);
@@ -409,7 +434,7 @@ class ExclusiveInnerCohPortUncachedDirectory : public InnerCohPortUncached<Polic
           }
         }
         if(!pwb) { // still get it from outer
-          outer->acquire_req(addr, meta, data, Policy::cmd_for_outer_acquire(cmd), delay);
+          outer->acquire_req(addr, meta, data, coh::is_prefetch(cmd) ? cmd : Policy::cmd_for_outer_acquire(cmd), delay);
           hit = false;
         } else {
           auto [promote, promote_local, promote_cmd] = Policy::access_need_promote(cmd, meta);
@@ -430,7 +455,7 @@ class ExclusiveInnerCohPortUncachedDirectory : public InnerCohPortUncached<Polic
         std::tie(meta, data, ai, s, w) = replace_line_ext(addr, prio, delay);
         data = cache->data_copy_buffer();
       }
-      outer->acquire_req(addr, meta, data, Policy::cmd_for_outer_acquire(cmd), delay); // fetch the missing block
+      outer->acquire_req(addr, meta, data, coh::is_prefetch(cmd) ? cmd : Policy::cmd_for_outer_acquire(cmd), delay); // fetch the missing block
       return std::make_tuple(meta, data, ai, s, w, hit);
     }
   }
@@ -447,7 +472,8 @@ class ExclusiveInnerCohPortUncachedDirectory : public InnerCohPortUncached<Polic
       Policy::meta_after_release(cmd, meta, meta_inner);
       if(meta->is_extend()) outer->writeback_req(addr, meta, data, coh::cmd_for_release_writeback(), delay); // writeback if dirty
       assert(meta_inner); // assume meta_inner is valid for all writebacks
-      cache->hook_write(addr, ai, s, w, hit, true, meta, data, delay);
+      cache->replace_write(ai, s, w, true);
+      cache->hook_write(addr, ai, s, w, hit, meta, data, delay);
       cache->data_return_buffer(data); // return it anyway
     } else {
       bool phit = false;
@@ -470,7 +496,8 @@ class ExclusiveInnerCohPortUncachedDirectory : public InnerCohPortUncached<Polic
         mmeta->init(addr); mmeta->copy(meta); meta->to_invalid();
         if(data_inner && mdata) mdata->copy(data);
         Policy::meta_after_release(cmd, mmeta, meta_inner);
-        cache->hook_write(addr, mai, ms, mw, true, true, mmeta, mdata, delay);
+        cache->replace_write(mai, ms, mw, true);
+        cache->hook_write(addr, mai, ms, mw, true, mmeta, mdata, delay);
       }
       cache->data_return_buffer(data);
     }
@@ -480,7 +507,7 @@ class ExclusiveInnerCohPortUncachedDirectory : public InnerCohPortUncached<Polic
     if constexpr (!Policy::is_uncached()) {
       outer->writeback_req(addr, nullptr, nullptr, coh::cmd_for_flush(), delay);
     } else {
-      auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, XactPrio::flush, false, false, delay);
+      auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, XactPrio::flush, false, delay);
       auto [probe, probe_cmd] = Policy::flush_need_sync(cmd, meta);
       if(!hit) return;
 
@@ -488,13 +515,17 @@ class ExclusiveInnerCohPortUncachedDirectory : public InnerCohPortUncached<Polic
 
       if(probe) {
         auto [phit, pwb] = this->probe_req(addr, meta, data, probe_cmd, delay); // sync if necessary
-        if(pwb) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay); // a write occurred during the probe
+        if(pwb){
+          cache->replace_write(ai, s, w, false);
+          cache->hook_write(addr, ai, s, w, true, meta, data, delay); // a write occurred during the probe
+        }
       }
 
       auto writeback = Policy::writeback_need_writeback(meta);
       if(writeback.first) outer->writeback_req(addr, meta, data, writeback.second, delay); // writeback if dirty
 
       Policy::meta_after_flush(cmd, meta, cache);
+      cache->replace_manage(ai, s, w, hit, (coh::is_evict(cmd) ? 2 : 0));
       cache->hook_manage(addr, ai, s, w, hit, (coh::is_evict(cmd) ? 2 : 0), writeback.first, meta, data, delay);
 
       if(meta->is_extend()) cache->data_return_buffer(data);
@@ -531,7 +562,10 @@ class ExclusiveOuterCohPortBroadcastT : public OPUC<Policy, EnMT>
       meta = cache->meta_copy_buffer(); meta->init(addr); meta->get_outer_meta()->to_invalid();
       data = cache->data_copy_buffer();
       std::tie(probe_hit, probe_writeback) = inner->probe_req(addr, meta, data, sync.second, delay);
-      if(probe_writeback) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay);
+      if(probe_writeback){
+        cache->replace_write(ai, s, w, false);
+        cache->hook_write(addr, ai, s, w, true, meta, data, delay);
+      }
     }
 
     if(hit || probe_writeback) {
@@ -540,6 +574,7 @@ class ExclusiveOuterCohPortBroadcastT : public OPUC<Policy, EnMT>
     }
 
     Policy::meta_after_probe(outer_cmd, meta, meta_outer, coh_id, writeback);
+    cache->replace_manage(ai, s, w, hit, (coh::is_evict(outer_cmd) ? 1 : 0));
     cache->hook_manage(addr, ai, s, w, hit, (coh::is_evict(outer_cmd) ? 1 : 0), writeback, meta, data, delay);
 
     if(!hit) {
@@ -581,7 +616,10 @@ class ExclusiveOuterCohPortDirectoryT : public OPUC<Policy, EnMT>
         if(sync.first) {
           data = cache->data_copy_buffer();
           std::tie(probe_hit, probe_writeback) = inner->probe_req(addr, meta, data, sync.second, delay);
-          if(probe_writeback) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay);
+          if(probe_writeback){
+            cache->replace_write(ai, s, w, false);
+            cache->hook_write(addr, ai, s, w, true, meta, data, delay);
+          }
         }
       }
 
@@ -590,6 +628,7 @@ class ExclusiveOuterCohPortDirectoryT : public OPUC<Policy, EnMT>
     }
 
     Policy::meta_after_probe(outer_cmd, meta, meta_outer, coh_id, writeback);
+    cache->replace_manage(ai, s, w, hit, (coh::is_evict(outer_cmd) ? 1 : 0));
     cache->hook_manage(addr, ai, s, w, hit, (coh::is_evict(outer_cmd) ? 1 : 0), writeback, meta, data, delay);
 
     if(hit && meta->is_extend()) {
diff --git a/cache/memory.hpp b/cache/memory.hpp
index 55b410b..f2fc5a7 100644
--- a/cache/memory.hpp
+++ b/cache/memory.hpp
@@ -101,7 +101,7 @@ class SimpleMemoryModel : public InnerCohPortUncached<policy_memory, EnMT>, publ
       data_inner->write(mem_addr);
     }
     if(meta_inner) meta_inner->to_modified(-1);
-    hook_read(addr, 0, 0, 0, true, false, meta_inner, data_inner, delay);
+    hook_read(addr, 0, 0, 0, true, meta_inner, data_inner, delay);
 #ifdef CHECK_MULTI
     if constexpr (EnMT) active_addr_remove(addr);
 #endif
@@ -119,7 +119,7 @@ class SimpleMemoryModel : public InnerCohPortUncached<policy_memory, EnMT>, publ
       uint64_t *mem_addr = reinterpret_cast<uint64_t *>(page + offset);
       for(int i=0; i<8; i++) mem_addr[i] = data_inner->read(i);
     }
-    hook_write(addr, 0, 0, 0, true, true, meta_inner, data_inner, delay);
+    hook_write(addr, 0, 0, 0, true, meta_inner, data_inner, delay);
 #ifdef CHECK_MULTI
     if constexpr (EnMT) active_addr_remove(addr);
 #endif
@@ -130,11 +130,11 @@ class SimpleMemoryModel : public InnerCohPortUncached<policy_memory, EnMT>, publ
   // support run-time assign/reassign mointors
   void detach_monitor() { monitors->detach_monitor(); }
 
-  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool prefetch, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
+  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
     if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_read(addr, -1, -1, -1, hit, meta, data, delay);
   }
 
-  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool demand_acc, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
+  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) override {
     if constexpr (EnMon || !C_VOID<DLY>) monitors->hook_write(addr, -1, -1, -1, hit, meta, data, delay);
   }
 
diff --git a/cache/mesi.hpp b/cache/mesi.hpp
index 35bb0de..f00f3dd 100644
--- a/cache/mesi.hpp
+++ b/cache/mesi.hpp
@@ -19,7 +19,7 @@ struct MESIPolicy : public MSIPolicy<false, uncached, Outer>
 {
   static __always_inline void meta_after_grant(coh_cmd_t cmd, CMMetadataBase *meta, CMMetadataBase *meta_inner) {
     int32_t id = cmd.id;
-    if(coh::is_fetch_read(cmd)) {
+    if(coh::is_fetch_read(cmd) || coh::is_prefetch(cmd)) {
       meta->to_shared(id);
       if(static_cast<MetadataDirectoryBase *>(meta)->is_exclusive_sharer(id)) { // add the support for exclusive
         meta->to_exclusive(id);
diff --git a/cache/mirage.hpp b/cache/mirage.hpp
index 3c2a99c..271a241 100644
--- a/cache/mirage.hpp
+++ b/cache/mirage.hpp
@@ -164,32 +164,28 @@ class MirageCache : public CacheSkewed<IW, NW+EW, P, MT, void, MIDX, MRPC, DLY,
     return std::make_pair(d_s, d_w);
   }
 
-  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool prefetch, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) override {
-    if(ai < P) {
+  virtual void replace_read(uint32_t ai, uint32_t s, uint32_t w, bool prefetch, bool genre = false) override {
+    if(!genre && ai < P) {
       auto [ds, dw] = static_cast<MT *>(this->access(ai, s, w))->pointer();
       d_replacer.access(ds, dw, true, prefetch);
     }
-    CacheT::hook_read(addr, ai, s, w, hit, prefetch, meta, data, delay);
+    CacheT::replace_read(ai, s, w, prefetch);
   }
 
-  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool demand_acc, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) override {
-    if(ai < P) {
+  virtual void replace_write(uint32_t ai, uint32_t s, uint32_t w, bool demand_acc, bool genre = false) override {
+    if(!genre && ai < P) {
       auto [ds, dw] = static_cast<MT *>(this->access(ai, s, w))->pointer();
       d_replacer.access(ds, dw, demand_acc, false);
     }
-    CacheT::hook_write(addr, ai, s, w, hit, demand_acc, meta, data, delay);
+    CacheT::replace_write(ai, s, w, demand_acc);
   }
 
-  virtual void hook_manage(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool writeback, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) override {
-    if(ai < P && hit && evict) {
+  virtual void replace_manage(uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool genre = false) override {
+    if(!genre && ai < P && hit && evict) {
       auto [ds, dw] = static_cast<MT *>(this->access(ai, s, w))->pointer();
       d_replacer.invalid(ds, dw);
     }
-    CacheT::hook_manage(addr, ai, s, w, hit, evict, writeback, meta, data, delay);
-  }
-
-  void relocate_invalidate(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool writeback, const CMMetadataBase * meta, const CMDataBase *data, uint64_t *delay) {
-    CacheT::hook_manage(addr, ai, s, w, hit, evict, writeback, meta, data, delay);
+    CacheT::replace_manage(ai, s, w, hit, evict);
   }
 
   bool pre_finish_reloc(uint64_t addr, uint32_t s_ai, uint32_t s_s, uint32_t ai){
@@ -235,21 +231,21 @@ class MirageInnerPortUncached : public InnerCohPortUncached<Policy, EnMT>, prote
       auto buf_meta = cache->meta_copy_buffer();
       auto addr = meta->addr(s);
       cache->relocate(addr, meta, buf_meta);
-      cache->relocate_invalidate(addr, ai, s, w, true, 1, false, nullptr, nullptr, delay);
+      cache->replace_manage(ai, s, w, true, 1, true);
       while(buf_meta->is_valid()){
         relocation++;
         cache->replace(addr, &m_ai, &m_s, &m_w, XactPrio::acquire, replace_for_relocate);
         auto m_meta = static_cast<MT *>(cache->access(m_ai, m_s, m_w));
         auto m_addr = m_meta->addr(m_s);
         if (m_meta->is_valid()) {
-          if (relocation >= MaxRelocN || cache->pre_finish_reloc(m_addr, ai, s, m_ai)){
+          if (relocation >= MaxRelocN || cache->pre_finish_reloc(m_addr, ai, s, m_ai))
             global_evict(m_meta, cache->get_data_data(static_cast<MT *>(m_meta)), m_ai, m_s, w, delay); // associative eviction!
-          }
-          else cache->relocate_invalidate(m_addr, m_ai, m_s, m_w, true, 1, false, nullptr, nullptr, delay);
+          else
+            cache->replace_manage(m_ai, m_s, m_w, true, 1, true);
         }
         cache->swap(m_addr, addr, m_meta, buf_meta, nullptr, nullptr);
         cache->get_data_meta(static_cast<MT *>(m_meta))->bind(m_ai, m_s, m_w);
-        cache->hook_read(addr, m_ai, m_s, m_w, false, false, nullptr, nullptr, delay);
+        cache->replace_read(m_ai, m_s, m_w, false, true);
         addr = m_addr;
       }
       cache->meta_return_buffer(buf_meta);
@@ -268,12 +264,15 @@ class MirageInnerPortUncached : public InnerCohPortUncached<Policy, EnMT>, prote
   virtual std::tuple<CMMetadataBase *, CMDataBase *, uint32_t, uint32_t, uint32_t, bool>
   access_line(uint64_t addr, coh_cmd_t cmd, uint16_t prio, uint64_t *delay) override { // common function for access a line in the cache
     auto cache = static_cast<CT *>(InnerCohPortBase::cache);
-    auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, prio, true, false, delay);
+    auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, prio, true, delay);
     if(hit) {
       auto sync = Policy::access_need_sync(cmd, meta);
       if(sync.first) {
         auto [phit, pwb] = this->probe_req(addr, meta, data, sync.second, delay); // sync if necessary
-        if(pwb) cache->hook_write(addr, ai, s, w, true, false, meta, data, delay); // a write occurred during the probe
+        if(pwb){
+          cache->replace_write(ai, s, w, false);
+          cache->hook_write(addr, ai, s, w, true, meta, data, delay); // a write occurred during the probe
+        }
       }
       auto [promote, promote_local, promote_cmd] = Policy::access_need_promote(cmd, meta);
       if(promote) { outer->acquire_req(addr, meta, data, promote_cmd, delay); hit = false; } // promote permission if needed
@@ -281,30 +280,17 @@ class MirageInnerPortUncached : public InnerCohPortUncached<Policy, EnMT>, prote
     } else { // miss
       if(meta->is_valid()) evict(meta, data, ai, s, w, delay);
       bind_data(addr, meta, data, ai, s, w, delay);
-      outer->acquire_req(addr, meta, data, Policy::cmd_for_outer_acquire(cmd), delay); // fetch the missing block
+      outer->acquire_req(addr, meta, data, coh::is_prefetch(cmd) ? cmd : Policy::cmd_for_outer_acquire(cmd), delay); // fetch the missing block
     }
     return std::make_tuple(meta, data, ai, s, w, hit);
   }
 
   virtual void flush_line(uint64_t addr, coh_cmd_t cmd, uint64_t *delay) {
-    auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, XactPrio::flush, false, false, delay);
+    auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, XactPrio::flush, false, delay);
     if(!hit) return;
     Inner::flush_line(addr, cmd, delay);
     static_cast<CT *>(InnerCohPortBase::cache)->get_data_meta(static_cast<MT *>(meta))->to_invalid();
   }
-
-  virtual void prefetch_line(uint64_t addr, coh_cmd_t cmd, uint64_t *delay) {
-    auto cache = static_cast<CT *>(InnerCohPortBase::cache);
-    auto [hit, meta, data, ai, s, w] = this->check_hit_or_replace(addr, XactPrio::acquire, true, true, delay);
-    if(!hit) {
-      if(meta->is_valid()) evict(meta, data, ai, s, w, delay);
-      bind_data(addr, meta, data, ai, s, w, delay);
-      outer->acquire_req(addr, meta, data, coh::cmd_for_prefetch(), delay); // fetch the missing block
-      cache->hook_read(addr, ai, s, w, hit, true, meta, data, delay);
-      this->finish_record(addr, coh::cmd_for_finish(-1), !hit, meta, ai, s);
-      this->finish_resp(addr, coh::cmd_for_finish(-1));
-    }
-  }
 };
 
 // template helper for pass the compiler
diff --git a/cache/msi.hpp b/cache/msi.hpp
index c683bc6..15fd21a 100644
--- a/cache/msi.hpp
+++ b/cache/msi.hpp
@@ -57,7 +57,7 @@ struct MSIPolicy : public MIPolicy<isL1, uncached, Outer>
 
   static __always_inline void meta_after_grant(coh_cmd_t cmd, CMMetadataBase *meta, CMMetadataBase *meta_inner) {
     int32_t id = cmd.id;
-    if(coh::is_fetch_read(cmd)) {
+    if(coh::is_fetch_read(cmd) || coh::is_prefetch(cmd)) {
       meta->to_shared(id);
       meta_inner->to_shared(-1);
     } else {
diff --git a/cache/replace.hpp b/cache/replace.hpp
index 4a9c96d..2f92a17 100644
--- a/cache/replace.hpp
+++ b/cache/replace.hpp
@@ -326,7 +326,7 @@ class ReplaceRandom : public ReplaceFuncBase<EF, NW, EnMT>
   }
 
   virtual uint32_t eviction_rank(uint32_t s, uint32_t w) const {
-    return (*loc_random)() % NW;
+    return NW/2;
   }
 };
 
diff --git a/regression/c2-l2-mirage.expect b/regression/c2-l2-mirage.expect
index d1743ce..51ef5da 100644
--- a/regression/c2-l2-mirage.expect
+++ b/regression/c2-l2-mirage.expect
@@ -3232,8 +3232,6 @@ mem        read  0000a90ecf11c380 -1 -001 -1 1 [McW] 0000000000000000
 l2         read  0000a90ecf11c380 00 0007 02 0 [McW(0012,06)] 0000000000000000
 l1d-0      write 0000a90ecf11c380 00 0014 01 0 [MdW] aac2b62c13e78085
 l1d-1      evict 000072629a2641c0 00 0007 03   [IcR] cff65dd3605c7fe3
-l2         evict 00002feadfa86d40 01 0021 01  
-l2         read  00002feadfa86d40 00 0020 00 0
 mem        read  00007a76f01141c0 -1 -001 -1 1 [McW] 4f7e9691e6e6e9e9
 l2         read  00007a76f01141c0 01 0021 01 0 [ScW(0002,01)] 4f7e9691e6e6e9e9
 l1d-1      read  00007a76f01141c0 00 0007 03 0 [ScR] 4f7e9691e6e6e9e9
@@ -4317,8 +4315,6 @@ l2         evict 00004d48d3ab6400 00 0025 00   [IcR(0005,00)] 0bad902dc5dbfa0f
 mem        read  000031e4a2646740 -1 -001 -1 1 [McW] 613b6d57ad34e57a
 l2         read  000031e4a2646740 01 0019 03 0 [ScW(0005,00)] 613b6d57ad34e57a
 l1d-1      read  000031e4a2646740 00 0013 03 0 [ScR] 613b6d57ad34e57a
-l2         evict 00004cfb5e6fc8c0 01 0015 00  
-l2         read  00004cfb5e6fc8c0 00 0002 03 0
 mem        write 0000b304f6dcc000 -1 -001 -1 1 [MdW] fb80ed3c4e7012f9
 l2         evict 0000b304f6dcc000 01 0016 03   [IcR(0006,04)] fb80ed3c4e7012f9
 mem        read  000066e78b358f00 -1 -001 -1 1 [McW] 50bcdb51cf5071b0
@@ -4522,10 +4518,6 @@ l2         write 000037bf6ed61cc0 00 0025 04 1 [MdW(0019,02)] 2e7d5828d25f0433
 l1d-0      evict 000037bf6ed61cc0 00 0003 02   [IcR] 2e7d5828d25f0433
 l2         read  0000534534d814c0 01 0030 00 1 [SdW(0019,06)] 8026669fe9d83abe
 l1d-0      read  0000534534d814c0 00 0003 02 0 [ScR] 8026669fe9d83abe
-l2         evict 000042ff28b0ea40 01 0023 00  
-l2         evict 00005e644f2ad540 00 0031 00  
-l2         read  000042ff28b0ea40 00 0031 00 0
-l2         read  00005e644f2ad540 01 0010 04 0
 mem        write 000048777e448ac0 -1 -001 -1 1 [MdW] cabd092ab80dc469
 l2         evict 000048777e448ac0 00 0017 04   [IcR(0016,00)] cabd092ab80dc469
 mem        read  0000f0d349d6ba00 -1 -001 -1 1 [McW] 87e448736b086b82
@@ -4922,12 +4914,8 @@ l1d-0      write 0000d3afe5d1ca40 00 0009 00 0 [MdW] a3d8e10393750a6f
 l1d-0      evict 0000e0ad5d373580 00 0006 01   [IcR] 06512cc805fd57c0
 l2         read  00002b4766af8580 00 0026 00 1 [SdW(0024,06)] e2d7bd4ad76f6849
 l1d-0      read  00002b4766af8580 00 0006 01 0 [ScR] e2d7bd4ad76f6849
-l2         evict 00002c1e14cbed40 01 0021 02  
-l2         evict 0000a941be991f00 00 0004 04  
-l2         read  00002c1e14cbed40 00 0004 04 0
 mem        write 000036c3a1e16900 -1 -001 -1 1 [MdW] d87c000743707e28
 l2         evict 000036c3a1e16900 01 0007 02   [IcR(0025,03)] d87c000743707e28
-l2         read  0000a941be991f00 01 0007 00 0
 l1d-0      evict 000030295cbb89c0 00 0007 02   [IcR] 0053d6a34dc70a2d
 l2         write 000030295cbb89c0 01 0015 01 1 [MdW(0023,07)] 0053d6a34dc70a2d
 mem        write 000030295cbb89c0 -1 -001 -1 1 [MdW] 0053d6a34dc70a2d
@@ -5003,8 +4991,6 @@ l1d-0      read  00002cbcc4bef440 00 0001 03 0 [ScR] bdb198bed3f166c8
 l1d-0      read  0000750cdfd9ed40 00 0005 01 1 [MdW] 14116ffad10ecda8
 l1i-1      read  0000b7fc8ec73280 00 0010 01 1 [ScR] 82cac3e599046a61
 l1d-0      evict 0000d6eae7df0a40 00 0009 03   [IcR] c8a334c853d1650e
-l2         evict 0000d6eae7df0a40 00 0020 00  
-l2         read  0000d6eae7df0a40 01 0025 00 0
 l1d-1      evict 0000b3031ae484c0 00 0003 01   [IcR] 0c4ecbd8ebb1420f
 l2         write 0000b3031ae484c0 01 0007 03 1 [MdW(0018,07)] 0c4ecbd8ebb1420f
 mem        write 0000b3031ae484c0 -1 -001 -1 1 [MdW] 0c4ecbd8ebb1420f
@@ -5062,8 +5048,6 @@ l1d-0      write 0000c86d27a3d040 00 0001 01 0 [MdW] 796aa0a9427c2e02
 l2         read  0000c7e07b801e00 01 0001 00 1 [McW(0023,06)] edaed707c9f0d11e
 l1d-0      write 0000c7e07b801e00 00 0008 01 0 [MdW] f5b0b925ea9fb0ef
 l1d-1      evict 00002e867eb6a900 00 0004 02   [IcR] e69494168320e39a
-l2         evict 0000deaf8d449780 00 0020 01  
-l2         read  0000deaf8d449780 01 0012 04 0
 l2         evict 00007d0902e50f80 00 0023 01   [IcR(0008,01)] 7acc9b6fe084c114
 mem        read  0000d8ad57bdad00 -1 -001 -1 1 [McW] d54d77b5577490c8
 l2         read  0000d8ad57bdad00 00 0020 01 0 [ScW(0008,01)] d54d77b5577490c8
@@ -5071,10 +5055,6 @@ l1d-1      read  0000d8ad57bdad00 00 0004 02 0 [ScR] d54d77b5577490c8
 l1d-1      read  00007e3437831800 00 0000 02 1 [MdW] af1f8f40af24a4a3
 l1d-0      read  000042cda8d19c00 00 0000 01 1 [MdW] 101b1b2079f8e967
 l1d-1      evict 000028a2a5cc7780 00 0014 01   [IcR] c2b3bde410eeed99
-l2         evict 0000b9927026ea40 00 0000 01  
-l2         evict 00004e67a6d81700 01 0023 01  
-l2         read  0000b9927026ea40 01 0023 01 0
-l2         read  00004e67a6d81700 00 0025 04 0
 l1d-0      evict 00002cbcc4bef440 00 0001 03   [IcR] bdb198bed3f166c8
 mem        write 00002cbcc4bef440 -1 -001 -1 1 [MdW] bdb198bed3f166c8
 l2         evict 00002cbcc4bef440 00 0001 00   [IcR(0009,06)] bdb198bed3f166c8
@@ -5161,8 +5141,6 @@ l1d-0      evict 0000a6f9f0803d80 00 0006 02   [IcR] 5719b2c00ecac89a
 l2         read  0000c662cc646980 01 0025 03 1 [ScW(0020,00)] 6794a45adab0c5a6
 l1d-0      read  0000c662cc646980 00 0006 02 0 [ScR] 6794a45adab0c5a6
 l1d-0      evict 00000701e403e980 00 0006 03   [IcR] a2b07763fc09116e
-l2         evict 00006cf58254d780 01 0007 02  
-l2         read  00006cf58254d780 00 0011 01 0
 mem        write 00008aa559520900 -1 -001 -1 1 [MdW] 4d6a292f5a35e768
 l2         evict 00008aa559520900 01 0024 02   [IcR(0025,07)] 4d6a292f5a35e768
 mem        read  0000e461479ae980 -1 -001 -1 1 [McW] f44a40aa263a924f
diff --git a/regression/c2-l2-remap.expect b/regression/c2-l2-remap.expect
index 69570f7..f0989ac 100644
--- a/regression/c2-l2-remap.expect
+++ b/regression/c2-l2-remap.expect
@@ -1237,6 +1237,8 @@ l2         evict 0000fa4efe47a000 00 0009 01   [IcR] df2c433ed877cb6c
 mem        read  000066e78b358f00 -1 -001 -1 1 [McW] 9d96c52a7d69d60e
 l2         read  000066e78b358f00 00 0009 01 0 [ScW] 9d96c52a7d69d60e
 l1d-0      read  000066e78b358f00 00 0012 02 0 [ScR] 9d96c52a7d69d60e
+mem        write 0000a6f9f0803d80 -1 -001 -1 1 [MdW] c0f82e8e69025d47
+l2         evict 0000a6f9f0803d80 00 0030 04   [IcR] c0f82e8e69025d47
 l2         write 0000ced5eac0d680 00 0022 05 1 [MdW] 286cd5e99abee408
 l1d-0      evict 0000ced5eac0d680 00 0010 00   [IcR] 286cd5e99abee408
 mem        read  00007121fd387e80 -1 -001 -1 1 [McW] 0000000000000000
diff --git a/util/monitor.hpp b/util/monitor.hpp
index a042808..8a57d32 100644
--- a/util/monitor.hpp
+++ b/util/monitor.hpp
@@ -71,8 +71,8 @@ class CacheMonitorSupport
   MonitorContainerBase *monitors; // monitor container
 
   // hook interface for replacer state update, Monitor and delay estimation
-  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool prefetch, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) = 0;
-  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, bool demand_acc, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) = 0;
+  virtual void hook_read(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) = 0;
+  virtual void hook_write(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) = 0;
   // probe, invalidate and writeback
   virtual void hook_manage(uint64_t addr, uint32_t ai, uint32_t s, uint32_t w, bool hit, uint32_t evict, bool writeback, const CMMetadataBase *meta, const CMDataBase *data, uint64_t *delay) = 0;
   // an interface for special communication with a specific monitor if attached