Verilog variant: mcpu.v:46: Case values incompletely covered (example pattern 0x0)

[yurivict]

https://github.com/cpldcpu/MCPU/blob/master/verilog/MCPU_0.1a.v#L50

Verilator complains:

%Warning-CASEINCOMPLETE: mcpu.v:46: Case values incompletely covered (example pattern 0x0)
   case(states)
   ^~~~
                         ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
%Error: Command Failed /usr/local/bin/verilator_bin -Wall --cc mcpu.v --exe sim_main.cpp

The VHDL variant has when others => null; at this place.

[cpldcpu]

Note sure why this occurs, maybe verilator is more strict.

Anyhow, can you submit a pull request to fix this?