-
Notifications
You must be signed in to change notification settings - Fork 3
/
Copy pathnvme.c
3616 lines (3166 loc) · 115 KB
/
nvme.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* QEMU NVM Express Controller
*
* Copyright (c) 2012, Intel Corporation
*
* Written by Keith Busch <[email protected]>
*
* This code is licensed under the GNU GPL v2 or later.
*/
/**
* Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
*
* http://www.nvmexpress.org/resources/
*/
/**
* Usage: add options:
* -drive file=<file>,if=none,id=<drive_id>
* -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>
*
* The "file" option must point to a path to a real file that you will use as
* the backing storage for your NVMe device. It must be a non-zero length, as
* this will be the disk image that your nvme controller will use to carve up
* namespaces for storage.
*
* Note the "drive" option's "id" name must match the "device nvme" drive's
* name to link the block device used for backing storage to the nvme
* interface.
*
* Advanced optional options:
*
* namespaces=<int> : Namespaces to make out of the backing storage, Default:1
* queues=<int> : Number of possible IO Queues, Default:64
* entries=<int> : Maximum number of Queue entires possible, Default:0x7ff
* max_cqes=<int> : Maximum completion queue entry size, Default:0x4
* max_sqes=<int> : Maximum submission queue entry size, Default:0x6
* mpsmin=<int> : Minimum page size supported, Default:0
* mpsmax=<int> : Maximum page size supported, Default:0
* stride=<int> : Doorbell stride, Default:0
* aerl=<int> : Async event request limit, Default:3
* acl=<int> : Abort command limit, Default:3
* elpe=<int> : Error log page entries, Default:3
* mdts=<int> : Maximum data transfer size, Default:5
* cqr=<int> : Contiguous queues required, Default:1
* vwc=<int> : Volatile write cache enabled, Default:0
* intc=<int> : Interrupt configuration disabled, Default:0
* intc_thresh=<int>: Interrupt coalesce threshold, Default:0
* intc_ttime=<int> : Interrupt coalesce time 100's of usecs, Default:0
* nlbaf=<int> : Number of logical block formats, Default:1
* lba_index=<int> : Default namespace block format index, Default:0
* extended=<int> : Use extended-lba for meta-data, Default:0
* dpc=<int> : Data protection capabilities, Default:0
* dps=<int> : Data protection settings, Default:0
* mc=<int> : Meta-data capabilities, Default:0
* meta=<int> : Meta-data size, Default:0
* oncs=<oncs> : Optional NVMe command support, Default:DSM
* oacs=<oacs> : Optional Admin command support, Default:Format
* cmbsz=<cmbsz> : Controller Memory Buffer CMBSZ register, Default:0
* cmbloc=<cmbloc> : Controller Memory Buffer CMBLOC register, Default:0
* lver=<int> : version of the LightNVM standard to use, Default:1
* ll2pmode=<int> : LightNVM op. mode. 1: hybrid, 0: full host-based. Default: 1
* lsec_size=<int> : Controller Sector Size. Default: 4096
* lsecs_per_pg=<int> : Number of sectors in a flash page. Default: 1
* lpgs_per_blk=<int> : Number of pages per flash block. Default: 256
* lmax_sec_per_rq=<int> : Maximum number of sectors per I/O request. Default: 64
* lmtype=<int> : Media type. Default: 0 (NAND Flash Memory)
* lfmtype=<int> : Flash media type. Default: 0 (SLC)
* lnum_ch=<int> : Number of controller channels. Default: 1
* lnum_lun=<int> : Number of LUNs per channel, Default:1
* lnum_pln=<int> : Number of flash planes per LUN. Supported single (1),
* dual (2) and quad (4) plane modes. Defult: 1
* lreadl2ptbl=<int> : Load logical to physical table. 1: yes, 0: no. Default: 1
* lbbtable=<file> : Load bad block table from file destination (Provide path
* to file. If no file is provided a bad block table will be generated. Look
* at lbbfrequency. Default: Null (no file).
* lbbfrequency:<int> : Bad block frequency for generating bad block table. If
* no frequency is provided LNVM_DEFAULT_BB_FREQ will be used.
* lmetadata=<file> : Load metadata from file destination
* lmetasize=<int> : LightNVM metadata (OOB) size. Default: 16
* lb_err_write : First ppa to inject write error. Default: 0 (disabled)
* ln_err_write : Number of ppas affected by write error injection
* ldebug : Enable LightNVM debugging. Default: 0 (disabled)
* lstrict : Enable strict checks. Necessary for pblk (disabled)
*
*
* The logical block formats all start at 512 byte blocks and double for the
* next index. If meta-data is non-zero, half the logical block formats will
* have 0 meta-data, the remaining will start the block size over at 512, but
* with the meta-data size set accordingly. Multiple meta-data sizes are not
* supported.
*
* Parameters will be verified against conflicting capabilities and attributes
* and fail to load if there is a conflict or a configuration the emulated
* device is unable to handle.
*
* Note that when a CMB is requested the NVMe version is set to 1.2,
* for all other cases it is set to 1.1.
*
*/
/**
* Hot-plug support
*
* To hot add a new nvme device, startup the qemu monitor. The easiest way is
* to add '-monitor stdio' option on your startup. At the monitor command line,
* run:
*
* (qemu) drive_add "" if=none,id=<new_drive_id>,file=</path/to/backing/file>
* (qemu) device_add nvme,drive=<new_drive_id>,serial=<serial>,id=<new_id>[,<optional options>]
*
* To hot remove the device, run:
*
* (qemu) device_del <id>
*
* You must have provided the "id" field for device_del to work. You may query
* the available devices by running "info pci" from the qemu monitor.
*
* To query what disks are available to be used as a backing storage, run "info
* block". You cannot assign the same block device to more than one storage
* interface.
*/
/**
* Controller Memory Buffer: For now, you can only turn it on or off, but can't
* tune the exact settings.
*/
#include <block/block_int.h>
#include <block/qapi.h>
#include <exec/memory.h>
#include <hw/block/block.h>
#include <hw/hw.h>
#include <hw/pci/msix.h>
#include <hw/pci/msi.h>
#include <hw/pci/pci.h>
#include <qapi/visitor.h>
#include <qemu/bitops.h>
#include <qemu/bitmap.h>
#include <sysemu/sysemu.h>
#include <sysemu/block-backend.h>
#include <qemu/main-loop.h>
#include "nvme.h"
#include "trace.h"
#define NVME_MAX_QS PCI_MSIX_FLAGS_QSIZE
#define NVME_MAX_QUEUE_ENTRIES 0xffff
#define NVME_MAX_STRIDE 12
#define NVME_MAX_NUM_NAMESPACES 256
#define NVME_MAX_QUEUE_ES 0xf
#define NVME_MIN_CQUEUE_ES 0x4
#define NVME_MIN_SQUEUE_ES 0x6
#define NVME_SPARE_THRESHOLD 20
#define NVME_TEMPERATURE 0x143
#define NVME_OP_ABORTED 0xff
#define LNVM_MAX_GRPS_PR_IDENT (20)
#define LNVM_FEAT_EXT_START 64
#define LNVM_FEAT_EXT_END 127
#define LNVM_PBA_UNMAPPED UINT64_MAX
#define LNVM_LBA_UNMAPPED UINT64_MAX
static void nvme_process_sq(void *opaque);
static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (n->cmbsz && addr >= n->ctrl_mem.addr &&
addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) {
memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size);
//if it's not use cmb, ussing dma directly.
} else {
pci_dma_read(&n->parent_obj, addr, buf, size);
}
}
static void nvme_addr_write(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (n->cmbsz && addr >= n->ctrl_mem.addr &&
addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) {
memcpy((void *)&n->cmbuf[addr - n->ctrl_mem.addr], buf, size);
return;
} else {
pci_dma_write(&n->parent_obj, addr, buf, size);
}
}
static uint8_t lnvm_dev(NvmeCtrl *n)
{
return (n->lnvm_ctrl.id_ctrl.ver_id != 0);
}
static uint8_t lnvm_hybrid_dev(NvmeCtrl *n)
{
return (n->lnvm_ctrl.id_ctrl.dom == 1);
}
static void lnvm_tbl_initialize(NvmeNamespace *ns)
{
uint32_t len = ns->tbl_entries;
uint32_t i;
for (i = 0; i < len; i++)
ns->tbl[i] = LNVM_LBA_UNMAPPED;
}
static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
{
return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1;
}
static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
{
return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1;
}
static void nvme_inc_cq_tail(NvmeCQueue *cq)
{
cq->tail++;
if (cq->tail >= cq->size) {
cq->tail = 0;
cq->phase = !cq->phase;
}
}
static int nvme_cqes_pending(NvmeCQueue *cq)
{
return cq->tail > cq->head ?
cq->head + (cq->size - cq->tail) :
cq->head - cq->tail;
}
static void nvme_inc_sq_head(NvmeSQueue *sq)
{
sq->head = (sq->head + 1) % sq->size;
}
static void nvme_update_cq_head(NvmeCQueue *cq)
{
if (cq->db_addr) {
nvme_addr_read(cq->ctrl, cq->db_addr, &cq->head, sizeof(cq->head));
}
}
static uint8_t nvme_cq_full(NvmeCQueue *cq)
{
nvme_update_cq_head(cq);
return (cq->tail + 1) % cq->size == cq->head;
}
static uint8_t nvme_sq_empty(NvmeSQueue *sq)
{
return sq->head == sq->tail;
}
static void nvme_isr_notify(void *opaque)
{
NvmeCQueue *cq = opaque;
NvmeCtrl *n = cq->ctrl;
if (cq->irq_enabled) {
if (msix_enabled(&(n->parent_obj))) {
msix_notify(&(n->parent_obj), cq->vector);
} else if (msi_enabled(&(n->parent_obj))) {
if (!(n->bar.intms & (1 << cq->vector))) {
msi_notify(&(n->parent_obj), cq->vector);
}
} else {
pci_irq_pulse(&n->parent_obj);
}
}
}
static uint64_t *nvme_setup_discontig(NvmeCtrl *n, uint64_t prp_addr,
uint16_t queue_depth, uint16_t entry_size)
{
int i;
uint16_t prps_per_page = n->page_size >> 3;
uint64_t prp[prps_per_page];
uint16_t total_prps = DIV_ROUND_UP(queue_depth * entry_size, n->page_size);
uint64_t *prp_list = g_malloc0(total_prps * sizeof(*prp_list));
for (i = 0; i < total_prps; i++) {
if (i % prps_per_page == 0 && i < total_prps - 1) {
if (!prp_addr || prp_addr & (n->page_size - 1)) {
g_free(prp_list);
return NULL;
}
nvme_addr_write(n, prp_addr, (uint8_t *)&prp, sizeof(prp));
prp_addr = le64_to_cpu(prp[prps_per_page - 1]);
}
prp_list[i] = le64_to_cpu(prp[i % prps_per_page]);
if (!prp_list[i] || prp_list[i] & (n->page_size - 1)) {
g_free(prp_list);
return NULL;
}
}
return prp_list;
}
static hwaddr nvme_discontig(uint64_t *dma_addr, uint16_t page_size,
uint16_t queue_idx, uint16_t entry_size)
{
uint16_t entries_per_page = page_size / entry_size;
uint16_t prp_index = queue_idx / entries_per_page;
uint16_t index_in_prp = queue_idx % entries_per_page;
return dma_addr[prp_index] + index_in_prp * entry_size;
}
static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov,
uint64_t prp1, uint64_t prp2, uint32_t len, NvmeCtrl *n)
{
hwaddr trans_len = n->page_size - (prp1 % n->page_size);
trans_len = MIN(len, trans_len);
int num_prps = (len >> n->page_bits) + 1;
bool cmb = false;
if (!prp1) {
return NVME_INVALID_FIELD | NVME_DNR;
} else if (n->cmbsz && prp1 >= n->ctrl_mem.addr &&
prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) {
cmb = true;
qsg->nsg = 0;
qemu_iovec_init(iov, num_prps);
qemu_iovec_add(iov, (void *)&n->cmbuf[prp1 - n->ctrl_mem.addr], trans_len);
} else {
pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
qemu_sglist_add(qsg, prp1, trans_len);
}
len -= trans_len;
if (len) {
if (!prp2) {
goto unmap;
}
if (len > n->page_size) {
uint64_t prp_list[n->max_prp_ents];
uint32_t nents, prp_trans;
int i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
while (len != 0) {
uint64_t prp_ent = le64_to_cpu(prp_list[i]);
if (i == n->max_prp_ents - 1 && len > n->page_size) {
if (!prp_ent || prp_ent & (n->page_size - 1)) {
goto unmap;
}
i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
nvme_addr_read(n, prp_ent, (void *)prp_list,
prp_trans);
prp_ent = le64_to_cpu(prp_list[i]);
}
if (!prp_ent || prp_ent & (n->page_size - 1)) {
goto unmap;
}
trans_len = MIN(len, n->page_size);
if (!cmb){
qemu_sglist_add(qsg, prp_ent, trans_len);
} else {
qemu_iovec_add(iov, (void *)&n->cmbuf[prp_ent - n->ctrl_mem.addr], trans_len);
}
len -= trans_len;
i++;
}
} else {
if (prp2 & (n->page_size - 1)) {
goto unmap;
}
if (!cmb) {
qemu_sglist_add(qsg, prp2, len);
} else {
qemu_iovec_add(iov, (void *)&n->cmbuf[prp2 - n->ctrl_mem.addr], trans_len);
}
}
}
return NVME_SUCCESS;
unmap:
if (!cmb){
qemu_sglist_destroy(qsg);
} else {
qemu_iovec_destroy(iov);
}
return NVME_INVALID_FIELD | NVME_DNR;
}
static uint16_t nvme_dma_write_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
uint64_t prp1, uint64_t prp2)
{
QEMUSGList qsg;
QEMUIOVector iov;
uint16_t status = NVME_SUCCESS;
if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
return NVME_INVALID_FIELD | NVME_DNR;
}
if (qsg.nsg > 0) {
if (dma_buf_write(ptr, len, &qsg)) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
} else {
if (qemu_iovec_from_buf(&iov, 0, ptr, len) != len) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
}
return status;
}
static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
uint64_t prp1, uint64_t prp2)
{
QEMUSGList qsg;
QEMUIOVector iov;
uint16_t status = NVME_SUCCESS;
if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
return NVME_INVALID_FIELD | NVME_DNR;
}
if (qsg.nsg > 0) {
if (dma_buf_read(ptr, len, &qsg)) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
} else {
if (qemu_iovec_to_buf(&iov, 0, ptr, len) != len) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
}
return status;
}
static void lnvm_inject_w_err(LnvmCtrl *ln, NvmeRequest *req, NvmeCqe *cqe)
{
if (ln->err_write && req->is_write) {
if (ln->debug)
printf("nvme:err_stat:err_write_cnt:%d,nppas:%d,err_write:%d, n_err_write:%d\n",
ln->err_write_cnt, req->nlb, ln->err_write, ln->n_err_write);
if ((ln->err_write_cnt + req->nlb) > ln->err_write) {
int i;
int bit;
/* kill n_err_write sectors in ppa list */
for (i = 0; i < req->nlb; i++) {
if (ln->err_write_cnt + i < ln->err_write)
continue;
bit = i;
bitmap_set(&cqe->res64, bit, ln->n_err_write);
break;
}
if (ln->debug)
printf("nvme: injected error:%u, n:%u, bitmap:%lu\n",
bit, ln->n_err_write, cqe->res64);
req->status = 0x40ff; /* FAIL WRITE status code */
ln->err_write_cnt = 0;
}
ln->err_write_cnt += req->nlb;
}
}
static void lnvm_post_cqe(NvmeCtrl *n, NvmeRequest *req)
{
LnvmCtrl *ln = &n->lnvm_ctrl;
NvmeCqe *cqe = &req->cqe;
/* Do post-completion processing depending on the type of command. This is
* used primarily to inject different types of errors.
*/
switch (req->cmd_opcode) {
case LNVM_CMD_HYBRID_WRITE:
case LNVM_CMD_PHYS_WRITE:
lnvm_inject_w_err(ln, req, cqe);
}
}
static void nvme_post_cqe(NvmeCQueue *cq, NvmeRequest *req)
{
NvmeCtrl *n = cq->ctrl;
NvmeSQueue *sq = req->sq;
NvmeCqe *cqe = &req->cqe;
uint8_t phase = cq->phase;
hwaddr addr;
if (cq->phys_contig) {
addr = cq->dma_addr + cq->tail * n->cqe_size;
} else {
addr = nvme_discontig(cq->prp_list, cq->tail, n->page_size,
n->cqe_size);
}
lnvm_post_cqe(n, req);
cqe->status = cpu_to_le16((req->status << 1) | phase);
cqe->sq_id = cpu_to_le16(sq->sqid);
cqe->sq_head = cpu_to_le16(sq->head);
nvme_addr_write(n, addr, (void *)cqe, sizeof(*cqe));
nvme_inc_cq_tail(cq);
QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
}
static void nvme_post_cqes(void *opaque)
{
NvmeCQueue *cq = opaque;
NvmeRequest *req, *next;
QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
if (nvme_cq_full(cq)) {
break;
}
QTAILQ_REMOVE(&cq->req_list, req, entry);
nvme_post_cqe(cq, req);
}
nvme_isr_notify(cq);
}
static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
{
NvmeCtrl *n = cq->ctrl;
uint64_t time_ns = NVME_INTC_TIME(n->features.int_coalescing) * 100 * 1000;
uint8_t thresh = NVME_INTC_THR(n->features.int_coalescing) + 1;
uint8_t coalesce_disabled =
(n->features.int_vector_config[cq->vector] >> 16) & 1;
uint8_t notify;
assert(cq->cqid == req->sq->cqid);
QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
if (nvme_cq_full(cq) || !QTAILQ_EMPTY(&cq->req_list)) {
QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
return;
}
nvme_post_cqe(cq, req);
notify = coalesce_disabled || !req->sq->sqid || !time_ns ||
req->status != NVME_SUCCESS || nvme_cqes_pending(cq) >= thresh;
if (!notify) {
if (!timer_pending(cq->timer)) {
timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
time_ns);
}
} else {
nvme_isr_notify(cq);
if (timer_pending(cq->timer)) {
timer_del(cq->timer);
}
}
}
static void nvme_set_error_page(NvmeCtrl *n, uint16_t sqid, uint16_t cid,
uint16_t status, uint16_t location, uint64_t lba, uint32_t nsid)
{
NvmeErrorLog *elp;
elp = &n->elpes[n->elp_index];
elp->error_count = n->error_count++;
elp->sqid = sqid;
elp->cid = cid;
elp->status_field = status;
elp->param_error_location = location;
elp->lba = lba;
elp->nsid = nsid;
n->elp_index = (n->elp_index + 1) % n->elpe;
++n->num_errors;
}
static void nvme_enqueue_event(NvmeCtrl *n, uint8_t event_type,
uint8_t event_info, uint8_t log_page)
{
NvmeAsyncEvent *event;
if (!(n->bar.csts & NVME_CSTS_READY))
return;
event = (NvmeAsyncEvent *)g_malloc0(sizeof(*event));
event->result.event_type = event_type;
event->result.event_info = event_info;
event->result.log_page = log_page;
QSIMPLEQ_INSERT_TAIL(&(n->aer_queue), event, entry);
timer_mod(n->aer_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
static void nvme_aer_process_cb(void *param)
{
NvmeCtrl *n = param;
NvmeRequest *req;
NvmeAerResult *result;
NvmeAsyncEvent *event, *next;;
QSIMPLEQ_FOREACH_SAFE(event, &n->aer_queue, entry, next) {
if (n->outstanding_aers <= 0) {
break;
}
if (n->aer_mask & (1 << event->result.event_type)) {
continue;
}
QSIMPLEQ_REMOVE_HEAD(&n->aer_queue, entry);
n->aer_mask |= 1 << event->result.event_type;
n->outstanding_aers--;
req = n->aer_reqs[n->outstanding_aers];
result = (NvmeAerResult *)&req->cqe.n.result;
result->event_type = event->result.event_type;
result->event_info = event->result.event_info;
result->log_page = event->result.log_page;
g_free(event);
req->status = NVME_SUCCESS;
nvme_enqueue_req_completion(n->cq[0], req);
}
}
//read write block completion function
static void nvme_rw_cb(void *opaque, int ret)
{
NvmeRequest *req = opaque;
NvmeSQueue *sq = req->sq;
NvmeCtrl *n = sq->ctrl;
NvmeCQueue *cq = n->cq[sq->cqid];
NvmeNamespace *ns = req->ns;
block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
if (!ret) {
req->status = NVME_SUCCESS;
} else {
req->status = NVME_INTERNAL_DEV_ERROR;
}
if (req->status != NVME_SUCCESS) {
nvme_set_error_page(n, sq->sqid, req->cqe.cid, req->status,
offsetof(NvmeRwCmd, slba), req->slba, ns->id);
if (req->is_write) {
bitmap_clear(ns->util, req->slba, req->nlb);
}
} else {
if (lnvm_dev(n)) {
if (lnvm_hybrid_dev(n) && req->is_write) {
if (req->nlb > 1) {
/* NOTE: This causes segfault with rpc
int i;
for (i = 0; i < req->nlb; i++)
ns->tbl[req->lnvm_slba + i] =
req->lnvm_ppa_list[i];
*/
} else {
ns->tbl[req->lnvm_slba] = req->slba;
}
}
/* TODO: Check this on spec 2.0 format */
if (!lnvm_hybrid_dev(n) && req->lnvm_ppa_list)
g_free(req->lnvm_ppa_list);
}
}
if (req->qsg.nsg) {
qemu_sglist_destroy(&req->qsg);
} else {
qemu_iovec_destroy(&req->iov);
}
nvme_enqueue_req_completion(cq, req);
}
static uint16_t nvme_rw_check_req(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
NvmeRequest *req, uint64_t slba, uint64_t elba, uint32_t nlb, uint16_t ctrl,
uint64_t data_size, uint64_t meta_size)
{
if (elba > le64_to_cpu(ns->id_ns.nsze)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(NvmeRwCmd, nlb), elba, ns->id);
return NVME_LBA_RANGE | NVME_DNR;
}
if (n->id_ctrl.mdts && data_size > n->page_size * (1 << n->id_ctrl.mdts)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, nlb), nlb, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
if (meta_size) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, control), ctrl, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
if ((ctrl & NVME_RW_PRINFO_PRACT) && !(ns->id_ns.dps & DPS_TYPE_MASK)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, control), ctrl, ns->id);
/* Not contemplated in LightNVM for now */
if (lnvm_dev(n))
return 0;
return NVME_INVALID_FIELD | NVME_DNR;
}
if (!req->is_write && find_next_bit(ns->uncorrectable, elba, slba) < elba) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_UNRECOVERED_READ,
offsetof(NvmeRwCmd, slba), elba, ns->id);
return NVME_UNRECOVERED_READ;
}
return 0;
}
static void print_ppa(LnvmCtrl *ln, uint64_t ppa)
{
uint64_t ch = (ppa & ln->ppaf.ch_mask) >> ln->ppaf.ch_offset;
uint64_t lun = (ppa & ln->ppaf.lun_mask) >> ln->ppaf.lun_offset;
uint64_t blk = (ppa & ln->ppaf.blk_mask) >> ln->ppaf.blk_offset;
uint64_t pg = (ppa & ln->ppaf.pg_mask) >> ln->ppaf.pg_offset;
uint64_t pln = (ppa & ln->ppaf.pln_mask) >> ln->ppaf.pln_offset;
uint64_t sec = (ppa & ln->ppaf.sec_mask) >> ln->ppaf.sec_offset;
printf("ppa: ch(%lu), lun(%lu), blk(%lu), pg(%lu), pl(%lu), sec(%lu)\n",
ch, lun, blk, pg, pln, sec);
}
struct lnvm_metadata_format {
uint32_t state;
uint64_t rsv[2];
} __attribute__((__packed__));
struct lnvm_tgt_meta {
uint64_t lba;
uint64_t rsvd;
} __attribute__((__packed__));
/**
*/
/**
* Write a single out-of-bound area entry
*
* NOTE: Ensure that `lnvm_set_written_state` has been called prior to this
* function to ensure correct file offset of ln->metadata?
*/
static inline int lnvm_meta_write(LnvmCtrl *ln, void *meta)
{
FILE *meta_fp = ln->metadata;
size_t tgt_oob_len = ln->params.sos;
size_t ret;
ret = fwrite(meta, tgt_oob_len, 1, meta_fp);
if (ret != 1) {
perror("lnvm_meta_write: fwrite");
return -1;
}
if (fflush(meta_fp)) {
perror("lnvm_meta_write: fflush");
return -1;
}
return 0;
}
/**
* Read a single out-of-bound area entry
*
* NOTE: Ensure that `lnvm_meta_state_get` has been called to have the correct
* file offset in ln->metadata?
*/
static inline int lnvm_meta_read(LnvmCtrl *ln, void *meta)
{
FILE *meta_fp = ln->metadata;
size_t tgt_oob_len = ln->params.sos;
size_t ret;
ret = fread(meta, tgt_oob_len, 1, meta_fp);
if (ret != 1) {
if (errno == EAGAIN)
return 0;
perror("lnvm_meta_read: fread");
return -1;
}
return 0;
}
static inline int64_t lnvm_bbt_pos_get(LnvmCtrl *ln, uint64_t r)
{
LnvmIdGroup *c = &ln->id_ctrl.groups[0];
uint64_t lun = (r & ln->ppaf.lun_mask) >> ln->ppaf.lun_offset;
uint64_t blk = (r & ln->ppaf.blk_mask) >> ln->ppaf.blk_offset;
uint64_t pln = (r & ln->ppaf.pln_mask) >> ln->ppaf.pln_offset;
uint64_t lun_off = lun * c->num_blk * c->num_pln;
uint64_t blk_off = blk * c->num_pln;
return pln + blk_off + lun_off;
}
static inline int64_t lnvm_ppa_to_off(LnvmCtrl *ln, uint64_t r)
{
uint64_t ch = (r & ln->ppaf.ch_mask) >> ln->ppaf.ch_offset;
uint64_t lun = (r & ln->ppaf.lun_mask) >> ln->ppaf.lun_offset;
uint64_t pln = (r & ln->ppaf.pln_mask) >> ln->ppaf.pln_offset;
uint64_t blk = (r & ln->ppaf.blk_mask) >> ln->ppaf.blk_offset;
uint64_t pg = (r & ln->ppaf.pg_mask) >> ln->ppaf.pg_offset;
uint64_t sec = (r & ln->ppaf.sec_mask) >> ln->ppaf.sec_offset;
uint64_t off = sec;
off += pln * ln->params.pl_units;
off += pg * ln->params.pg_units;
off += blk * ln->params.blk_units;
off += lun * ln->params.lun_units;
if (off > ln->params.total_units) {
printf("lnvm: ppa OOB:ch:%lu,lun:%lu,blk:%lu,pg:%lu,pl:%lu,sec:%lu\n",
ch, lun, blk, pg, pln, sec);
return -1;
}
return off;
}
static inline int lnvm_meta_state_get(LnvmCtrl *ln, uint64_t ppa,
uint32_t *state)
{
FILE *meta_fp = ln->metadata;
size_t tgt_oob_len = ln->params.sos;
size_t int_oob_len = ln->int_meta_size;
size_t meta_len = tgt_oob_len + int_oob_len;
uint32_t seek = ppa * meta_len;
size_t ret;
if (fseek(meta_fp, seek, SEEK_SET)) {
perror("lnvm_meta_state_get: fseek");
printf("Could not seek to offset in metadata file\n");
return -1;
}
ret = fread(state, int_oob_len, 1, meta_fp);
if (ret != 1) {
if (errno == EAGAIN) {
//printf("lnvm_meta_state_get: Why is this not an error?\n");
return 0;
}
perror("lnvm_meta_state_get: fread");
printf("lnvm_meta_state_get: ppa(%lu), ret(%lu)\n", ppa, ret);
return -1;
}
return 0;
}
/**
* Similar to lnvm_meta_set_written, however, this function sets not a single
* but multiple ppas, also checks if a block is marked bad
*/
static inline int lnvm_meta_blk_set_erased(NvmeNamespace *ns, LnvmCtrl *ln,
uint64_t *psl, int nr_ppas, int pmode)
{
struct lnvm_metadata_format meta = {.state = LNVM_SEC_ERASED};
LnvmIdGroup *c = &ln->id_ctrl.groups[0];
FILE *meta_fp = ln->metadata;
size_t tgt_oob_len = ln->params.sos;
size_t int_oob_len = ln->int_meta_size;
size_t meta_len = tgt_oob_len + int_oob_len;
int i;
uint64_t mask = 0;
if (ln->strict && nr_ppas != 1) {
printf("_erase_meta: Erase command unfolds on device\n");
return NVME_INVALID_FIELD | NVME_DNR;
}
switch(pmode) { // Check that pmode is supported
case LNVM_PMODE_DUAL:
if (c->num_pln != 2) {
printf("_erase_meta: Unsupported pmode(%d) for num_pln(%d)\n",
pmode, c->num_pln);
return -1;
}
break;
case LNVM_PMODE_QUAD:
if (c->num_pln != 4) {
printf("_erase_meta: Unsupported pmode(%d) for num_pln(%d)\n",
pmode, c->num_pln);
return -1;
}
break;
case LNVM_PMODE_SNGL:
break;
default:
printf("_erase_meta: Unsupported pmode(%d)\n", pmode);
}
mask |= ln->ppaf.ch_mask; // Construct mask
mask |= ln->ppaf.lun_mask;
mask |= ln->ppaf.blk_mask;
for (i = 0; i < nr_ppas; ++i) {
uint64_t ppa = psl[i];
size_t pl_bgn, pl_end;
size_t pl;
if (pmode) {
pl_bgn = 0;
pl_end = c->num_pln - 1;
} else {
pl_bgn = (ppa & ln->ppaf.pln_mask) >> ln->ppaf.pln_offset;
pl_end = pl_bgn;
}
for (pl = pl_bgn; pl <= pl_end; ++pl) {
uint32_t cur_state = 0;
uint64_t ppa_pl;
size_t pg, sec;
ppa_pl = ppa & mask;
ppa_pl |= pl << ln->ppaf.pln_offset;
// Check bad-block-table to error on bad blocks
if (ns->bbtbl[lnvm_bbt_pos_get(ln, ppa_pl)]) {
printf("_erase_meta: failed -- block is bad\n");
return -1;
}
// Check state of first sector to error on double-erase
if (lnvm_meta_state_get(ln, ppa_pl, &cur_state)) {
printf("_erase_meta: failed: reading current state\n");
return -1;
}
if (cur_state == LNVM_SEC_ERASED) {
printf("_erase_meta: failed -- already erased\n");
}
for (pg = 0; pg < ln->params.pgs_per_blk; ++pg) {
for (sec = 0; sec < ln->params.sec_per_pg; ++sec) {
uint64_t ppa_sec, off;
ppa_sec = ppa & mask;
ppa_sec |= pg << ln->ppaf.pg_offset;
ppa_sec |= pl << ln->ppaf.pln_offset;
ppa_sec |= sec << ln->ppaf.sec_offset;
off = lnvm_ppa_to_off(ln, ppa_sec);
if (fseek(meta_fp, off * meta_len, SEEK_SET)) {
perror("_set_erased: fseek");
return -1;
}
if (fwrite(&meta, meta_len, 1, meta_fp) != 1) {
perror("_erase_meta: fwrite");
printf("_erase_meta: ppa(%016lx), off(%lu)\n", ppa_sec,
off);
}
}
}
}
}
if (fflush(meta_fp)) {
perror("_erase_meta: fflush");
return -1;
}
return 0;
}
static inline int lnvm_meta_state_set_written(LnvmCtrl *ln, uint64_t ppa)
{
FILE *meta_fp = ln->metadata;
size_t tgt_oob_len = ln->params.sos;
size_t int_oob_len = ln->int_meta_size;
size_t meta_len = tgt_oob_len + int_oob_len;
uint32_t seek = ppa * meta_len;
uint32_t state;
size_t ret;
if (lnvm_meta_state_get(ln, ppa, &state)) {
printf("_set_written: lnvm_meta_state_get failed\n");
return -1;
}
if (state != LNVM_SEC_ERASED) {
printf("_set_written: Invalid block state(%02x)\n", state);
return -1;
}
if (fseek(meta_fp, seek, SEEK_SET)) {
perror("_set_written: fseek");
return -1;
}
state = LNVM_SEC_WRITTEN;